From: "Jiang, Haochen" <haochen.jiang@intel.com>
To: "Beulich, Jan" <JBeulich@suse.com>, "H.J. Lu" <hjl.tools@gmail.com>
Cc: Binutils <binutils@sourceware.org>
Subject: RE: [PATCH 5/5] x86: support AVX10.1 vector size restrictions
Date: Fri, 1 Sep 2023 06:21:37 +0000 [thread overview]
Message-ID: <SA1PR11MB59463D4D371779A6DA8383FAECE4A@SA1PR11MB5946.namprd11.prod.outlook.com> (raw)
In-Reply-To: <b86e5aa6-27e5-749d-d9c8-657fd198ede3@suse.com>
> >>
> >> AVX10 spec only has
> >>
> >> Quadword opmask instructions will only be supported on processors
> >> supporting vector lengths of 512 bits.
> >>
> >> It doesn't say anything about 32-bit mask. 32-bit mask can be useful
> >> even with 16 byte vector.
>
> How's that any different for 64-bit mask with 32-byte vector?
>
> > The concern form my side is if there is an extreme case that overloads
> > registers, we might need to spill 32-bit register to 32-bit mask
> > register in the compiler.
>
> How's that any different for spilling of 64-bit registers?
>
In GCC, under 256 bit mode, we will ban them. But since there is no definition
for 128 bit mode in GCC for a long time, it will leave some space of undefined.
Actually, the cost for that spill is really high. So it should be little concern, not a
blocking issue.
Thx,
Haochen
prev parent reply other threads:[~2023-09-01 6:21 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-25 12:43 [PATCH 0/5] x86: AVX10.1 (alternative attempt) Jan Beulich
2023-08-25 12:44 ` [PATCH 1/5] x86: correct source used for two non-AVX512 VEXWIG tests Jan Beulich
2023-08-25 12:45 ` [PATCH 2/5] x86: rename CpuPCLMUL Jan Beulich
2023-08-25 12:46 ` [PATCH 3/5] x86: support AVX10.1/512 Jan Beulich
2023-08-28 2:34 ` Jiang, Haochen
2023-08-28 6:45 ` Jan Beulich
2023-08-28 6:59 ` Jiang, Haochen
2023-08-28 7:09 ` Jan Beulich
2023-08-29 16:18 ` H.J. Lu
2023-08-30 1:10 ` Jiang, Haochen
2023-08-30 7:47 ` Jan Beulich
2023-08-30 15:28 ` H.J. Lu
2023-09-01 8:41 ` Jan Beulich
2023-09-01 8:52 ` Jiang, Haochen
2023-09-01 9:57 ` Jan Beulich
2023-09-05 7:04 ` Jiang, Haochen
2023-09-05 7:25 ` Jan Beulich
2023-08-25 12:47 ` [PATCH 4/5] x86: unindent most of set_cpu_arch() Jan Beulich
2023-08-25 12:47 ` [PATCH 5/5] x86: support AVX10.1 vector size restrictions Jan Beulich
2023-08-29 16:26 ` H.J. Lu
2023-08-30 7:57 ` Jan Beulich
2023-08-30 15:25 ` H.J. Lu
2023-08-30 16:16 ` Jan Beulich
2023-08-30 18:00 ` H.J. Lu
2023-08-31 5:56 ` Jiang, Haochen
2023-08-31 7:18 ` Jan Beulich
2023-09-01 6:21 ` Jiang, Haochen [this message]
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