From: "H.J. Lu" <hjl.tools@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Binutils <binutils@sourceware.org>,
"Jiang, Haochen" <haochen.jiang@intel.com>
Subject: Re: [PATCH 5/5] x86: support AVX10.1 vector size restrictions
Date: Wed, 30 Aug 2023 08:25:01 -0700 [thread overview]
Message-ID: <CAMe9rOrqPnNxd2451Z4zz4FWjoBfV4HrcdGtXKxdXM=76UMpEA@mail.gmail.com> (raw)
In-Reply-To: <1b1b6e37-9484-95d8-d63d-c586a064729f@suse.com>
On Wed, Aug 30, 2023 at 12:57 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 29.08.2023 18:26, H.J. Lu wrote:
> > On Fri, Aug 25, 2023 at 5:48 AM Jan Beulich <jbeulich@suse.com> wrote:
> >> @@ -1673,6 +1680,12 @@ an unconditional jump to the target.
> >>
> >> Note that the sub-architecture specifiers (starting with a dot) can be prefixed
> >> with @code{no} to revoke the respective (and any dependent) functionality.
> >> +Note further that @samp{.avx10.<N>} can be suffixed with a vector length
> >> +restriction (@samp{/256} or @samp{/128}, with @samp{/512} simply restoring the
> >> +default). Despite these otherwise being "enabling" specifiers, using these
> >> +suffixes will disable all insns with wider vector or mask register operands.
> >> +On SVR4-derived platforms, the separator character @samp{/} can be replaced by
> >> +@samp{:}.
> >>
> >> Following the CPU architecture (but not a sub-architecture, which are those
> >> starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
> >
> > Although CPUID bits in AVX10 spec may leave an impression that 128-bit,
> > 256-bit and 512-bit vectors may be enabled independently. But it also says
> >
> > A “converged” version of Intel AVX10 with maximum vector lengths of 256
> > bits and 32-bit opmask registers will be supported across all Intel processors,
> > while 512-bit vector registers and 64-bit opmasks will continue to be supported
> > on some P-core processors.
> >
> > Adding avx10.1/128 isn't necessary.
>
> I agree it isn't necessary, but as expressed before I view it as desirable.
> Apart from the sentence you quoted the spec later also says "There are
> currently no plans to support an Intel AVX10/128 implementation." For my
> choice of also supporting the 128-bit restriction I'd like to put emphasis
> on "currently". I think I said before that emulation environments (qemu,
> sde to name just two well-known examples) are free to implement such
> further restricted ISAs without then becoming out-of-spec.
>
> Plus supporting this mode right away has made me make certain adjustments
> in what I'd call more clean a way, which I view as desirable as well.
>
Since AVX10 spec doesn't specify if mask registers should be limited to
16 bits for AVX10/128, doing it in assembler is premature.
--
H.J.
next prev parent reply other threads:[~2023-08-30 15:25 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-25 12:43 [PATCH 0/5] x86: AVX10.1 (alternative attempt) Jan Beulich
2023-08-25 12:44 ` [PATCH 1/5] x86: correct source used for two non-AVX512 VEXWIG tests Jan Beulich
2023-08-25 12:45 ` [PATCH 2/5] x86: rename CpuPCLMUL Jan Beulich
2023-08-25 12:46 ` [PATCH 3/5] x86: support AVX10.1/512 Jan Beulich
2023-08-28 2:34 ` Jiang, Haochen
2023-08-28 6:45 ` Jan Beulich
2023-08-28 6:59 ` Jiang, Haochen
2023-08-28 7:09 ` Jan Beulich
2023-08-29 16:18 ` H.J. Lu
2023-08-30 1:10 ` Jiang, Haochen
2023-08-30 7:47 ` Jan Beulich
2023-08-30 15:28 ` H.J. Lu
2023-09-01 8:41 ` Jan Beulich
2023-09-01 8:52 ` Jiang, Haochen
2023-09-01 9:57 ` Jan Beulich
2023-09-05 7:04 ` Jiang, Haochen
2023-09-05 7:25 ` Jan Beulich
2023-08-25 12:47 ` [PATCH 4/5] x86: unindent most of set_cpu_arch() Jan Beulich
2023-08-25 12:47 ` [PATCH 5/5] x86: support AVX10.1 vector size restrictions Jan Beulich
2023-08-29 16:26 ` H.J. Lu
2023-08-30 7:57 ` Jan Beulich
2023-08-30 15:25 ` H.J. Lu [this message]
2023-08-30 16:16 ` Jan Beulich
2023-08-30 18:00 ` H.J. Lu
2023-08-31 5:56 ` Jiang, Haochen
2023-08-31 7:18 ` Jan Beulich
2023-09-01 6:21 ` Jiang, Haochen
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