From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: binutils@sourceware.org
Subject: [PATCH 5/5] RISC-V: Fix RV64_Zqinx to use register pairs
Date: Tue, 1 Feb 2022 22:49:06 +0900 [thread overview]
Message-ID: <5a15b23e892bebb106433548fb3e3494281b7e4a.1643723292.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1643723292.git.research_trasio@irq.a4lg.com>
This commit ensures that all FP128 register numbers to be even because
RV64_Zqinx would require it.
gas/ChangeLog:
* testsuite/gas/riscv/zqinx.s: Make register numbers even.
* testsuite/gas/riscv/zqinx.d: Likewise.
---
gas/testsuite/gas/riscv/zqinx.d | 70 ++++++++++++++++-----------------
gas/testsuite/gas/riscv/zqinx.s | 70 ++++++++++++++++-----------------
2 files changed, 70 insertions(+), 70 deletions(-)
diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d
index c704241bc90..52b5445d010 100644
--- a/gas/testsuite/gas/riscv/zqinx.d
+++ b/gas/testsuite/gas/riscv/zqinx.d
@@ -7,38 +7,38 @@
Disassembly of section .text:
0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+06c5f553[ ]+fadd.q[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+0ec5f553[ ]+fsub.q[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+16c5f553[ ]+fmul.q[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+1ec5f553[ ]+fdiv.q[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+5e05f553[ ]+fsqrt.q[ ]+a0,a1
-[ ]+[0-9a-f]+:[ ]+2ec58553[ ]+fmin.q[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+2ec59553[ ]+fmax.q[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+6ec5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3
-[ ]+[0-9a-f]+:[ ]+6ec5f54f[ ]+fnmadd.q[ ]+a0,a1,a2,a3
-[ ]+[0-9a-f]+:[ ]+6ec5f547[ ]+fmsub.q[ ]+a0,a1,a2,a3
-[ ]+[0-9a-f]+:[ ]+6ec5f54b[ ]+fnmsub.q[ ]+a0,a1,a2,a3
-[ ]+[0-9a-f]+:[ ]+c605f553[ ]+fcvt.w.q[ ]+a0,a1
-[ ]+[0-9a-f]+:[ ]+c615f553[ ]+fcvt.wu.q[ ]+a0,a1
-[ ]+[0-9a-f]+:[ ]+c625f553[ ]+fcvt.l.q[ ]+a0,a1
-[ ]+[0-9a-f]+:[ ]+c635f553[ ]+fcvt.lu.q[ ]+a0,a1
-[ ]+[0-9a-f]+:[ ]+4035f553[ ]+fcvt.s.q[ ]+a0,a1
-[ ]+[0-9a-f]+:[ ]+4235f553[ ]+fcvt.d.q[ ]+a0,a1
-[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1
-[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1
-[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1
-[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1
-[ ]+[0-9a-f]+:[ ]+d625f553[ ]+fcvt.q.l[ ]+a0,a1
-[ ]+[0-9a-f]+:[ ]+d635f553[ ]+fcvt.q.lu[ ]+a0,a1
-[ ]+[0-9a-f]+:[ ]+26c58553[ ]+fsgnj.q[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+26c59553[ ]+fsgnjn.q[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+26c5a553[ ]+fsgnjx.q[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+a6c5a553[ ]+feq.q[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+a6c59553[ ]+flt.q[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1
-[ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1
-[ ]+[0-9a-f]+:[ ]+26b58553[ ]+fmv.q[ ]+a0,a1
-[ ]+[0-9a-f]+:[ ]+26b59553[ ]+fneg.q[ ]+a0,a1
-[ ]+[0-9a-f]+:[ ]+26b5a553[ ]+fabs.q[ ]+a0,a1
-[ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4
+[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4
+[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4
+[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4
+[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2
+[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4
+[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4
+[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6
+[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6
+[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6
+[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6
+[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2
+[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2
+[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2
+[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2
+[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2
+[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2
+[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2
+[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2
+[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2
+[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2
+[ ]+[0-9a-f]+:[ ]+d6267553[ ]+fcvt.q.l[ ]+a0,a2
+[ ]+[0-9a-f]+:[ ]+d6367553[ ]+fcvt.q.lu[ ]+a0,a2
+[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4
+[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4
+[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4
+[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4
+[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4
+[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4
+[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2
+[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2
+[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2
+[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2
+[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2
+[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2
diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s
index 02147b1919c..2dc2a7c1483 100644
--- a/gas/testsuite/gas/riscv/zqinx.s
+++ b/gas/testsuite/gas/riscv/zqinx.s
@@ -1,36 +1,36 @@
target:
- fadd.q a0, a1, a2
- fsub.q a0, a1, a2
- fmul.q a0, a1, a2
- fdiv.q a0, a1, a2
- fsqrt.q a0, a1
- fmin.q a0, a1, a2
- fmax.q a0, a1, a2
- fmadd.q a0, a1, a2, a3
- fnmadd.q a0, a1, a2, a3
- fmsub.q a0, a1, a2, a3
- fnmsub.q a0, a1, a2, a3
- fcvt.w.q a0, a1
- fcvt.wu.q a0, a1
- fcvt.l.q a0, a1
- fcvt.lu.q a0, a1
- fcvt.s.q a0, a1
- fcvt.d.q a0, a1
- fcvt.q.s a0, a1
- fcvt.q.d a0, a1
- fcvt.q.w a0, a1
- fcvt.q.wu a0, a1
- fcvt.q.l a0, a1
- fcvt.q.lu a0, a1
- fsgnj.q a0, a1, a2
- fsgnjn.q a0, a1, a2
- fsgnjx.q a0, a1, a2
- feq.q a0, a1, a2
- flt.q a0, a1, a2
- fle.q a0, a1, a2
- fgt.q a0, a1, a2
- fge.q a0, a1, a2
- fmv.q a0, a1
- fneg.q a0, a1
- fabs.q a0, a1
- fclass.q a0, a1
+ fadd.q a0, a2, a4
+ fsub.q a0, a2, a4
+ fmul.q a0, a2, a4
+ fdiv.q a0, a2, a4
+ fsqrt.q a0, a2
+ fmin.q a0, a2, a4
+ fmax.q a0, a2, a4
+ fmadd.q a0, a2, a4, a6
+ fnmadd.q a0, a2, a4, a6
+ fmsub.q a0, a2, a4, a6
+ fnmsub.q a0, a2, a4, a6
+ fcvt.w.q a0, a2
+ fcvt.wu.q a0, a2
+ fcvt.l.q a0, a2
+ fcvt.lu.q a0, a2
+ fcvt.s.q a0, a2
+ fcvt.d.q a0, a2
+ fcvt.q.s a0, a2
+ fcvt.q.d a0, a2
+ fcvt.q.w a0, a2
+ fcvt.q.wu a0, a2
+ fcvt.q.l a0, a2
+ fcvt.q.lu a0, a2
+ fsgnj.q a0, a2, a4
+ fsgnjn.q a0, a2, a4
+ fsgnjx.q a0, a2, a4
+ feq.q a0, a2, a4
+ flt.q a0, a2, a4
+ fle.q a0, a2, a4
+ fgt.q a0, a2, a4
+ fge.q a0, a2, a4
+ fmv.q a0, a2
+ fneg.q a0, a2
+ fabs.q a0, a2
+ fclass.q a0, a2
--
2.32.0
next prev parent reply other threads:[~2022-02-01 13:50 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-01 13:49 [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1 Tsukasa OI
2022-02-01 13:49 ` [PATCH 1/5] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 2/5] RISC-V: Make indentation consistent Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 3/5] RISC-V: Use different registers for testing Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 4/5] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-08 9:51 ` Tsukasa OI
2022-02-01 13:49 ` Tsukasa OI [this message]
2022-02-08 2:00 ` [PATCH 5/5] RISC-V: Fix RV64_Zqinx to use register pairs Palmer Dabbelt
2022-02-01 13:51 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Tsukasa OI
2022-02-01 13:51 ` [RFC PATCH 1/2] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI
2022-02-01 13:51 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-02-08 2:00 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Palmer Dabbelt
2022-02-01 13:52 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2B Tsukasa OI
2022-02-01 13:52 ` [RFC PATCH 1/2] RISC-V: Add floating point instruction metadata Tsukasa OI
2022-02-01 13:52 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-02-01 13:53 ` [PATCH 0/4] RISC-V: Zfinx fixes/enhancements: Part 3 Tsukasa OI
2022-02-01 13:53 ` [PATCH 1/4] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 2/4] RISC-V: Add disassembler tests " Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 3/4] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI
2022-02-08 2:01 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 4/4] RISC-V: Add disassembler tests " Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 01/11] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 02/11] RISC-V: Make indentation consistent Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 03/11] RISC-V: Use different registers for testing Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 04/11] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 05/11] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 06/11] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 07/11] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 08/11] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 09/11] RISC-V: Add disassembler tests " Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 10/11] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI
2022-05-22 5:16 ` [PATCH v2 11/11] RISC-V: Add disassembler tests " Tsukasa OI
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