From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: binutils@sourceware.org
Subject: [PATCH 4/4] RISC-V: Add disassembler tests for Zqinx regs
Date: Tue, 1 Feb 2022 22:53:38 +0900 [thread overview]
Message-ID: <d734211a9233b86605e18f1e0127c40059de3ce4.1643723585.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1643723585.git.research_trasio@irq.a4lg.com>
This commid adds disassembler tests for invalid Zqinx register numbers
(make sure that we don't disassemble invalid encodings).
gas/ChangeLog:
* testsuite/gas/riscv/zqinx-32-regpair-dis.s: New test to make
sure that invalid encodings are not disassembled.
* testsuite/gas/riscv/zqinx-32-regpair-dis.d: Likewise.
* testsuite/gas/riscv/zqinx-64-regpair-dis.s: New test to make
sure that invalid encoding is not disassembled.
* testsuite/gas/riscv/zqinx-64-regpair-dis.d: Likewise.
---
gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s | 7 +++++++
gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d | 11 +++++++++++
gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s | 5 +++++
4 files changed, 35 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s
diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d
new file mode 100644
index 00000000000..5af92477116
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d
@@ -0,0 +1,12 @@
+#as: -march=rv32ima_zqinx
+#source: zqinx-32-regpair-dis.s
+#objdump: -dr -Mnumeric
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+06c47253[ ]+fadd.q[ ]+x4,x8,x12
+[ ]+[0-9a-f]+:[ ]+06d4f2d3[ ]+\.4byte[ ]+0x6d4f2d3
+[ ]+[0-9a-f]+:[ ]+06e57353[ ]+\.4byte[ ]+0x6e57353
diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s
new file mode 100644
index 00000000000..e11e671ecdc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s
@@ -0,0 +1,7 @@
+target:
+ # fadd.q x4, x8, x12
+ .insn 0x06c47253
+ # fadd.q x5, x9, x13 (invalid)
+ .insn 0x06d4f2d3
+ # fadd.q x6, x10, x14 (invalid)
+ .insn 0x06e57353
diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d
new file mode 100644
index 00000000000..894ed34948e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d
@@ -0,0 +1,11 @@
+#as: -march=rv64ima_zqinx
+#source: zqinx-64-regpair-dis.s
+#objdump: -dr -Mnumeric
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+06627153[ ]+fadd.q[ ]+x2,x4,x6
+[ ]+[0-9a-f]+:[ ]+0672f1d3[ ]+\.4byte[ ]+0x672f1d3
diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s
new file mode 100644
index 00000000000..9edeae84ba7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s
@@ -0,0 +1,5 @@
+target:
+ # fadd.q x2, x4, x6
+ .insn 0x06627153
+ # fadd.q x3, x5, x7 (invalid)
+ .insn 0x0672f1d3
--
2.32.0
next prev parent reply other threads:[~2022-02-01 13:54 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-01 13:49 [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1 Tsukasa OI
2022-02-01 13:49 ` [PATCH 1/5] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 2/5] RISC-V: Make indentation consistent Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 3/5] RISC-V: Use different registers for testing Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 4/5] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-08 9:51 ` Tsukasa OI
2022-02-01 13:49 ` [PATCH 5/5] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:51 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Tsukasa OI
2022-02-01 13:51 ` [RFC PATCH 1/2] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI
2022-02-01 13:51 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-02-08 2:00 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Palmer Dabbelt
2022-02-01 13:52 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2B Tsukasa OI
2022-02-01 13:52 ` [RFC PATCH 1/2] RISC-V: Add floating point instruction metadata Tsukasa OI
2022-02-01 13:52 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-02-01 13:53 ` [PATCH 0/4] RISC-V: Zfinx fixes/enhancements: Part 3 Tsukasa OI
2022-02-01 13:53 ` [PATCH 1/4] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 2/4] RISC-V: Add disassembler tests " Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 3/4] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI
2022-02-08 2:01 ` Palmer Dabbelt
2022-02-01 13:53 ` Tsukasa OI [this message]
2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 01/11] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 02/11] RISC-V: Make indentation consistent Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 03/11] RISC-V: Use different registers for testing Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 04/11] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 05/11] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 06/11] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 07/11] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 08/11] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 09/11] RISC-V: Add disassembler tests " Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 10/11] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI
2022-05-22 5:16 ` [PATCH v2 11/11] RISC-V: Add disassembler tests " Tsukasa OI
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