From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: binutils@sourceware.org
Subject: [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs
Date: Tue, 1 Feb 2022 22:52:45 +0900 [thread overview]
Message-ID: <77833bfe4b6f33b6fc35ee7d248e857fe9dca027.1643723532.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1643723532.git.research_trasio@irq.a4lg.com>
This commit adds floating point register validation on Zdinx/Zqinx
extensions enabled. Assembler only.
gas/ChangeLog:
* config/tc-riscv.c (reg_lookup_fp): New function to look up and
validate floating point register operands.
(riscv_ip): Use `reg_lookup_fp' to look up FPRs.
---
gas/config/tc-riscv.c | 65 +++++++++++++++++++++++++++++++++++++++----
1 file changed, 59 insertions(+), 6 deletions(-)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 25908597436..bfb2f94b061 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2137,6 +2137,61 @@ riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
return false;
}
+/* Look up floating point register and validate against operand type.
+ This function checks invalid register such as "x1" on a FP64 operand
+ in RV32_Zdinx. */
+
+static bool
+reg_lookup_fp (char operand, char **str,
+ struct riscv_opcode *insn, unsigned int *regno)
+{
+ bool is_zfinx = riscv_subset_supports (&riscv_rps_as, "zfinx");
+ unsigned int float_size = insn->pinfo & INSN_FLOAT;
+ if (!reg_lookup (str, (is_zfinx ? RCLASS_GPR : RCLASS_FPR), regno))
+ return false;
+ if (!is_zfinx || (insn->pinfo & INSN_FLOAT_VAR))
+ return true;
+ /* Source operand for fcvt.[FLOAT].[FLOAT] instructions requires
+ different float_size than the destination. */
+ if ((insn->pinfo & INSN_FCVT_F_F) && operand == 'S')
+ float_size = (insn->pinfo & INSN_FCVT_SRC) >> INSN_FCVT_SRC_SHIFT;
+ /* Check register index for Zdinx/Zqinx. */
+ switch (float_size)
+ {
+ case INSN_FLOAT_S:
+ return true;
+ case INSN_FLOAT_D:
+ switch (xlen)
+ {
+ case 32:
+ if (*regno & 0x01)
+ break;
+ return true;
+ default:
+ return true;
+ }
+ break;
+ case INSN_FLOAT_Q:
+ switch (xlen)
+ {
+ case 32:
+ if (*regno & 0x03)
+ break;
+ return true;
+ case 64:
+ if (*regno & 0x01)
+ break;
+ return true;
+ default:
+ return true;
+ }
+ break;
+ default:
+ return false;
+ }
+ return false;
+}
+
/* All RISC-V CSR instructions belong to one of these classes. */
enum csr_insn_type
{
@@ -2518,19 +2573,19 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
case 'a':
goto jump;
case 'S': /* Floating-point RS1 x8-x15. */
- if (!reg_lookup (&asarg, RCLASS_FPR, ®no)
+ if (!reg_lookup_fp(*oparg, &asarg, insn, ®no)
|| !(regno >= 8 && regno <= 15))
break;
INSERT_OPERAND (CRS1S, *ip, regno % 8);
continue;
case 'D': /* Floating-point RS2 x8-x15. */
- if (!reg_lookup (&asarg, RCLASS_FPR, ®no)
+ if (!reg_lookup_fp(*oparg, &asarg, insn, ®no)
|| !(regno >= 8 && regno <= 15))
break;
INSERT_OPERAND (CRS2S, *ip, regno % 8);
continue;
case 'T': /* Floating-point RS2. */
- if (!reg_lookup (&asarg, RCLASS_FPR, ®no))
+ if (!reg_lookup_fp(*oparg, &asarg, insn, ®no))
break;
INSERT_OPERAND (CRS2, *ip, regno);
continue;
@@ -2897,9 +2952,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
case 'T': /* Floating point RS2. */
case 'U': /* Floating point RS1 and RS2. */
case 'R': /* Floating point RS3. */
- if (reg_lookup (&asarg,
- (riscv_subset_supports (&riscv_rps_as, "zfinx")
- ? RCLASS_GPR : RCLASS_FPR), ®no))
+ if (reg_lookup_fp(*oparg, &asarg, insn, ®no))
{
char c = *oparg;
if (*asarg == ' ')
--
2.32.0
next prev parent reply other threads:[~2022-02-01 13:52 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-01 13:49 [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1 Tsukasa OI
2022-02-01 13:49 ` [PATCH 1/5] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 2/5] RISC-V: Make indentation consistent Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 3/5] RISC-V: Use different registers for testing Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 4/5] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-08 9:51 ` Tsukasa OI
2022-02-01 13:49 ` [PATCH 5/5] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:51 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Tsukasa OI
2022-02-01 13:51 ` [RFC PATCH 1/2] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI
2022-02-01 13:51 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-02-08 2:00 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Palmer Dabbelt
2022-02-01 13:52 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2B Tsukasa OI
2022-02-01 13:52 ` [RFC PATCH 1/2] RISC-V: Add floating point instruction metadata Tsukasa OI
2022-02-01 13:52 ` Tsukasa OI [this message]
2022-02-01 13:53 ` [PATCH 0/4] RISC-V: Zfinx fixes/enhancements: Part 3 Tsukasa OI
2022-02-01 13:53 ` [PATCH 1/4] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 2/4] RISC-V: Add disassembler tests " Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 3/4] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI
2022-02-08 2:01 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 4/4] RISC-V: Add disassembler tests " Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 01/11] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 02/11] RISC-V: Make indentation consistent Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 03/11] RISC-V: Use different registers for testing Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 04/11] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 05/11] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 06/11] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 07/11] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 08/11] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 09/11] RISC-V: Add disassembler tests " Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 10/11] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI
2022-05-22 5:16 ` [PATCH v2 11/11] RISC-V: Add disassembler tests " Tsukasa OI
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