From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: binutils@sourceware.org
Subject: [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements
Date: Sun, 22 May 2022 14:15:49 +0900 [thread overview]
Message-ID: <cover.1653196556.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1643723292.git.research_trasio@irq.a4lg.com>
This patchset fixes various issues on Zfinx/Zdinx/Zqinx extensions.
PATCH v1:
<https://sourceware.org/pipermail/binutils/2022-February/119570.html> (Part 1)
<https://sourceware.org/pipermail/binutils/2022-February/119576.html> (Part 2A)
<https://sourceware.org/pipermail/binutils/2022-February/119582.html> (Part 3)
Although general idea of my fixes is reviewed by Palmer Dabbelt (and
this patchset is based on reviewed Part 1+2A+3 of PATCH v1), I made
relatively large changes to former Part 2A (06 and 07 in PATCH v2).
So, I'll explain what happened since then. Part 1 and 3 of PATCH v1
(01-05, 08-11 in PATCH v2) are practically unchanged.
Patrick O'Neill made important changes to error and feature handling
on the assembler (commit e4028336b19998e74a51dd0918a8b3922e08a537) but
it affected my PATCH v1 in a bad way.
On a GAS testcase gas/riscv/rouding-fail, it should generate errors
like this:
/.../gas/testsuite/gas/riscv/rouding-fail.s:2: Error: illegal operands `fadd.s fa1,fa1,fa1,'
/.../gas/testsuite/gas/riscv/rouding-fail.s:3: Error: illegal operands `fadd.d fa1,fa1,fa1,'
But with rebased PATCH v1, it looks like this:
/.../gas/testsuite/gas/riscv/rouding-fail.s:2: Error: illegal operands `fadd.s fa1,fa1,fa1,'
/.../gas/testsuite/gas/riscv/rouding-fail.s:3: Error: illegal operands `fadd.d fa1,fa1,fa1,', extension `zdinx' required
Note that "extension `zdinx' required" on `fadd.d'.
If D/Zdinx or Q/Zqinx assembler instruction fails to parse with a reason
BUT insufficient ISA extensions (e.g. D or Zdinx is enabled but has an
invalid operand), it fails with an "extension required" message.
This is caused as follows (e.g. on `fadd.d'):
- In my PATCH v1, all D/Zdinx and Q/Zqinx instructions are splitted to
XLEN-independent D/Q and XLEN-dependent Zdinx/Zqinx variants
(due to register constraints in Zdinx/Zqinx).
- All three entries of "fadd.d" are scanned:
1. XLEN-independent D variant
2. RV32_Zdinx variant
3. RV64_Zdinx variant
- But at least one of them fails because of insufficient ISA
extensions (because D and Zdinx are mutually exclusive).
- So, `error.missing_ext' is set to a non-null value on
`riscv_ip' function.
- Since `error.missing_ext' is non-null, "extension required" message
is generated and shown.
That's why I needed a special pinfo flag `INSN_F_OR_X' on PATCH v2.
In my PATCH v2, I implemented as follows:
if an instruction (with INSN_F_OR_X) parsing fails with an insufficient
extension error, it tests with secondary instruction class
(diagnostics-only) and `error.missing_ext' is set only if it ALSO fails
(note that setting `error.missing_ext' is suppressed but fails anyway
even if the secondary test succeeds).
On XLEN-independent D variant of `fadd.d' with Zdinx enabled
(instruction class INSN_CLASS_D), it also checks Zdinx with secondary
instruction class INSN_CLASS_D_OR_ZDINX. It can suppress unnecessary
"extension required" error.
Tsukasa OI (11):
RISC-V: Fix disassembling Zfinx with -M numeric
RISC-V: Make indentation consistent
RISC-V: Use different registers for testing
RISC-V: Relax `fmv.[sdq]' requirements
RISC-V: Fix RV64_Zqinx to use register pairs
RISC-V: Prepare D/Q and Zdinx/Zqinx separation
RISC-V: Validate Zdinx/Zqinx register pairs
RISC-V: Add assembler testcases for Zdinx regs
RISC-V: Add disassembler tests for Zdinx regs
RISC-V: Add assembler testcases for Zqinx regs
RISC-V: Add disassembler tests for Zqinx regs
bfd/elfxx-riscv.c | 8 +
gas/config/tc-riscv.c | 20 +-
.../gas/riscv/zdinx-32-regpair-dis.d | 11 +
.../gas/riscv/zdinx-32-regpair-dis.s | 5 +
.../gas/riscv/zdinx-32-regpair-fail.d | 3 +
.../gas/riscv/zdinx-32-regpair-fail.l | 111 ++++
.../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++
gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 +++
gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++
gas/testsuite/gas/riscv/zdinx.d | 7 +-
gas/testsuite/gas/riscv/zdinx.s | 7 +-
gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 10 +
gas/testsuite/gas/riscv/zfinx-dis-numeric.s | 2 +
gas/testsuite/gas/riscv/zfinx.d | 7 +-
gas/testsuite/gas/riscv/zfinx.s | 7 +-
.../gas/riscv/zqinx-32-regpair-dis.d | 12 +
.../gas/riscv/zqinx-32-regpair-dis.s | 7 +
.../gas/riscv/zqinx-32-regpair-fail.d | 3 +
.../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++
.../gas/riscv/zqinx-32-regpair-fail.s | 218 +++++++
gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 +++
gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++
.../gas/riscv/zqinx-64-regpair-dis.d | 11 +
.../gas/riscv/zqinx-64-regpair-dis.s | 5 +
.../gas/riscv/zqinx-64-regpair-fail.d | 3 +
.../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++
.../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++
gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++
gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++
gas/testsuite/gas/riscv/zqinx.d | 69 +--
gas/testsuite/gas/riscv/zqinx.s | 69 +--
include/opcode/riscv.h | 10 +-
opcodes/riscv-dis.c | 2 +-
opcodes/riscv-opc.c | 541 ++++++++++++++----
34 files changed, 1985 insertions(+), 190 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s
create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.d
create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s
base-commit: cb3a7614feb82ffdc25161bf60529116c6112ab3
--
2.34.1
next prev parent reply other threads:[~2022-05-22 5:16 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-01 13:49 [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1 Tsukasa OI
2022-02-01 13:49 ` [PATCH 1/5] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 2/5] RISC-V: Make indentation consistent Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 3/5] RISC-V: Use different registers for testing Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 4/5] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-08 9:51 ` Tsukasa OI
2022-02-01 13:49 ` [PATCH 5/5] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:51 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Tsukasa OI
2022-02-01 13:51 ` [RFC PATCH 1/2] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI
2022-02-01 13:51 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-02-08 2:00 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Palmer Dabbelt
2022-02-01 13:52 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2B Tsukasa OI
2022-02-01 13:52 ` [RFC PATCH 1/2] RISC-V: Add floating point instruction metadata Tsukasa OI
2022-02-01 13:52 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-02-01 13:53 ` [PATCH 0/4] RISC-V: Zfinx fixes/enhancements: Part 3 Tsukasa OI
2022-02-01 13:53 ` [PATCH 1/4] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 2/4] RISC-V: Add disassembler tests " Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 3/4] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI
2022-02-08 2:01 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 4/4] RISC-V: Add disassembler tests " Tsukasa OI
2022-05-22 5:15 ` Tsukasa OI [this message]
2022-05-22 5:15 ` [PATCH v2 01/11] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 02/11] RISC-V: Make indentation consistent Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 03/11] RISC-V: Use different registers for testing Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 04/11] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 05/11] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 06/11] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 07/11] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 08/11] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 09/11] RISC-V: Add disassembler tests " Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 10/11] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI
2022-05-22 5:16 ` [PATCH v2 11/11] RISC-V: Add disassembler tests " Tsukasa OI
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