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From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: binutils@sourceware.org
Subject: [PATCH v2 01/11] RISC-V: Fix disassembling Zfinx with -M numeric
Date: Sun, 22 May 2022 14:15:50 +0900	[thread overview]
Message-ID: <8a2114fd36300f027e7a312ded7bd9dae13c7f07.1653196556.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1653196556.git.research_trasio@irq.a4lg.com>

This commit fixes floating point operand register names from ABI ones
to dynamically set ones.

gas/ChangeLog:

	* testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of
	Zfinx extension and -M numeric disassembler option.
	* testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise.

opcodes/ChangeLog:

	* riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR
	names to disassemble Zfinx instructions.
---
 gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 10 ++++++++++
 gas/testsuite/gas/riscv/zfinx-dis-numeric.s |  2 ++
 opcodes/riscv-dis.c                         |  2 +-
 3 files changed, 13 insertions(+), 1 deletion(-)
 create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.d
 create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.s

diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.d b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d
new file mode 100644
index 00000000000..ba3f62295eb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d
@@ -0,0 +1,10 @@
+#as: -march=rv64ima_zfinx
+#source: zfinx-dis-numeric.s
+#objdump: -dr -Mnumeric
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+a0c5a553[ 	]+feq.s[ 	]+x10,x11,x12
diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.s b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s
new file mode 100644
index 00000000000..b55cbd56b21
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s
@@ -0,0 +1,2 @@
+target:
+	feq.s	a0, a1, a2
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 9ff31167775..164fd209dbd 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -639,7 +639,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 
       /* If arch has ZFINX flags, use gpr for disassemble.  */
       if(riscv_subset_supports (&riscv_rps_dis, "zfinx"))
-	riscv_fpr_names = riscv_gpr_names_abi;
+	riscv_fpr_names = riscv_gpr_names;
 
       for (; op->name; op++)
 	{
-- 
2.34.1


  reply	other threads:[~2022-05-22  5:16 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-01 13:49 [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1 Tsukasa OI
2022-02-01 13:49 ` [PATCH 1/5] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-02-08  2:00   ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 2/5] RISC-V: Make indentation consistent Tsukasa OI
2022-02-08  2:00   ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 3/5] RISC-V: Use different registers for testing Tsukasa OI
2022-02-08  2:00   ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 4/5] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-02-08  2:00   ` Palmer Dabbelt
2022-02-08  9:51     ` Tsukasa OI
2022-02-01 13:49 ` [PATCH 5/5] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI
2022-02-08  2:00   ` Palmer Dabbelt
2022-02-01 13:51 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Tsukasa OI
2022-02-01 13:51   ` [RFC PATCH 1/2] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI
2022-02-01 13:51   ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-02-08  2:00   ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Palmer Dabbelt
2022-02-01 13:52 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2B Tsukasa OI
2022-02-01 13:52   ` [RFC PATCH 1/2] RISC-V: Add floating point instruction metadata Tsukasa OI
2022-02-01 13:52   ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-02-01 13:53 ` [PATCH 0/4] RISC-V: Zfinx fixes/enhancements: Part 3 Tsukasa OI
2022-02-01 13:53   ` [PATCH 1/4] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI
2022-02-08  2:00     ` Palmer Dabbelt
2022-02-01 13:53   ` [PATCH 2/4] RISC-V: Add disassembler tests " Tsukasa OI
2022-02-08  2:00     ` Palmer Dabbelt
2022-02-01 13:53   ` [PATCH 3/4] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI
2022-02-08  2:01     ` Palmer Dabbelt
2022-02-01 13:53   ` [PATCH 4/4] RISC-V: Add disassembler tests " Tsukasa OI
2022-05-22  5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI
2022-05-22  5:15   ` Tsukasa OI [this message]
2022-05-22  5:15   ` [PATCH v2 02/11] RISC-V: Make indentation consistent Tsukasa OI
2022-05-22  5:15   ` [PATCH v2 03/11] RISC-V: Use different registers for testing Tsukasa OI
2022-05-22  5:15   ` [PATCH v2 04/11] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-05-22  5:15   ` [PATCH v2 05/11] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI
2022-05-22  5:15   ` [PATCH v2 06/11] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI
2022-05-22  5:15   ` [PATCH v2 07/11] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-05-22  5:15   ` [PATCH v2 08/11] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI
2022-05-22  5:15   ` [PATCH v2 09/11] RISC-V: Add disassembler tests " Tsukasa OI
2022-05-22  5:15   ` [PATCH v2 10/11] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI
2022-05-22  5:16   ` [PATCH v2 11/11] RISC-V: Add disassembler tests " Tsukasa OI

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