From: Palmer Dabbelt <palmer@rivosinc.com>
To: binutils@sourceware.org
Cc: research_trasio@irq.a4lg.com, binutils@sourceware.org
Subject: Re: [PATCH 2/4] RISC-V: Add disassembler tests for Zdinx regs
Date: Mon, 07 Feb 2022 18:00:57 -0800 (PST) [thread overview]
Message-ID: <mhng-751aac98-4c27-40ab-973f-610cc40fc000@palmer-ri-x1c9> (raw)
In-Reply-To: <0224765598be7e004b28401f045ffede73a6e6f7.1643723585.git.research_trasio@irq.a4lg.com>
On Tue, 01 Feb 2022 05:53:36 PST (-0800), binutils@sourceware.org wrote:
> This commid adds disassembler tests for invalid Zdinx register numbers
> (make sure that we don't disassemble invalid encodings).
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/zdinx-32-regpair-dis.s: New test to make
> sure that invalid encoding is not disassembled.
> * testsuite/gas/riscv/zdinx-32-regpair-dis.d: Likewise.
> ---
> gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d | 11 +++++++++++
> gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s | 5 +++++
> 2 files changed, 16 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d
> create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s
>
> diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d
> new file mode 100644
> index 00000000000..018a0e51f03
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d
> @@ -0,0 +1,11 @@
> +#as: -march=rv32ima_zdinx
> +#source: zdinx-32-regpair-dis.s
> +#objdump: -dr -Mnumeric
> +
> +.*:[ ]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+02627153[ ]+fadd.d[ ]+x2,x4,x6
> +[ ]+[0-9a-f]+:[ ]+0272f1d3[ ]+\.4byte[ ]+0x272f1d3
> diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s
> new file mode 100644
> index 00000000000..aa0c72cae87
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s
> @@ -0,0 +1,5 @@
> +target:
> + # fadd.d x2, x4, x6
> + .insn 0x02627153
> + # fadd.d x3, x5, x7 (invalid)
> + .insn 0x0272f1d3
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
next prev parent reply other threads:[~2022-02-08 2:00 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-01 13:49 [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1 Tsukasa OI
2022-02-01 13:49 ` [PATCH 1/5] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 2/5] RISC-V: Make indentation consistent Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 3/5] RISC-V: Use different registers for testing Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 4/5] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-08 9:51 ` Tsukasa OI
2022-02-01 13:49 ` [PATCH 5/5] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:51 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Tsukasa OI
2022-02-01 13:51 ` [RFC PATCH 1/2] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI
2022-02-01 13:51 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-02-08 2:00 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Palmer Dabbelt
2022-02-01 13:52 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2B Tsukasa OI
2022-02-01 13:52 ` [RFC PATCH 1/2] RISC-V: Add floating point instruction metadata Tsukasa OI
2022-02-01 13:52 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-02-01 13:53 ` [PATCH 0/4] RISC-V: Zfinx fixes/enhancements: Part 3 Tsukasa OI
2022-02-01 13:53 ` [PATCH 1/4] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 2/4] RISC-V: Add disassembler tests " Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt [this message]
2022-02-01 13:53 ` [PATCH 3/4] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI
2022-02-08 2:01 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 4/4] RISC-V: Add disassembler tests " Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 01/11] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 02/11] RISC-V: Make indentation consistent Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 03/11] RISC-V: Use different registers for testing Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 04/11] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 05/11] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 06/11] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 07/11] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 08/11] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 09/11] RISC-V: Add disassembler tests " Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 10/11] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI
2022-05-22 5:16 ` [PATCH v2 11/11] RISC-V: Add disassembler tests " Tsukasa OI
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=mhng-751aac98-4c27-40ab-973f-610cc40fc000@palmer-ri-x1c9 \
--to=palmer@rivosinc.com \
--cc=binutils@sourceware.org \
--cc=research_trasio@irq.a4lg.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).