From: Palmer Dabbelt <palmer@rivosinc.com>
To: binutils@sourceware.org
Cc: research_trasio@irq.a4lg.com, binutils@sourceware.org
Subject: Re: [PATCH 2/5] RISC-V: Make indentation consistent
Date: Mon, 07 Feb 2022 18:00:50 -0800 (PST) [thread overview]
Message-ID: <mhng-bf82b2cf-4332-4632-aedb-1d9e1e371861@palmer-ri-x1c9> (raw)
In-Reply-To: <d2f5e2e69b5a8effda1aea21cd305b149b26b81b.1643723292.git.research_trasio@irq.a4lg.com>
On Tue, 01 Feb 2022 05:49:03 PST (-0800), binutils@sourceware.org wrote:
> This commit makes indentation consistent (replaces two spaces to a tab)
> on Zfinx / Zdinx / Zqinx testcases.
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/zfinx.s: Make indentation consistent.
> * testsuite/gas/riscv/zdinx.s: Likewise.
> * testsuite/gas/riscv/zqinx.s: Likewise.
> ---
> gas/testsuite/gas/riscv/zdinx.s | 2 +-
> gas/testsuite/gas/riscv/zfinx.s | 2 +-
> gas/testsuite/gas/riscv/zqinx.s | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s
> index c427d982aaf..d8d13c88046 100644
> --- a/gas/testsuite/gas/riscv/zdinx.s
> +++ b/gas/testsuite/gas/riscv/zdinx.s
> @@ -28,6 +28,6 @@ target:
> fle.d a0, a1, a2
> fgt.d a0, a1, a2
> fge.d a0, a1, a2
> - fneg.d a0, a0
> + fneg.d a0, a0
> fabs.d a0, a0
> fclass.d a0, a1
> diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s
> index af50490fadf..37a2aa75992 100644
> --- a/gas/testsuite/gas/riscv/zfinx.s
> +++ b/gas/testsuite/gas/riscv/zfinx.s
> @@ -26,6 +26,6 @@ target:
> fle.s a0, a1, a2
> fgt.s a0, a1, a2
> fge.s a0, a1, a2
> - fneg.s a0, a0
> + fneg.s a0, a0
> fabs.s a0, a0
> fclass.s a0, a1
> diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s
> index ba5179dc727..4b83552aced 100644
> --- a/gas/testsuite/gas/riscv/zqinx.s
> +++ b/gas/testsuite/gas/riscv/zqinx.s
> @@ -30,6 +30,6 @@ target:
> fle.q a0, a1, a2
> fgt.q a0, a1, a2
> fge.q a0, a1, a2
> - fneg.q a0, a0
> + fneg.q a0, a0
> fabs.q a0, a0
> fclass.q a0, a1
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
next prev parent reply other threads:[~2022-02-08 2:00 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-01 13:49 [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1 Tsukasa OI
2022-02-01 13:49 ` [PATCH 1/5] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 2/5] RISC-V: Make indentation consistent Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt [this message]
2022-02-01 13:49 ` [PATCH 3/5] RISC-V: Use different registers for testing Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 4/5] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-08 9:51 ` Tsukasa OI
2022-02-01 13:49 ` [PATCH 5/5] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:51 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Tsukasa OI
2022-02-01 13:51 ` [RFC PATCH 1/2] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI
2022-02-01 13:51 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-02-08 2:00 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Palmer Dabbelt
2022-02-01 13:52 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2B Tsukasa OI
2022-02-01 13:52 ` [RFC PATCH 1/2] RISC-V: Add floating point instruction metadata Tsukasa OI
2022-02-01 13:52 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-02-01 13:53 ` [PATCH 0/4] RISC-V: Zfinx fixes/enhancements: Part 3 Tsukasa OI
2022-02-01 13:53 ` [PATCH 1/4] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 2/4] RISC-V: Add disassembler tests " Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 3/4] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI
2022-02-08 2:01 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 4/4] RISC-V: Add disassembler tests " Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 01/11] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 02/11] RISC-V: Make indentation consistent Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 03/11] RISC-V: Use different registers for testing Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 04/11] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 05/11] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 06/11] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 07/11] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 08/11] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 09/11] RISC-V: Add disassembler tests " Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 10/11] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI
2022-05-22 5:16 ` [PATCH v2 11/11] RISC-V: Add disassembler tests " Tsukasa OI
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