From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: binutils@sourceware.org
Subject: [PATCH v2 03/11] RISC-V: Use different registers for testing
Date: Sun, 22 May 2022 14:15:52 +0900 [thread overview]
Message-ID: <d0b8b6104daa935df7de04f530ea76bd83b2c0a4.1653196556.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1653196556.git.research_trasio@irq.a4lg.com>
This commit ensures that different registers are used when testing.
gas/ChangeLog:
* testsuite/gas/riscv/zfinx.s: Use different registers.
* testsuite/gas/riscv/zfinx.d: Likewise.
* testsuite/gas/riscv/zdinx.s: Use different registers.
* testsuite/gas/riscv/zdinx.d: Likewise.
* testsuite/gas/riscv/zqinx.s: Use different registers.
* testsuite/gas/riscv/zqinx.d: Likewise.
---
gas/testsuite/gas/riscv/zdinx.d | 6 +++---
gas/testsuite/gas/riscv/zdinx.s | 6 +++---
gas/testsuite/gas/riscv/zfinx.d | 6 +++---
gas/testsuite/gas/riscv/zfinx.s | 6 +++---
gas/testsuite/gas/riscv/zqinx.d | 6 +++---
gas/testsuite/gas/riscv/zqinx.s | 6 +++---
6 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d
index 3e4c1a73388..cb465bfbef4 100644
--- a/gas/testsuite/gas/riscv/zdinx.d
+++ b/gas/testsuite/gas/riscv/zdinx.d
@@ -11,7 +11,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+0ac5f553[ ]+fsub.d[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+12c5f553[ ]+fmul.d[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+1ac5f553[ ]+fdiv.d[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+5a057553[ ]+fsqrt.d[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+5a05f553[ ]+fsqrt.d[ ]+a0,a1
[ ]+[0-9a-f]+:[ ]+2ac58553[ ]+fmin.d[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+2ac59553[ ]+fmax.d[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+6ac5f543[ ]+fmadd.d[ ]+a0,a1,a2,a3
@@ -36,6 +36,6 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1
[ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1
-[ ]+[0-9a-f]+:[ ]+22a51553[ ]+fneg.d[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+22a52553[ ]+fabs.d[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1
[ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1
diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s
index d8d13c88046..f44358111de 100644
--- a/gas/testsuite/gas/riscv/zdinx.s
+++ b/gas/testsuite/gas/riscv/zdinx.s
@@ -3,7 +3,7 @@ target:
fsub.d a0, a1, a2
fmul.d a0, a1, a2
fdiv.d a0, a1, a2
- fsqrt.d a0, a0
+ fsqrt.d a0, a1
fmin.d a0, a1, a2
fmax.d a0, a1, a2
fmadd.d a0, a1, a2, a3
@@ -28,6 +28,6 @@ target:
fle.d a0, a1, a2
fgt.d a0, a1, a2
fge.d a0, a1, a2
- fneg.d a0, a0
- fabs.d a0, a0
+ fneg.d a0, a1
+ fabs.d a0, a1
fclass.d a0, a1
diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d
index d5499aa9131..6465c08ea9a 100644
--- a/gas/testsuite/gas/riscv/zfinx.d
+++ b/gas/testsuite/gas/riscv/zfinx.d
@@ -11,7 +11,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+08c5f553[ ]+fsub.s[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+10c5f553[ ]+fmul.s[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+18c5f553[ ]+fdiv.s[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+58057553[ ]+fsqrt.s[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+5805f553[ ]+fsqrt.s[ ]+a0,a1
[ ]+[0-9a-f]+:[ ]+28c58553[ ]+fmin.s[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+28c59553[ ]+fmax.s[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+68c5f543[ ]+fmadd.s[ ]+a0,a1,a2,a3
@@ -34,6 +34,6 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1
[ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1
-[ ]+[0-9a-f]+:[ ]+20a51553[ ]+fneg.s[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+20a52553[ ]+fabs.s[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1
[ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1
diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s
index 37a2aa75992..41ae0e38ad4 100644
--- a/gas/testsuite/gas/riscv/zfinx.s
+++ b/gas/testsuite/gas/riscv/zfinx.s
@@ -3,7 +3,7 @@ target:
fsub.s a0, a1, a2
fmul.s a0, a1, a2
fdiv.s a0, a1, a2
- fsqrt.s a0, a0
+ fsqrt.s a0, a1
fmin.s a0, a1, a2
fmax.s a0, a1, a2
fmadd.s a0, a1, a2, a3
@@ -26,6 +26,6 @@ target:
fle.s a0, a1, a2
fgt.s a0, a1, a2
fge.s a0, a1, a2
- fneg.s a0, a0
- fabs.s a0, a0
+ fneg.s a0, a1
+ fabs.s a0, a1
fclass.s a0, a1
diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d
index c1a09201206..2123ee1b864 100644
--- a/gas/testsuite/gas/riscv/zqinx.d
+++ b/gas/testsuite/gas/riscv/zqinx.d
@@ -11,7 +11,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+0ec5f553[ ]+fsub.q[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+16c5f553[ ]+fmul.q[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+1ec5f553[ ]+fdiv.q[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+5e057553[ ]+fsqrt.q[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+5e05f553[ ]+fsqrt.q[ ]+a0,a1
[ ]+[0-9a-f]+:[ ]+2ec58553[ ]+fmin.q[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+2ec59553[ ]+fmax.q[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+6ec5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3
@@ -38,6 +38,6 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1
[ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1
-[ ]+[0-9a-f]+:[ ]+26a51553[ ]+fneg.q[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+26a52553[ ]+fabs.q[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+26b59553[ ]+fneg.q[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+26b5a553[ ]+fabs.q[ ]+a0,a1
[ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1
diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s
index 4b83552aced..ecfa509b98c 100644
--- a/gas/testsuite/gas/riscv/zqinx.s
+++ b/gas/testsuite/gas/riscv/zqinx.s
@@ -3,7 +3,7 @@ target:
fsub.q a0, a1, a2
fmul.q a0, a1, a2
fdiv.q a0, a1, a2
- fsqrt.q a0, a0
+ fsqrt.q a0, a1
fmin.q a0, a1, a2
fmax.q a0, a1, a2
fmadd.q a0, a1, a2, a3
@@ -30,6 +30,6 @@ target:
fle.q a0, a1, a2
fgt.q a0, a1, a2
fge.q a0, a1, a2
- fneg.q a0, a0
- fabs.q a0, a0
+ fneg.q a0, a1
+ fabs.q a0, a1
fclass.q a0, a1
--
2.34.1
next prev parent reply other threads:[~2022-05-22 5:16 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-01 13:49 [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1 Tsukasa OI
2022-02-01 13:49 ` [PATCH 1/5] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 2/5] RISC-V: Make indentation consistent Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 3/5] RISC-V: Use different registers for testing Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:49 ` [PATCH 4/5] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-08 9:51 ` Tsukasa OI
2022-02-01 13:49 ` [PATCH 5/5] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:51 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Tsukasa OI
2022-02-01 13:51 ` [RFC PATCH 1/2] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI
2022-02-01 13:51 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-02-08 2:00 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A Palmer Dabbelt
2022-02-01 13:52 ` [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2B Tsukasa OI
2022-02-01 13:52 ` [RFC PATCH 1/2] RISC-V: Add floating point instruction metadata Tsukasa OI
2022-02-01 13:52 ` [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-02-01 13:53 ` [PATCH 0/4] RISC-V: Zfinx fixes/enhancements: Part 3 Tsukasa OI
2022-02-01 13:53 ` [PATCH 1/4] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 2/4] RISC-V: Add disassembler tests " Tsukasa OI
2022-02-08 2:00 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 3/4] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI
2022-02-08 2:01 ` Palmer Dabbelt
2022-02-01 13:53 ` [PATCH 4/4] RISC-V: Add disassembler tests " Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 00/11] RISC-V: Zfinx fixes/enhancements Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 01/11] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 02/11] RISC-V: Make indentation consistent Tsukasa OI
2022-05-22 5:15 ` Tsukasa OI [this message]
2022-05-22 5:15 ` [PATCH v2 04/11] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 05/11] RISC-V: Fix RV64_Zqinx to use register pairs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 06/11] RISC-V: Prepare D/Q and Zdinx/Zqinx separation Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 07/11] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 08/11] RISC-V: Add assembler testcases for Zdinx regs Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 09/11] RISC-V: Add disassembler tests " Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 10/11] RISC-V: Add assembler testcases for Zqinx regs Tsukasa OI
2022-05-22 5:16 ` [PATCH v2 11/11] RISC-V: Add disassembler tests " Tsukasa OI
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