* [REVIEW ONLY 0/2] NEAR RATIFICATION RISC-V: Extensions from the RISC-V Profiles
@ 2022-11-03 12:26 Tsukasa OI
2022-11-03 12:26 ` [REVIEW ONLY 1/2] NEAR-RATIFICATION RISC-V: Add 'Ssstateen' extension and its CSRs Tsukasa OI
` (3 more replies)
0 siblings, 4 replies; 17+ messages in thread
From: Tsukasa OI @ 2022-11-03 12:26 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
Hello,
This patchset implements all extensions from RISC-V Profiles (but not
profile itself). I'm not sure whether this patchset helps someone
implementing RISC-V Profiles but I hope so.
Thanks,
Tsukasa
Tsukasa OI (2):
NEAR-RATIFICATION RISC-V: Add 'Ssstateen' extension and its CSRs
NEAR-RATIFICATION RISC-V: Add platform property/capability extensions
bfd/elfxx-riscv.c | 38 +++++++++++++++-
gas/config/tc-riscv.c | 20 +++++----
gas/testsuite/gas/riscv/csr-version-1p10.l | 48 ++++++++++-----------
gas/testsuite/gas/riscv/csr-version-1p11.l | 48 ++++++++++-----------
gas/testsuite/gas/riscv/csr-version-1p12.l | 48 ++++++++++-----------
gas/testsuite/gas/riscv/csr-version-1p9p1.l | 48 ++++++++++-----------
gas/testsuite/gas/riscv/csr.s | 2 +-
gas/testsuite/gas/riscv/smstateen-csr-s.d | 22 ++++++++++
gas/testsuite/gas/riscv/ssstateen-csr.d | 22 ++++++++++
gas/testsuite/gas/riscv/ssstateen-csr.s | 13 ++++++
include/opcode/riscv-opc.h | 26 +++++------
11 files changed, 215 insertions(+), 120 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/smstateen-csr-s.d
create mode 100644 gas/testsuite/gas/riscv/ssstateen-csr.d
create mode 100644 gas/testsuite/gas/riscv/ssstateen-csr.s
base-commit: ae1c45ead6b60ef0fd338bbeb6a4c5e5808c6e6a
--
2.37.2
^ permalink raw reply [flat|nested] 17+ messages in thread* [REVIEW ONLY 1/2] NEAR-RATIFICATION RISC-V: Add 'Ssstateen' extension and its CSRs 2022-11-03 12:26 [REVIEW ONLY 0/2] NEAR RATIFICATION RISC-V: Extensions from the RISC-V Profiles Tsukasa OI @ 2022-11-03 12:26 ` Tsukasa OI 2022-11-03 12:26 ` [REVIEW ONLY 2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions Tsukasa OI ` (2 subsequent siblings) 3 siblings, 0 replies; 17+ messages in thread From: Tsukasa OI @ 2022-11-03 12:26 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils [DO NOT MERGE] RISC-V Profiles are frozen but -- from my view -- this document will still change in some way. Meanwhile, this patch should not be merged upstream. This commit uses tentative version 1.0 (same as 'Smstateen'). This commit adds 'Ssstateen' extension, which is a supervisor-visible view of the 'Smstateen' extension. It means, this extension implements sstateen* and hstateen* CSRs of the 'Smstateen' extension. Note that 'Smstateen' extension itself is unchanged but due to implementation simplicity, it is implemented so that 'Smstateen' implies 'Ssstateen' (just like 'M' implies 'Zmmul'). This is based on the latest version of RISC-V Profiles (version 0.9-draft): <https://github.com/riscv/riscv-profiles/commit/226b7f643067b29abc6723fac60d5f6d3f9eb901> bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Update implication rules. (riscv_supported_std_s_ext) Add 'Ssstateen' extension. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Rename CSR_CLASS_SMSTATEEN_AND_H{,_32} to CSR_CLASS_SSSTATEEN_... Add CSR_CLASS_SSSTATEEN. (riscv_csr_address): Support new/renamed CSR classes. * testsuite/gas/riscv/csr.s: Add 'Ssstateen' extension to comment. * testsuite/gas/riscv/csr-version-1p9p1.l: Reflect changes to error messages. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/ssstateen-csr.s: Test for 'Ssstateen' CSRs. * testsuite/gas/riscv/ssstateen-csr.d: Likewise. * testsuite/gas/riscv/smstateen-csr-s.d: Test to make sure that supervisor/hypervisor part of 'Smstateen' CSRs are accessible from 'RV32IH_Smstateen', not just from 'RV32IH_Ssstateen' that is tested in ssstateen-csr.d. include/ChangeLog: * opcode/riscv-opc.h: Update DECLARE_CSR declarations with new CSR classes. --- bfd/elfxx-riscv.c | 4 +- gas/config/tc-riscv.c | 20 +++++---- gas/testsuite/gas/riscv/csr-version-1p10.l | 48 ++++++++++----------- gas/testsuite/gas/riscv/csr-version-1p11.l | 48 ++++++++++----------- gas/testsuite/gas/riscv/csr-version-1p12.l | 48 ++++++++++----------- gas/testsuite/gas/riscv/csr-version-1p9p1.l | 48 ++++++++++----------- gas/testsuite/gas/riscv/csr.s | 2 +- gas/testsuite/gas/riscv/smstateen-csr-s.d | 22 ++++++++++ gas/testsuite/gas/riscv/ssstateen-csr.d | 22 ++++++++++ gas/testsuite/gas/riscv/ssstateen-csr.s | 13 ++++++ include/opcode/riscv-opc.h | 26 +++++------ 11 files changed, 182 insertions(+), 119 deletions(-) create mode 100644 gas/testsuite/gas/riscv/smstateen-csr-s.d create mode 100644 gas/testsuite/gas/riscv/ssstateen-csr.d create mode 100644 gas/testsuite/gas/riscv/ssstateen-csr.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 94bff0e0388..781b57cbd98 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1097,9 +1097,10 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zks", "zbkx", check_implicit_always}, {"zks", "zksed", check_implicit_always}, {"zks", "zksh", check_implicit_always}, + {"smstateen", "ssstateen", check_implicit_always}, {"smepmp", "zicsr", check_implicit_always}, - {"smstateen", "zicsr", check_implicit_always}, {"sscofpmf", "zicsr", check_implicit_always}, + {"ssstateen", "zicsr", check_implicit_always}, {"sstc", "zicsr", check_implicit_always}, {NULL, NULL, NULL} }; @@ -1219,6 +1220,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 2dc92ecd3c3..019545171f5 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -69,9 +69,10 @@ enum riscv_csr_class CSR_CLASS_H, /* hypervisor */ CSR_CLASS_H_32, /* hypervisor, rv32 only */ CSR_CLASS_SMSTATEEN, /* Smstateen only */ - CSR_CLASS_SMSTATEEN_AND_H, /* Smstateen only (with H) */ CSR_CLASS_SMSTATEEN_32, /* Smstateen RV32 only */ - CSR_CLASS_SMSTATEEN_AND_H_32, /* Smstateen RV32 only (with H) */ + CSR_CLASS_SSSTATEEN, /* S[ms]stateen only */ + CSR_CLASS_SSSTATEEN_AND_H, /* S[ms]stateen only (with H) */ + CSR_CLASS_SSSTATEEN_AND_H_32, /* S[ms]stateen RV32 only (with H) */ CSR_CLASS_SSCOFPMF, /* Sscofpmf only */ CSR_CLASS_SSCOFPMF_32, /* Sscofpmf RV32 only */ CSR_CLASS_SSTC, /* Sstc only */ @@ -1029,15 +1030,18 @@ riscv_csr_address (const char *csr_name, extension = "zve32x"; break; case CSR_CLASS_SMSTATEEN: - case CSR_CLASS_SMSTATEEN_AND_H: case CSR_CLASS_SMSTATEEN_32: - case CSR_CLASS_SMSTATEEN_AND_H_32: - is_rv32_only = (csr_class == CSR_CLASS_SMSTATEEN_32 - || csr_class == CSR_CLASS_SMSTATEEN_AND_H_32); - is_h_required = (csr_class == CSR_CLASS_SMSTATEEN_AND_H - || csr_class == CSR_CLASS_SMSTATEEN_AND_H_32); + is_rv32_only = (csr_class == CSR_CLASS_SMSTATEEN_32); extension = "smstateen"; break; + case CSR_CLASS_SSSTATEEN: + case CSR_CLASS_SSSTATEEN_AND_H: + case CSR_CLASS_SSSTATEEN_AND_H_32: + is_rv32_only = (csr_class == CSR_CLASS_SSSTATEEN_AND_H_32); + is_h_required = (csr_class == CSR_CLASS_SSSTATEEN_AND_H + || csr_class == CSR_CLASS_SSSTATEEN_AND_H_32); + extension = "ssstateen"; + break; case CSR_CLASS_SSCOFPMF_32: is_rv32_only = true; /* Fall through. */ diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l index 999e9af1520..03af32d3bef 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p10.l +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l @@ -419,30 +419,30 @@ .*Warning: invalid CSR `mstateen2', needs `smstateen' extension .*Warning: invalid CSR `mstateen3', needs `smstateen' extension .*Warning: invalid CSR `mstateen3', needs `smstateen' extension -.*Warning: invalid CSR `sstateen0', needs `smstateen' extension -.*Warning: invalid CSR `sstateen0', needs `smstateen' extension -.*Warning: invalid CSR `sstateen1', needs `smstateen' extension -.*Warning: invalid CSR `sstateen1', needs `smstateen' extension -.*Warning: invalid CSR `sstateen2', needs `smstateen' extension -.*Warning: invalid CSR `sstateen2', needs `smstateen' extension -.*Warning: invalid CSR `sstateen3', needs `smstateen' extension -.*Warning: invalid CSR `sstateen3', needs `smstateen' extension +.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension .*Warning: invalid CSR `hstateen0', needs `h' extension -.*Warning: invalid CSR `hstateen0', needs `smstateen' extension +.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension .*Warning: invalid CSR `hstateen0', needs `h' extension -.*Warning: invalid CSR `hstateen0', needs `smstateen' extension +.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension .*Warning: invalid CSR `hstateen1', needs `h' extension -.*Warning: invalid CSR `hstateen1', needs `smstateen' extension +.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension .*Warning: invalid CSR `hstateen1', needs `h' extension -.*Warning: invalid CSR `hstateen1', needs `smstateen' extension +.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension .*Warning: invalid CSR `hstateen2', needs `h' extension -.*Warning: invalid CSR `hstateen2', needs `smstateen' extension +.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension .*Warning: invalid CSR `hstateen2', needs `h' extension -.*Warning: invalid CSR `hstateen2', needs `smstateen' extension +.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension .*Warning: invalid CSR `hstateen3', needs `h' extension -.*Warning: invalid CSR `hstateen3', needs `smstateen' extension +.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension .*Warning: invalid CSR `hstateen3', needs `h' extension -.*Warning: invalid CSR `hstateen3', needs `smstateen' extension +.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension .*Warning: invalid CSR `mstateen0h', needs rv32i extension .*Warning: invalid CSR `mstateen0h', needs `smstateen' extension .*Warning: invalid CSR `mstateen0h', needs rv32i extension @@ -461,28 +461,28 @@ .*Warning: invalid CSR `mstateen3h', needs `smstateen' extension .*Warning: invalid CSR `hstateen0h', needs rv32i extension .*Warning: invalid CSR `hstateen0h', needs `h' extension -.*Warning: invalid CSR `hstateen0h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen0h', needs rv32i extension .*Warning: invalid CSR `hstateen0h', needs `h' extension -.*Warning: invalid CSR `hstateen0h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen1h', needs rv32i extension .*Warning: invalid CSR `hstateen1h', needs `h' extension -.*Warning: invalid CSR `hstateen1h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen1h', needs rv32i extension .*Warning: invalid CSR `hstateen1h', needs `h' extension -.*Warning: invalid CSR `hstateen1h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen2h', needs rv32i extension .*Warning: invalid CSR `hstateen2h', needs `h' extension -.*Warning: invalid CSR `hstateen2h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen2h', needs rv32i extension .*Warning: invalid CSR `hstateen2h', needs `h' extension -.*Warning: invalid CSR `hstateen2h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen3h', needs rv32i extension .*Warning: invalid CSR `hstateen3h', needs `h' extension -.*Warning: invalid CSR `hstateen3h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen3h', needs rv32i extension .*Warning: invalid CSR `hstateen3h', needs `h' extension -.*Warning: invalid CSR `hstateen3h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension .*Warning: invalid CSR `scountovf', needs `sscofpmf' extension .*Warning: invalid CSR `scountovf', needs `sscofpmf' extension .*Warning: read-only CSR is written `csrw scountovf,a1' diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l index a099e4ecc93..0766c2263ec 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p11.l +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l @@ -417,30 +417,30 @@ .*Warning: invalid CSR `mstateen2', needs `smstateen' extension .*Warning: invalid CSR `mstateen3', needs `smstateen' extension .*Warning: invalid CSR `mstateen3', needs `smstateen' extension -.*Warning: invalid CSR `sstateen0', needs `smstateen' extension -.*Warning: invalid CSR `sstateen0', needs `smstateen' extension -.*Warning: invalid CSR `sstateen1', needs `smstateen' extension -.*Warning: invalid CSR `sstateen1', needs `smstateen' extension -.*Warning: invalid CSR `sstateen2', needs `smstateen' extension -.*Warning: invalid CSR `sstateen2', needs `smstateen' extension -.*Warning: invalid CSR `sstateen3', needs `smstateen' extension -.*Warning: invalid CSR `sstateen3', needs `smstateen' extension +.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension .*Warning: invalid CSR `hstateen0', needs `h' extension -.*Warning: invalid CSR `hstateen0', needs `smstateen' extension +.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension .*Warning: invalid CSR `hstateen0', needs `h' extension -.*Warning: invalid CSR `hstateen0', needs `smstateen' extension +.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension .*Warning: invalid CSR `hstateen1', needs `h' extension -.*Warning: invalid CSR `hstateen1', needs `smstateen' extension +.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension .*Warning: invalid CSR `hstateen1', needs `h' extension -.*Warning: invalid CSR `hstateen1', needs `smstateen' extension +.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension .*Warning: invalid CSR `hstateen2', needs `h' extension -.*Warning: invalid CSR `hstateen2', needs `smstateen' extension +.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension .*Warning: invalid CSR `hstateen2', needs `h' extension -.*Warning: invalid CSR `hstateen2', needs `smstateen' extension +.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension .*Warning: invalid CSR `hstateen3', needs `h' extension -.*Warning: invalid CSR `hstateen3', needs `smstateen' extension +.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension .*Warning: invalid CSR `hstateen3', needs `h' extension -.*Warning: invalid CSR `hstateen3', needs `smstateen' extension +.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension .*Warning: invalid CSR `mstateen0h', needs rv32i extension .*Warning: invalid CSR `mstateen0h', needs `smstateen' extension .*Warning: invalid CSR `mstateen0h', needs rv32i extension @@ -459,28 +459,28 @@ .*Warning: invalid CSR `mstateen3h', needs `smstateen' extension .*Warning: invalid CSR `hstateen0h', needs rv32i extension .*Warning: invalid CSR `hstateen0h', needs `h' extension -.*Warning: invalid CSR `hstateen0h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen0h', needs rv32i extension .*Warning: invalid CSR `hstateen0h', needs `h' extension -.*Warning: invalid CSR `hstateen0h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen1h', needs rv32i extension .*Warning: invalid CSR `hstateen1h', needs `h' extension -.*Warning: invalid CSR `hstateen1h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen1h', needs rv32i extension .*Warning: invalid CSR `hstateen1h', needs `h' extension -.*Warning: invalid CSR `hstateen1h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen2h', needs rv32i extension .*Warning: invalid CSR `hstateen2h', needs `h' extension -.*Warning: invalid CSR `hstateen2h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen2h', needs rv32i extension .*Warning: invalid CSR `hstateen2h', needs `h' extension -.*Warning: invalid CSR `hstateen2h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen3h', needs rv32i extension .*Warning: invalid CSR `hstateen3h', needs `h' extension -.*Warning: invalid CSR `hstateen3h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen3h', needs rv32i extension .*Warning: invalid CSR `hstateen3h', needs `h' extension -.*Warning: invalid CSR `hstateen3h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension .*Warning: invalid CSR `scountovf', needs `sscofpmf' extension .*Warning: invalid CSR `scountovf', needs `sscofpmf' extension .*Warning: read-only CSR is written `csrw scountovf,a1' diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l index cf8f2e25634..c13efcc6681 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p12.l +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l @@ -279,30 +279,30 @@ .*Warning: invalid CSR `mstateen2', needs `smstateen' extension .*Warning: invalid CSR `mstateen3', needs `smstateen' extension .*Warning: invalid CSR `mstateen3', needs `smstateen' extension -.*Warning: invalid CSR `sstateen0', needs `smstateen' extension -.*Warning: invalid CSR `sstateen0', needs `smstateen' extension -.*Warning: invalid CSR `sstateen1', needs `smstateen' extension -.*Warning: invalid CSR `sstateen1', needs `smstateen' extension -.*Warning: invalid CSR `sstateen2', needs `smstateen' extension -.*Warning: invalid CSR `sstateen2', needs `smstateen' extension -.*Warning: invalid CSR `sstateen3', needs `smstateen' extension -.*Warning: invalid CSR `sstateen3', needs `smstateen' extension +.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension .*Warning: invalid CSR `hstateen0', needs `h' extension -.*Warning: invalid CSR `hstateen0', needs `smstateen' extension +.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension .*Warning: invalid CSR `hstateen0', needs `h' extension -.*Warning: invalid CSR `hstateen0', needs `smstateen' extension +.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension .*Warning: invalid CSR `hstateen1', needs `h' extension -.*Warning: invalid CSR `hstateen1', needs `smstateen' extension +.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension .*Warning: invalid CSR `hstateen1', needs `h' extension -.*Warning: invalid CSR `hstateen1', needs `smstateen' extension +.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension .*Warning: invalid CSR `hstateen2', needs `h' extension -.*Warning: invalid CSR `hstateen2', needs `smstateen' extension +.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension .*Warning: invalid CSR `hstateen2', needs `h' extension -.*Warning: invalid CSR `hstateen2', needs `smstateen' extension +.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension .*Warning: invalid CSR `hstateen3', needs `h' extension -.*Warning: invalid CSR `hstateen3', needs `smstateen' extension +.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension .*Warning: invalid CSR `hstateen3', needs `h' extension -.*Warning: invalid CSR `hstateen3', needs `smstateen' extension +.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension .*Warning: invalid CSR `mstateen0h', needs rv32i extension .*Warning: invalid CSR `mstateen0h', needs `smstateen' extension .*Warning: invalid CSR `mstateen0h', needs rv32i extension @@ -321,28 +321,28 @@ .*Warning: invalid CSR `mstateen3h', needs `smstateen' extension .*Warning: invalid CSR `hstateen0h', needs rv32i extension .*Warning: invalid CSR `hstateen0h', needs `h' extension -.*Warning: invalid CSR `hstateen0h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen0h', needs rv32i extension .*Warning: invalid CSR `hstateen0h', needs `h' extension -.*Warning: invalid CSR `hstateen0h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen1h', needs rv32i extension .*Warning: invalid CSR `hstateen1h', needs `h' extension -.*Warning: invalid CSR `hstateen1h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen1h', needs rv32i extension .*Warning: invalid CSR `hstateen1h', needs `h' extension -.*Warning: invalid CSR `hstateen1h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen2h', needs rv32i extension .*Warning: invalid CSR `hstateen2h', needs `h' extension -.*Warning: invalid CSR `hstateen2h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen2h', needs rv32i extension .*Warning: invalid CSR `hstateen2h', needs `h' extension -.*Warning: invalid CSR `hstateen2h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen3h', needs rv32i extension .*Warning: invalid CSR `hstateen3h', needs `h' extension -.*Warning: invalid CSR `hstateen3h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen3h', needs rv32i extension .*Warning: invalid CSR `hstateen3h', needs `h' extension -.*Warning: invalid CSR `hstateen3h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension .*Warning: invalid CSR `scountovf', needs `sscofpmf' extension .*Warning: invalid CSR `scountovf', needs `sscofpmf' extension .*Warning: read-only CSR is written `csrw scountovf,a1' diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l index 5f298c1dda9..bc35630abd0 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l @@ -469,30 +469,30 @@ .*Warning: invalid CSR `mstateen2', needs `smstateen' extension .*Warning: invalid CSR `mstateen3', needs `smstateen' extension .*Warning: invalid CSR `mstateen3', needs `smstateen' extension -.*Warning: invalid CSR `sstateen0', needs `smstateen' extension -.*Warning: invalid CSR `sstateen0', needs `smstateen' extension -.*Warning: invalid CSR `sstateen1', needs `smstateen' extension -.*Warning: invalid CSR `sstateen1', needs `smstateen' extension -.*Warning: invalid CSR `sstateen2', needs `smstateen' extension -.*Warning: invalid CSR `sstateen2', needs `smstateen' extension -.*Warning: invalid CSR `sstateen3', needs `smstateen' extension -.*Warning: invalid CSR `sstateen3', needs `smstateen' extension +.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension +.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension .*Warning: invalid CSR `hstateen0', needs `h' extension -.*Warning: invalid CSR `hstateen0', needs `smstateen' extension +.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension .*Warning: invalid CSR `hstateen0', needs `h' extension -.*Warning: invalid CSR `hstateen0', needs `smstateen' extension +.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension .*Warning: invalid CSR `hstateen1', needs `h' extension -.*Warning: invalid CSR `hstateen1', needs `smstateen' extension +.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension .*Warning: invalid CSR `hstateen1', needs `h' extension -.*Warning: invalid CSR `hstateen1', needs `smstateen' extension +.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension .*Warning: invalid CSR `hstateen2', needs `h' extension -.*Warning: invalid CSR `hstateen2', needs `smstateen' extension +.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension .*Warning: invalid CSR `hstateen2', needs `h' extension -.*Warning: invalid CSR `hstateen2', needs `smstateen' extension +.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension .*Warning: invalid CSR `hstateen3', needs `h' extension -.*Warning: invalid CSR `hstateen3', needs `smstateen' extension +.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension .*Warning: invalid CSR `hstateen3', needs `h' extension -.*Warning: invalid CSR `hstateen3', needs `smstateen' extension +.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension .*Warning: invalid CSR `mstateen0h', needs rv32i extension .*Warning: invalid CSR `mstateen0h', needs `smstateen' extension .*Warning: invalid CSR `mstateen0h', needs rv32i extension @@ -511,28 +511,28 @@ .*Warning: invalid CSR `mstateen3h', needs `smstateen' extension .*Warning: invalid CSR `hstateen0h', needs rv32i extension .*Warning: invalid CSR `hstateen0h', needs `h' extension -.*Warning: invalid CSR `hstateen0h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen0h', needs rv32i extension .*Warning: invalid CSR `hstateen0h', needs `h' extension -.*Warning: invalid CSR `hstateen0h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen1h', needs rv32i extension .*Warning: invalid CSR `hstateen1h', needs `h' extension -.*Warning: invalid CSR `hstateen1h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen1h', needs rv32i extension .*Warning: invalid CSR `hstateen1h', needs `h' extension -.*Warning: invalid CSR `hstateen1h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen2h', needs rv32i extension .*Warning: invalid CSR `hstateen2h', needs `h' extension -.*Warning: invalid CSR `hstateen2h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen2h', needs rv32i extension .*Warning: invalid CSR `hstateen2h', needs `h' extension -.*Warning: invalid CSR `hstateen2h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen3h', needs rv32i extension .*Warning: invalid CSR `hstateen3h', needs `h' extension -.*Warning: invalid CSR `hstateen3h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension .*Warning: invalid CSR `hstateen3h', needs rv32i extension .*Warning: invalid CSR `hstateen3h', needs `h' extension -.*Warning: invalid CSR `hstateen3h', needs `smstateen' extension +.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension .*Warning: invalid CSR `scountovf', needs `sscofpmf' extension .*Warning: invalid CSR `scountovf', needs `sscofpmf' extension .*Warning: read-only CSR is written `csrw scountovf,a1' diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s index 128aeb83a04..397fe0b9eb8 100644 --- a/gas/testsuite/gas/riscv/csr.s +++ b/gas/testsuite/gas/riscv/csr.s @@ -337,7 +337,7 @@ csr vsip csr vsatp - # Smstateen extension + # Smstateen/Ssstateen extensions csr mstateen0 csr mstateen1 csr mstateen2 diff --git a/gas/testsuite/gas/riscv/smstateen-csr-s.d b/gas/testsuite/gas/riscv/smstateen-csr-s.d new file mode 100644 index 00000000000..44b6dd66373 --- /dev/null +++ b/gas/testsuite/gas/riscv/smstateen-csr-s.d @@ -0,0 +1,22 @@ +#as: -march=rv32ih_smstateen -mcsr-check -mpriv-spec=1.12 +#source: ssstateen-csr.s +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+10c02573[ ]+csrr[ ]+a0,sstateen0 +[ ]+[0-9a-f]+:[ ]+10d02573[ ]+csrr[ ]+a0,sstateen1 +[ ]+[0-9a-f]+:[ ]+10e02573[ ]+csrr[ ]+a0,sstateen2 +[ ]+[0-9a-f]+:[ ]+10f02573[ ]+csrr[ ]+a0,sstateen3 +[ ]+[0-9a-f]+:[ ]+60c02573[ ]+csrr[ ]+a0,hstateen0 +[ ]+[0-9a-f]+:[ ]+60d02573[ ]+csrr[ ]+a0,hstateen1 +[ ]+[0-9a-f]+:[ ]+60e02573[ ]+csrr[ ]+a0,hstateen2 +[ ]+[0-9a-f]+:[ ]+60f02573[ ]+csrr[ ]+a0,hstateen3 +[ ]+[0-9a-f]+:[ ]+61c02573[ ]+csrr[ ]+a0,hstateen0h +[ ]+[0-9a-f]+:[ ]+61d02573[ ]+csrr[ ]+a0,hstateen1h +[ ]+[0-9a-f]+:[ ]+61e02573[ ]+csrr[ ]+a0,hstateen2h +[ ]+[0-9a-f]+:[ ]+61f02573[ ]+csrr[ ]+a0,hstateen3h diff --git a/gas/testsuite/gas/riscv/ssstateen-csr.d b/gas/testsuite/gas/riscv/ssstateen-csr.d new file mode 100644 index 00000000000..29b286a6353 --- /dev/null +++ b/gas/testsuite/gas/riscv/ssstateen-csr.d @@ -0,0 +1,22 @@ +#as: -march=rv32ih_ssstateen -mcsr-check -mpriv-spec=1.12 +#source: ssstateen-csr.s +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+10c02573[ ]+csrr[ ]+a0,sstateen0 +[ ]+[0-9a-f]+:[ ]+10d02573[ ]+csrr[ ]+a0,sstateen1 +[ ]+[0-9a-f]+:[ ]+10e02573[ ]+csrr[ ]+a0,sstateen2 +[ ]+[0-9a-f]+:[ ]+10f02573[ ]+csrr[ ]+a0,sstateen3 +[ ]+[0-9a-f]+:[ ]+60c02573[ ]+csrr[ ]+a0,hstateen0 +[ ]+[0-9a-f]+:[ ]+60d02573[ ]+csrr[ ]+a0,hstateen1 +[ ]+[0-9a-f]+:[ ]+60e02573[ ]+csrr[ ]+a0,hstateen2 +[ ]+[0-9a-f]+:[ ]+60f02573[ ]+csrr[ ]+a0,hstateen3 +[ ]+[0-9a-f]+:[ ]+61c02573[ ]+csrr[ ]+a0,hstateen0h +[ ]+[0-9a-f]+:[ ]+61d02573[ ]+csrr[ ]+a0,hstateen1h +[ ]+[0-9a-f]+:[ ]+61e02573[ ]+csrr[ ]+a0,hstateen2h +[ ]+[0-9a-f]+:[ ]+61f02573[ ]+csrr[ ]+a0,hstateen3h diff --git a/gas/testsuite/gas/riscv/ssstateen-csr.s b/gas/testsuite/gas/riscv/ssstateen-csr.s new file mode 100644 index 00000000000..82707a4625b --- /dev/null +++ b/gas/testsuite/gas/riscv/ssstateen-csr.s @@ -0,0 +1,13 @@ +target: + csrr a0, sstateen0 + csrr a0, sstateen1 + csrr a0, sstateen2 + csrr a0, sstateen3 + csrr a0, hstateen0 + csrr a0, hstateen1 + csrr a0, hstateen2 + csrr a0, hstateen3 + csrr a0, hstateen0h + csrr a0, hstateen1h + csrr a0, hstateen2h + csrr a0, hstateen3h diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index e40592159cd..982a732bcd2 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -3488,27 +3488,27 @@ DECLARE_CSR(vscause, CSR_VSCAUSE, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_C DECLARE_CSR(vstval, CSR_VSTVAL, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(vsip, CSR_VSIP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(vsatp, CSR_VSATP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) -/* Smstateen extension */ +/* Smstateen/Ssstateen extensions. */ DECLARE_CSR(mstateen0, CSR_MSTATEEN0, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mstateen1, CSR_MSTATEEN1, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mstateen2, CSR_MSTATEEN2, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mstateen3, CSR_MSTATEEN3, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) -DECLARE_CSR(sstateen0, CSR_SSTATEEN0, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) -DECLARE_CSR(sstateen1, CSR_SSTATEEN1, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) -DECLARE_CSR(sstateen2, CSR_SSTATEEN2, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) -DECLARE_CSR(sstateen3, CSR_SSTATEEN3, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) -DECLARE_CSR(hstateen0, CSR_HSTATEEN0, CSR_CLASS_SMSTATEEN_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) -DECLARE_CSR(hstateen1, CSR_HSTATEEN1, CSR_CLASS_SMSTATEEN_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) -DECLARE_CSR(hstateen2, CSR_HSTATEEN2, CSR_CLASS_SMSTATEEN_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) -DECLARE_CSR(hstateen3, CSR_HSTATEEN3, CSR_CLASS_SMSTATEEN_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(sstateen0, CSR_SSTATEEN0, CSR_CLASS_SSSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(sstateen1, CSR_SSTATEEN1, CSR_CLASS_SSSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(sstateen2, CSR_SSTATEEN2, CSR_CLASS_SSSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(sstateen3, CSR_SSTATEEN3, CSR_CLASS_SSSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hstateen0, CSR_HSTATEEN0, CSR_CLASS_SSSTATEEN_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hstateen1, CSR_HSTATEEN1, CSR_CLASS_SSSTATEEN_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hstateen2, CSR_HSTATEEN2, CSR_CLASS_SSSTATEEN_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hstateen3, CSR_HSTATEEN3, CSR_CLASS_SSSTATEEN_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mstateen0h, CSR_MSTATEEN0H, CSR_CLASS_SMSTATEEN_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mstateen1h, CSR_MSTATEEN1H, CSR_CLASS_SMSTATEEN_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mstateen2h, CSR_MSTATEEN2H, CSR_CLASS_SMSTATEEN_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mstateen3h, CSR_MSTATEEN3H, CSR_CLASS_SMSTATEEN_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) -DECLARE_CSR(hstateen0h, CSR_HSTATEEN0H, CSR_CLASS_SMSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) -DECLARE_CSR(hstateen1h, CSR_HSTATEEN1H, CSR_CLASS_SMSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) -DECLARE_CSR(hstateen2h, CSR_HSTATEEN2H, CSR_CLASS_SMSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) -DECLARE_CSR(hstateen3h, CSR_HSTATEEN3H, CSR_CLASS_SMSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hstateen0h, CSR_HSTATEEN0H, CSR_CLASS_SSSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hstateen1h, CSR_HSTATEEN1H, CSR_CLASS_SSSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hstateen2h, CSR_HSTATEEN2H, CSR_CLASS_SSSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hstateen3h, CSR_HSTATEEN3H, CSR_CLASS_SSSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) /* Sscofpmf extension */ DECLARE_CSR(scountovf, CSR_SCOUNTOVF, CSR_CLASS_SSCOFPMF, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mhpmevent3h, CSR_MHPMEVENT3H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) -- 2.37.2 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [REVIEW ONLY 2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions 2022-11-03 12:26 [REVIEW ONLY 0/2] NEAR RATIFICATION RISC-V: Extensions from the RISC-V Profiles Tsukasa OI 2022-11-03 12:26 ` [REVIEW ONLY 1/2] NEAR-RATIFICATION RISC-V: Add 'Ssstateen' extension and its CSRs Tsukasa OI @ 2022-11-03 12:26 ` Tsukasa OI 2022-11-03 13:11 ` [REVIEW ONLY 0/2] NEAR RATIFICATION RISC-V: Extensions from the RISC-V Profiles Nelson Chu 2023-01-30 6:35 ` [PATCH v2 0/1] " Tsukasa OI 3 siblings, 0 replies; 17+ messages in thread From: Tsukasa OI @ 2022-11-03 12:26 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils [DO NOT MERGE] RISC-V Profiles are frozen but -- from my view -- this document will still change in some way. Meanwhile, this patch should not be merged upstream. This commit uses tentative version 1.0 (as there are no versions). RISC-V Profiles document defines number of "extensions" that indicate certain platform properties/capabilities just like 'Zkt' extension from the RISC-V cryptography extensions. This commit defines 19 platform property/capability extensions as defined in the RISC-V Profiles documentation. The version number is tentatively set to 1.0. The only exception: 'Ssstateen' extension is defined separately because it defines a subset (supervisor/hypervisor view) of the 'Smstateen' extension. This is based on the latest version of RISC-V Profiles (version 0.9-draft): <https://github.com/riscv/riscv-profiles/commit/226b7f643067b29abc6723fac60d5f6d3f9eb901> [Definition] "Main memory regions": memory regions with both the cacheability and coherence PMAs. [New Unprivileged Extensions] 1. 'Ziccif' "Main memory regions" support instruction fetch and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN, XLEN) are atomic. 2. 'Ziccrse' "Main memory regions" provide the eventual success guarantee for LR/SC sequence. 3. 'Ziccamoa' "Main memory regions" support all AMO operations including atomic swap, logical and arithmetic operations. 4. 'Za64rs' For LR/SC instructions, reservation sets are contiguous, naturally aligned and at most 64-bytes in size. 5. 'Za128rs' Likewise, but reservation sets are at most 128-bytes in size. 6. 'Zicclsm' Misaligned loads / stores to "main memory regions" are supported. Those include both regular scalar and vector access but does not include AMOs and other specialized forms of memory access. 7. 'Zic64b' Cache blocks are (exactly) 64-bytes in size and naturally aligned. [New Privileged Extensions] 1. 'Svbare' "satp" mode Bare is supported. 2. 'Ssptead' Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear. 3. 'Ssccptr' "Main memory regions" support hardware page-table reads. 4. 'Sstvecd' "stvec" mode Direct is supported. When "stvec" mode is Direct, "stvec.BASE" is capable of holding any valid 4-byte aligned address. 5. 'Sstvala' "stval" is always written with a nonzero value whenever possible as specified in the Privileged Architecture documentation (version 20211203: see section 4.1.9). 6. 'Ssu64xl' "sstatus.UXL"=64 [sic]. 7. 'Shcounterenw' For any "hpmcounter" that is not read-only zero, the corresponding bit in "hcounteren" is writable. 8. 'Shvstvala' Similar to 'Sstvala' but the same rule applies to "vstval". 9. 'Shtvala' "htval" is written with the faulting guest physical address as long as permitted by the ISA (a bit similar to 'Sstvala' and 'Shvstvala'). 10. 'Shvstvecd' Similar to 'Sstvecd' but the same rule applies to "vstvec". 11. 'Shvsatpa' All translation modes supported in "satp" are also supported in "vsatp". 12. 'Shgatpa' For each supported virtual memory scheme SvNN supported in "satp", the corresponding "hgatp" SvNNx4 mode is supported. The "hgatp" mode Bare is also supported. [Implications] (Due to reservation set size constraints) - 'Za64rs' -> 'Za128rs' (Due to the fact that a privileged "extension" directly refers a CSR) - 'Svbare' -> 'Zicsr' - 'Sstvecd' -> 'Zicsr' - 'Sstvala' -> 'Zicsr' - 'Ssu64xl' -> 'Zicsr' (Due to the fact that a privileged "extension" indirectly depends on CSRs) - 'Ssptead' -> 'Zicsr' - 'Ssccptr' -> 'Zicsr' (Due to the fact that a privileged "extension" is a hypervisor property) - 'Shcounterenw' -> 'H' - 'Shvstvala' -> 'H' - 'Shtvala' -> 'H' - 'Shvstvecd' -> 'H' - 'Shvsatpa' -> 'H' - 'Shgatpa' -> 'H' bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add 13 implication rules. (riscv_supported_std_z_ext) Add 7 property/capability extensions. (riscv_supported_std_s_ext) Add 12 property/capability extensions. --- bfd/elfxx-riscv.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 781b57cbd98..64811a138a3 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1047,7 +1047,6 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"g", "zicsr", check_implicit_always}, {"g", "zifencei", check_implicit_always}, {"m", "zmmul", check_implicit_always}, - {"h", "zicsr", check_implicit_always}, {"q", "d", check_implicit_always}, {"v", "d", check_implicit_always}, {"v", "zve64d", check_implicit_always}, @@ -1083,6 +1082,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zhinx", "zhinxmin", check_implicit_always}, {"zhinxmin", "zfinx", check_implicit_always}, {"zfinx", "zicsr", check_implicit_always}, + {"za64rs", "za128rs", check_implicit_always}, {"zk", "zkn", check_implicit_always}, {"zk", "zkr", check_implicit_always}, {"zk", "zkt", check_implicit_always}, @@ -1099,9 +1099,22 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zks", "zksh", check_implicit_always}, {"smstateen", "ssstateen", check_implicit_always}, {"smepmp", "zicsr", check_implicit_always}, + {"shcounterenw", "h", check_implicit_always}, + {"shgatpa", "h", check_implicit_always}, + {"shtvala", "h", check_implicit_always}, + {"shvsatpa", "h", check_implicit_always}, + {"shvstvala", "h", check_implicit_always}, + {"shvstvecd", "h", check_implicit_always}, + {"h", "zicsr", check_implicit_always}, + {"ssccptr", "zicsr", check_implicit_always}, {"sscofpmf", "zicsr", check_implicit_always}, + {"ssptead", "zicsr", check_implicit_always}, {"ssstateen", "zicsr", check_implicit_always}, {"sstc", "zicsr", check_implicit_always}, + {"sstvala", "zicsr", check_implicit_always}, + {"sstvecd", "zicsr", check_implicit_always}, + {"ssu64xl", "zicsr", check_implicit_always}, + {"svbare", "zicsr", check_implicit_always}, {NULL, NULL, NULL} }; @@ -1159,6 +1172,11 @@ static struct riscv_supported_ext riscv_supported_std_ext[] = static struct riscv_supported_ext riscv_supported_std_z_ext[] = { + {"zic64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ziccamoa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ziccif", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicclsm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ziccrse", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -1168,6 +1186,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -1217,11 +1237,23 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = static struct riscv_supported_ext riscv_supported_std_s_ext[] = { + {"shcounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shgatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shtvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shvsatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shvstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shvstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssptead", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssu64xl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svbare", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svpbmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -- 2.37.2 ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [REVIEW ONLY 0/2] NEAR RATIFICATION RISC-V: Extensions from the RISC-V Profiles 2022-11-03 12:26 [REVIEW ONLY 0/2] NEAR RATIFICATION RISC-V: Extensions from the RISC-V Profiles Tsukasa OI 2022-11-03 12:26 ` [REVIEW ONLY 1/2] NEAR-RATIFICATION RISC-V: Add 'Ssstateen' extension and its CSRs Tsukasa OI 2022-11-03 12:26 ` [REVIEW ONLY 2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions Tsukasa OI @ 2022-11-03 13:11 ` Nelson Chu 2022-11-03 13:20 ` Tsukasa OI 2022-11-19 2:56 ` Tsukasa OI 2023-01-30 6:35 ` [PATCH v2 0/1] " Tsukasa OI 3 siblings, 2 replies; 17+ messages in thread From: Nelson Chu @ 2022-11-03 13:11 UTC (permalink / raw) To: Tsukasa OI; +Cc: Kito Cheng, Palmer Dabbelt, binutils On Thu, Nov 3, 2022 at 8:26 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote: > > Hello, > > This patchset implements all extensions from RISC-V Profiles (but not > profile itself). I'm not sure whether this patchset helps someone > implementing RISC-V Profiles but I hope so. > > Thanks, > Tsukasa > > > > > Tsukasa OI (2): > NEAR-RATIFICATION RISC-V: Add 'Ssstateen' extension and its CSRs Looks good. > NEAR-RATIFICATION RISC-V: Add platform property/capability extensions If we just need to recognize them in assembler, then it looks good. Thanks for arranging these bunch of extensions before everything gets messy... Generally, since they are frozen, we have good reason to commit them to the mainline. But if you prefer to wait until they are ratified, then that's also work to me, I believe you know when will be the best time, so please commit at that time. Thanks Nelson Nelson > bfd/elfxx-riscv.c | 38 +++++++++++++++- > gas/config/tc-riscv.c | 20 +++++---- > gas/testsuite/gas/riscv/csr-version-1p10.l | 48 ++++++++++----------- > gas/testsuite/gas/riscv/csr-version-1p11.l | 48 ++++++++++----------- > gas/testsuite/gas/riscv/csr-version-1p12.l | 48 ++++++++++----------- > gas/testsuite/gas/riscv/csr-version-1p9p1.l | 48 ++++++++++----------- > gas/testsuite/gas/riscv/csr.s | 2 +- > gas/testsuite/gas/riscv/smstateen-csr-s.d | 22 ++++++++++ > gas/testsuite/gas/riscv/ssstateen-csr.d | 22 ++++++++++ > gas/testsuite/gas/riscv/ssstateen-csr.s | 13 ++++++ > include/opcode/riscv-opc.h | 26 +++++------ > 11 files changed, 215 insertions(+), 120 deletions(-) > create mode 100644 gas/testsuite/gas/riscv/smstateen-csr-s.d > create mode 100644 gas/testsuite/gas/riscv/ssstateen-csr.d > create mode 100644 gas/testsuite/gas/riscv/ssstateen-csr.s > > > base-commit: ae1c45ead6b60ef0fd338bbeb6a4c5e5808c6e6a > -- > 2.37.2 > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [REVIEW ONLY 0/2] NEAR RATIFICATION RISC-V: Extensions from the RISC-V Profiles 2022-11-03 13:11 ` [REVIEW ONLY 0/2] NEAR RATIFICATION RISC-V: Extensions from the RISC-V Profiles Nelson Chu @ 2022-11-03 13:20 ` Tsukasa OI 2022-11-19 2:56 ` Tsukasa OI 1 sibling, 0 replies; 17+ messages in thread From: Tsukasa OI @ 2022-11-03 13:20 UTC (permalink / raw) To: Nelson Chu; +Cc: binutils On 2022/11/03 22:11, Nelson Chu wrote: > On Thu, Nov 3, 2022 at 8:26 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote: >> >> Hello, >> >> This patchset implements all extensions from RISC-V Profiles (but not >> profile itself). I'm not sure whether this patchset helps someone >> implementing RISC-V Profiles but I hope so. >> >> Thanks, >> Tsukasa >> >> >> >> >> Tsukasa OI (2): >> NEAR-RATIFICATION RISC-V: Add 'Ssstateen' extension and its CSRs > > Looks good. > >> NEAR-RATIFICATION RISC-V: Add platform property/capability extensions > > If we just need to recognize them in assembler, then it looks good. > Thanks for arranging these bunch of extensions before everything gets > messy... Generally, since they are frozen, we have good reason to > commit them to the mainline. But if you prefer to wait until they are > ratified, then that's also work to me, I believe you know when will be > the best time, so please commit at that time. Thanks for the review! I want to clarify that whether those names are actually extensions and I just pushed a pull request for this (related to PATCH 2/2): <https://github.com/riscv/riscv-profiles/pull/76> I will push this depending on the resolution of this pull request. Thanks, Tsukasa > > Thanks > Nelson > > Nelson > >> bfd/elfxx-riscv.c | 38 +++++++++++++++- >> gas/config/tc-riscv.c | 20 +++++---- >> gas/testsuite/gas/riscv/csr-version-1p10.l | 48 ++++++++++----------- >> gas/testsuite/gas/riscv/csr-version-1p11.l | 48 ++++++++++----------- >> gas/testsuite/gas/riscv/csr-version-1p12.l | 48 ++++++++++----------- >> gas/testsuite/gas/riscv/csr-version-1p9p1.l | 48 ++++++++++----------- >> gas/testsuite/gas/riscv/csr.s | 2 +- >> gas/testsuite/gas/riscv/smstateen-csr-s.d | 22 ++++++++++ >> gas/testsuite/gas/riscv/ssstateen-csr.d | 22 ++++++++++ >> gas/testsuite/gas/riscv/ssstateen-csr.s | 13 ++++++ >> include/opcode/riscv-opc.h | 26 +++++------ >> 11 files changed, 215 insertions(+), 120 deletions(-) >> create mode 100644 gas/testsuite/gas/riscv/smstateen-csr-s.d >> create mode 100644 gas/testsuite/gas/riscv/ssstateen-csr.d >> create mode 100644 gas/testsuite/gas/riscv/ssstateen-csr.s >> >> >> base-commit: ae1c45ead6b60ef0fd338bbeb6a4c5e5808c6e6a >> -- >> 2.37.2 >> > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [REVIEW ONLY 0/2] NEAR RATIFICATION RISC-V: Extensions from the RISC-V Profiles 2022-11-03 13:11 ` [REVIEW ONLY 0/2] NEAR RATIFICATION RISC-V: Extensions from the RISC-V Profiles Nelson Chu 2022-11-03 13:20 ` Tsukasa OI @ 2022-11-19 2:56 ` Tsukasa OI 1 sibling, 0 replies; 17+ messages in thread From: Tsukasa OI @ 2022-11-19 2:56 UTC (permalink / raw) To: Nelson Chu; +Cc: binutils On 2022/11/03 22:11, Nelson Chu wrote: > On Thu, Nov 3, 2022 at 8:26 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote: >> >> Hello, >> >> This patchset implements all extensions from RISC-V Profiles (but not >> profile itself). I'm not sure whether this patchset helps someone >> implementing RISC-V Profiles but I hope so. >> >> Thanks, >> Tsukasa >> >> >> >> >> Tsukasa OI (2): >> NEAR-RATIFICATION RISC-V: Add 'Ssstateen' extension and its CSRs > > Looks good. I will commit this (PATCH 1/2) soon. > >> NEAR-RATIFICATION RISC-V: Add platform property/capability extensions > > If we just need to recognize them in assembler, then it looks good. > Thanks for arranging these bunch of extensions before everything gets > messy... Generally, since they are frozen, we have good reason to > commit them to the mainline. But if you prefer to wait until they are > ratified, then that's also work to me, I believe you know when will be > the best time, so please commit at that time. Some pointed out that an extension name 'Ssptead' is no good: https://github.com/riscv/riscv-profiles/issues/81 New name would be 'Svptead'? In any case, I'll wait PATCH 2/2 until... at least this issue is resolved in the main branch in some way. Thanks, Tsukasa > > Thanks > Nelson > > Nelson > >> bfd/elfxx-riscv.c | 38 +++++++++++++++- >> gas/config/tc-riscv.c | 20 +++++---- >> gas/testsuite/gas/riscv/csr-version-1p10.l | 48 ++++++++++----------- >> gas/testsuite/gas/riscv/csr-version-1p11.l | 48 ++++++++++----------- >> gas/testsuite/gas/riscv/csr-version-1p12.l | 48 ++++++++++----------- >> gas/testsuite/gas/riscv/csr-version-1p9p1.l | 48 ++++++++++----------- >> gas/testsuite/gas/riscv/csr.s | 2 +- >> gas/testsuite/gas/riscv/smstateen-csr-s.d | 22 ++++++++++ >> gas/testsuite/gas/riscv/ssstateen-csr.d | 22 ++++++++++ >> gas/testsuite/gas/riscv/ssstateen-csr.s | 13 ++++++ >> include/opcode/riscv-opc.h | 26 +++++------ >> 11 files changed, 215 insertions(+), 120 deletions(-) >> create mode 100644 gas/testsuite/gas/riscv/smstateen-csr-s.d >> create mode 100644 gas/testsuite/gas/riscv/ssstateen-csr.d >> create mode 100644 gas/testsuite/gas/riscv/ssstateen-csr.s >> >> >> base-commit: ae1c45ead6b60ef0fd338bbeb6a4c5e5808c6e6a >> -- >> 2.37.2 >> > ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 0/1] RISC-V: Extensions from the RISC-V Profiles 2022-11-03 12:26 [REVIEW ONLY 0/2] NEAR RATIFICATION RISC-V: Extensions from the RISC-V Profiles Tsukasa OI ` (2 preceding siblings ...) 2022-11-03 13:11 ` [REVIEW ONLY 0/2] NEAR RATIFICATION RISC-V: Extensions from the RISC-V Profiles Nelson Chu @ 2023-01-30 6:35 ` Tsukasa OI 2023-01-30 6:35 ` [PATCH v2 1/1] RISC-V: Add platform property/capability extensions Tsukasa OI ` (2 more replies) 3 siblings, 3 replies; 17+ messages in thread From: Tsukasa OI @ 2023-01-30 6:35 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils Hello, First, to whom concerned (especially, to Nelson): I quit the job two weeks ago due to my poor health conditions and will take some time for recuperation. Because of this (despite that I've seen all your reviews and responses), I will not be able to respond properly (and in a responsible manner) until... probably April or May. Before I get busier, I will submit this one because the RISC-V Profiles documentation is now updated (version 0.9.2, the release for TSC recommendation to ratify) and this time, it's very unlikely to change now (I found a typo in this but at least it's stable enough to implement). c.f. <https://github.com/riscv/riscv-profiles/releases/tag/v0.9.2> On PATCH v1, though the base specification (version 0.9-draft) was Frozen, some changes are expected and I submitted it with DO NOT MERGE status. The change actually happened and an extension name has changed ('Ssptead' -> 'Svptead' -> 'Svade'). This time, I think it's safe to upstream new extension names. Sincerely, Tsukasa Tsukasa OI (1): RISC-V: Add platform property/capability extensions bfd/elfxx-riscv.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) base-commit: 594a01c217143dce2f1f3181bcca4047b4a44107 -- 2.39.0 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 1/1] RISC-V: Add platform property/capability extensions 2023-01-30 6:35 ` [PATCH v2 0/1] " Tsukasa OI @ 2023-01-30 6:35 ` Tsukasa OI 2023-01-30 7:11 ` [PATCH v3 0/1] RISC-V: Extensions from the RISC-V Profiles Tsukasa OI 2023-01-31 4:46 ` [PATCH v2 0/1] RISC-V: Extensions from the RISC-V Profiles Nelson Chu 2 siblings, 0 replies; 17+ messages in thread From: Tsukasa OI @ 2023-01-30 6:35 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils From: Tsukasa OI <research_trasio@irq.a4lg.com> RISC-V Profiles document defines number of "extensions" that indicate certain platform properties/capabilities just like 'Zkt' extension from the RISC-V cryptography extensions. This commit defines 19 platform property/capability extensions as defined in the RISC-V Profiles documentation. The version number is set to 1.0. The only exception: 'Ssstateen' extension is defined separately because it defines a subset (supervisor/hypervisor view) of the 'Smstateen' extension. This is based on the latest version of RISC-V Profiles (version 0.9.2, the release for TSC recommendation to ratify): <https://github.com/riscv/riscv-profiles/releases/tag/v0.9.2> [Definition] "Main memory regions": Main memory regions (in contrast to I/O or vacant memory regions) with both the cacheability and coherence PMAs. [New Unprivileged Extensions] 1. 'Ziccif' "Main memory regions" support instruction fetch and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN, XLEN) are atomic. 2. 'Ziccrse' "Main memory regions" provide the eventual success guarantee for LR/SC sequence (RsrvEventual). 3. 'Ziccamoa' "Main memory regions" support all currently-defined AMO operations including swap, logical and arithmetic operations (AMOArithmetic). 4. 'Za64rs' For LR/SC instructions, reservation sets are contiguous, naturally aligned and at most 64-bytes in size. 5. 'Za128rs' Likewise, but reservation sets are at most 128-bytes in size. 6. 'Zicclsm' Misaligned loads / stores to "main memory regions" are supported. Those include both regular scalar and vector accesses but does not include AMOs and other specialized forms of memory access. 7. 'Zic64b' Cache blocks are (exactly) 64-bytes in size and naturally aligned. [New Privileged Extensions] 1. 'Svbare' "satp" mode Bare is supported. 2. 'Svade' Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear. 3. 'Ssccptr' "Main memory regions" support hardware page-table reads. 4. 'Sstvecd' "stvec" mode Direct is supported. When "stvec" mode is Direct, "stvec.BASE" is capable of holding any valid 4-byte aligned address. 5. 'Sstvala' "stval" is always written with a nonzero value whenever possible as specified in the Privileged Architecture documentation (version 20211203: see section 4.1.9). 6. 'Ssu64xl' "sstatus.UXL" is capable of holding the value 0b10 (UXLEN==64 is supported). 7. 'Shcounterenw' For any "hpmcounter" that is not read-only zero, the corresponding bit in "hcounteren" is writable. 8. 'Shvstvala' Similar to 'Sstvala' but the same rule applies to "vstval". 9. 'Shtvala' "htval" is written with the faulting guest physical address as long as permitted by the ISA (a bit similar to 'Sstvala' and 'Shvstvala'). 10. 'Shvstvecd' Similar to 'Sstvecd' but the same rule applies to "vstvec". 11. 'Shvsatpa' All translation modes supported in "satp" are also supported in "vsatp". 12. 'Shgatpa' For each supported virtual memory scheme SvNN supported in "satp", the corresponding "hgatp" SvNNx4 mode is supported. The "hgatp" mode Bare is also supported. [Implications] (Due to reservation set size constraints) - 'Za64rs' -> 'Za128rs' (Due to the fact that a privileged "extension" directly refers a CSR) - 'Svbare' -> 'Zicsr' - 'Sstvecd' -> 'Zicsr' - 'Sstvala' -> 'Zicsr' - 'Ssu64xl' -> 'Zicsr' (Due to the fact that a privileged "extension" indirectly depends on CSRs) - 'Svade' -> 'Zicsr' (Due to the fact that a privileged "extension" is a hypervisor property) - 'Shcounterenw' -> 'H' - 'Shvstvala' -> 'H' - 'Shtvala' -> 'H' - 'Shvstvecd' -> 'H' - 'Shvsatpa' -> 'H' - 'Shgatpa' -> 'H' bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add 12 implication rules. (riscv_supported_std_z_ext) Add 7 property/capability extensions. (riscv_supported_std_s_ext) Add 12 property/capability extensions. --- bfd/elfxx-riscv.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 19391d94e305..6d1c913fb183 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1051,7 +1051,6 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"g", "zicsr", check_implicit_always}, {"g", "zifencei", check_implicit_always}, {"m", "zmmul", check_implicit_always}, - {"h", "zicsr", check_implicit_always}, {"q", "d", check_implicit_always}, {"v", "d", check_implicit_always}, {"v", "zve64d", check_implicit_always}, @@ -1087,6 +1086,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zhinx", "zhinxmin", check_implicit_always}, {"zhinxmin", "zfinx", check_implicit_always}, {"zfinx", "zicsr", check_implicit_always}, + {"za64rs", "za128rs", check_implicit_always}, {"zk", "zkn", check_implicit_always}, {"zk", "zkr", check_implicit_always}, {"zk", "zkt", check_implicit_always}, @@ -1104,10 +1104,22 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"smaia", "ssaia", check_implicit_always}, {"smstateen", "ssstateen", check_implicit_always}, {"smepmp", "zicsr", check_implicit_always}, + {"shcounterenw", "h", check_implicit_always}, + {"shgatpa", "h", check_implicit_always}, + {"shtvala", "h", check_implicit_always}, + {"shvsatpa", "h", check_implicit_always}, + {"shvstvala", "h", check_implicit_always}, + {"shvstvecd", "h", check_implicit_always}, + {"h", "zicsr", check_implicit_always}, {"ssaia", "zicsr", check_implicit_always}, {"sscofpmf", "zicsr", check_implicit_always}, {"ssstateen", "zicsr", check_implicit_always}, {"sstc", "zicsr", check_implicit_always}, + {"sstvala", "zicsr", check_implicit_always}, + {"sstvecd", "zicsr", check_implicit_always}, + {"ssu64xl", "zicsr", check_implicit_always}, + {"svade", "zicsr", check_implicit_always}, + {"svbare", "zicsr", check_implicit_always}, {NULL, NULL, NULL} }; @@ -1165,6 +1177,11 @@ static struct riscv_supported_ext riscv_supported_std_ext[] = static struct riscv_supported_ext riscv_supported_std_z_ext[] = { + {"zic64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ziccamoa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ziccif", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicclsm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ziccrse", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -1174,6 +1191,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -1227,11 +1246,25 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shcounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shgatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shtvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shvsatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shvstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shvstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssu64xl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svbare", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svade", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svpbmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; -- 2.39.0 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 0/1] RISC-V: Extensions from the RISC-V Profiles 2023-01-30 6:35 ` [PATCH v2 0/1] " Tsukasa OI 2023-01-30 6:35 ` [PATCH v2 1/1] RISC-V: Add platform property/capability extensions Tsukasa OI @ 2023-01-30 7:11 ` Tsukasa OI 2023-01-30 7:11 ` [PATCH v3 1/1] RISC-V: Add platform property/capability extensions Tsukasa OI 2023-07-26 0:05 ` [PATCH v4 0/1] RISC-V: Extensions from the RISC-V Profiles Tsukasa OI 2023-01-31 4:46 ` [PATCH v2 0/1] RISC-V: Extensions from the RISC-V Profiles Nelson Chu 2 siblings, 2 replies; 17+ messages in thread From: Tsukasa OI @ 2023-01-30 7:11 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils Oops, PATCH v2 has some minor mistakes. [Changes: v2 -> v3] 1. After AIA is upstreamed, I haven't done tidying up with riscv_supported_std_s_ext with my rebased branch. That made location of 'Ssaia' a bit out of place. PATCH v3 fixes this. 2. After version 0.8, the new extension 'Sscounterenw' is added but I missed that. PATCH v3 adds support for this new extension correctly. 3. I made minor changes to ChangeLog part of the commit message (I moved 'H' -> 'Zicsr' dependency for a reason but I didn't mentioned in the ChangeLog). Thanks, Tsukasa Tsukasa OI (1): RISC-V: Add platform property/capability extensions bfd/elfxx-riscv.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) base-commit: 594a01c217143dce2f1f3181bcca4047b4a44107 -- 2.39.1 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 1/1] RISC-V: Add platform property/capability extensions 2023-01-30 7:11 ` [PATCH v3 0/1] RISC-V: Extensions from the RISC-V Profiles Tsukasa OI @ 2023-01-30 7:11 ` Tsukasa OI 2023-07-26 0:05 ` [PATCH v4 0/1] RISC-V: Extensions from the RISC-V Profiles Tsukasa OI 1 sibling, 0 replies; 17+ messages in thread From: Tsukasa OI @ 2023-01-30 7:11 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils From: Tsukasa OI <research_trasio@irq.a4lg.com> RISC-V Profiles document defines number of "extensions" that indicate certain platform properties/capabilities just like 'Zkt' extension from the RISC-V cryptography extensions. This commit defines 20 platform property/capability extensions as defined in the RISC-V Profiles documentation. The version number is set to 1.0. The only exception: 'Ssstateen' extension is defined separately because it defines a subset (supervisor/hypervisor view) of the 'Smstateen' extension. This is based on the latest version of RISC-V Profiles (version 0.9.2, the release for TSC recommendation to ratify): <https://github.com/riscv/riscv-profiles/releases/tag/v0.9.2> [Definition] "Main memory regions": Main memory regions (in contrast to I/O or vacant memory regions) with both the cacheability and coherence PMAs. [New Unprivileged Extensions] 1. 'Ziccif' "Main memory regions" support instruction fetch and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN, XLEN) are atomic. 2. 'Ziccrse' "Main memory regions" provide the eventual success guarantee for LR/SC sequence (RsrvEventual). 3. 'Ziccamoa' "Main memory regions" support all currently-defined AMO operations including swap, logical and arithmetic operations (AMOArithmetic). 4. 'Za64rs' For LR/SC instructions, reservation sets are contiguous, naturally aligned and at most 64-bytes in size. 5. 'Za128rs' Likewise, but reservation sets are at most 128-bytes in size. 6. 'Zicclsm' Misaligned loads / stores to "main memory regions" are supported. Those include both regular scalar and vector accesses but does not include AMOs and other specialized forms of memory access. 7. 'Zic64b' Cache blocks are (exactly) 64-bytes in size and naturally aligned. [New Privileged Extensions] 1. 'Svbare' "satp" mode Bare is supported. 2. 'Svade' Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear. 3. 'Ssccptr' "Main memory regions" support hardware page-table reads. 4. 'Sstvecd' "stvec" mode Direct is supported. When "stvec" mode is Direct, "stvec.BASE" is capable of holding any valid 4-byte aligned address. 5. 'Sstvala' "stval" is always written with a nonzero value whenever possible as specified in the Privileged Architecture documentation (version 20211203: see section 4.1.9). 6. 'Sscounterenw' For any "hpmcounter" that is not read-only zero, the corresponding bit in "scounteren" is writable. 7. 'Ssu64xl' "sstatus.UXL" is capable of holding the value 0b10 (UXLEN==64 is supported). 8. 'Shcounterenw' For any "hpmcounter" that is not read-only zero, the corresponding bit in "hcounteren" is writable. 9. 'Shvstvala' Similar to 'Sstvala' but the same rule applies to "vstval". 10. 'Shtvala' "htval" is written with the faulting guest physical address as long as permitted by the ISA (a bit similar to 'Sstvala' and 'Shvstvala'). 11. 'Shvstvecd' Similar to 'Sstvecd' but the same rule applies to "vstvec". 12. 'Shvsatpa' All translation modes supported in "satp" are also supported in "vsatp". 13. 'Shgatpa' For each supported virtual memory scheme SvNN supported in "satp", the corresponding "hgatp" SvNNx4 mode is supported. The "hgatp" mode Bare is also supported. [Implications] (Due to reservation set size constraints) - 'Za64rs' -> 'Za128rs' (Due to the fact that a privileged "extension" directly refers a CSR) - 'Svbare' -> 'Zicsr' - 'Sstvecd' -> 'Zicsr' - 'Sstvala' -> 'Zicsr' - 'Sscounterenw' -> 'Zicsr' - 'Ssu64xl' -> 'Zicsr' (Due to the fact that a privileged "extension" indirectly depends on CSRs) - 'Svade' -> 'Zicsr' (Due to the fact that a privileged "extension" is a hypervisor property) - 'Shcounterenw' -> 'H' - 'Shvstvala' -> 'H' - 'Shtvala' -> 'H' - 'Shvstvecd' -> 'H' - 'Shvsatpa' -> 'H' - 'Shgatpa' -> 'H' bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add 13 implication rules. Reorder 'H' for new 'Sh*' extensions. (riscv_supported_std_z_ext) Add 7 property/capability extensions. (riscv_supported_std_s_ext) Add 13 property/capability extensions. --- bfd/elfxx-riscv.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 19391d94e305..19aa9f9ef74f 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1051,7 +1051,6 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"g", "zicsr", check_implicit_always}, {"g", "zifencei", check_implicit_always}, {"m", "zmmul", check_implicit_always}, - {"h", "zicsr", check_implicit_always}, {"q", "d", check_implicit_always}, {"v", "d", check_implicit_always}, {"v", "zve64d", check_implicit_always}, @@ -1087,6 +1086,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zhinx", "zhinxmin", check_implicit_always}, {"zhinxmin", "zfinx", check_implicit_always}, {"zfinx", "zicsr", check_implicit_always}, + {"za64rs", "za128rs", check_implicit_always}, {"zk", "zkn", check_implicit_always}, {"zk", "zkr", check_implicit_always}, {"zk", "zkt", check_implicit_always}, @@ -1104,10 +1104,23 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"smaia", "ssaia", check_implicit_always}, {"smstateen", "ssstateen", check_implicit_always}, {"smepmp", "zicsr", check_implicit_always}, + {"shcounterenw", "h", check_implicit_always}, + {"shgatpa", "h", check_implicit_always}, + {"shtvala", "h", check_implicit_always}, + {"shvsatpa", "h", check_implicit_always}, + {"shvstvala", "h", check_implicit_always}, + {"shvstvecd", "h", check_implicit_always}, + {"h", "zicsr", check_implicit_always}, {"ssaia", "zicsr", check_implicit_always}, {"sscofpmf", "zicsr", check_implicit_always}, + {"sscounterenw", "zicsr", check_implicit_always}, {"ssstateen", "zicsr", check_implicit_always}, {"sstc", "zicsr", check_implicit_always}, + {"sstvala", "zicsr", check_implicit_always}, + {"sstvecd", "zicsr", check_implicit_always}, + {"ssu64xl", "zicsr", check_implicit_always}, + {"svade", "zicsr", check_implicit_always}, + {"svbare", "zicsr", check_implicit_always}, {NULL, NULL, NULL} }; @@ -1165,6 +1178,11 @@ static struct riscv_supported_ext riscv_supported_std_ext[] = static struct riscv_supported_ext riscv_supported_std_z_ext[] = { + {"zic64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ziccamoa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ziccif", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicclsm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ziccrse", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -1174,6 +1192,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -1226,12 +1246,27 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = {"smaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shcounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shgatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shtvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shvsatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shvstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shvstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sscounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssu64xl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svbare", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svade", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svpbmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; -- 2.39.1 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v4 0/1] RISC-V: Extensions from the RISC-V Profiles 2023-01-30 7:11 ` [PATCH v3 0/1] RISC-V: Extensions from the RISC-V Profiles Tsukasa OI 2023-01-30 7:11 ` [PATCH v3 1/1] RISC-V: Add platform property/capability extensions Tsukasa OI @ 2023-07-26 0:05 ` Tsukasa OI 2023-07-26 0:05 ` [PATCH v4 1/1] RISC-V: Add platform property/capability extensions Tsukasa OI 1 sibling, 1 reply; 17+ messages in thread From: Tsukasa OI @ 2023-07-26 0:05 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils This patch (set) adds 7 unprivileged extensions and 13 privileged extensions, all of which denotes certain platform capability / constraint. This is almost a resend of the previous PATCH v3 (in January 2023) but since the RISC-V Profiles specification is now ratified, it's much safer to merge. [Changes: v2 -> v3] 1. After AIA is upstreamed, I haven't done tidying up with riscv_supported_std_s_ext with my rebased branch. That made location of 'Ssaia' a bit out of place. PATCH v3 fixes this. 2. After version 0.8, the new extension 'Sscounterenw' is added but I missed that. PATCH v3 adds support for this new extension correctly. 3. I made minor changes to ChangeLog part of the commit message (I moved 'H' -> 'Zicsr' dependency for a reason but I didn't mentioned in the ChangeLog). [Changes: v3 -> v4] 1. Rebase against the latest master (with a bit of reordering). 2. Reorder renamed 'Svade' to reflect canonical order. 3. Referenced specification is now the ratified one (version 1.0), not frozen but draft one (version 0.9.2). Thanks, Tsukasa Tsukasa OI (1): RISC-V: Add platform property/capability extensions bfd/elfxx-riscv.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) base-commit: 6296109afcd8c8e89b771fbaf092d17a17d4ea99 -- 2.41.0 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v4 1/1] RISC-V: Add platform property/capability extensions 2023-07-26 0:05 ` [PATCH v4 0/1] RISC-V: Extensions from the RISC-V Profiles Tsukasa OI @ 2023-07-26 0:05 ` Tsukasa OI 2023-07-26 0:47 ` Palmer Dabbelt 0 siblings, 1 reply; 17+ messages in thread From: Tsukasa OI @ 2023-07-26 0:05 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils From: Tsukasa OI <research_trasio@irq.a4lg.com> RISC-V Profiles document defines number of "extensions" that indicate certain platform properties/capabilities just like 'Zkt' extension from the RISC-V cryptography extensions. This commit defines 20 platform property/capability extensions as defined in the RISC-V Profiles documentation. The only exception: 'Ssstateen' extension is defined separately because it defines a subset (supervisor/hypervisor view) of the 'Smstateen' extension. This is based on the ratified version of RISC-V Profiles: <https://github.com/riscv/riscv-profiles/releases/tag/v1.0> [Definition] "Main memory regions": Main memory regions (in contrast to I/O or vacant memory regions) with both the cacheability and coherence PMAs. [New Unprivileged Extensions] 1. 'Ziccif' "Main memory regions" support instruction fetch and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN, XLEN) are atomic. 2. 'Ziccrse' "Main memory regions" provide the eventual success guarantee for LR/SC sequence (RsrvEventual). 3. 'Ziccamoa' "Main memory regions" support all currently-defined AMO operations including swap, logical and arithmetic operations (AMOArithmetic). 4. 'Za64rs' For LR/SC instructions, reservation sets are contiguous, naturally aligned and at most 64-bytes in size. 5. 'Za128rs' Likewise, but reservation sets are at most 128-bytes in size. 6. 'Zicclsm' Misaligned loads / stores to "main memory regions" are supported. Those include both regular scalar and vector accesses but does not include AMOs and other specialized forms of memory accesses. 7. 'Zic64b' Cache blocks are (exactly) 64-bytes in size and naturally aligned. [New Privileged Extensions] 1. 'Svbare' "satp" mode Bare is supported. 2. 'Svade' Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear. 3. 'Ssccptr' "Main memory regions" support hardware page-table reads. 4. 'Sstvecd' "stvec" mode Direct is supported. When "stvec" mode is Direct, "stvec.BASE" is capable of holding any valid 4-byte aligned address. 5. 'Sstvala' "stval" is always written with a nonzero value whenever possible as specified in the Privileged Architecture documentation (version 20211203: see section 4.1.9). 6. 'Sscounterenw' For any "hpmcounter" that is not read-only zero, the corresponding bit in "scounteren" is writable. 7. 'Ssu64xl' "sstatus.UXL" is capable of holding the value 0b10 (UXLEN==64 is supported). 8. 'Shcounterenw' Similar to 'Sscounterenw' but the same rule applies to "hcounteren". 9. 'Shvstvala' Similar to 'Sstvala' but the same rule applies to "vstval". 10. 'Shtvala' "htval" is written with the faulting guest physical address as long as permitted by the ISA (a bit similar to 'Sstvala' and 'Shvstvala'). 11. 'Shvstvecd' Similar to 'Sstvecd' but the same rule applies to "vstvec". 12. 'Shvsatpa' All translation modes supported in "satp" are also supported in "vsatp". 13. 'Shgatpa' For each supported virtual memory scheme SvNN supported in "satp", the corresponding "hgatp" SvNNx4 mode is supported. The "hgatp" mode Bare is also supported. [Implications] (Due to reservation set size constraints) - 'Za64rs' -> 'Za128rs' (Due to the fact that a privileged "extension" directly refers a CSR) - 'Svbare' -> 'Zicsr' - 'Sstvecd' -> 'Zicsr' - 'Sstvala' -> 'Zicsr' - 'Sscounterenw' -> 'Zicsr' - 'Ssu64xl' -> 'Zicsr' (Due to the fact that a privileged "extension" indirectly depends on CSRs) - 'Svade' -> 'Zicsr' (Due to the fact that a privileged "extension" is a hypervisor property) - 'Shcounterenw' -> 'H' - 'Shvstvala' -> 'H' - 'Shtvala' -> 'H' - 'Shvstvecd' -> 'H' - 'Shvsatpa' -> 'H' - 'Shgatpa' -> 'H' bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add 13 implication rules. Reorder 'H' for new 'Sh*' extensions. (riscv_supported_std_z_ext) Add 7 property/capability extensions. (riscv_supported_std_s_ext) Add 13 property/capability extensions. --- bfd/elfxx-riscv.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index b43d2cfa0fab..47dede91e064 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1105,7 +1105,6 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"g", "zicsr", check_implicit_always}, {"g", "zifencei", check_implicit_always}, {"m", "zmmul", check_implicit_always}, - {"h", "zicsr", check_implicit_always}, {"q", "d", check_implicit_always}, {"v", "d", check_implicit_always}, {"v", "zve64d", check_implicit_always}, @@ -1144,6 +1143,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zhinx", "zhinxmin", check_implicit_always}, {"zhinxmin", "zfinx", check_implicit_always}, {"zfinx", "zicsr", check_implicit_always}, + {"za64rs", "za128rs", check_implicit_always}, {"zk", "zkn", check_implicit_always}, {"zk", "zkr", check_implicit_always}, {"zk", "zkt", check_implicit_always}, @@ -1179,10 +1179,23 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"smaia", "ssaia", check_implicit_always}, {"smstateen", "ssstateen", check_implicit_always}, {"smepmp", "zicsr", check_implicit_always}, + {"shcounterenw", "h", check_implicit_always}, + {"shgatpa", "h", check_implicit_always}, + {"shtvala", "h", check_implicit_always}, + {"shvsatpa", "h", check_implicit_always}, + {"shvstvala", "h", check_implicit_always}, + {"shvstvecd", "h", check_implicit_always}, + {"h", "zicsr", check_implicit_always}, {"ssaia", "zicsr", check_implicit_always}, {"sscofpmf", "zicsr", check_implicit_always}, + {"sscounterenw", "zicsr", check_implicit_always}, {"ssstateen", "zicsr", check_implicit_always}, {"sstc", "zicsr", check_implicit_always}, + {"sstvala", "zicsr", check_implicit_always}, + {"sstvecd", "zicsr", check_implicit_always}, + {"ssu64xl", "zicsr", check_implicit_always}, + {"svade", "zicsr", check_implicit_always}, + {"svbare", "zicsr", check_implicit_always}, {NULL, NULL, NULL} }; @@ -1240,6 +1253,11 @@ static struct riscv_supported_ext riscv_supported_std_ext[] = static struct riscv_supported_ext riscv_supported_std_z_ext[] = { + {"zic64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ziccamoa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ziccif", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicclsm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ziccrse", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -1250,6 +1268,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfa", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -1318,13 +1338,26 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = static struct riscv_supported_ext riscv_supported_std_s_ext[] = { + {"shcounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shgatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shtvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shvsatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shvstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shvstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sscounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssu64xl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svade", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svbare", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svpbmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -- 2.41.0 ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v4 1/1] RISC-V: Add platform property/capability extensions 2023-07-26 0:05 ` [PATCH v4 1/1] RISC-V: Add platform property/capability extensions Tsukasa OI @ 2023-07-26 0:47 ` Palmer Dabbelt 2023-07-26 1:02 ` Tsukasa OI 2023-07-31 2:56 ` Tsukasa OI 0 siblings, 2 replies; 17+ messages in thread From: Palmer Dabbelt @ 2023-07-26 0:47 UTC (permalink / raw) To: research_trasio; +Cc: research_trasio, nelson, kito.cheng, binutils On Tue, 25 Jul 2023 17:05:53 PDT (-0700), research_trasio@irq.a4lg.com wrote: > From: Tsukasa OI <research_trasio@irq.a4lg.com> > > RISC-V Profiles document defines number of "extensions" that indicate > certain platform properties/capabilities just like 'Zkt' extension from the > RISC-V cryptography extensions. > > This commit defines 20 platform property/capability extensions as defined > in the RISC-V Profiles documentation. > > The only exception: 'Ssstateen' extension is defined separately because it > defines a subset (supervisor/hypervisor view) of the 'Smstateen' extension. > > This is based on the ratified version of RISC-V Profiles: > <https://github.com/riscv/riscv-profiles/releases/tag/v1.0> > > [Definition] > > "Main memory regions": > Main memory regions (in contrast to I/O or vacant memory regions) with > both the cacheability and coherence PMAs. > > [New Unprivileged Extensions] > > 1. 'Ziccif' > "Main memory regions" support instruction fetch and any instruction > fetches of naturally aligned power-of-2 sizes up to min(ILEN, XLEN) > are atomic. > 2. 'Ziccrse' > "Main memory regions" provide the eventual success guarantee for > LR/SC sequence (RsrvEventual). > 3. 'Ziccamoa' > "Main memory regions" support all currently-defined AMO operations > including swap, logical and arithmetic operations (AMOArithmetic). > 4. 'Za64rs' > For LR/SC instructions, reservation sets are contiguous, naturally > aligned and at most 64-bytes in size. > 5. 'Za128rs' > Likewise, but reservation sets are at most 128-bytes in size. > 6. 'Zicclsm' > Misaligned loads / stores to "main memory regions" are supported. > Those include both regular scalar and vector accesses but does not > include AMOs and other specialized forms of memory accesses. > 7. 'Zic64b' > Cache blocks are (exactly) 64-bytes in size and naturally aligned. IMO we want to stay away from these extensions that are just defined by a single phrase in the spec. We're still digging out from the first rounds of changed specs, trying to start supporting stuff that's not even been defined is going to just make for another round of headaches. > [New Privileged Extensions] > > 1. 'Svbare' > "satp" mode Bare is supported. > 2. 'Svade' > Page-fault exceptions are raised when a page is accessed when A bit is > clear, or written when D bit is clear. > 3. 'Ssccptr' > "Main memory regions" support hardware page-table reads. > 4. 'Sstvecd' > "stvec" mode Direct is supported. When "stvec" mode is Direct, > "stvec.BASE" is capable of holding any valid 4-byte aligned address. > 5. 'Sstvala' > "stval" is always written with a nonzero value whenever possible as > specified in the Privileged Architecture documentation > (version 20211203: see section 4.1.9). > 6. 'Sscounterenw' > For any "hpmcounter" that is not read-only zero, the corresponding bit > in "scounteren" is writable. > 7. 'Ssu64xl' > "sstatus.UXL" is capable of holding the value 0b10 > (UXLEN==64 is supported). > 8. 'Shcounterenw' > Similar to 'Sscounterenw' but the same rule applies to "hcounteren". > 9. 'Shvstvala' > Similar to 'Sstvala' but the same rule applies to "vstval". > 10. 'Shtvala' > "htval" is written with the faulting guest physical address as long as > permitted by the ISA (a bit similar to 'Sstvala' and 'Shvstvala'). > 11. 'Shvstvecd' > Similar to 'Sstvecd' but the same rule applies to "vstvec". > 12. 'Shvsatpa' > All translation modes supported in "satp" are also supported in "vsatp". > 13. 'Shgatpa' > For each supported virtual memory scheme SvNN supported in "satp", the > corresponding "hgatp" SvNNx4 mode is supported. The "hgatp" mode Bare > is also supported. > > [Implications] > > (Due to reservation set size constraints) > - 'Za64rs' -> 'Za128rs' > > (Due to the fact that a privileged "extension" directly refers a CSR) > - 'Svbare' -> 'Zicsr' > - 'Sstvecd' -> 'Zicsr' > - 'Sstvala' -> 'Zicsr' > - 'Sscounterenw' -> 'Zicsr' > - 'Ssu64xl' -> 'Zicsr' > > (Due to the fact that a privileged "extension" indirectly depends on CSRs) > - 'Svade' -> 'Zicsr' > > (Due to the fact that a privileged "extension" is a hypervisor property) > - 'Shcounterenw' -> 'H' > - 'Shvstvala' -> 'H' > - 'Shtvala' -> 'H' > - 'Shvstvecd' -> 'H' > - 'Shvsatpa' -> 'H' > - 'Shgatpa' -> 'H' > > bfd/ChangeLog: > > * elfxx-riscv.c > (riscv_implicit_subsets): Add 13 implication rules. > Reorder 'H' for new 'Sh*' extensions. > (riscv_supported_std_z_ext) Add 7 property/capability extensions. > (riscv_supported_std_s_ext) Add 13 property/capability extensions. > --- > bfd/elfxx-riscv.c | 35 ++++++++++++++++++++++++++++++++++- > 1 file changed, 34 insertions(+), 1 deletion(-) > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index b43d2cfa0fab..47dede91e064 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -1105,7 +1105,6 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = > {"g", "zicsr", check_implicit_always}, > {"g", "zifencei", check_implicit_always}, > {"m", "zmmul", check_implicit_always}, > - {"h", "zicsr", check_implicit_always}, > {"q", "d", check_implicit_always}, > {"v", "d", check_implicit_always}, > {"v", "zve64d", check_implicit_always}, > @@ -1144,6 +1143,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = > {"zhinx", "zhinxmin", check_implicit_always}, > {"zhinxmin", "zfinx", check_implicit_always}, > {"zfinx", "zicsr", check_implicit_always}, > + {"za64rs", "za128rs", check_implicit_always}, > {"zk", "zkn", check_implicit_always}, > {"zk", "zkr", check_implicit_always}, > {"zk", "zkt", check_implicit_always}, > @@ -1179,10 +1179,23 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = > {"smaia", "ssaia", check_implicit_always}, > {"smstateen", "ssstateen", check_implicit_always}, > {"smepmp", "zicsr", check_implicit_always}, > + {"shcounterenw", "h", check_implicit_always}, > + {"shgatpa", "h", check_implicit_always}, > + {"shtvala", "h", check_implicit_always}, > + {"shvsatpa", "h", check_implicit_always}, > + {"shvstvala", "h", check_implicit_always}, > + {"shvstvecd", "h", check_implicit_always}, > + {"h", "zicsr", check_implicit_always}, > {"ssaia", "zicsr", check_implicit_always}, > {"sscofpmf", "zicsr", check_implicit_always}, > + {"sscounterenw", "zicsr", check_implicit_always}, > {"ssstateen", "zicsr", check_implicit_always}, > {"sstc", "zicsr", check_implicit_always}, > + {"sstvala", "zicsr", check_implicit_always}, > + {"sstvecd", "zicsr", check_implicit_always}, > + {"ssu64xl", "zicsr", check_implicit_always}, > + {"svade", "zicsr", check_implicit_always}, > + {"svbare", "zicsr", check_implicit_always}, > {NULL, NULL, NULL} > }; > > @@ -1240,6 +1253,11 @@ static struct riscv_supported_ext riscv_supported_std_ext[] = > > static struct riscv_supported_ext riscv_supported_std_z_ext[] = > { > + {"zic64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"ziccamoa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"ziccif", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"zicclsm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"ziccrse", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > @@ -1250,6 +1268,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = > {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, > {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, > {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zfa", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, > {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > @@ -1318,13 +1338,26 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = > > static struct riscv_supported_ext riscv_supported_std_s_ext[] = > { > + {"shcounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"shgatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"shtvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"shvsatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"shvstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"shvstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"smaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"sscounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"ssu64xl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"svade", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"svbare", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"svpbmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v4 1/1] RISC-V: Add platform property/capability extensions 2023-07-26 0:47 ` Palmer Dabbelt @ 2023-07-26 1:02 ` Tsukasa OI 2023-07-31 2:56 ` Tsukasa OI 1 sibling, 0 replies; 17+ messages in thread From: Tsukasa OI @ 2023-07-26 1:02 UTC (permalink / raw) To: Palmer Dabbelt; +Cc: binutils On 2023/07/26 9:47, Palmer Dabbelt wrote: > IMO we want to stay away from these extensions that are just defined by > a single phrase in the spec. We're still digging out from the first > rounds of changed specs, trying to start supporting stuff that's not > even been defined is going to just make for another round of headaches. I see. I don't completely agree but it makes sense ('Zkt' for example, has a dedicated section to describe this extension). I think there's not so much room for improvements for many of "single phrase" extensions (on 'Ssu64xl', I requested to clarify some details before the ratification; 'Zic64b' describes itself completely and adding more words won't work; definition of 'Zicclsm' on the other hand, might be better to be a bit stricter). However, I see they are not so urgent. As long as this patch set is considered as a prerequisite of further "RISC-V Profiles" support (e.g. "-march=rva..."), I can wait. Thanks, Tsukasa ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v4 1/1] RISC-V: Add platform property/capability extensions 2023-07-26 0:47 ` Palmer Dabbelt 2023-07-26 1:02 ` Tsukasa OI @ 2023-07-31 2:56 ` Tsukasa OI 1 sibling, 0 replies; 17+ messages in thread From: Tsukasa OI @ 2023-07-31 2:56 UTC (permalink / raw) To: Palmer Dabbelt; +Cc: binutils Again, I'm not strongly object this decision but I'll note a background before I forget again (and in July, before the thread tree in the Binutils Archives website breaks). My initial patch set (in 2022-11) <https://sourceware.org/pipermail/binutils/2022-November/124155.html> is approved by Nelson once. <https://sourceware.org/pipermail/binutils/2022-November/124158.html> But I decided not to commit it because I felt something in the RISC-V Profiles specification will likely change (despite it being frozen; and it did, 'Ssptead' was renamed to 'Svade' and 'Sscounterenw' was added). I'm **not** going through using this approval since it's too old. But I will appreciate if you consider this a little. As I replied earlier, I can wait until RISC-V Profiles through "-march" is supported. <https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36> Thanks, Tsukasa On 2023/07/26 9:47, Palmer Dabbelt wrote: > On Tue, 25 Jul 2023 17:05:53 PDT (-0700), research_trasio@irq.a4lg.com > wrote: >> From: Tsukasa OI <research_trasio@irq.a4lg.com> >> >> RISC-V Profiles document defines number of "extensions" that indicate >> certain platform properties/capabilities just like 'Zkt' extension >> from the >> RISC-V cryptography extensions. >> >> This commit defines 20 platform property/capability extensions as defined >> in the RISC-V Profiles documentation. >> >> The only exception: 'Ssstateen' extension is defined separately >> because it >> defines a subset (supervisor/hypervisor view) of the 'Smstateen' >> extension. >> >> This is based on the ratified version of RISC-V Profiles: >> <https://github.com/riscv/riscv-profiles/releases/tag/v1.0> >> >> [Definition] >> >> "Main memory regions": >> Main memory regions (in contrast to I/O or vacant memory regions) >> with >> both the cacheability and coherence PMAs. >> >> [New Unprivileged Extensions] >> >> 1. 'Ziccif' >> "Main memory regions" support instruction fetch and any instruction >> fetches of naturally aligned power-of-2 sizes up to min(ILEN, XLEN) >> are atomic. >> 2. 'Ziccrse' >> "Main memory regions" provide the eventual success guarantee for >> LR/SC sequence (RsrvEventual). >> 3. 'Ziccamoa' >> "Main memory regions" support all currently-defined AMO operations >> including swap, logical and arithmetic operations (AMOArithmetic). >> 4. 'Za64rs' >> For LR/SC instructions, reservation sets are contiguous, naturally >> aligned and at most 64-bytes in size. >> 5. 'Za128rs' >> Likewise, but reservation sets are at most 128-bytes in size. >> 6. 'Zicclsm' >> Misaligned loads / stores to "main memory regions" are supported. >> Those include both regular scalar and vector accesses but does not >> include AMOs and other specialized forms of memory accesses. >> 7. 'Zic64b' >> Cache blocks are (exactly) 64-bytes in size and naturally aligned. > > IMO we want to stay away from these extensions that are just defined by > a single phrase in the spec. We're still digging out from the first > rounds of changed specs, trying to start supporting stuff that's not > even been defined is going to just make for another round of headaches. > >> [New Privileged Extensions] >> >> 1. 'Svbare' >> "satp" mode Bare is supported. >> 2. 'Svade' >> Page-fault exceptions are raised when a page is accessed when A >> bit is >> clear, or written when D bit is clear. >> 3. 'Ssccptr' >> "Main memory regions" support hardware page-table reads. >> 4. 'Sstvecd' >> "stvec" mode Direct is supported. When "stvec" mode is Direct, >> "stvec.BASE" is capable of holding any valid 4-byte aligned address. >> 5. 'Sstvala' >> "stval" is always written with a nonzero value whenever possible as >> specified in the Privileged Architecture documentation >> (version 20211203: see section 4.1.9). >> 6. 'Sscounterenw' >> For any "hpmcounter" that is not read-only zero, the corresponding >> bit >> in "scounteren" is writable. >> 7. 'Ssu64xl' >> "sstatus.UXL" is capable of holding the value 0b10 >> (UXLEN==64 is supported). >> 8. 'Shcounterenw' >> Similar to 'Sscounterenw' but the same rule applies to "hcounteren". >> 9. 'Shvstvala' >> Similar to 'Sstvala' but the same rule applies to "vstval". >> 10. 'Shtvala' >> "htval" is written with the faulting guest physical address as >> long as >> permitted by the ISA (a bit similar to 'Sstvala' and 'Shvstvala'). >> 11. 'Shvstvecd' >> Similar to 'Sstvecd' but the same rule applies to "vstvec". >> 12. 'Shvsatpa' >> All translation modes supported in "satp" are also supported in >> "vsatp". >> 13. 'Shgatpa' >> For each supported virtual memory scheme SvNN supported in "satp", >> the >> corresponding "hgatp" SvNNx4 mode is supported. The "hgatp" mode >> Bare >> is also supported. >> >> [Implications] >> >> (Due to reservation set size constraints) >> - 'Za64rs' -> 'Za128rs' >> >> (Due to the fact that a privileged "extension" directly refers a CSR) >> - 'Svbare' -> 'Zicsr' >> - 'Sstvecd' -> 'Zicsr' >> - 'Sstvala' -> 'Zicsr' >> - 'Sscounterenw' -> 'Zicsr' >> - 'Ssu64xl' -> 'Zicsr' >> >> (Due to the fact that a privileged "extension" indirectly depends on >> CSRs) >> - 'Svade' -> 'Zicsr' >> >> (Due to the fact that a privileged "extension" is a hypervisor property) >> - 'Shcounterenw' -> 'H' >> - 'Shvstvala' -> 'H' >> - 'Shtvala' -> 'H' >> - 'Shvstvecd' -> 'H' >> - 'Shvsatpa' -> 'H' >> - 'Shgatpa' -> 'H' >> >> bfd/ChangeLog: >> >> * elfxx-riscv.c >> (riscv_implicit_subsets): Add 13 implication rules. >> Reorder 'H' for new 'Sh*' extensions. >> (riscv_supported_std_z_ext) Add 7 property/capability extensions. >> (riscv_supported_std_s_ext) Add 13 property/capability extensions. >> --- >> bfd/elfxx-riscv.c | 35 ++++++++++++++++++++++++++++++++++- >> 1 file changed, 34 insertions(+), 1 deletion(-) >> >> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c >> index b43d2cfa0fab..47dede91e064 100644 >> --- a/bfd/elfxx-riscv.c >> +++ b/bfd/elfxx-riscv.c >> @@ -1105,7 +1105,6 @@ static struct riscv_implicit_subset >> riscv_implicit_subsets[] = >> {"g", "zicsr", check_implicit_always}, >> {"g", "zifencei", check_implicit_always}, >> {"m", "zmmul", check_implicit_always}, >> - {"h", "zicsr", check_implicit_always}, >> {"q", "d", check_implicit_always}, >> {"v", "d", check_implicit_always}, >> {"v", "zve64d", check_implicit_always}, >> @@ -1144,6 +1143,7 @@ static struct riscv_implicit_subset >> riscv_implicit_subsets[] = >> {"zhinx", "zhinxmin", check_implicit_always}, >> {"zhinxmin", "zfinx", check_implicit_always}, >> {"zfinx", "zicsr", check_implicit_always}, >> + {"za64rs", "za128rs", check_implicit_always}, >> {"zk", "zkn", check_implicit_always}, >> {"zk", "zkr", check_implicit_always}, >> {"zk", "zkt", check_implicit_always}, >> @@ -1179,10 +1179,23 @@ static struct riscv_implicit_subset >> riscv_implicit_subsets[] = >> {"smaia", "ssaia", check_implicit_always}, >> {"smstateen", "ssstateen", check_implicit_always}, >> {"smepmp", "zicsr", check_implicit_always}, >> + {"shcounterenw", "h", check_implicit_always}, >> + {"shgatpa", "h", check_implicit_always}, >> + {"shtvala", "h", check_implicit_always}, >> + {"shvsatpa", "h", check_implicit_always}, >> + {"shvstvala", "h", check_implicit_always}, >> + {"shvstvecd", "h", check_implicit_always}, >> + {"h", "zicsr", check_implicit_always}, >> {"ssaia", "zicsr", check_implicit_always}, >> {"sscofpmf", "zicsr", check_implicit_always}, >> + {"sscounterenw", "zicsr", check_implicit_always}, >> {"ssstateen", "zicsr", check_implicit_always}, >> {"sstc", "zicsr", check_implicit_always}, >> + {"sstvala", "zicsr", check_implicit_always}, >> + {"sstvecd", "zicsr", check_implicit_always}, >> + {"ssu64xl", "zicsr", check_implicit_always}, >> + {"svade", "zicsr", check_implicit_always}, >> + {"svbare", "zicsr", check_implicit_always}, >> {NULL, NULL, NULL} >> }; >> >> @@ -1240,6 +1253,11 @@ static struct riscv_supported_ext >> riscv_supported_std_ext[] = >> >> static struct riscv_supported_ext riscv_supported_std_z_ext[] = >> { >> + {"zic64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"ziccamoa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"ziccif", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"zicclsm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"ziccrse", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> @@ -1250,6 +1268,8 @@ static struct riscv_supported_ext >> riscv_supported_std_z_ext[] = >> {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, >> {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, >> {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"zfa", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, >> {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> @@ -1318,13 +1338,26 @@ static struct riscv_supported_ext >> riscv_supported_std_z_ext[] = >> >> static struct riscv_supported_ext riscv_supported_std_s_ext[] = >> { >> + {"shcounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"shgatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"shtvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"shvsatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"shvstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"shvstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"smaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"sscounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"ssu64xl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"svade", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"svbare", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"svpbmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 0/1] RISC-V: Extensions from the RISC-V Profiles 2023-01-30 6:35 ` [PATCH v2 0/1] " Tsukasa OI 2023-01-30 6:35 ` [PATCH v2 1/1] RISC-V: Add platform property/capability extensions Tsukasa OI 2023-01-30 7:11 ` [PATCH v3 0/1] RISC-V: Extensions from the RISC-V Profiles Tsukasa OI @ 2023-01-31 4:46 ` Nelson Chu 2 siblings, 0 replies; 17+ messages in thread From: Nelson Chu @ 2023-01-31 4:46 UTC (permalink / raw) To: Tsukasa OI; +Cc: Kito Cheng, Palmer Dabbelt, binutils On Mon, Jan 30, 2023 at 2:35 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote: > > Hello, > > First, to whom concerned (especially, to Nelson): > I quit the job two weeks ago due to my poor health conditions and will take > some time for recuperation. Because of this (despite that I've seen all > your reviews and responses), I will not be able to respond properly (and in > a responsible manner) until... probably April or May. For me at least, I believe health and family are definitely top of mind, so even though this news is certainly a loss for the entire risc-v community, especially for the GNU developers and me, I still hope that you can take this time to recover just like before. Don't pay too much attention to what I thought at that time, since people always change their mind and become better with time :-) The only thing that won't change is everyone here wants to make upstream better, that definitely includes you and me. So thanks for all your contributions and efforts before. Take care, stay safe, looking forward to co-work with you soon, no matter what field and what times. Nelson > Before I get busier, I will submit this one because the RISC-V Profiles > documentation is now updated (version 0.9.2, the release for TSC > recommendation to ratify) and this time, it's very unlikely to change now > (I found a typo in this but at least it's stable enough to implement). > > c.f. <https://github.com/riscv/riscv-profiles/releases/tag/v0.9.2> > > On PATCH v1, though the base specification (version 0.9-draft) was Frozen, > some changes are expected and I submitted it with DO NOT MERGE status. > > The change actually happened and an extension name has changed ('Ssptead' -> > 'Svptead' -> 'Svade'). This time, I think it's safe to upstream new > extension names. Thanks, I will take a look at this later :) > > Sincerely, > Tsukasa > > > > > Tsukasa OI (1): > RISC-V: Add platform property/capability extensions > > bfd/elfxx-riscv.c | 35 ++++++++++++++++++++++++++++++++++- > 1 file changed, 34 insertions(+), 1 deletion(-) > > > base-commit: 594a01c217143dce2f1f3181bcca4047b4a44107 > -- > 2.39.0 > ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 0/8] RISC-V: Combined floating point enhancements
@ 2022-06-27 2:03 Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 5/8] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI
0 siblings, 1 reply; 17+ messages in thread
From: Tsukasa OI @ 2022-06-27 2:03 UTC (permalink / raw)
To: Tsukasa OI, Weiwei Li, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
Before combining patchsets:
<https://sourceware.org/pipermail/binutils/2022-May/120935.html> (Zfh/Zfhmin v2)
<https://sourceware.org/pipermail/binutils/2022-May/120940.html> (Zfinx v2)
Combined v1:
<https://sourceware.org/pipermail/binutils/2022-June/121138.html>
Combined CURRENT (GitHub):
<https://github.com/a4lg/binutils-gdb/tree/riscv-float-combined>
[Combined Enhancements / Fixes]
1. Zfh/Zhinx refactoring / new Zfhmin/Zhinxmin support
<https://sourceware.org/pipermail/binutils/2022-May/120935.html>
<https://sourceware.org/pipermail/binutils/2022-May/120952.html>
2. Zfinx fixes / test enhancements
<https://sourceware.org/pipermail/binutils/2022-February/119570.html>
<https://sourceware.org/pipermail/binutils/2022-February/119576.html>
<https://sourceware.org/pipermail/binutils/2022-May/120940.html>
They are supposed to be separate but involves similar/same locations
that need to be modified. To ease testing and integration to upstream,
I decided to merge those fixes in a single patchset. Of course, I can
split it if requested.
Also in general, I squashed some of fixes/enhancements (spanned in
multiple patches) for simplicity.
As a result, it halved the number of patches.
Zfh/Zfhmin: 5 -> 3
Zfinx/Zdinx/Zqinx: 11 -> 5
Note that, this is a long-term fix to Zfinx/Zfhmin/Zhinxmin implementation.
As a result, this is incompatible with my quicker patchset:
<https://sourceware.org/pipermail/binutils/2022-June/121416.html>
... which I consider quicker one a backup plan when this patchset will not
make it into the GNU Binutils 2.39.
[Changed: v1 -> v2]
1. i18n enablement (wrap some strings with the _() gettext macro)
2. Removed original PATCH 01 (as it was merged independently)
<https://sourceware.org/pipermail/binutils/2022-June/121342.html>
[Details of Changes (mostly duplicate of v1 but some are fixed)]
1.1. Zfhmin/Zhinxmin subset extension support (PATCH 03)
This patch implements Zfhmin/Zhinxmin extension, conversion-only subset
of Zfh/Zhinx instruction set extensions, respectively.
1.2. [minor] Refactoring for better integration (PATCH 01)
In particular, better integration with F, D and Q. To do that, it
required moving certain macros and constants. But there are no
functional changes. The whole patchset would (and should) work without
this patch.
1.3. [minor] DECLARE_INSN declarations (PATCH 02)
Zfh instructions did not have their own DECLARE_INSN declarations.
PATCH 02 resolves this problem (although not having those is harmless
on current design).
2.1. Disassembler output with Zfinx + -M numeric option (PATCH 04)
Disassembling Zhinx/Zhinxmin/Zfinx/Zdinx/Zqinx instructions with -M
numeric option has an issue. It used ABI names instead of numeric one.
This commit fixes that.
2.2. Enhanced Zfinx/Zdinx/Zqinx testcases (PATCH 05)
I enhanced Zfinx/Zdinx/Zqinx testcases based on Jiawei's Zhinx support
patch. I also...
- Made indentation / coding style consistent and clean
- Started to use valid register number (on Zqinx)
- Started to use different register per operand
2.3. Relaxed requirements to fmv.[sdq] instructions (PATCH 06)
On Zfinx/Zdinx/Zqinx, fmv instructions seem redundant but actually not.
On RV32_Z[dq]inx and RV64_Zqinx, it requires register pair. That means,
single...
fmv.d x10, x12
is equivalent to 2 regular instructions on RV32_Zdinx (with 32b GPRs):
mv x10, x12
mv x11, x13
Since fsgnj.[sdq] (base instruction of fmv.[sdq]) are a part of
Z[fdq]inx extensions, it's safe to implement this pseudoinstructions.
PATCH 06 makes fmv.[sdq] available to Zfinx/Zdinx/Zqinx environments.
2.4. Validate register pairs on Zdinx/Zqinx (PATCH 07, 08)
For RV32_Zdinx and RV64_Zqinx, all registers holding a FP64 value must
be even (x0, x2, x4... are valid, x1, x3, x5... are invalid).
For RV32_Zqinx, it would be all registers holding a FP128 value must be
a multiple of 4 (x0, x4, x8... are valid, x1, x2, x3, x5... are not).
On the other hand, current Binutils can generate invalid instructions
with odd register numbers (or register number x % 4 != 0). PATCH 07
makes those invalid and PATCH 08 adds tests.
Due to complexity, this patch is relatively large.
Tsukasa OI (8):
RISC-V: Refactor Zfh/Zhinx-related constants
RISC-V: Add instruction declaration for Zfh/Zhinx
RISC-V: Add Zfhmin/Zhinxmin (with refactoring)
RISC-V: Fix disassembling Zfinx with -M numeric
RISC-V: Reorganize and enhance Zfinx tests
RISC-V: Relax `fmv.[sdq]' requirements
RISC-V: Validate Zdinx/Zqinx register pairs
RISC-V: Add testcases for Z[dq]inx register pairs
bfd/elfxx-riscv.c | 87 ++-
gas/config/tc-riscv.c | 40 +-
.../gas/riscv/zdinx-32-regpair-dis.d | 11 +
.../gas/riscv/zdinx-32-regpair-dis.s | 5 +
.../gas/riscv/zdinx-32-regpair-fail.d | 3 +
.../gas/riscv/zdinx-32-regpair-fail.l | 111 +++
.../gas/riscv/zdinx-32-regpair-fail.s | 116 +++
gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 ++
gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++
gas/testsuite/gas/riscv/zdinx.d | 27 +-
gas/testsuite/gas/riscv/zdinx.s | 46 +-
.../gas/riscv/zfhmin-d-insn-class-fail-1.d | 3 +
.../gas/riscv/zfhmin-d-insn-class-fail-1.l | 2 +
.../gas/riscv/zfhmin-d-insn-class-fail-2.d | 3 +
.../gas/riscv/zfhmin-d-insn-class-fail-2.l | 2 +
.../gas/riscv/zfhmin-d-insn-class-fail-3.d | 3 +
.../gas/riscv/zfhmin-d-insn-class-fail-3.l | 2 +
.../gas/riscv/zfhmin-d-insn-class-fail-4.d | 3 +
.../gas/riscv/zfhmin-d-insn-class-fail-4.l | 2 +
.../gas/riscv/zfhmin-d-insn-class-fail-5.d | 3 +
.../gas/riscv/zfhmin-d-insn-class-fail-5.l | 2 +
.../gas/riscv/zfhmin-d-insn-class-fail.s | 4 +
gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 10 +
gas/testsuite/gas/riscv/zfinx-dis-numeric.s | 2 +
gas/testsuite/gas/riscv/zfinx.d | 24 +-
gas/testsuite/gas/riscv/zfinx.s | 42 +-
.../gas/riscv/{fp-zhinx-insns.d => zhinx.d} | 37 +-
.../gas/riscv/{fp-zhinx-insns.s => zhinx.s} | 32 +-
.../gas/riscv/zqinx-32-regpair-dis.d | 12 +
.../gas/riscv/zqinx-32-regpair-dis.s | 7 +
.../gas/riscv/zqinx-32-regpair-fail.d | 3 +
.../gas/riscv/zqinx-32-regpair-fail.l | 212 ++++++
.../gas/riscv/zqinx-32-regpair-fail.s | 218 ++++++
gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 ++
gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 ++
.../gas/riscv/zqinx-64-regpair-dis.d | 11 +
.../gas/riscv/zqinx-64-regpair-dis.s | 5 +
.../gas/riscv/zqinx-64-regpair-fail.d | 3 +
.../gas/riscv/zqinx-64-regpair-fail.l | 133 ++++
.../gas/riscv/zqinx-64-regpair-fail.s | 138 ++++
gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++
gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++
gas/testsuite/gas/riscv/zqinx.d | 86 ++-
gas/testsuite/gas/riscv/zqinx.s | 89 ++-
include/opcode/riscv-opc.h | 180 +++--
include/opcode/riscv.h | 21 +-
opcodes/riscv-dis.c | 2 +-
opcodes/riscv-opc.c | 667 +++++++++++++-----
48 files changed, 2419 insertions(+), 418 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s
create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.d
create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.s
rename gas/testsuite/gas/riscv/{fp-zhinx-insns.d => zhinx.d} (81%)
rename gas/testsuite/gas/riscv/{fp-zhinx-insns.s => zhinx.s} (85%)
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s
base-commit: b4eb841afe9306fd7a6df95efcde120bfaa71e32
--
2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v2 5/8] RISC-V: Reorganize and enhance Zfinx tests 2022-06-27 2:03 [PATCH v2 0/8] RISC-V: Combined floating point enhancements Tsukasa OI @ 2022-06-27 2:03 ` Tsukasa OI 2022-11-29 6:35 ` [REVIEW ONLY 2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions jiawei 0 siblings, 1 reply; 17+ messages in thread From: Tsukasa OI @ 2022-06-27 2:03 UTC (permalink / raw) To: Tsukasa OI, Weiwei Li, Nelson Chu, Kito Cheng, Palmer Dabbelt Cc: binutils, jiawei This commit adds certain test cases for Zfinx/Zdinx/Zqinx extensions and reorganizes them, fixes coding style. This is partially based on jiawei's Zhinx testcases. gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Use different registers for better encode space testing / make indentation consistent / add tests for instruction with rounding mode. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Use different registers for better encode space testing / make indentation consistent / add tests for instruction with rounding mode. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.s: Use different registers for better encode space testing / make indentation consistent / add tests for instruction with rounding mode / use even-numbered registers to use valid register pairs. * testsuite/gas/riscv/zqinx.d: Likewise. Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> Signed-off-by: jiawei <jiawei@iscas.ac.cn> --- gas/testsuite/gas/riscv/zdinx.d | 26 ++++++++-- gas/testsuite/gas/riscv/zdinx.s | 45 ++++++++++++----- gas/testsuite/gas/riscv/zfinx.d | 23 +++++++-- gas/testsuite/gas/riscv/zfinx.s | 41 ++++++++++----- gas/testsuite/gas/riscv/zqinx.d | 85 ++++++++++++++++++------------- gas/testsuite/gas/riscv/zqinx.s | 88 ++++++++++++++++++++------------- 6 files changed, 208 insertions(+), 100 deletions(-) diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d index 3e4c1a73388..f0b2ca687ee 100644 --- a/gas/testsuite/gas/riscv/zdinx.d +++ b/gas/testsuite/gas/riscv/zdinx.d @@ -8,26 +8,42 @@ Disassembly of section .text: 0+000 <target>: [ ]+[0-9a-f]+:[ ]+02c5f553[ ]+fadd.d[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c58553[ ]+fadd.d[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+0ac5f553[ ]+fsub.d[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0ac58553[ ]+fsub.d[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+12c5f553[ ]+fmul.d[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+12c58553[ ]+fmul.d[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+1ac5f553[ ]+fdiv.d[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+5a057553[ ]+fsqrt.d[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+1ac58553[ ]+fdiv.d[ ]+a0,a1,a2,rne +[ ]+[0-9a-f]+:[ ]+5a05f553[ ]+fsqrt.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+5a058553[ ]+fsqrt.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+2ac58553[ ]+fmin.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+2ac59553[ ]+fmax.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+6ac5f543[ ]+fmadd.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac58543[ ]+fmadd.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+6ac5f54f[ ]+fnmadd.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac5854f[ ]+fnmadd.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+6ac5f547[ ]+fmsub.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac58547[ ]+fmsub.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+6ac5f54b[ ]+fnmsub.d[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+6ac5854b[ ]+fnmsub.d[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+c205f553[ ]+fcvt.w.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2058553[ ]+fcvt.w.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c215f553[ ]+fcvt.wu.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2158553[ ]+fcvt.wu.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c225f553[ ]+fcvt.l.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2258553[ ]+fcvt.l.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c235f553[ ]+fcvt.lu.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c2358553[ ]+fcvt.lu.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+d225f553[ ]+fcvt.d.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2258553[ ]+fcvt.d.l[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d235f553[ ]+fcvt.d.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2358553[ ]+fcvt.d.lu[ ]+a0,a1,rne +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+40158553[ ]+fcvt.s.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+22c58553[ ]+fsgnj.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+22c59553[ ]+fsgnjn.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+22c5a553[ ]+fsgnjx.d[ ]+a0,a1,a2 @@ -36,6 +52,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+22a51553[ ]+fneg.d[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+22a52553[ ]+fabs.d[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s index c427d982aaf..be9a47fa404 100644 --- a/gas/testsuite/gas/riscv/zdinx.s +++ b/gas/testsuite/gas/riscv/zdinx.s @@ -1,33 +1,52 @@ target: fadd.d a0, a1, a2 + fadd.d a0, a1, a2, rne fsub.d a0, a1, a2 + fsub.d a0, a1, a2, rne fmul.d a0, a1, a2 + fmul.d a0, a1, a2, rne fdiv.d a0, a1, a2 - fsqrt.d a0, a0 + fdiv.d a0, a1, a2, rne + fsqrt.d a0, a1 + fsqrt.d a0, a1, rne fmin.d a0, a1, a2 fmax.d a0, a1, a2 - fmadd.d a0, a1, a2, a3 + fmadd.d a0, a1, a2, a3 + fmadd.d a0, a1, a2, a3, rne fnmadd.d a0, a1, a2, a3 - fmsub.d a0, a1, a2, a3 + fnmadd.d a0, a1, a2, a3, rne + fmsub.d a0, a1, a2, a3 + fmsub.d a0, a1, a2, a3, rne fnmsub.d a0, a1, a2, a3 + fnmsub.d a0, a1, a2, a3, rne + fcvt.w.d a0, a1 + fcvt.w.d a0, a1, rne fcvt.wu.d a0, a1 + fcvt.wu.d a0, a1, rne fcvt.l.d a0, a1 + fcvt.l.d a0, a1, rne fcvt.lu.d a0, a1 - fcvt.s.d a0, a1 - fcvt.d.s a0, a1 + fcvt.lu.d a0, a1, rne fcvt.d.w a0, a1 fcvt.d.wu a0, a1 fcvt.d.l a0, a1 + fcvt.d.l a0, a1, rne fcvt.d.lu a0, a1 - fsgnj.d a0, a1, a2 + fcvt.d.lu a0, a1, rne + + fcvt.d.s a0, a1 + fcvt.s.d a0, a1 + fcvt.s.d a0, a1, rne + + fsgnj.d a0, a1, a2 fsgnjn.d a0, a1, a2 fsgnjx.d a0, a1, a2 - feq.d a0, a1, a2 - flt.d a0, a1, a2 - fle.d a0, a1, a2 - fgt.d a0, a1, a2 - fge.d a0, a1, a2 - fneg.d a0, a0 - fabs.d a0, a0 + feq.d a0, a1, a2 + flt.d a0, a1, a2 + fle.d a0, a1, a2 + fgt.d a0, a1, a2 + fge.d a0, a1, a2 + fneg.d a0, a1 + fabs.d a0, a1 fclass.d a0, a1 diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d index d5499aa9131..18a4e17f930 100644 --- a/gas/testsuite/gas/riscv/zfinx.d +++ b/gas/testsuite/gas/riscv/zfinx.d @@ -8,24 +8,41 @@ Disassembly of section .text: 0+000 <target>: [ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+00c58553[ ]+fadd.s[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+08c5f553[ ]+fsub.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+08c58553[ ]+fsub.s[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+10c5f553[ ]+fmul.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+10c58553[ ]+fmul.s[ ]+a0,a1,a2,rne [ ]+[0-9a-f]+:[ ]+18c5f553[ ]+fdiv.s[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+58057553[ ]+fsqrt.s[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+18c58553[ ]+fdiv.s[ ]+a0,a1,a2,rne +[ ]+[0-9a-f]+:[ ]+5805f553[ ]+fsqrt.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+58058553[ ]+fsqrt.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+28c58553[ ]+fmin.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+28c59553[ ]+fmax.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+68c5f543[ ]+fmadd.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c58543[ ]+fmadd.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+68c5f54f[ ]+fnmadd.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c5854f[ ]+fnmadd.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+68c5f547[ ]+fmsub.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c58547[ ]+fmsub.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+68c5f54b[ ]+fnmsub.s[ ]+a0,a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+68c5854b[ ]+fnmsub.s[ ]+a0,a1,a2,a3,rne [ ]+[0-9a-f]+:[ ]+c005f553[ ]+fcvt.w.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0058553[ ]+fcvt.w.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c015f553[ ]+fcvt.wu.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0158553[ ]+fcvt.wu.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c025f553[ ]+fcvt.l.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0258553[ ]+fcvt.l.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+c035f553[ ]+fcvt.lu.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c0358553[ ]+fcvt.lu.s[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d005f553[ ]+fcvt.s.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0058553[ ]+fcvt.s.w[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d015f553[ ]+fcvt.s.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0158553[ ]+fcvt.s.wu[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d025f553[ ]+fcvt.s.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0258553[ ]+fcvt.s.l[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d035f553[ ]+fcvt.s.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d0358553[ ]+fcvt.s.lu[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+20c58553[ ]+fsgnj.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+20c59553[ ]+fsgnjn.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+20c5a553[ ]+fsgnjx.s[ ]+a0,a1,a2 @@ -34,6 +51,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1 [ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+20a51553[ ]+fneg.s[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+20a52553[ ]+fabs.s[ ]+a0,a0 +[ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s index af50490fadf..6687f3187ef 100644 --- a/gas/testsuite/gas/riscv/zfinx.s +++ b/gas/testsuite/gas/riscv/zfinx.s @@ -1,31 +1,50 @@ target: fadd.s a0, a1, a2 + fadd.s a0, a1, a2, rne fsub.s a0, a1, a2 + fsub.s a0, a1, a2, rne fmul.s a0, a1, a2 + fmul.s a0, a1, a2, rne fdiv.s a0, a1, a2 - fsqrt.s a0, a0 + fdiv.s a0, a1, a2, rne + fsqrt.s a0, a1 + fsqrt.s a0, a1, rne fmin.s a0, a1, a2 fmax.s a0, a1, a2 - fmadd.s a0, a1, a2, a3 + fmadd.s a0, a1, a2, a3 + fmadd.s a0, a1, a2, a3, rne fnmadd.s a0, a1, a2, a3 - fmsub.s a0, a1, a2, a3 + fnmadd.s a0, a1, a2, a3, rne + fmsub.s a0, a1, a2, a3 + fmsub.s a0, a1, a2, a3, rne fnmsub.s a0, a1, a2, a3 + fnmsub.s a0, a1, a2, a3, rne + fcvt.w.s a0, a1 + fcvt.w.s a0, a1, rne fcvt.wu.s a0, a1 + fcvt.wu.s a0, a1, rne fcvt.l.s a0, a1 + fcvt.l.s a0, a1, rne fcvt.lu.s a0, a1 + fcvt.lu.s a0, a1, rne fcvt.s.w a0, a1 + fcvt.s.w a0, a1, rne fcvt.s.wu a0, a1 + fcvt.s.wu a0, a1, rne fcvt.s.l a0, a1 + fcvt.s.l a0, a1, rne fcvt.s.lu a0, a1 - fsgnj.s a0, a1, a2 + fcvt.s.lu a0, a1, rne + + fsgnj.s a0, a1, a2 fsgnjn.s a0, a1, a2 fsgnjx.s a0, a1, a2 - feq.s a0, a1, a2 - flt.s a0, a1, a2 - fle.s a0, a1, a2 - fgt.s a0, a1, a2 - fge.s a0, a1, a2 - fneg.s a0, a0 - fabs.s a0, a0 + feq.s a0, a1, a2 + flt.s a0, a1, a2 + fle.s a0, a1, a2 + fgt.s a0, a1, a2 + fge.s a0, a1, a2 + fneg.s a0, a1 + fabs.s a0, a1 fclass.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d index c1a09201206..f583002db0f 100644 --- a/gas/testsuite/gas/riscv/zqinx.d +++ b/gas/testsuite/gas/riscv/zqinx.d @@ -7,37 +7,54 @@ Disassembly of section .text: 0+000 <target>: -[ ]+[0-9a-f]+:[ ]+06c5f553[ ]+fadd.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+0ec5f553[ ]+fsub.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+16c5f553[ ]+fmul.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+1ec5f553[ ]+fdiv.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+5e057553[ ]+fsqrt.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+2ec58553[ ]+fmin.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+2ec59553[ ]+fmax.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+6ec5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f54f[ ]+fnmadd.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f547[ ]+fmsub.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+6ec5f54b[ ]+fnmsub.q[ ]+a0,a1,a2,a3 -[ ]+[0-9a-f]+:[ ]+c605f553[ ]+fcvt.w.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c615f553[ ]+fcvt.wu.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c625f553[ ]+fcvt.l.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+c635f553[ ]+fcvt.lu.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4035f553[ ]+fcvt.s.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+4235f553[ ]+fcvt.d.q[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6258553[ ]+fcvt.q.l[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+d6358553[ ]+fcvt.q.lu[ ]+a0,a1 -[ ]+[0-9a-f]+:[ ]+26c58553[ ]+fsgnj.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+26c59553[ ]+fsgnjn.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+26c5a553[ ]+fsgnjx.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c5a553[ ]+feq.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c59553[ ]+flt.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6c58553[ ]+fle.q[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+a6b61553[ ]+flt.q[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+a6b60553[ ]+fle.q[ ]+a0,a2,a1 -[ ]+[0-9a-f]+:[ ]+26a51553[ ]+fneg.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+26a52553[ ]+fabs.q[ ]+a0,a0 -[ ]+[0-9a-f]+:[ ]+e6059553[ ]+fclass.q[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+06e60553[ ]+fadd.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ee60553[ ]+fsub.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+16e60553[ ]+fmul.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ee60553[ ]+fdiv.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5e060553[ ]+fsqrt.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60543[ ]+fmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054f[ ]+fnmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60547[ ]+fmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054b[ ]+fnmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6060553[ ]+fcvt.w.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6160553[ ]+fcvt.wu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6260553[ ]+fcvt.l.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6360553[ ]+fcvt.lu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6267553[ ]+fcvt.q.l[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6260553[ ]+fcvt.q.l[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+d6367553[ ]+fcvt.q.lu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6360553[ ]+fcvt.q.lu[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40360553[ ]+fcvt.s.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42360553[ ]+fcvt.d.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index ba5179dc727..8158108230a 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -1,35 +1,55 @@ target: - fadd.q a0, a1, a2 - fsub.q a0, a1, a2 - fmul.q a0, a1, a2 - fdiv.q a0, a1, a2 - fsqrt.q a0, a0 - fmin.q a0, a1, a2 - fmax.q a0, a1, a2 - fmadd.q a0, a1, a2, a3 - fnmadd.q a0, a1, a2, a3 - fmsub.q a0, a1, a2, a3 - fnmsub.q a0, a1, a2, a3 - fcvt.w.q a0, a1 - fcvt.wu.q a0, a1 - fcvt.l.q a0, a1 - fcvt.lu.q a0, a1 - fcvt.s.q a0, a1 - fcvt.d.q a0, a1 - fcvt.q.s a0, a1 - fcvt.q.d a0, a1 - fcvt.q.w a0, a1 - fcvt.q.wu a0, a1 - fcvt.q.l a0, a1 - fcvt.q.lu a0, a1 - fsgnj.q a0, a1, a2 - fsgnjn.q a0, a1, a2 - fsgnjx.q a0, a1, a2 - feq.q a0, a1, a2 - flt.q a0, a1, a2 - fle.q a0, a1, a2 - fgt.q a0, a1, a2 - fge.q a0, a1, a2 - fneg.q a0, a0 - fabs.q a0, a0 - fclass.q a0, a1 + fadd.q a0, a2, a4 + fadd.q a0, a2, a4, rne + fsub.q a0, a2, a4 + fsub.q a0, a2, a4, rne + fmul.q a0, a2, a4 + fmul.q a0, a2, a4, rne + fdiv.q a0, a2, a4 + fdiv.q a0, a2, a4, rne + fsqrt.q a0, a2 + fsqrt.q a0, a2, rne + fmin.q a0, a2, a4 + fmax.q a0, a2, a4 + fmadd.q a0, a2, a4, a6 + fmadd.q a0, a2, a4, a6, rne + fnmadd.q a0, a2, a4, a6 + fnmadd.q a0, a2, a4, a6, rne + fmsub.q a0, a2, a4, a6 + fmsub.q a0, a2, a4, a6, rne + fnmsub.q a0, a2, a4, a6 + fnmsub.q a0, a2, a4, a6, rne + + fcvt.w.q a0, a2 + fcvt.w.q a0, a2, rne + fcvt.wu.q a0, a2 + fcvt.wu.q a0, a2, rne + fcvt.l.q a0, a2 + fcvt.l.q a0, a2, rne + fcvt.lu.q a0, a2 + fcvt.lu.q a0, a2, rne + fcvt.q.w a0, a2 + fcvt.q.wu a0, a2 + fcvt.q.l a0, a2 + fcvt.q.l a0, a2, rne + fcvt.q.lu a0, a2 + fcvt.q.lu a0, a2, rne + + fcvt.q.s a0, a2 + fcvt.q.d a0, a2 + fcvt.s.q a0, a2 + fcvt.s.q a0, a2, rne + fcvt.d.q a0, a2 + fcvt.d.q a0, a2, rne + + fsgnj.q a0, a2, a4 + fsgnjn.q a0, a2, a4 + fsgnjx.q a0, a2, a4 + feq.q a0, a2, a4 + flt.q a0, a2, a4 + fle.q a0, a2, a4 + fgt.q a0, a2, a4 + fge.q a0, a2, a4 + fneg.q a0, a2 + fabs.q a0, a2 + fclass.q a0, a2 -- 2.25.1 ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [REVIEW ONLY 2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions 2022-06-27 2:03 ` [PATCH v2 5/8] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI @ 2022-11-29 6:35 ` jiawei 0 siblings, 0 replies; 17+ messages in thread From: jiawei @ 2022-11-29 6:35 UTC (permalink / raw) To: Tsukasa OI; +Cc: Nelson Chu, Kito Cheng, Palmer Dabbelt, binutils > [DO NOT MERGE] > RISC-V Profiles are frozen but -- from my view -- this document will still > change in some way. Meanwhile, this patch should not be merged upstream. > This commit uses tentative version 1.0 (as there are no versions). > > RISC-V Profiles document defines number of "extensions" that indicate > certain platform properties/capabilities just like 'Zkt' extension from the > RISC-V cryptography extensions. > > This commit defines 19 platform property/capability extensions as defined > in the RISC-V Profiles documentation. > The version number is tentatively set to 1.0. > > The only exception: 'Ssstateen' extension is defined separately because it > defines a subset (supervisor/hypervisor view) of the 'Smstateen' extension. > > This is based on the latest version of RISC-V Profiles (version 0.9-draft): > <https: github.com="" riscv="" riscv-profiles="" commit="" 226b7f643067b29abc6723fac60d5f6d3f9eb901=""> > > [Definition] > > "Main memory regions": memory regions with both the cacheability > and coherence PMAs. > > [New Unprivileged Extensions] > > 1. 'Ziccif' > "Main memory regions" support instruction fetch and any instruction > fetches of naturally aligned power-of-2 sizes up to min(ILEN, XLEN) > are atomic. > 2. 'Ziccrse' > "Main memory regions" provide the eventual success guarantee for > LR/SC sequence. > 3. 'Ziccamoa' > "Main memory regions" support all AMO operations including atomic swap, > logical and arithmetic operations. > 4. 'Za64rs' > For LR/SC instructions, reservation sets are contiguous, naturally > aligned and at most 64-bytes in size. > 5. 'Za128rs' > Likewise, but reservation sets are at most 128-bytes in size. > 6. 'Zicclsm' > Misaligned loads / stores to "main memory regions" are supported. > Those include both regular scalar and vector access but does not include > AMOs and other specialized forms of memory access. > 7. 'Zic64b' > Cache blocks are (exactly) 64-bytes in size and naturally aligned. > > [New Privileged Extensions] > > 1. 'Svbare' > "satp" mode Bare is supported. > 2. 'Ssptead' > Page-fault exceptions are raised when a page is accessed when A bit is > clear, or written when D bit is clear. > 3. 'Ssccptr' > "Main memory regions" support hardware page-table reads. > 4. 'Sstvecd' > "stvec" mode Direct is supported. When "stvec" mode is Direct, > "stvec.BASE" is capable of holding any valid 4-byte aligned address. > 5. 'Sstvala' > "stval" is always written with a nonzero value whenever possible as > specified in the Privileged Architecture documentation > (version 20211203: see section 4.1.9). > 6. 'Ssu64xl' > "sstatus.UXL"=64 [sic]. > 7. 'Shcounterenw' > For any "hpmcounter" that is not read-only zero, the corresponding bit > in "hcounteren" is writable. > 8. 'Shvstvala' > Similar to 'Sstvala' but the same rule applies to "vstval". > 9. 'Shtvala' > "htval" is written with the faulting guest physical address as long as > permitted by the ISA (a bit similar to 'Sstvala' and 'Shvstvala'). > 10. 'Shvstvecd' > Similar to 'Sstvecd' but the same rule applies to "vstvec". > 11. 'Shvsatpa' > All translation modes supported in "satp" are also supported in "vsatp". > 12. 'Shgatpa' > For each supported virtual memory scheme SvNN supported in "satp", the > corresponding "hgatp" SvNNx4 mode is supported. The "hgatp" mode Bare > is also supported. > > [Implications] > > (Due to reservation set size constraints) > - 'Za64rs' -> 'Za128rs' > > (Due to the fact that a privileged "extension" directly refers a CSR) > - 'Svbare' -> 'Zicsr' > - 'Sstvecd' -> 'Zicsr' > - 'Sstvala' -> 'Zicsr' > - 'Ssu64xl' -> 'Zicsr' > > (Due to the fact that a privileged "extension" indirectly depends on CSRs) > - 'Ssptead' -> 'Zicsr' > - 'Ssccptr' -> 'Zicsr' > > (Due to the fact that a privileged "extension" is a hypervisor property) > - 'Shcounterenw' -> 'H' > - 'Shvstvala' -> 'H' > - 'Shtvala' -> 'H' > - 'Shvstvecd' -> 'H' > - 'Shvsatpa' -> 'H' > - 'Shgatpa' -> 'H' > > bfd/ChangeLog: > > * elfxx-riscv.c > (riscv_implicit_subsets): Add 13 implication rules. > (riscv_supported_std_z_ext) Add 7 property/capability extensions. > (riscv_supported_std_s_ext) Add 12 property/capability extensions. > --- > bfd/elfxx-riscv.c | 34 +++++++++++++++++++++++++++++++++- > 1 file changed, 33 insertions(+), 1 deletion(-) > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index 781b57cbd98..64811a138a3 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -1047,7 +1047,6 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = > {"g", "zicsr", check_implicit_always}, > {"g", "zifencei", check_implicit_always}, > {"m", "zmmul", check_implicit_always}, > - {"h", "zicsr", check_implicit_always}, > {"q", "d", check_implicit_always}, > {"v", "d", check_implicit_always}, > {"v", "zve64d", check_implicit_always}, > @@ -1083,6 +1082,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = > {"zhinx", "zhinxmin", check_implicit_always}, > {"zhinxmin", "zfinx", check_implicit_always}, > {"zfinx", "zicsr", check_implicit_always}, > + {"za64rs", "za128rs", check_implicit_always}, > {"zk", "zkn", check_implicit_always}, > {"zk", "zkr", check_implicit_always}, > {"zk", "zkt", check_implicit_always}, > @@ -1099,9 +1099,22 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = > {"zks", "zksh", check_implicit_always}, > {"smstateen", "ssstateen", check_implicit_always}, > {"smepmp", "zicsr", check_implicit_always}, > + {"shcounterenw", "h", check_implicit_always}, > + {"shgatpa", "h", check_implicit_always}, > + {"shtvala", "h", check_implicit_always}, > + {"shvsatpa", "h", check_implicit_always}, > + {"shvstvala", "h", check_implicit_always}, > + {"shvstvecd", "h", check_implicit_always}, > + {"h", "zicsr", check_implicit_always}, > + {"ssccptr", "zicsr", check_implicit_always}, > {"sscofpmf", "zicsr", check_implicit_always}, > + {"ssptead", "zicsr", check_implicit_always}, > {"ssstateen", "zicsr", check_implicit_always}, > {"sstc", "zicsr", check_implicit_always}, > + {"sstvala", "zicsr", check_implicit_always}, > + {"sstvecd", "zicsr", check_implicit_always}, > + {"ssu64xl", "zicsr", check_implicit_always}, > + {"svbare", "zicsr", check_implicit_always}, > {NULL, NULL, NULL} > }; > > @@ -1159,6 +1172,11 @@ static struct riscv_supported_ext riscv_supported_std_ext[] = > > static struct riscv_supported_ext riscv_supported_std_z_ext[] = > { > + {"zic64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"ziccamoa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"ziccif", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"zicclsm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"ziccrse", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > @@ -1168,6 +1186,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = > {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, > {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, > {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > @@ -1217,11 +1237,23 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = > > static struct riscv_supported_ext riscv_supported_std_s_ext[] = > { > + {"shcounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"shgatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"shtvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"shvsatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"shvstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"shvstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"ssptead", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"ssu64xl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"svbare", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"svpbmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > -- > 2.37.2 LGTM, since some extensions are optional in profile and not documented yet, I'm not sure if we need to add all of them here, anyway thanks for your works. </https:> ^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2023-07-31 2:56 UTC | newest] Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-11-03 12:26 [REVIEW ONLY 0/2] NEAR RATIFICATION RISC-V: Extensions from the RISC-V Profiles Tsukasa OI 2022-11-03 12:26 ` [REVIEW ONLY 1/2] NEAR-RATIFICATION RISC-V: Add 'Ssstateen' extension and its CSRs Tsukasa OI 2022-11-03 12:26 ` [REVIEW ONLY 2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions Tsukasa OI 2022-11-03 13:11 ` [REVIEW ONLY 0/2] NEAR RATIFICATION RISC-V: Extensions from the RISC-V Profiles Nelson Chu 2022-11-03 13:20 ` Tsukasa OI 2022-11-19 2:56 ` Tsukasa OI 2023-01-30 6:35 ` [PATCH v2 0/1] " Tsukasa OI 2023-01-30 6:35 ` [PATCH v2 1/1] RISC-V: Add platform property/capability extensions Tsukasa OI 2023-01-30 7:11 ` [PATCH v3 0/1] RISC-V: Extensions from the RISC-V Profiles Tsukasa OI 2023-01-30 7:11 ` [PATCH v3 1/1] RISC-V: Add platform property/capability extensions Tsukasa OI 2023-07-26 0:05 ` [PATCH v4 0/1] RISC-V: Extensions from the RISC-V Profiles Tsukasa OI 2023-07-26 0:05 ` [PATCH v4 1/1] RISC-V: Add platform property/capability extensions Tsukasa OI 2023-07-26 0:47 ` Palmer Dabbelt 2023-07-26 1:02 ` Tsukasa OI 2023-07-31 2:56 ` Tsukasa OI 2023-01-31 4:46 ` [PATCH v2 0/1] RISC-V: Extensions from the RISC-V Profiles Nelson Chu -- strict thread matches above, loose matches on Subject: below -- 2022-06-27 2:03 [PATCH v2 0/8] RISC-V: Combined floating point enhancements Tsukasa OI 2022-06-27 2:03 ` [PATCH v2 5/8] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI 2022-11-29 6:35 ` [REVIEW ONLY 2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions jiawei
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