* [PATCH 0/2] Disassembler styling for ARM
@ 2022-09-16 13:21 Andrew Burgess
2022-09-16 13:21 ` [PATCH 1/2] opcodes/arm: add missing ';' characters Andrew Burgess
` (2 more replies)
0 siblings, 3 replies; 15+ messages in thread
From: Andrew Burgess @ 2022-09-16 13:21 UTC (permalink / raw)
To: binutils; +Cc: Andrew Burgess
This series adds disassembler styling for ARM.
The first patch fixes what I believe is a missing comment marker (';')
in a couple of instructions.
The second patch adds styling support.
All thoughts and feedback welcome.
Thanks,
Andrew
---
Andrew Burgess (2):
opcodes/arm: add missing ';' characters
opcodes/arm: add disassembler styling for arm
.../testsuite/binutils-all/arm/objdump.exp | 4 +-
gas/testsuite/gas/arm/armv8.1-m.main-fp.d | 8 +-
gas/testsuite/gas/arm/vfp1xD.d | 16 +-
gas/testsuite/gas/arm/vfp1xD_t2.d | 8 +-
opcodes/arm-dis.c | 2628 ++++++++++-------
5 files changed, 1644 insertions(+), 1020 deletions(-)
--
2.25.4
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/2] opcodes/arm: add missing ';' characters
2022-09-16 13:21 [PATCH 0/2] Disassembler styling for ARM Andrew Burgess
@ 2022-09-16 13:21 ` Andrew Burgess
2022-09-20 15:13 ` Richard Earnshaw
2022-09-16 13:21 ` [PATCH 2/2] opcodes/arm: add disassembler styling for arm Andrew Burgess
2022-10-02 10:47 ` [PATCHv2 0/2] Disassembler styling for ARM Andrew Burgess
2 siblings, 1 reply; 15+ messages in thread
From: Andrew Burgess @ 2022-09-16 13:21 UTC (permalink / raw)
To: binutils; +Cc: Andrew Burgess
I spotted a couple of places where the ARM disassembler produces what
seems to be some comment style text '@ Impl Def' without including a
comment character ';'. In other places where we have similar messages
a comment character is emitted, so I suspect this was just an
oversight.
Fixed in this commit by adding two new comment characters, and
updating the expected test results.
---
gas/testsuite/gas/arm/armv8.1-m.main-fp.d | 8 ++++----
gas/testsuite/gas/arm/vfp1xD.d | 16 ++++++++--------
gas/testsuite/gas/arm/vfp1xD_t2.d | 8 ++++----
opcodes/arm-dis.c | 8 ++++----
4 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/gas/testsuite/gas/arm/armv8.1-m.main-fp.d b/gas/testsuite/gas/arm/armv8.1-m.main-fp.d
index dd69e0d5252..e8d57ab5fd1 100644
--- a/gas/testsuite/gas/arm/armv8.1-m.main-fp.d
+++ b/gas/testsuite/gas/arm/armv8.1-m.main-fp.d
@@ -252,13 +252,13 @@ Disassembly of section .text:
0+3b2 <[^>]*> bf04 itt eq
0+3b4 <[^>]*> ee01 9a90 (vmoveq|fmsreq) s3, r9
0+3b8 <[^>]*> eee0 8a10 (vmsreq|fmxreq) fpsid, r8
-0+3bc <[^>]*> eef9 0a10 (vmrs|fmrx) r0, fpinst @ Impl def
-0+3c0 <[^>]*> eefa 0a10 (vmrs|fmrx) r0, fpinst2 @ Impl def
+0+3bc <[^>]*> eef9 0a10 (vmrs|fmrx) r0, fpinst ;@ Impl def
+0+3c0 <[^>]*> eefa 0a10 (vmrs|fmrx) r0, fpinst2 ;@ Impl def
0+3c4 <[^>]*> eef7 0a10 (vmrs|fmrx) r0, mvfr0
0+3c8 <[^>]*> eef6 0a10 (vmrs|fmrx) r0, mvfr1
0+3cc <[^>]*> eefc 0a10 (vmrs|fmrx) r0, (<impl def 0xc>|vpr)
-0+3d0 <[^>]*> eee9 0a10 (vmsr|fmxr) fpinst, r0 @ Impl def
-0+3d4 <[^>]*> eeea 0a10 (vmsr|fmxr) fpinst2, r0 @ Impl def
+0+3d0 <[^>]*> eee9 0a10 (vmsr|fmxr) fpinst, r0 ;@ Impl def
+0+3d4 <[^>]*> eeea 0a10 (vmsr|fmxr) fpinst2, r0 ;@ Impl def
0+3d8 <[^>]*> eee7 0a10 (vmsr|fmxr) mvfr0, r0
0+3dc <[^>]*> eee6 0a10 (vmsr|fmxr) mvfr1, r0
0+3e0 <[^>]*> eeec 0a10 (vmsr|fmxr) (<impl def 0xc>|vpr), r0
diff --git a/gas/testsuite/gas/arm/vfp1xD.d b/gas/testsuite/gas/arm/vfp1xD.d
index 079f7a17e59..2c33e14edc7 100644
--- a/gas/testsuite/gas/arm/vfp1xD.d
+++ b/gas/testsuite/gas/arm/vfp1xD.d
@@ -239,13 +239,13 @@ Disassembly of section .text:
0+394 <[^>]*> 0ef09a10 (vmrseq|fmrxeq) r9, fpsid
0+398 <[^>]*> 0e019a90 (vmoveq|fmsreq) s3, r9
0+39c <[^>]*> 0ee08a10 (vmsreq|fmxreq) fpsid, r8
-0+3a0 <[^>]*> eef90a10 (vmrs|fmrx) r0, fpinst @ Impl def
-0+3a4 <[^>]*> eefa0a10 (vmrs|fmrx) r0, fpinst2 @ Impl def
+0+3a0 <[^>]*> eef90a10 (vmrs|fmrx) r0, fpinst ;@ Impl def
+0+3a4 <[^>]*> eefa0a10 (vmrs|fmrx) r0, fpinst2 ;@ Impl def
0+3a8 <[^>]*> eef70a10 (vmrs|fmrx) r0, mvfr0
0+3ac <[^>]*> eef60a10 (vmrs|fmrx) r0, mvfr1
0+3b0 <[^>]*> eefc0a10 (vmrs|fmrx) r0, (vpr|<impl def 0xc>)
-0+3b4 <[^>]*> eee90a10 (vmsr|fmxr) fpinst, r0 @ Impl def
-0+3b8 <[^>]*> eeea0a10 (vmsr|fmxr) fpinst2, r0 @ Impl def
+0+3b4 <[^>]*> eee90a10 (vmsr|fmxr) fpinst, r0 ;@ Impl def
+0+3b8 <[^>]*> eeea0a10 (vmsr|fmxr) fpinst2, r0 ;@ Impl def
0+3bc <[^>]*> eee70a10 (vmsr|fmxr) mvfr0, r0
0+3c0 <[^>]*> eee60a10 (vmsr|fmxr) mvfr1, r0
0+3c4 <[^>]*> eeec0a10 (vmsr|fmxr) (vpr|<impl def 0xc>), r0
@@ -280,15 +280,15 @@ Disassembly of section .text:
0+438 <[^>]*> eee1ea10 vmsr fpscr, lr
0+43c <[^>]*> eee01a10 vmsr fpsid, r1
0+440 <[^>]*> eee82a10 vmsr fpexc, r2
-0+444 <[^>]*> eee93a10 vmsr fpinst, r3 @ Impl def
-0+448 <[^>]*> eeea4a10 vmsr fpinst2, r4 @ Impl def
+0+444 <[^>]*> eee93a10 vmsr fpinst, r3 ;@ Impl def
+0+448 <[^>]*> eeea4a10 vmsr fpinst2, r4 ;@ Impl def
0+44c <[^>]*> eeef5a10 vmsr (c15|<impl def 0xf>|fpcxt_s), r5
0+450 <[^>]*> eef03a10 vmrs r3, fpsid
0+454 <[^>]*> eef64a10 vmrs r4, mvfr1
0+458 <[^>]*> eef75a10 vmrs r5, mvfr0
0+45c <[^>]*> eef86a10 vmrs r6, fpexc
-0+460 <[^>]*> eef97a10 vmrs r7, fpinst @ Impl def
-0+464 <[^>]*> eefa8a10 vmrs r8, fpinst2 @ Impl def
+0+460 <[^>]*> eef97a10 vmrs r7, fpinst ;@ Impl def
+0+464 <[^>]*> eefa8a10 vmrs r8, fpinst2 ;@ Impl def
0+468 <[^>]*> eeff9a10 vmrs r9, (c15|<impl def 0xf>|fpcxt_s)
0+46c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
0+470 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/vfp1xD_t2.d b/gas/testsuite/gas/arm/vfp1xD_t2.d
index 248185d4486..634fbb00518 100644
--- a/gas/testsuite/gas/arm/vfp1xD_t2.d
+++ b/gas/testsuite/gas/arm/vfp1xD_t2.d
@@ -253,13 +253,13 @@ Disassembly of section .text:
0+3b2 <[^>]*> bf04 itt eq
0+3b4 <[^>]*> ee01 9a90 (vmoveq|fmsreq) s3, r9
0+3b8 <[^>]*> eee0 8a10 (vmsreq|fmxreq) fpsid, r8
-0+3bc <[^>]*> eef9 0a10 (vmrs|fmrx) r0, fpinst @ Impl def
-0+3c0 <[^>]*> eefa 0a10 (vmrs|fmrx) r0, fpinst2 @ Impl def
+0+3bc <[^>]*> eef9 0a10 (vmrs|fmrx) r0, fpinst ;@ Impl def
+0+3c0 <[^>]*> eefa 0a10 (vmrs|fmrx) r0, fpinst2 ;@ Impl def
0+3c4 <[^>]*> eef7 0a10 (vmrs|fmrx) r0, mvfr0
0+3c8 <[^>]*> eef6 0a10 (vmrs|fmrx) r0, mvfr1
0+3cc <[^>]*> eefc 0a10 (vmrs|fmrx) r0, (<impl def 0xc>|vpr)
-0+3d0 <[^>]*> eee9 0a10 (vmsr|fmxr) fpinst, r0 @ Impl def
-0+3d4 <[^>]*> eeea 0a10 (vmsr|fmxr) fpinst2, r0 @ Impl def
+0+3d0 <[^>]*> eee9 0a10 (vmsr|fmxr) fpinst, r0 ;@ Impl def
+0+3d4 <[^>]*> eeea 0a10 (vmsr|fmxr) fpinst2, r0 ;@ Impl def
0+3d8 <[^>]*> eee7 0a10 (vmsr|fmxr) mvfr0, r0
0+3dc <[^>]*> eee6 0a10 (vmsr|fmxr) mvfr1, r0
0+3e0 <[^>]*> eeec 0a10 (vmsr|fmxr) (<impl def 0xc>|vpr), r0
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 684c74f7f20..5de78cec33d 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -897,9 +897,9 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
+ 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t;@ Impl def"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
+ 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t;@ Impl def"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -925,9 +925,9 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
+ 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t;@ Impl def"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
+ 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t;@ Impl def"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
--
2.25.4
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/2] opcodes/arm: add disassembler styling for arm
2022-09-16 13:21 [PATCH 0/2] Disassembler styling for ARM Andrew Burgess
2022-09-16 13:21 ` [PATCH 1/2] opcodes/arm: add missing ';' characters Andrew Burgess
@ 2022-09-16 13:21 ` Andrew Burgess
2022-10-02 10:47 ` [PATCHv2 0/2] Disassembler styling for ARM Andrew Burgess
2 siblings, 0 replies; 15+ messages in thread
From: Andrew Burgess @ 2022-09-16 13:21 UTC (permalink / raw)
To: binutils; +Cc: Andrew Burgess
This commit adds disassembler styling for the ARM architecture.
The ARM disassembler is driven by several instruction tables,
e.g. cde_opcodes, coprocessor_opcodes, neon_opcodes, etc
The type for elements in each table can vary, but they all have one
thing in common, a 'const char * assembler' field. This field
contains a string that describes the assembler syntax of the
instruction.
Embedded within that assembler syntax are various escape characters,
prefixed with a '%'. Here's an example of a very simple instruction
from the arm_opcodes table:
"pld\t%a"
The '%a' indicates a particular type of operand, the function
print_insn_arm processes the arm_opcodes table, and includes a switch
statement that handles the '%a' operand, and takes care of printing
the correct value for that instruction operand.
It is worth noting that there are many print_* functions, each
function handles a single *_opcodes table, and includes its own switch
statement for operand handling. As a result, every *_opcodes table
uses a different mapping for the operand escape sequences. This means
that '%a' might print an address for one *_opcodes table, but in a
different *_opcodes table '%a' might print a register operand.
Notice as well that in our example above, the instruction mnemonic
'pld' is embedded within the assembler string. Some instructions also
include comments within the assembler string, for example, also from
the arm_opcodes table:
"nop\t\t\t; (mov r0, r0)"
here, everything after the ';' is a comment that is displayed at the
end of the instruction disassembly.
The next complexity is that the meaning of some escape sequences is
not necessarily fixed. Consider these two examples from arm_opcodes:
"ldrex%c\tr%12-15d, [%16-19R]"
"setpan\t#%9-9d"
Here, the '%d' escape is used with a bitfield modifier, '%12-15d' in
the first instruction, and '%9-9d' in the second instruction, but,
both of these are the '%d' escape.
However, in the first instruction, the '%d' is used to print a
register number, notice the 'r' immediately before the '%d'. In the
second instruction the '%d' is used to print an immediate, notice the
'#' just before the '%d'.
We have two problems here, first, the '%d' needs to know if it should
use register style or immediate style, and secondly, the 'r' and '#'
characters also need to be styled appropriately.
The final thing we must consider is that some escape codes result in
more than just a single operand being printed, for example, the '%q'
operand as used in arm_opcodes ends up calling arm_decode_shift, which
can print a register name, a shift type, and a shift amount, this
could end up using register, sub-mnemonic, and immediate styles, as
well as the text style for things like ',' between the different
parts.
I propose a three layer approach to adding styling:
(1) Basic state machine:
When we start printing an instruction we should maintain the idea
of a 'base_style'. Every character from the assembler string will
be printed using the base_style.
The base_style will start as mnemonic, as each instruction starts
with an instruction mnemonic. When we encounter the first '\t'
character, the base_style will change to text. When we encounter
the first ';' the base_style will change to comment_start.
This simple state machine ensures that for simple instructions the
basic parts, except for the operands themselves, will be printed in
the correct style.
(2) Simple operand styling:
For operands that only have a single meaning, or which expand to
multiple parts, all of which have a consistent meaning, then I
will simply update the operand printing code to print the operand
with the correct style. This will cover a large number of the
operands, and is the most consistent with how styling has been
added to previous architectures.
(3) New styling syntax in assembler strings:
For cases like the '%s' that I describe above, I propose adding a
new extension to the assembler syntax. This extension will allow
me to temporarily change the base_style. Some operands, like
'%d', will then print using the base_style rather than using a
fixed style.
Here are the two examples from above that use '%d', updated with
the new syntax extension:
"ldrex%c\t%{R:r%12-15d%}, [%16-19R]"
"setpan\t%{I:#%9-9d%}"
The syntax has the general form '%{X:....%}' where the 'X'
character changes to indicate a different style. In the first
instruction I use '%{R:...%}' to change base_style to the register
style, and in the second '%{I:...%}' changes base_style to
immediate style.
Notice that the 'r' and '#' characters are included within the new
style group, this ensures that these characters are printed with
the correct style rather than as text.
The function decode_base_style maps from character to style. I've
included a character for each style for completeness, though only
a small number of styles are currently used.
I have updated arm-dis.c to the above scheme, and checked all of the
tests in gas/testsuite/gas/arm/, and the styling looks reasonable.
There are no regressions on the ARM gas/binutils/ld tests that I can
see, so I don't believe I've changed the output layout at all. There
were two binutils tests for which I needed to force the disassembler
styling off.
I can't guarantee that I've not missed some untested corners of the
disassembler, or that I might have just missed some incorrectly styled
output when reviewing the test results, but I don't believe I've
introduced any changes that could break the disassembler - the worst
should be some aspect is not styled correctly.
---
.../testsuite/binutils-all/arm/objdump.exp | 4 +-
opcodes/arm-dis.c | 2628 ++++++++++-------
2 files changed, 1628 insertions(+), 1004 deletions(-)
diff --git a/binutils/testsuite/binutils-all/arm/objdump.exp b/binutils/testsuite/binutils-all/arm/objdump.exp
index 9cd057e60f1..c667577f19e 100644
--- a/binutils/testsuite/binutils-all/arm/objdump.exp
+++ b/binutils/testsuite/binutils-all/arm/objdump.exp
@@ -51,7 +51,7 @@ if {![binutils_assemble $srcdir/$subdir/thumb2-cond.s tmpdir/thumb2-cond.o]} the
fail "thumb2-cond test1"
}
- set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS --disassemble --start-address=10 $objfile"]
+ set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS --disassemble --disassembler-color=off --start-address=10 $objfile"]
set want "bx\[ \t\]*lr"
@@ -78,7 +78,7 @@ if {![binutils_assemble $srcdir/$subdir/simple.s tmpdir/simple.o]} then {
# Make sure multiple disassemblies come out the same
- set got [binutils_run $OBJDUMP "-dr $objfile $objfile"]
+ set got [binutils_run $OBJDUMP "-dr --disassembler-color=off $objfile $objfile"]
set want "$objfile:\[ \]*file format.*$objfile:\[ \]*file format.*push.*add.*sub.*str.*add.*ldmfd"
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 5de78cec33d..06b3f7811cd 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -490,45 +490,45 @@ static const struct cdeopcode32 cde_opcodes[] =
/* Custom Datapath Extension instructions. */
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xee000000, 0xefc00840,
- "cx1%a\t%p, %12-15n, #%0-5,7,16-21d"),
+ "cx1%a\t%p, %12-15n, %{I:#%0-5,7,16-21d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xee000040, 0xefc00840,
- "cx1d%a\t%p, %12-15S, %12-15T, #%0-5,7,16-21d"),
+ "cx1d%a\t%p, %12-15S, %12-15T, %{I:#%0-5,7,16-21d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xee400000, 0xefc00840,
- "cx2%a\t%p, %12-15n, %16-19n, #%0-5,7,20-21d"),
+ "cx2%a\t%p, %12-15n, %16-19n, %{I:#%0-5,7,20-21d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xee400040, 0xefc00840,
- "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, #%0-5,7,20-21d"),
+ "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, %{I:#%0-5,7,20-21d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xee800000, 0xef800840,
- "cx3%a\t%p, %0-3n, %16-19n, %12-15n, #%4-5,7,20-22d"),
+ "cx3%a\t%p, %0-3n, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xee800040, 0xef800840,
- "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, #%4-5,7,20-22d"),
+ "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xec200000, 0xeeb00840,
- "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19d"),
+ "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xec200040, 0xeeb00840,
- "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19,24d"),
+ "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19,24d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xec300000, 0xeeb00840,
- "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19d"),
+ "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xec300040, 0xeeb00840,
- "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19,24d"),
+ "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19,24d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xec800000, 0xee800840,
- "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21d"),
+ "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xec800040, 0xee800840,
- "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21,24d"),
+ "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21,24d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
@@ -539,16 +539,16 @@ static const struct sopcode32 coprocessor_opcodes[] =
/* XScale instructions. */
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200010, 0x0fff0ff0,
- "mia%c\tacc0, %0-3r, %12-15r"},
+ "mia%c\t%{R:acc0%}, %0-3r, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e280010, 0x0fff0ff0,
- "miaph%c\tacc0, %0-3r, %12-15r"},
+ "miaph%c\t%{R:acc0%}, %0-3r, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
+ 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\t%{R:acc0%}, %0-3r, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
+ 0x0c400000, 0x0ff00fff, "mar%c\t%{R:acc0%}, %12-15r, %16-19r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
+ 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, %{R:acc0%}"},
/* Intel Wireless MMX technology instructions. */
{ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
@@ -557,11 +557,11 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
+ 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, %{I:#%0-2d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
+ 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, %{I:#%0-2d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
+ 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, %{I:#%0-2d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
@@ -593,7 +593,7 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
+ 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, %{I:#%20-22d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
@@ -621,7 +621,7 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
+ 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, %{I:#%21-23d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
@@ -651,7 +651,7 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
+ 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
@@ -659,21 +659,21 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
+ 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, %{I:#%Z%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
+ 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
+ 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
+ 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
@@ -860,17 +860,17 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
+ 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%{R:%16-19,7D[%21d]%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
+ 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %{R:%16-19,7D[%21d]%}"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
+ 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%{R:%16-19,7D[%6,21d]%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
+ 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %{R:%16-19,7D[%6,21d]%}"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
+ 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%{R:%16-19,7D[%5,6,21d]%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
+ 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %{R:%16-19,7D[%5,6,21d]%}"},
/* Half-precision conversion instructions. */
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
@@ -883,63 +883,63 @@ static const struct sopcode32 coprocessor_opcodes[] =
/* Floating point coprocessor (VFP) instructions. */
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
+ 0x0ee00a10, 0x0fff0fff, "vmsr%c\t%{R:fpsid%}, %12-15r"},
{ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
- 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
+ 0x0ee10a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr%}, %12-15r"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
+ 0x0ee20a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr_nzcvqc%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
+ 0x0ee60a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr1%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
+ 0x0ee70a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr0%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
+ 0x0ee50a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr2%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
+ 0x0ee80a10, 0x0fff0fff, "vmsr%c\t%{R:fpexc%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t;@ Impl def"},
+ 0x0ee90a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst%}, %12-15r\t;@ Impl def"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t;@ Impl def"},
+ 0x0eea0a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst2%}, %12-15r\t;@ Impl def"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
- 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
+ 0x0eec0a10, 0x0fff0fff, "vmsr%c\t%{R:vpr%}, %12-15r"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
- 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
+ 0x0eed0a10, 0x0fff0fff, "vmsr%c\t%{R:p0%}, %12-15r"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
+ 0x0eee0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_ns%}, %12-15r"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
+ 0x0eef0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_s%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
+ 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpsid%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
+ 0x0ef1fa10, 0x0fffffff, "vmrs%c\t%{R:APSR_nzcv%}, %{R:fpscr%}"},
{ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
- 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
+ 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
+ 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr_nzcvqc%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
+ 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr2%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
+ 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr1%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
+ 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr0%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
+ 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpexc%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t;@ Impl def"},
+ 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst%}\t;@ Impl def"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t;@ Impl def"},
+ 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst2%}\t;@ Impl def"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
- 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
+ 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:vpr%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
- 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
+ 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:p0%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
+ 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_ns%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
+ 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_s%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
- 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
+ 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%{I:%21d%}], %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
- 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
+ 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%{I:%21d%}]"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
@@ -949,9 +949,9 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
+ 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, %{I:#0.0%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
- 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
+ 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, %{I:#0.0%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
@@ -981,23 +981,23 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
- 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
+ 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
- 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
+ 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, %{I:#%5,0-3k%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
- 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
+ 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, %{I:#%5,0-3k%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
- 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
+ 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, %{I:#%5,0-3k%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
- 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
+ 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, %{I:#%0-3,16-19E%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
- 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
+ 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, %{I:#%0-3,16-19E%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
@@ -1043,177 +1043,177 @@ static const struct sopcode32 coprocessor_opcodes[] =
/* Cirrus coprocessor instructions. */
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
+ 0x0d100400, 0x0f500f00, "cfldrs%c\t%{R:mvf%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
+ 0x0c100400, 0x0f500f00, "cfldrs%c\t%{R:mvf%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
+ 0x0d500400, 0x0f500f00, "cfldrd%c\t%{R:mvd%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
+ 0x0c500400, 0x0f500f00, "cfldrd%c\t%{R:mvd%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
+ 0x0d100500, 0x0f500f00, "cfldr32%c\t%{R:mvfx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
+ 0x0c100500, 0x0f500f00, "cfldr32%c\t%{R:mvfx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
+ 0x0d500500, 0x0f500f00, "cfldr64%c\t%{R:mvdx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
+ 0x0c500500, 0x0f500f00, "cfldr64%c\t%{R:mvdx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
+ 0x0d000400, 0x0f500f00, "cfstrs%c\t%{R:mvf%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
+ 0x0c000400, 0x0f500f00, "cfstrs%c\t%{R:mvf%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
+ 0x0d400400, 0x0f500f00, "cfstrd%c\t%{R:mvd%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
+ 0x0c400400, 0x0f500f00, "cfstrd%c\t%{R:mvd%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
+ 0x0d000500, 0x0f500f00, "cfstr32%c\t%{R:mvfx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
+ 0x0c000500, 0x0f500f00, "cfstr32%c\t%{R:mvfx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
+ 0x0d400500, 0x0f500f00, "cfstr64%c\t%{R:mvdx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
+ 0x0c400500, 0x0f500f00, "cfstr64%c\t%{R:mvdx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
+ 0x0e000450, 0x0ff00ff0, "cfmvsr%c\t%{R:mvf%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
+ 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
+ 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\t%{R:mvd%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
+ 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
+ 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\t%{R:mvd%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
+ 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
+ 0x0e000510, 0x0ff00fff, "cfmv64lr%c\t%{R:mvdx%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
+ 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
+ 0x0e000530, 0x0ff00fff, "cfmv64hr%c\t%{R:mvdx%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
+ 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
+ 0x0e200440, 0x0ff00fff, "cfmval32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
+ 0x0e100440, 0x0ff00fff, "cfmv32al%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
+ 0x0e200460, 0x0ff00fff, "cfmvam32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
+ 0x0e100460, 0x0ff00fff, "cfmv32am%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
+ 0x0e200480, 0x0ff00fff, "cfmvah32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
+ 0x0e100480, 0x0ff00fff, "cfmv32ah%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
+ 0x0e2004a0, 0x0ff00fff, "cfmva32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
+ 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
+ 0x0e2004c0, 0x0ff00fff, "cfmva64%c\t%{R:mvax%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
+ 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\t%{R:mvdx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
+ 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\t%{R:dspsc%}, %{R:mvdx%12-15d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
+ 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\t%{R:mvdx%12-15d%}, %{R:dspsc%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
+ 0x0e000400, 0x0ff00fff, "cfcpys%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
+ 0x0e000420, 0x0ff00fff, "cfcpyd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
+ 0x0e000460, 0x0ff00fff, "cfcvtsd%c\t%{R:mvd%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
+ 0x0e000440, 0x0ff00fff, "cfcvtds%c\t%{R:mvf%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
+ 0x0e000480, 0x0ff00fff, "cfcvt32s%c\t%{R:mvf%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
+ 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\t%{R:mvd%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
+ 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\t%{R:mvf%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
+ 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\t%{R:mvd%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
+ 0x0e100580, 0x0ff00fff, "cfcvts32%c\t%{R:mvfx%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
+ 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\t%{R:mvfx%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
+ 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\t%{R:mvfx%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
+ 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\t%{R:mvfx%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
+ 0x0e000550, 0x0ff00ff0, "cfrshl32%c\t%{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
+ 0x0e000570, 0x0ff00ff0, "cfrshl64%c\t%{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
+ 0x0e000500, 0x0ff00f10, "cfsh32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{I:#%I%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
+ 0x0e200500, 0x0ff00f10, "cfsh64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{I:#%I%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
+ 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
+ 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
+ 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
+ 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
+ 0x0e300400, 0x0ff00fff, "cfabss%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
+ 0x0e300420, 0x0ff00fff, "cfabsd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
+ 0x0e300440, 0x0ff00fff, "cfnegs%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
+ 0x0e300460, 0x0ff00fff, "cfnegd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
+ 0x0e300480, 0x0ff00ff0, "cfadds%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
+ 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
+ 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
+ 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
+ 0x0e100400, 0x0ff00ff0, "cfmuls%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
+ 0x0e100420, 0x0ff00ff0, "cfmuld%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
+ 0x0e300500, 0x0ff00fff, "cfabs32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
+ 0x0e300520, 0x0ff00fff, "cfabs64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
+ 0x0e300540, 0x0ff00fff, "cfneg32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
+ 0x0e300560, 0x0ff00fff, "cfneg64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ 0x0e300580, 0x0ff00ff0, "cfadd32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
+ 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
+ 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ 0x0e100500, 0x0ff00ff0, "cfmul32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
+ 0x0e100520, 0x0ff00ff0, "cfmul64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ 0x0e100540, 0x0ff00ff0, "cfmac32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ 0x0e100560, 0x0ff00ff0, "cfmsc32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000600, 0x0ff00f10,
- "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ "cfmadd32%c\t%{R:mvax%5-7d%}, %{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100600, 0x0ff00f10,
- "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ "cfmsub32%c\t%{R:mvax%5-7d%}, %{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200600, 0x0ff00f10,
- "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ "cfmadda32%c\t%{R:mvax%5-7d%}, %{R:mvax%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300600, 0x0ff00f10,
- "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ "cfmsuba32%c\t%{R:mvax%5-7d%}, %{R:mvax%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
/* VFP Fused multiply add instructions. */
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
@@ -1262,25 +1262,25 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
/* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
+ 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
+ 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
+ 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
+ 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
+ 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
+ 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
+ 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20'90%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
+ 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20?21%20?780%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
+ 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20'90%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
+ 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20?21%20?780%}"},
/* BFloat16 instructions. */
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
@@ -1290,25 +1290,25 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
- 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
+ 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}"},
/* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
+ 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
+ 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
+ 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
+ 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
+ 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
+ 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
+ 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
+ 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
/* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
cp_num: bit <11:8> == 0b1001.
@@ -1320,11 +1320,11 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
+ 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, %{I:#0.0%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
+ 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
+ 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, %{I:#%5,0-3k%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
@@ -1362,7 +1362,7 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
+ 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, %{I:#%0-3,16-19E%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
@@ -1398,49 +1398,49 @@ static const struct sopcode32 generic_coprocessor_opcodes[] =
{
/* Generic coprocessor instructions. */
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
- 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
+ 0x0c400000, 0x0ff00000, "mcrr%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19r, %{R:cr%0-3d%}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
0x0c500000, 0x0ff00000,
- "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
+ "mrrc%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e000000, 0x0f000010,
- "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
+ "cdp%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e10f010, 0x0f10f010,
- "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
+ "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %{R:APSR_nzcv%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e100010, 0x0f100010,
- "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
+ "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e000010, 0x0f100010,
- "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
+ "mcr%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
- 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
+ 0x0c000000, 0x0e100000, "stc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
- 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
+ 0x0c100000, 0x0e100000, "ldc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
/* V6 coprocessor instructions. */
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0xfc500000, 0xfff00000,
- "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
+ "mrrc2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0xfc400000, 0xfff00000,
- "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
+ "mcrr2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19R, %{R:cr%0-3d%}"},
/* V5 coprocessor instructions. */
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
- 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
+ 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
- 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
+ 0xfc000000, 0xfe100000, "stc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe000000, 0xff000010,
- "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
+ "cdp2%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe000010, 0xff100010,
- "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
+ "mcr2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe100010, 0xff100010,
- "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
+ "mrc2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
{ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
};
@@ -1482,10 +1482,10 @@ static const struct opcode32 neon_opcodes[] =
/* Extract. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2b00840, 0xffb00850,
- "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
+ "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2b00000, 0xffb00810,
- "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
+ "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
/* Data transfer between ARM and NEON registers. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
@@ -1503,11 +1503,11 @@ static const struct opcode32 neon_opcodes[] =
/* Move data element to all lanes. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
+ 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %{R:%0-3,5D[%19d]%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
+ 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %{R:%0-3,5D[%18-19d]%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
+ 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %{R:%0-3,5D[%17-19d]%}"},
/* Table lookup. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
@@ -1535,7 +1535,7 @@ static const struct opcode32 neon_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
- 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
+ 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
@@ -1543,7 +1543,7 @@ static const struct opcode32 neon_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
- 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
+ 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %{R:%0-2D[%3,5d]%}"},
/* Matrix Multiply instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
@@ -1555,9 +1555,9 @@ static const struct opcode32 neon_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
- 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
+ 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
- 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
+ 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
/* Two registers, miscellaneous. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
@@ -1604,7 +1604,7 @@ static const struct opcode32 neon_opcodes[] =
0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b20300, 0xffb30fd0,
- "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
+ "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, %{I:#%18-19S2%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
@@ -1634,15 +1634,15 @@ static const struct opcode32 neon_opcodes[] =
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
+ 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
+ 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
+ 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
+ 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
+ 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
@@ -1881,128 +1881,128 @@ static const struct opcode32 neon_opcodes[] =
/* Two registers and a shift amount. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
+ 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
+ 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
+ 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
+ 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
+ 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2880950, 0xfeb80fd0,
- "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
+ "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
+ 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, %{I:#%16-18d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
+ 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
+ 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
+ 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
+ 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
+ 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
+ 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
+ 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
+ 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
+ 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2900950, 0xfeb00fd0,
- "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
+ "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
+ 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, %{I:#%16-19d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
+ 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
+ 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
+ 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
+ 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
+ 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
+ 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
+ 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
+ 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
+ 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
+ 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
+ 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
+ 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, %{I:#%16-20d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
+ 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
+ 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
+ 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
+ 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
+ 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
+ 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
+ 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
+ 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00950, 0xfea00fd0,
- "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
+ "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
+ 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
+ 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
+ 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
+ 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
+ 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
+ 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
+ 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
+ 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
+ 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
+ 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
+ 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
+ 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
+ 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00e10, 0xfea00e90,
- "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf2a00c10, 0xfea00e90,
- "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
+ "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
/* Three registers of different lengths. */
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
@@ -2372,13 +2372,13 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCADD_FP,
0xfc800840, 0xfea11f51,
- "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
+ "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%24o%}"},
/* Vector VCADD. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCADD_VEC,
0xfe000f00, 0xff810f51,
- "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
+ "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
/* Vector VCLS. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -2396,7 +2396,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCMLA_FP,
0xfc200840, 0xfe211f51,
- "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
+ "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%23-24o%}"},
/* Vector VCMP floating point T1. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
@@ -2505,7 +2505,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCMUL_FP,
0xee300e00, 0xefb10f50,
- "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
+ "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%0,12o%}"},
/* Vector VCTP. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -2529,7 +2529,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCVT_FP_FIX_VEC,
0xef800c50, 0xef801cd1,
- "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
+ "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, %{I:#%16-21k%}"},
/* Vector VCVT. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
@@ -2559,31 +2559,31 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VDDUP,
0xee011f6e, 0xff811f7e,
- "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
+ "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
/* Vector VDWDUP. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VDWDUP,
0xee011f60, 0xff811f70,
- "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
+ "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
/* Vector VHCADD. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VHCADD,
0xee000f00, 0xff810f51,
- "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
+ "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
/* Vector VIWDUP. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VIWDUP,
0xee010f60, 0xff811f70,
- "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
+ "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
/* Vector VIDUP. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VIDUP,
0xee010f6e, 0xff811f7e,
- "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
+ "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
/* Vector VLD2. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -2625,13 +2625,13 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VLDRW_GATHER_T5,
0xfd101e00, 0xff111f00,
- "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
+ "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
/* Vector VLDRD gather load, variant T6. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VLDRD_GATHER_T6,
0xfd101f00, 0xff111f00,
- "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
+ "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
/* Vector VLDRB. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -2848,7 +2848,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VMOV_GP_TO_VEC_LANE,
0xee000b10, 0xff900f1f,
- "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
+ "vmov%c.%5-6,21-22s\t%{R:%17-19,7Q[%N]%}, %12-15r"},
/* Vector VORR immediate to vector.
NOTE: MVE_VORR_IMM must appear in the table
@@ -2864,7 +2864,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQSHL_T2,
0xef800750, 0xef801fd1,
- "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VQSHLU T3 Variant
NOTE: MVE_VQSHL_T2 must appear in the table before
@@ -2873,7 +2873,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQSHLU_T3,
0xff800650, 0xff801fd1,
- "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VRSHR
NOTE: MVE_VRSHR must appear in the table before
@@ -2881,7 +2881,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VRSHR,
0xef800250, 0xef801fd1,
- "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VSHL.
NOTE: MVE_VSHL must appear in the table before
@@ -2889,7 +2889,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHL_T1,
0xef800550, 0xff801fd1,
- "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VSHR
NOTE: MVE_VSHR must appear in the table before
@@ -2897,7 +2897,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHR,
0xef800050, 0xef801fd1,
- "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VSLI
NOTE: MVE_VSLI must appear in the table before
@@ -2905,7 +2905,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSLI,
0xff800550, 0xff801fd1,
- "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VSRI
NOTE: MVE_VSRI must appear in the table before
@@ -2913,7 +2913,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSRI,
0xff800450, 0xff801fd1,
- "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VMOV immediate to vector,
undefinded for cmode == 1111 */
@@ -2936,38 +2936,38 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMOV2_VEC_LANE_TO_GP,
0xec000f00, 0xffb01ff0,
- "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
+ "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}"},
/* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMOV2_VEC_LANE_TO_GP,
0xec000f10, 0xffb01ff0,
- "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
+ "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}"},
/* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMOV2_GP_TO_VEC_LANE,
0xec100f00, 0xffb01ff0,
- "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
+ "vmov%c\t%{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}, %0-3r, %16-19r"},
/* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMOV2_GP_TO_VEC_LANE,
0xec100f10, 0xffb01ff0,
- "vmov%c\t%13-15,22Q[3], %13-15,22Q[1], %0-3r, %16-19r"},
+ "vmov%c\t%{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}, %0-3r, %16-19r"},
/* Vector VMOV Vector lane to gpr. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VMOV_VEC_LANE_TO_GP,
0xee100b10, 0xff100f1f,
- "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
+ "vmov%c.%u%5-6,21-22s\t%12-15r, %{R:%17-19,7Q[%N]%}"},
/* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
to instruction opcode aliasing. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHLL_T1,
0xeea00f40, 0xefa00fd1,
- "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VMOVL long. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -3229,13 +3229,13 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQRSHRN,
0xee800f41, 0xefa00fd1,
- "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VQRSHRUN. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQRSHRUN,
0xfe800fc0, 0xffa00fd1,
- "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VQSHL T1 Variant. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -3253,13 +3253,13 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQSHRN,
0xee800f40, 0xefa00fd1,
- "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VQSHRUN. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQSHRUN,
0xee800fc0, 0xffa00fd1,
- "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VQSUB T1 Variant. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -3325,7 +3325,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VRSHRN,
0xfe800fc1, 0xffa00fd1,
- "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VSBC. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -3349,19 +3349,19 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHLC,
0xeea00fc0, 0xffa01ff0,
- "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
+ "vshlc%v\t%13-15,22Q, %0-3r, %{I:#%16-20d%}"},
/* Vector VSHLL T2 Variant. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHLL_T2,
0xee310e01, 0xefb30fd1,
- "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
+ "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, %{I:#%18-19d%}"},
/* Vector VSHRN. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHRN,
0xee800fc1, 0xffa00fd1,
- "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VST2 no writeback. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -3415,13 +3415,13 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSTRW_SCATTER_T5,
0xfd001e00, 0xff111f00,
- "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
+ "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
/* Vector VSTRD scatter store, T6 variant. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSTRD_SCATTER_T6,
0xfd001f00, 0xff111f00,
- "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
+ "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
/* Vector VSTRB. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -3659,7 +3659,7 @@ static const struct opcode32 arm_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
- 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
+ 0xe7f000f0, 0xfff000f0, "udf\t%{I:#%e%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
@@ -3689,7 +3689,7 @@ static const struct opcode32 arm_opcodes[] =
0x0320f005, 0x0fffffff, "sevl"},
/* Defined in V8 but is in NOP space so available to all arch. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
- 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
+ 0xe1000070, 0xfff000f0, "hlt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
@@ -3734,7 +3734,7 @@ static const struct opcode32 arm_opcodes[] =
/* Privileged Access Never extension instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
- 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
+ 0xf1100000, 0xfffffdff, "setpan\t%{I:#%9-9d%}"},
/* Virtualization Extension instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
@@ -3756,14 +3756,14 @@ static const struct opcode32 arm_opcodes[] =
/* V7 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t%{I:#%0-3d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
- 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
+ 0x0320f000, 0x0fffffff, "nop%c\t{%{I:%0-7d%}}"},
/* ARM V6T2 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
@@ -3787,7 +3787,7 @@ static const struct opcode32 arm_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
+ 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, %{I:#%7-11d%}, %{I:#%16-20W%}"},
/* ARM Security extension instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
@@ -3822,29 +3822,29 @@ static const struct opcode32 arm_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
0x0320f004, 0x0fffffff, "sev%c"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
- 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
+ 0x0320f000, 0x0fffff00, "nop%c\t{%{I:%0-7d%}}"},
/* ARM V6 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
+ 0xf1080000, 0xfffffe3f, "cpsie\t%{B:%8'a%7'i%6'f%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
+ 0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%},%{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
+ 0xf10C0000, 0xfffffe3f, "cpsid\t%{B:%8'a%7'i%6'f%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
+ 0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%},%{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
+ 0xf1000000, 0xfff1fe20, "cps\t%{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
+ 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
+ 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#32%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
+ 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
+ 0x01900f9f, 0x0ff00fff, "ldrex%c\t%{R:r%12-15d%}, [%16-19R]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
@@ -3928,103 +3928,103 @@ static const struct opcode32 arm_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
+ 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
+ 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
+ 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
+ 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
+ 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
+ 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
+ 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
+ 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
+ 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
+ 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
+ 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
+ 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
+ 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
+ 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
+ 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
+ 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
+ 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
+ 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
+ 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
+ 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
+ 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
+ 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
+ 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
+ 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
+ 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
+ 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
+ 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
+ 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
+ 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
+ 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
+ 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
+ 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
+ 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
+ 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
+ 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
+ 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
+ 0xf1010000, 0xfffffc00, "setend\t%{B:%9?ble%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
@@ -4044,15 +4044,15 @@ static const struct opcode32 arm_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
+ 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, %{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
+ 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
+ 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
+ 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
+ 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, %{I:#%16-19W%}, %0-3r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
@@ -4062,13 +4062,13 @@ static const struct opcode32 arm_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
+ 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
+ 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
+ 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
+ 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, %{I:#%16-19d%}, %0-3R"},
/* V5J instruction. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
@@ -4077,7 +4077,7 @@ static const struct opcode32 arm_opcodes[] =
/* V5 Instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xe1200070, 0xfff000f0,
- "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
+ "bkpt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfa000000, 0xfe000000, "blx\t%B"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
@@ -4398,7 +4398,7 @@ static const struct opcode32 arm_opcodes[] =
/* The rest. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
- 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
+ 0x03200000, 0x0fff00ff, "nop%c\t{%{I:%0-7d%}}" UNPREDICTABLE_INSTRUCTION},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
{ARM_FEATURE_CORE_LOW (0),
@@ -4443,7 +4443,7 @@ static const struct opcode16 thumb_opcodes[] =
/* ARM V8 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t%{I:#%3-3d%}"},
/* ARM V6K no-argument instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
@@ -4461,13 +4461,13 @@ static const struct opcode16 thumb_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
/* ARM V6. */
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%{B:%2'a%1'i%0'f%}%X"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%{B:%2'a%1'i%0'f%}%X"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%{B:%3?ble%}%X"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
@@ -4500,8 +4500,8 @@ static const struct opcode16 thumb_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
/* format 13 */
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\t%{R:sp%}, %{I:#%0-6W%}"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\t%{R:sp%}, %{I:#%0-6W%}"},
/* format 5 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
@@ -4516,9 +4516,9 @@ static const struct opcode16 thumb_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
+ 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
+ 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
/* format 8 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
@@ -4534,50 +4534,50 @@ static const struct opcode16 thumb_opcodes[] =
/* format 1 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
+ 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, %{I:#%6-10d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
/* format 3 */
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, %{I:#%0-7d%}"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, %{I:#%0-7d%}"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, %{I:#%0-7d%}"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, %{I:#%0-7d%}"},
/* format 6 */
/* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
0x4800, 0xF800,
- "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
+ "ldr%c\t%8-10r, [%{R:pc%}, %{I:#%0-7W%}]\t; (%0-7a)"},
/* format 9 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
+ 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
+ 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
+ 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
+ 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
/* format 10 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
+ 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
+ 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
/* format 11 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
+ 0x9000, 0xF800, "str%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
+ 0x9800, 0xF800, "ldr%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
/* format 12 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
+ 0xA000, 0xF800, "add%c\t%8-10r, %{R:pc%}, %{I:#%0-7W%}\t; (adr %8-10r, %0-7a)"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
+ 0xA800, 0xF800, "add%c\t%8-10r, %{R:sp%}, %{I:#%0-7W%}"},
/* format 15 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
/* format 17 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
/* format 16 */
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t%{I:#%0-7d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
/* format 18 */
@@ -4655,7 +4655,7 @@ static const struct opcode32 thumb32_opcodes[] =
/* Arm v8.1-M Mainline Pointer Authentication and Branch Target
Identification Extension. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf3af802d, 0xffffffff, "aut\tr12, lr, sp"},
+ 0xf3af802d, 0xffffffff, "aut\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
{ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
0xfb500f00, 0xfff00ff0, "autg%c\t%12-15r, %16-19r, %0-3r"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
@@ -4663,9 +4663,9 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
0xfb500f10, 0xfff00ff0, "bxaut%c\t%12-15r, %16-19r, %0-3r"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf3af801d, 0xffffffff, "pac\tr12, lr, sp"},
+ 0xf3af801d, 0xffffffff, "pac\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf3af800d, 0xffffffff, "pacbti\tr12, lr, sp"},
+ 0xf3af800d, 0xffffffff, "pacbti\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
{ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
0xfb60f000, 0xfff0f0f0, "pacg%c\t%8-11r, %16-19r, %0-3r"},
@@ -4676,17 +4676,17 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf02fc001, 0xfffff001, "le\t%P"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf00fc001, 0xfffff001, "le\tlr, %P"},
+ 0xf00fc001, 0xfffff001, "le\t%{R:lr%}, %P"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
+ 0xf01fc001, 0xfffff001, "letp\t%{R:lr%}, %P"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
+ 0xf040c001, 0xfff0f001, "wls\t%{R:lr%}, %16-19S, %Q"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
+ 0xf000c001, 0xffc0f001, "wlstp.%20-21s\t%{R:lr%}, %16-19S, %Q"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
+ 0xf040e001, 0xfff0ffff, "dls\t%{R:lr%}, %16-19S"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
+ 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\t%{R:lr%}, %16-19S"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
@@ -4697,7 +4697,7 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
+ 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %{B:%18-21c%}"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xe89f0000, 0xffff2000, "clrm%c\t%n"},
@@ -4776,7 +4776,7 @@ static const struct opcode32 thumb32_opcodes[] =
/* V7 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t%{I:#%0-3d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
@@ -4807,15 +4807,15 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
+ 0xf3af8000, 0xffffff00, "nop%c.w\t{%{I:%0-7d%}}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
0xf3bf8f2f, 0xffffffff, "clrex%c"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
+ 0xf3af8400, 0xffffff1f, "cpsie.w\t%{B:%7'a%6'i%5'f%}%X"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
+ 0xf3af8600, 0xffffff1f, "cpsid.w\t%{B:%7'a%6'i%5'f%}%X"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
@@ -4825,17 +4825,17 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
+ 0xf3af8100, 0xffffffe0, "cps\t%{I:#%0-4d%}%X"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
+ 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, %{B:lsl%} %{I:#1%}]%x"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
+ 0xf3af8500, 0xffffff00, "cpsie\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
+ 0xf3af8700, 0xffffff00, "cpsid\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
+ 0xf3de8f00, 0xffffff00, "subs%c\t%{R:pc%}, %{R:lr%}, %{I:#%0-7d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
@@ -4843,9 +4843,9 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
+ 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, %{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
+ 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, %{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
@@ -4969,9 +4969,9 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
+ 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, %{I:#%0-4D%}, %16-19r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
+ 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, %{I:#%0-4d%}, %16-19r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
@@ -5035,7 +5035,7 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
- 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
+ 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, %{I:#%0-7W%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
@@ -5077,9 +5077,9 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
+ 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, %{I:#%0-4D%}, %16-19r%s"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
+ 0xf3800000, 0xffd08020, "usat%c\t%8-11r, %{I:#%0-4d%}, %16-19r%s"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
@@ -5109,7 +5109,7 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
- 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
+ 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, %{I:#%0-7W%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
@@ -5144,16 +5144,16 @@ static const struct opcode32 thumb32_opcodes[] =
0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xe9400000, 0xff500000,
- "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
+ "strd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xe9500000, 0xff500000,
- "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
+ "ldrd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xe8600000, 0xff700000,
- "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
+ "strd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xe8700000, 0xff700000,
- "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
+ "ldrd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
@@ -5459,10 +5459,10 @@ arm_decode_bitfield (const char *ptr,
}
static void
-arm_decode_shift (long given, fprintf_ftype func, void *stream,
+arm_decode_shift (long given, fprintf_styled_ftype func, void *stream,
bool print_shift)
{
- func (stream, "%s", arm_regnames[given & 0xf]);
+ func (stream, dis_style_register, "%s", arm_regnames[given & 0xf]);
if ((given & 0xff0) != 0)
{
@@ -5475,7 +5475,8 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream,
{
if (shift == 3)
{
- func (stream, ", rrx");
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "rrx");
return;
}
@@ -5483,17 +5484,34 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream,
}
if (print_shift)
- func (stream, ", %s #%d", arm_shift[shift], amount);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "%s ", arm_shift[shift]);
+ func (stream, dis_style_immediate, "#%d", amount);
+ }
else
- func (stream, ", #%d", amount);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%d", amount);
+ }
}
else if ((given & 0x80) == 0x80)
- func (stream, "\t; <illegal shifter operand>");
+ func (stream, dis_style_comment_start,
+ "\t; <illegal shifter operand>");
else if (print_shift)
- func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
- arm_regnames[(given & 0xf00) >> 8]);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "%s ",
+ arm_shift[(given & 0x60) >> 5]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[(given & 0xf00) >> 8]);
+ }
else
- func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "%s",
+ arm_regnames[(given & 0xf00) >> 8]);
+ }
}
}
@@ -5929,7 +5947,7 @@ print_mve_vld_str_addr (struct disassemble_info *info,
enum mve_instructions matched_insn)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
unsigned long p, w, gpr, imm, add, mod_imm;
@@ -5983,18 +6001,25 @@ print_mve_vld_str_addr (struct disassemble_info *info,
else
add_sub = "-";
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, arm_regnames[gpr]);
if (p == 1)
{
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
/* Offset mode. */
if (w == 0)
- func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
+ func (stream, dis_style_text, "]");
/* Pre-indexed mode. */
else
- func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
+ func (stream, dis_style_text, "]!");
}
else if ((p == 0) && (w == 1))
- /* Post-index mode. */
- func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
+ {
+ /* Post-index mode. */
+ func (stream, dis_style_text, "], ");
+ func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
+ }
}
/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
@@ -6932,7 +6957,7 @@ print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
unsigned long h = arm_decode_field (given, 16, 16);
unsigned long index_operand, esize, targetBeat, idx;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
if ((op1 & 0x2) == 0x2)
{
@@ -6951,14 +6976,14 @@ print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
}
else
{
- func (stream, "<undefined index>");
+ func (stream, dis_style_text, "<undefined index>");
return;
}
targetBeat = (op1 & 0x1) | (h << 1);
idx = index_operand + targetBeat * (32/esize);
- func (stream, "%lu", idx);
+ func (stream, dis_style_immediate, "%lu", idx);
}
/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
@@ -6975,7 +7000,7 @@ print_simd_imm8 (struct disassemble_info *info, unsigned long given,
int size = 0;
int isfloat = 0;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
/* On Neon the 'i' bit is at bit 24, on mve it is
at bit 28. */
@@ -7043,7 +7068,7 @@ print_simd_imm8 (struct disassemble_info *info, unsigned long given,
}
else
{
- func (stream, "<illegal constant %.8x:%x:%x>",
+ func (stream, dis_style_text, "<illegal constant %.8x:%x:%x>",
bits, cmode, op);
size = 32;
return;
@@ -7067,14 +7092,13 @@ print_simd_imm8 (struct disassemble_info *info, unsigned long given,
switch (size)
{
case 8:
- func (stream, "#%ld\t; 0x%.2lx", value, value);
+ func (stream, dis_style_immediate, "#%ld", value);
+ func (stream, dis_style_comment_start, "\t; 0x%.2lx", value);
break;
case 16:
- func (stream,
- printU
- ? "#%lu\t; 0x%.4lx"
- : "#%ld\t; 0x%.4lx", value, value);
+ func (stream, dis_style_immediate, printU ? "#%lu" : "#%ld", value);
+ func (stream, dis_style_comment_start, "\t; 0x%.4lx", value);
break;
case 32:
@@ -7094,22 +7118,22 @@ print_simd_imm8 (struct disassemble_info *info, unsigned long given,
(& floatformat_ieee_single_little, valbytes,
& fvalue);
- func (stream, "#%.7g\t; 0x%.8lx", fvalue,
- value);
+ func (stream, dis_style_immediate, "#%.7g", fvalue);
+ func (stream, dis_style_comment_start, "\t; 0x%.8lx", value);
}
else
- func (stream,
- printU
- ? "#%lu\t; 0x%.8lx"
- : "#%ld\t; 0x%.8lx",
- (long) (((value & 0x80000000L) != 0)
- && !printU
- ? value | ~0xffffffffL : value),
- value);
+ {
+ func (stream, dis_style_immediate,
+ printU ? "#%lu" : "#%ld",
+ (long) (((value & 0x80000000L) != 0)
+ && !printU
+ ? value | ~0xffffffffL : value));
+ func (stream, dis_style_comment_start, "\t; 0x%.8lx", value);
+ }
break;
case 64:
- func (stream, "#0x%.8lx%.8lx", hival, value);
+ func (stream, dis_style_immediate, "#0x%.8lx%.8lx", hival, value);
break;
default:
@@ -7123,84 +7147,85 @@ print_mve_undefined (struct disassemble_info *info,
enum mve_undefined undefined_code)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
-
- func (stream, "\t\tundefined instruction: ");
+ fprintf_styled_ftype func = info->fprintf_styled_func;
+ const char *reason;
switch (undefined_code)
{
case UNDEF_SIZE:
- func (stream, "illegal size");
+ reason = "illegal size";
break;
case UNDEF_SIZE_0:
- func (stream, "size equals zero");
+ reason = "size equals zero";
break;
case UNDEF_SIZE_2:
- func (stream, "size equals two");
+ reason = "size equals two";
break;
case UNDEF_SIZE_3:
- func (stream, "size equals three");
+ reason = "size equals three";
break;
case UNDEF_SIZE_LE_1:
- func (stream, "size <= 1");
+ reason = "size <= 1";
break;
case UNDEF_SIZE_NOT_0:
- func (stream, "size not equal to 0");
+ reason = "size not equal to 0";
break;
case UNDEF_SIZE_NOT_2:
- func (stream, "size not equal to 2");
+ reason = "size not equal to 2";
break;
case UNDEF_SIZE_NOT_3:
- func (stream, "size not equal to 3");
+ reason = "size not equal to 3";
break;
case UNDEF_NOT_UNS_SIZE_0:
- func (stream, "not unsigned and size = zero");
+ reason = "not unsigned and size = zero";
break;
case UNDEF_NOT_UNS_SIZE_1:
- func (stream, "not unsigned and size = one");
+ reason = "not unsigned and size = one";
break;
case UNDEF_NOT_UNSIGNED:
- func (stream, "not unsigned");
+ reason = "not unsigned";
break;
case UNDEF_VCVT_IMM6:
- func (stream, "invalid imm6");
+ reason = "invalid imm6";
break;
case UNDEF_VCVT_FSI_IMM6:
- func (stream, "fsi = 0 and invalid imm6");
+ reason = "fsi = 0 and invalid imm6";
break;
case UNDEF_BAD_OP1_OP2:
- func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
+ reason = "bad size with op2 = 2 and op1 = 0 or 1";
break;
case UNDEF_BAD_U_OP1_OP2:
- func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
+ reason = "unsigned with op2 = 0 and op1 = 0 or 1";
break;
case UNDEF_OP_0_BAD_CMODE:
- func (stream, "op field equal 0 and bad cmode");
+ reason = "op field equal 0 and bad cmode";
break;
case UNDEF_XCHG_UNS:
- func (stream, "exchange and unsigned together");
+ reason = "exchange and unsigned together";
break;
case UNDEF_NONE:
+ reason = "";
break;
}
+ func (stream, dis_style_text, "\t\tundefined instruction: %s", reason);
}
static void
@@ -7208,64 +7233,65 @@ print_mve_unpredictable (struct disassemble_info *info,
enum mve_unpredictable unpredict_code)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
-
- func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
+ fprintf_styled_ftype func = info->fprintf_styled_func;
+ const char *reason;
switch (unpredict_code)
{
case UNPRED_IT_BLOCK:
- func (stream, "mve instruction in it block");
+ reason = "mve instruction in it block";
break;
case UNPRED_FCA_0_FCB_1:
- func (stream, "condition bits, fca = 0 and fcb = 1");
+ reason = "condition bits, fca = 0 and fcb = 1";
break;
case UNPRED_R13:
- func (stream, "use of r13 (sp)");
+ reason = "use of r13 (sp)";
break;
case UNPRED_R15:
- func (stream, "use of r15 (pc)");
+ reason = "use of r15 (pc)";
break;
case UNPRED_Q_GT_4:
- func (stream, "start register block > r4");
+ reason = "start register block > r4";
break;
case UNPRED_Q_GT_6:
- func (stream, "start register block > r6");
+ reason = "start register block > r6";
break;
case UNPRED_R13_AND_WB:
- func (stream, "use of r13 and write back");
+ reason = "use of r13 and write back";
break;
case UNPRED_Q_REGS_EQUAL:
- func (stream,
- "same vector register used for destination and other operand");
+ reason = "same vector register used for destination and other operand";
break;
case UNPRED_OS:
- func (stream, "use of offset scaled");
+ reason = "use of offset scaled";
break;
case UNPRED_GP_REGS_EQUAL:
- func (stream, "same general-purpose register used for both operands");
+ reason = "same general-purpose register used for both operands";
break;
case UNPRED_Q_REGS_EQ_AND_SIZE_1:
- func (stream, "use of identical q registers and size = 1");
+ reason = "use of identical q registers and size = 1";
break;
case UNPRED_Q_REGS_EQ_AND_SIZE_2:
- func (stream, "use of identical q registers and size = 1");
+ reason = "use of identical q registers and size = 1";
break;
case UNPRED_NONE:
+ reason = "";
break;
}
+
+ func (stream, dis_style_text, "%s: %s", UNPREDICTABLE_INSTRUCTION, reason);
}
/* Print register block operand for mve vld2/vld4/vst2/vld4. */
@@ -7276,7 +7302,7 @@ print_mve_register_blocks (struct disassemble_info *info,
enum mve_instructions matched_insn)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
unsigned long q_reg_start = arm_decode_field_multiple (given,
13, 15,
@@ -7286,19 +7312,33 @@ print_mve_register_blocks (struct disassemble_info *info,
case MVE_VLD2:
case MVE_VST2:
if (q_reg_start <= 6)
- func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
+ {
+ func (stream, dis_style_text, "{");
+ func (stream, dis_style_register, "q%ld", q_reg_start);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "q%ld", q_reg_start + 1);
+ func (stream, dis_style_text, "}");
+ }
else
- func (stream, "<illegal reg q%ld>", q_reg_start);
+ func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
break;
case MVE_VLD4:
case MVE_VST4:
if (q_reg_start <= 4)
- func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
- q_reg_start + 1, q_reg_start + 2,
- q_reg_start + 3);
+ {
+ func (stream, dis_style_text, "{");
+ func (stream, dis_style_register, "q%ld", q_reg_start);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "q%ld", q_reg_start + 1);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "q%ld", q_reg_start + 2);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "q%ld", q_reg_start + 3);
+ func (stream, dis_style_text, "}");
+ }
else
- func (stream, "<illegal reg q%ld>", q_reg_start);
+ func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
break;
default:
@@ -7312,7 +7352,7 @@ print_mve_rounding_mode (struct disassemble_info *info,
enum mve_instructions matched_insn)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
switch (matched_insn)
{
@@ -7321,19 +7361,19 @@ print_mve_rounding_mode (struct disassemble_info *info,
switch (arm_decode_field (given, 8, 9))
{
case 0:
- func (stream, "a");
+ func (stream, dis_style_mnemonic, "a");
break;
case 1:
- func (stream, "n");
+ func (stream, dis_style_mnemonic, "n");
break;
case 2:
- func (stream, "p");
+ func (stream, dis_style_mnemonic, "p");
break;
case 3:
- func (stream, "m");
+ func (stream, dis_style_mnemonic, "m");
break;
default:
@@ -7347,27 +7387,27 @@ print_mve_rounding_mode (struct disassemble_info *info,
switch (arm_decode_field (given, 7, 9))
{
case 0:
- func (stream, "n");
+ func (stream, dis_style_mnemonic, "n");
break;
case 1:
- func (stream, "x");
+ func (stream, dis_style_mnemonic, "x");
break;
case 2:
- func (stream, "a");
+ func (stream, dis_style_mnemonic, "a");
break;
case 3:
- func (stream, "z");
+ func (stream, dis_style_mnemonic, "z");
break;
case 5:
- func (stream, "m");
+ func (stream, dis_style_mnemonic, "m");
break;
case 7:
- func (stream, "p");
+ func (stream, dis_style_mnemonic, "p");
case 4:
case 6:
@@ -7389,7 +7429,7 @@ print_mve_vcvt_size (struct disassemble_info *info,
{
unsigned long mode = 0;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
switch (matched_insn)
{
@@ -7402,35 +7442,35 @@ print_mve_vcvt_size (struct disassemble_info *info,
switch (mode)
{
case 0:
- func (stream, "f16.s16");
+ func (stream, dis_style_mnemonic, "f16.s16");
break;
case 1:
- func (stream, "s16.f16");
+ func (stream, dis_style_mnemonic, "s16.f16");
break;
case 2:
- func (stream, "f16.u16");
+ func (stream, dis_style_mnemonic, "f16.u16");
break;
case 3:
- func (stream, "u16.f16");
+ func (stream, dis_style_mnemonic, "u16.f16");
break;
case 4:
- func (stream, "f32.s32");
+ func (stream, dis_style_mnemonic, "f32.s32");
break;
case 5:
- func (stream, "s32.f32");
+ func (stream, dis_style_mnemonic, "s32.f32");
break;
case 6:
- func (stream, "f32.u32");
+ func (stream, dis_style_mnemonic, "f32.u32");
break;
case 7:
- func (stream, "u32.f32");
+ func (stream, dis_style_mnemonic, "u32.f32");
break;
default:
@@ -7448,19 +7488,19 @@ print_mve_vcvt_size (struct disassemble_info *info,
switch (op)
{
case 0:
- func (stream, "f16.s16");
+ func (stream, dis_style_mnemonic, "f16.s16");
break;
case 1:
- func (stream, "f16.u16");
+ func (stream, dis_style_mnemonic, "f16.u16");
break;
case 2:
- func (stream, "s16.f16");
+ func (stream, dis_style_mnemonic, "s16.f16");
break;
case 3:
- func (stream, "u16.f16");
+ func (stream, dis_style_mnemonic, "u16.f16");
break;
default:
@@ -7472,19 +7512,19 @@ print_mve_vcvt_size (struct disassemble_info *info,
switch (op)
{
case 0:
- func (stream, "f32.s32");
+ func (stream, dis_style_mnemonic, "f32.s32");
break;
case 1:
- func (stream, "f32.u32");
+ func (stream, dis_style_mnemonic, "f32.u32");
break;
case 2:
- func (stream, "s32.f32");
+ func (stream, dis_style_mnemonic, "s32.f32");
break;
case 3:
- func (stream, "u32.f32");
+ func (stream, dis_style_mnemonic, "u32.f32");
break;
}
}
@@ -7495,9 +7535,9 @@ print_mve_vcvt_size (struct disassemble_info *info,
{
unsigned long op = arm_decode_field (given, 28, 28);
if (op == 0)
- func (stream, "f16.f32");
+ func (stream, dis_style_mnemonic, "f16.f32");
else if (op == 1)
- func (stream, "f32.f16");
+ func (stream, dis_style_mnemonic, "f32.f16");
}
break;
@@ -7508,19 +7548,19 @@ print_mve_vcvt_size (struct disassemble_info *info,
switch (size)
{
case 2:
- func (stream, "s16.f16");
+ func (stream, dis_style_mnemonic, "s16.f16");
break;
case 3:
- func (stream, "u16.f16");
+ func (stream, dis_style_mnemonic, "u16.f16");
break;
case 4:
- func (stream, "s32.f32");
+ func (stream, dis_style_mnemonic, "s32.f32");
break;
case 5:
- func (stream, "u32.f32");
+ func (stream, dis_style_mnemonic, "u32.f32");
break;
default:
@@ -7539,17 +7579,17 @@ print_mve_rotate (struct disassemble_info *info, unsigned long rot,
unsigned long rot_width)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
if (rot_width == 1)
{
switch (rot)
{
case 0:
- func (stream, "90");
+ func (stream, dis_style_immediate, "90");
break;
case 1:
- func (stream, "270");
+ func (stream, dis_style_immediate, "270");
break;
default:
break;
@@ -7560,16 +7600,16 @@ print_mve_rotate (struct disassemble_info *info, unsigned long rot,
switch (rot)
{
case 0:
- func (stream, "0");
+ func (stream, dis_style_immediate, "0");
break;
case 1:
- func (stream, "90");
+ func (stream, dis_style_immediate, "90");
break;
case 2:
- func (stream, "180");
+ func (stream, dis_style_immediate, "180");
break;
case 3:
- func (stream, "270");
+ func (stream, dis_style_immediate, "270");
break;
default:
break;
@@ -7581,12 +7621,12 @@ static void
print_instruction_predicate (struct disassemble_info *info)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
if (vpt_block_state.next_pred_state == PRED_THEN)
- func (stream, "t");
+ func (stream, dis_style_mnemonic, "t");
else if (vpt_block_state.next_pred_state == PRED_ELSE)
- func (stream, "e");
+ func (stream, dis_style_mnemonic, "e");
}
static void
@@ -7595,7 +7635,7 @@ print_mve_size (struct disassemble_info *info,
enum mve_instructions matched_insn)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
switch (matched_insn)
{
@@ -7698,9 +7738,9 @@ print_mve_size (struct disassemble_info *info,
case MVE_VSUB_VEC_T1:
case MVE_VSUB_VEC_T2:
if (size <= 3)
- func (stream, "%s", mve_vec_sizename[size]);
+ func (stream, dis_style_mnemonic, "%s", mve_vec_sizename[size]);
else
- func (stream, "<undef size>");
+ func (stream, dis_style_text, "<undef size>");
break;
case MVE_VABD_FP:
@@ -7727,9 +7767,9 @@ print_mve_size (struct disassemble_info *info,
case MVE_VPT_FP_T1:
case MVE_VPT_FP_T2:
if (size == 0)
- func (stream, "32");
+ func (stream, dis_style_mnemonic, "32");
else if (size == 1)
- func (stream, "16");
+ func (stream, dis_style_mnemonic, "16");
break;
case MVE_VCADD_FP:
@@ -7745,29 +7785,29 @@ print_mve_size (struct disassemble_info *info,
case MVE_VQMOVN:
case MVE_VQMOVUN:
if (size == 0)
- func (stream, "16");
+ func (stream, dis_style_mnemonic, "16");
else if (size == 1)
- func (stream, "32");
+ func (stream, dis_style_mnemonic, "32");
break;
case MVE_VMOVL:
if (size == 1)
- func (stream, "8");
+ func (stream, dis_style_mnemonic, "8");
else if (size == 2)
- func (stream, "16");
+ func (stream, dis_style_mnemonic, "16");
break;
case MVE_VDUP:
switch (size)
{
case 0:
- func (stream, "32");
+ func (stream, dis_style_mnemonic, "32");
break;
case 1:
- func (stream, "16");
+ func (stream, dis_style_mnemonic, "16");
break;
case 2:
- func (stream, "8");
+ func (stream, dis_style_mnemonic, "8");
break;
default:
break;
@@ -7779,17 +7819,17 @@ print_mve_size (struct disassemble_info *info,
switch (size)
{
case 0: case 4:
- func (stream, "32");
+ func (stream, dis_style_mnemonic, "32");
break;
case 1: case 3:
case 5: case 7:
- func (stream, "16");
+ func (stream, dis_style_mnemonic, "16");
break;
case 8: case 9: case 10: case 11:
case 12: case 13: case 14: case 15:
- func (stream, "8");
+ func (stream, dis_style_mnemonic, "8");
break;
default:
@@ -7802,19 +7842,19 @@ print_mve_size (struct disassemble_info *info,
{
case 0: case 4: case 8:
case 12: case 24: case 26:
- func (stream, "i32");
+ func (stream, dis_style_mnemonic, "i32");
break;
case 16: case 20:
- func (stream, "i16");
+ func (stream, dis_style_mnemonic, "i16");
break;
case 28:
- func (stream, "i8");
+ func (stream, dis_style_mnemonic, "i8");
break;
case 29:
- func (stream, "i64");
+ func (stream, dis_style_mnemonic, "i64");
break;
case 30:
- func (stream, "f32");
+ func (stream, dis_style_mnemonic, "f32");
break;
default:
break;
@@ -7823,9 +7863,9 @@ print_mve_size (struct disassemble_info *info,
case MVE_VMULL_POLY:
if (size == 0)
- func (stream, "p8");
+ func (stream, dis_style_mnemonic, "p8");
else if (size == 1)
- func (stream, "p16");
+ func (stream, dis_style_mnemonic, "p16");
break;
case MVE_VMVN_IMM:
@@ -7833,11 +7873,11 @@ print_mve_size (struct disassemble_info *info,
{
case 0: case 2: case 4:
case 6: case 12: case 13:
- func (stream, "32");
+ func (stream, dis_style_mnemonic, "32");
break;
case 8: case 10:
- func (stream, "16");
+ func (stream, dis_style_mnemonic, "16");
break;
default:
@@ -7851,11 +7891,11 @@ print_mve_size (struct disassemble_info *info,
{
case 1: case 3:
case 5: case 7:
- func (stream, "32");
+ func (stream, dis_style_mnemonic, "32");
break;
case 9: case 11:
- func (stream, "16");
+ func (stream, dis_style_mnemonic, "16");
break;
default:
@@ -7873,11 +7913,11 @@ print_mve_size (struct disassemble_info *info,
switch (size)
{
case 1:
- func (stream, "16");
+ func (stream, dis_style_mnemonic, "16");
break;
case 2: case 3:
- func (stream, "32");
+ func (stream, dis_style_mnemonic, "32");
break;
default:
@@ -7898,15 +7938,15 @@ print_mve_size (struct disassemble_info *info,
switch (size)
{
case 1:
- func (stream, "8");
+ func (stream, dis_style_mnemonic, "8");
break;
case 2: case 3:
- func (stream, "16");
+ func (stream, dis_style_mnemonic, "16");
break;
case 4: case 5: case 6: case 7:
- func (stream, "32");
+ func (stream, dis_style_mnemonic, "32");
break;
default:
@@ -7925,7 +7965,7 @@ print_mve_shift_n (struct disassemble_info *info, long given,
enum mve_instructions matched_insn)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
int startAt0
= matched_insn == MVE_VQSHL_T2
@@ -7949,7 +7989,7 @@ print_mve_shift_n (struct disassemble_info *info, long given,
else
print_mve_undefined (info, UNDEF_SIZE_0);
- func (stream, "%u", shiftAmount);
+ func (stream, dis_style_immediate, "%u", shiftAmount);
}
static void
@@ -7957,7 +7997,7 @@ print_vec_condition (struct disassemble_info *info, long given,
enum mve_instructions matched_insn)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
long vec_cond = 0;
switch (matched_insn)
@@ -7967,7 +8007,7 @@ print_vec_condition (struct disassemble_info *info, long given,
vec_cond = (((given & 0x1000) >> 10)
| ((given & 1) << 1)
| ((given & 0x0080) >> 7));
- func (stream, "%s",vec_condnames[vec_cond]);
+ func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
break;
case MVE_VPT_FP_T2:
@@ -7975,43 +8015,43 @@ print_vec_condition (struct disassemble_info *info, long given,
vec_cond = (((given & 0x1000) >> 10)
| ((given & 0x0020) >> 4)
| ((given & 0x0080) >> 7));
- func (stream, "%s",vec_condnames[vec_cond]);
+ func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
break;
case MVE_VPT_VEC_T1:
case MVE_VCMP_VEC_T1:
vec_cond = (given & 0x0080) >> 7;
- func (stream, "%s",vec_condnames[vec_cond]);
+ func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
break;
case MVE_VPT_VEC_T2:
case MVE_VCMP_VEC_T2:
vec_cond = 2 | ((given & 0x0080) >> 7);
- func (stream, "%s",vec_condnames[vec_cond]);
+ func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
break;
case MVE_VPT_VEC_T3:
case MVE_VCMP_VEC_T3:
vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
- func (stream, "%s",vec_condnames[vec_cond]);
+ func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
break;
case MVE_VPT_VEC_T4:
case MVE_VCMP_VEC_T4:
vec_cond = (given & 0x0080) >> 7;
- func (stream, "%s",vec_condnames[vec_cond]);
+ func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
break;
case MVE_VPT_VEC_T5:
case MVE_VCMP_VEC_T5:
vec_cond = 2 | ((given & 0x0080) >> 7);
- func (stream, "%s",vec_condnames[vec_cond]);
+ func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
break;
case MVE_VPT_VEC_T6:
case MVE_VCMP_VEC_T6:
vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
- func (stream, "%s",vec_condnames[vec_cond]);
+ func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
break;
case MVE_NONE:
@@ -8031,6 +8071,32 @@ print_vec_condition (struct disassemble_info *info, long given,
#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
#define PRE_BIT_SET (given & (1 << P_BIT))
+/* The assembler string for an instruction can include %{X:...%} patterns,
+ where the 'X' is one of the characters understood by this function.
+
+ This function takes the X character, and returns a new style. This new
+ style will be used by the caller to temporarily change the current base
+ style. */
+
+static enum disassembler_style
+decode_base_style (const char x)
+{
+ switch (x)
+ {
+ case 'A': return dis_style_address;
+ case 'B': return dis_style_sub_mnemonic;
+ case 'C': return dis_style_comment_start;
+ case 'D': return dis_style_assembler_directive;
+ case 'I': return dis_style_immediate;
+ case 'M': return dis_style_mnemonic;
+ case 'O': return dis_style_address_offset;
+ case 'R': return dis_style_register;
+ case 'S': return dis_style_symbol;
+ case 'T': return dis_style_text;
+ default:
+ abort ();
+ }
+}
/* Print one coprocessor instruction on INFO->STREAM.
Return TRUE if the instuction matched, FALSE if this is not a
@@ -8045,7 +8111,7 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
{
const struct sopcode32 *insn;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
unsigned long mask;
unsigned long value = 0;
int cond;
@@ -8054,6 +8120,8 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
arm_feature_set allowed_arches = ARM_ARCH_NONE;
arm_feature_set arm_ext_v8_1m_main =
ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
+ enum disassembler_style base_style = dis_style_mnemonic;
+ enum disassembler_style old_base_style = base_style;
allowed_arches = private_data->features;
@@ -8177,10 +8245,26 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
if (*c == '%')
{
const char mod = *++c;
+
switch (mod)
{
+ case '{':
+ ++c;
+ if (*c == '\0')
+ abort ();
+ old_base_style = base_style;
+ base_style = decode_base_style (*c);
+ ++c;
+ if (*c != ':')
+ abort ();
+ break;
+
+ case '}':
+ base_style = old_base_style;
+ break;
+
case '%':
- func (stream, "%%");
+ func (stream, base_style, "%%");
break;
case 'A':
@@ -8192,7 +8276,9 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
if (mod == 'K')
offset = given & 0x7f;
- func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "%s",
+ arm_regnames [(given >> 16) & 0xf]);
if (PRE_BIT_SET || WRITEBACK_BIT_SET)
{
@@ -8213,36 +8299,53 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
if (PRE_BIT_SET)
{
if (offset)
- func (stream, ", #%d]%s",
- (int) offset,
- WRITEBACK_BIT_SET ? "!" : "");
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%d",
+ (int) offset);
+ func (stream, dis_style_text, "]%s",
+ WRITEBACK_BIT_SET ? "!" : "");
+ }
else if (NEGATIVE_BIT_SET)
- func (stream, ", #-0]");
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#-0");
+ func (stream, dis_style_text, "]");
+ }
else
- func (stream, "]");
+ func (stream, dis_style_text, "]");
}
else
{
- func (stream, "]");
+ func (stream, dis_style_text, "]");
if (WRITEBACK_BIT_SET)
{
if (offset)
- func (stream, ", #%d", (int) offset);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate,
+ "#%d", (int) offset);
+ }
else if (NEGATIVE_BIT_SET)
- func (stream, ", #-0");
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#-0");
+ }
}
else
{
- func (stream, ", {%s%d}",
+ func (stream, dis_style_text, ", {");
+ func (stream, dis_style_immediate, "%s%d",
(NEGATIVE_BIT_SET && !offset) ? "-" : "",
(int) offset);
+ func (stream, dis_style_text, "}");
value_in_comment = offset;
}
}
if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
{
- func (stream, "\t; ");
+ func (stream, dis_style_comment_start, "\t; ");
/* For unaligned PCs, apply off-by-alignment
correction. */
info->print_address_func (offset + pc
@@ -8258,12 +8361,23 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
int offset = (given >> 1) & 0x3f;
+ func (stream, dis_style_text, "{");
if (offset == 1)
- func (stream, "{d%d}", regno);
+ func (stream, dis_style_register, "d%d", regno);
else if (regno + offset > 32)
- func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
+ {
+ func (stream, dis_style_register, "d%d", regno);
+ func (stream, dis_style_text, "-<overflow reg d%d>",
+ regno + offset - 1);
+ }
else
- func (stream, "{d%d-d%d}", regno, regno + offset - 1);
+ {
+ func (stream, dis_style_register, "d%d", regno);
+ func (stream, dis_style_text, "-");
+ func (stream, dis_style_register, "d%d",
+ regno + offset - 1);
+ }
+ func (stream, dis_style_text, "}");
}
break;
@@ -8279,16 +8393,35 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
int maxreg = single ? 31 : 15;
int topreg = reg + num - 1;
+ func (stream, dis_style_text, "{");
if (!num)
- func (stream, "{VPR}");
+ {
+ /* Nothing. */
+ }
else if (num == 1)
- func (stream, "{%c%d, VPR}", reg_prefix, reg);
+ {
+ func (stream, dis_style_register,
+ "%c%d", reg_prefix, reg);
+ func (stream, dis_style_text, ", ");
+ }
else if (topreg > maxreg)
- func (stream, "{%c%d-<overflow reg d%d, VPR}",
- reg_prefix, reg, single ? topreg >> 1 : topreg);
+ {
+ func (stream, dis_style_register, "%c%d",
+ reg_prefix, reg);
+ func (stream, dis_style_text, "-<overflow reg d%d, ",
+ single ? topreg >> 1 : topreg);
+ }
else
- func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
- reg_prefix, topreg);
+ {
+ func (stream, dis_style_register,
+ "%c%d", reg_prefix, reg);
+ func (stream, dis_style_text, "-");
+ func (stream, dis_style_register, "%c%d",
+ reg_prefix, topreg);
+ func (stream, dis_style_text, ", ");
+ }
+ func (stream, dis_style_register, "VPR");
+ func (stream, dis_style_text, "}");
}
break;
@@ -8303,7 +8436,8 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
/* Fall through. */
case 'b':
- func (stream, "%s", arm_conditional[cond]);
+ func (stream, dis_style_mnemonic, "%s",
+ arm_conditional[cond]);
break;
case 'I':
@@ -8320,7 +8454,7 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
if (imm & 0x40)
imm -= 0x80;
- func (stream, "%d", imm);
+ func (stream, dis_style_immediate, "%d", imm);
}
break;
@@ -8333,25 +8467,26 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
switch (regno)
{
case 0x1:
- func (stream, "FPSCR");
+ func (stream, dis_style_register, "FPSCR");
break;
case 0x2:
- func (stream, "FPSCR_nzcvqc");
+ func (stream, dis_style_register, "FPSCR_nzcvqc");
break;
case 0xc:
- func (stream, "VPR");
+ func (stream, dis_style_register, "VPR");
break;
case 0xd:
- func (stream, "P0");
+ func (stream, dis_style_register, "P0");
break;
case 0xe:
- func (stream, "FPCXTNS");
+ func (stream, dis_style_register, "FPCXTNS");
break;
case 0xf:
- func (stream, "FPCXTS");
+ func (stream, dis_style_register, "FPCXTS");
break;
default:
- func (stream, "<invalid reg %lu>", regno);
+ func (stream, dis_style_text, "<invalid reg %lu>",
+ regno);
break;
}
}
@@ -8361,16 +8496,16 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
switch (given & 0x00408000)
{
case 0:
- func (stream, "4");
+ func (stream, dis_style_immediate, "4");
break;
case 0x8000:
- func (stream, "1");
+ func (stream, dis_style_immediate, "1");
break;
case 0x00400000:
- func (stream, "2");
+ func (stream, dis_style_immediate, "2");
break;
default:
- func (stream, "3");
+ func (stream, dis_style_immediate, "3");
}
break;
@@ -8378,16 +8513,16 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
switch (given & 0x00080080)
{
case 0:
- func (stream, "s");
+ func (stream, dis_style_mnemonic, "s");
break;
case 0x80:
- func (stream, "d");
+ func (stream, dis_style_mnemonic, "d");
break;
case 0x00080000:
- func (stream, "e");
+ func (stream, dis_style_mnemonic, "e");
break;
default:
- func (stream, _("<illegal precision>"));
+ func (stream, dis_style_text, _("<illegal precision>"));
break;
}
break;
@@ -8396,16 +8531,16 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
switch (given & 0x00408000)
{
case 0:
- func (stream, "s");
+ func (stream, dis_style_mnemonic, "s");
break;
case 0x8000:
- func (stream, "d");
+ func (stream, dis_style_mnemonic, "d");
break;
case 0x00400000:
- func (stream, "e");
+ func (stream, dis_style_mnemonic, "e");
break;
default:
- func (stream, "p");
+ func (stream, dis_style_mnemonic, "p");
break;
}
break;
@@ -8416,13 +8551,13 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
case 0:
break;
case 0x20:
- func (stream, "p");
+ func (stream, dis_style_mnemonic, "p");
break;
case 0x40:
- func (stream, "m");
+ func (stream, dis_style_mnemonic, "m");
break;
default:
- func (stream, "z");
+ func (stream, dis_style_mnemonic, "z");
break;
}
break;
@@ -8450,24 +8585,26 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
is_unpredictable = true;
u_reg = value;
}
- func (stream, "%s", arm_regnames[value]);
+ func (stream, dis_style_register, arm_regnames[value]);
break;
case 'V':
if (given & (1 << 6))
goto Q;
/* FALLTHROUGH */
case 'D':
- func (stream, "d%ld", value);
+ func (stream, dis_style_register, "d%ld", value);
break;
case 'Q':
Q:
if (value & 1)
- func (stream, "<illegal reg q%ld.5>", value >> 1);
+ func (stream, dis_style_text,
+ "<illegal reg q%ld.5>", value >> 1);
else
- func (stream, "q%ld", value >> 1);
+ func (stream, dis_style_register,
+ "q%ld", value >> 1);
break;
case 'd':
- func (stream, "%ld", value);
+ func (stream, base_style, "%ld", value);
value_in_comment = value;
break;
case 'E':
@@ -8485,74 +8622,93 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
(16 + (value & 0xF));
if (!(decVal % 1000000))
- func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
- floatVal, value & 0x80 ? '-' : ' ',
- decVal / 10000000,
- decVal % 10000000 / 1000000);
+ {
+ func (stream, dis_style_immediate, "%ld", value);
+ func (stream, dis_style_comment_start,
+ "\t; 0x%08x %c%u.%01u",
+ floatVal, value & 0x80 ? '-' : ' ',
+ decVal / 10000000,
+ decVal % 10000000 / 1000000);
+ }
else if (!(decVal % 10000))
- func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
- floatVal, value & 0x80 ? '-' : ' ',
- decVal / 10000000,
- decVal % 10000000 / 10000);
+ {
+ func (stream, dis_style_immediate, "%ld", value);
+ func (stream, dis_style_comment_start,
+ "\t; 0x%08x %c%u.%03u",
+ floatVal, value & 0x80 ? '-' : ' ',
+ decVal / 10000000,
+ decVal % 10000000 / 10000);
+ }
else
- func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
- floatVal, value & 0x80 ? '-' : ' ',
- decVal / 10000000, decVal % 10000000);
+ {
+ func (stream, dis_style_immediate, "%ld", value);
+ func (stream, dis_style_comment_start,
+ "\t; 0x%08x %c%u.%07u",
+ floatVal, value & 0x80 ? '-' : ' ',
+ decVal / 10000000, decVal % 10000000);
+ }
break;
}
case 'k':
{
int from = (given & (1 << 7)) ? 32 : 16;
- func (stream, "%ld", from - value);
+ func (stream, dis_style_immediate, "%ld",
+ from - value);
}
break;
case 'f':
if (value > 7)
- func (stream, "#%s", arm_fp_const[value & 7]);
+ func (stream, dis_style_immediate, "#%s",
+ arm_fp_const[value & 7]);
else
- func (stream, "f%ld", value);
+ func (stream, dis_style_register, "f%ld", value);
break;
case 'w':
if (width == 2)
- func (stream, "%s", iwmmxt_wwnames[value]);
+ func (stream, dis_style_mnemonic, "%s",
+ iwmmxt_wwnames[value]);
else
- func (stream, "%s", iwmmxt_wwssnames[value]);
+ func (stream, dis_style_mnemonic, "%s",
+ iwmmxt_wwssnames[value]);
break;
case 'g':
- func (stream, "%s", iwmmxt_regnames[value]);
+ func (stream, dis_style_register, "%s",
+ iwmmxt_regnames[value]);
break;
case 'G':
- func (stream, "%s", iwmmxt_cregnames[value]);
+ func (stream, dis_style_register, "%s",
+ iwmmxt_cregnames[value]);
break;
case 'x':
- func (stream, "0x%lx", (value & 0xffffffffUL));
+ func (stream, dis_style_immediate, "0x%lx",
+ (value & 0xffffffffUL));
break;
case 'c':
switch (value)
{
case 0:
- func (stream, "eq");
+ func (stream, dis_style_mnemonic, "eq");
break;
case 1:
- func (stream, "vs");
+ func (stream, dis_style_mnemonic, "vs");
break;
case 2:
- func (stream, "ge");
+ func (stream, dis_style_mnemonic, "ge");
break;
case 3:
- func (stream, "gt");
+ func (stream, dis_style_mnemonic, "gt");
break;
default:
- func (stream, "??");
+ func (stream, dis_style_text, "??");
break;
}
break;
@@ -8560,15 +8716,16 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
case '`':
c++;
if (value == 0)
- func (stream, "%c", *c);
+ func (stream, dis_style_mnemonic, "%c", *c);
break;
case '\'':
c++;
if (value == ((1ul << width) - 1))
- func (stream, "%c", *c);
+ func (stream, base_style, "%c", *c);
break;
case '?':
- func (stream, "%c", c[(1 << width) - (int) value]);
+ func (stream, base_style, "%c",
+ c[(1 << width) - (int) value]);
c += 1 << width;
break;
default:
@@ -8620,7 +8777,7 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
break;
case '3': /* List */
- func (stream, "{");
+ func (stream, dis_style_text, "{");
regno = (given >> 12) & 0x0000000f;
if (single)
{
@@ -8635,7 +8792,8 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
abort ();
}
- func (stream, "%c%d", single ? 's' : 'd', regno);
+ func (stream, dis_style_register, "%c%d",
+ single ? 's' : 'd', regno);
if (*c == '3')
{
@@ -8646,26 +8804,38 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
if (--count)
{
- func (stream, "-%c%d",
+ func (stream, dis_style_text, "-");
+ func (stream, dis_style_register, "%c%d",
single ? 's' : 'd',
regno + count);
}
- func (stream, "}");
+ func (stream, dis_style_text, "}");
}
else if (*c == '4')
- func (stream, ", %c%d", single ? 's' : 'd',
- regno + 1);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "%c%d",
+ single ? 's' : 'd', regno + 1);
+ }
}
break;
case 'L':
switch (given & 0x00400100)
{
- case 0x00000000: func (stream, "b"); break;
- case 0x00400000: func (stream, "h"); break;
- case 0x00000100: func (stream, "w"); break;
- case 0x00400100: func (stream, "d"); break;
+ case 0x00000000:
+ func (stream, dis_style_mnemonic, "b");
+ break;
+ case 0x00400000:
+ func (stream, dis_style_mnemonic, "h");
+ break;
+ case 0x00000100:
+ func (stream, dis_style_mnemonic, "w");
+ break;
+ case 0x00400100:
+ func (stream, dis_style_mnemonic, "d");
+ break;
default:
break;
}
@@ -8675,7 +8845,7 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
{
/* given (20, 23) | given (0, 3) */
value = ((given >> 16) & 0xf0) | (given & 0xf);
- func (stream, "%d", (int) value);
+ func (stream, dis_style_immediate, "%d", (int) value);
}
break;
@@ -8687,7 +8857,9 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
int offset = given & 0xff;
int multiplier = (given & 0x00000100) ? 4 : 1;
- func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "%s",
+ arm_regnames [(given >> 16) & 0xf]);
if (multiplier > 1)
{
@@ -8699,17 +8871,24 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
if (offset)
{
if (PRE_BIT_SET)
- func (stream, ", #%s%d]%s",
- NEGATIVE_BIT_SET ? "-" : "",
- offset * multiplier,
- WRITEBACK_BIT_SET ? "!" : "");
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%s%d",
+ NEGATIVE_BIT_SET ? "-" : "",
+ offset * multiplier);
+ func (stream, dis_style_text, "]%s",
+ WRITEBACK_BIT_SET ? "!" : "");
+ }
else
- func (stream, "], #%s%d",
- NEGATIVE_BIT_SET ? "-" : "",
- offset * multiplier);
+ {
+ func (stream, dis_style_text, "], ");
+ func (stream, dis_style_immediate, "#%s%d",
+ NEGATIVE_BIT_SET ? "-" : "",
+ offset * multiplier);
+ }
}
else
- func (stream, "]");
+ func (stream, dis_style_text, "]");
}
break;
@@ -8725,25 +8904,41 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
{
case 1:
case 3:
- func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "%s", rn);
+ func (stream, dis_style_text, "], ");
+ func (stream, dis_style_text, "%c", ubit ? '+' : '-');
+ func (stream, dis_style_register, "%s", rm);
if (imm4)
- func (stream, ", lsl #%d", imm4);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "lsl ");
+ func (stream, dis_style_immediate, "#%d", imm4);
+ }
break;
case 4:
case 5:
case 6:
case 7:
- func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "%s", rn);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_text, "%c", ubit ? '+' : '-');
+ func (stream, dis_style_register, "%s", rm);
if (imm4 > 0)
- func (stream, ", lsl #%d", imm4);
- func (stream, "]");
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "lsl ");
+ func (stream, dis_style_immediate, "#%d", imm4);
+ }
+ func (stream, dis_style_text, "]");
if (puw_bits == 5 || puw_bits == 7)
- func (stream, "!");
+ func (stream, dis_style_text, "!");
break;
default:
- func (stream, "INVALID");
+ func (stream, dis_style_text, "INVALID");
}
}
break;
@@ -8752,7 +8947,8 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
{
long imm5;
imm5 = ((given & 0x100) >> 4) | (given & 0xf);
- func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
+ func (stream, dis_style_immediate, "%ld",
+ (imm5 == 0) ? 32 : imm5);
}
break;
@@ -8761,14 +8957,23 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
}
}
else
- func (stream, "%c", *c);
+ {
+ if (*c == ';')
+ base_style = dis_style_comment_start;
+
+ if (*c == '\t')
+ base_style = dis_style_text;
+
+ func (stream, base_style, "%c", *c);
+ }
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
+ func (stream, dis_style_comment_start, "\t; 0x%lx",
+ (value_in_comment & 0xffffffffUL));
if (is_unpredictable)
- func (stream, UNPREDICTABLE_INSTRUCTION);
+ func (stream, dis_style_text, UNPREDICTABLE_INSTRUCTION);
return true;
}
@@ -8804,7 +9009,7 @@ static signed long
print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
bfd_vma offset = 0;
if (((given & 0x000f0000) == 0x000f0000)
@@ -8812,14 +9017,19 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
{
offset = given & 0xfff;
- func (stream, "[pc");
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "pc");
if (PRE_BIT_SET)
{
/* Pre-indexed. Elide offset of positive zero when
non-writeback. */
if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
- func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%s%d",
+ NEGATIVE_BIT_SET ? "-" : "", (int) offset);
+ }
if (NEGATIVE_BIT_SET)
offset = -offset;
@@ -8830,23 +9040,26 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
being used. Probably a very dangerous thing
for the programmer to do, but who are we to
argue ? */
- func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
+ func (stream, dis_style_text, "]%s", WRITEBACK_BIT_SET ? "!" : "");
}
else /* Post indexed. */
{
- func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
+ func (stream, dis_style_text, "], ");
+ func (stream, dis_style_immediate, "#%s%d",
+ NEGATIVE_BIT_SET ? "-" : "", (int) offset);
/* Ie ignore the offset. */
offset = pc + 8;
}
- func (stream, "\t; ");
+ func (stream, dis_style_comment_start, "\t; ");
info->print_address_func (offset, info);
offset = 0;
}
else
{
- func (stream, "[%s",
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "%s",
arm_regnames[(given >> 16) & 0xf]);
if (PRE_BIT_SET)
@@ -8856,15 +9069,20 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
/* Elide offset of positive zero when non-writeback. */
offset = given & 0xfff;
if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
- func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%s%d",
+ NEGATIVE_BIT_SET ? "-" : "", (int) offset);
+ }
}
else
{
- func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
+ func (stream, dis_style_text, ", %s",
+ NEGATIVE_BIT_SET ? "-" : "");
arm_decode_shift (given, func, stream, true);
}
- func (stream, "]%s",
+ func (stream, dis_style_text, "]%s",
WRITEBACK_BIT_SET ? "!" : "");
}
else
@@ -8873,12 +9091,13 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
{
/* Always show offset. */
offset = given & 0xfff;
- func (stream, "], #%s%d",
+ func (stream, dis_style_text, "], ");
+ func (stream, dis_style_immediate, "#%s%d",
NEGATIVE_BIT_SET ? "-" : "", (int) offset);
}
else
{
- func (stream, "], %s",
+ func (stream, dis_style_text, "], %s",
NEGATIVE_BIT_SET ? "-" : "");
arm_decode_shift (given, func, stream, true);
}
@@ -8899,7 +9118,9 @@ print_insn_cde (struct disassemble_info *info, long given, bool thumb)
{
const struct cdeopcode32 *insn;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
+ enum disassembler_style base_style = dis_style_mnemonic;
+ enum disassembler_style old_base_style = base_style;
if (thumb)
{
@@ -8923,8 +9144,23 @@ print_insn_cde (struct disassemble_info *info, long given, bool thumb)
{
switch (*++c)
{
+ case '{':
+ ++c;
+ if (*c == '\0')
+ abort ();
+ old_base_style = base_style;
+ base_style = decode_base_style (*c);
+ ++c;
+ if (*c != ':')
+ abort ();
+ break;
+
+ case '}':
+ base_style = old_base_style;
+ break;
+
case '%':
- func (stream, "%%");
+ func (stream, base_style, "%%");
break;
case '0': case '1': case '2': case '3': case '4':
@@ -8946,29 +9182,32 @@ print_insn_cde (struct disassemble_info *info, long given, bool thumb)
is_unpredictable = true;
/* Fall through. */
case 'r':
- func (stream, "%s", arm_regnames[value]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[value]);
break;
case 'n':
if (value == 15)
- func (stream, "%s", "APSR_nzcv");
+ func (stream, dis_style_register, "%s", "APSR_nzcv");
else
- func (stream, "%s", arm_regnames[value]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[value]);
break;
case 'T':
- func (stream, "%s", arm_regnames[(value + 1) & 15]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[(value + 1) & 15]);
break;
case 'd':
- func (stream, "%ld", value);
+ func (stream, dis_style_immediate, "%ld", value);
break;
case 'V':
if (given & (1 << 6))
- func (stream, "q%ld", value >> 1);
+ func (stream, dis_style_register, "q%ld", value >> 1);
else if (given & (1 << 24))
- func (stream, "d%ld", value);
+ func (stream, dis_style_register, "d%ld", value);
else
{
/* Encoding for S register is different than for D and
@@ -8979,7 +9218,7 @@ print_insn_cde (struct disassemble_info *info, long given, bool thumb)
uint8_t top_bit = (value >> 4) & 1;
uint8_t tmp = (value << 1) & 0x1e;
uint8_t res = tmp | top_bit;
- func (stream, "s%u", res);
+ func (stream, dis_style_register, "s%u", res);
}
break;
@@ -8992,7 +9231,7 @@ print_insn_cde (struct disassemble_info *info, long given, bool thumb)
case 'p':
{
uint8_t proc_number = (given >> 8) & 0x7;
- func (stream, "p%u", proc_number);
+ func (stream, dis_style_register, "p%u", proc_number);
break;
}
@@ -9000,7 +9239,7 @@ print_insn_cde (struct disassemble_info *info, long given, bool thumb)
{
uint8_t a_offset = 28;
if (given & (1 << a_offset))
- func (stream, "a");
+ func (stream, dis_style_mnemonic, "a");
break;
}
default:
@@ -9008,11 +9247,18 @@ print_insn_cde (struct disassemble_info *info, long given, bool thumb)
}
}
else
- func (stream, "%c", *c);
+ {
+ if (*c == ';')
+ base_style = dis_style_comment_start;
+ if (*c == '\t')
+ base_style = dis_style_text;
+
+ func (stream, base_style, "%c", *c);
+ }
}
if (is_unpredictable)
- func (stream, UNPREDICTABLE_INSTRUCTION);
+ func (stream, dis_style_text, UNPREDICTABLE_INSTRUCTION);
return true;
}
@@ -9033,7 +9279,9 @@ print_insn_neon (struct disassemble_info *info, long given, bool thumb)
{
const struct opcode32 *insn;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
+ enum disassembler_style base_style = dis_style_mnemonic;
+ enum disassembler_style old_base_style = base_style;
if (thumb)
{
@@ -9111,8 +9359,23 @@ print_insn_neon (struct disassemble_info *info, long given, bool thumb)
{
switch (*++c)
{
+ case '{':
+ ++c;
+ if (*c == '\0')
+ abort ();
+ old_base_style = base_style;
+ base_style = decode_base_style (*c);
+ ++c;
+ if (*c != ':')
+ abort ();
+ break;
+
+ case '}':
+ base_style = old_base_style;
+ break;
+
case '%':
- func (stream, "%%");
+ func (stream, base_style, "%%");
break;
case 'u':
@@ -9121,7 +9384,8 @@ print_insn_neon (struct disassemble_info *info, long given, bool thumb)
/* Fall through. */
case 'c':
- func (stream, "%s", arm_conditional[cond]);
+ func (stream, dis_style_mnemonic, "%s",
+ arm_conditional[cond]);
break;
case 'A':
@@ -9149,22 +9413,42 @@ print_insn_neon (struct disassemble_info *info, long given, bool thumb)
int stride = (enc[type] >> 4) + 1;
int ix;
- func (stream, "{");
+ func (stream, dis_style_text, "{");
if (stride > 1)
for (ix = 0; ix != n; ix++)
- func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
+ {
+ if (ix > 0)
+ func (stream, dis_style_text, ",");
+ func (stream, dis_style_register, "d%d",
+ rd + ix * stride);
+ }
else if (n == 1)
- func (stream, "d%d", rd);
+ func (stream, dis_style_register, "d%d", rd);
else
- func (stream, "d%d-d%d", rd, rd + n - 1);
- func (stream, "}, [%s", arm_regnames[rn]);
+ {
+ func (stream, dis_style_register, "d%d", rd);
+ func (stream, dis_style_text, "-");
+ func (stream, dis_style_register, "d%d",
+ rd + n - 1);
+ }
+ func (stream, dis_style_text, "}, [");
+ func (stream, dis_style_register, "%s",
+ arm_regnames[rn]);
if (align)
- func (stream, " :%d", 32 << align);
- func (stream, "]");
+ {
+ func (stream, dis_style_text, " :");
+ func (stream, dis_style_immediate, "%d",
+ 32 << align);
+ }
+ func (stream, dis_style_text, "]");
if (rm == 0xd)
- func (stream, "!");
+ func (stream, dis_style_text, "!");
else if (rm != 0xf)
- func (stream, ", %s", arm_regnames[rm]);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "%s",
+ arm_regnames[rm]);
+ }
}
break;
@@ -9228,18 +9512,31 @@ print_insn_neon (struct disassemble_info *info, long given, bool thumb)
abort ();
}
- func (stream, "{");
+ func (stream, dis_style_text, "{");
for (i = 0; i < length; i++)
- func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
- rd + i * stride, idx);
- func (stream, "}, [%s", arm_regnames[rn]);
+ {
+ if (i > 0)
+ func (stream, dis_style_text, ",");
+ func (stream, dis_style_register, "d%d[%d]",
+ rd + i * stride, idx);
+ }
+ func (stream, dis_style_text, "}, [");
+ func (stream, dis_style_register, "%s",
+ arm_regnames[rn]);
if (align)
- func (stream, " :%d", align);
- func (stream, "]");
+ {
+ func (stream, dis_style_text, " :");
+ func (stream, dis_style_immediate, "%d", align);
+ }
+ func (stream, dis_style_text, "]");
if (rm == 0xd)
- func (stream, "!");
+ func (stream, dis_style_text, "!");
else if (rm != 0xf)
- func (stream, ", %s", arm_regnames[rm]);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "%s",
+ arm_regnames[rm]);
+ }
}
break;
@@ -9260,30 +9557,51 @@ print_insn_neon (struct disassemble_info *info, long given, bool thumb)
else
stride++;
- func (stream, "{");
+ func (stream, dis_style_text, "{");
if (stride > 1)
for (ix = 0; ix != n; ix++)
- func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
+ {
+ if (ix > 0)
+ func (stream, dis_style_text, ",");
+ func (stream, dis_style_register, "d%d[]",
+ rd + ix * stride);
+ }
else if (n == 1)
- func (stream, "d%d[]", rd);
+ func (stream, dis_style_register, "d%d[]", rd);
else
- func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
- func (stream, "}, [%s", arm_regnames[rn]);
+ {
+ func (stream, dis_style_register, "d%d[]", rd);
+ func (stream, dis_style_text, "-");
+ func (stream, dis_style_register, "d%d[]",
+ rd + n - 1);
+ }
+ func (stream, dis_style_text, "}, [");
+ func (stream, dis_style_register, "%s",
+ arm_regnames[rn]);
if (align)
{
align = (8 * (type + 1)) << size;
if (type == 3)
align = (size > 1) ? align >> 1 : align;
if (type == 2 || (type == 0 && !size))
- func (stream, " :<bad align %d>", align);
+ func (stream, dis_style_text,
+ " :<bad align %d>", align);
else
- func (stream, " :%d", align);
+ {
+ func (stream, dis_style_text, " :");
+ func (stream, dis_style_immediate,
+ "%d", align);
+ }
}
- func (stream, "]");
+ func (stream, dis_style_text, "]");
if (rm == 0xd)
- func (stream, "!");
+ func (stream, dis_style_text, "!");
else if (rm != 0xf)
- func (stream, ", %s", arm_regnames[rm]);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "%s",
+ arm_regnames[rm]);
+ }
}
break;
@@ -9294,7 +9612,7 @@ print_insn_neon (struct disassemble_info *info, long given, bool thumb)
int reg = raw_reg & ((4 << size) - 1);
int ix = raw_reg >> size >> 2;
- func (stream, "d%d[%d]", reg, ix);
+ func (stream, dis_style_register, "d%d[%d]", reg, ix);
}
break;
@@ -9373,7 +9691,8 @@ print_insn_neon (struct disassemble_info *info, long given, bool thumb)
}
else
{
- func (stream, "<illegal constant %.8x:%x:%x>",
+ func (stream, dis_style_text,
+ "<illegal constant %.8x:%x:%x>",
bits, cmode, op);
size = 32;
break;
@@ -9381,11 +9700,15 @@ print_insn_neon (struct disassemble_info *info, long given, bool thumb)
switch (size)
{
case 8:
- func (stream, "#%ld\t; 0x%.2lx", value, value);
+ func (stream, dis_style_immediate, "#%ld", value);
+ func (stream, dis_style_comment_start,
+ "\t; 0x%.2lx", value);
break;
case 16:
- func (stream, "#%ld\t; 0x%.4lx", value, value);
+ func (stream, dis_style_immediate, "#%ld", value);
+ func (stream, dis_style_comment_start,
+ "\t; 0x%.4lx", value);
break;
case 32:
@@ -9405,18 +9728,24 @@ print_insn_neon (struct disassemble_info *info, long given, bool thumb)
(& floatformat_ieee_single_little, valbytes,
& fvalue);
- func (stream, "#%.7g\t; 0x%.8lx", fvalue,
- value);
+ func (stream, dis_style_immediate,
+ "#%.7g", fvalue);
+ func (stream, dis_style_comment_start,
+ "\t; 0x%.8lx", value);
}
else
- func (stream, "#%ld\t; 0x%.8lx",
- (long) (((value & 0x80000000L) != 0)
- ? value | ~0xffffffffL : value),
- value);
+ {
+ func (stream, dis_style_immediate, "#%ld",
+ (long) (((value & 0x80000000L) != 0)
+ ? value | ~0xffffffffL : value));
+ func (stream, dis_style_comment_start,
+ "\t; 0x%.8lx", value);
+ }
break;
case 64:
- func (stream, "#0x%.8lx%.8lx", hival, value);
+ func (stream, dis_style_immediate,
+ "#0x%.8lx%.8lx", hival, value);
break;
default:
@@ -9430,12 +9759,23 @@ print_insn_neon (struct disassemble_info *info, long given, bool thumb)
int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
int num = (given >> 8) & 0x3;
+ func (stream, dis_style_text, "{");
if (!num)
- func (stream, "{d%d}", regno);
+ func (stream, dis_style_register, "d%d", regno);
else if (num + regno >= 32)
- func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
+ {
+ func (stream, dis_style_register, "d%d", regno);
+ func (stream, dis_style_text, "-<overflow reg d%d",
+ regno + num);
+ }
else
- func (stream, "{d%d-d%d}", regno, regno + num);
+ {
+ func (stream, dis_style_register, "d%d", regno);
+ func (stream, dis_style_text, "-");
+ func (stream, dis_style_register, "d%d",
+ regno + num);
+ }
+ func (stream, dis_style_text, "}");
}
break;
@@ -9451,14 +9791,16 @@ print_insn_neon (struct disassemble_info *info, long given, bool thumb)
switch (*c)
{
case 'r':
- func (stream, "%s", arm_regnames[value]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[value]);
break;
case 'd':
- func (stream, "%ld", value);
+ func (stream, base_style, "%ld", value);
value_in_comment = value;
break;
case 'e':
- func (stream, "%ld", (1ul << width) - value);
+ func (stream, dis_style_immediate, "%ld",
+ (1ul << width) - value);
break;
case 'S':
@@ -9481,9 +9823,11 @@ print_insn_neon (struct disassemble_info *info, long given, bool thumb)
high = limit & 3;
if (value < low || value > high)
- func (stream, "<illegal width %d>", base << value);
+ func (stream, dis_style_text,
+ "<illegal width %d>", base << value);
else
- func (stream, "%d", base << value);
+ func (stream, base_style, "%d",
+ base << value);
}
break;
case 'R':
@@ -9491,28 +9835,31 @@ print_insn_neon (struct disassemble_info *info, long given, bool thumb)
goto Q;
/* FALLTHROUGH */
case 'D':
- func (stream, "d%ld", value);
+ func (stream, dis_style_register, "d%ld", value);
break;
case 'Q':
Q:
if (value & 1)
- func (stream, "<illegal reg q%ld.5>", value >> 1);
+ func (stream, dis_style_text,
+ "<illegal reg q%ld.5>", value >> 1);
else
- func (stream, "q%ld", value >> 1);
+ func (stream, dis_style_register,
+ "q%ld", value >> 1);
break;
case '`':
c++;
if (value == 0)
- func (stream, "%c", *c);
+ func (stream, dis_style_text, "%c", *c);
break;
case '\'':
c++;
if (value == ((1ul << width) - 1))
- func (stream, "%c", *c);
+ func (stream, dis_style_text, "%c", *c);
break;
case '?':
- func (stream, "%c", c[(1 << width) - (int) value]);
+ func (stream, dis_style_mnemonic, "%c",
+ c[(1 << width) - (int) value]);
c += 1 << width;
break;
default:
@@ -9526,14 +9873,24 @@ print_insn_neon (struct disassemble_info *info, long given, bool thumb)
}
}
else
- func (stream, "%c", *c);
+ {
+ if (*c == ';')
+ base_style = dis_style_comment_start;
+
+ if (*c == '\t')
+ base_style = dis_style_text;
+
+ func (stream, base_style, "%c", *c);
+
+ }
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", value_in_comment);
+ func (stream, dis_style_comment_start, "\t; 0x%lx",
+ value_in_comment);
if (is_unpredictable)
- func (stream, UNPREDICTABLE_INSTRUCTION);
+ func (stream, dis_style_text, UNPREDICTABLE_INSTRUCTION);
return true;
}
@@ -9550,7 +9907,9 @@ print_insn_mve (struct disassemble_info *info, long given)
{
const struct mopcode32 *insn;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
+ enum disassembler_style base_style = dis_style_mnemonic;
+ enum disassembler_style old_base_style = base_style;
for (insn = mve_opcodes; insn->assembler; insn++)
{
@@ -9591,19 +9950,35 @@ print_insn_mve (struct disassemble_info *info, long given)
{
switch (*++c)
{
+ case '{':
+ ++c;
+ if (*c == '\0')
+ abort ();
+ old_base_style = base_style;
+ base_style = decode_base_style (*c);
+ ++c;
+ if (*c != ':')
+ abort ();
+ break;
+
+ case '}':
+ base_style = old_base_style;
+ break;
+
case '%':
- func (stream, "%%");
+ func (stream, base_style, "%%");
break;
case 'a':
/* Don't print anything for '+' as it is implied. */
if (arm_decode_field (given, 23, 23) == 0)
- func (stream, "-");
+ func (stream, dis_style_immediate, "-");
break;
case 'c':
if (ifthen_state)
- func (stream, "%s", arm_conditional[IFTHEN_COND]);
+ func (stream, dis_style_mnemonic, "%s",
+ arm_conditional[IFTHEN_COND]);
break;
case 'd':
@@ -9613,7 +9988,8 @@ print_insn_mve (struct disassemble_info *info, long given)
case 'i':
{
long mve_mask = mve_extract_pred_mask (given);
- func (stream, "%s", mve_predicatenames[mve_mask]);
+ func (stream, dis_style_mnemonic, "%s",
+ mve_predicatenames[mve_mask]);
}
break;
@@ -9622,12 +9998,13 @@ print_insn_mve (struct disassemble_info *info, long given)
unsigned int imm5 = 0;
imm5 |= arm_decode_field (given, 6, 7);
imm5 |= (arm_decode_field (given, 12, 14) << 2);
- func (stream, "#%u", (imm5 == 0) ? 32 : imm5);
+ func (stream, dis_style_immediate, "#%u",
+ (imm5 == 0) ? 32 : imm5);
}
break;
case 'k':
- func (stream, "#%u",
+ func (stream, dis_style_immediate, "#%u",
(arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
break;
@@ -9642,7 +10019,9 @@ print_insn_mve (struct disassemble_info *info, long given)
= arm_decode_field (given, 4, 4)
| (arm_decode_field (given, 6, 6) << 1);
- func (stream, ", uxtw #%lu", size);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "uxtw ");
+ func (stream, dis_style_immediate, "#%lu", size);
}
break;
@@ -9668,17 +10047,17 @@ print_insn_mve (struct disassemble_info *info, long given)
&& ((op1 == 0) || (op1 == 1)))
;
else
- func (stream, "s");
+ func (stream, dis_style_mnemonic, "s");
}
else
- func (stream, "u");
+ func (stream, dis_style_mnemonic, "u");
}
else
{
if (arm_decode_field (given, 28, 28) == 0)
- func (stream, "s");
+ func (stream, dis_style_mnemonic, "s");
else
- func (stream, "u");
+ func (stream, dis_style_mnemonic, "u");
}
}
break;
@@ -9689,7 +10068,7 @@ print_insn_mve (struct disassemble_info *info, long given)
case 'w':
if (arm_decode_field (given, 21, 21) == 1)
- func (stream, "!");
+ func (stream, dis_style_text, "!");
break;
case 'B':
@@ -9708,14 +10087,14 @@ print_insn_mve (struct disassemble_info *info, long given)
case 'T':
if (arm_decode_field (given, 12, 12) == 0)
- func (stream, "b");
+ func (stream, dis_style_mnemonic, "b");
else
- func (stream, "t");
+ func (stream, dis_style_mnemonic, "t");
break;
case 'X':
if (arm_decode_field (given, 12, 12) == 1)
- func (stream, "x");
+ func (stream, dis_style_mnemonic, "x");
break;
case '0': case '1': case '2': case '3': case '4':
@@ -9732,25 +10111,29 @@ print_insn_mve (struct disassemble_info *info, long given)
if (value == 13)
is_unpredictable = true;
else if (value == 15)
- func (stream, "zr");
+ func (stream, dis_style_register, "zr");
else
- func (stream, "%s", arm_regnames[value]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[value]);
break;
case 'c':
- func (stream, "%s", arm_conditional[value]);
+ func (stream, dis_style_sub_mnemonic, "%s",
+ arm_conditional[value]);
break;
case 'C':
value ^= 1;
- func (stream, "%s", arm_conditional[value]);
+ func (stream, dis_style_sub_mnemonic, "%s",
+ arm_conditional[value]);
break;
case 'S':
if (value == 13 || value == 15)
is_unpredictable = true;
else
- func (stream, "%s", arm_regnames[value]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[value]);
break;
case 's':
@@ -9760,16 +10143,17 @@ print_insn_mve (struct disassemble_info *info, long given)
break;
case 'I':
if (value == 1)
- func (stream, "i");
+ func (stream, dis_style_mnemonic, "i");
break;
case 'A':
if (value == 1)
- func (stream, "a");
+ func (stream, dis_style_mnemonic, "a");
break;
case 'h':
{
unsigned int odd_reg = (value << 1) | 1;
- func (stream, "%s", arm_regnames[odd_reg]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[odd_reg]);
}
break;
case 'i':
@@ -9793,32 +10177,35 @@ print_insn_mve (struct disassemble_info *info, long given)
break;
}
- func (stream, "%lu", mod_imm);
+ func (stream, dis_style_immediate, "%lu",
+ mod_imm);
}
break;
case 'k':
- func (stream, "%lu", 64 - value);
+ func (stream, dis_style_immediate, "%lu",
+ 64 - value);
break;
case 'l':
{
unsigned int even_reg = value << 1;
- func (stream, "%s", arm_regnames[even_reg]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[even_reg]);
}
break;
case 'u':
switch (value)
{
case 0:
- func (stream, "1");
+ func (stream, dis_style_immediate, "1");
break;
case 1:
- func (stream, "2");
+ func (stream, dis_style_immediate, "2");
break;
case 2:
- func (stream, "4");
+ func (stream, dis_style_immediate, "4");
break;
case 3:
- func (stream, "8");
+ func (stream, dis_style_immediate, "8");
break;
default:
break;
@@ -9828,7 +10215,8 @@ print_insn_mve (struct disassemble_info *info, long given)
print_mve_rotate (info, value, width);
break;
case 'r':
- func (stream, "%s", arm_regnames[value]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[value]);
break;
case 'd':
if (insn->mve_op == MVE_VQSHL_T2
@@ -9847,10 +10235,10 @@ print_insn_mve (struct disassemble_info *info, long given)
switch (value)
{
case 0x00:
- func (stream, "8");
+ func (stream, dis_style_immediate, "8");
break;
case 0x01:
- func (stream, "16");
+ func (stream, dis_style_immediate, "16");
break;
case 0x10:
print_mve_undefined (info, UNDEF_SIZE_0);
@@ -9864,21 +10252,23 @@ print_insn_mve (struct disassemble_info *info, long given)
{
if (insn->mve_op == MVE_VSHLC && value == 0)
value = 32;
- func (stream, "%ld", value);
+ func (stream, base_style, "%ld", value);
value_in_comment = value;
}
break;
case 'F':
- func (stream, "s%ld", value);
+ func (stream, dis_style_register, "s%ld", value);
break;
case 'Q':
if (value & 0x8)
- func (stream, "<illegal reg q%ld.5>", value);
+ func (stream, dis_style_text,
+ "<illegal reg q%ld.5>", value);
else
- func (stream, "q%ld", value);
+ func (stream, dis_style_register, "q%ld", value);
break;
case 'x':
- func (stream, "0x%08lx", value);
+ func (stream, dis_style_immediate,
+ "0x%08lx", value);
break;
default:
abort ();
@@ -9890,11 +10280,20 @@ print_insn_mve (struct disassemble_info *info, long given)
}
}
else
- func (stream, "%c", *c);
+ {
+ if (*c == ';')
+ base_style = dis_style_comment_start;
+
+ if (*c == '\t')
+ base_style = dis_style_text;
+
+ func (stream, base_style, "%c", *c);
+ }
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", value_in_comment);
+ func (stream, dis_style_comment_start, "\t; 0x%lx",
+ value_in_comment);
if (is_unpredictable)
print_mve_unpredictable (info, unpredictable_cond);
@@ -9991,8 +10390,10 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
{
const struct opcode32 *insn;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
struct arm_private_data *private_data = info->private_data;
+ enum disassembler_style base_style = dis_style_mnemonic;
+ enum disassembler_style old_base_style = base_style;
if (print_insn_coprocessor (pc, info, given, false))
return;
@@ -10032,8 +10433,23 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
switch (*++c)
{
+ case '{':
+ ++c;
+ if (*c == '\0')
+ abort ();
+ old_base_style = base_style;
+ base_style = decode_base_style (*c);
+ ++c;
+ if (*c != ':')
+ abort ();
+ break;
+
+ case '}':
+ base_style = old_base_style;
+ break;
+
case '%':
- func (stream, "%%");
+ func (stream, base_style, "%%");
break;
case 'a':
@@ -10059,18 +10475,33 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
{
/* Elide positive zero offset. */
if (offset || NEGATIVE_BIT_SET)
- func (stream, "[pc, #%s%d]\t; ",
- NEGATIVE_BIT_SET ? "-" : "", (int) offset);
+ {
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "pc");
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%s%d",
+ (NEGATIVE_BIT_SET ? "-" : ""),
+ (int) offset);
+ func (stream, dis_style_text, "]");
+ }
else
- func (stream, "[pc]\t; ");
+ {
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "pc");
+ func (stream, dis_style_text, "]");
+ }
if (NEGATIVE_BIT_SET)
offset = -offset;
+ func (stream, dis_style_comment_start, "\t; ");
info->print_address_func (offset + pc + 8, info);
}
else
{
/* Always show the offset. */
- func (stream, "[pc], #%s%d",
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "pc");
+ func (stream, dis_style_text, "], ");
+ func (stream, dis_style_immediate, "#%s%d",
NEGATIVE_BIT_SET ? "-" : "", (int) offset);
if (! allow_unpredictable)
is_unpredictable = true;
@@ -10080,7 +10511,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
{
int offset = ((given & 0xf00) >> 4) | (given & 0xf);
- func (stream, "[%s",
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "%s",
arm_regnames[(given >> 16) & 0xf]);
if (PRE_BIT_SET)
@@ -10091,8 +10523,13 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
positive zero. */
if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
|| offset)
- func (stream, ", #%s%d",
- NEGATIVE_BIT_SET ? "-" : "", offset);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate,
+ "#%s%d",
+ (NEGATIVE_BIT_SET ? "-" : ""),
+ offset);
+ }
if (NEGATIVE_BIT_SET)
offset = -offset;
@@ -10102,8 +10539,9 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
else
{
/* Register Offset or Register Pre-Indexed. */
- func (stream, ", %s%s",
- NEGATIVE_BIT_SET ? "-" : "",
+ func (stream, dis_style_text, ", %s",
+ NEGATIVE_BIT_SET ? "-" : "");
+ func (stream, dis_style_register, "%s",
arm_regnames[given & 0xf]);
/* Writing back to the register that is the source/
@@ -10114,7 +10552,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
is_unpredictable = true;
}
- func (stream, "]%s",
+ func (stream, dis_style_text, "]%s",
WRITEBACK_BIT_SET ? "!" : "");
}
else
@@ -10123,7 +10561,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
{
/* Immediate Post-indexed. */
/* PR 10924: Offset must be printed, even if it is zero. */
- func (stream, "], #%s%d",
+ func (stream, dis_style_text, "], ");
+ func (stream, dis_style_immediate, "#%s%d",
NEGATIVE_BIT_SET ? "-" : "", offset);
if (NEGATIVE_BIT_SET)
offset = -offset;
@@ -10132,8 +10571,9 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
else
{
/* Register Post-indexed. */
- func (stream, "], %s%s",
- NEGATIVE_BIT_SET ? "-" : "",
+ func (stream, dis_style_text, "], %s",
+ NEGATIVE_BIT_SET ? "-" : "");
+ func (stream, dis_style_register, "%s",
arm_regnames[given & 0xf]);
/* Writing back to the register that is the source/
@@ -10173,7 +10613,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
case 'c':
if (((given >> 28) & 0xf) != 0xe)
- func (stream, "%s",
+ func (stream, dis_style_mnemonic, "%s",
arm_conditional [(given >> 28) & 0xf]);
break;
@@ -10182,16 +10622,17 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
int started = 0;
int reg;
- func (stream, "{");
+ func (stream, dis_style_text, "{");
for (reg = 0; reg < 16; reg++)
if ((given & (1 << reg)) != 0)
{
if (started)
- func (stream, ", ");
+ func (stream, dis_style_text, ", ");
started = 1;
- func (stream, "%s", arm_regnames[reg]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[reg]);
}
- func (stream, "}");
+ func (stream, dis_style_text, "}");
if (! started)
is_unpredictable = true;
}
@@ -10217,9 +10658,13 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
break;
if (i != rotate)
- func (stream, "#%d, %d", immed, rotate);
+ {
+ func (stream, dis_style_immediate, "#%d", immed);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "%d", rotate);
+ }
else
- func (stream, "#%d", a);
+ func (stream, dis_style_immediate, "#%d", a);
value_in_comment = a;
}
else
@@ -10237,7 +10682,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
obsolete in V6 onwards. */
if (! ARM_CPU_HAS_FEATURE (private_data->features, \
arm_ext_v6))
- func (stream, "p");
+ func (stream, dis_style_mnemonic, "p");
else
is_unpredictable = true;
}
@@ -10245,7 +10690,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
case 't':
if ((given & 0x01200000) == 0x00200000)
- func (stream, "t");
+ func (stream, dis_style_mnemonic, "t");
break;
case 'A':
@@ -10256,29 +10701,32 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
if (NEGATIVE_BIT_SET)
value_in_comment = - value_in_comment;
- func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
+ func (stream, dis_style_text, "[%s",
+ arm_regnames [(given >> 16) & 0xf]);
if (PRE_BIT_SET)
{
if (offset)
- func (stream, ", #%d]%s",
+ func (stream, dis_style_text, ", #%d]%s",
(int) value_in_comment,
WRITEBACK_BIT_SET ? "!" : "");
else
- func (stream, "]");
+ func (stream, dis_style_text, "]");
}
else
{
- func (stream, "]");
+ func (stream, dis_style_text, "]");
if (WRITEBACK_BIT_SET)
{
if (offset)
- func (stream, ", #%d", (int) value_in_comment);
+ func (stream, dis_style_text,
+ ", #%d", (int) value_in_comment);
}
else
{
- func (stream, ", {%d}", (int) offset);
+ func (stream, dis_style_text,
+ ", {%d}", (int) offset);
value_in_comment = offset;
}
}
@@ -10323,22 +10771,24 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
name = banked_regname (sysm);
if (name != NULL)
- func (stream, "%s", name);
+ func (stream, dis_style_register, "%s", name);
else
- func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
+ func (stream, dis_style_text,
+ "(UNDEF: %lu)", (unsigned long) sysm);
}
else
{
- func (stream, "%cPSR_",
+ func (stream, dis_style_register, "%cPSR_",
(given & 0x00400000) ? 'S' : 'C');
+
if (given & 0x80000)
- func (stream, "f");
+ func (stream, dis_style_register, "f");
if (given & 0x40000)
- func (stream, "s");
+ func (stream, dis_style_register, "s");
if (given & 0x20000)
- func (stream, "x");
+ func (stream, dis_style_register, "x");
if (given & 0x10000)
- func (stream, "c");
+ func (stream, dis_style_register, "c");
}
break;
@@ -10347,9 +10797,12 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
{
switch (given & 0xf)
{
- case 0xf: func (stream, "sy"); break;
+ case 0xf:
+ func (stream, dis_style_sub_mnemonic, "sy");
+ break;
default:
- func (stream, "#%d", (int) given & 0xf);
+ func (stream, dis_style_immediate, "#%d",
+ (int) given & 0xf);
break;
}
}
@@ -10357,9 +10810,10 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
{
const char * opt = data_barrier_option (given & 0xf);
if (opt != NULL)
- func (stream, "%s", opt);
+ func (stream, dis_style_sub_mnemonic, "%s", opt);
else
- func (stream, "#%d", (int) given & 0xf);
+ func (stream, dis_style_immediate,
+ "#%d", (int) given & 0xf);
}
break;
@@ -10401,46 +10855,54 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
is_unpredictable = true;
U_reg = value;
}
- func (stream, "%s", arm_regnames[value]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[value]);
break;
case 'd':
- func (stream, "%ld", value);
+ func (stream, base_style, "%ld", value);
value_in_comment = value;
break;
case 'b':
- func (stream, "%ld", value * 8);
+ func (stream, dis_style_immediate,
+ "%ld", value * 8);
value_in_comment = value * 8;
break;
case 'W':
- func (stream, "%ld", value + 1);
+ func (stream, dis_style_immediate,
+ "%ld", value + 1);
value_in_comment = value + 1;
break;
case 'x':
- func (stream, "0x%08lx", value);
+ func (stream, dis_style_immediate,
+ "0x%08lx", value);
/* Some SWI instructions have special
meanings. */
if ((given & 0x0fffffff) == 0x0FF00000)
- func (stream, "\t; IMB");
+ func (stream, dis_style_comment_start,
+ "\t; IMB");
else if ((given & 0x0fffffff) == 0x0FF00001)
- func (stream, "\t; IMBRange");
+ func (stream, dis_style_comment_start,
+ "\t; IMBRange");
break;
case 'X':
- func (stream, "%01lx", value & 0xf);
+ func (stream, dis_style_immediate,
+ "%01lx", value & 0xf);
value_in_comment = value;
break;
case '`':
c++;
if (value == 0)
- func (stream, "%c", *c);
+ func (stream, dis_style_text, "%c", *c);
break;
case '\'':
c++;
if (value == ((1ul << width) - 1))
- func (stream, "%c", *c);
+ func (stream, base_style, "%c", *c);
break;
case '?':
- func (stream, "%c", c[(1 << width) - (int) value]);
+ func (stream, base_style, "%c",
+ c[(1 << width) - (int) value]);
c += 1 << width;
break;
default:
@@ -10454,7 +10916,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
int imm;
imm = (given & 0xf) | ((given & 0xfff00) >> 4);
- func (stream, "%d", imm);
+ func (stream, dis_style_immediate, "%d", imm);
value_in_comment = imm;
}
break;
@@ -10468,9 +10930,14 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
long w = msb - lsb + 1;
if (w > 0)
- func (stream, "#%lu, #%lu", lsb, w);
+ {
+ func (stream, dis_style_immediate, "#%lu", lsb);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%lu", w);
+ }
else
- func (stream, "(invalid: %lu:%lu)", lsb, msb);
+ func (stream, dis_style_text,
+ "(invalid: %lu:%lu)", lsb, msb);
}
break;
@@ -10484,9 +10951,10 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
name = banked_regname (sysm);
if (name != NULL)
- func (stream, "%s", name);
+ func (stream, dis_style_register, "%s", name);
else
- func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
+ func (stream, dis_style_text,
+ "(UNDEF: %lu)", (unsigned long) sysm);
}
break;
@@ -10498,7 +10966,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
long lo = (given & 0x00000fff);
long imm16 = hi | lo;
- func (stream, "#%lu", imm16);
+ func (stream, dis_style_immediate, "#%lu", imm16);
value_in_comment = imm16;
}
break;
@@ -10508,19 +10976,29 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
}
}
else
- func (stream, "%c", *c);
+ {
+
+ if (*c == ';')
+ base_style = dis_style_comment_start;
+
+ if (*c == '\t')
+ base_style = dis_style_text;
+
+ func (stream, base_style, "%c", *c);
+ }
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
+ func (stream, dis_style_comment_start, "\t; 0x%lx",
+ (value_in_comment & 0xffffffffUL));
if (is_unpredictable)
- func (stream, UNPREDICTABLE_INSTRUCTION);
+ func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
return;
}
}
- func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
+ func (stream, dis_style_text, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
return;
}
@@ -10531,7 +11009,9 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
{
const struct opcode16 *insn;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
+ enum disassembler_style base_style = dis_style_mnemonic;
+ enum disassembler_style old_base_style = base_style;
for (insn = thumb_opcodes; insn->assembler; insn++)
if ((given & insn->mask) == insn->value)
@@ -10546,26 +11026,50 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
if (*c != '%')
{
- func (stream, "%c", *c);
+ if (*c == ';')
+ base_style = dis_style_comment_start;
+
+ if (*c == '\t')
+ base_style = dis_style_text;
+
+ func (stream, base_style, "%c", *c);
+
continue;
}
switch (*++c)
{
+ case '{':
+ ++c;
+ if (*c == '\0')
+ abort ();
+ old_base_style = base_style;
+ base_style = decode_base_style (*c);
+ ++c;
+ if (*c != ':')
+ abort ();
+ break;
+
+ case '}':
+ base_style = old_base_style;
+ break;
+
case '%':
- func (stream, "%%");
+ func (stream, base_style, "%%");
break;
case 'c':
if (ifthen_state)
- func (stream, "%s", arm_conditional[IFTHEN_COND]);
+ func (stream, dis_style_mnemonic, "%s",
+ arm_conditional[IFTHEN_COND]);
break;
case 'C':
if (ifthen_state)
- func (stream, "%s", arm_conditional[IFTHEN_COND]);
+ func (stream, dis_style_mnemonic, "%s",
+ arm_conditional[IFTHEN_COND]);
else
- func (stream, "s");
+ func (stream, dis_style_mnemonic, "s");
break;
case 'I':
@@ -10574,19 +11078,24 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
ifthen_next_state = given & 0xff;
for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
- func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
- func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
+ func (stream, dis_style_mnemonic,
+ ((given ^ tmp) & 0x10) ? "e" : "t");
+ func (stream, dis_style_text, "\t");
+ func (stream, dis_style_sub_mnemonic, "%s",
+ arm_conditional[(given >> 4) & 0xf]);
}
break;
case 'x':
if (ifthen_next_state)
- func (stream, "\t; unpredictable branch in IT block\n");
+ func (stream, dis_style_comment_start,
+ "\t; unpredictable branch in IT block\n");
break;
case 'X':
if (ifthen_state)
- func (stream, "\t; unpredictable <IT:%s>",
+ func (stream, dis_style_comment_start,
+ "\t; unpredictable <IT:%s>",
arm_conditional[IFTHEN_COND]);
break;
@@ -10598,7 +11107,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
if (given & (1 << 6))
reg += 8;
- func (stream, "%s", arm_regnames[reg]);
+ func (stream, dis_style_register, "%s", arm_regnames[reg]);
}
break;
@@ -10610,7 +11119,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
if (given & (1 << 7))
reg += 8;
- func (stream, "%s", arm_regnames[reg]);
+ func (stream, dis_style_register, "%s", arm_regnames[reg]);
}
break;
@@ -10627,7 +11136,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
int started = 0;
int reg;
- func (stream, "{");
+ func (stream, dis_style_text, "{");
/* It would be nice if we could spot
ranges, and generate the rS-rE format: */
@@ -10635,27 +11144,30 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
if ((given & (1 << reg)) != 0)
{
if (started)
- func (stream, ", ");
+ func (stream, dis_style_text, ", ");
started = 1;
- func (stream, "%s", arm_regnames[reg]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[reg]);
}
if (domasklr)
{
if (started)
- func (stream, ", ");
+ func (stream, dis_style_text, ", ");
started = 1;
- func (stream, "%s", arm_regnames[14] /* "lr" */);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[14] /* "lr" */);
}
if (domaskpc)
{
if (started)
- func (stream, ", ");
- func (stream, "%s", arm_regnames[15] /* "pc" */);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "%s",
+ arm_regnames[15] /* "pc" */);
}
- func (stream, "}");
+ func (stream, dis_style_text, "}");
}
break;
@@ -10664,7 +11176,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
writeback if the base register is not in the register
mask. */
if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
- func (stream, "!");
+ func (stream, dis_style_text, "!");
break;
case 'b':
@@ -10689,7 +11201,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
long imm = (given & 0x07c0) >> 6;
if (imm == 0)
imm = 32;
- func (stream, "#%ld", imm);
+ func (stream, dis_style_immediate, "#%ld", imm);
}
break;
@@ -10719,21 +11231,25 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
switch (*c)
{
case 'r':
- func (stream, "%s", arm_regnames[reg]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[reg]);
break;
case 'd':
- func (stream, "%ld", (long) reg);
+ func (stream, dis_style_immediate, "%ld",
+ (long) reg);
value_in_comment = reg;
break;
case 'H':
- func (stream, "%ld", (long) (reg << 1));
+ func (stream, dis_style_immediate, "%ld",
+ (long) (reg << 1));
value_in_comment = reg << 1;
break;
case 'W':
- func (stream, "%ld", (long) (reg << 2));
+ func (stream, dis_style_immediate, "%ld",
+ (long) (reg << 2));
value_in_comment = reg << 2;
break;
@@ -10747,7 +11263,8 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
break;
case 'x':
- func (stream, "0x%04lx", (long) reg);
+ func (stream, dis_style_immediate, "0x%04lx",
+ (long) reg);
break;
case 'B':
@@ -10763,7 +11280,8 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
break;
case 'c':
- func (stream, "%s", arm_conditional [reg]);
+ func (stream, dis_style_mnemonic, "%s",
+ arm_conditional [reg]);
break;
default:
@@ -10775,15 +11293,15 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
case '\'':
c++;
if ((given & (1 << bitstart)) != 0)
- func (stream, "%c", *c);
+ func (stream, base_style, "%c", *c);
break;
case '?':
++c;
if ((given & (1 << bitstart)) != 0)
- func (stream, "%c", *c++);
+ func (stream, base_style, "%c", *c++);
else
- func (stream, "%c", *++c);
+ func (stream, base_style, "%c", *++c);
break;
default:
@@ -10798,12 +11316,13 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", value_in_comment);
+ func (stream, dis_style_comment_start,
+ "\t; 0x%lx", value_in_comment);
return;
}
/* No match. */
- func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
+ func (stream, dis_style_text, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
return;
}
@@ -10850,8 +11369,10 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
{
const struct opcode32 *insn;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
bool is_mve = is_mve_architecture (info);
+ enum disassembler_style base_style = dis_style_mnemonic;
+ enum disassembler_style old_base_style = base_style;
if (print_insn_coprocessor (pc, info, given, true))
return;
@@ -10880,29 +11401,51 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
{
if (*c != '%')
{
- func (stream, "%c", *c);
+ if (*c == ';')
+ base_style = dis_style_comment_start;
+ if (*c == '\t')
+ base_style = dis_style_text;
+ func (stream, base_style, "%c", *c);
continue;
}
switch (*++c)
{
+ case '{':
+ ++c;
+ if (*c == '\0')
+ abort ();
+ old_base_style = base_style;
+ base_style = decode_base_style (*c);
+ ++c;
+ if (*c != ':')
+ abort ();
+ break;
+
+ case '}':
+ base_style = old_base_style;
+ break;
+
case '%':
- func (stream, "%%");
+ func (stream, base_style, "%%");
break;
case 'c':
if (ifthen_state)
- func (stream, "%s", arm_conditional[IFTHEN_COND]);
+ func (stream, dis_style_mnemonic, "%s",
+ arm_conditional[IFTHEN_COND]);
break;
case 'x':
if (ifthen_next_state)
- func (stream, "\t; unpredictable branch in IT block\n");
+ func (stream, dis_style_comment_start,
+ "\t; unpredictable branch in IT block\n");
break;
case 'X':
if (ifthen_state)
- func (stream, "\t; unpredictable <IT:%s>",
+ func (stream, dis_style_comment_start,
+ "\t; unpredictable <IT:%s>",
arm_conditional[IFTHEN_COND]);
break;
@@ -10913,7 +11456,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
imm12 |= (given & 0x000000ffu);
imm12 |= (given & 0x00007000u) >> 4;
imm12 |= (given & 0x04000000u) >> 15;
- func (stream, "#%u", imm12);
+ func (stream, dis_style_immediate, "#%u", imm12);
value_in_comment = imm12;
}
break;
@@ -10938,7 +11481,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
imm8 = (bits & 0x07f) | 0x80;
imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
}
- func (stream, "#%u", imm);
+ func (stream, dis_style_immediate, "#%u", imm);
value_in_comment = imm;
}
break;
@@ -10951,7 +11494,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
imm |= (given & 0x00007000u) >> 4;
imm |= (given & 0x04000000u) >> 15;
imm |= (given & 0x000f0000u) >> 4;
- func (stream, "#%u", imm);
+ func (stream, dis_style_immediate, "#%u", imm);
value_in_comment = imm;
}
break;
@@ -10963,7 +11506,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
imm |= (given & 0x000f0000u) >> 16;
imm |= (given & 0x00000ff0u) >> 0;
imm |= (given & 0x0000000fu) << 12;
- func (stream, "#%u", imm);
+ func (stream, dis_style_immediate, "#%u", imm);
value_in_comment = imm;
}
break;
@@ -10974,7 +11517,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
imm |= (given & 0x000f0000u) >> 4;
imm |= (given & 0x00000fffu) >> 0;
- func (stream, "#%u", imm);
+ func (stream, dis_style_immediate, "#%u", imm);
value_in_comment = imm;
}
break;
@@ -10985,7 +11528,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
imm |= (given & 0x00000fffu);
imm |= (given & 0x000f0000u) >> 4;
- func (stream, "#%u", imm);
+ func (stream, dis_style_immediate, "#%u", imm);
value_in_comment = imm;
}
break;
@@ -10998,31 +11541,46 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
imm |= (given & 0x000000c0u) >> 6;
imm |= (given & 0x00007000u) >> 10;
- func (stream, "%s", arm_regnames[reg]);
+ func (stream, dis_style_register, "%s", arm_regnames[reg]);
switch (stp)
{
case 0:
if (imm > 0)
- func (stream, ", lsl #%u", imm);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "lsl ");
+ func (stream, dis_style_immediate, "#%u", imm);
+ }
break;
case 1:
if (imm == 0)
imm = 32;
- func (stream, ", lsr #%u", imm);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "lsr ");
+ func (stream, dis_style_immediate, "#%u", imm);
break;
case 2:
if (imm == 0)
imm = 32;
- func (stream, ", asr #%u", imm);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "asr ");
+ func (stream, dis_style_immediate, "#%u", imm);
break;
case 3:
if (imm == 0)
- func (stream, ", rrx");
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "rrx");
+ }
else
- func (stream, ", ror #%u", imm);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "ror ");
+ func (stream, dis_style_immediate, "#%u", imm);
+ }
}
}
break;
@@ -11037,7 +11595,8 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
bool writeback = false, postind = false;
bfd_vma offset = 0;
- func (stream, "[%s", arm_regnames[Rn]);
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "%s", arm_regnames[Rn]);
if (U) /* 12-bit positive immediate offset. */
{
offset = i12;
@@ -11051,10 +11610,16 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
unsigned int Rm = (i8 & 0x0f);
unsigned int sh = (i8 & 0x30) >> 4;
- func (stream, ", %s", arm_regnames[Rm]);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "%s",
+ arm_regnames[Rm]);
if (sh)
- func (stream, ", lsl #%u", sh);
- func (stream, "]");
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "lsl ");
+ func (stream, dis_style_immediate, "#%u", sh);
+ }
+ func (stream, dis_style_text, "]");
break;
}
else switch (op)
@@ -11088,22 +11653,29 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
break;
default:
- func (stream, ", <undefined>]");
+ func (stream, dis_style_text, ", <undefined>]");
goto skip;
}
if (postind)
- func (stream, "], #%d", (int) offset);
+ {
+ func (stream, dis_style_text, "], ");
+ func (stream, dis_style_immediate, "#%d", (int) offset);
+ }
else
{
if (offset)
- func (stream, ", #%d", (int) offset);
- func (stream, writeback ? "]!" : "]");
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%d",
+ (int) offset);
+ }
+ func (stream, dis_style_text, writeback ? "]!" : "]");
}
if (Rn == 15)
{
- func (stream, "\t; ");
+ func (stream, dis_style_comment_start, "\t; ");
info->print_address_func (((pc + 4) & ~3) + offset, info);
}
}
@@ -11117,30 +11689,36 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
unsigned int Rn = (given & 0x000f0000) >> 16;
unsigned int off = (given & 0x000000ff);
- func (stream, "[%s", arm_regnames[Rn]);
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "%s", arm_regnames[Rn]);
if (PRE_BIT_SET)
{
if (off || !U)
{
- func (stream, ", #%c%u", U ? '+' : '-', off * 4);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%c%u",
+ U ? '+' : '-', off * 4);
value_in_comment = off * 4 * (U ? 1 : -1);
}
- func (stream, "]");
+ func (stream, dis_style_text, "]");
if (W)
- func (stream, "!");
+ func (stream, dis_style_text, "!");
}
else
{
- func (stream, "], ");
+ func (stream, dis_style_text, "], ");
if (W)
{
- func (stream, "#%c%u", U ? '+' : '-', off * 4);
+ func (stream, dis_style_immediate, "#%c%u",
+ U ? '+' : '-', off * 4);
value_in_comment = off * 4 * (U ? 1 : -1);
}
else
{
- func (stream, "{%u}", off);
+ func (stream, dis_style_text, "{");
+ func (stream, dis_style_immediate, "%u", off);
+ func (stream, dis_style_text, "}");
value_in_comment = off;
}
}
@@ -11154,14 +11732,18 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
switch (type)
{
- case 0: func (stream, Sbit ? "sb" : "b"); break;
- case 1: func (stream, Sbit ? "sh" : "h"); break;
+ case 0:
+ func (stream, dis_style_mnemonic, Sbit ? "sb" : "b");
+ break;
+ case 1:
+ func (stream, dis_style_mnemonic, Sbit ? "sh" : "h");
+ break;
case 2:
if (Sbit)
- func (stream, "??");
+ func (stream, dis_style_text, "??");
break;
case 3:
- func (stream, "??");
+ func (stream, dis_style_text, "??");
break;
}
}
@@ -11175,21 +11757,23 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
int started = 0;
int reg;
- func (stream, "{");
+ func (stream, dis_style_text, "{");
for (reg = 0; reg < 16; reg++)
if ((given & (1 << reg)) != 0)
{
if (started)
- func (stream, ", ");
+ func (stream, dis_style_text, ", ");
started = 1;
if (is_clrm && reg == 13)
- func (stream, "(invalid: %s)", arm_regnames[reg]);
+ func (stream, dis_style_text, "(invalid: %s)",
+ arm_regnames[reg]);
else if (is_clrm && reg == 15)
- func (stream, "%s", "APSR");
+ func (stream, dis_style_register, "%s", "APSR");
else
- func (stream, "%s", arm_regnames[reg]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[reg]);
}
- func (stream, "}");
+ func (stream, dis_style_text, "}");
}
break;
@@ -11200,7 +11784,9 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
lsb |= (given & 0x000000c0u) >> 6;
lsb |= (given & 0x00007000u) >> 10;
- func (stream, "#%u, #%u", lsb, msb - lsb + 1);
+ func (stream, dis_style_immediate, "#%u", lsb);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%u", msb - lsb + 1);
}
break;
@@ -11211,14 +11797,16 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
lsb |= (given & 0x000000c0u) >> 6;
lsb |= (given & 0x00007000u) >> 10;
- func (stream, "#%u, #%u", lsb, width);
+ func (stream, dis_style_immediate, "#%u", lsb);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%u", width);
}
break;
case 'G':
{
unsigned int boff = (((given & 0x07800000) >> 23) << 1);
- func (stream, "%x", boff);
+ func (stream, dis_style_immediate, "%x", boff);
}
break;
@@ -11274,8 +11862,9 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
unsigned int T = (given & 0x00020000u) >> 17;
unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
unsigned int boffset = (T == 1) ? 4 : 2;
- func (stream, ", ");
- func (stream, "%x", endoffset + boffset);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "%x",
+ endoffset + boffset);
}
break;
@@ -11364,9 +11953,17 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
shift |= (given & 0x000000c0u) >> 6;
shift |= (given & 0x00007000u) >> 10;
if (WRITEBACK_BIT_SET)
- func (stream, ", asr #%u", shift);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "asr ");
+ func (stream, dis_style_immediate, "#%u", shift);
+ }
else if (shift)
- func (stream, ", lsl #%u", shift);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "lsl ");
+ func (stream, dis_style_immediate, "#%u", shift);
+ }
/* else print nothing - lsl #0 */
}
break;
@@ -11376,7 +11973,11 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
unsigned int rot = (given & 0x00000030) >> 4;
if (rot)
- func (stream, ", ror #%u", rot * 8);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "ror ");
+ func (stream, dis_style_immediate, "#%u", rot * 8);
+ }
}
break;
@@ -11385,34 +11986,40 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
{
switch (given & 0xf)
{
- case 0xf: func (stream, "sy"); break;
- default:
- func (stream, "#%d", (int) given & 0xf);
- break;
+ case 0xf:
+ func (stream, dis_style_sub_mnemonic, "sy");
+ break;
+ default:
+ func (stream, dis_style_immediate, "#%d",
+ (int) given & 0xf);
+ break;
}
}
else
{
const char * opt = data_barrier_option (given & 0xf);
if (opt != NULL)
- func (stream, "%s", opt);
+ func (stream, dis_style_sub_mnemonic, "%s", opt);
else
- func (stream, "#%d", (int) given & 0xf);
+ func (stream, dis_style_immediate, "#%d",
+ (int) given & 0xf);
}
break;
case 'C':
if ((given & 0xff) == 0)
{
- func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
+ func (stream, dis_style_register, "%cPSR_",
+ (given & 0x100000) ? 'S' : 'C');
+
if (given & 0x800)
- func (stream, "f");
+ func (stream, dis_style_register, "f");
if (given & 0x400)
- func (stream, "s");
+ func (stream, dis_style_register, "s");
if (given & 0x200)
- func (stream, "x");
+ func (stream, dis_style_register, "x");
if (given & 0x100)
- func (stream, "c");
+ func (stream, dis_style_register, "c");
}
else if ((given & 0x20) == 0x20)
{
@@ -11424,13 +12031,15 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
name = banked_regname (sysm);
if (name != NULL)
- func (stream, "%s", name);
+ func (stream, dis_style_register, "%s", name);
else
- func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
+ func (stream, dis_style_text,
+ "(UNDEF: %lu)", (unsigned long) sysm);
}
else
{
- func (stream, "%s", psr_name (given & 0xff));
+ func (stream, dis_style_register, "%s",
+ psr_name (given & 0xff));
}
break;
@@ -11446,12 +12055,14 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
name = banked_regname (sm);
if (name != NULL)
- func (stream, "%s", name);
+ func (stream, dis_style_register, "%s", name);
else
- func (stream, "(UNDEF: %lu)", (unsigned long) sm);
+ func (stream, dis_style_text,
+ "(UNDEF: %lu)", (unsigned long) sm);
}
else
- func (stream, "%s", psr_name (given & 0xff));
+ func (stream, dis_style_register, "%s",
+ psr_name (given & 0xff));
break;
case '0': case '1': case '2': case '3': case '4':
@@ -11466,23 +12077,24 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
{
case 's':
if (val <= 3)
- func (stream, "%s", mve_vec_sizename[val]);
+ func (stream, dis_style_mnemonic, "%s",
+ mve_vec_sizename[val]);
else
- func (stream, "<undef size>");
+ func (stream, dis_style_text, "<undef size>");
break;
case 'd':
- func (stream, "%lu", val);
+ func (stream, base_style, "%lu", val);
value_in_comment = val;
break;
case 'D':
- func (stream, "%lu", val + 1);
+ func (stream, dis_style_immediate, "%lu", val + 1);
value_in_comment = val + 1;
break;
case 'W':
- func (stream, "%lu", val * 4);
+ func (stream, dis_style_immediate, "%lu", val * 4);
value_in_comment = val * 4;
break;
@@ -11495,32 +12107,35 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
is_unpredictable = true;
/* Fall through. */
case 'r':
- func (stream, "%s", arm_regnames[val]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[val]);
break;
case 'c':
- func (stream, "%s", arm_conditional[val]);
+ func (stream, base_style, "%s", arm_conditional[val]);
break;
case '\'':
c++;
if (val == ((1ul << width) - 1))
- func (stream, "%c", *c);
+ func (stream, base_style, "%c", *c);
break;
case '`':
c++;
if (val == 0)
- func (stream, "%c", *c);
+ func (stream, dis_style_immediate, "%c", *c);
break;
case '?':
- func (stream, "%c", c[(1 << width) - (int) val]);
+ func (stream, dis_style_mnemonic, "%c",
+ c[(1 << width) - (int) val]);
c += 1 << width;
break;
case 'x':
- func (stream, "0x%lx", val & 0xffffffffUL);
+ func (stream, dis_style_immediate, "0x%lx",
+ val & 0xffffffffUL);
break;
default:
@@ -11539,7 +12154,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
if ((given & (1 << 23)) == 0)
offset = - offset;
- func (stream, "\t; ");
+ func (stream, dis_style_comment_start, "\t; ");
info->print_address_func ((pc & ~3) + 4 + offset, info);
}
break;
@@ -11550,16 +12165,17 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", value_in_comment);
+ func (stream, dis_style_comment_start, "\t; 0x%lx",
+ value_in_comment);
if (is_unpredictable)
- func (stream, UNPREDICTABLE_INSTRUCTION);
+ func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
return;
}
/* No match. */
- func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
+ func (stream, dis_style_text, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
return;
}
@@ -11570,16 +12186,24 @@ print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
struct disassemble_info *info,
long given)
{
+ fprintf_styled_ftype func = info->fprintf_styled_func;
+
switch (info->bytes_per_chunk)
{
case 1:
- info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
+ func (info->stream, dis_style_assembler_directive, ".byte");
+ func (info->stream, dis_style_text, "\t");
+ func (info->stream, dis_style_immediate, "0x%02lx", given);
break;
case 2:
- info->fprintf_func (info->stream, ".short\t0x%04lx", given);
+ func (info->stream, dis_style_assembler_directive, ".short");
+ func (info->stream, dis_style_text, "\t");
+ func (info->stream, dis_style_immediate, "0x%04lx", given);
break;
case 4:
- info->fprintf_func (info->stream, ".word\t0x%08lx", given);
+ func (info->stream, dis_style_assembler_directive, ".word");
+ func (info->stream, dis_style_text, "\t");
+ func (info->stream, dis_style_immediate, "0x%08lx", given);
break;
default:
abort ();
--
2.25.4
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] opcodes/arm: add missing ';' characters
2022-09-16 13:21 ` [PATCH 1/2] opcodes/arm: add missing ';' characters Andrew Burgess
@ 2022-09-20 15:13 ` Richard Earnshaw
2022-09-22 9:08 ` Andrew Burgess
0 siblings, 1 reply; 15+ messages in thread
From: Richard Earnshaw @ 2022-09-20 15:13 UTC (permalink / raw)
To: Andrew Burgess, binutils
On 16/09/2022 14:21, Andrew Burgess via Binutils wrote:
> I spotted a couple of places where the ARM disassembler produces what
> seems to be some comment style text '@ Impl Def' without including a
> comment character ';'. In other places where we have similar messages
> a comment character is emitted, so I suspect this was just an
> oversight.
>
> Fixed in this commit by adding two new comment characters, and
> updating the expected test results.
No, this is incorrect. @ is the comment marker on Arm; ';' is the
statement separator.
R.
> ---
> gas/testsuite/gas/arm/armv8.1-m.main-fp.d | 8 ++++----
> gas/testsuite/gas/arm/vfp1xD.d | 16 ++++++++--------
> gas/testsuite/gas/arm/vfp1xD_t2.d | 8 ++++----
> opcodes/arm-dis.c | 8 ++++----
> 4 files changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/gas/testsuite/gas/arm/armv8.1-m.main-fp.d b/gas/testsuite/gas/arm/armv8.1-m.main-fp.d
> index dd69e0d5252..e8d57ab5fd1 100644
> --- a/gas/testsuite/gas/arm/armv8.1-m.main-fp.d
> +++ b/gas/testsuite/gas/arm/armv8.1-m.main-fp.d
> @@ -252,13 +252,13 @@ Disassembly of section .text:
> 0+3b2 <[^>]*> bf04 itt eq
> 0+3b4 <[^>]*> ee01 9a90 (vmoveq|fmsreq) s3, r9
> 0+3b8 <[^>]*> eee0 8a10 (vmsreq|fmxreq) fpsid, r8
> -0+3bc <[^>]*> eef9 0a10 (vmrs|fmrx) r0, fpinst @ Impl def
> -0+3c0 <[^>]*> eefa 0a10 (vmrs|fmrx) r0, fpinst2 @ Impl def
> +0+3bc <[^>]*> eef9 0a10 (vmrs|fmrx) r0, fpinst ;@ Impl def
> +0+3c0 <[^>]*> eefa 0a10 (vmrs|fmrx) r0, fpinst2 ;@ Impl def
> 0+3c4 <[^>]*> eef7 0a10 (vmrs|fmrx) r0, mvfr0
> 0+3c8 <[^>]*> eef6 0a10 (vmrs|fmrx) r0, mvfr1
> 0+3cc <[^>]*> eefc 0a10 (vmrs|fmrx) r0, (<impl def 0xc>|vpr)
> -0+3d0 <[^>]*> eee9 0a10 (vmsr|fmxr) fpinst, r0 @ Impl def
> -0+3d4 <[^>]*> eeea 0a10 (vmsr|fmxr) fpinst2, r0 @ Impl def
> +0+3d0 <[^>]*> eee9 0a10 (vmsr|fmxr) fpinst, r0 ;@ Impl def
> +0+3d4 <[^>]*> eeea 0a10 (vmsr|fmxr) fpinst2, r0 ;@ Impl def
> 0+3d8 <[^>]*> eee7 0a10 (vmsr|fmxr) mvfr0, r0
> 0+3dc <[^>]*> eee6 0a10 (vmsr|fmxr) mvfr1, r0
> 0+3e0 <[^>]*> eeec 0a10 (vmsr|fmxr) (<impl def 0xc>|vpr), r0
> diff --git a/gas/testsuite/gas/arm/vfp1xD.d b/gas/testsuite/gas/arm/vfp1xD.d
> index 079f7a17e59..2c33e14edc7 100644
> --- a/gas/testsuite/gas/arm/vfp1xD.d
> +++ b/gas/testsuite/gas/arm/vfp1xD.d
> @@ -239,13 +239,13 @@ Disassembly of section .text:
> 0+394 <[^>]*> 0ef09a10 (vmrseq|fmrxeq) r9, fpsid
> 0+398 <[^>]*> 0e019a90 (vmoveq|fmsreq) s3, r9
> 0+39c <[^>]*> 0ee08a10 (vmsreq|fmxreq) fpsid, r8
> -0+3a0 <[^>]*> eef90a10 (vmrs|fmrx) r0, fpinst @ Impl def
> -0+3a4 <[^>]*> eefa0a10 (vmrs|fmrx) r0, fpinst2 @ Impl def
> +0+3a0 <[^>]*> eef90a10 (vmrs|fmrx) r0, fpinst ;@ Impl def
> +0+3a4 <[^>]*> eefa0a10 (vmrs|fmrx) r0, fpinst2 ;@ Impl def
> 0+3a8 <[^>]*> eef70a10 (vmrs|fmrx) r0, mvfr0
> 0+3ac <[^>]*> eef60a10 (vmrs|fmrx) r0, mvfr1
> 0+3b0 <[^>]*> eefc0a10 (vmrs|fmrx) r0, (vpr|<impl def 0xc>)
> -0+3b4 <[^>]*> eee90a10 (vmsr|fmxr) fpinst, r0 @ Impl def
> -0+3b8 <[^>]*> eeea0a10 (vmsr|fmxr) fpinst2, r0 @ Impl def
> +0+3b4 <[^>]*> eee90a10 (vmsr|fmxr) fpinst, r0 ;@ Impl def
> +0+3b8 <[^>]*> eeea0a10 (vmsr|fmxr) fpinst2, r0 ;@ Impl def
> 0+3bc <[^>]*> eee70a10 (vmsr|fmxr) mvfr0, r0
> 0+3c0 <[^>]*> eee60a10 (vmsr|fmxr) mvfr1, r0
> 0+3c4 <[^>]*> eeec0a10 (vmsr|fmxr) (vpr|<impl def 0xc>), r0
> @@ -280,15 +280,15 @@ Disassembly of section .text:
> 0+438 <[^>]*> eee1ea10 vmsr fpscr, lr
> 0+43c <[^>]*> eee01a10 vmsr fpsid, r1
> 0+440 <[^>]*> eee82a10 vmsr fpexc, r2
> -0+444 <[^>]*> eee93a10 vmsr fpinst, r3 @ Impl def
> -0+448 <[^>]*> eeea4a10 vmsr fpinst2, r4 @ Impl def
> +0+444 <[^>]*> eee93a10 vmsr fpinst, r3 ;@ Impl def
> +0+448 <[^>]*> eeea4a10 vmsr fpinst2, r4 ;@ Impl def
> 0+44c <[^>]*> eeef5a10 vmsr (c15|<impl def 0xf>|fpcxt_s), r5
> 0+450 <[^>]*> eef03a10 vmrs r3, fpsid
> 0+454 <[^>]*> eef64a10 vmrs r4, mvfr1
> 0+458 <[^>]*> eef75a10 vmrs r5, mvfr0
> 0+45c <[^>]*> eef86a10 vmrs r6, fpexc
> -0+460 <[^>]*> eef97a10 vmrs r7, fpinst @ Impl def
> -0+464 <[^>]*> eefa8a10 vmrs r8, fpinst2 @ Impl def
> +0+460 <[^>]*> eef97a10 vmrs r7, fpinst ;@ Impl def
> +0+464 <[^>]*> eefa8a10 vmrs r8, fpinst2 ;@ Impl def
> 0+468 <[^>]*> eeff9a10 vmrs r9, (c15|<impl def 0xf>|fpcxt_s)
> 0+46c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
> 0+470 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
> diff --git a/gas/testsuite/gas/arm/vfp1xD_t2.d b/gas/testsuite/gas/arm/vfp1xD_t2.d
> index 248185d4486..634fbb00518 100644
> --- a/gas/testsuite/gas/arm/vfp1xD_t2.d
> +++ b/gas/testsuite/gas/arm/vfp1xD_t2.d
> @@ -253,13 +253,13 @@ Disassembly of section .text:
> 0+3b2 <[^>]*> bf04 itt eq
> 0+3b4 <[^>]*> ee01 9a90 (vmoveq|fmsreq) s3, r9
> 0+3b8 <[^>]*> eee0 8a10 (vmsreq|fmxreq) fpsid, r8
> -0+3bc <[^>]*> eef9 0a10 (vmrs|fmrx) r0, fpinst @ Impl def
> -0+3c0 <[^>]*> eefa 0a10 (vmrs|fmrx) r0, fpinst2 @ Impl def
> +0+3bc <[^>]*> eef9 0a10 (vmrs|fmrx) r0, fpinst ;@ Impl def
> +0+3c0 <[^>]*> eefa 0a10 (vmrs|fmrx) r0, fpinst2 ;@ Impl def
> 0+3c4 <[^>]*> eef7 0a10 (vmrs|fmrx) r0, mvfr0
> 0+3c8 <[^>]*> eef6 0a10 (vmrs|fmrx) r0, mvfr1
> 0+3cc <[^>]*> eefc 0a10 (vmrs|fmrx) r0, (<impl def 0xc>|vpr)
> -0+3d0 <[^>]*> eee9 0a10 (vmsr|fmxr) fpinst, r0 @ Impl def
> -0+3d4 <[^>]*> eeea 0a10 (vmsr|fmxr) fpinst2, r0 @ Impl def
> +0+3d0 <[^>]*> eee9 0a10 (vmsr|fmxr) fpinst, r0 ;@ Impl def
> +0+3d4 <[^>]*> eeea 0a10 (vmsr|fmxr) fpinst2, r0 ;@ Impl def
> 0+3d8 <[^>]*> eee7 0a10 (vmsr|fmxr) mvfr0, r0
> 0+3dc <[^>]*> eee6 0a10 (vmsr|fmxr) mvfr1, r0
> 0+3e0 <[^>]*> eeec 0a10 (vmsr|fmxr) (<impl def 0xc>|vpr), r0
> diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
> index 684c74f7f20..5de78cec33d 100644
> --- a/opcodes/arm-dis.c
> +++ b/opcodes/arm-dis.c
> @@ -897,9 +897,9 @@ static const struct sopcode32 coprocessor_opcodes[] =
> {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
> 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
> {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
> - 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
> + 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t;@ Impl def"},
> {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
> - 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
> + 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t;@ Impl def"},
> {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
> 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
> {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
> @@ -925,9 +925,9 @@ static const struct sopcode32 coprocessor_opcodes[] =
> {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
> 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
> {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
> - 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
> + 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t;@ Impl def"},
> {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
> - 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
> + 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t;@ Impl def"},
> {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
> 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
> {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] opcodes/arm: add missing ';' characters
2022-09-20 15:13 ` Richard Earnshaw
@ 2022-09-22 9:08 ` Andrew Burgess
2022-09-22 12:39 ` Richard Earnshaw
0 siblings, 1 reply; 15+ messages in thread
From: Andrew Burgess @ 2022-09-22 9:08 UTC (permalink / raw)
To: Richard Earnshaw, binutils
Richard Earnshaw <Richard.Earnshaw@foss.arm.com> writes:
> On 16/09/2022 14:21, Andrew Burgess via Binutils wrote:
>> I spotted a couple of places where the ARM disassembler produces what
>> seems to be some comment style text '@ Impl Def' without including a
>> comment character ';'. In other places where we have similar messages
>> a comment character is emitted, so I suspect this was just an
>> oversight.
>>
>> Fixed in this commit by adding two new comment characters, and
>> updating the expected test results.
>
> No, this is incorrect. @ is the comment marker on Arm; ';' is the
> statement separator.
>
Wow! OK. So, I tested what you said, and you'd absolutely correct.
But does that mean all the places where the disassembler prints what (I
believe) is clearly a comment without printing '@' is actually a bug?
Or am I missing something really subtle here?
Here are just a few of the many examples that can be found in the gas
testsuite for ARM:
sub r0, r0, #32, 24 ; 0x2000
add r0, r0, #32, 24 ; 0x2000
nop ; (mov r0, r0)
subhi pc, pc, #805306368 ; 0x30000000
ldrh r3, [pc, #-8] ; 8 <foo>
ldrsb r2, [r3, #255] ; 0xff
ldrsh r1, [r4, #-250] ; 0xffffff06
ldrsb r1, [r5, #240] ; 0xf0
strh r2, [pc, #48] ; 68 <bar>
There are many more, but they are all pretty similar in content.
Should I instead propose changing all these to use '@' ?
Thanks,
Andrew
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] opcodes/arm: add missing ';' characters
2022-09-22 9:08 ` Andrew Burgess
@ 2022-09-22 12:39 ` Richard Earnshaw
2022-09-22 18:20 ` Andrew Burgess
0 siblings, 1 reply; 15+ messages in thread
From: Richard Earnshaw @ 2022-09-22 12:39 UTC (permalink / raw)
To: Andrew Burgess, binutils
On 22/09/2022 10:08, Andrew Burgess wrote:
> Richard Earnshaw <Richard.Earnshaw@foss.arm.com> writes:
>
>> On 16/09/2022 14:21, Andrew Burgess via Binutils wrote:
>>> I spotted a couple of places where the ARM disassembler produces what
>>> seems to be some comment style text '@ Impl Def' without including a
>>> comment character ';'. In other places where we have similar messages
>>> a comment character is emitted, so I suspect this was just an
>>> oversight.
>>>
>>> Fixed in this commit by adding two new comment characters, and
>>> updating the expected test results.
>>
>> No, this is incorrect. @ is the comment marker on Arm; ';' is the
>> statement separator.
>>
>
> Wow! OK. So, I tested what you said, and you'd absolutely correct.
> But does that mean all the places where the disassembler prints what (I
> believe) is clearly a comment without printing '@' is actually a bug?
> Or am I missing something really subtle here?
>
> Here are just a few of the many examples that can be found in the gas
> testsuite for ARM:
>
> sub r0, r0, #32, 24 ; 0x2000
> add r0, r0, #32, 24 ; 0x2000
> nop ; (mov r0, r0)
> subhi pc, pc, #805306368 ; 0x30000000
> ldrh r3, [pc, #-8] ; 8 <foo>
> ldrsb r2, [r3, #255] ; 0xff
> ldrsh r1, [r4, #-250] ; 0xffffff06
> ldrsb r1, [r5, #240] ; 0xf0
> strh r2, [pc, #48] ; 68 <bar>
>
> There are many more, but they are all pretty similar in content.
>
> Should I instead propose changing all these to use '@' ?
>
> Thanks,
> Andrew
>
Technically, yes. But I don't think we've ever claimed that you could
paste the output of the disassembler into an assembler and directly use
the result. So while this would be good to fix, I don't think it's a
disaster.
R.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] opcodes/arm: add missing ';' characters
2022-09-22 12:39 ` Richard Earnshaw
@ 2022-09-22 18:20 ` Andrew Burgess
0 siblings, 0 replies; 15+ messages in thread
From: Andrew Burgess @ 2022-09-22 18:20 UTC (permalink / raw)
To: Richard Earnshaw, binutils
Richard Earnshaw <Richard.Earnshaw@foss.arm.com> writes:
> On 22/09/2022 10:08, Andrew Burgess wrote:
>> Richard Earnshaw <Richard.Earnshaw@foss.arm.com> writes:
>>
>>> On 16/09/2022 14:21, Andrew Burgess via Binutils wrote:
>>>> I spotted a couple of places where the ARM disassembler produces what
>>>> seems to be some comment style text '@ Impl Def' without including a
>>>> comment character ';'. In other places where we have similar messages
>>>> a comment character is emitted, so I suspect this was just an
>>>> oversight.
>>>>
>>>> Fixed in this commit by adding two new comment characters, and
>>>> updating the expected test results.
>>>
>>> No, this is incorrect. @ is the comment marker on Arm; ';' is the
>>> statement separator.
>>>
>>
>> Wow! OK. So, I tested what you said, and you'd absolutely correct.
>> But does that mean all the places where the disassembler prints what (I
>> believe) is clearly a comment without printing '@' is actually a bug?
>> Or am I missing something really subtle here?
>>
>> Here are just a few of the many examples that can be found in the gas
>> testsuite for ARM:
>>
>> sub r0, r0, #32, 24 ; 0x2000
>> add r0, r0, #32, 24 ; 0x2000
>> nop ; (mov r0, r0)
>> subhi pc, pc, #805306368 ; 0x30000000
>> ldrh r3, [pc, #-8] ; 8 <foo>
>> ldrsb r2, [r3, #255] ; 0xff
>> ldrsh r1, [r4, #-250] ; 0xffffff06
>> ldrsb r1, [r5, #240] ; 0xf0
>> strh r2, [pc, #48] ; 68 <bar>
>>
>> There are many more, but they are all pretty similar in content.
>>
>> Should I instead propose changing all these to use '@' ?
>>
>> Thanks,
>> Andrew
>>
>
> Technically, yes. But I don't think we've ever claimed that you could
> paste the output of the disassembler into an assembler and directly use
> the result. So while this would be good to fix, I don't think it's a
> disaster.
Except I would like to style the disassembler output. Right now, based
on what I was seeing, I've handled ';' as the start of a comment. Which
is probably wrong.
I could continue to treat ';' (in addition to '@') as a comment marker
in disassembler output, which would proably give the best looking output.
Or I can fix the disassembler to use '@' consistently? Which is probably
the best all round solution. It sounds like you wouldn't object to this?
Or I could treat ';' as a statement separator and style whatever's after
it as... whatever it would be, immediate, text, label, etc? Which I
think will give the most confusing output.
Would value your thoughts,
Thanks,
Andrew
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCHv2 0/2] Disassembler styling for ARM
2022-09-16 13:21 [PATCH 0/2] Disassembler styling for ARM Andrew Burgess
2022-09-16 13:21 ` [PATCH 1/2] opcodes/arm: add missing ';' characters Andrew Burgess
2022-09-16 13:21 ` [PATCH 2/2] opcodes/arm: add disassembler styling for arm Andrew Burgess
@ 2022-10-02 10:47 ` Andrew Burgess
2022-10-02 10:47 ` [PATCHv2 1/2] opcodes/arm: use '@' consistently for the comment character Andrew Burgess
` (2 more replies)
2 siblings, 3 replies; 15+ messages in thread
From: Andrew Burgess @ 2022-10-02 10:47 UTC (permalink / raw)
To: binutils; +Cc: Andrew Burgess
This series adds disassembler styling for ARM.
Changes since v1:
- Patch #1 is now much bigger! The ARM disassembler now uses '@'
consistently for its comment character. This is a minor change in
the disassembler, but a huge change in the expected test results.
I believe I've fixed all the tests; I'm not seeing any failures,
but as always, I suspect I will have missed something. I
apologies in advance, and hopefully, it should be pretty easy to
update any tests I've missed.
- Patch #2 is largely unchanged. The only difference is that we now
look for '@' to indicate the start of a comment instead of ';'.
All feedback welcome.
Thanks,
Andrew
---
Andrew Burgess (2):
opcodes/arm: use '@' consistently for the comment character
opcodes/arm: add disassembler styling for arm
.../testsuite/binutils-all/arm/objdump.exp | 4 +-
gas/testsuite/gas/arm/adr.d | 2 +-
gas/testsuite/gas/arm/adrl.d | 20 +-
gas/testsuite/gas/arm/arch4t-eabi.d | 8 +-
gas/testsuite/gas/arm/arch4t.d | 8 +-
gas/testsuite/gas/arm/arch7.d | 4 +-
gas/testsuite/gas/arm/arch7a-mp.d | 6 +-
gas/testsuite/gas/arm/arch7r-mp.d | 6 +-
gas/testsuite/gas/arm/archv6t2.d | 10 +-
gas/testsuite/gas/arm/archv8m-base.d | 12 +-
gas/testsuite/gas/arm/archv8m-main-dsp-1.d | 12 +-
gas/testsuite/gas/arm/archv8m-main.d | 12 +-
gas/testsuite/gas/arm/arm3.d | 2 +-
gas/testsuite/gas/arm/arm6.d | 4 +-
gas/testsuite/gas/arm/arm7dm.d | 6 +-
gas/testsuite/gas/arm/arm7t.d | 26 +-
gas/testsuite/gas/arm/armv1.d | 8 +-
gas/testsuite/gas/arm/armv7-a+virt.d | 4 +-
.../gas/arm/armv8-2-fp16-scalar-ext.d | 8 +-
.../gas/arm/armv8-2-fp16-scalar-thumb-ext.d | 8 +-
.../gas/arm/armv8-2-fp16-scalar-thumb.d | 8 +-
gas/testsuite/gas/arm/armv8-2-fp16-scalar.d | 8 +-
gas/testsuite/gas/arm/armv8.1-m.main-fp.d | 70 +-
gas/testsuite/gas/arm/armv8.1-m.main-hp.d | 8 +-
gas/testsuite/gas/arm/bl-local-2.d | 10 +-
gas/testsuite/gas/arm/bl-local-v4t.d | 10 +-
gas/testsuite/gas/arm/blx-bad.d | 14 +-
gas/testsuite/gas/arm/blx-local-thumb.d | 10 +-
gas/testsuite/gas/arm/blx-local.d | 12 +-
gas/testsuite/gas/arm/branch-reloc.d | 10 +-
gas/testsuite/gas/arm/ccs.d | 2 +-
.../gas/arm/copro-arm_v2plus-arm_v2.d | 8 +-
.../gas/arm/copro-arm_v5plus-arm_v5.d | 4 +-
.../arm/copro-thumb_v6t2plus-thumb_v6t2-1.d | 4 +-
.../arm/copro-thumb_v6t2plus-thumb_v6t2-2.d | 4 +-
gas/testsuite/gas/arm/crc32-armv8-a-bad.d | 24 +-
gas/testsuite/gas/arm/crc32-armv8-r-bad.d | 24 +-
gas/testsuite/gas/arm/dis-data3.d | 2 +-
gas/testsuite/gas/arm/el_segundo.d | 2 +-
gas/testsuite/gas/arm/float.d | 2 +-
gas/testsuite/gas/arm/group-reloc-alu.d | 160 +-
gas/testsuite/gas/arm/group-reloc-ldrs.d | 240 +-
gas/testsuite/gas/arm/immed.d | 10 +-
gas/testsuite/gas/arm/immed2.d | 2 +-
gas/testsuite/gas/arm/inst.d | 36 +-
gas/testsuite/gas/arm/iwmmxt.d | 2 +-
gas/testsuite/gas/arm/ldconst.d | 42 +-
gas/testsuite/gas/arm/ldr-global.d | 14 +-
gas/testsuite/gas/arm/ldr-t.d | 16 +-
gas/testsuite/gas/arm/ldr.d | 10 +-
gas/testsuite/gas/arm/ldst-offset0.d | 6 +-
gas/testsuite/gas/arm/ldst-pc.d | 8 +-
gas/testsuite/gas/arm/m0-load-pseudo.d | 4 +-
gas/testsuite/gas/arm/m23-load-pseudo.d | 4 +-
gas/testsuite/gas/arm/m33-load-pseudo.d | 4 +-
gas/testsuite/gas/arm/macro1.d | 6 +-
gas/testsuite/gas/arm/mapdir.d | 4 +-
gas/testsuite/gas/arm/mapmisc.d | 38 +-
gas/testsuite/gas/arm/mapsecs.d | 10 +-
gas/testsuite/gas/arm/mapshort-eabi.d | 10 +-
gas/testsuite/gas/arm/mapshort-elf.d | 10 +-
gas/testsuite/gas/arm/mask_1-armv8-a.d | 32 +-
gas/testsuite/gas/arm/mask_1-armv8-r.d | 32 +-
gas/testsuite/gas/arm/mrs-msr-arm-v6.d | 6 +-
gas/testsuite/gas/arm/mrs-msr-arm-v7-a.d | 6 +-
gas/testsuite/gas/arm/msr-imm.d | 268 +-
gas/testsuite/gas/arm/mve-vand.d | 94 +-
gas/testsuite/gas/arm/mve-vbic.d | 20 +-
gas/testsuite/gas/arm/mve-vcvt-3.d | 80 +-
gas/testsuite/gas/arm/mve-vmov-1.d | 20 +-
gas/testsuite/gas/arm/mve-vmov-2.d | 34 +-
.../gas/arm/mve-vmov-vmvn-vorr-vbic.d | 64 +-
gas/testsuite/gas/arm/mve-vmvn.d | 114 +-
gas/testsuite/gas/arm/mve-vorn.d | 22 +-
gas/testsuite/gas/arm/mve-vorr.d | 20 +-
gas/testsuite/gas/arm/neon-cond-bad_t2.d | 4 +-
gas/testsuite/gas/arm/neon-const.d | 516 ++--
gas/testsuite/gas/arm/neon-cov.d | 564 ++--
gas/testsuite/gas/arm/neon-ldst-rm.d | 4 +-
gas/testsuite/gas/arm/neon-logic.d | 8 +-
gas/testsuite/gas/arm/nops.d | 2 +-
gas/testsuite/gas/arm/offset-1.d | 8 +-
gas/testsuite/gas/arm/offset.d | 8 +-
gas/testsuite/gas/arm/pr21458.d | 14 +-
gas/testsuite/gas/arm/pr24907.d | 6 +-
gas/testsuite/gas/arm/pr25235.d | 14 +-
gas/testsuite/gas/arm/push-pop.d | 8 +-
gas/testsuite/gas/arm/reg-alias.d | 6 +-
gas/testsuite/gas/arm/relax_branch_align.d | 8 +-
gas/testsuite/gas/arm/relax_load_align.d | 6 +-
gas/testsuite/gas/arm/sp-pc-usage-t.d | 8 +-
gas/testsuite/gas/arm/tcompat.d | 6 +-
gas/testsuite/gas/arm/tcompat2.d | 8 +-
gas/testsuite/gas/arm/thumb-eabi.d | 42 +-
gas/testsuite/gas/arm/thumb-nop.d | 4 +-
gas/testsuite/gas/arm/thumb.d | 42 +-
gas/testsuite/gas/arm/thumb1_unified.d | 4 +-
gas/testsuite/gas/arm/thumb2_add.d | 38 +-
gas/testsuite/gas/arm/thumb2_invert.d | 24 +-
gas/testsuite/gas/arm/thumb2_pool.d | 32 +-
gas/testsuite/gas/arm/thumb2_relax.d | 52 +-
gas/testsuite/gas/arm/thumb2_vpool.d | 158 +-
gas/testsuite/gas/arm/thumb2_vpool_be.d | 158 +-
gas/testsuite/gas/arm/thumb32.d | 186 +-
gas/testsuite/gas/arm/thumbv6.d | 8 +-
gas/testsuite/gas/arm/thumbv6k.d | 8 +-
gas/testsuite/gas/arm/tls.d | 14 +-
gas/testsuite/gas/arm/tls_vxworks.d | 6 +-
gas/testsuite/gas/arm/udf.d | 24 +-
gas/testsuite/gas/arm/unpredictable.d | 2 +-
gas/testsuite/gas/arm/vfp-mov-enc.d | 18 +-
gas/testsuite/gas/arm/vfp-neon-overlap.d | 8 +-
gas/testsuite/gas/arm/vfp1.d | 6 +-
gas/testsuite/gas/arm/vfp1xD.d | 76 +-
gas/testsuite/gas/arm/vfp1xD_t2.d | 70 +-
gas/testsuite/gas/arm/vfpv3-32drs.d | 6 +-
gas/testsuite/gas/arm/vldconst.d | 246 +-
gas/testsuite/gas/arm/vldconst_be.d | 246 +-
gas/testsuite/gas/arm/vldr.d | 4 +-
gas/testsuite/gas/arm/wince.d | 12 +-
gas/testsuite/gas/arm/wince_inst.d | 36 +-
gas/testsuite/gas/arm/xscale.d | 4 +-
ld/testsuite/ld-arm/arm-app-abs32.d | 8 +-
ld/testsuite/ld-arm/arm-app.d | 6 +-
ld/testsuite/ld-arm/arm-be8.d | 2 +-
ld/testsuite/ld-arm/arm-call.d | 8 +-
ld/testsuite/ld-arm/arm-lib-plt32.d | 6 +-
ld/testsuite/ld-arm/arm-lib.d | 6 +-
ld/testsuite/ld-arm/arm-movwt.d | 40 +-
ld/testsuite/ld-arm/arm-pic-veneer.d | 4 +-
ld/testsuite/ld-arm/armthumb-lib.d | 16 +-
ld/testsuite/ld-arm/attr-merge-wchar-24.d | 2 +-
ld/testsuite/ld-arm/attr-merge-wchar-42.d | 2 +-
ld/testsuite/ld-arm/callweak.d | 2 +-
ld/testsuite/ld-arm/cortex-a8-far.d | 6 +-
ld/testsuite/ld-arm/cortex-a8-fix-b-plt.d | 8 +-
ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.d | 8 +-
ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.d | 8 +-
.../ld-arm/cortex-a8-fix-bl-rel-plt.d | 8 +-
ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.d | 8 +-
.../ld-arm/farcall-arm-arm-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-arm-arm.d | 2 +-
ld/testsuite/ld-arm/farcall-arm-nacl-pic.d | 4 +-
ld/testsuite/ld-arm/farcall-arm-nacl.d | 4 +-
.../ld-arm/farcall-arm-thumb-blx-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-arm-thumb-blx.d | 2 +-
.../ld-arm/farcall-arm-thumb-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-arm-thumb.d | 2 +-
ld/testsuite/ld-arm/farcall-data-nacl.d | 4 +-
ld/testsuite/ld-arm/farcall-data.d | 2 +-
ld/testsuite/ld-arm/farcall-group-limit.d | 2 +-
ld/testsuite/ld-arm/farcall-group-size2.d | 10 +-
ld/testsuite/ld-arm/farcall-group.d | 10 +-
ld/testsuite/ld-arm/farcall-mix.d | 10 +-
ld/testsuite/ld-arm/farcall-mix2.d | 10 +-
ld/testsuite/ld-arm/farcall-mixed-app-v5.d | 26 +-
ld/testsuite/ld-arm/farcall-mixed-app.d | 26 +-
ld/testsuite/ld-arm/farcall-mixed-app2.d | 28 +-
ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d | 36 +-
ld/testsuite/ld-arm/farcall-mixed-lib.d | 24 +-
.../ld-arm/farcall-thumb-arm-blx-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb-arm-blx.d | 2 +-
.../ld-arm/farcall-thumb-arm-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb-arm.d | 2 +-
.../farcall-thumb-thumb-blx-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d | 2 +-
.../ld-arm/farcall-thumb-thumb-m-no-profile.d | 2 +-
.../ld-arm/farcall-thumb-thumb-m-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb-thumb-m.d | 2 +-
.../ld-arm/farcall-thumb-thumb-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb-thumb.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb2-purecode.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb2-thumb2-m.d | 2 +-
ld/testsuite/ld-arm/fdpic-main-m.d | 16 +-
ld/testsuite/ld-arm/fdpic-main.d | 16 +-
ld/testsuite/ld-arm/fdpic-shared-m.d | 4 +-
ld/testsuite/ld-arm/fdpic-shared.d | 4 +-
ld/testsuite/ld-arm/fix-arm1176-off.d | 2 +-
ld/testsuite/ld-arm/fix-arm1176-on.d | 2 +-
ld/testsuite/ld-arm/gc-hidden-1.d | 2 +-
ld/testsuite/ld-arm/group-relocs.d | 58 +-
ld/testsuite/ld-arm/ifunc-1.dd | 50 +-
ld/testsuite/ld-arm/ifunc-10.dd | 236 +-
ld/testsuite/ld-arm/ifunc-11.dd | 28 +-
ld/testsuite/ld-arm/ifunc-12.dd | 28 +-
ld/testsuite/ld-arm/ifunc-13.dd | 28 +-
ld/testsuite/ld-arm/ifunc-14.dd | 42 +-
ld/testsuite/ld-arm/ifunc-15.dd | 42 +-
ld/testsuite/ld-arm/ifunc-16.dd | 36 +-
ld/testsuite/ld-arm/ifunc-17.dd | 2 +-
ld/testsuite/ld-arm/ifunc-2.dd | 146 +-
ld/testsuite/ld-arm/ifunc-3.dd | 40 +-
ld/testsuite/ld-arm/ifunc-4.dd | 236 +-
ld/testsuite/ld-arm/ifunc-5.dd | 26 +-
ld/testsuite/ld-arm/ifunc-6.dd | 38 +-
ld/testsuite/ld-arm/ifunc-7.dd | 18 +-
ld/testsuite/ld-arm/ifunc-8.dd | 118 +-
ld/testsuite/ld-arm/ifunc-9.dd | 56 +-
.../jump-reloc-veneers-cond-long-backward.d | 2 +-
.../ld-arm/jump-reloc-veneers-cond-long.d | 2 +-
ld/testsuite/ld-arm/jump-reloc-veneers-long.d | 2 +-
ld/testsuite/ld-arm/long-plt-format.d | 4 +-
ld/testsuite/ld-arm/mixed-app-v5.d | 26 +-
ld/testsuite/ld-arm/mixed-app.d | 26 +-
ld/testsuite/ld-arm/mixed-lib.d | 12 +-
ld/testsuite/ld-arm/movw-merge.d | 4 +-
ld/testsuite/ld-arm/non-contiguous-arm2.d | 10 +-
ld/testsuite/ld-arm/non-contiguous-arm3.d | 12 +-
ld/testsuite/ld-arm/non-contiguous-arm5.d | 10 +-
ld/testsuite/ld-arm/non-contiguous-arm6.d | 12 +-
.../ld-arm/stm32l4xx-cannot-fix-far-ldm.d | 2 +-
ld/testsuite/ld-arm/stm32l4xx-fix-ldm.d | 8 +-
ld/testsuite/ld-arm/stm32l4xx-fix-vldm-dp.d | 2 +-
ld/testsuite/ld-arm/stm32l4xx-fix-vldm.d | 2 +-
ld/testsuite/ld-arm/thumb-plt.d | 4 +-
ld/testsuite/ld-arm/thumb1-adds.d | 12 +-
ld/testsuite/ld-arm/thumb1-movs.d | 10 +-
ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.d | 2 +-
ld/testsuite/ld-arm/thumb2-bl-bad.d | 2 +-
ld/testsuite/ld-arm/tls-app.d | 4 +-
ld/testsuite/ld-arm/tls-descrelax-be32.d | 112 +-
ld/testsuite/ld-arm/tls-descrelax-be8.d | 78 +-
ld/testsuite/ld-arm/tls-descrelax-v7.d | 78 +-
ld/testsuite/ld-arm/tls-descrelax.d | 112 +-
ld/testsuite/ld-arm/tls-descseq.d | 20 +-
ld/testsuite/ld-arm/tls-gdesc-neg.d | 14 +-
ld/testsuite/ld-arm/tls-gdesc.d | 22 +-
ld/testsuite/ld-arm/tls-gdierelax.d | 8 +-
ld/testsuite/ld-arm/tls-gdierelax2.d | 10 +-
ld/testsuite/ld-arm/tls-gdlerelax.d | 4 +-
ld/testsuite/ld-arm/tls-lib-loc.d | 14 +-
ld/testsuite/ld-arm/tls-lib.d | 4 +-
ld/testsuite/ld-arm/tls-longplt-lib.d | 28 +-
ld/testsuite/ld-arm/tls-longplt.d | 30 +-
ld/testsuite/ld-arm/tls-thumb1.d | 36 +-
ld/testsuite/ld-arm/vxworks1-lib.dd | 12 +-
ld/testsuite/ld-arm/vxworks1.dd | 10 +-
opcodes/arm-dis.c | 2660 ++++++++++-------
238 files changed, 5146 insertions(+), 4518 deletions(-)
--
2.25.4
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCHv2 1/2] opcodes/arm: use '@' consistently for the comment character
2022-10-02 10:47 ` [PATCHv2 0/2] Disassembler styling for ARM Andrew Burgess
@ 2022-10-02 10:47 ` Andrew Burgess
2022-10-03 16:37 ` Andrew Burgess
2022-10-02 10:47 ` [PATCHv2 2/2] opcodes/arm: add disassembler styling for arm Andrew Burgess
2022-10-19 10:10 ` [PATCHv2 0/2] Disassembler styling for ARM Andrew Burgess
2 siblings, 1 reply; 15+ messages in thread
From: Andrew Burgess @ 2022-10-02 10:47 UTC (permalink / raw)
To: binutils; +Cc: Andrew Burgess
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then started a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is event harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated after this change.
---
gas/testsuite/gas/arm/adr.d | 2 +-
gas/testsuite/gas/arm/adrl.d | 20 +-
gas/testsuite/gas/arm/arch4t-eabi.d | 8 +-
gas/testsuite/gas/arm/arch4t.d | 8 +-
gas/testsuite/gas/arm/arch7.d | 4 +-
gas/testsuite/gas/arm/arch7a-mp.d | 6 +-
gas/testsuite/gas/arm/arch7r-mp.d | 6 +-
gas/testsuite/gas/arm/archv6t2.d | 10 +-
gas/testsuite/gas/arm/archv8m-base.d | 12 +-
gas/testsuite/gas/arm/archv8m-main-dsp-1.d | 12 +-
gas/testsuite/gas/arm/archv8m-main.d | 12 +-
gas/testsuite/gas/arm/arm3.d | 2 +-
gas/testsuite/gas/arm/arm6.d | 4 +-
gas/testsuite/gas/arm/arm7dm.d | 6 +-
gas/testsuite/gas/arm/arm7t.d | 26 +-
gas/testsuite/gas/arm/armv1.d | 8 +-
gas/testsuite/gas/arm/armv7-a+virt.d | 4 +-
.../gas/arm/armv8-2-fp16-scalar-ext.d | 8 +-
.../gas/arm/armv8-2-fp16-scalar-thumb-ext.d | 8 +-
.../gas/arm/armv8-2-fp16-scalar-thumb.d | 8 +-
gas/testsuite/gas/arm/armv8-2-fp16-scalar.d | 8 +-
gas/testsuite/gas/arm/armv8.1-m.main-fp.d | 70 +--
gas/testsuite/gas/arm/armv8.1-m.main-hp.d | 8 +-
gas/testsuite/gas/arm/bl-local-2.d | 10 +-
gas/testsuite/gas/arm/bl-local-v4t.d | 10 +-
gas/testsuite/gas/arm/blx-bad.d | 14 +-
gas/testsuite/gas/arm/blx-local-thumb.d | 10 +-
gas/testsuite/gas/arm/blx-local.d | 12 +-
gas/testsuite/gas/arm/branch-reloc.d | 10 +-
gas/testsuite/gas/arm/ccs.d | 2 +-
.../gas/arm/copro-arm_v2plus-arm_v2.d | 8 +-
.../gas/arm/copro-arm_v5plus-arm_v5.d | 4 +-
.../arm/copro-thumb_v6t2plus-thumb_v6t2-1.d | 4 +-
.../arm/copro-thumb_v6t2plus-thumb_v6t2-2.d | 4 +-
gas/testsuite/gas/arm/crc32-armv8-a-bad.d | 24 +-
gas/testsuite/gas/arm/crc32-armv8-r-bad.d | 24 +-
gas/testsuite/gas/arm/dis-data3.d | 2 +-
gas/testsuite/gas/arm/el_segundo.d | 2 +-
gas/testsuite/gas/arm/float.d | 2 +-
gas/testsuite/gas/arm/group-reloc-alu.d | 160 ++---
gas/testsuite/gas/arm/group-reloc-ldrs.d | 240 ++++----
gas/testsuite/gas/arm/immed.d | 10 +-
gas/testsuite/gas/arm/immed2.d | 2 +-
gas/testsuite/gas/arm/inst.d | 36 +-
gas/testsuite/gas/arm/iwmmxt.d | 2 +-
gas/testsuite/gas/arm/ldconst.d | 42 +-
gas/testsuite/gas/arm/ldr-global.d | 14 +-
gas/testsuite/gas/arm/ldr-t.d | 16 +-
gas/testsuite/gas/arm/ldr.d | 10 +-
gas/testsuite/gas/arm/ldst-offset0.d | 6 +-
gas/testsuite/gas/arm/ldst-pc.d | 8 +-
gas/testsuite/gas/arm/m0-load-pseudo.d | 4 +-
gas/testsuite/gas/arm/m23-load-pseudo.d | 4 +-
gas/testsuite/gas/arm/m33-load-pseudo.d | 4 +-
gas/testsuite/gas/arm/macro1.d | 6 +-
gas/testsuite/gas/arm/mapdir.d | 4 +-
gas/testsuite/gas/arm/mapmisc.d | 38 +-
gas/testsuite/gas/arm/mapsecs.d | 10 +-
gas/testsuite/gas/arm/mapshort-eabi.d | 10 +-
gas/testsuite/gas/arm/mapshort-elf.d | 10 +-
gas/testsuite/gas/arm/mask_1-armv8-a.d | 32 +-
gas/testsuite/gas/arm/mask_1-armv8-r.d | 32 +-
gas/testsuite/gas/arm/mrs-msr-arm-v6.d | 6 +-
gas/testsuite/gas/arm/mrs-msr-arm-v7-a.d | 6 +-
gas/testsuite/gas/arm/msr-imm.d | 268 ++++-----
gas/testsuite/gas/arm/mve-vand.d | 94 +--
gas/testsuite/gas/arm/mve-vbic.d | 20 +-
gas/testsuite/gas/arm/mve-vcvt-3.d | 80 +--
gas/testsuite/gas/arm/mve-vmov-1.d | 20 +-
gas/testsuite/gas/arm/mve-vmov-2.d | 34 +-
.../gas/arm/mve-vmov-vmvn-vorr-vbic.d | 64 +-
gas/testsuite/gas/arm/mve-vmvn.d | 114 ++--
gas/testsuite/gas/arm/mve-vorn.d | 22 +-
gas/testsuite/gas/arm/mve-vorr.d | 20 +-
gas/testsuite/gas/arm/neon-cond-bad_t2.d | 4 +-
gas/testsuite/gas/arm/neon-const.d | 516 ++++++++--------
gas/testsuite/gas/arm/neon-cov.d | 564 +++++++++---------
gas/testsuite/gas/arm/neon-ldst-rm.d | 4 +-
gas/testsuite/gas/arm/neon-logic.d | 8 +-
gas/testsuite/gas/arm/nops.d | 2 +-
gas/testsuite/gas/arm/offset-1.d | 8 +-
gas/testsuite/gas/arm/offset.d | 8 +-
gas/testsuite/gas/arm/pr21458.d | 14 +-
gas/testsuite/gas/arm/pr24907.d | 6 +-
gas/testsuite/gas/arm/pr25235.d | 14 +-
gas/testsuite/gas/arm/push-pop.d | 8 +-
gas/testsuite/gas/arm/reg-alias.d | 6 +-
gas/testsuite/gas/arm/relax_branch_align.d | 8 +-
gas/testsuite/gas/arm/relax_load_align.d | 6 +-
gas/testsuite/gas/arm/sp-pc-usage-t.d | 8 +-
gas/testsuite/gas/arm/tcompat.d | 6 +-
gas/testsuite/gas/arm/tcompat2.d | 8 +-
gas/testsuite/gas/arm/thumb-eabi.d | 42 +-
gas/testsuite/gas/arm/thumb-nop.d | 4 +-
gas/testsuite/gas/arm/thumb.d | 42 +-
gas/testsuite/gas/arm/thumb1_unified.d | 4 +-
gas/testsuite/gas/arm/thumb2_add.d | 38 +-
gas/testsuite/gas/arm/thumb2_invert.d | 24 +-
gas/testsuite/gas/arm/thumb2_pool.d | 32 +-
gas/testsuite/gas/arm/thumb2_relax.d | 52 +-
gas/testsuite/gas/arm/thumb2_vpool.d | 158 ++---
gas/testsuite/gas/arm/thumb2_vpool_be.d | 158 ++---
gas/testsuite/gas/arm/thumb32.d | 186 +++---
gas/testsuite/gas/arm/thumbv6.d | 8 +-
gas/testsuite/gas/arm/thumbv6k.d | 8 +-
gas/testsuite/gas/arm/tls.d | 14 +-
gas/testsuite/gas/arm/tls_vxworks.d | 6 +-
gas/testsuite/gas/arm/udf.d | 24 +-
gas/testsuite/gas/arm/unpredictable.d | 2 +-
gas/testsuite/gas/arm/vfp-mov-enc.d | 18 +-
gas/testsuite/gas/arm/vfp-neon-overlap.d | 8 +-
gas/testsuite/gas/arm/vfp1.d | 6 +-
gas/testsuite/gas/arm/vfp1xD.d | 76 +--
gas/testsuite/gas/arm/vfp1xD_t2.d | 70 +--
gas/testsuite/gas/arm/vfpv3-32drs.d | 6 +-
gas/testsuite/gas/arm/vldconst.d | 246 ++++----
gas/testsuite/gas/arm/vldconst_be.d | 246 ++++----
gas/testsuite/gas/arm/vldr.d | 4 +-
gas/testsuite/gas/arm/wince.d | 12 +-
gas/testsuite/gas/arm/wince_inst.d | 36 +-
gas/testsuite/gas/arm/xscale.d | 4 +-
ld/testsuite/ld-arm/arm-app-abs32.d | 8 +-
ld/testsuite/ld-arm/arm-app.d | 6 +-
ld/testsuite/ld-arm/arm-be8.d | 2 +-
ld/testsuite/ld-arm/arm-call.d | 8 +-
ld/testsuite/ld-arm/arm-lib-plt32.d | 6 +-
ld/testsuite/ld-arm/arm-lib.d | 6 +-
ld/testsuite/ld-arm/arm-movwt.d | 40 +-
ld/testsuite/ld-arm/arm-pic-veneer.d | 4 +-
ld/testsuite/ld-arm/armthumb-lib.d | 16 +-
ld/testsuite/ld-arm/attr-merge-wchar-24.d | 2 +-
ld/testsuite/ld-arm/attr-merge-wchar-42.d | 2 +-
ld/testsuite/ld-arm/callweak.d | 2 +-
ld/testsuite/ld-arm/cortex-a8-far.d | 6 +-
ld/testsuite/ld-arm/cortex-a8-fix-b-plt.d | 8 +-
ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.d | 8 +-
ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.d | 8 +-
.../ld-arm/cortex-a8-fix-bl-rel-plt.d | 8 +-
ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.d | 8 +-
.../ld-arm/farcall-arm-arm-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-arm-arm.d | 2 +-
ld/testsuite/ld-arm/farcall-arm-nacl-pic.d | 4 +-
ld/testsuite/ld-arm/farcall-arm-nacl.d | 4 +-
.../ld-arm/farcall-arm-thumb-blx-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-arm-thumb-blx.d | 2 +-
.../ld-arm/farcall-arm-thumb-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-arm-thumb.d | 2 +-
ld/testsuite/ld-arm/farcall-data-nacl.d | 4 +-
ld/testsuite/ld-arm/farcall-data.d | 2 +-
ld/testsuite/ld-arm/farcall-group-limit.d | 2 +-
ld/testsuite/ld-arm/farcall-group-size2.d | 10 +-
ld/testsuite/ld-arm/farcall-group.d | 10 +-
ld/testsuite/ld-arm/farcall-mix.d | 10 +-
ld/testsuite/ld-arm/farcall-mix2.d | 10 +-
ld/testsuite/ld-arm/farcall-mixed-app-v5.d | 26 +-
ld/testsuite/ld-arm/farcall-mixed-app.d | 26 +-
ld/testsuite/ld-arm/farcall-mixed-app2.d | 28 +-
ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d | 36 +-
ld/testsuite/ld-arm/farcall-mixed-lib.d | 24 +-
.../ld-arm/farcall-thumb-arm-blx-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb-arm-blx.d | 2 +-
.../ld-arm/farcall-thumb-arm-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb-arm.d | 2 +-
.../farcall-thumb-thumb-blx-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d | 2 +-
.../ld-arm/farcall-thumb-thumb-m-no-profile.d | 2 +-
.../ld-arm/farcall-thumb-thumb-m-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb-thumb-m.d | 2 +-
.../ld-arm/farcall-thumb-thumb-pic-veneer.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb-thumb.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb2-purecode.d | 2 +-
ld/testsuite/ld-arm/farcall-thumb2-thumb2-m.d | 2 +-
ld/testsuite/ld-arm/fdpic-main-m.d | 16 +-
ld/testsuite/ld-arm/fdpic-main.d | 16 +-
ld/testsuite/ld-arm/fdpic-shared-m.d | 4 +-
ld/testsuite/ld-arm/fdpic-shared.d | 4 +-
ld/testsuite/ld-arm/fix-arm1176-off.d | 2 +-
ld/testsuite/ld-arm/fix-arm1176-on.d | 2 +-
ld/testsuite/ld-arm/gc-hidden-1.d | 2 +-
ld/testsuite/ld-arm/group-relocs.d | 58 +-
ld/testsuite/ld-arm/ifunc-1.dd | 50 +-
ld/testsuite/ld-arm/ifunc-10.dd | 236 ++++----
ld/testsuite/ld-arm/ifunc-11.dd | 28 +-
ld/testsuite/ld-arm/ifunc-12.dd | 28 +-
ld/testsuite/ld-arm/ifunc-13.dd | 28 +-
ld/testsuite/ld-arm/ifunc-14.dd | 42 +-
ld/testsuite/ld-arm/ifunc-15.dd | 42 +-
ld/testsuite/ld-arm/ifunc-16.dd | 36 +-
ld/testsuite/ld-arm/ifunc-17.dd | 2 +-
ld/testsuite/ld-arm/ifunc-2.dd | 146 ++---
ld/testsuite/ld-arm/ifunc-3.dd | 40 +-
ld/testsuite/ld-arm/ifunc-4.dd | 236 ++++----
ld/testsuite/ld-arm/ifunc-5.dd | 26 +-
ld/testsuite/ld-arm/ifunc-6.dd | 38 +-
ld/testsuite/ld-arm/ifunc-7.dd | 18 +-
ld/testsuite/ld-arm/ifunc-8.dd | 118 ++--
ld/testsuite/ld-arm/ifunc-9.dd | 56 +-
.../jump-reloc-veneers-cond-long-backward.d | 2 +-
.../ld-arm/jump-reloc-veneers-cond-long.d | 2 +-
ld/testsuite/ld-arm/jump-reloc-veneers-long.d | 2 +-
ld/testsuite/ld-arm/long-plt-format.d | 4 +-
ld/testsuite/ld-arm/mixed-app-v5.d | 26 +-
ld/testsuite/ld-arm/mixed-app.d | 26 +-
ld/testsuite/ld-arm/mixed-lib.d | 12 +-
ld/testsuite/ld-arm/movw-merge.d | 4 +-
ld/testsuite/ld-arm/non-contiguous-arm2.d | 10 +-
ld/testsuite/ld-arm/non-contiguous-arm3.d | 12 +-
ld/testsuite/ld-arm/non-contiguous-arm5.d | 10 +-
ld/testsuite/ld-arm/non-contiguous-arm6.d | 12 +-
.../ld-arm/stm32l4xx-cannot-fix-far-ldm.d | 2 +-
ld/testsuite/ld-arm/stm32l4xx-fix-ldm.d | 8 +-
ld/testsuite/ld-arm/stm32l4xx-fix-vldm-dp.d | 2 +-
ld/testsuite/ld-arm/stm32l4xx-fix-vldm.d | 2 +-
ld/testsuite/ld-arm/thumb-plt.d | 4 +-
ld/testsuite/ld-arm/thumb1-adds.d | 12 +-
ld/testsuite/ld-arm/thumb1-movs.d | 10 +-
ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.d | 2 +-
ld/testsuite/ld-arm/thumb2-bl-bad.d | 2 +-
ld/testsuite/ld-arm/tls-app.d | 4 +-
ld/testsuite/ld-arm/tls-descrelax-be32.d | 112 ++--
ld/testsuite/ld-arm/tls-descrelax-be8.d | 78 +--
ld/testsuite/ld-arm/tls-descrelax-v7.d | 78 +--
ld/testsuite/ld-arm/tls-descrelax.d | 112 ++--
ld/testsuite/ld-arm/tls-descseq.d | 20 +-
ld/testsuite/ld-arm/tls-gdesc-neg.d | 14 +-
ld/testsuite/ld-arm/tls-gdesc.d | 22 +-
ld/testsuite/ld-arm/tls-gdierelax.d | 8 +-
ld/testsuite/ld-arm/tls-gdierelax2.d | 10 +-
ld/testsuite/ld-arm/tls-gdlerelax.d | 4 +-
ld/testsuite/ld-arm/tls-lib-loc.d | 14 +-
ld/testsuite/ld-arm/tls-lib.d | 4 +-
ld/testsuite/ld-arm/tls-longplt-lib.d | 28 +-
ld/testsuite/ld-arm/tls-longplt.d | 30 +-
ld/testsuite/ld-arm/tls-thumb1.d | 36 +-
ld/testsuite/ld-arm/vxworks1-lib.dd | 12 +-
ld/testsuite/ld-arm/vxworks1.dd | 10 +-
opcodes/arm-dis.c | 96 +--
237 files changed, 3548 insertions(+), 3548 deletions(-)
diff --git a/gas/testsuite/gas/arm/adr.d b/gas/testsuite/gas/arm/adr.d
index 13722cd9cdd..817d7df1859 100644
--- a/gas/testsuite/gas/arm/adr.d
+++ b/gas/testsuite/gas/arm/adr.d
@@ -7,4 +7,4 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0+ <.*> 824ff203 subhi pc, pc, #805306368 ; 0x30000000
+0+ <.*> 824ff203 subhi pc, pc, #805306368 @ 0x30000000
diff --git a/gas/testsuite/gas/arm/adrl.d b/gas/testsuite/gas/arm/adrl.d
index b6011f1f89c..9657e0eec1a 100644
--- a/gas/testsuite/gas/arm/adrl.d
+++ b/gas/testsuite/gas/arm/adrl.d
@@ -9,20 +9,20 @@
Disassembly of section .text:
...
0+2000 <.*> e24f0008 sub r0, pc, #8
-0+2004 <.*> e2400c20 sub r0, r0, #32, 24 ; 0x2000
+0+2004 <.*> e2400c20 sub r0, r0, #32, 24 @ 0x2000
0+2008 <.*> e28f0020 add r0, pc, #32
-0+200c <.*> e2800c20 add r0, r0, #32, 24 ; 0x2000
+0+200c <.*> e2800c20 add r0, r0, #32, 24 @ 0x2000
0+2010 <.*> e24f0018 sub r0, pc, #24
-0+2014 <.*> e1a00000 nop ; \(mov r0, r0\)
+0+2014 <.*> e1a00000 nop @ \(mov r0, r0\)
0+2018 <.*> e28f0008 add r0, pc, #8
-0+201c <.*> e1a00000 nop ; \(mov r0, r0\)
+0+201c <.*> e1a00000 nop @ \(mov r0, r0\)
0+2020 <.*> 028f0000 addeq r0, pc, #0
-0+2024 <.*> e1a00000 nop ; \(mov r0, r0\)
-0+2028 <.*> e24f0030 sub r0, pc, #48 ; 0x30
-0+202c <.*> e2400c20 sub r0, r0, #32, 24 ; 0x2000
-0+2030 <.*> e28f0c21 add r0, pc, #8448 ; 0x2100
-0+2034 <.*> e1a00000 nop ; \(mov r0, r0\)
+0+2024 <.*> e1a00000 nop @ \(mov r0, r0\)
+0+2028 <.*> e24f0030 sub r0, pc, #48 @ 0x30
+0+202c <.*> e2400c20 sub r0, r0, #32, 24 @ 0x2000
+0+2030 <.*> e28f0c21 add r0, pc, #8448 @ 0x2100
+0+2034 <.*> e1a00000 nop @ \(mov r0, r0\)
...
-0+4030 <.*> e28fec01 add lr, pc, #256 ; 0x100
+0+4030 <.*> e28fec01 add lr, pc, #256 @ 0x100
...
...
diff --git a/gas/testsuite/gas/arm/arch4t-eabi.d b/gas/testsuite/gas/arm/arch4t-eabi.d
index 66c0a4deb5c..3e3499d13ce 100644
--- a/gas/testsuite/gas/arm/arch4t-eabi.d
+++ b/gas/testsuite/gas/arm/arch4t-eabi.d
@@ -11,7 +11,7 @@ Disassembly of section .text:
.*: R_ARM_V4BX.*
0+04 <[^>]+> 012fff11 ? bxeq r1
.*: R_ARM_V4BX.*
-0+08 <[^>]+> e15f30b8 ? ldrh r3, \[pc, #-8\] ; 0+08 <[^>]+>
+0+08 <[^>]+> e15f30b8 ? ldrh r3, \[pc, #-8\] @ 0+08 <[^>]+>
0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5\]
0+10 <[^>]+> e19140d3 ? ldrsb r4, \[r1, r3\]
0+14 <[^>]+> e1b410f4 ? ldrsh r1, \[r4, r4\]!
@@ -21,7 +21,7 @@ Disassembly of section .text:
0+24 <[^>]+> e1d32fdf ? ldrsb r2, \[r3, #255\].*
0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\].*
0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\].*
-0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] ; 0+68 <[^>]+>
+0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] @ 0+68 <[^>]+>
0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3\]
0+38 <[^>]+> e328f002 ? msr CPSR_f, #2
0+3c <[^>]+> e121f003 ? msr CPSR_c, r3
@@ -35,5 +35,5 @@ Disassembly of section .text:
0+5c <[^>]+> e164f00a ? msr SPSR_s, sl
0+60 <[^>]+> e168f00b ? msr SPSR_f, fp
0+64 <[^>]+> e169f00c ? msr SPSR_fc, ip
-0+68 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
-0+6c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
+0+68 <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
+0+6c <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/arch4t.d b/gas/testsuite/gas/arm/arch4t.d
index f00f2b8209e..d8b7439c656 100644
--- a/gas/testsuite/gas/arm/arch4t.d
+++ b/gas/testsuite/gas/arm/arch4t.d
@@ -9,7 +9,7 @@
Disassembly of section .text:
0+00 <[^>]+> e12fff10 ? bx r0
0+04 <[^>]+> 012fff11 ? bxeq r1
-0+08 <[^>]+> e15f30b8 ? ldrh r3, \[pc, #-8\] ; 0+08 <[^>]+>
+0+08 <[^>]+> e15f30b8 ? ldrh r3, \[pc, #-8\] @ 0+08 <[^>]+>
0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5\]
0+10 <[^>]+> e19140d3 ? ldrsb r4, \[r1, r3\]
0+14 <[^>]+> e1b410f4 ? ldrsh r1, \[r4, r4\]!
@@ -19,7 +19,7 @@ Disassembly of section .text:
0+24 <[^>]+> e1d32fdf ? ldrsb r2, \[r3, #255\].*
0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\].*
0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\].*
-0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] ; 0+68 <[^>]+>
+0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] @ 0+68 <[^>]+>
0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3\]
0+38 <[^>]+> e328f002 ? msr CPSR_f, #2
0+3c <[^>]+> e121f003 ? msr CPSR_c, r3
@@ -33,6 +33,6 @@ Disassembly of section .text:
0+5c <[^>]+> e164f00a ? msr SPSR_s, sl
0+60 <[^>]+> e168f00b ? msr SPSR_f, fp
0+64 <[^>]+> e169f00c ? msr SPSR_fc, ip
-0+68 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
-0+6c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
+0+68 <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
+0+6c <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/arch7.d b/gas/testsuite/gas/arm/arch7.d
index a7149a62b39..c353b8ec21a 100644
--- a/gas/testsuite/gas/arm/arch7.d
+++ b/gas/testsuite/gas/arm/arch7.d
@@ -28,8 +28,8 @@ Disassembly of section .text:
0+050 <[^>]*> f995 f000 pli \[r5\]
0+054 <[^>]*> f995 ffff pli \[r5, #4095\].*
0+058 <[^>]*> f915 fcff pli \[r5, #-255\]
-0+05c <[^>]*> f99f ffff pli \[pc, #4095\] ; 0+0105f <[^>]*>
-0+060 <[^>]*> f91f ffff pli \[pc, #-4095\] ; f+ff065 <[^>]*>
+0+05c <[^>]*> f99f ffff pli \[pc, #4095\] @ 0+0105f <[^>]*>
+0+060 <[^>]*> f91f ffff pli \[pc, #-4095\] @ f+ff065 <[^>]*>
0+064 <[^>]*> f3af 80f0 dbg #0
0+068 <[^>]*> f3af 80ff dbg #15
0+06c <[^>]*> f3bf 8f5f dmb sy
diff --git a/gas/testsuite/gas/arm/arch7a-mp.d b/gas/testsuite/gas/arm/arch7a-mp.d
index 06042e297cc..2797d8abf74 100644
--- a/gas/testsuite/gas/arm/arch7a-mp.d
+++ b/gas/testsuite/gas/arm/arch7a-mp.d
@@ -9,8 +9,8 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f590f000 pldw \[r0\]
0[0-9a-f]+ <[^>]+> f59ef000 pldw \[lr\]
0[0-9a-f]+ <[^>]+> f591f000 pldw \[r1\]
-0[0-9a-f]+ <[^>]+> f590ffff pldw \[r0, #4095\] ; 0xfff
-0[0-9a-f]+ <[^>]+> f510ffff pldw \[r0, #-4095\] ; 0xfffff001
+0[0-9a-f]+ <[^>]+> f590ffff pldw \[r0, #4095\] @ 0xfff
+0[0-9a-f]+ <[^>]+> f510ffff pldw \[r0, #-4095\] @ 0xfffff001
0[0-9a-f]+ <[^>]+> f790f000 pldw \[r0, r0\]
0[0-9a-f]+ <[^>]+> f791f000 pldw \[r1, r0\]
0[0-9a-f]+ <[^>]+> f79ef000 pldw \[lr, r0\]
@@ -20,7 +20,7 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f8b0 f000 pldw \[r0\]
0[0-9a-f]+ <[^>]+> f8be f000 pldw \[lr\]
0[0-9a-f]+ <[^>]+> f8b1 f000 pldw \[r1\]
-0[0-9a-f]+ <[^>]+> f8b0 ffff pldw \[r0, #4095\] ; 0xfff
+0[0-9a-f]+ <[^>]+> f8b0 ffff pldw \[r0, #4095\] @ 0xfff
0[0-9a-f]+ <[^>]+> f830 fcff pldw \[r0, #-255\]
0[0-9a-f]+ <[^>]+> f830 f000 pldw \[r0, r0\]
0[0-9a-f]+ <[^>]+> f831 f000 pldw \[r1, r0\]
diff --git a/gas/testsuite/gas/arm/arch7r-mp.d b/gas/testsuite/gas/arm/arch7r-mp.d
index b6efd6a934e..45400c0c0ea 100644
--- a/gas/testsuite/gas/arm/arch7r-mp.d
+++ b/gas/testsuite/gas/arm/arch7r-mp.d
@@ -9,8 +9,8 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f590f000 pldw \[r0\]
0[0-9a-f]+ <[^>]+> f59ef000 pldw \[lr\]
0[0-9a-f]+ <[^>]+> f591f000 pldw \[r1\]
-0[0-9a-f]+ <[^>]+> f590ffff pldw \[r0, #4095\] ; 0xfff
-0[0-9a-f]+ <[^>]+> f510ffff pldw \[r0, #-4095\] ; 0xfffff001
+0[0-9a-f]+ <[^>]+> f590ffff pldw \[r0, #4095\] @ 0xfff
+0[0-9a-f]+ <[^>]+> f510ffff pldw \[r0, #-4095\] @ 0xfffff001
0[0-9a-f]+ <[^>]+> f790f000 pldw \[r0, r0\]
0[0-9a-f]+ <[^>]+> f791f000 pldw \[r1, r0\]
0[0-9a-f]+ <[^>]+> f79ef000 pldw \[lr, r0\]
@@ -20,7 +20,7 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f8b0 f000 pldw \[r0\]
0[0-9a-f]+ <[^>]+> f8be f000 pldw \[lr\]
0[0-9a-f]+ <[^>]+> f8b1 f000 pldw \[r1\]
-0[0-9a-f]+ <[^>]+> f8b0 ffff pldw \[r0, #4095\] ; 0xfff
+0[0-9a-f]+ <[^>]+> f8b0 ffff pldw \[r0, #4095\] @ 0xfff
0[0-9a-f]+ <[^>]+> f830 fcff pldw \[r0, #-255\]
0[0-9a-f]+ <[^>]+> f830 f000 pldw \[r0, r0\]
0[0-9a-f]+ <[^>]+> f831 f000 pldw \[r1, r0\]
diff --git a/gas/testsuite/gas/arm/archv6t2.d b/gas/testsuite/gas/arm/archv6t2.d
index 8769b3f3a18..cc6fbc0cc13 100644
--- a/gas/testsuite/gas/arm/archv6t2.d
+++ b/gas/testsuite/gas/arm/archv6t2.d
@@ -38,8 +38,8 @@ Disassembly of section .text:
0+78 <[^>]+> e3400000 movt r0, #0
0+7c <[^>]+> 13000000 movwne r0, #0
0+80 <[^>]+> e3009000 movw r9, #0
-0+84 <[^>]+> e3000999 movw r0, #2457 ; 0x999
-0+88 <[^>]+> e3090000 movw r0, #36864 ; 0x9000
+0+84 <[^>]+> e3000999 movw r0, #2457 @ 0x999
+0+88 <[^>]+> e3090000 movw r0, #36864 @ 0x9000
0+8c <[^>]+> e0f900b0 ldrht r0, \[r9\], #0
0+90 <[^>]+> e0f900f0 ldrsht r0, \[r9\], #0
0+94 <[^>]+> e0f900d0 ldrsbt r0, \[r9\], #0
@@ -51,8 +51,8 @@ Disassembly of section .text:
0+ac <[^>]+> e07099b9 ldrht r9, \[r0\], #-153.*
0+b0 <[^>]+> 10b090b9 ldrhtne r9, \[r0\], r9
0+b4 <[^>]+> 103090b9 ldrhtne r9, \[r0\], -r9
-0+b8 <[^>]+> 10f099b9 ldrhtne r9, \[r0\], #153 ; 0x99
-0+bc <[^>]+> 107099b9 ldrhtne r9, \[r0\], #-153 ; 0xffffff67
+0+b8 <[^>]+> 10f099b9 ldrhtne r9, \[r0\], #153 @ 0x99
+0+bc <[^>]+> 107099b9 ldrhtne r9, \[r0\], #-153 @ 0xffffff67
0+c0 <[^>]+> e02100b2 strht r0, \[r1\], -r2
0+c4 <[^>]+> 102100b2 strhtne r0, \[r1\], -r2
0+c8 <[^>]+> e0a100b2 strht r0, \[r1\], r2
@@ -61,4 +61,4 @@ Disassembly of section .text:
0+d4 <[^>]+> e06100b2 strht r0, \[r1\], #-2
0+d8 <[^>]+> 10e100b2 strhtne r0, \[r1\], #2
0+dc <[^>]+> 106100b2 strhtne r0, \[r1\], #-2
-0+e0 <[^>]+> e3009999 movw r9, #2457 ; 0x999
+0+e0 <[^>]+> e3009999 movw r9, #2457 @ 0x999
diff --git a/gas/testsuite/gas/arm/archv8m-base.d b/gas/testsuite/gas/arm/archv8m-base.d
index 6075ee048a0..d956eb55e11 100644
--- a/gas/testsuite/gas/arm/archv8m-base.d
+++ b/gas/testsuite/gas/arm/archv8m-base.d
@@ -14,12 +14,12 @@ Disassembly of section .text:
0+.* <[^>]*> e849 f800 tt r8, r9
0+.* <[^>]*> e841 f040 ttt r0, r1
0+.* <[^>]*> e849 f840 ttt r8, r9
-0+.* <[^>]*> f24f 1023 movw r0, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f2cf 1023 movt r0, #61731 ; 0xf123
-0+.* <[^>]*> f2cf 1823 movt r8, #61731 ; 0xf123
+0+.* <[^>]*> f24f 1023 movw r0, #61731 @ 0xf123
+0+.* <[^>]*> f24f 1823 movw r8, #61731 @ 0xf123
+0+.* <[^>]*> f24f 1823 movw r8, #61731 @ 0xf123
+0+.* <[^>]*> f24f 1823 movw r8, #61731 @ 0xf123
+0+.* <[^>]*> f2cf 1023 movt r0, #61731 @ 0xf123
+0+.* <[^>]*> f2cf 1823 movt r8, #61731 @ 0xf123
0+.* <[^>]*> b154 cbz r4, 0+.* <[^>]*>
0+.* <[^>]*> b94c cbnz r4, 0+.* <[^>]*>
0+.* <[^>]*> f000 b808 b.w 0+.* <[^>]*>
diff --git a/gas/testsuite/gas/arm/archv8m-main-dsp-1.d b/gas/testsuite/gas/arm/archv8m-main-dsp-1.d
index 8c2c12d0d1c..444d3005ac4 100644
--- a/gas/testsuite/gas/arm/archv8m-main-dsp-1.d
+++ b/gas/testsuite/gas/arm/archv8m-main-dsp-1.d
@@ -14,12 +14,12 @@ Disassembly of section .text:
0+.* <[^>]*> e849 f800 tt r8, r9
0+.* <[^>]*> e841 f040 ttt r0, r1
0+.* <[^>]*> e849 f840 ttt r8, r9
-0+.* <[^>]*> f24f 1023 movw r0, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f2cf 1023 movt r0, #61731 ; 0xf123
-0+.* <[^>]*> f2cf 1823 movt r8, #61731 ; 0xf123
+0+.* <[^>]*> f24f 1023 movw r0, #61731 @ 0xf123
+0+.* <[^>]*> f24f 1823 movw r8, #61731 @ 0xf123
+0+.* <[^>]*> f24f 1823 movw r8, #61731 @ 0xf123
+0+.* <[^>]*> f24f 1823 movw r8, #61731 @ 0xf123
+0+.* <[^>]*> f2cf 1023 movt r0, #61731 @ 0xf123
+0+.* <[^>]*> f2cf 1823 movt r8, #61731 @ 0xf123
0+.* <[^>]*> b154 cbz r4, 0+.* <[^>]*>
0+.* <[^>]*> b94c cbnz r4, 0+.* <[^>]*>
0+.* <[^>]*> f000 b808 b.w 0+.* <[^>]*>
diff --git a/gas/testsuite/gas/arm/archv8m-main.d b/gas/testsuite/gas/arm/archv8m-main.d
index 0b76db10fbd..d5a0c9a16a1 100644
--- a/gas/testsuite/gas/arm/archv8m-main.d
+++ b/gas/testsuite/gas/arm/archv8m-main.d
@@ -14,12 +14,12 @@ Disassembly of section .text:
0+.* <[^>]*> e849 f800 tt r8, r9
0+.* <[^>]*> e841 f040 ttt r0, r1
0+.* <[^>]*> e849 f840 ttt r8, r9
-0+.* <[^>]*> f24f 1023 movw r0, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f2cf 1023 movt r0, #61731 ; 0xf123
-0+.* <[^>]*> f2cf 1823 movt r8, #61731 ; 0xf123
+0+.* <[^>]*> f24f 1023 movw r0, #61731 @ 0xf123
+0+.* <[^>]*> f24f 1823 movw r8, #61731 @ 0xf123
+0+.* <[^>]*> f24f 1823 movw r8, #61731 @ 0xf123
+0+.* <[^>]*> f24f 1823 movw r8, #61731 @ 0xf123
+0+.* <[^>]*> f2cf 1023 movt r0, #61731 @ 0xf123
+0+.* <[^>]*> f2cf 1823 movt r8, #61731 @ 0xf123
0+.* <[^>]*> b154 cbz r4, 0+.* <[^>]*>
0+.* <[^>]*> b94c cbnz r4, 0+.* <[^>]*>
0+.* <[^>]*> f000 b808 b.w 0+.* <[^>]*>
diff --git a/gas/testsuite/gas/arm/arm3.d b/gas/testsuite/gas/arm/arm3.d
index c4a1001ba10..dd973ab7621 100644
--- a/gas/testsuite/gas/arm/arm3.d
+++ b/gas/testsuite/gas/arm/arm3.d
@@ -8,4 +8,4 @@ Disassembly of section .text:
0+0 <[^>]*> e1080091 ? swp r0, r1, \[r8\]
0+4 <[^>]*> e1423093 ? swpb r3, r3, \[r2\]
0+8 <[^>]*> a1454091 ? swpbge r4, r1, \[r5\]
-0+c <[^>]*> e1a00000 ? nop ; \(mov r0, r0\)
+0+c <[^>]*> e1a00000 ? nop @ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/arm6.d b/gas/testsuite/gas/arm/arm6.d
index 3fc0de8198b..27bd08ffbf9 100644
--- a/gas/testsuite/gas/arm/arm6.d
+++ b/gas/testsuite/gas/arm/arm6.d
@@ -8,12 +8,12 @@ Disassembly of section .text:
0+00 <[^>]+> e10f8000 ? mrs r8, CPSR
0+04 <[^>]+> e14f2000 ? mrs r2, SPSR
0+08 <[^>]+> e129f001 ? msr CPSR_fc, r1
-0+0c <[^>]+> 1328f20f ? msrne CPSR_f, #-268435456 ; 0xf0000000
+0+0c <[^>]+> 1328f20f ? msrne CPSR_f, #-268435456 @ 0xf0000000
0+10 <[^>]+> e168f008 ? msr SPSR_f, r8
0+14 <[^>]+> e169f009 ? msr SPSR_fc, r9
0+18 <[^>]+> e10f8000 ? mrs r8, CPSR
0+1c <[^>]+> e14f2000 ? mrs r2, SPSR
0+20 <[^>]+> e129f001 ? msr CPSR_fc, r1
-0+24 <[^>]+> 1328f20f ? msrne CPSR_f, #-268435456 ; 0xf0000000
+0+24 <[^>]+> 1328f20f ? msrne CPSR_f, #-268435456 @ 0xf0000000
0+28 <[^>]+> e168f008 ? msr SPSR_f, r8
0+2c <[^>]+> e169f009 ? msr SPSR_fc, r9
diff --git a/gas/testsuite/gas/arm/arm7dm.d b/gas/testsuite/gas/arm/arm7dm.d
index 9411170dbdf..0cb31cde062 100644
--- a/gas/testsuite/gas/arm/arm7dm.d
+++ b/gas/testsuite/gas/arm/arm7dm.d
@@ -14,6 +14,6 @@ Disassembly of section .text:
0+18 <[^>]+> 00b92994 ? umlalseq r2, r9, r4, r9
0+1c <[^>]+> a0eaee98 ? smlalge lr, sl, r8, lr
0+20 <[^>]+> e322f000 ? msr CPSR_x, #0
-0+24 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
-0+28 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
-0+2c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
+0+24 <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
+0+28 <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
+0+2c <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/arm7t.d b/gas/testsuite/gas/arm/arm7t.d
index a16192bd078..451497d7a77 100644
--- a/gas/testsuite/gas/arm/arm7t.d
+++ b/gas/testsuite/gas/arm/arm7t.d
@@ -15,9 +15,9 @@ Disassembly of section .text:
0+14 <[^>]*> e1f100bc ? ldrh r0, \[r1, #12\]!
0+18 <[^>]*> e15100bc ? ldrh r0, \[r1, #-12\]
0+1c <[^>]*> e09100b2 ? ldrh r0, \[r1\], r2
-0+20 <[^>]*> e3a00cff ? mov r0, #65280 ; 0xff00
-0+24 <[^>]*> e1df0bb4 ? ldrh r0, \[pc, #180\] ; 0+e0 <[^>]*>
-0+28 <[^>]*> e1df0abc ? ldrh r0, \[pc, #172\] ; 0+dc <[^>]*>
+0+20 <[^>]*> e3a00cff ? mov r0, #65280 @ 0xff00
+0+24 <[^>]*> e1df0bb4 ? ldrh r0, \[pc, #180\] @ 0+e0 <[^>]*>
+0+28 <[^>]*> e1df0abc ? ldrh r0, \[pc, #172\] @ 0+dc <[^>]*>
0+2c <[^>]*> e1c100b0 ? strh r0, \[r1\]
0+30 <[^>]*> e1e100b0 ? strh r0, \[r1, #0\]!
0+34 <[^>]*> e18100b2 ? strh r0, \[r1, r2\]
@@ -26,7 +26,7 @@ Disassembly of section .text:
0+40 <[^>]*> e1e100bc ? strh r0, \[r1, #12\]!
0+44 <[^>]*> e14100bc ? strh r0, \[r1, #-12\]
0+48 <[^>]*> e08100b2 ? strh r0, \[r1\], r2
-0+4c <[^>]*> e1cf08b8 ? strh r0, \[pc, #136\] ; 0+dc <[^>]*>
+0+4c <[^>]*> e1cf08b8 ? strh r0, \[pc, #136\] @ 0+dc <[^>]*>
0+50 <[^>]*> e1d100d0 ? ldrsb r0, \[r1\]
0+54 <[^>]*> e1f100d0 ? ldrsb r0, \[r1, #0\]!
0+58 <[^>]*> e19100d2 ? ldrsb r0, \[r1, r2\]
@@ -35,8 +35,8 @@ Disassembly of section .text:
0+64 <[^>]*> e1f100dc ? ldrsb r0, \[r1, #12\]!
0+68 <[^>]*> e15100dc ? ldrsb r0, \[r1, #-12\]
0+6c <[^>]*> e09100d2 ? ldrsb r0, \[r1\], r2
-0+70 <[^>]*> e3a000de ? mov r0, #222 ; 0xde
-0+74 <[^>]*> e1df06d0 ? ldrsb r0, \[pc, #96\] ; 0+dc <[^>]*>
+0+70 <[^>]*> e3a000de ? mov r0, #222 @ 0xde
+0+74 <[^>]*> e1df06d0 ? ldrsb r0, \[pc, #96\] @ 0+dc <[^>]*>
0+78 <[^>]*> e1d100f0 ? ldrsh r0, \[r1\]
0+7c <[^>]*> e1f100f0 ? ldrsh r0, \[r1, #0\]!
0+80 <[^>]*> e19100f2 ? ldrsh r0, \[r1, r2\]
@@ -45,9 +45,9 @@ Disassembly of section .text:
0+8c <[^>]*> e1f100fc ? ldrsh r0, \[r1, #12\]!
0+90 <[^>]*> e15100fc ? ldrsh r0, \[r1, #-12\]
0+94 <[^>]*> e09100f2 ? ldrsh r0, \[r1\], r2
-0+98 <[^>]*> e3a00cff ? mov r0, #65280 ; 0xff00
-0+9c <[^>]*> e1df03fc ? ldrsh r0, \[pc, #60\] ; 0+e0 <[^>]*>
-0+a0 <[^>]*> e1df03f4 ? ldrsh r0, \[pc, #52\] ; 0+dc <[^>]*>
+0+98 <[^>]*> e3a00cff ? mov r0, #65280 @ 0xff00
+0+9c <[^>]*> e1df03fc ? ldrsh r0, \[pc, #60\] @ 0+e0 <[^>]*>
+0+a0 <[^>]*> e1df03f4 ? ldrsh r0, \[pc, #52\] @ 0+dc <[^>]*>
0+a4 <[^>]*> e19100b2 ? ldrh r0, \[r1, r2\]
0+a8 <[^>]*> 119100b2 ? ldrhne r0, \[r1, r2\]
0+ac <[^>]*> 819100b2 ? ldrhhi r0, \[r1, r2\]
@@ -60,11 +60,11 @@ Disassembly of section .text:
0+c8 <[^>]*> 119100d2 ? ldrsbne r0, \[r1, r2\]
0+cc <[^>]*> 819100d2 ? ldrsbhi r0, \[r1, r2\]
0+d0 <[^>]*> b19100d2 ? ldrsblt r0, \[r1, r2\]
-0+d4 <[^>]*> e1df00f4 ? ldrsh r0, \[pc, #4\] ; 0+e0 <[^>]*>
-0+d8 <[^>]*> e1df00f4 ? ldrsh r0, \[pc, #4\] ; 0+e4 <[^>]*>
+0+d4 <[^>]*> e1df00f4 ? ldrsh r0, \[pc, #4\] @ 0+e0 <[^>]*>
+0+d8 <[^>]*> e1df00f4 ? ldrsh r0, \[pc, #4\] @ 0+e4 <[^>]*>
0+dc <[^>]*> 00000000 ? .*
[ ]*dc:.*fred
0+e0 <[^>]*> 0000c0de ? .*
0+e4 <[^>]*> 0000dead ? .*
-0+e8 <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\)
-0+ec <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\)
+0+e8 <[^>]*> e1a00000 ? nop[ ]+@ \(mov r0, r0\)
+0+ec <[^>]*> e1a00000 ? nop[ ]+@ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/armv1.d b/gas/testsuite/gas/arm/armv1.d
index ad8fc48f2d0..3ae310a2fb7 100644
--- a/gas/testsuite/gas/arm/armv1.d
+++ b/gas/testsuite/gas/arm/armv1.d
@@ -40,7 +40,7 @@ Disassembly of section .text:
0+74 <[^>]*> e1700000 ? cmn r0, r0
0+78 <[^>]*> e1700000 ? cmn r0, r0
0+7c <[^>]*> e170f000 ? cmnp r0, r0
-0+80 <[^>]*> e1a00000 ? nop[\s]+; \(mov r0, r0\)
+0+80 <[^>]*> e1a00000 ? nop[\s]+@ \(mov r0, r0\)
0+84 <[^>]*> e1b00000 ? movs r0, r0
0+88 <[^>]*> e1e00000 ? mvn r0, r0
0+8c <[^>]*> e1f00000 ? mvns r0, r0
@@ -69,6 +69,6 @@ Disassembly of section .text:
0+e8 <[^>]*> e8100001 ? ldmda r0, {r0}
0+ec <[^>]*> e9100001 ? ldmdb r0, {r0}
0+f0 <[^>]*> e9900001 ? ldmib r0, {r0}
-0+f4 <[^>]*> e1a00000 ? nop[\s]+; \(mov r0, r0\)
-0+f8 <[^>]*> e1a00000 ? nop[\s]+; \(mov r0, r0\)
-0+fc <[^>]*> e1a00000 ? nop[\s]+; \(mov r0, r0\)
+0+f4 <[^>]*> e1a00000 ? nop[\s]+@ \(mov r0, r0\)
+0+f8 <[^>]*> e1a00000 ? nop[\s]+@ \(mov r0, r0\)
+0+fc <[^>]*> e1a00000 ? nop[\s]+@ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/armv7-a+virt.d b/gas/testsuite/gas/arm/armv7-a+virt.d
index 1e3224ceca2..b0893f2c6c4 100644
--- a/gas/testsuite/gas/arm/armv7-a+virt.d
+++ b/gas/testsuite/gas/arm/armv7-a+virt.d
@@ -6,7 +6,7 @@
Disassembly of section .text:
0[0-9a-f]+ <[^>]+> e1400070 hvc 0
-0[0-9a-f]+ <[^>]+> e14fff7f hvc 65535 ; 0xffff
+0[0-9a-f]+ <[^>]+> e14fff7f hvc 65535 @ 0xffff
0[0-9a-f]+ <[^>]+> e160006e eret
0[0-9a-f]+ <[^>]+> e1001200 mrs r1, R8_usr
0[0-9a-f]+ <[^>]+> e1011200 mrs r1, R9_usr
@@ -75,7 +75,7 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> e12ef301 msr ELR_hyp, r1
0[0-9a-f]+ <[^>]+> e16ef301 msr SPSR_hyp, r1
0[0-9a-f]+ <[^>]+> f7e0 8000 hvc #0
-0[0-9a-f]+ <[^>]+> f7ef 8fff hvc #65535 ; 0xffff
+0[0-9a-f]+ <[^>]+> f7ef 8fff hvc #65535 @ 0xffff
0[0-9a-f]+ <[^>]+> f3de 8f00 subs pc, lr, #0
0[0-9a-f]+ <[^>]+> f3e0 8120 mrs r1, R8_usr
0[0-9a-f]+ <[^>]+> f3e1 8120 mrs r1, R9_usr
diff --git a/gas/testsuite/gas/arm/armv8-2-fp16-scalar-ext.d b/gas/testsuite/gas/arm/armv8-2-fp16-scalar-ext.d
index 0b5e4e4861c..7934fdb0544 100644
--- a/gas/testsuite/gas/arm/armv8-2-fp16-scalar-ext.d
+++ b/gas/testsuite/gas/arm/armv8-2-fp16-scalar-ext.d
@@ -10,13 +10,13 @@ Disassembly of section .text:
00000000 <label-0xc>:
0: ee001910 vmov.f16 s0, r1
4: ee100990 vmov.f16 r0, s1
- 8: eeb00900 vmov.f16 s0, #0 ; 0x40000000 2.0
+ 8: eeb00900 vmov.f16 s0, #0 @ 0x40000000 2.0
0000000c <label>:
c: 00000ffe .word 0x00000ffe
- 10: ed5f1906 vldr.16 s3, \[pc, #-12\] ; c <label>
- 14: ed1f3902 vldr.16 s6, \[pc, #-4\] ; 18 <label\+0xc>
- 18: eddf1902 vldr.16 s3, \[pc, #4\] ; 24 <label\+0x18>
+ 10: ed5f1906 vldr.16 s3, \[pc, #-12\] @ c <label>
+ 14: ed1f3902 vldr.16 s6, \[pc, #-4\] @ 18 <label\+0xc>
+ 18: eddf1902 vldr.16 s3, \[pc, #4\] @ 24 <label\+0x18>
1c: edd00902 vldr.16 s1, \[r0, #4\]
20: ed101902 vldr.16 s2, \[r0, #-4\]
24: ed803902 vstr.16 s6, \[r0, #4\]
diff --git a/gas/testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d b/gas/testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d
index 9b1ab0aaeaa..cfe40d37f3e 100644
--- a/gas/testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d
+++ b/gas/testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d
@@ -10,13 +10,13 @@ Disassembly of section .text:
00000000 <label-0xc>:
0: ee00 1910 vmov.f16 s0, r1
4: ee10 0990 vmov.f16 r0, s1
- 8: eeb0 0900 vmov.f16 s0, #0 ; 0x40000000 2.0
+ 8: eeb0 0900 vmov.f16 s0, #0 @ 0x40000000 2.0
0000000c <label>:
c: 00000ffe .word 0x00000ffe
- 10: ed5f 1904 vldr.16 s3, \[pc, #-8\] ; c <label>
- 14: ed1f 3902 vldr.16 s6, \[pc, #-4\] ; 14 <label\+0x8>
- 18: eddf 1902 vldr.16 s3, \[pc, #4\] ; 20 <label\+0x14>
+ 10: ed5f 1904 vldr.16 s3, \[pc, #-8\] @ c <label>
+ 14: ed1f 3902 vldr.16 s6, \[pc, #-4\] @ 14 <label\+0x8>
+ 18: eddf 1902 vldr.16 s3, \[pc, #4\] @ 20 <label\+0x14>
1c: edd0 0902 vldr.16 s1, \[r0, #4\]
20: ed10 1902 vldr.16 s2, \[r0, #-4\]
24: ed80 3902 vstr.16 s6, \[r0, #4\]
diff --git a/gas/testsuite/gas/arm/armv8-2-fp16-scalar-thumb.d b/gas/testsuite/gas/arm/armv8-2-fp16-scalar-thumb.d
index 0fb04fe7033..b41893373fa 100644
--- a/gas/testsuite/gas/arm/armv8-2-fp16-scalar-thumb.d
+++ b/gas/testsuite/gas/arm/armv8-2-fp16-scalar-thumb.d
@@ -10,13 +10,13 @@ Disassembly of section .text:
00000000 <label-0xc>:
0: ee00 1910 vmov.f16 s0, r1
4: ee10 0990 vmov.f16 r0, s1
- 8: eeb0 0900 vmov.f16 s0, #0 ; 0x40000000 2.0
+ 8: eeb0 0900 vmov.f16 s0, #0 @ 0x40000000 2.0
0000000c <label>:
c: 00000ffe .word 0x00000ffe
- 10: ed5f 1904 vldr.16 s3, \[pc, #-8\] ; c <label>
- 14: ed1f 3902 vldr.16 s6, \[pc, #-4\] ; 14 <label\+0x8>
- 18: eddf 1902 vldr.16 s3, \[pc, #4\] ; 20 <label\+0x14>
+ 10: ed5f 1904 vldr.16 s3, \[pc, #-8\] @ c <label>
+ 14: ed1f 3902 vldr.16 s6, \[pc, #-4\] @ 14 <label\+0x8>
+ 18: eddf 1902 vldr.16 s3, \[pc, #4\] @ 20 <label\+0x14>
1c: edd0 0902 vldr.16 s1, \[r0, #4\]
20: ed10 1902 vldr.16 s2, \[r0, #-4\]
24: ed80 3902 vstr.16 s6, \[r0, #4\]
diff --git a/gas/testsuite/gas/arm/armv8-2-fp16-scalar.d b/gas/testsuite/gas/arm/armv8-2-fp16-scalar.d
index 42e8ef4dca4..3111ee4bc25 100644
--- a/gas/testsuite/gas/arm/armv8-2-fp16-scalar.d
+++ b/gas/testsuite/gas/arm/armv8-2-fp16-scalar.d
@@ -10,13 +10,13 @@ Disassembly of section .text:
00000000 <label-0xc>:
0: ee001910 vmov.f16 s0, r1
4: ee100990 vmov.f16 r0, s1
- 8: eeb00900 vmov.f16 s0, #0 ; 0x40000000 2.0
+ 8: eeb00900 vmov.f16 s0, #0 @ 0x40000000 2.0
0000000c <label>:
c: 00000ffe .word 0x00000ffe
- 10: ed5f1906 vldr.16 s3, \[pc, #-12\] ; c <label>
- 14: ed1f3902 vldr.16 s6, \[pc, #-4\] ; 18 <label\+0xc>
- 18: eddf1902 vldr.16 s3, \[pc, #4\] ; 24 <label\+0x18>
+ 10: ed5f1906 vldr.16 s3, \[pc, #-12\] @ c <label>
+ 14: ed1f3902 vldr.16 s6, \[pc, #-4\] @ 18 <label\+0xc>
+ 18: eddf1902 vldr.16 s3, \[pc, #4\] @ 24 <label\+0x18>
1c: edd00902 vldr.16 s1, \[r0, #4\]
20: ed101902 vldr.16 s2, \[r0, #-4\]
24: ed803902 vstr.16 s6, \[r0, #4\]
diff --git a/gas/testsuite/gas/arm/armv8.1-m.main-fp.d b/gas/testsuite/gas/arm/armv8.1-m.main-fp.d
index dd69e0d5252..d1186f25684 100644
--- a/gas/testsuite/gas/arm/armv8.1-m.main-fp.d
+++ b/gas/testsuite/gas/arm/armv8.1-m.main-fp.d
@@ -32,24 +32,24 @@ Disassembly of section .text:
0+05c <[^>]*> ecb0 0a01 (vldmia|fldmias) r0!, {s0}
0+060 <[^>]*> ed30 0a01 (vldmdb|fldmdbs) r0!, {s0}
0+064 <[^>]*> ed30 0a01 (vldmdb|fldmdbs) r0!, {s0}
-0+068 <[^>]*> ec90 0b03 fldmiax r0, {d0}( ;@ Deprecated|)
-0+06c <[^>]*> ec90 0b03 fldmiax r0, {d0}( ;@ Deprecated|)
-0+070 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( ;@ Deprecated|)
-0+074 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( ;@ Deprecated|)
-0+078 <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( ;@ Deprecated|)
-0+07c <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( ;@ Deprecated|)
+0+068 <[^>]*> ec90 0b03 fldmiax r0, {d0}( @ Deprecated|)
+0+06c <[^>]*> ec90 0b03 fldmiax r0, {d0}( @ Deprecated|)
+0+070 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( @ Deprecated|)
+0+074 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( @ Deprecated|)
+0+078 <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( @ Deprecated|)
+0+07c <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( @ Deprecated|)
0+080 <[^>]*> ec80 0a01 (vstmia|fstmias) r0, {s0}
0+084 <[^>]*> ec80 0a01 (vstmia|fstmias) r0, {s0}
0+088 <[^>]*> eca0 0a01 (vstmia|fstmias) r0!, {s0}
0+08c <[^>]*> eca0 0a01 (vstmia|fstmias) r0!, {s0}
0+090 <[^>]*> ed20 0a01 (vstmdb|fstmdbs) r0!, {s0}
0+094 <[^>]*> ed20 0a01 (vstmdb|fstmdbs) r0!, {s0}
-0+098 <[^>]*> ec80 0b03 fstmiax r0, {d0}( ;@ Deprecated|)
-0+09c <[^>]*> ec80 0b03 fstmiax r0, {d0}( ;@ Deprecated|)
-0+0a0 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( ;@ Deprecated|)
-0+0a4 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( ;@ Deprecated|)
-0+0a8 <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( ;@ Deprecated|)
-0+0ac <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( ;@ Deprecated|)
+0+098 <[^>]*> ec80 0b03 fstmiax r0, {d0}( @ Deprecated|)
+0+09c <[^>]*> ec80 0b03 fstmiax r0, {d0}( @ Deprecated|)
+0+0a0 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( @ Deprecated|)
+0+0a4 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( @ Deprecated|)
+0+0a8 <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( @ Deprecated|)
+0+0ac <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( @ Deprecated|)
0+0b0 <[^>]*> eeb8 0ac0 (vcvt\.f32\.s32|fsitos) s0, s0
0+0b4 <[^>]*> eeb8 0a40 (vcvt\.f32\.u32|fuitos) s0, s0
0+0b8 <[^>]*> eebd 0a40 (vcvtr\.s32\.f32|ftosis) s0, s0
@@ -141,17 +141,17 @@ Disassembly of section .text:
0+210 <[^>]*> ec90 fa02 (vldmia|fldmias) r0, {s30-s31}
0+214 <[^>]*> ec91 0a01 (vldmia|fldmias) r1, {s0}
0+218 <[^>]*> ec9e 0a01 (vldmia|fldmias) lr, {s0}
-0+21c <[^>]*> ec80 1b03 fstmiax r0, {d1}( ;@ Deprecated|)
-0+220 <[^>]*> ec80 2b03 fstmiax r0, {d2}( ;@ Deprecated|)
-0+224 <[^>]*> ec80 fb03 fstmiax r0, {d15}( ;@ Deprecated|)
-0+228 <[^>]*> ec80 0b05 fstmiax r0, {d0-d1}( ;@ Deprecated|)
-0+22c <[^>]*> ec80 0b07 fstmiax r0, {d0-d2}( ;@ Deprecated|)
-0+230 <[^>]*> ec80 0b21 fstmiax r0, {d0-d15}( ;@ Deprecated|)
-0+234 <[^>]*> ec80 1b1f fstmiax r0, {d1-d15}( ;@ Deprecated|)
-0+238 <[^>]*> ec80 2b1d fstmiax r0, {d2-d15}( ;@ Deprecated|)
-0+23c <[^>]*> ec80 eb05 fstmiax r0, {d14-d15}( ;@ Deprecated|)
-0+240 <[^>]*> ec81 0b03 fstmiax r1, {d0}( ;@ Deprecated|)
-0+244 <[^>]*> ec8e 0b03 fstmiax lr, {d0}( ;@ Deprecated|)
+0+21c <[^>]*> ec80 1b03 fstmiax r0, {d1}( @ Deprecated|)
+0+220 <[^>]*> ec80 2b03 fstmiax r0, {d2}( @ Deprecated|)
+0+224 <[^>]*> ec80 fb03 fstmiax r0, {d15}( @ Deprecated|)
+0+228 <[^>]*> ec80 0b05 fstmiax r0, {d0-d1}( @ Deprecated|)
+0+22c <[^>]*> ec80 0b07 fstmiax r0, {d0-d2}( @ Deprecated|)
+0+230 <[^>]*> ec80 0b21 fstmiax r0, {d0-d15}( @ Deprecated|)
+0+234 <[^>]*> ec80 1b1f fstmiax r0, {d1-d15}( @ Deprecated|)
+0+238 <[^>]*> ec80 2b1d fstmiax r0, {d2-d15}( @ Deprecated|)
+0+23c <[^>]*> ec80 eb05 fstmiax r0, {d14-d15}( @ Deprecated|)
+0+240 <[^>]*> ec81 0b03 fstmiax r1, {d0}( @ Deprecated|)
+0+244 <[^>]*> ec8e 0b03 fstmiax lr, {d0}( @ Deprecated|)
0+248 <[^>]*> eeb5 0a40 (vcmp\.f32 s0, #0.0|fcmpzs s0)
0+24c <[^>]*> eef5 0a40 (vcmp\.f32 s1, #0.0|fcmpzs s1)
0+250 <[^>]*> eeb5 1a40 (vcmp\.f32 s2, #0.0|fcmpzs s2)
@@ -217,13 +217,13 @@ Disassembly of section .text:
0+334 <[^>]*> bf01 itttt eq
0+336 <[^>]*> ed35 2a01 (vldmdbeq|fldmdbseq) r5!, {s4}
0+33a <[^>]*> ed76 1a01 (vldmdbeq|fldmdbseq) r6!, {s3}
-0+33e <[^>]*> ec97 1b03 fldmiaxeq r7, {d1}( ;@ Deprecated|)
-0+342 <[^>]*> ec98 2b03 fldmiaxeq r8, {d2}( ;@ Deprecated|)
+0+33e <[^>]*> ec97 1b03 fldmiaxeq r7, {d1}( @ Deprecated|)
+0+342 <[^>]*> ec98 2b03 fldmiaxeq r8, {d2}( @ Deprecated|)
0+346 <[^>]*> bf01 itttt eq
-0+348 <[^>]*> ecb9 3b03 fldmiaxeq r9!, {d3}( ;@ Deprecated|)
-0+34c <[^>]*> ecba 4b03 fldmiaxeq sl!, {d4}( ;@ Deprecated|)
-0+350 <[^>]*> ed3b 5b03 fldmdbxeq fp!, {d5}( ;@ Deprecated|)
-0+354 <[^>]*> ed3c 6b03 fldmdbxeq ip!, {d6}( ;@ Deprecated|)
+0+348 <[^>]*> ecb9 3b03 fldmiaxeq r9!, {d3}( @ Deprecated|)
+0+34c <[^>]*> ecba 4b03 fldmiaxeq sl!, {d4}( @ Deprecated|)
+0+350 <[^>]*> ed3b 5b03 fldmdbxeq fp!, {d5}( @ Deprecated|)
+0+354 <[^>]*> ed3c 6b03 fldmdbxeq ip!, {d6}( @ Deprecated|)
0+358 <[^>]*> bf01 itttt eq
0+35a <[^>]*> ec8d 1a01 (vstmiaeq|fstmiaseq) sp, {s2}
0+35e <[^>]*> ecce 0a01 (vstmiaeq|fstmiaseq) lr, {s1}
@@ -232,13 +232,13 @@ Disassembly of section .text:
0+36a <[^>]*> bf01 itttt eq
0+36c <[^>]*> ed63 ea01 (vstmdbeq|fstmdbseq) r3!, {s29}
0+370 <[^>]*> ed24 ea01 (vstmdbeq|fstmdbseq) r4!, {s28}
-0+374 <[^>]*> ec85 7b03 fstmiaxeq r5, {d7}( ;@ Deprecated|)
-0+378 <[^>]*> ec86 8b03 fstmiaxeq r6, {d8}( ;@ Deprecated|)
+0+374 <[^>]*> ec85 7b03 fstmiaxeq r5, {d7}( @ Deprecated|)
+0+378 <[^>]*> ec86 8b03 fstmiaxeq r6, {d8}( @ Deprecated|)
0+37c <[^>]*> bf01 itttt eq
-0+37e <[^>]*> eca7 9b03 fstmiaxeq r7!, {d9}( ;@ Deprecated|)
-0+382 <[^>]*> eca8 ab03 fstmiaxeq r8!, {d10}( ;@ Deprecated|)
-0+386 <[^>]*> ed29 bb03 fstmdbxeq r9!, {d11}( ;@ Deprecated|)
-0+38a <[^>]*> ed2a cb03 fstmdbxeq sl!, {d12}( ;@ Deprecated|)
+0+37e <[^>]*> eca7 9b03 fstmiaxeq r7!, {d9}( @ Deprecated|)
+0+382 <[^>]*> eca8 ab03 fstmiaxeq r8!, {d10}( @ Deprecated|)
+0+386 <[^>]*> ed29 bb03 fstmdbxeq r9!, {d11}( @ Deprecated|)
+0+38a <[^>]*> ed2a cb03 fstmdbxeq sl!, {d12}( @ Deprecated|)
0+38e <[^>]*> bf01 itttt eq
0+390 <[^>]*> eef8 dac3 (vcvteq\.f32\.s32|fsitoseq) s27, s6
0+394 <[^>]*> eefd ca62 (vcvtreq\.s32\.f32|ftosiseq) s25, s5
diff --git a/gas/testsuite/gas/arm/armv8.1-m.main-hp.d b/gas/testsuite/gas/arm/armv8.1-m.main-hp.d
index 1743d1e19cd..41ebb842f1d 100644
--- a/gas/testsuite/gas/arm/armv8.1-m.main-hp.d
+++ b/gas/testsuite/gas/arm/armv8.1-m.main-hp.d
@@ -10,13 +10,13 @@ Disassembly of section .text:
00000000 <label-0xc>:
0: ee00 1910 vmov.f16 s0, r1
4: ee10 0990 vmov.f16 r0, s1
- 8: eeb0 0900 vmov.f16 s0, #0 ; 0x40000000 2.0
+ 8: eeb0 0900 vmov.f16 s0, #0 @ 0x40000000 2.0
0000000c <label>:
c: 00000ffe .word 0x00000ffe
- 10: ed5f 1904 vldr.16 s3, \[pc, #-8\] ; c <label>
- 14: ed1f 3902 vldr.16 s6, \[pc, #-4\] ; 14 <label\+0x8>
- 18: eddf 1902 vldr.16 s3, \[pc, #4\] ; 20 <label\+0x14>
+ 10: ed5f 1904 vldr.16 s3, \[pc, #-8\] @ c <label>
+ 14: ed1f 3902 vldr.16 s6, \[pc, #-4\] @ 14 <label\+0x8>
+ 18: eddf 1902 vldr.16 s3, \[pc, #4\] @ 20 <label\+0x14>
1c: edd0 0902 vldr.16 s1, \[r0, #4\]
20: ed10 1902 vldr.16 s2, \[r0, #-4\]
24: ed80 3902 vstr.16 s6, \[r0, #4\]
diff --git a/gas/testsuite/gas/arm/bl-local-2.d b/gas/testsuite/gas/arm/bl-local-2.d
index 6b55f5ab773..ba75aeeb617 100644
--- a/gas/testsuite/gas/arm/bl-local-2.d
+++ b/gas/testsuite/gas/arm/bl-local-2.d
@@ -9,14 +9,14 @@
Disassembly of section \.text:
0+00 <[^>]+> e12fff1e bx lr
-0+04 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+04 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+06 <[^>]+> f7ff effc blx 0+ <myfunction>
-0+0a <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+0a <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+0c <[^>]+> f7ff eff8 blx 0+ <myfunction>
-0+10 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+10 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+12 <[^>]+> f7ff eff6 blx 0+ <myfunction>
-0+16 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+16 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+18 <[^>]+> f7ff eff2 blx 0+ <myfunction>
0+1c <[^>]+> 4770 bx lr
-0+1e <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+1e <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+20 <[^>]+> fafffffd blx 0000001c <mythumbfunction>
diff --git a/gas/testsuite/gas/arm/bl-local-v4t.d b/gas/testsuite/gas/arm/bl-local-v4t.d
index cf68093988d..11af135bdcd 100644
--- a/gas/testsuite/gas/arm/bl-local-v4t.d
+++ b/gas/testsuite/gas/arm/bl-local-v4t.d
@@ -10,9 +10,9 @@ Disassembly of section .text:
0+06 <[^>]*> e003 b.n 00+10 <[^>]*>
0+08 <[^>]*> f000 f808 bl 00+1c <[^>]*>
0+0c <[^>]*> f000 f802 bl 00+14 <[^>]*>
-0+10 <[^>]*> 46c0 nop ; \(mov r8, r8\)
-0+12 <[^>]*> 46c0 nop ; \(mov r8, r8\)
-0+14 <[^>]*> 46c0 nop ; \(mov r8, r8\)
+0+10 <[^>]*> 46c0 nop @ \(mov r8, r8\)
+0+12 <[^>]*> 46c0 nop @ \(mov r8, r8\)
+0+14 <[^>]*> 46c0 nop @ \(mov r8, r8\)
...
-0+18 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
-0+1c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
+0+18 <[^>]*> e1a00000 nop @ \(mov r0, r0\)
+0+1c <[^>]*> e1a00000 nop @ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/blx-bad.d b/gas/testsuite/gas/arm/blx-bad.d
index d95729c34fe..79608eb1e21 100644
--- a/gas/testsuite/gas/arm/blx-bad.d
+++ b/gas/testsuite/gas/arm/blx-bad.d
@@ -9,16 +9,16 @@
Disassembly of section .text:
00000000 <ARM>:
- 0: e1a00000 nop ; \(mov r0, r0\)
+ 0: e1a00000 nop @ \(mov r0, r0\)
00000004 <THUMB>:
4: f7ff effc blx 0 <ARM>
- 8: 46c0 nop ; \(mov r8, r8\)
+ 8: 46c0 nop @ \(mov r8, r8\)
a: f7ff effa blx 0 <ARM>
- e: 46c0 nop ; \(mov r8, r8\)
+ e: 46c0 nop @ \(mov r8, r8\)
10: f7ff eff6 blx 0 <ARM>
- 14: f7ff eff5 ; <UNDEFINED> instruction: 0xf7ffeff5
- 18: 46c0 nop ; \(mov r8, r8\)
- 1a: f7ff eff1 ; <UNDEFINED> instruction: 0xf7ffeff1
+ 14: f7ff eff5 @ <UNDEFINED> instruction: 0xf7ffeff5
+ 18: 46c0 nop @ \(mov r8, r8\)
+ 1a: f7ff eff1 @ <UNDEFINED> instruction: 0xf7ffeff1
1e: f7ff eff0 blx 0 <ARM>
- 22: 46c0 nop ; \(mov r8, r8\)
+ 22: 46c0 nop @ \(mov r8, r8\)
diff --git a/gas/testsuite/gas/arm/blx-local-thumb.d b/gas/testsuite/gas/arm/blx-local-thumb.d
index 61b1fbdf886..9a76584c909 100644
--- a/gas/testsuite/gas/arm/blx-local-thumb.d
+++ b/gas/testsuite/gas/arm/blx-local-thumb.d
@@ -16,9 +16,9 @@ Disassembly of section .text:
[^<]*<one\+0x1c> f000 f804 bl 00000028 <fooundefthumb>
[^<]*<foo> e7ee b.n 00000000 <one>
[^<]*<foo\+0x2> e003 b.n 0000002c <foo2>
-[^<]*<foo\+0x4> 46c0 nop ; \(mov r8, r8\)
-[^<]*<foo\+0x6> 46c0 nop ; \(mov r8, r8\)
-[^<]*<fooundefthumb> 46c0 nop ; \(mov r8, r8\)
+[^<]*<foo\+0x4> 46c0 nop @ \(mov r8, r8\)
+[^<]*<foo\+0x6> 46c0 nop @ \(mov r8, r8\)
+[^<]*<fooundefthumb> 46c0 nop @ \(mov r8, r8\)
...
-[^<]*<foo2> e1a00000 nop ; \(mov r0, r0\)
-[^<]*<fooundefarm> e1a00000 nop ; \(mov r0, r0\)
+[^<]*<foo2> e1a00000 nop @ \(mov r0, r0\)
+[^<]*<fooundefarm> e1a00000 nop @ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/blx-local.d b/gas/testsuite/gas/arm/blx-local.d
index 36cfd4f7487..44c885c8ee2 100644
--- a/gas/testsuite/gas/arm/blx-local.d
+++ b/gas/testsuite/gas/arm/blx-local.d
@@ -15,15 +15,15 @@ Disassembly of section .text:
0+14 <[^>]*> eb00000a bl 00000044 <fooundefarm>
0+18 <[^>]*> fa000001 blx 00000024 <fooundefthumb>
0+1c <[^>]*> eb000000 bl 00000024 <fooundefthumb>
-0+20 <[^>]*> 46c0 nop ; \(mov r8, r8\)
-0+22 <[^>]*> 46c0 nop ; \(mov r8, r8\)
-0+24 <[^>]*> 46c0 nop ; \(mov r8, r8\)
-0+26 <[^>]*> 46c0 nop ; \(mov r8, r8\)
+0+20 <[^>]*> 46c0 nop @ \(mov r8, r8\)
+0+22 <[^>]*> 46c0 nop @ \(mov r8, r8\)
+0+24 <[^>]*> 46c0 nop @ \(mov r8, r8\)
+0+26 <[^>]*> 46c0 nop @ \(mov r8, r8\)
0+28 <[^>]*> 0bfffffd bleq 00000024 <fooundefthumb>
0+2c <[^>]*> 0afffffc beq 00000024 <fooundefthumb>
0+30 <[^>]*> eafffffb b 00000024 <fooundefthumb>
0+34 <[^>]*> 0bfffffe bleq 00000020 <foo> 34: R_ARM_JUMP24 foo
0+38 <[^>]*> 0afffffe beq 00000020 <foo> 38: R_ARM_JUMP24 foo
0+3c <[^>]*> eafffffe b 00000020 <foo> 3c: R_ARM_JUMP24 foo
-0+40 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
-0+44 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
+0+40 <[^>]*> e1a00000 nop @ \(mov r0, r0\)
+0+44 <[^>]*> e1a00000 nop @ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/branch-reloc.d b/gas/testsuite/gas/arm/branch-reloc.d
index 40159557861..118c4b8553f 100644
--- a/gas/testsuite/gas/arm/branch-reloc.d
+++ b/gas/testsuite/gas/arm/branch-reloc.d
@@ -13,7 +13,7 @@
Disassembly of section .text:
00000000 <arm_glob_sym1-0x4>:
- 0: e1a00000 nop ; \(mov r0, r0\)
+ 0: e1a00000 nop @ \(mov r0, r0\)
00000004 <arm_glob_sym1>:
4: ebfffffe bl 46 <thumb_glob_sym1>
@@ -36,11 +36,11 @@ Disassembly of section .text:
2c: fafffffe blx 13c <arm_glob_sym2>
2c: R_ARM_CALL arm_glob_sym2
30: eb000001 bl 3c <arm_sym1>
- 34: e1a00000 nop ; \(mov r0, r0\)
+ 34: e1a00000 nop @ \(mov r0, r0\)
38: e12fff1e bx lr
0000003c <arm_sym1>:
- 3c: e1a00000 nop ; \(mov r0, r0\)
+ 3c: e1a00000 nop @ \(mov r0, r0\)
40: e12fff1e bx lr
00000044 <thumb_sym1>:
@@ -75,11 +75,11 @@ Disassembly of section foo:
128: f7ff effe blx 100 <thumb_glob_sym2>
128: R_ARM_THM_CALL thumb_glob_sym2
12c: f000 f802 bl 134 <thumb_sym2>
- 130: 46c0 nop ; \(mov r8, r8\)
+ 130: 46c0 nop @ \(mov r8, r8\)
132: 4770 bx lr
00000134 <thumb_sym2>:
- 134: 46c0 nop ; \(mov r8, r8\)
+ 134: 46c0 nop @ \(mov r8, r8\)
136: 4770 bx lr
00000138 <arm_sym2>:
diff --git a/gas/testsuite/gas/arm/ccs.d b/gas/testsuite/gas/arm/ccs.d
index 742993ba846..3be96d9979e 100644
--- a/gas/testsuite/gas/arm/ccs.d
+++ b/gas/testsuite/gas/arm/ccs.d
@@ -8,7 +8,7 @@ Disassembly of section \.text:
00000000 <_test_func>:
0: e92d5fff push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
- 4: e59fc018 ldr ip, \[pc, #24\] ; 24 <sym1>
+ 4: e59fc018 ldr ip, \[pc, #24\] @ 24 <sym1>
8: e59c0000 ldr r0, \[ip\]
c: e3100008 tst r0, #8
10: 1a000000 bne 18 <aLabel>
diff --git a/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d b/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d
index 04a3d37eae2..a7f01668b79 100644
--- a/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d
+++ b/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d
@@ -14,12 +14,12 @@ Disassembly of section .text:
0+00c <[^>]*> edd1e108 ldfp f6, \[r1, #32\]
0+010 <[^>]*> 4db200ff ldcmi 0, cr0, \[r2, #1020\]!.*
0+014 <[^>]*> 5cf31710 ldclpl 7, cr1, \[r3\], #64.*
-0+018 <[^>]*> ed1f8001 ldc 0, cr8, \[pc, #-4\] ; .* <foo>
+0+018 <[^>]*> ed1f8001 ldc 0, cr8, \[pc, #-4\] @ .* <foo>
0+01c <[^>]*> ed830500 cfstr32 mvfx0, \[r3\]
0+020 <[^>]*> edc0f302 stcl 3, cr15, \[r0, #8\]
0+024 <[^>]*> 0da2c419 cfstrseq mvf12, \[r2, #100\]!.*
0+028 <[^>]*> 3ca4860c stccc 6, cr8, \[r4\], #48.*
-0+02c <[^>]*> ed0f7101 stfs f7, \[pc, #-4\] ; .* <bar>
+0+02c <[^>]*> ed0f7101 stfs f7, \[pc, #-4\] @ .* <bar>
0+030 <[^>]*> ee715212 mrc 2, 3, r5, cr1, cr2, \{0\}
0+034 <[^>]*> aeb1f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
0+038 <[^>]*> ee215711 mcr 7, 1, r5, cr1, cr1, \{0\}
@@ -30,6 +30,6 @@ Disassembly of section .text:
0+04c <[^>]*> ecc52805 stcl 8, cr2, \[r5\], \{5\}
0+050 <[^>]*> ecd88cff ldcl 12, cr8, \[r8\], \{255\}.*
0+054 <[^>]*> ecc99cfe stcl 12, cr9, \[r9\], \{254\}.*
-0+058 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
-0+05c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
+0+058 <[^>]*> e1a00000 nop @ \(mov r0, r0\)
+0+05c <[^>]*> e1a00000 nop @ \(mov r0, r0\)
0+060 <[^>]*> aeb1f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
diff --git a/gas/testsuite/gas/arm/copro-arm_v5plus-arm_v5.d b/gas/testsuite/gas/arm/copro-arm_v5plus-arm_v5.d
index ab9571707ba..3d1fe79c20e 100644
--- a/gas/testsuite/gas/arm/copro-arm_v5plus-arm_v5.d
+++ b/gas/testsuite/gas/arm/copro-arm_v5plus-arm_v5.d
@@ -11,10 +11,10 @@ Disassembly of section .text:
0+000 <[^>]*> fe421103 cdp2 1, 4, cr1, cr2, cr3, \{0\}
0+004 <[^>]*> fd939500 ldc2 5, cr9, \[r3\]
0+008 <[^>]*> fdd1e108 ldc2l 1, cr14, \[r1, #32\]
-0+00c <[^>]*> fd1f8001 ldc2 0, cr8, \[pc, #-4\] ; .* <foo>
+0+00c <[^>]*> fd1f8001 ldc2 0, cr8, \[pc, #-4\] @ .* <foo>
0+010 <[^>]*> fd830500 stc2 5, cr0, \[r3\]
0+014 <[^>]*> fdc0f302 stc2l 3, cr15, \[r0, #8\]
-0+018 <[^>]*> fd0f7101 stc2 1, cr7, \[pc, #-4\] ; .* <bar>
+0+018 <[^>]*> fd0f7101 stc2 1, cr7, \[pc, #-4\] @ .* <bar>
0+01c <[^>]*> fe715212 mrc2 2, 3, r5, cr1, cr2, \{0\}
0+020 <[^>]*> fe215711 mcr2 7, 1, r5, cr1, cr1, \{0\}
0+024 <[^>]*> fc925502 ldc2 5, cr5, \[r2\], \{2\}
diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d
index 55c696735af..35c65ac7150 100644
--- a/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d
+++ b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d
@@ -16,14 +16,14 @@ Disassembly of section .text:
0+012 <[^>]*> [^ ]* ite mi
0+014 <[^>]*> edb2 00ff ldcmi 0, cr0, \[r2, #1020\]!.*
0+018 <[^>]*> ecf3 1710 ldclpl 7, cr1, \[r3\], #64.*
-0+01c <[^>]*> ed9f 8000 ldc 0, cr8, \[pc] ; .* <foo>
+0+01c <[^>]*> ed9f 8000 ldc 0, cr8, \[pc] @ .* <foo>
0+020 <[^>]*> ed83 0500 cfstr32 mvfx0, \[r3\]
0+024 <[^>]*> edc0 f302 stcl 3, cr15, \[r0, #8\]
0+028 <[^>]*> [^ ]* it eq
0+02a <[^>]*> eda2 c419 cfstrseq mvf12, \[r2, #100\]!.*
0+02e <[^>]*> [^ ]* it cc
0+030 <[^>]*> eca4 860c stccc 6, cr8, \[r4\], #48.*
-0+034 <[^>]*> ed8f 7100 stfs f7, \[pc\] ; .* <bar>
+0+034 <[^>]*> ed8f 7100 stfs f7, \[pc\] @ .* <bar>
0+038 <[^>]*> ee71 5212 mrc 2, 3, r5, cr1, cr2, \{0\}
0+03c <[^>]*> [^ ]* it ge
0+03e <[^>]*> eeb1 f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-2.d b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-2.d
index e31536e1584..5abc82cf1dd 100644
--- a/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-2.d
+++ b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-2.d
@@ -11,10 +11,10 @@ Disassembly of section .text:
0+000 <[^>]*> fe42 1103 cdp2 1, 4, cr1, cr2, cr3, \{0\}
0+004 <[^>]*> fd93 9500 ldc2 5, cr9, \[r3\]
0+008 <[^>]*> fdd1 e108 ldc2l 1, cr14, \[r1, #32\]
-0+00c <[^>]*> fd9f 8000 ldc2 0, cr8, \[pc\] ; .* <foo>
+0+00c <[^>]*> fd9f 8000 ldc2 0, cr8, \[pc\] @ .* <foo>
0+010 <[^>]*> fd83 0500 stc2 5, cr0, \[r3\]
0+014 <[^>]*> fdc0 f302 stc2l 3, cr15, \[r0, #8\]
-0+018 <[^>]*> fd8f 7100 stc2 1, cr7, \[pc\] ; .* <bar>
+0+018 <[^>]*> fd8f 7100 stc2 1, cr7, \[pc\] @ .* <bar>
0+01c <[^>]*> fe71 5212 mrc2 2, 3, r5, cr1, cr2, \{0\}
0+020 <[^>]*> fe21 5711 mcr2 7, 1, r5, cr1, cr1, \{0\}
0+024 <[^>]*> fc92 5502 ldc2 5, cr5, \[r2\], \{2\}
diff --git a/gas/testsuite/gas/arm/crc32-armv8-a-bad.d b/gas/testsuite/gas/arm/crc32-armv8-a-bad.d
index 638c972d8a2..e19f0786d3c 100644
--- a/gas/testsuite/gas/arm/crc32-armv8-a-bad.d
+++ b/gas/testsuite/gas/arm/crc32-armv8-a-bad.d
@@ -9,15 +9,15 @@
Disassembly of section .text:
-0+0 <[^>]*> e101f042 crc32b pc, r1, r2 ; <UNPREDICTABLE>
-0+4 <[^>]*> e12f0042 crc32h r0, pc, r2 ; <UNPREDICTABLE>
-0+8 <[^>]*> e141004f crc32w r0, r1, pc ; <UNPREDICTABLE>
-0+c <[^>]*> e10f0242 crc32cb r0, pc, r2 ; <UNPREDICTABLE>
-0+10 <[^>]*> e121f242 crc32ch pc, r1, r2 ; <UNPREDICTABLE>
-0+14 <[^>]*> e14f0242 crc32cw r0, pc, r2 ; <UNPREDICTABLE>
-0+18 <[^>]*> fac1 ff82 crc32b pc, r1, r2 ; <UNPREDICTABLE>
-0+1c <[^>]*> facf f092 crc32h r0, pc, r2 ; <UNPREDICTABLE>
-0+20 <[^>]*> fac1 f0af crc32w r0, r1, pc ; <UNPREDICTABLE>
-0+24 <[^>]*> fadf f082 crc32cb r0, pc, r2 ; <UNPREDICTABLE>
-0+28 <[^>]*> fad1 ff92 crc32ch pc, r1, r2 ; <UNPREDICTABLE>
-0+2c <[^>]*> fadf f0a2 crc32cw r0, pc, r2 ; <UNPREDICTABLE>
+0+0 <[^>]*> e101f042 crc32b pc, r1, r2 @ <UNPREDICTABLE>
+0+4 <[^>]*> e12f0042 crc32h r0, pc, r2 @ <UNPREDICTABLE>
+0+8 <[^>]*> e141004f crc32w r0, r1, pc @ <UNPREDICTABLE>
+0+c <[^>]*> e10f0242 crc32cb r0, pc, r2 @ <UNPREDICTABLE>
+0+10 <[^>]*> e121f242 crc32ch pc, r1, r2 @ <UNPREDICTABLE>
+0+14 <[^>]*> e14f0242 crc32cw r0, pc, r2 @ <UNPREDICTABLE>
+0+18 <[^>]*> fac1 ff82 crc32b pc, r1, r2 @ <UNPREDICTABLE>
+0+1c <[^>]*> facf f092 crc32h r0, pc, r2 @ <UNPREDICTABLE>
+0+20 <[^>]*> fac1 f0af crc32w r0, r1, pc @ <UNPREDICTABLE>
+0+24 <[^>]*> fadf f082 crc32cb r0, pc, r2 @ <UNPREDICTABLE>
+0+28 <[^>]*> fad1 ff92 crc32ch pc, r1, r2 @ <UNPREDICTABLE>
+0+2c <[^>]*> fadf f0a2 crc32cw r0, pc, r2 @ <UNPREDICTABLE>
diff --git a/gas/testsuite/gas/arm/crc32-armv8-r-bad.d b/gas/testsuite/gas/arm/crc32-armv8-r-bad.d
index 5a00ffcacc3..a4cefc184c7 100644
--- a/gas/testsuite/gas/arm/crc32-armv8-r-bad.d
+++ b/gas/testsuite/gas/arm/crc32-armv8-r-bad.d
@@ -9,15 +9,15 @@
Disassembly of section .text:
-0+0 <[^>]*> e101f042 crc32b pc, r1, r2 ; <UNPREDICTABLE>
-0+4 <[^>]*> e12f0042 crc32h r0, pc, r2 ; <UNPREDICTABLE>
-0+8 <[^>]*> e141004f crc32w r0, r1, pc ; <UNPREDICTABLE>
-0+c <[^>]*> e10f0242 crc32cb r0, pc, r2 ; <UNPREDICTABLE>
-0+10 <[^>]*> e121f242 crc32ch pc, r1, r2 ; <UNPREDICTABLE>
-0+14 <[^>]*> e14f0242 crc32cw r0, pc, r2 ; <UNPREDICTABLE>
-0+18 <[^>]*> fac1 ff82 crc32b pc, r1, r2 ; <UNPREDICTABLE>
-0+1c <[^>]*> facf f092 crc32h r0, pc, r2 ; <UNPREDICTABLE>
-0+20 <[^>]*> fac1 f0af crc32w r0, r1, pc ; <UNPREDICTABLE>
-0+24 <[^>]*> fadf f082 crc32cb r0, pc, r2 ; <UNPREDICTABLE>
-0+28 <[^>]*> fad1 ff92 crc32ch pc, r1, r2 ; <UNPREDICTABLE>
-0+2c <[^>]*> fadf f0a2 crc32cw r0, pc, r2 ; <UNPREDICTABLE>
+0+0 <[^>]*> e101f042 crc32b pc, r1, r2 @ <UNPREDICTABLE>
+0+4 <[^>]*> e12f0042 crc32h r0, pc, r2 @ <UNPREDICTABLE>
+0+8 <[^>]*> e141004f crc32w r0, r1, pc @ <UNPREDICTABLE>
+0+c <[^>]*> e10f0242 crc32cb r0, pc, r2 @ <UNPREDICTABLE>
+0+10 <[^>]*> e121f242 crc32ch pc, r1, r2 @ <UNPREDICTABLE>
+0+14 <[^>]*> e14f0242 crc32cw r0, pc, r2 @ <UNPREDICTABLE>
+0+18 <[^>]*> fac1 ff82 crc32b pc, r1, r2 @ <UNPREDICTABLE>
+0+1c <[^>]*> facf f092 crc32h r0, pc, r2 @ <UNPREDICTABLE>
+0+20 <[^>]*> fac1 f0af crc32w r0, r1, pc @ <UNPREDICTABLE>
+0+24 <[^>]*> fadf f082 crc32cb r0, pc, r2 @ <UNPREDICTABLE>
+0+28 <[^>]*> fad1 ff92 crc32ch pc, r1, r2 @ <UNPREDICTABLE>
+0+2c <[^>]*> fadf f0a2 crc32cw r0, pc, r2 @ <UNPREDICTABLE>
diff --git a/gas/testsuite/gas/arm/dis-data3.d b/gas/testsuite/gas/arm/dis-data3.d
index f0e1afd456e..e7ea111c73b 100644
--- a/gas/testsuite/gas/arm/dis-data3.d
+++ b/gas/testsuite/gas/arm/dis-data3.d
@@ -8,4 +8,4 @@ Disassembly of section \.text:
00000000 <main> 20010000 .word 0x20010000
00000004 <main\+0x4> 000000f9 .word 0x000000f9
00000008 <main\+0x8> 00004cd5 .word 0x00004cd5
-0000000c <main\+0xc> e1a00000 nop ; \(mov r0, r0\)
+0000000c <main\+0xc> e1a00000 nop @ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/el_segundo.d b/gas/testsuite/gas/arm/el_segundo.d
index 6126060bbdb..256e3b86472 100644
--- a/gas/testsuite/gas/arm/el_segundo.d
+++ b/gas/testsuite/gas/arm/el_segundo.d
@@ -31,4 +31,4 @@ Disassembly of section \.text:
0+60 <[^>]+> e1220051 qsub r0, r1, r2
0+64 <[^>]+> e1620051 qdsub r0, r1, r2
0+68 <[^>]+> e1220051 qsub r0, r1, r2
-0+6c <[^>]+> e1a00000 nop ; \(mov r0, r0\)
+0+6c <[^>]+> e1a00000 nop @ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/float.d b/gas/testsuite/gas/arm/float.d
index c04943099a0..9faaf209158 100644
--- a/gas/testsuite/gas/arm/float.d
+++ b/gas/testsuite/gas/arm/float.d
@@ -124,7 +124,7 @@ Disassembly of section .text:
0+1d0 <[^>]+> ed911210 ? lfm f1, 4, \[r1, #64\].*
0+1d4 <[^>]+> edae22ff ? sfm f2, 4, \[lr, #1020\]!.*
0+1d8 <[^>]+> 0c68f2ff ? sfmeq f7, 3, \[r8\], #-1020.*
-0+1dc <[^>]+> eddf6200 ? lfm f6, 2, \[pc\] ; .* <l\+.*>
+0+1dc <[^>]+> eddf6200 ? lfm f6, 2, \[pc\] @ .* <l\+.*>
0+1e0 <[^>]+> eca8f203 ? sfm f7, 1, \[r8\], #12
0+1e4 <[^>]+> 0d16520c ? lfmeq f5, 4, \[r6, #-48\].*
0+1e8 <[^>]+> 1d42c209 ? sfmne f4, 3, \[r2, #-36\].*
diff --git a/gas/testsuite/gas/arm/group-reloc-alu.d b/gas/testsuite/gas/arm/group-reloc-alu.d
index 3f84b7042b1..d435017f7b0 100644
--- a/gas/testsuite/gas/arm/group-reloc-alu.d
+++ b/gas/testsuite/gas/arm/group-reloc-alu.d
@@ -5,164 +5,164 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
0: R_ARM_ALU_PC_G0 f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
4: R_ARM_ALU_PC_G1 f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
8: R_ARM_ALU_PC_G2 f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
c: R_ARM_ALU_PC_G0_NC f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
10: R_ARM_ALU_PC_G1_NC f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
14: R_ARM_ALU_SB_G0 f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
18: R_ARM_ALU_SB_G1 f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
1c: R_ARM_ALU_SB_G2 f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
20: R_ARM_ALU_SB_G0_NC f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
24: R_ARM_ALU_SB_G1_NC f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
28: R_ARM_ALU_PC_G0 localsym
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
2c: R_ARM_ALU_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
30: R_ARM_ALU_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
34: R_ARM_ALU_PC_G0_NC localsym
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
38: R_ARM_ALU_PC_G1_NC localsym
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
3c: R_ARM_ALU_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
40: R_ARM_ALU_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
44: R_ARM_ALU_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
48: R_ARM_ALU_SB_G0_NC localsym
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
4c: R_ARM_ALU_SB_G1_NC localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
50: R_ARM_ALU_PC_G0 f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
54: R_ARM_ALU_PC_G1 f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
58: R_ARM_ALU_PC_G2 f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
5c: R_ARM_ALU_PC_G0_NC f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
60: R_ARM_ALU_PC_G1_NC f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
64: R_ARM_ALU_SB_G0 f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
68: R_ARM_ALU_SB_G1 f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
6c: R_ARM_ALU_SB_G2 f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
70: R_ARM_ALU_SB_G0_NC f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
74: R_ARM_ALU_SB_G1_NC f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
78: R_ARM_ALU_PC_G0 localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
7c: R_ARM_ALU_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
80: R_ARM_ALU_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
84: R_ARM_ALU_PC_G0_NC localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
88: R_ARM_ALU_PC_G1_NC localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
8c: R_ARM_ALU_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
90: R_ARM_ALU_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
94: R_ARM_ALU_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
98: R_ARM_ALU_SB_G0_NC localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
9c: R_ARM_ALU_SB_G1_NC localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
a0: R_ARM_ALU_PC_G0 f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
a4: R_ARM_ALU_PC_G1 f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
a8: R_ARM_ALU_PC_G2 f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
ac: R_ARM_ALU_PC_G0_NC f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
b0: R_ARM_ALU_PC_G1_NC f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
b4: R_ARM_ALU_SB_G0 f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
b8: R_ARM_ALU_SB_G1 f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
bc: R_ARM_ALU_SB_G2 f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
c0: R_ARM_ALU_SB_G0_NC f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
c4: R_ARM_ALU_SB_G1_NC f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
c8: R_ARM_ALU_PC_G0 localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
cc: R_ARM_ALU_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
d0: R_ARM_ALU_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
d4: R_ARM_ALU_PC_G0_NC localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
d8: R_ARM_ALU_PC_G1_NC localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
dc: R_ARM_ALU_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
e0: R_ARM_ALU_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
e4: R_ARM_ALU_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
e8: R_ARM_ALU_SB_G0_NC localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
ec: R_ARM_ALU_SB_G1_NC localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
f0: R_ARM_ALU_PC_G0 f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
f4: R_ARM_ALU_PC_G1 f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
f8: R_ARM_ALU_PC_G2 f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
fc: R_ARM_ALU_PC_G0_NC f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
100: R_ARM_ALU_PC_G1_NC f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
104: R_ARM_ALU_SB_G0 f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
108: R_ARM_ALU_SB_G1 f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
10c: R_ARM_ALU_SB_G2 f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
110: R_ARM_ALU_SB_G0_NC f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
114: R_ARM_ALU_SB_G1_NC f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
118: R_ARM_ALU_PC_G0 localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
11c: R_ARM_ALU_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
120: R_ARM_ALU_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
124: R_ARM_ALU_PC_G0_NC localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
128: R_ARM_ALU_PC_G1_NC localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
12c: R_ARM_ALU_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
130: R_ARM_ALU_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
134: R_ARM_ALU_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
138: R_ARM_ALU_SB_G0_NC localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
13c: R_ARM_ALU_SB_G1_NC localsym
0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0
diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs.d b/gas/testsuite/gas/arm/group-reloc-ldrs.d
index 6aba9bbc252..6db5d36c730 100644
--- a/gas/testsuite/gas/arm/group-reloc-ldrs.d
+++ b/gas/testsuite/gas/arm/group-reloc-ldrs.d
@@ -5,244 +5,244 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
0: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
4: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
8: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
c: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
10: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
14: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
18: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
1c: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
20: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
24: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
28: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
2c: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
30: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
34: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
38: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
3c: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
40: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
44: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
48: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
4c: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
50: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
54: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
58: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
5c: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
60: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
64: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
68: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
6c: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
70: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
74: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
78: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
7c: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
80: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
84: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
88: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
8c: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
90: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
94: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
98: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
9c: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
a0: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
a4: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
a8: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
ac: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
b0: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
b4: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
b8: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
bc: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
c0: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
c4: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
c8: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
cc: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
d0: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
d4: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
d8: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
dc: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
e0: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
e4: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
e8: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
ec: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
f0: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
f4: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
f8: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
fc: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
100: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
104: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
108: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
10c: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
110: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
114: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
118: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
11c: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
120: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
124: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
128: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
12c: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
130: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
134: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
138: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
13c: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
140: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
144: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
148: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
14c: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
150: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
154: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
158: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
15c: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
160: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
164: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
168: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
16c: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
170: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
174: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
178: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
17c: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
180: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
184: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
188: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
18c: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
190: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
194: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
198: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
19c: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
1a0: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
1a4: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
1a8: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
1ac: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
1b0: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
1b4: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
1b8: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
1bc: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
1c0: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
1c4: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
1c8: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
1cc: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
1d0: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
1d4: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
1d8: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
1dc: R_ARM_LDRS_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0
diff --git a/gas/testsuite/gas/arm/immed.d b/gas/testsuite/gas/arm/immed.d
index 42ca13bc327..4890f954d33 100644
--- a/gas/testsuite/gas/arm/immed.d
+++ b/gas/testsuite/gas/arm/immed.d
@@ -7,10 +7,10 @@
Disassembly of section .text:
0+0000 <[^>]+> e3a00000 ? mov r0, #0
0+0004 <[^>]+> e3e00003 ? mvn r0, #3
-0+0008 <[^>]+> e51f0010 ? ldr r0, \[pc, #-16\] ; 0+0 <[^>]+>
-0+000c <[^>]+> e51f0014 ? ldr r0, \[pc, #-20\] ; 0+0 <[^>]+>
+0+0008 <[^>]+> e51f0010 ? ldr r0, \[pc, #-16\] @ 0+0 <[^>]+>
+0+000c <[^>]+> e51f0014 ? ldr r0, \[pc, #-20\] @ 0+0 <[^>]+>
\.\.\.
0+1010 <[^>]+> e3a00008 ? mov r0, #8
-0+1014 <[^>]+> e59f00e4 ? ldr r0, \[pc, #228\] ; 0+1100 <[^>]+>
-0+1018 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
-0+101c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
+0+1014 <[^>]+> e59f00e4 ? ldr r0, \[pc, #228\] @ 0+1100 <[^>]+>
+0+1018 <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
+0+101c <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/immed2.d b/gas/testsuite/gas/arm/immed2.d
index 49fa895be56..3e5d4f4225c 100644
--- a/gas/testsuite/gas/arm/immed2.d
+++ b/gas/testsuite/gas/arm/immed2.d
@@ -5,4 +5,4 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0+0000 <[^>]+> b351029c ? cmplt r1, #156, 4 ; 0xc0000009
+0+0000 <[^>]+> b351029c ? cmplt r1, #156, 4 @ 0xc0000009
diff --git a/gas/testsuite/gas/arm/inst.d b/gas/testsuite/gas/arm/inst.d
index d7ca4a3ce84..6f642dbe97f 100644
--- a/gas/testsuite/gas/arm/inst.d
+++ b/gas/testsuite/gas/arm/inst.d
@@ -95,22 +95,22 @@ Disassembly of section .text:
0+14c <[^>]*> e1720004 ? cmn r2, r4
0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5
0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1
-0+158 <[^>]*> e330f00a ? teq r0, #10 ; <UNPREDICTABLE>
-0+15c <[^>]*> e132f004 ? teq r2, r4 ; <UNPREDICTABLE>
-0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5 ; <UNPREDICTABLE>
-0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1 ; <UNPREDICTABLE>
-0+168 <[^>]*> e370f00a ? cmn r0, #10 ; <UNPREDICTABLE>
-0+16c <[^>]*> e172f004 ? cmn r2, r4 ; <UNPREDICTABLE>
-0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5 ; <UNPREDICTABLE>
-0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1 ; <UNPREDICTABLE>
-0+178 <[^>]*> e350f00a ? cmp r0, #10 ; <UNPREDICTABLE>
-0+17c <[^>]*> e152f004 ? cmp r2, r4 ; <UNPREDICTABLE>
-0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5 ; <UNPREDICTABLE>
-0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1 ; <UNPREDICTABLE>
-0+188 <[^>]*> e310f00a ? tst r0, #10 ; <UNPREDICTABLE>
-0+18c <[^>]*> e112f004 ? tst r2, r4 ; <UNPREDICTABLE>
-0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5 ; <UNPREDICTABLE>
-0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1 ; <UNPREDICTABLE>
+0+158 <[^>]*> e330f00a ? teq r0, #10 @ <UNPREDICTABLE>
+0+15c <[^>]*> e132f004 ? teq r2, r4 @ <UNPREDICTABLE>
+0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5 @ <UNPREDICTABLE>
+0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1 @ <UNPREDICTABLE>
+0+168 <[^>]*> e370f00a ? cmn r0, #10 @ <UNPREDICTABLE>
+0+16c <[^>]*> e172f004 ? cmn r2, r4 @ <UNPREDICTABLE>
+0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5 @ <UNPREDICTABLE>
+0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1 @ <UNPREDICTABLE>
+0+178 <[^>]*> e350f00a ? cmp r0, #10 @ <UNPREDICTABLE>
+0+17c <[^>]*> e152f004 ? cmp r2, r4 @ <UNPREDICTABLE>
+0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5 @ <UNPREDICTABLE>
+0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1 @ <UNPREDICTABLE>
+0+188 <[^>]*> e310f00a ? tst r0, #10 @ <UNPREDICTABLE>
+0+18c <[^>]*> e112f004 ? tst r2, r4 @ <UNPREDICTABLE>
+0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5 @ <UNPREDICTABLE>
+0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1 @ <UNPREDICTABLE>
0+198 <[^>]*> e0000291 ? mul r0, r1, r2
0+19c <[^>]*> e0110392 ? muls r1, r2, r3
0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0
@@ -128,7 +128,7 @@ Disassembly of section .text:
0+1d0 <[^>]*> 14954006 ? ldrne r4, \[r5\], #6
0+1d4 <[^>]*> e6b21003 ? ldrt r1, \[r2\], r3
0+1d8 <[^>]*> e6942425 ? ldr r2, \[r4\], r5, lsr #8
-0+1dc <[^>]*> e51f0008 ? ldr r0, \[pc, #-8\] ; 0+1dc <[^>]*>
+0+1dc <[^>]*> e51f0008 ? ldr r0, \[pc, #-8\] @ 0+1dc <[^>]*>
0+1e0 <[^>]*> e5d43000 ? ldrb r3, \[r4\]
0+1e4 <[^>]*> 14f85000 ? ldrbtne r5, \[r8\], #0
0+1e8 <[^>]*> e5810000 ? str r0, \[r1\]
@@ -140,7 +140,7 @@ Disassembly of section .text:
0+200 <[^>]*> 14854006 ? strne r4, \[r5\], #6
0+204 <[^>]*> e6821003 ? str r1, \[r2\], r3
0+208 <[^>]*> e6a42425 ? strt r2, \[r4\], r5, lsr #8
-0+20c <[^>]*> e50f1004 ? str r1, \[pc, #-4\] ; 0+210 <[^>]*>
+0+20c <[^>]*> e50f1004 ? str r1, \[pc, #-4\] @ 0+210 <[^>]*>
0+210 <[^>]*> e5c71000 ? strb r1, \[r7\]
0+214 <[^>]*> e4e02000 ? strbt r2, \[r0\], #0
0+218 <[^>]*> e8900002 ? ldm r0, {r1}
diff --git a/gas/testsuite/gas/arm/iwmmxt.d b/gas/testsuite/gas/arm/iwmmxt.d
index 1739ebb476f..54b8546a87a 100644
--- a/gas/testsuite/gas/arm/iwmmxt.d
+++ b/gas/testsuite/gas/arm/iwmmxt.d
@@ -168,4 +168,4 @@ Disassembly of section .text:
0+280 <[^>]*> ae377007[ ]+wandnge[ ]+wr7, wr7, wr7
0+284 <[^>]*> ee080110[ ]+tmcr[ ]+wcgr0, r0
0+288 <[^>]*> ee1a1110[ ]+tmrc[ ]+r1, wcgr2
-0+28c <[^>]*> e1a00000[ ]+nop[ ]+; \(mov r0, r0\)
+0+28c <[^>]*> e1a00000[ ]+nop[ ]+@ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/ldconst.d b/gas/testsuite/gas/arm/ldconst.d
index 167ed00e49f..60b28ea15c8 100644
--- a/gas/testsuite/gas/arm/ldconst.d
+++ b/gas/testsuite/gas/arm/ldconst.d
@@ -7,34 +7,34 @@
Disassembly of section .text:
0+00 <[^>]*> e3a00000 ? mov r0, #0
-0+04 <[^>]*> e3a004ff ? mov r0, #-16777216 ; 0xff000000
+0+04 <[^>]*> e3a004ff ? mov r0, #-16777216 @ 0xff000000
0+08 <[^>]*> e3e00000 ? mvn r0, #0
-0+0c <[^>]*> e51f0004 ? ldr r0, \[pc, #-4\] ; 0+10 <[^>]*>
+0+0c <[^>]*> e51f0004 ? ldr r0, \[pc, #-4\] @ 0+10 <[^>]*>
0+10 <[^>]*> 0fff0000 ? .*
0+14 <[^>]*> e3a0e000 ? mov lr, #0
-0+18 <[^>]*> e3a0e8ff ? mov lr, #16711680 ; 0xff0000
-0+1c <[^>]*> e3e0e8ff ? mvn lr, #16711680 ; 0xff0000
-0+20 <[^>]*> e51fe004 ? ldr lr, \[pc, #-4\] ; 0+24 <[^>]*>
+0+18 <[^>]*> e3a0e8ff ? mov lr, #16711680 @ 0xff0000
+0+1c <[^>]*> e3e0e8ff ? mvn lr, #16711680 @ 0xff0000
+0+20 <[^>]*> e51fe004 ? ldr lr, \[pc, #-4\] @ 0+24 <[^>]*>
0+24 <[^>]*> 00fff000 ? .*
0+28 <[^>]*> 03a00000 ? moveq r0, #0
-0+2c <[^>]*> 03a00cff ? moveq r0, #65280 ; 0xff00
-0+30 <[^>]*> 03e00cff ? mvneq r0, #65280 ; 0xff00
-0+34 <[^>]*> 051f0004 ? ldreq r0, \[pc, #-4\] ; 0+38 <[^>]*>
+0+2c <[^>]*> 03a00cff ? moveq r0, #65280 @ 0xff00
+0+30 <[^>]*> 03e00cff ? mvneq r0, #65280 @ 0xff00
+0+34 <[^>]*> 051f0004 ? ldreq r0, \[pc, #-4\] @ 0+38 <[^>]*>
0+38 <[^>]*> 000fff00 ? .*
0+3c <[^>]*> 43a0b000 ? movmi fp, #0
-0+40 <[^>]*> 43a0b0ff ? movmi fp, #255 ; 0xff
-0+44 <[^>]*> 43e0b0ff ? mvnmi fp, #255 ; 0xff
-0+48 <[^>]*> 451fb004 ? ldrmi fp, \[pc, #-4\] ; 0+4c <[^>]*>
+0+40 <[^>]*> 43a0b0ff ? movmi fp, #255 @ 0xff
+0+44 <[^>]*> 43e0b0ff ? mvnmi fp, #255 @ 0xff
+0+48 <[^>]*> 451fb004 ? ldrmi fp, \[pc, #-4\] @ 0+4c <[^>]*>
0+4c <[^>]*> 0000fff0 ? .*
-0+50 <[^>]*> e59f0020 ? ldr r0, \[pc, #32\] ; 0+78 <[^>]*>
-0+54 <[^>]*> e59f301c ? ldr r3, \[pc, #28\] ; 0+78 <[^>]*>
-0+58 <[^>]*> e59f8018 ? ldr r8, \[pc, #24\] ; 0+78 <[^>]*>
-0+5c <[^>]*> e59fb014 ? ldr fp, \[pc, #20\] ; 0+78 <[^>]*>
-0+60 <[^>]*> e59fe010 ? ldr lr, \[pc, #16\] ; 0+78 <[^>]*>
-0+64 <[^>]*> e59f0010 ? ldr r0, \[pc, #16\] ; 0+7c <[^>]*>
-0+68 <[^>]*> e59f300c ? ldr r3, \[pc, #12\] ; 0+7c <[^>]*>
-0+6c <[^>]*> e59f8008 ? ldr r8, \[pc, #8\] ; 0+7c <[^>]*>
-0+70 <[^>]*> e59fb004 ? ldr fp, \[pc, #4\] ; 0+7c <[^>]*>
-0+74 <[^>]*> e51fe000 ? ldr lr, \[pc, #-0\] ; 0+7c <[^>]*>
+0+50 <[^>]*> e59f0020 ? ldr r0, \[pc, #32\] @ 0+78 <[^>]*>
+0+54 <[^>]*> e59f301c ? ldr r3, \[pc, #28\] @ 0+78 <[^>]*>
+0+58 <[^>]*> e59f8018 ? ldr r8, \[pc, #24\] @ 0+78 <[^>]*>
+0+5c <[^>]*> e59fb014 ? ldr fp, \[pc, #20\] @ 0+78 <[^>]*>
+0+60 <[^>]*> e59fe010 ? ldr lr, \[pc, #16\] @ 0+78 <[^>]*>
+0+64 <[^>]*> e59f0010 ? ldr r0, \[pc, #16\] @ 0+7c <[^>]*>
+0+68 <[^>]*> e59f300c ? ldr r3, \[pc, #12\] @ 0+7c <[^>]*>
+0+6c <[^>]*> e59f8008 ? ldr r8, \[pc, #8\] @ 0+7c <[^>]*>
+0+70 <[^>]*> e59fb004 ? ldr fp, \[pc, #4\] @ 0+7c <[^>]*>
+0+74 <[^>]*> e51fe000 ? ldr lr, \[pc, #-0\] @ 0+7c <[^>]*>
#pass
diff --git a/gas/testsuite/gas/arm/ldr-global.d b/gas/testsuite/gas/arm/ldr-global.d
index 3528d4efcbe..2c52885772d 100644
--- a/gas/testsuite/gas/arm/ldr-global.d
+++ b/gas/testsuite/gas/arm/ldr-global.d
@@ -4,11 +4,11 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0+00 <[^>]*> e59f0010 ? ldr r0, \[pc, #16\] ; 0+18 <[^>]*>
-0+04 <[^>]*> e1df00fc ? ldrsh r0, \[pc, #12\] ; 0+18 <[^>]*>
-0+08 <[^>]*> ed9f0a02 ? vldr s0, \[pc, #8\] ; 0+18 <[^>]*>
-0+0c <[^>]*> 4802 ? ldr r0, \[pc, #8\] ; \(0+18 <[^>]*>\)
-0+0e <[^>]*> 4802 ? ldr r0, \[pc, #8\] ; \(0+18 <[^>]*>\)
-0+10 <[^>]*> ed9f 0a01 ? vldr s0, \[pc, #4\] ; 0+18 <[^>]*>
-0+14 <[^>]*> f8df 0000 ? ldr\.w r0, \[pc\] ; 0+18 <[^>]*>
+0+00 <[^>]*> e59f0010 ? ldr r0, \[pc, #16\] @ 0+18 <[^>]*>
+0+04 <[^>]*> e1df00fc ? ldrsh r0, \[pc, #12\] @ 0+18 <[^>]*>
+0+08 <[^>]*> ed9f0a02 ? vldr s0, \[pc, #8\] @ 0+18 <[^>]*>
+0+0c <[^>]*> 4802 ? ldr r0, \[pc, #8\] @ \(0+18 <[^>]*>\)
+0+0e <[^>]*> 4802 ? ldr r0, \[pc, #8\] @ \(0+18 <[^>]*>\)
+0+10 <[^>]*> ed9f 0a01 ? vldr s0, \[pc, #4\] @ 0+18 <[^>]*>
+0+14 <[^>]*> f8df 0000 ? ldr\.w r0, \[pc\] @ 0+18 <[^>]*>
#...
diff --git a/gas/testsuite/gas/arm/ldr-t.d b/gas/testsuite/gas/arm/ldr-t.d
index 97637392c16..431d556a710 100644
--- a/gas/testsuite/gas/arm/ldr-t.d
+++ b/gas/testsuite/gas/arm/ldr-t.d
@@ -6,23 +6,23 @@
Disassembly of section [^>]+:
0+00 <[^>]+> f8d1 1005 ldr.w r1, \[r1, #5\]
0+04 <[^>]+> f852 1f05 ldr.w r1, \[r2, #5\]!
-0+08 <[^>]+> f8df 1005 ldr.w r1, \[pc, #5\] ; 0+11 <[^>]+0x11>
+0+08 <[^>]+> f8df 1005 ldr.w r1, \[pc, #5\] @ 0+11 <[^>]+0x11>
0+0c <[^>]+> f8d1 f005 ldr.w pc, \[r1, #5\]
-0+10 <[^>]+> f8df f004 ldr.w pc, \[pc, #4\] ; 0+18 <[^>]+0x18>
+0+10 <[^>]+> f8df f004 ldr.w pc, \[pc, #4\] @ 0+18 <[^>]+0x18>
0+14 <[^>]+> bfa2 ittt ge
-0+16 <[^>]+> 4901 ldrge r1, \[pc, #4\] ; \(0+1c <[^>]+0x1c>\)
+0+16 <[^>]+> 4901 ldrge r1, \[pc, #4\] @ \(0+1c <[^>]+0x1c>\)
0+18 <[^>]+> bf00 nopge
0+1a <[^>]+> bf00 nopge
0+1c <[^>]+> bfa8 it ge
-0+1e <[^>]+> f8df f004 ldrge.w pc, \[pc, #4\] ; 0+24 <[^>]+0x24>
+0+1e <[^>]+> f8df f004 ldrge.w pc, \[pc, #4\] @ 0+24 <[^>]+0x24>
0+22 <[^>]+> bfa2 ittt ge
-0+24 <[^>]+> f85f 1ab8 ldrge.w r1, \[pc, #-2744\] ; fffff570 <[^>]+>
+0+24 <[^>]+> f85f 1ab8 ldrge.w r1, \[pc, #-2744\] @ fffff570 <[^>]+>
0+28 <[^>]+> bf00 nopge
0+2a <[^>]+> bf00 nopge
0+2c <[^>]+> bfa8 it ge
-0+2e <[^>]+> f85f fab6 ldrge.w pc, \[pc, #-2742\] ; fffff57a <[^>]+>
-0+32 <[^>]+> f85f 1ab9 ldr.w r1, \[pc, #-2745\] ; fffff57b <[^>]+>
-0+36 <[^>]+> f85f fab6 ldr.w pc, \[pc, #-2742\] ; fffff582 <[^>]+>
+0+2e <[^>]+> f85f fab6 ldrge.w pc, \[pc, #-2742\] @ fffff57a <[^>]+>
+0+32 <[^>]+> f85f 1ab9 ldr.w r1, \[pc, #-2745\] @ fffff57b <[^>]+>
+0+36 <[^>]+> f85f fab6 ldr.w pc, \[pc, #-2742\] @ fffff582 <[^>]+>
0+3a <[^>]+> bfa2 ittt ge
0+3c <[^>]+> 5851 ldrge r1, \[r2, r1\]
0+3e <[^>]+> bf00 nopge
diff --git a/gas/testsuite/gas/arm/ldr.d b/gas/testsuite/gas/arm/ldr.d
index 6e959dee62d..679acf4770e 100644
--- a/gas/testsuite/gas/arm/ldr.d
+++ b/gas/testsuite/gas/arm/ldr.d
@@ -6,17 +6,17 @@
Disassembly of section \.text:
0+00 <[^>]+> e5911005 ldr r1, \[r1, #5\]
0+04 <[^>]+> e5b21005 ldr r1, \[r2, #5\]!
-0+08 <[^>]+> e59f1005 ldr r1, \[pc, #5\] ; 0+15 <[^>]+0x15>
+0+08 <[^>]+> e59f1005 ldr r1, \[pc, #5\] @ 0+15 <[^>]+0x15>
0+0c <[^>]+> e591f005 ldr pc, \[r1, #5\]
-0+10 <[^>]+> e59ff004 ldr pc, \[pc, #4\] ; 0+1c <[^>]+0x1c>
-0+14 <[^>]+> e51ffabc ldr pc, \[pc, #-2748\] ; fffff560 <[^>]+>
-0+18 <[^>]+> e51f1abf ldr r1, \[pc, #-2751\] ; fffff561 <[^>]+>
+0+10 <[^>]+> e59ff004 ldr pc, \[pc, #4\] @ 0+1c <[^>]+0x1c>
+0+14 <[^>]+> e51ffabc ldr pc, \[pc, #-2748\] @ fffff560 <[^>]+>
+0+18 <[^>]+> e51f1abf ldr r1, \[pc, #-2751\] @ fffff561 <[^>]+>
0+1c <[^>]+> e7911002 ldr r1, \[r1, r2\]
0+20 <[^>]+> e79f2002 ldr r2, \[pc, r2\]
0+24 <[^>]+> e7b21003 ldr r1, \[r2, r3\]!
0+28 <[^>]+> e791100c ldr r1, \[r1, ip\]
0+2c <[^>]+> e581100a str r1, \[r1, #10\]
-0+30 <[^>]+> e58f100a str r1, \[pc, #10\] ; 0+42 <[^>]+0x42>
+0+30 <[^>]+> e58f100a str r1, \[pc, #10\] @ 0+42 <[^>]+0x42>
0+34 <[^>]+> e5a2100a str r1, \[r2, #10\]!
0+38 <[^>]+> e7811002 str r1, \[r1, r2\]
0+3c <[^>]+> e78f1002 str r1, \[pc, r2\]
diff --git a/gas/testsuite/gas/arm/ldst-offset0.d b/gas/testsuite/gas/arm/ldst-offset0.d
index bcbc97d3773..df76e0686e5 100644
--- a/gas/testsuite/gas/arm/ldst-offset0.d
+++ b/gas/testsuite/gas/arm/ldst-offset0.d
@@ -46,7 +46,7 @@ Disassembly of section .text:
0+08c <[^>]*> e4e21000 strbt r1, \[r2\], #0
0+090 <[^>]*> 5d465300 stclpl 3, cr5, \[r6, #-0\]
0+094 <[^>]*> 5dc65300 stclpl 3, cr5, \[r6\]
-0+098 <[^>]*> e59f0004 ldr r0, \[pc, #4\] ; .*
-0+09c <[^>]*> e59f0000 ldr r0, \[pc\] ; .*
-0+0a0 <[^>]*> e51f0004 ldr r0, \[pc, #-4\] ; .*
+0+098 <[^>]*> e59f0004 ldr r0, \[pc, #4\] @ .*
+0+09c <[^>]*> e59f0000 ldr r0, \[pc\] @ .*
+0+0a0 <[^>]*> e51f0004 ldr r0, \[pc, #-4\] @ .*
0+0a4 <[^>]*> 00000000 .word 0x00000000
diff --git a/gas/testsuite/gas/arm/ldst-pc.d b/gas/testsuite/gas/arm/ldst-pc.d
index 7a745c541a4..bf4a8f909c0 100644
--- a/gas/testsuite/gas/arm/ldst-pc.d
+++ b/gas/testsuite/gas/arm/ldst-pc.d
@@ -7,18 +7,18 @@
.*: +file format .*arm.*
Disassembly of section .text:
-(0[0-9a-f]+) <[^>]+> e51f1008 ldr r1, \[pc, #-8\] ; \1 <[^>]*>
+(0[0-9a-f]+) <[^>]+> e51f1008 ldr r1, \[pc, #-8\] @ \1 <[^>]*>
0[0-9a-f]+ <[^>]+> e79f1002 ldr r1, \[pc, r2\]
0[0-9a-f]+ <[^>]+> e7df1002 ldrb r1, \[pc, r2\]
0[0-9a-f]+ <[^>]+> e18f00d2 ldrd r0, \[pc, r2\]
0[0-9a-f]+ <[^>]+> e19f10b2 ldrh r1, \[pc, r2\]
0[0-9a-f]+ <[^>]+> e19f10d2 ldrsb r1, \[pc, r2\]
0[0-9a-f]+ <[^>]+> e19f10f2 ldrsh r1, \[pc, r2\]
-(0[0-9a-f]+) <[^>]+> f55ff008 pld \[pc, #-8\] ; \1 <[^>]*>
+(0[0-9a-f]+) <[^>]+> f55ff008 pld \[pc, #-8\] @ \1 <[^>]*>
0[0-9a-f]+ <[^>]+> f7dff001 pld \[pc, r1\]
-(0[0-9a-f]+) <[^>]+> f45ff008 pli \[pc, #-8\] ; \1 <[^>]*>
+(0[0-9a-f]+) <[^>]+> f45ff008 pli \[pc, #-8\] @ \1 <[^>]*>
0[0-9a-f]+ <[^>]+> f6dff001 pli \[pc, r1\]
-0[0-9a-f]+ <[^>]+> e58f1004 str r1, \[pc, #4\] ; 0+038 <[^>]*>
+0[0-9a-f]+ <[^>]+> e58f1004 str r1, \[pc, #4\] @ 0+038 <[^>]*>
0[0-9a-f]+ <[^>]+> e78f1002 str r1, \[pc, r2\]
0[0-9a-f]+ <[^>]+> e7cf1002 strb r1, \[pc, r2\]
0[0-9a-f]+ <[^>]+> e18f00f2 strd r0, \[pc, r2\]
diff --git a/gas/testsuite/gas/arm/m0-load-pseudo.d b/gas/testsuite/gas/arm/m0-load-pseudo.d
index cc7e08518ff..f65e78ec1e3 100644
--- a/gas/testsuite/gas/arm/m0-load-pseudo.d
+++ b/gas/testsuite/gas/arm/m0-load-pseudo.d
@@ -7,6 +7,6 @@
Disassembly of section .text:
-[^>]*> 4800 ldr r0, \[pc, #0\] ; \(00000004 [^>]*>\)
-[^>]*> 4801 ldr r0, \[pc, #4\] ; \(00000008 [^>]*>\)
+[^>]*> 4800 ldr r0, \[pc, #0\] @ \(00000004 [^>]*>\)
+[^>]*> 4801 ldr r0, \[pc, #4\] @ \(00000008 [^>]*>\)
#...
diff --git a/gas/testsuite/gas/arm/m23-load-pseudo.d b/gas/testsuite/gas/arm/m23-load-pseudo.d
index 2e0dbe5479b..a8da7877a16 100644
--- a/gas/testsuite/gas/arm/m23-load-pseudo.d
+++ b/gas/testsuite/gas/arm/m23-load-pseudo.d
@@ -7,6 +7,6 @@
Disassembly of section .text:
-[^>]*> f240 0030 movw r0, #48 ; 0x30
-[^>]*> 4800 ldr r0, \[pc, #0\] ; \(00000008 [^>]*>\)
+[^>]*> f240 0030 movw r0, #48 @ 0x30
+[^>]*> 4800 ldr r0, \[pc, #0\] @ \(00000008 [^>]*>\)
#...
diff --git a/gas/testsuite/gas/arm/m33-load-pseudo.d b/gas/testsuite/gas/arm/m33-load-pseudo.d
index e77bffd0f4d..29e9555a934 100644
--- a/gas/testsuite/gas/arm/m33-load-pseudo.d
+++ b/gas/testsuite/gas/arm/m33-load-pseudo.d
@@ -7,5 +7,5 @@
Disassembly of section .text:
-[^>]*> f04f 0030 mov.w r0, #48 ; 0x30
-[^>]*> f04f 40e0 mov.w r0, #1879048192 ; 0x70000000
+[^>]*> f04f 0030 mov.w r0, #48 @ 0x30
+[^>]*> f04f 40e0 mov.w r0, #1879048192 @ 0x70000000
diff --git a/gas/testsuite/gas/arm/macro1.d b/gas/testsuite/gas/arm/macro1.d
index 1e28877feda..af867a4592f 100644
--- a/gas/testsuite/gas/arm/macro1.d
+++ b/gas/testsuite/gas/arm/macro1.d
@@ -7,6 +7,6 @@
Disassembly of section .text:
0+0 <[^>]*> e8bd8030 ? pop {r4, r5, pc}
-0+4 <[^>]*> e1a00000 ? nop ; \(mov r0, r0\)
-0+8 <[^>]*> e1a00000 ? nop ; \(mov r0, r0\)
-0+c <[^>]*> e1a00000 ? nop ; \(mov r0, r0\)
+0+4 <[^>]*> e1a00000 ? nop @ \(mov r0, r0\)
+0+8 <[^>]*> e1a00000 ? nop @ \(mov r0, r0\)
+0+c <[^>]*> e1a00000 ? nop @ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/mapdir.d b/gas/testsuite/gas/arm/mapdir.d
index b7f2a5cc324..b52bb0adb19 100644
--- a/gas/testsuite/gas/arm/mapdir.d
+++ b/gas/testsuite/gas/arm/mapdir.d
@@ -27,9 +27,9 @@ SYMBOL TABLE:
Disassembly of section .code:
00000000 <.code>:
- 0: e1a00000 nop ; \(mov r0, r0\)
+ 0: e1a00000 nop @ \(mov r0, r0\)
Disassembly of section .tcode:
00000000 <.tcode>:
- 0: 46c0 nop ; \(mov r8, r8\)
+ 0: 46c0 nop @ \(mov r8, r8\)
diff --git a/gas/testsuite/gas/arm/mapmisc.d b/gas/testsuite/gas/arm/mapmisc.d
index 22d58bbdba6..b67138ffdf6 100644
--- a/gas/testsuite/gas/arm/mapmisc.d
+++ b/gas/testsuite/gas/arm/mapmisc.d
@@ -58,48 +58,48 @@ SYMBOL TABLE:
Disassembly of section .text:
00000000 <foo>:
- 0: e1a00000 nop ; \(mov r0, r0\)
+ 0: e1a00000 nop @ \(mov r0, r0\)
4: 64636261 .word 0x64636261
- 8: e1a00000 nop ; \(mov r0, r0\)
+ 8: e1a00000 nop @ \(mov r0, r0\)
c: 00636261 .word 0x00636261
- 10: e1a00000 nop ; \(mov r0, r0\)
+ 10: e1a00000 nop @ \(mov r0, r0\)
14: 00676665 .word 0x00676665
- 18: e1a00000 nop ; \(mov r0, r0\)
+ 18: e1a00000 nop @ \(mov r0, r0\)
1c: 006a6968 .word 0x006a6968
- 20: e1a00000 nop ; \(mov r0, r0\)
+ 20: e1a00000 nop @ \(mov r0, r0\)
24: 0000006b .word 0x0000006b
- 28: e1a00000 nop ; \(mov r0, r0\)
+ 28: e1a00000 nop @ \(mov r0, r0\)
2c: 0000006c .word 0x0000006c
30: 00000000 .word 0x00000000
- 34: e1a00000 nop ; \(mov r0, r0\)
+ 34: e1a00000 nop @ \(mov r0, r0\)
38: 0000006d .word 0x0000006d
...
- 48: e1a00000 nop ; \(mov r0, r0\)
+ 48: e1a00000 nop @ \(mov r0, r0\)
4c: 3fc00000 .word 0x3fc00000
- 50: e1a00000 nop ; \(mov r0, r0\)
+ 50: e1a00000 nop @ \(mov r0, r0\)
54: 40200000 .word 0x40200000
- 58: e1a00000 nop ; \(mov r0, r0\)
+ 58: e1a00000 nop @ \(mov r0, r0\)
5c: 00000000 .word 0x00000000
60: 400c0000 .word 0x400c0000
- 64: e1a00000 nop ; \(mov r0, r0\)
+ 64: e1a00000 nop @ \(mov r0, r0\)
68: 00000000 .word 0x00000000
6c: 40120000 .word 0x40120000
- 70: e1a00000 nop ; \(mov r0, r0\)
+ 70: e1a00000 nop @ \(mov r0, r0\)
74: 00000004 .word 0x00000004
78: 00000004 .word 0x00000004
7c: 00000004 .word 0x00000004
80: 00000004 .word 0x00000004
- 84: e1a00000 nop ; \(mov r0, r0\)
+ 84: e1a00000 nop @ \(mov r0, r0\)
88: 00000000 .word 0x00000000
- 8c: e1a00000 nop ; \(mov r0, r0\)
+ 8c: e1a00000 nop @ \(mov r0, r0\)
90: 00000000 .word 0x00000000
- 94: e1a00000 nop ; \(mov r0, r0\)
+ 94: e1a00000 nop @ \(mov r0, r0\)
98: 00000000 .word 0x00000000
- 9c: e1a00000 nop ; \(mov r0, r0\)
+ 9c: e1a00000 nop @ \(mov r0, r0\)
a0: 7778797a .word 0x7778797a
- a4: e1a00000 nop ; \(mov r0, r0\)
- a8: e1a00000 nop ; \(mov r0, r0\)
- ac: e51f0000 ldr r0, \[pc, #-0\] ; b4 <string\+0x4>
+ a4: e1a00000 nop @ \(mov r0, r0\)
+ a8: e1a00000 nop @ \(mov r0, r0\)
+ ac: e51f0000 ldr r0, \[pc, #-0\] @ b4 <string\+0x4>
000000b0 <string>:
b0: 6261 .short 0x6261
b2: 63 .byte 0x63
diff --git a/gas/testsuite/gas/arm/mapsecs.d b/gas/testsuite/gas/arm/mapsecs.d
index ffcfd6d0134..5f013be401a 100644
--- a/gas/testsuite/gas/arm/mapsecs.d
+++ b/gas/testsuite/gas/arm/mapsecs.d
@@ -29,17 +29,17 @@ SYMBOL TABLE:
Disassembly of section .text.f1:
00000000 <f1>:
- 0: e1a00000 nop ; \(mov r0, r0\)
- 4: e1a00000 nop ; \(mov r0, r0\)
+ 0: e1a00000 nop @ \(mov r0, r0\)
+ 4: e1a00000 nop @ \(mov r0, r0\)
00000008 <f1a>:
- 8: e1a00000 nop ; \(mov r0, r0\)
+ 8: e1a00000 nop @ \(mov r0, r0\)
Disassembly of section .text.f2:
00000000 <f2>:
- 0: e1a00000 nop ; \(mov r0, r0\)
+ 0: e1a00000 nop @ \(mov r0, r0\)
4: 00000001 .word 0x00000001
00000008 <f2a>:
- 8: e1a00000 nop ; \(mov r0, r0\)
+ 8: e1a00000 nop @ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/mapshort-eabi.d b/gas/testsuite/gas/arm/mapshort-eabi.d
index 7144ace4b41..8ec5b6d08db 100644
--- a/gas/testsuite/gas/arm/mapshort-eabi.d
+++ b/gas/testsuite/gas/arm/mapshort-eabi.d
@@ -29,14 +29,14 @@ SYMBOL TABLE:
Disassembly of section .text:
0+00 <foo>:
- 0: e1a00000 nop ; \(mov r0, r0\)
- 4: 46c0 nop ; \(mov r8, r8\)
- 6: 46c0 nop ; \(mov r8, r8\)
+ 0: e1a00000 nop @ \(mov r0, r0\)
+ 4: 46c0 nop @ \(mov r8, r8\)
+ 6: 46c0 nop @ \(mov r8, r8\)
8: 00000002 .word 0x00000002
c: 00010001 .word 0x00010001
10: 0003 .short 0x0003
- 12: 46c0 nop ; \(mov r8, r8\)
- 14: 46c0 nop ; \(mov r8, r8\)
+ 12: 46c0 nop @ \(mov r8, r8\)
+ 14: 46c0 nop @ \(mov r8, r8\)
16: 0001 .short 0x0001
18: ebfffff8 bl 0 <foo>
1c: 0008 .short 0x0008
diff --git a/gas/testsuite/gas/arm/mapshort-elf.d b/gas/testsuite/gas/arm/mapshort-elf.d
index 56e84f7e71e..d4790e595c6 100644
--- a/gas/testsuite/gas/arm/mapshort-elf.d
+++ b/gas/testsuite/gas/arm/mapshort-elf.d
@@ -27,14 +27,14 @@ SYMBOL TABLE:
Disassembly of section .text:
0+00 <foo>:
- 0: e1a00000 nop ; \(mov r0, r0\)
- 4: 46c0 nop ; \(mov r8, r8\)
- 6: 46c0 nop ; \(mov r8, r8\)
+ 0: e1a00000 nop @ \(mov r0, r0\)
+ 4: 46c0 nop @ \(mov r8, r8\)
+ 6: 46c0 nop @ \(mov r8, r8\)
8: 00000002 .word 0x00000002
c: 00010001 .word 0x00010001
10: 0003 .short 0x0003
- 12: 46c0 nop ; \(mov r8, r8\)
- 14: 46c0 nop ; \(mov r8, r8\)
+ 12: 46c0 nop @ \(mov r8, r8\)
+ 14: 46c0 nop @ \(mov r8, r8\)
16: 0001 .short 0x0001
18: ebfffff8 bl 0 <foo>
1c: 0008 .short 0x0008
diff --git a/gas/testsuite/gas/arm/mask_1-armv8-a.d b/gas/testsuite/gas/arm/mask_1-armv8-a.d
index 6315f437ee2..8dd8cfbc427 100644
--- a/gas/testsuite/gas/arm/mask_1-armv8-a.d
+++ b/gas/testsuite/gas/arm/mask_1-armv8-a.d
@@ -11,19 +11,19 @@
Disassembly of section .text:
-0+000 <.*> fe011a10 mcr2 10, 0, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
-0+004 <.*> fe011b10 mcr2 11, 0, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
-0+008 <.*> fe811a10 mcr2 10, 4, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
-0+00c <.*> fe811b10 mcr2 11, 4, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
-0+010 <.*> fe811a50 mcr2 10, 4, r1, cr1, cr0, \{2\} ; <UNPREDICTABLE>
-0+014 <.*> fe811b50 mcr2 11, 4, r1, cr1, cr0, \{2\} ; <UNPREDICTABLE>
-0+018 <.*> fefb0ae0 ; <UNDEFINED> instruction: 0xfefb0ae0
-0+01c <.*> fefb0be0 ; <UNDEFINED> instruction: 0xfefb0be0
-0+020 <.*> fefb0ae0 ; <UNDEFINED> instruction: 0xfefb0ae0
-0+024 <.*> fefb0be0 ; <UNDEFINED> instruction: 0xfefb0be0
-0+028 <.*> fef80ae0 ; <UNDEFINED> instruction: 0xfef80ae0
-0+02c <.*> fef80be0 ; <UNDEFINED> instruction: 0xfef80be0
-0+030 <.*> fef90ae0 ; <UNDEFINED> instruction: 0xfef90ae0
-0+034 <.*> fef90be0 ; <UNDEFINED> instruction: 0xfef90be0
-0+038 <.*> fefa0ae0 ; <UNDEFINED> instruction: 0xfefa0ae0
-0+03c <.*> fefa0be0 ; <UNDEFINED> instruction: 0xfefa0be0
+0+000 <.*> fe011a10 mcr2 10, 0, r1, cr1, cr0, \{0\} @ <UNPREDICTABLE>
+0+004 <.*> fe011b10 mcr2 11, 0, r1, cr1, cr0, \{0\} @ <UNPREDICTABLE>
+0+008 <.*> fe811a10 mcr2 10, 4, r1, cr1, cr0, \{0\} @ <UNPREDICTABLE>
+0+00c <.*> fe811b10 mcr2 11, 4, r1, cr1, cr0, \{0\} @ <UNPREDICTABLE>
+0+010 <.*> fe811a50 mcr2 10, 4, r1, cr1, cr0, \{2\} @ <UNPREDICTABLE>
+0+014 <.*> fe811b50 mcr2 11, 4, r1, cr1, cr0, \{2\} @ <UNPREDICTABLE>
+0+018 <.*> fefb0ae0 @ <UNDEFINED> instruction: 0xfefb0ae0
+0+01c <.*> fefb0be0 @ <UNDEFINED> instruction: 0xfefb0be0
+0+020 <.*> fefb0ae0 @ <UNDEFINED> instruction: 0xfefb0ae0
+0+024 <.*> fefb0be0 @ <UNDEFINED> instruction: 0xfefb0be0
+0+028 <.*> fef80ae0 @ <UNDEFINED> instruction: 0xfef80ae0
+0+02c <.*> fef80be0 @ <UNDEFINED> instruction: 0xfef80be0
+0+030 <.*> fef90ae0 @ <UNDEFINED> instruction: 0xfef90ae0
+0+034 <.*> fef90be0 @ <UNDEFINED> instruction: 0xfef90be0
+0+038 <.*> fefa0ae0 @ <UNDEFINED> instruction: 0xfefa0ae0
+0+03c <.*> fefa0be0 @ <UNDEFINED> instruction: 0xfefa0be0
diff --git a/gas/testsuite/gas/arm/mask_1-armv8-r.d b/gas/testsuite/gas/arm/mask_1-armv8-r.d
index e45d1634e60..24815f138ef 100644
--- a/gas/testsuite/gas/arm/mask_1-armv8-r.d
+++ b/gas/testsuite/gas/arm/mask_1-armv8-r.d
@@ -11,19 +11,19 @@
Disassembly of section .text:
-0+000 <.*> fe011a10 mcr2 10, 0, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
-0+004 <.*> fe011b10 mcr2 11, 0, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
-0+008 <.*> fe811a10 mcr2 10, 4, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
-0+00c <.*> fe811b10 mcr2 11, 4, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
-0+010 <.*> fe811a50 mcr2 10, 4, r1, cr1, cr0, \{2\} ; <UNPREDICTABLE>
-0+014 <.*> fe811b50 mcr2 11, 4, r1, cr1, cr0, \{2\} ; <UNPREDICTABLE>
-0+018 <.*> fefb0ae0 ; <UNDEFINED> instruction: 0xfefb0ae0
-0+01c <.*> fefb0be0 ; <UNDEFINED> instruction: 0xfefb0be0
-0+020 <.*> fefb0ae0 ; <UNDEFINED> instruction: 0xfefb0ae0
-0+024 <.*> fefb0be0 ; <UNDEFINED> instruction: 0xfefb0be0
-0+028 <.*> fef80ae0 ; <UNDEFINED> instruction: 0xfef80ae0
-0+02c <.*> fef80be0 ; <UNDEFINED> instruction: 0xfef80be0
-0+030 <.*> fef90ae0 ; <UNDEFINED> instruction: 0xfef90ae0
-0+034 <.*> fef90be0 ; <UNDEFINED> instruction: 0xfef90be0
-0+038 <.*> fefa0ae0 ; <UNDEFINED> instruction: 0xfefa0ae0
-0+03c <.*> fefa0be0 ; <UNDEFINED> instruction: 0xfefa0be0
+0+000 <.*> fe011a10 mcr2 10, 0, r1, cr1, cr0, \{0\} @ <UNPREDICTABLE>
+0+004 <.*> fe011b10 mcr2 11, 0, r1, cr1, cr0, \{0\} @ <UNPREDICTABLE>
+0+008 <.*> fe811a10 mcr2 10, 4, r1, cr1, cr0, \{0\} @ <UNPREDICTABLE>
+0+00c <.*> fe811b10 mcr2 11, 4, r1, cr1, cr0, \{0\} @ <UNPREDICTABLE>
+0+010 <.*> fe811a50 mcr2 10, 4, r1, cr1, cr0, \{2\} @ <UNPREDICTABLE>
+0+014 <.*> fe811b50 mcr2 11, 4, r1, cr1, cr0, \{2\} @ <UNPREDICTABLE>
+0+018 <.*> fefb0ae0 @ <UNDEFINED> instruction: 0xfefb0ae0
+0+01c <.*> fefb0be0 @ <UNDEFINED> instruction: 0xfefb0be0
+0+020 <.*> fefb0ae0 @ <UNDEFINED> instruction: 0xfefb0ae0
+0+024 <.*> fefb0be0 @ <UNDEFINED> instruction: 0xfefb0be0
+0+028 <.*> fef80ae0 @ <UNDEFINED> instruction: 0xfef80ae0
+0+02c <.*> fef80be0 @ <UNDEFINED> instruction: 0xfef80be0
+0+030 <.*> fef90ae0 @ <UNDEFINED> instruction: 0xfef90ae0
+0+034 <.*> fef90be0 @ <UNDEFINED> instruction: 0xfef90be0
+0+038 <.*> fefa0ae0 @ <UNDEFINED> instruction: 0xfefa0ae0
+0+03c <.*> fefa0be0 @ <UNDEFINED> instruction: 0xfefa0be0
diff --git a/gas/testsuite/gas/arm/mrs-msr-arm-v6.d b/gas/testsuite/gas/arm/mrs-msr-arm-v6.d
index 0afafad1588..da47b786c67 100644
--- a/gas/testsuite/gas/arm/mrs-msr-arm-v6.d
+++ b/gas/testsuite/gas/arm/mrs-msr-arm-v6.d
@@ -8,9 +8,9 @@ Disassembly of section .text:
0+00 <[^>]*> e10f4000 mrs r4, CPSR
0+04 <[^>]*> e10f5000 mrs r5, CPSR
0+08 <[^>]*> e14f6000 mrs r6, SPSR
-0+0c <[^>]*> e328f101 msr CPSR_f, #1073741824 ; 0x40000000
-0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 ; 0x20000000
-0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 ; 0x10000000
+0+0c <[^>]*> e328f101 msr CPSR_f, #1073741824 @ 0x40000000
+0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 @ 0x20000000
+0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 @ 0x10000000
0+18 <[^>]*> e128f004 msr CPSR_f, r4
0+1c <[^>]*> e128f005 msr CPSR_f, r5
0+20 <[^>]*> e169f006 msr SPSR_fc, r6
diff --git a/gas/testsuite/gas/arm/mrs-msr-arm-v7-a.d b/gas/testsuite/gas/arm/mrs-msr-arm-v7-a.d
index 62d93492b3e..3b7395e307c 100644
--- a/gas/testsuite/gas/arm/mrs-msr-arm-v7-a.d
+++ b/gas/testsuite/gas/arm/mrs-msr-arm-v7-a.d
@@ -8,9 +8,9 @@ Disassembly of section .text:
0+00 <[^>]*> e10f4000 mrs r4, CPSR
0+04 <[^>]*> e10f5000 mrs r5, CPSR
0+08 <[^>]*> e14f6000 mrs r6, SPSR
-0+0c <[^>]*> e32cf101 msr CPSR_fs, #1073741824 ; 0x40000000
-0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 ; 0x20000000
-0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 ; 0x10000000
+0+0c <[^>]*> e32cf101 msr CPSR_fs, #1073741824 @ 0x40000000
+0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 @ 0x20000000
+0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 @ 0x10000000
0+18 <[^>]*> e128f004 msr CPSR_f, r4
0+1c <[^>]*> e128f005 msr CPSR_f, r5
0+20 <[^>]*> e169f006 msr SPSR_fc, r6
diff --git a/gas/testsuite/gas/arm/msr-imm.d b/gas/testsuite/gas/arm/msr-imm.d
index 729720d66f4..2123522ce60 100644
--- a/gas/testsuite/gas/arm/msr-imm.d
+++ b/gas/testsuite/gas/arm/msr-imm.d
@@ -5,137 +5,137 @@
.*: +file format .*arm.*
Disassembly of section .text:
-00000000 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
-00000004 <[^>]*> e324f113 msr CPSR_s, #-1073741820 ; 0xc0000004
-00000008 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
-0000000c <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004
-00000010 <[^>]*> e329f113 msr CPSR_fc, #-1073741820 ; 0xc0000004
-00000014 <[^>]*> e324f113 msr CPSR_s, #-1073741820 ; 0xc0000004
-00000018 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
-0000001c <[^>]*> e321f113 msr CPSR_c, #-1073741820 ; 0xc0000004
-00000020 <[^>]*> e322f113 msr CPSR_x, #-1073741820 ; 0xc0000004
-00000024 <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004
-00000028 <[^>]*> e32af113 msr CPSR_fx, #-1073741820 ; 0xc0000004
-0000002c <[^>]*> e329f113 msr CPSR_fc, #-1073741820 ; 0xc0000004
-00000030 <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004
-00000034 <[^>]*> e326f113 msr CPSR_sx, #-1073741820 ; 0xc0000004
-00000038 <[^>]*> e325f113 msr CPSR_sc, #-1073741820 ; 0xc0000004
-0000003c <[^>]*> e32af113 msr CPSR_fx, #-1073741820 ; 0xc0000004
-00000040 <[^>]*> e326f113 msr CPSR_sx, #-1073741820 ; 0xc0000004
-00000044 <[^>]*> e323f113 msr CPSR_xc, #-1073741820 ; 0xc0000004
-00000048 <[^>]*> e329f113 msr CPSR_fc, #-1073741820 ; 0xc0000004
-0000004c <[^>]*> e325f113 msr CPSR_sc, #-1073741820 ; 0xc0000004
-00000050 <[^>]*> e323f113 msr CPSR_xc, #-1073741820 ; 0xc0000004
-00000054 <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004
-00000058 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004
-0000005c <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004
-00000060 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004
-00000064 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004
-00000068 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004
-0000006c <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004
-00000070 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004
-00000074 <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004
-00000078 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004
-0000007c <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004
-00000080 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004
-00000084 <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004
-00000088 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004
-0000008c <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004
-00000090 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004
-00000094 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004
-00000098 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004
-0000009c <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004
-000000a0 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004
-000000a4 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004
-000000a8 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004
-000000ac <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004
-000000b0 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004
-000000b4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000b8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000bc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000c0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000c4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000c8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000cc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000d0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000d4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000d8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000dc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000e0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000e4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000e8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000ec <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000f0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000f4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000f8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000fc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-00000100 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-00000104 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-00000108 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-0000010c <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-00000110 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-00000114 <[^>]*> e369f113 msr SPSR_fc, #-1073741820 ; 0xc0000004
-00000118 <[^>]*> e364f113 msr SPSR_s, #-1073741820 ; 0xc0000004
-0000011c <[^>]*> e368f113 msr SPSR_f, #-1073741820 ; 0xc0000004
-00000120 <[^>]*> e361f113 msr SPSR_c, #-1073741820 ; 0xc0000004
-00000124 <[^>]*> e362f113 msr SPSR_x, #-1073741820 ; 0xc0000004
-00000128 <[^>]*> e36cf113 msr SPSR_fs, #-1073741820 ; 0xc0000004
-0000012c <[^>]*> e36af113 msr SPSR_fx, #-1073741820 ; 0xc0000004
-00000130 <[^>]*> e369f113 msr SPSR_fc, #-1073741820 ; 0xc0000004
-00000134 <[^>]*> e36cf113 msr SPSR_fs, #-1073741820 ; 0xc0000004
-00000138 <[^>]*> e366f113 msr SPSR_sx, #-1073741820 ; 0xc0000004
-0000013c <[^>]*> e365f113 msr SPSR_sc, #-1073741820 ; 0xc0000004
-00000140 <[^>]*> e36af113 msr SPSR_fx, #-1073741820 ; 0xc0000004
-00000144 <[^>]*> e366f113 msr SPSR_sx, #-1073741820 ; 0xc0000004
-00000148 <[^>]*> e363f113 msr SPSR_xc, #-1073741820 ; 0xc0000004
-0000014c <[^>]*> e369f113 msr SPSR_fc, #-1073741820 ; 0xc0000004
-00000150 <[^>]*> e365f113 msr SPSR_sc, #-1073741820 ; 0xc0000004
-00000154 <[^>]*> e363f113 msr SPSR_xc, #-1073741820 ; 0xc0000004
-00000158 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004
-0000015c <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004
-00000160 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004
-00000164 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004
-00000168 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004
-0000016c <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004
-00000170 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004
-00000174 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004
-00000178 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004
-0000017c <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004
-00000180 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004
-00000184 <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004
-00000188 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004
-0000018c <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004
-00000190 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004
-00000194 <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004
-00000198 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004
-0000019c <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004
-000001a0 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004
-000001a4 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004
-000001a8 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004
-000001ac <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004
-000001b0 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004
-000001b4 <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004
-000001b8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001bc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001c0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001c4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001c8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001cc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001d0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001d4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001d8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001dc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001e0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001e4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001e8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001ec <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001f0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001f4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001f8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001fc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-00000200 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-00000204 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-00000208 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-0000020c <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-00000210 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-00000214 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
+00000000 <[^>]*> e328f113 msr CPSR_f, #-1073741820 @ 0xc0000004
+00000004 <[^>]*> e324f113 msr CPSR_s, #-1073741820 @ 0xc0000004
+00000008 <[^>]*> e328f113 msr CPSR_f, #-1073741820 @ 0xc0000004
+0000000c <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 @ 0xc0000004
+00000010 <[^>]*> e329f113 msr CPSR_fc, #-1073741820 @ 0xc0000004
+00000014 <[^>]*> e324f113 msr CPSR_s, #-1073741820 @ 0xc0000004
+00000018 <[^>]*> e328f113 msr CPSR_f, #-1073741820 @ 0xc0000004
+0000001c <[^>]*> e321f113 msr CPSR_c, #-1073741820 @ 0xc0000004
+00000020 <[^>]*> e322f113 msr CPSR_x, #-1073741820 @ 0xc0000004
+00000024 <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 @ 0xc0000004
+00000028 <[^>]*> e32af113 msr CPSR_fx, #-1073741820 @ 0xc0000004
+0000002c <[^>]*> e329f113 msr CPSR_fc, #-1073741820 @ 0xc0000004
+00000030 <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 @ 0xc0000004
+00000034 <[^>]*> e326f113 msr CPSR_sx, #-1073741820 @ 0xc0000004
+00000038 <[^>]*> e325f113 msr CPSR_sc, #-1073741820 @ 0xc0000004
+0000003c <[^>]*> e32af113 msr CPSR_fx, #-1073741820 @ 0xc0000004
+00000040 <[^>]*> e326f113 msr CPSR_sx, #-1073741820 @ 0xc0000004
+00000044 <[^>]*> e323f113 msr CPSR_xc, #-1073741820 @ 0xc0000004
+00000048 <[^>]*> e329f113 msr CPSR_fc, #-1073741820 @ 0xc0000004
+0000004c <[^>]*> e325f113 msr CPSR_sc, #-1073741820 @ 0xc0000004
+00000050 <[^>]*> e323f113 msr CPSR_xc, #-1073741820 @ 0xc0000004
+00000054 <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 @ 0xc0000004
+00000058 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 @ 0xc0000004
+0000005c <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 @ 0xc0000004
+00000060 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 @ 0xc0000004
+00000064 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 @ 0xc0000004
+00000068 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 @ 0xc0000004
+0000006c <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 @ 0xc0000004
+00000070 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 @ 0xc0000004
+00000074 <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 @ 0xc0000004
+00000078 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 @ 0xc0000004
+0000007c <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 @ 0xc0000004
+00000080 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 @ 0xc0000004
+00000084 <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 @ 0xc0000004
+00000088 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 @ 0xc0000004
+0000008c <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 @ 0xc0000004
+00000090 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 @ 0xc0000004
+00000094 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 @ 0xc0000004
+00000098 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 @ 0xc0000004
+0000009c <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 @ 0xc0000004
+000000a0 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 @ 0xc0000004
+000000a4 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 @ 0xc0000004
+000000a8 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 @ 0xc0000004
+000000ac <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 @ 0xc0000004
+000000b0 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 @ 0xc0000004
+000000b4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000b8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000bc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000c0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000c4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000c8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000cc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000d0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000d4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000d8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000dc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000e0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000e4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000e8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000ec <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000f0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000f4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000f8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000fc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+00000100 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+00000104 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+00000108 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+0000010c <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+00000110 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+00000114 <[^>]*> e369f113 msr SPSR_fc, #-1073741820 @ 0xc0000004
+00000118 <[^>]*> e364f113 msr SPSR_s, #-1073741820 @ 0xc0000004
+0000011c <[^>]*> e368f113 msr SPSR_f, #-1073741820 @ 0xc0000004
+00000120 <[^>]*> e361f113 msr SPSR_c, #-1073741820 @ 0xc0000004
+00000124 <[^>]*> e362f113 msr SPSR_x, #-1073741820 @ 0xc0000004
+00000128 <[^>]*> e36cf113 msr SPSR_fs, #-1073741820 @ 0xc0000004
+0000012c <[^>]*> e36af113 msr SPSR_fx, #-1073741820 @ 0xc0000004
+00000130 <[^>]*> e369f113 msr SPSR_fc, #-1073741820 @ 0xc0000004
+00000134 <[^>]*> e36cf113 msr SPSR_fs, #-1073741820 @ 0xc0000004
+00000138 <[^>]*> e366f113 msr SPSR_sx, #-1073741820 @ 0xc0000004
+0000013c <[^>]*> e365f113 msr SPSR_sc, #-1073741820 @ 0xc0000004
+00000140 <[^>]*> e36af113 msr SPSR_fx, #-1073741820 @ 0xc0000004
+00000144 <[^>]*> e366f113 msr SPSR_sx, #-1073741820 @ 0xc0000004
+00000148 <[^>]*> e363f113 msr SPSR_xc, #-1073741820 @ 0xc0000004
+0000014c <[^>]*> e369f113 msr SPSR_fc, #-1073741820 @ 0xc0000004
+00000150 <[^>]*> e365f113 msr SPSR_sc, #-1073741820 @ 0xc0000004
+00000154 <[^>]*> e363f113 msr SPSR_xc, #-1073741820 @ 0xc0000004
+00000158 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 @ 0xc0000004
+0000015c <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 @ 0xc0000004
+00000160 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 @ 0xc0000004
+00000164 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 @ 0xc0000004
+00000168 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 @ 0xc0000004
+0000016c <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 @ 0xc0000004
+00000170 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 @ 0xc0000004
+00000174 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 @ 0xc0000004
+00000178 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 @ 0xc0000004
+0000017c <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 @ 0xc0000004
+00000180 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 @ 0xc0000004
+00000184 <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 @ 0xc0000004
+00000188 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 @ 0xc0000004
+0000018c <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 @ 0xc0000004
+00000190 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 @ 0xc0000004
+00000194 <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 @ 0xc0000004
+00000198 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 @ 0xc0000004
+0000019c <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 @ 0xc0000004
+000001a0 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 @ 0xc0000004
+000001a4 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 @ 0xc0000004
+000001a8 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 @ 0xc0000004
+000001ac <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 @ 0xc0000004
+000001b0 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 @ 0xc0000004
+000001b4 <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 @ 0xc0000004
+000001b8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001bc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001c0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001c4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001c8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001cc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001d0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001d4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001d8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001dc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001e0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001e4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001e8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001ec <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001f0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001f4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001f8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001fc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+00000200 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+00000204 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+00000208 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+0000020c <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+00000210 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+00000214 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
diff --git a/gas/testsuite/gas/arm/mve-vand.d b/gas/testsuite/gas/arm/mve-vand.d
index 792b576a27c..e3399476bf9 100644
--- a/gas/testsuite/gas/arm/mve-vand.d
+++ b/gas/testsuite/gas/arm/mve-vand.d
@@ -1380,53 +1380,53 @@ Disassembly of section .text:
[^>]*> ef0e e154 vand q7, q7, q2
[^>]*> ef0e e158 vand q7, q7, q4
[^>]*> ef0e e15e vand q7, q7, q7
-[^>]*> ef80 0170 vbic.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0170 vbic.i32 q0, #0 ; 0x00000000
-[^>]*> ff87 017f vbic.i32 q0, #255 ; 0x000000ff
-[^>]*> ff87 037f vbic.i32 q0, #65280 ; 0x0000ff00
-[^>]*> ff87 057f vbic.i32 q0, #16711680 ; 0x00ff0000
-[^>]*> ff87 077f vbic.i32 q0, #4278190080 ; 0xff000000
-[^>]*> ef80 0970 vbic.i16 q0, #0 ; 0x0000
-[^>]*> ff87 0b7f vbic.i16 q0, #65280 ; 0xff00
-[^>]*> ff87 097f vbic.i16 q0, #255 ; 0x00ff
-[^>]*> ef80 2170 vbic.i32 q1, #0 ; 0x00000000
-[^>]*> ef80 2170 vbic.i32 q1, #0 ; 0x00000000
-[^>]*> ff87 217f vbic.i32 q1, #255 ; 0x000000ff
-[^>]*> ff87 237f vbic.i32 q1, #65280 ; 0x0000ff00
-[^>]*> ff87 257f vbic.i32 q1, #16711680 ; 0x00ff0000
-[^>]*> ff87 277f vbic.i32 q1, #4278190080 ; 0xff000000
-[^>]*> ef80 2970 vbic.i16 q1, #0 ; 0x0000
-[^>]*> ff87 2b7f vbic.i16 q1, #65280 ; 0xff00
-[^>]*> ff87 297f vbic.i16 q1, #255 ; 0x00ff
-[^>]*> ef80 4170 vbic.i32 q2, #0 ; 0x00000000
-[^>]*> ef80 4170 vbic.i32 q2, #0 ; 0x00000000
-[^>]*> ff87 417f vbic.i32 q2, #255 ; 0x000000ff
-[^>]*> ff87 437f vbic.i32 q2, #65280 ; 0x0000ff00
-[^>]*> ff87 457f vbic.i32 q2, #16711680 ; 0x00ff0000
-[^>]*> ff87 477f vbic.i32 q2, #4278190080 ; 0xff000000
-[^>]*> ef80 4970 vbic.i16 q2, #0 ; 0x0000
-[^>]*> ff87 4b7f vbic.i16 q2, #65280 ; 0xff00
-[^>]*> ff87 497f vbic.i16 q2, #255 ; 0x00ff
-[^>]*> ef80 8170 vbic.i32 q4, #0 ; 0x00000000
-[^>]*> ef80 8170 vbic.i32 q4, #0 ; 0x00000000
-[^>]*> ff87 817f vbic.i32 q4, #255 ; 0x000000ff
-[^>]*> ff87 837f vbic.i32 q4, #65280 ; 0x0000ff00
-[^>]*> ff87 857f vbic.i32 q4, #16711680 ; 0x00ff0000
-[^>]*> ff87 877f vbic.i32 q4, #4278190080 ; 0xff000000
-[^>]*> ef80 8970 vbic.i16 q4, #0 ; 0x0000
-[^>]*> ff87 8b7f vbic.i16 q4, #65280 ; 0xff00
-[^>]*> ff87 897f vbic.i16 q4, #255 ; 0x00ff
-[^>]*> ef80 e170 vbic.i32 q7, #0 ; 0x00000000
-[^>]*> ef80 e170 vbic.i32 q7, #0 ; 0x00000000
-[^>]*> ff87 e17f vbic.i32 q7, #255 ; 0x000000ff
-[^>]*> ff87 e37f vbic.i32 q7, #65280 ; 0x0000ff00
-[^>]*> ff87 e57f vbic.i32 q7, #16711680 ; 0x00ff0000
-[^>]*> ff87 e77f vbic.i32 q7, #4278190080 ; 0xff000000
-[^>]*> ef80 e970 vbic.i16 q7, #0 ; 0x0000
-[^>]*> ff87 eb7f vbic.i16 q7, #65280 ; 0xff00
-[^>]*> ff87 e97f vbic.i16 q7, #255 ; 0x00ff
+[^>]*> ef80 0170 vbic.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0170 vbic.i32 q0, #0 @ 0x00000000
+[^>]*> ff87 017f vbic.i32 q0, #255 @ 0x000000ff
+[^>]*> ff87 037f vbic.i32 q0, #65280 @ 0x0000ff00
+[^>]*> ff87 057f vbic.i32 q0, #16711680 @ 0x00ff0000
+[^>]*> ff87 077f vbic.i32 q0, #4278190080 @ 0xff000000
+[^>]*> ef80 0970 vbic.i16 q0, #0 @ 0x0000
+[^>]*> ff87 0b7f vbic.i16 q0, #65280 @ 0xff00
+[^>]*> ff87 097f vbic.i16 q0, #255 @ 0x00ff
+[^>]*> ef80 2170 vbic.i32 q1, #0 @ 0x00000000
+[^>]*> ef80 2170 vbic.i32 q1, #0 @ 0x00000000
+[^>]*> ff87 217f vbic.i32 q1, #255 @ 0x000000ff
+[^>]*> ff87 237f vbic.i32 q1, #65280 @ 0x0000ff00
+[^>]*> ff87 257f vbic.i32 q1, #16711680 @ 0x00ff0000
+[^>]*> ff87 277f vbic.i32 q1, #4278190080 @ 0xff000000
+[^>]*> ef80 2970 vbic.i16 q1, #0 @ 0x0000
+[^>]*> ff87 2b7f vbic.i16 q1, #65280 @ 0xff00
+[^>]*> ff87 297f vbic.i16 q1, #255 @ 0x00ff
+[^>]*> ef80 4170 vbic.i32 q2, #0 @ 0x00000000
+[^>]*> ef80 4170 vbic.i32 q2, #0 @ 0x00000000
+[^>]*> ff87 417f vbic.i32 q2, #255 @ 0x000000ff
+[^>]*> ff87 437f vbic.i32 q2, #65280 @ 0x0000ff00
+[^>]*> ff87 457f vbic.i32 q2, #16711680 @ 0x00ff0000
+[^>]*> ff87 477f vbic.i32 q2, #4278190080 @ 0xff000000
+[^>]*> ef80 4970 vbic.i16 q2, #0 @ 0x0000
+[^>]*> ff87 4b7f vbic.i16 q2, #65280 @ 0xff00
+[^>]*> ff87 497f vbic.i16 q2, #255 @ 0x00ff
+[^>]*> ef80 8170 vbic.i32 q4, #0 @ 0x00000000
+[^>]*> ef80 8170 vbic.i32 q4, #0 @ 0x00000000
+[^>]*> ff87 817f vbic.i32 q4, #255 @ 0x000000ff
+[^>]*> ff87 837f vbic.i32 q4, #65280 @ 0x0000ff00
+[^>]*> ff87 857f vbic.i32 q4, #16711680 @ 0x00ff0000
+[^>]*> ff87 877f vbic.i32 q4, #4278190080 @ 0xff000000
+[^>]*> ef80 8970 vbic.i16 q4, #0 @ 0x0000
+[^>]*> ff87 8b7f vbic.i16 q4, #65280 @ 0xff00
+[^>]*> ff87 897f vbic.i16 q4, #255 @ 0x00ff
+[^>]*> ef80 e170 vbic.i32 q7, #0 @ 0x00000000
+[^>]*> ef80 e170 vbic.i32 q7, #0 @ 0x00000000
+[^>]*> ff87 e17f vbic.i32 q7, #255 @ 0x000000ff
+[^>]*> ff87 e37f vbic.i32 q7, #65280 @ 0x0000ff00
+[^>]*> ff87 e57f vbic.i32 q7, #16711680 @ 0x00ff0000
+[^>]*> ff87 e77f vbic.i32 q7, #4278190080 @ 0xff000000
+[^>]*> ef80 e970 vbic.i16 q7, #0 @ 0x0000
+[^>]*> ff87 eb7f vbic.i16 q7, #65280 @ 0xff00
+[^>]*> ff87 e97f vbic.i16 q7, #255 @ 0x00ff
[^>]*> fe71 ef4d vpstete
[^>]*> ef02 0154 vandt q0, q1, q2
[^>]*> ef02 0154 vande q0, q1, q2
-[^>]*> ef80 0170 vbict.i32 q0, #0 ; 0x00000000
-[^>]*> ff87 097f vbice.i16 q0, #255 ; 0x00ff
+[^>]*> ef80 0170 vbict.i32 q0, #0 @ 0x00000000
+[^>]*> ff87 097f vbice.i16 q0, #255 @ 0x00ff
diff --git a/gas/testsuite/gas/arm/mve-vbic.d b/gas/testsuite/gas/arm/mve-vbic.d
index f51fecba88f..beae05157ef 100644
--- a/gas/testsuite/gas/arm/mve-vbic.d
+++ b/gas/testsuite/gas/arm/mve-vbic.d
@@ -1005,16 +1005,16 @@ Disassembly of section .text:
[^>]*> ef1e e15e vbic q7, q7, q7
[^>]*> ef1e e15e vbic q7, q7, q7
[^>]*> ef1e e15e vbic q7, q7, q7
-[^>]*> ef80 0170 vbic.i32 q0, #0 ; 0x00000000
-[^>]*> ff87 017f vbic.i32 q0, #255 ; 0x000000ff
-[^>]*> ff87 037f vbic.i32 q0, #65280 ; 0x0000ff00
-[^>]*> ff87 077f vbic.i32 q0, #4278190080 ; 0xff000000
-[^>]*> ff87 057f vbic.i32 q0, #16711680 ; 0x00ff0000
-[^>]*> ef80 0970 vbic.i16 q0, #0 ; 0x0000
-[^>]*> ff87 097f vbic.i16 q0, #255 ; 0x00ff
-[^>]*> ff87 0b7f vbic.i16 q0, #65280 ; 0xff00
+[^>]*> ef80 0170 vbic.i32 q0, #0 @ 0x00000000
+[^>]*> ff87 017f vbic.i32 q0, #255 @ 0x000000ff
+[^>]*> ff87 037f vbic.i32 q0, #65280 @ 0x0000ff00
+[^>]*> ff87 077f vbic.i32 q0, #4278190080 @ 0xff000000
+[^>]*> ff87 057f vbic.i32 q0, #16711680 @ 0x00ff0000
+[^>]*> ef80 0970 vbic.i16 q0, #0 @ 0x0000
+[^>]*> ff87 097f vbic.i16 q0, #255 @ 0x00ff
+[^>]*> ff87 0b7f vbic.i16 q0, #65280 @ 0xff00
[^>]*> fe71 ef4d vpstete
[^>]*> ef12 0154 vbict q0, q1, q2
[^>]*> ef12 0154 vbice q0, q1, q2
-[^>]*> ef80 0170 vbict.i32 q0, #0 ; 0x00000000
-[^>]*> ff87 0b7f vbice.i16 q0, #65280 ; 0xff00
+[^>]*> ef80 0170 vbict.i32 q0, #0 @ 0x00000000
+[^>]*> ff87 0b7f vbice.i16 q0, #65280 @ 0xff00
diff --git a/gas/testsuite/gas/arm/mve-vcvt-3.d b/gas/testsuite/gas/arm/mve-vcvt-3.d
index 0b50b2f8389..6a2a1ffa944 100644
--- a/gas/testsuite/gas/arm/mve-vcvt-3.d
+++ b/gas/testsuite/gas/arm/mve-vcvt-3.d
@@ -11,100 +11,100 @@ Disassembly of section .text:
[^>]*> ee3f 0e05 vcvtb.f16.f32 q0, q2
[^>]*> ee3f 1e09 vcvtt.f16.f32 q0, q4
[^>]*> ee3f 0e09 vcvtb.f16.f32 q0, q4
-[^>]*> ee3f 1e11 ; <UNDEFINED> instruction: 0xee3f1e11
-[^>]*> ee3f 0e11 ; <UNDEFINED> instruction: 0xee3f0e11
-[^>]*> ee3f 1e1d ; <UNDEFINED> instruction: 0xee3f1e1d
-[^>]*> ee3f 0e1d ; <UNDEFINED> instruction: 0xee3f0e1d
+[^>]*> ee3f 1e11 @ <UNDEFINED> instruction: 0xee3f1e11
+[^>]*> ee3f 0e11 @ <UNDEFINED> instruction: 0xee3f0e11
+[^>]*> ee3f 1e1d @ <UNDEFINED> instruction: 0xee3f1e1d
+[^>]*> ee3f 0e1d @ <UNDEFINED> instruction: 0xee3f0e1d
[^>]*> ee3f 5e01 vcvtt.f16.f32 q2, q0
[^>]*> ee3f 4e01 vcvtb.f16.f32 q2, q0
[^>]*> ee3f 5e05 vcvtt.f16.f32 q2, q2
[^>]*> ee3f 4e05 vcvtb.f16.f32 q2, q2
[^>]*> ee3f 5e09 vcvtt.f16.f32 q2, q4
[^>]*> ee3f 4e09 vcvtb.f16.f32 q2, q4
-[^>]*> ee3f 5e11 ; <UNDEFINED> instruction: 0xee3f5e11
-[^>]*> ee3f 4e11 ; <UNDEFINED> instruction: 0xee3f4e11
-[^>]*> ee3f 5e1d ; <UNDEFINED> instruction: 0xee3f5e1d
-[^>]*> ee3f 4e1d ; <UNDEFINED> instruction: 0xee3f4e1d
+[^>]*> ee3f 5e11 @ <UNDEFINED> instruction: 0xee3f5e11
+[^>]*> ee3f 4e11 @ <UNDEFINED> instruction: 0xee3f4e11
+[^>]*> ee3f 5e1d @ <UNDEFINED> instruction: 0xee3f5e1d
+[^>]*> ee3f 4e1d @ <UNDEFINED> instruction: 0xee3f4e1d
[^>]*> ee3f 9e01 vcvtt.f16.f32 q4, q0
[^>]*> ee3f 8e01 vcvtb.f16.f32 q4, q0
[^>]*> ee3f 9e05 vcvtt.f16.f32 q4, q2
[^>]*> ee3f 8e05 vcvtb.f16.f32 q4, q2
[^>]*> ee3f 9e09 vcvtt.f16.f32 q4, q4
[^>]*> ee3f 8e09 vcvtb.f16.f32 q4, q4
-[^>]*> ee3f 9e11 ; <UNDEFINED> instruction: 0xee3f9e11
-[^>]*> ee3f 8e11 ; <UNDEFINED> instruction: 0xee3f8e11
-[^>]*> ee3f 9e1d ; <UNDEFINED> instruction: 0xee3f9e1d
-[^>]*> ee3f 8e1d ; <UNDEFINED> instruction: 0xee3f8e1d
+[^>]*> ee3f 9e11 @ <UNDEFINED> instruction: 0xee3f9e11
+[^>]*> ee3f 8e11 @ <UNDEFINED> instruction: 0xee3f8e11
+[^>]*> ee3f 9e1d @ <UNDEFINED> instruction: 0xee3f9e1d
+[^>]*> ee3f 8e1d @ <UNDEFINED> instruction: 0xee3f8e1d
[^>]*> ee3f 1e01 vcvtt.f16.f32 q0, q0
[^>]*> ee3f 0e01 vcvtb.f16.f32 q0, q0
[^>]*> ee3f 1e05 vcvtt.f16.f32 q0, q2
[^>]*> ee3f 0e05 vcvtb.f16.f32 q0, q2
[^>]*> ee3f 1e09 vcvtt.f16.f32 q0, q4
[^>]*> ee3f 0e09 vcvtb.f16.f32 q0, q4
-[^>]*> ee3f 1e11 ; <UNDEFINED> instruction: 0xee3f1e11
-[^>]*> ee3f 0e11 ; <UNDEFINED> instruction: 0xee3f0e11
-[^>]*> ee3f 1e1d ; <UNDEFINED> instruction: 0xee3f1e1d
-[^>]*> ee3f 0e1d ; <UNDEFINED> instruction: 0xee3f0e1d
+[^>]*> ee3f 1e11 @ <UNDEFINED> instruction: 0xee3f1e11
+[^>]*> ee3f 0e11 @ <UNDEFINED> instruction: 0xee3f0e11
+[^>]*> ee3f 1e1d @ <UNDEFINED> instruction: 0xee3f1e1d
+[^>]*> ee3f 0e1d @ <UNDEFINED> instruction: 0xee3f0e1d
[^>]*> ee3f de01 vcvtt.f16.f32 q6, q0
[^>]*> ee3f ce01 vcvtb.f16.f32 q6, q0
[^>]*> ee3f de05 vcvtt.f16.f32 q6, q2
[^>]*> ee3f ce05 vcvtb.f16.f32 q6, q2
[^>]*> ee3f de09 vcvtt.f16.f32 q6, q4
[^>]*> ee3f ce09 vcvtb.f16.f32 q6, q4
-[^>]*> ee3f de11 ; <UNDEFINED> instruction: 0xee3fde11
-[^>]*> ee3f ce11 ; <UNDEFINED> instruction: 0xee3fce11
-[^>]*> ee3f de1d ; <UNDEFINED> instruction: 0xee3fde1d
-[^>]*> ee3f ce1d ; <UNDEFINED> instruction: 0xee3fce1d
+[^>]*> ee3f de11 @ <UNDEFINED> instruction: 0xee3fde11
+[^>]*> ee3f ce11 @ <UNDEFINED> instruction: 0xee3fce11
+[^>]*> ee3f de1d @ <UNDEFINED> instruction: 0xee3fde1d
+[^>]*> ee3f ce1d @ <UNDEFINED> instruction: 0xee3fce1d
[^>]*> fe3f 1e01 vcvtt.f32.f16 q0, q0
[^>]*> fe3f 0e01 vcvtb.f32.f16 q0, q0
[^>]*> fe3f 1e05 vcvtt.f32.f16 q0, q2
[^>]*> fe3f 0e05 vcvtb.f32.f16 q0, q2
[^>]*> fe3f 1e09 vcvtt.f32.f16 q0, q4
[^>]*> fe3f 0e09 vcvtb.f32.f16 q0, q4
-[^>]*> fe3f 1e11 ; <UNDEFINED> instruction: 0xfe3f1e11
-[^>]*> fe3f 0e11 ; <UNDEFINED> instruction: 0xfe3f0e11
-[^>]*> fe3f 1e1d ; <UNDEFINED> instruction: 0xfe3f1e1d
-[^>]*> fe3f 0e1d ; <UNDEFINED> instruction: 0xfe3f0e1d
+[^>]*> fe3f 1e11 @ <UNDEFINED> instruction: 0xfe3f1e11
+[^>]*> fe3f 0e11 @ <UNDEFINED> instruction: 0xfe3f0e11
+[^>]*> fe3f 1e1d @ <UNDEFINED> instruction: 0xfe3f1e1d
+[^>]*> fe3f 0e1d @ <UNDEFINED> instruction: 0xfe3f0e1d
[^>]*> fe3f 5e01 vcvtt.f32.f16 q2, q0
[^>]*> fe3f 4e01 vcvtb.f32.f16 q2, q0
[^>]*> fe3f 5e05 vcvtt.f32.f16 q2, q2
[^>]*> fe3f 4e05 vcvtb.f32.f16 q2, q2
[^>]*> fe3f 5e09 vcvtt.f32.f16 q2, q4
[^>]*> fe3f 4e09 vcvtb.f32.f16 q2, q4
-[^>]*> fe3f 5e11 ; <UNDEFINED> instruction: 0xfe3f5e11
-[^>]*> fe3f 4e11 ; <UNDEFINED> instruction: 0xfe3f4e11
-[^>]*> fe3f 5e1d ; <UNDEFINED> instruction: 0xfe3f5e1d
-[^>]*> fe3f 4e1d ; <UNDEFINED> instruction: 0xfe3f4e1d
+[^>]*> fe3f 5e11 @ <UNDEFINED> instruction: 0xfe3f5e11
+[^>]*> fe3f 4e11 @ <UNDEFINED> instruction: 0xfe3f4e11
+[^>]*> fe3f 5e1d @ <UNDEFINED> instruction: 0xfe3f5e1d
+[^>]*> fe3f 4e1d @ <UNDEFINED> instruction: 0xfe3f4e1d
[^>]*> fe3f 9e01 vcvtt.f32.f16 q4, q0
[^>]*> fe3f 8e01 vcvtb.f32.f16 q4, q0
[^>]*> fe3f 9e05 vcvtt.f32.f16 q4, q2
[^>]*> fe3f 8e05 vcvtb.f32.f16 q4, q2
[^>]*> fe3f 9e09 vcvtt.f32.f16 q4, q4
[^>]*> fe3f 8e09 vcvtb.f32.f16 q4, q4
-[^>]*> fe3f 9e11 ; <UNDEFINED> instruction: 0xfe3f9e11
-[^>]*> fe3f 8e11 ; <UNDEFINED> instruction: 0xfe3f8e11
-[^>]*> fe3f 9e1d ; <UNDEFINED> instruction: 0xfe3f9e1d
-[^>]*> fe3f 8e1d ; <UNDEFINED> instruction: 0xfe3f8e1d
+[^>]*> fe3f 9e11 @ <UNDEFINED> instruction: 0xfe3f9e11
+[^>]*> fe3f 8e11 @ <UNDEFINED> instruction: 0xfe3f8e11
+[^>]*> fe3f 9e1d @ <UNDEFINED> instruction: 0xfe3f9e1d
+[^>]*> fe3f 8e1d @ <UNDEFINED> instruction: 0xfe3f8e1d
[^>]*> fe3f 1e01 vcvtt.f32.f16 q0, q0
[^>]*> fe3f 0e01 vcvtb.f32.f16 q0, q0
[^>]*> fe3f 1e05 vcvtt.f32.f16 q0, q2
[^>]*> fe3f 0e05 vcvtb.f32.f16 q0, q2
[^>]*> fe3f 1e09 vcvtt.f32.f16 q0, q4
[^>]*> fe3f 0e09 vcvtb.f32.f16 q0, q4
-[^>]*> fe3f 1e11 ; <UNDEFINED> instruction: 0xfe3f1e11
-[^>]*> fe3f 0e11 ; <UNDEFINED> instruction: 0xfe3f0e11
-[^>]*> fe3f 1e1d ; <UNDEFINED> instruction: 0xfe3f1e1d
-[^>]*> fe3f 0e1d ; <UNDEFINED> instruction: 0xfe3f0e1d
+[^>]*> fe3f 1e11 @ <UNDEFINED> instruction: 0xfe3f1e11
+[^>]*> fe3f 0e11 @ <UNDEFINED> instruction: 0xfe3f0e11
+[^>]*> fe3f 1e1d @ <UNDEFINED> instruction: 0xfe3f1e1d
+[^>]*> fe3f 0e1d @ <UNDEFINED> instruction: 0xfe3f0e1d
[^>]*> fe3f de01 vcvtt.f32.f16 q6, q0
[^>]*> fe3f ce01 vcvtb.f32.f16 q6, q0
[^>]*> fe3f de05 vcvtt.f32.f16 q6, q2
[^>]*> fe3f ce05 vcvtb.f32.f16 q6, q2
[^>]*> fe3f de09 vcvtt.f32.f16 q6, q4
[^>]*> fe3f ce09 vcvtb.f32.f16 q6, q4
-[^>]*> fe3f de11 ; <UNDEFINED> instruction: 0xfe3fde11
-[^>]*> fe3f ce11 ; <UNDEFINED> instruction: 0xfe3fce11
-[^>]*> fe3f de1d ; <UNDEFINED> instruction: 0xfe3fde1d
-[^>]*> fe3f ce1d ; <UNDEFINED> instruction: 0xfe3fce1d
+[^>]*> fe3f de11 @ <UNDEFINED> instruction: 0xfe3fde11
+[^>]*> fe3f ce11 @ <UNDEFINED> instruction: 0xfe3fce11
+[^>]*> fe3f de1d @ <UNDEFINED> instruction: 0xfe3fde1d
+[^>]*> fe3f ce1d @ <UNDEFINED> instruction: 0xfe3fce1d
[^>]*> fe31 af4d vpsttee
[^>]*> ee3f 1e05 vcvttt.f16.f32 q0, q2
[^>]*> ee3f 0e05 vcvtbt.f16.f32 q0, q2
diff --git a/gas/testsuite/gas/arm/mve-vmov-1.d b/gas/testsuite/gas/arm/mve-vmov-1.d
index de8dabe79b2..76be5f3e586 100644
--- a/gas/testsuite/gas/arm/mve-vmov-1.d
+++ b/gas/testsuite/gas/arm/mve-vmov-1.d
@@ -4136,16 +4136,16 @@ Disassembly of section .text:
[^>]*> ee35 eb10 vmov.32 lr, d5\[1\]
[^>]*> ee39 eb10 vmov.32 lr, d9\[1\]
[^>]*> ee3f eb10 vmov.32 lr, d15\[1\]
-[^>]*> ef80 0050 vmov.i32 q0, #0 ; 0x00000000
-[^>]*> ff87 005f vmov.i32 q0, #255 ; 0x000000ff
-[^>]*> ff87 025f vmov.i32 q0, #65280 ; 0x0000ff00
-[^>]*> ff87 065f vmov.i32 q0, #4278190080 ; 0xff000000
-[^>]*> ff87 045f vmov.i32 q0, #16711680 ; 0x00ff0000
-[^>]*> ef80 0850 vmov.i16 q0, #0 ; 0x0000
-[^>]*> ff87 085f vmov.i16 q0, #255 ; 0x00ff
-[^>]*> ff87 0a5f vmov.i16 q0, #65280 ; 0xff00
-[^>]*> ef80 0e50 vmov.i8 q0, #0 ; 0x00
-[^>]*> ff87 0e5f vmov.i8 q0, #255 ; 0xff
+[^>]*> ef80 0050 vmov.i32 q0, #0 @ 0x00000000
+[^>]*> ff87 005f vmov.i32 q0, #255 @ 0x000000ff
+[^>]*> ff87 025f vmov.i32 q0, #65280 @ 0x0000ff00
+[^>]*> ff87 065f vmov.i32 q0, #4278190080 @ 0xff000000
+[^>]*> ff87 045f vmov.i32 q0, #16711680 @ 0x00ff0000
+[^>]*> ef80 0850 vmov.i16 q0, #0 @ 0x0000
+[^>]*> ff87 085f vmov.i16 q0, #255 @ 0x00ff
+[^>]*> ff87 0a5f vmov.i16 q0, #65280 @ 0xff00
+[^>]*> ef80 0e50 vmov.i8 q0, #0 @ 0x00
+[^>]*> ff87 0e5f vmov.i8 q0, #255 @ 0xff
[^>]*> ff80 0e70 vmov.i64 q0, #0xff00000000000000
[^>]*> ef84 0e70 vmov.i64 q0, #0x00ff000000000000
[^>]*> ef82 0e70 vmov.i64 q0, #0x0000ff0000000000
diff --git a/gas/testsuite/gas/arm/mve-vmov-2.d b/gas/testsuite/gas/arm/mve-vmov-2.d
index c1133aa95e0..5a63c792ac7 100644
--- a/gas/testsuite/gas/arm/mve-vmov-2.d
+++ b/gas/testsuite/gas/arm/mve-vmov-2.d
@@ -4136,16 +4136,16 @@ Disassembly of section .text:
[^>]*> ee35 eb10 vmov.32 lr, d5\[1\]
[^>]*> ee39 eb10 vmov.32 lr, d9\[1\]
[^>]*> ee3f eb10 vmov.32 lr, d15\[1\]
-[^>]*> ef80 0050 vmov.i32 q0, #0 ; 0x00000000
-[^>]*> ff87 005f vmov.i32 q0, #255 ; 0x000000ff
-[^>]*> ff87 025f vmov.i32 q0, #65280 ; 0x0000ff00
-[^>]*> ff87 065f vmov.i32 q0, #4278190080 ; 0xff000000
-[^>]*> ff87 045f vmov.i32 q0, #16711680 ; 0x00ff0000
-[^>]*> ef80 0850 vmov.i16 q0, #0 ; 0x0000
-[^>]*> ff87 085f vmov.i16 q0, #255 ; 0x00ff
-[^>]*> ff87 0a5f vmov.i16 q0, #65280 ; 0xff00
-[^>]*> ef80 0e50 vmov.i8 q0, #0 ; 0x00
-[^>]*> ff87 0e5f vmov.i8 q0, #255 ; 0xff
+[^>]*> ef80 0050 vmov.i32 q0, #0 @ 0x00000000
+[^>]*> ff87 005f vmov.i32 q0, #255 @ 0x000000ff
+[^>]*> ff87 025f vmov.i32 q0, #65280 @ 0x0000ff00
+[^>]*> ff87 065f vmov.i32 q0, #4278190080 @ 0xff000000
+[^>]*> ff87 045f vmov.i32 q0, #16711680 @ 0x00ff0000
+[^>]*> ef80 0850 vmov.i16 q0, #0 @ 0x0000
+[^>]*> ff87 085f vmov.i16 q0, #255 @ 0x00ff
+[^>]*> ff87 0a5f vmov.i16 q0, #65280 @ 0xff00
+[^>]*> ef80 0e50 vmov.i8 q0, #0 @ 0x00
+[^>]*> ff87 0e5f vmov.i8 q0, #255 @ 0xff
[^>]*> ff80 0e70 vmov.i64 q0, #0xff00000000000000
[^>]*> ef84 0e70 vmov.i64 q0, #0x00ff000000000000
[^>]*> ef82 0e70 vmov.i64 q0, #0x0000ff0000000000
@@ -4298,10 +4298,10 @@ Disassembly of section .text:
[^>]*> ee1f c990 vmov.f16 ip, s31
[^>]*> ee0f e990 vmov.f16 s31, lr
[^>]*> ee1f e990 vmov.f16 lr, s31
-[^>]*> ef80 0050 vmov.i32 q0, #0 ; 0x00000000
-[^>]*> ff83 0f5f vmov.f32 q0, #-31 ; 0xc1f80000
-[^>]*> ff83 0f5f vmov.f32 q0, #-31 ; 0xc1f80000
-[^>]*> ff87 0f5f vmov.f32 q0, #-1.9375 ; 0xbff80000
-[^>]*> ef87 0f50 vmov.f32 q0, #1 ; 0x3f800000
-[^>]*> eeb0 0900 vmov.f16 s0, #0 ; 0x40000000 2.0
-[^>]*> eeb0 0a04 vmov.f32 s0, #4 ; 0x40200000 2.5
+[^>]*> ef80 0050 vmov.i32 q0, #0 @ 0x00000000
+[^>]*> ff83 0f5f vmov.f32 q0, #-31 @ 0xc1f80000
+[^>]*> ff83 0f5f vmov.f32 q0, #-31 @ 0xc1f80000
+[^>]*> ff87 0f5f vmov.f32 q0, #-1.9375 @ 0xbff80000
+[^>]*> ef87 0f50 vmov.f32 q0, #1 @ 0x3f800000
+[^>]*> eeb0 0900 vmov.f16 s0, #0 @ 0x40000000 2.0
+[^>]*> eeb0 0a04 vmov.f32 s0, #4 @ 0x40200000 2.5
diff --git a/gas/testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.d b/gas/testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.d
index ad2196640ef..edb8006e342 100644
--- a/gas/testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.d
+++ b/gas/testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.d
@@ -6,36 +6,36 @@
.*: +file format .*arm.*
Disassembly of section .text:
-[^>]*> ff80 0d70 vmvn.i32 q0, #8454143 ; 0x0080ffff
-[^>]*> ff80 0f70 ; <UNDEFINED> instruction: 0xff800f70
+[^>]*> ff80 0d70 vmvn.i32 q0, #8454143 @ 0x0080ffff
+[^>]*> ff80 0f70 @ <UNDEFINED> instruction: 0xff800f70
[^>]*> ef80 0e70 vmov.i64 q0, #0x0000000000000000
-[^>]*> ef80 0070 vmvn.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0270 vmvn.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0470 vmvn.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0670 vmvn.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0870 vmvn.i16 q0, #0 ; 0x0000
-[^>]*> ef80 0a70 vmvn.i16 q0, #0 ; 0x0000
-[^>]*> ef80 0c70 vmvn.i32 q0, #255 ; 0x000000ff
-[^>]*> ef80 0150 vorr.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0350 vorr.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0550 vorr.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0950 vorr.i16 q0, #0 ; 0x0000
-[^>]*> ef80 0b50 vorr.i16 q0, #0 ; 0x0000
-[^>]*> ef80 0170 vbic.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0370 vbic.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0570 vbic.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0770 vbic.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0970 vbic.i16 q0, #0 ; 0x0000
-[^>]*> ef80 0b70 vbic.i16 q0, #0 ; 0x0000
-[^>]*> ef80 0050 vmov.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0250 vmov.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0450 vmov.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0650 vmov.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0850 vmov.i16 q0, #0 ; 0x0000
-[^>]*> ef80 0a50 vmov.i16 q0, #0 ; 0x0000
-[^>]*> ef80 0c50 vmov.i32 q0, #255 ; 0x000000ff
-[^>]*> ef80 0e50 vmov.i8 q0, #0 ; 0x00
-[^>]*> ef80 0d50 vmov.i32 q0, #65535 ; 0x0000ffff
-[^>]*> ef80 0f50 vmov.f32 q0, #2 ; 0x40000000
-[^>]*> ff80 0d70 vmvn.i32 q0, #8454143 ; 0x0080ffff
-[^>]*> ff80 0d50 vmov.i32 q0, #8454143 ; 0x0080ffff
+[^>]*> ef80 0070 vmvn.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0270 vmvn.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0470 vmvn.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0670 vmvn.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0870 vmvn.i16 q0, #0 @ 0x0000
+[^>]*> ef80 0a70 vmvn.i16 q0, #0 @ 0x0000
+[^>]*> ef80 0c70 vmvn.i32 q0, #255 @ 0x000000ff
+[^>]*> ef80 0150 vorr.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0350 vorr.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0550 vorr.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0950 vorr.i16 q0, #0 @ 0x0000
+[^>]*> ef80 0b50 vorr.i16 q0, #0 @ 0x0000
+[^>]*> ef80 0170 vbic.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0370 vbic.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0570 vbic.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0770 vbic.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0970 vbic.i16 q0, #0 @ 0x0000
+[^>]*> ef80 0b70 vbic.i16 q0, #0 @ 0x0000
+[^>]*> ef80 0050 vmov.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0250 vmov.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0450 vmov.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0650 vmov.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0850 vmov.i16 q0, #0 @ 0x0000
+[^>]*> ef80 0a50 vmov.i16 q0, #0 @ 0x0000
+[^>]*> ef80 0c50 vmov.i32 q0, #255 @ 0x000000ff
+[^>]*> ef80 0e50 vmov.i8 q0, #0 @ 0x00
+[^>]*> ef80 0d50 vmov.i32 q0, #65535 @ 0x0000ffff
+[^>]*> ef80 0f50 vmov.f32 q0, #2 @ 0x40000000
+[^>]*> ff80 0d70 vmvn.i32 q0, #8454143 @ 0x0080ffff
+[^>]*> ff80 0d50 vmov.i32 q0, #8454143 @ 0x0080ffff
diff --git a/gas/testsuite/gas/arm/mve-vmvn.d b/gas/testsuite/gas/arm/mve-vmvn.d
index 71deaed2528..6efab7346eb 100644
--- a/gas/testsuite/gas/arm/mve-vmvn.d
+++ b/gas/testsuite/gas/arm/mve-vmvn.d
@@ -10,83 +10,83 @@ Disassembly of section .text:
[^>]*> ffb0 05c4 vmvn q0, q2
[^>]*> ffb0 05c8 vmvn q0, q4
[^>]*> ffb0 05ce vmvn q0, q7
-[^>]*> ef80 0070 vmvn.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0870 vmvn.i16 q0, #0 ; 0x0000
-[^>]*> ff87 007f vmvn.i32 q0, #255 ; 0x000000ff
-[^>]*> ff87 027f vmvn.i32 q0, #65280 ; 0x0000ff00
-[^>]*> ff87 047f vmvn.i32 q0, #16711680 ; 0x00ff0000
-[^>]*> ff87 067f vmvn.i32 q0, #4278190080 ; 0xff000000
-[^>]*> ff82 0c7b vmvn.i32 q0, #44031 ; 0x0000abff
-[^>]*> ff87 087f vmvn.i16 q0, #255 ; 0x00ff
-[^>]*> ff87 0a7f vmvn.i16 q0, #65280 ; 0xff00
-[^>]*> ff87 0a5e vmov.i16 q0, #65024 ; 0xfe00
-[^>]*> ef80 0e50 vmov.i8 q0, #0 ; 0x00
+[^>]*> ef80 0070 vmvn.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0870 vmvn.i16 q0, #0 @ 0x0000
+[^>]*> ff87 007f vmvn.i32 q0, #255 @ 0x000000ff
+[^>]*> ff87 027f vmvn.i32 q0, #65280 @ 0x0000ff00
+[^>]*> ff87 047f vmvn.i32 q0, #16711680 @ 0x00ff0000
+[^>]*> ff87 067f vmvn.i32 q0, #4278190080 @ 0xff000000
+[^>]*> ff82 0c7b vmvn.i32 q0, #44031 @ 0x0000abff
+[^>]*> ff87 087f vmvn.i16 q0, #255 @ 0x00ff
+[^>]*> ff87 0a7f vmvn.i16 q0, #65280 @ 0xff00
+[^>]*> ff87 0a5e vmov.i16 q0, #65024 @ 0xfe00
+[^>]*> ef80 0e50 vmov.i8 q0, #0 @ 0x00
[^>]*> ffb0 25c0 vmvn q1, q0
[^>]*> ffb0 25c2 vmvn q1, q1
[^>]*> ffb0 25c4 vmvn q1, q2
[^>]*> ffb0 25c8 vmvn q1, q4
[^>]*> ffb0 25ce vmvn q1, q7
-[^>]*> ef80 2070 vmvn.i32 q1, #0 ; 0x00000000
-[^>]*> ef80 2870 vmvn.i16 q1, #0 ; 0x0000
-[^>]*> ff87 207f vmvn.i32 q1, #255 ; 0x000000ff
-[^>]*> ff87 227f vmvn.i32 q1, #65280 ; 0x0000ff00
-[^>]*> ff87 247f vmvn.i32 q1, #16711680 ; 0x00ff0000
-[^>]*> ff87 267f vmvn.i32 q1, #4278190080 ; 0xff000000
-[^>]*> ff82 2c7b vmvn.i32 q1, #44031 ; 0x0000abff
-[^>]*> ff87 287f vmvn.i16 q1, #255 ; 0x00ff
-[^>]*> ff87 2a7f vmvn.i16 q1, #65280 ; 0xff00
-[^>]*> ff87 2a5e vmov.i16 q1, #65024 ; 0xfe00
-[^>]*> ef80 2e50 vmov.i8 q1, #0 ; 0x00
+[^>]*> ef80 2070 vmvn.i32 q1, #0 @ 0x00000000
+[^>]*> ef80 2870 vmvn.i16 q1, #0 @ 0x0000
+[^>]*> ff87 207f vmvn.i32 q1, #255 @ 0x000000ff
+[^>]*> ff87 227f vmvn.i32 q1, #65280 @ 0x0000ff00
+[^>]*> ff87 247f vmvn.i32 q1, #16711680 @ 0x00ff0000
+[^>]*> ff87 267f vmvn.i32 q1, #4278190080 @ 0xff000000
+[^>]*> ff82 2c7b vmvn.i32 q1, #44031 @ 0x0000abff
+[^>]*> ff87 287f vmvn.i16 q1, #255 @ 0x00ff
+[^>]*> ff87 2a7f vmvn.i16 q1, #65280 @ 0xff00
+[^>]*> ff87 2a5e vmov.i16 q1, #65024 @ 0xfe00
+[^>]*> ef80 2e50 vmov.i8 q1, #0 @ 0x00
[^>]*> ffb0 45c0 vmvn q2, q0
[^>]*> ffb0 45c2 vmvn q2, q1
[^>]*> ffb0 45c4 vmvn q2, q2
[^>]*> ffb0 45c8 vmvn q2, q4
[^>]*> ffb0 45ce vmvn q2, q7
-[^>]*> ef80 4070 vmvn.i32 q2, #0 ; 0x00000000
-[^>]*> ef80 4870 vmvn.i16 q2, #0 ; 0x0000
-[^>]*> ff87 407f vmvn.i32 q2, #255 ; 0x000000ff
-[^>]*> ff87 427f vmvn.i32 q2, #65280 ; 0x0000ff00
-[^>]*> ff87 447f vmvn.i32 q2, #16711680 ; 0x00ff0000
-[^>]*> ff87 467f vmvn.i32 q2, #4278190080 ; 0xff000000
-[^>]*> ff82 4c7b vmvn.i32 q2, #44031 ; 0x0000abff
-[^>]*> ff87 487f vmvn.i16 q2, #255 ; 0x00ff
-[^>]*> ff87 4a7f vmvn.i16 q2, #65280 ; 0xff00
-[^>]*> ff87 4a5e vmov.i16 q2, #65024 ; 0xfe00
-[^>]*> ef80 4e50 vmov.i8 q2, #0 ; 0x00
+[^>]*> ef80 4070 vmvn.i32 q2, #0 @ 0x00000000
+[^>]*> ef80 4870 vmvn.i16 q2, #0 @ 0x0000
+[^>]*> ff87 407f vmvn.i32 q2, #255 @ 0x000000ff
+[^>]*> ff87 427f vmvn.i32 q2, #65280 @ 0x0000ff00
+[^>]*> ff87 447f vmvn.i32 q2, #16711680 @ 0x00ff0000
+[^>]*> ff87 467f vmvn.i32 q2, #4278190080 @ 0xff000000
+[^>]*> ff82 4c7b vmvn.i32 q2, #44031 @ 0x0000abff
+[^>]*> ff87 487f vmvn.i16 q2, #255 @ 0x00ff
+[^>]*> ff87 4a7f vmvn.i16 q2, #65280 @ 0xff00
+[^>]*> ff87 4a5e vmov.i16 q2, #65024 @ 0xfe00
+[^>]*> ef80 4e50 vmov.i8 q2, #0 @ 0x00
[^>]*> ffb0 85c0 vmvn q4, q0
[^>]*> ffb0 85c2 vmvn q4, q1
[^>]*> ffb0 85c4 vmvn q4, q2
[^>]*> ffb0 85c8 vmvn q4, q4
[^>]*> ffb0 85ce vmvn q4, q7
-[^>]*> ef80 8070 vmvn.i32 q4, #0 ; 0x00000000
-[^>]*> ef80 8870 vmvn.i16 q4, #0 ; 0x0000
-[^>]*> ff87 807f vmvn.i32 q4, #255 ; 0x000000ff
-[^>]*> ff87 827f vmvn.i32 q4, #65280 ; 0x0000ff00
-[^>]*> ff87 847f vmvn.i32 q4, #16711680 ; 0x00ff0000
-[^>]*> ff87 867f vmvn.i32 q4, #4278190080 ; 0xff000000
-[^>]*> ff82 8c7b vmvn.i32 q4, #44031 ; 0x0000abff
-[^>]*> ff87 887f vmvn.i16 q4, #255 ; 0x00ff
-[^>]*> ff87 8a7f vmvn.i16 q4, #65280 ; 0xff00
-[^>]*> ff87 8a5e vmov.i16 q4, #65024 ; 0xfe00
-[^>]*> ef80 8e50 vmov.i8 q4, #0 ; 0x00
+[^>]*> ef80 8070 vmvn.i32 q4, #0 @ 0x00000000
+[^>]*> ef80 8870 vmvn.i16 q4, #0 @ 0x0000
+[^>]*> ff87 807f vmvn.i32 q4, #255 @ 0x000000ff
+[^>]*> ff87 827f vmvn.i32 q4, #65280 @ 0x0000ff00
+[^>]*> ff87 847f vmvn.i32 q4, #16711680 @ 0x00ff0000
+[^>]*> ff87 867f vmvn.i32 q4, #4278190080 @ 0xff000000
+[^>]*> ff82 8c7b vmvn.i32 q4, #44031 @ 0x0000abff
+[^>]*> ff87 887f vmvn.i16 q4, #255 @ 0x00ff
+[^>]*> ff87 8a7f vmvn.i16 q4, #65280 @ 0xff00
+[^>]*> ff87 8a5e vmov.i16 q4, #65024 @ 0xfe00
+[^>]*> ef80 8e50 vmov.i8 q4, #0 @ 0x00
[^>]*> ffb0 e5c0 vmvn q7, q0
[^>]*> ffb0 e5c2 vmvn q7, q1
[^>]*> ffb0 e5c4 vmvn q7, q2
[^>]*> ffb0 e5c8 vmvn q7, q4
[^>]*> ffb0 e5ce vmvn q7, q7
-[^>]*> ef80 e070 vmvn.i32 q7, #0 ; 0x00000000
-[^>]*> ef80 e870 vmvn.i16 q7, #0 ; 0x0000
-[^>]*> ff87 e07f vmvn.i32 q7, #255 ; 0x000000ff
-[^>]*> ff87 e27f vmvn.i32 q7, #65280 ; 0x0000ff00
-[^>]*> ff87 e47f vmvn.i32 q7, #16711680 ; 0x00ff0000
-[^>]*> ff87 e67f vmvn.i32 q7, #4278190080 ; 0xff000000
-[^>]*> ff82 ec7b vmvn.i32 q7, #44031 ; 0x0000abff
-[^>]*> ff87 e87f vmvn.i16 q7, #255 ; 0x00ff
-[^>]*> ff87 ea7f vmvn.i16 q7, #65280 ; 0xff00
-[^>]*> ff87 ea5e vmov.i16 q7, #65024 ; 0xfe00
-[^>]*> ef80 ee50 vmov.i8 q7, #0 ; 0x00
+[^>]*> ef80 e070 vmvn.i32 q7, #0 @ 0x00000000
+[^>]*> ef80 e870 vmvn.i16 q7, #0 @ 0x0000
+[^>]*> ff87 e07f vmvn.i32 q7, #255 @ 0x000000ff
+[^>]*> ff87 e27f vmvn.i32 q7, #65280 @ 0x0000ff00
+[^>]*> ff87 e47f vmvn.i32 q7, #16711680 @ 0x00ff0000
+[^>]*> ff87 e67f vmvn.i32 q7, #4278190080 @ 0xff000000
+[^>]*> ff82 ec7b vmvn.i32 q7, #44031 @ 0x0000abff
+[^>]*> ff87 e87f vmvn.i16 q7, #255 @ 0x00ff
+[^>]*> ff87 ea7f vmvn.i16 q7, #65280 @ 0xff00
+[^>]*> ff87 ea5e vmov.i16 q7, #65024 @ 0xfe00
+[^>]*> ef80 ee50 vmov.i8 q7, #0 @ 0x00
[^>]*> fe71 ef4d vpstete
-[^>]*> ff87 007f vmvnt.i32 q0, #255 ; 0x000000ff
-[^>]*> ff87 ca7f vmvne.i16 q6, #65280 ; 0xff00
+[^>]*> ff87 007f vmvnt.i32 q0, #255 @ 0x000000ff
+[^>]*> ff87 ca7f vmvne.i16 q6, #65280 @ 0xff00
[^>]*> ffb0 05c2 vmvnt q0, q1
[^>]*> ffb0 e5c6 vmvne q7, q3
diff --git a/gas/testsuite/gas/arm/mve-vorn.d b/gas/testsuite/gas/arm/mve-vorn.d
index d2c20a25e5b..083de03812f 100644
--- a/gas/testsuite/gas/arm/mve-vorn.d
+++ b/gas/testsuite/gas/arm/mve-vorn.d
@@ -1005,17 +1005,17 @@ Disassembly of section .text:
[^>]*> ef3e e15e vorn q7, q7, q7
[^>]*> ef3e e15e vorn q7, q7, q7
[^>]*> ef3e e15e vorn q7, q7, q7
-[^>]*> ef80 0150 vorr.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 e150 vorr.i32 q7, #0 ; 0x00000000
-[^>]*> ff87 015f vorr.i32 q0, #255 ; 0x000000ff
-[^>]*> ff87 035f vorr.i32 q0, #65280 ; 0x0000ff00
-[^>]*> ff87 055f vorr.i32 q0, #16711680 ; 0x00ff0000
-[^>]*> ff87 075f vorr.i32 q0, #4278190080 ; 0xff000000
-[^>]*> ef80 0950 vorr.i16 q0, #0 ; 0x0000
-[^>]*> ff87 0b5f vorr.i16 q0, #65280 ; 0xff00
-[^>]*> ff87 095f vorr.i16 q0, #255 ; 0x00ff
+[^>]*> ef80 0150 vorr.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 e150 vorr.i32 q7, #0 @ 0x00000000
+[^>]*> ff87 015f vorr.i32 q0, #255 @ 0x000000ff
+[^>]*> ff87 035f vorr.i32 q0, #65280 @ 0x0000ff00
+[^>]*> ff87 055f vorr.i32 q0, #16711680 @ 0x00ff0000
+[^>]*> ff87 075f vorr.i32 q0, #4278190080 @ 0xff000000
+[^>]*> ef80 0950 vorr.i16 q0, #0 @ 0x0000
+[^>]*> ff87 0b5f vorr.i16 q0, #65280 @ 0xff00
+[^>]*> ff87 095f vorr.i16 q0, #255 @ 0x00ff
[^>]*> fe71 ef4d vpstete
[^>]*> ef32 0154 vornt q0, q1, q2
[^>]*> ef32 0154 vorne q0, q1, q2
-[^>]*> ef80 0150 vorrt.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0950 vorre.i16 q0, #0 ; 0x0000
+[^>]*> ef80 0150 vorrt.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0950 vorre.i16 q0, #0 @ 0x0000
diff --git a/gas/testsuite/gas/arm/mve-vorr.d b/gas/testsuite/gas/arm/mve-vorr.d
index 96a69d8d13c..a21a511623c 100644
--- a/gas/testsuite/gas/arm/mve-vorr.d
+++ b/gas/testsuite/gas/arm/mve-vorr.d
@@ -1005,16 +1005,16 @@ Disassembly of section .text:
[^>]*> ef2e e15e vmov q7, q7
[^>]*> ef2e e15e vmov q7, q7
[^>]*> ef2e e15e vmov q7, q7
-[^>]*> ef80 0150 vorr.i32 q0, #0 ; 0x00000000
-[^>]*> ff87 015f vorr.i32 q0, #255 ; 0x000000ff
-[^>]*> ff87 035f vorr.i32 q0, #65280 ; 0x0000ff00
-[^>]*> ff87 075f vorr.i32 q0, #4278190080 ; 0xff000000
-[^>]*> ff87 055f vorr.i32 q0, #16711680 ; 0x00ff0000
-[^>]*> ef80 0950 vorr.i16 q0, #0 ; 0x0000
-[^>]*> ff87 095f vorr.i16 q0, #255 ; 0x00ff
-[^>]*> ff87 0b5f vorr.i16 q0, #65280 ; 0xff00
+[^>]*> ef80 0150 vorr.i32 q0, #0 @ 0x00000000
+[^>]*> ff87 015f vorr.i32 q0, #255 @ 0x000000ff
+[^>]*> ff87 035f vorr.i32 q0, #65280 @ 0x0000ff00
+[^>]*> ff87 075f vorr.i32 q0, #4278190080 @ 0xff000000
+[^>]*> ff87 055f vorr.i32 q0, #16711680 @ 0x00ff0000
+[^>]*> ef80 0950 vorr.i16 q0, #0 @ 0x0000
+[^>]*> ff87 095f vorr.i16 q0, #255 @ 0x00ff
+[^>]*> ff87 0b5f vorr.i16 q0, #65280 @ 0xff00
[^>]*> fe71 ef4d vpstete
[^>]*> ef22 0154 vorrt q0, q1, q2
[^>]*> ef22 0154 vorre q0, q1, q2
-[^>]*> ef80 0150 vorrt.i32 q0, #0 ; 0x00000000
-[^>]*> ff87 0b5f vorre.i16 q0, #65280 ; 0xff00
+[^>]*> ef80 0150 vorrt.i32 q0, #0 @ 0x00000000
+[^>]*> ff87 0b5f vorre.i16 q0, #65280 @ 0xff00
diff --git a/gas/testsuite/gas/arm/neon-cond-bad_t2.d b/gas/testsuite/gas/arm/neon-cond-bad_t2.d
index 47717ba4775..f2799140085 100644
--- a/gas/testsuite/gas/arm/neon-cond-bad_t2.d
+++ b/gas/testsuite/gas/arm/neon-cond-bad_t2.d
@@ -8,8 +8,8 @@ Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> bf01 itttt eq
0[0-9a-f]+ <[^>]+> ef22 0152 vorreq q0, q1, q1
0[0-9a-f]+ <[^>]+> ef21 0111 vorreq d0, d1, d1
-0[0-9a-f]+ <[^>]+> ef80 0050 vmoveq\.i32 q0, #0 ; 0x00000000
-0[0-9a-f]+ <[^>]+> ef80 0010 vmoveq\.i32 d0, #0 ; 0x00000000
+0[0-9a-f]+ <[^>]+> ef80 0050 vmoveq\.i32 q0, #0 @ 0x00000000
+0[0-9a-f]+ <[^>]+> ef80 0010 vmoveq\.i32 d0, #0 @ 0x00000000
0[0-9a-f]+ <[^>]+> bf01 itttt eq
0[0-9a-f]+ <[^>]+> ee20 2b10 vmoveq\.32 d0\[1\], r2
0[0-9a-f]+ <[^>]+> ec42 1b10 vmoveq d0, r1, r2
diff --git a/gas/testsuite/gas/arm/neon-const.d b/gas/testsuite/gas/arm/neon-const.d
index 6c46930b7e0..3c80694ac2c 100644
--- a/gas/testsuite/gas/arm/neon-const.d
+++ b/gas/testsuite/gas/arm/neon-const.d
@@ -5,262 +5,262 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> f2800050 vmov\.i32 q0, #0 ; 0x00000000
-0[0-9a-f]+ <[^>]+> f2800f50 vmov\.f32 q0, #2 ; 0x40000000
-0[0-9a-f]+ <[^>]+> f2810f50 vmov\.f32 q0, #4 ; 0x40800000
-0[0-9a-f]+ <[^>]+> f2820f50 vmov\.f32 q0, #8 ; 0x41000000
-0[0-9a-f]+ <[^>]+> f2830f50 vmov\.f32 q0, #16 ; 0x41800000
-0[0-9a-f]+ <[^>]+> f2840f50 vmov\.f32 q0, #0\.125 ; 0x3e000000
-0[0-9a-f]+ <[^>]+> f2850f50 vmov\.f32 q0, #0\.25 ; 0x3e800000
-0[0-9a-f]+ <[^>]+> f2860f50 vmov\.f32 q0, #0\.5 ; 0x3f000000
-0[0-9a-f]+ <[^>]+> f2870f50 vmov\.f32 q0, #1 ; 0x3f800000
-0[0-9a-f]+ <[^>]+> f2800f51 vmov\.f32 q0, #2\.125 ; 0x40080000
-0[0-9a-f]+ <[^>]+> f2810f51 vmov\.f32 q0, #4\.25 ; 0x40880000
-0[0-9a-f]+ <[^>]+> f2820f51 vmov\.f32 q0, #8\.5 ; 0x41080000
-0[0-9a-f]+ <[^>]+> f2830f51 vmov\.f32 q0, #17 ; 0x41880000
-0[0-9a-f]+ <[^>]+> f2840f51 vmov\.f32 q0, #0\.1328125 ; 0x3e080000
-0[0-9a-f]+ <[^>]+> f2850f51 vmov\.f32 q0, #0\.265625 ; 0x3e880000
-0[0-9a-f]+ <[^>]+> f2860f51 vmov\.f32 q0, #0\.53125 ; 0x3f080000
-0[0-9a-f]+ <[^>]+> f2870f51 vmov\.f32 q0, #1\.0625 ; 0x3f880000
-0[0-9a-f]+ <[^>]+> f2800f52 vmov\.f32 q0, #2\.25 ; 0x40100000
-0[0-9a-f]+ <[^>]+> f2810f52 vmov\.f32 q0, #4\.5 ; 0x40900000
-0[0-9a-f]+ <[^>]+> f2820f52 vmov\.f32 q0, #9 ; 0x41100000
-0[0-9a-f]+ <[^>]+> f2830f52 vmov\.f32 q0, #18 ; 0x41900000
-0[0-9a-f]+ <[^>]+> f2840f52 vmov\.f32 q0, #0\.140625 ; 0x3e100000
-0[0-9a-f]+ <[^>]+> f2850f52 vmov\.f32 q0, #0\.28125 ; 0x3e900000
-0[0-9a-f]+ <[^>]+> f2860f52 vmov\.f32 q0, #0\.5625 ; 0x3f100000
-0[0-9a-f]+ <[^>]+> f2870f52 vmov\.f32 q0, #1\.125 ; 0x3f900000
-0[0-9a-f]+ <[^>]+> f2800f53 vmov\.f32 q0, #2\.375 ; 0x40180000
-0[0-9a-f]+ <[^>]+> f2810f53 vmov\.f32 q0, #4\.75 ; 0x40980000
-0[0-9a-f]+ <[^>]+> f2820f53 vmov\.f32 q0, #9\.5 ; 0x41180000
-0[0-9a-f]+ <[^>]+> f2830f53 vmov\.f32 q0, #19 ; 0x41980000
-0[0-9a-f]+ <[^>]+> f2840f53 vmov\.f32 q0, #0\.1484375 ; 0x3e180000
-0[0-9a-f]+ <[^>]+> f2850f53 vmov\.f32 q0, #0\.296875 ; 0x3e980000
-0[0-9a-f]+ <[^>]+> f2860f53 vmov\.f32 q0, #0\.59375 ; 0x3f180000
-0[0-9a-f]+ <[^>]+> f2870f53 vmov\.f32 q0, #1\.1875 ; 0x3f980000
-0[0-9a-f]+ <[^>]+> f2800f54 vmov\.f32 q0, #2\.5 ; 0x40200000
-0[0-9a-f]+ <[^>]+> f2810f54 vmov\.f32 q0, #5 ; 0x40a00000
-0[0-9a-f]+ <[^>]+> f2820f54 vmov\.f32 q0, #10 ; 0x41200000
-0[0-9a-f]+ <[^>]+> f2830f54 vmov\.f32 q0, #20 ; 0x41a00000
-0[0-9a-f]+ <[^>]+> f2840f54 vmov\.f32 q0, #0\.15625 ; 0x3e200000
-0[0-9a-f]+ <[^>]+> f2850f54 vmov\.f32 q0, #0\.3125 ; 0x3ea00000
-0[0-9a-f]+ <[^>]+> f2860f54 vmov\.f32 q0, #0\.625 ; 0x3f200000
-0[0-9a-f]+ <[^>]+> f2870f54 vmov\.f32 q0, #1\.25 ; 0x3fa00000
-0[0-9a-f]+ <[^>]+> f2800f55 vmov\.f32 q0, #2\.625 ; 0x40280000
-0[0-9a-f]+ <[^>]+> f2810f55 vmov\.f32 q0, #5\.25 ; 0x40a80000
-0[0-9a-f]+ <[^>]+> f2820f55 vmov\.f32 q0, #10\.5 ; 0x41280000
-0[0-9a-f]+ <[^>]+> f2830f55 vmov\.f32 q0, #21 ; 0x41a80000
-0[0-9a-f]+ <[^>]+> f2840f55 vmov\.f32 q0, #0\.1640625 ; 0x3e280000
-0[0-9a-f]+ <[^>]+> f2850f55 vmov\.f32 q0, #0\.328125 ; 0x3ea80000
-0[0-9a-f]+ <[^>]+> f2860f55 vmov\.f32 q0, #0\.65625 ; 0x3f280000
-0[0-9a-f]+ <[^>]+> f2870f55 vmov\.f32 q0, #1\.3125 ; 0x3fa80000
-0[0-9a-f]+ <[^>]+> f2800f56 vmov\.f32 q0, #2\.75 ; 0x40300000
-0[0-9a-f]+ <[^>]+> f2810f56 vmov\.f32 q0, #5\.5 ; 0x40b00000
-0[0-9a-f]+ <[^>]+> f2820f56 vmov\.f32 q0, #11 ; 0x41300000
-0[0-9a-f]+ <[^>]+> f2830f56 vmov\.f32 q0, #22 ; 0x41b00000
-0[0-9a-f]+ <[^>]+> f2840f56 vmov\.f32 q0, #0\.171875 ; 0x3e300000
-0[0-9a-f]+ <[^>]+> f2850f56 vmov\.f32 q0, #0\.34375 ; 0x3eb00000
-0[0-9a-f]+ <[^>]+> f2860f56 vmov\.f32 q0, #0\.6875 ; 0x3f300000
-0[0-9a-f]+ <[^>]+> f2870f56 vmov\.f32 q0, #1\.375 ; 0x3fb00000
-0[0-9a-f]+ <[^>]+> f2800f57 vmov\.f32 q0, #2\.875 ; 0x40380000
-0[0-9a-f]+ <[^>]+> f2810f57 vmov\.f32 q0, #5\.75 ; 0x40b80000
-0[0-9a-f]+ <[^>]+> f2820f57 vmov\.f32 q0, #11\.5 ; 0x41380000
-0[0-9a-f]+ <[^>]+> f2830f57 vmov\.f32 q0, #23 ; 0x41b80000
-0[0-9a-f]+ <[^>]+> f2840f57 vmov\.f32 q0, #0\.1796875 ; 0x3e380000
-0[0-9a-f]+ <[^>]+> f2850f57 vmov\.f32 q0, #0\.359375 ; 0x3eb80000
-0[0-9a-f]+ <[^>]+> f2860f57 vmov\.f32 q0, #0\.71875 ; 0x3f380000
-0[0-9a-f]+ <[^>]+> f2870f57 vmov\.f32 q0, #1\.4375 ; 0x3fb80000
-0[0-9a-f]+ <[^>]+> f2800f58 vmov\.f32 q0, #3 ; 0x40400000
-0[0-9a-f]+ <[^>]+> f2810f58 vmov\.f32 q0, #6 ; 0x40c00000
-0[0-9a-f]+ <[^>]+> f2820f58 vmov\.f32 q0, #12 ; 0x41400000
-0[0-9a-f]+ <[^>]+> f2830f58 vmov\.f32 q0, #24 ; 0x41c00000
-0[0-9a-f]+ <[^>]+> f2840f58 vmov\.f32 q0, #0\.1875 ; 0x3e400000
-0[0-9a-f]+ <[^>]+> f2850f58 vmov\.f32 q0, #0\.375 ; 0x3ec00000
-0[0-9a-f]+ <[^>]+> f2860f58 vmov\.f32 q0, #0\.75 ; 0x3f400000
-0[0-9a-f]+ <[^>]+> f2870f58 vmov\.f32 q0, #1\.5 ; 0x3fc00000
-0[0-9a-f]+ <[^>]+> f2800f59 vmov\.f32 q0, #3\.125 ; 0x40480000
-0[0-9a-f]+ <[^>]+> f2810f59 vmov\.f32 q0, #6\.25 ; 0x40c80000
-0[0-9a-f]+ <[^>]+> f2820f59 vmov\.f32 q0, #12\.5 ; 0x41480000
-0[0-9a-f]+ <[^>]+> f2830f59 vmov\.f32 q0, #25 ; 0x41c80000
-0[0-9a-f]+ <[^>]+> f2840f59 vmov\.f32 q0, #0\.1953125 ; 0x3e480000
-0[0-9a-f]+ <[^>]+> f2850f59 vmov\.f32 q0, #0\.390625 ; 0x3ec80000
-0[0-9a-f]+ <[^>]+> f2860f59 vmov\.f32 q0, #0\.78125 ; 0x3f480000
-0[0-9a-f]+ <[^>]+> f2870f59 vmov\.f32 q0, #1\.5625 ; 0x3fc80000
-0[0-9a-f]+ <[^>]+> f2800f5a vmov\.f32 q0, #3\.25 ; 0x40500000
-0[0-9a-f]+ <[^>]+> f2810f5a vmov\.f32 q0, #6\.5 ; 0x40d00000
-0[0-9a-f]+ <[^>]+> f2820f5a vmov\.f32 q0, #13 ; 0x41500000
-0[0-9a-f]+ <[^>]+> f2830f5a vmov\.f32 q0, #26 ; 0x41d00000
-0[0-9a-f]+ <[^>]+> f2840f5a vmov\.f32 q0, #0\.203125 ; 0x3e500000
-0[0-9a-f]+ <[^>]+> f2850f5a vmov\.f32 q0, #0\.40625 ; 0x3ed00000
-0[0-9a-f]+ <[^>]+> f2860f5a vmov\.f32 q0, #0\.8125 ; 0x3f500000
-0[0-9a-f]+ <[^>]+> f2870f5a vmov\.f32 q0, #1\.625 ; 0x3fd00000
-0[0-9a-f]+ <[^>]+> f2800f5b vmov\.f32 q0, #3\.375 ; 0x40580000
-0[0-9a-f]+ <[^>]+> f2810f5b vmov\.f32 q0, #6\.75 ; 0x40d80000
-0[0-9a-f]+ <[^>]+> f2820f5b vmov\.f32 q0, #13\.5 ; 0x41580000
-0[0-9a-f]+ <[^>]+> f2830f5b vmov\.f32 q0, #27 ; 0x41d80000
-0[0-9a-f]+ <[^>]+> f2840f5b vmov\.f32 q0, #0\.2109375 ; 0x3e580000
-0[0-9a-f]+ <[^>]+> f2850f5b vmov\.f32 q0, #0\.421875 ; 0x3ed80000
-0[0-9a-f]+ <[^>]+> f2860f5b vmov\.f32 q0, #0\.84375 ; 0x3f580000
-0[0-9a-f]+ <[^>]+> f2870f5b vmov\.f32 q0, #1\.6875 ; 0x3fd80000
-0[0-9a-f]+ <[^>]+> f2800f5c vmov\.f32 q0, #3\.5 ; 0x40600000
-0[0-9a-f]+ <[^>]+> f2810f5c vmov\.f32 q0, #7 ; 0x40e00000
-0[0-9a-f]+ <[^>]+> f2820f5c vmov\.f32 q0, #14 ; 0x41600000
-0[0-9a-f]+ <[^>]+> f2830f5c vmov\.f32 q0, #28 ; 0x41e00000
-0[0-9a-f]+ <[^>]+> f2840f5c vmov\.f32 q0, #0\.21875 ; 0x3e600000
-0[0-9a-f]+ <[^>]+> f2850f5c vmov\.f32 q0, #0\.4375 ; 0x3ee00000
-0[0-9a-f]+ <[^>]+> f2860f5c vmov\.f32 q0, #0\.875 ; 0x3f600000
-0[0-9a-f]+ <[^>]+> f2870f5c vmov\.f32 q0, #1\.75 ; 0x3fe00000
-0[0-9a-f]+ <[^>]+> f2800f5d vmov\.f32 q0, #3\.625 ; 0x40680000
-0[0-9a-f]+ <[^>]+> f2810f5d vmov\.f32 q0, #7\.25 ; 0x40e80000
-0[0-9a-f]+ <[^>]+> f2820f5d vmov\.f32 q0, #14\.5 ; 0x41680000
-0[0-9a-f]+ <[^>]+> f2830f5d vmov\.f32 q0, #29 ; 0x41e80000
-0[0-9a-f]+ <[^>]+> f2840f5d vmov\.f32 q0, #0\.2265625 ; 0x3e680000
-0[0-9a-f]+ <[^>]+> f2850f5d vmov\.f32 q0, #0\.453125 ; 0x3ee80000
-0[0-9a-f]+ <[^>]+> f2860f5d vmov\.f32 q0, #0\.90625 ; 0x3f680000
-0[0-9a-f]+ <[^>]+> f2870f5d vmov\.f32 q0, #1\.8125 ; 0x3fe80000
-0[0-9a-f]+ <[^>]+> f2800f5e vmov\.f32 q0, #3\.75 ; 0x40700000
-0[0-9a-f]+ <[^>]+> f2810f5e vmov\.f32 q0, #7\.5 ; 0x40f00000
-0[0-9a-f]+ <[^>]+> f2820f5e vmov\.f32 q0, #15 ; 0x41700000
-0[0-9a-f]+ <[^>]+> f2830f5e vmov\.f32 q0, #30 ; 0x41f00000
-0[0-9a-f]+ <[^>]+> f2840f5e vmov\.f32 q0, #0\.234375 ; 0x3e700000
-0[0-9a-f]+ <[^>]+> f2850f5e vmov\.f32 q0, #0\.46875 ; 0x3ef00000
-0[0-9a-f]+ <[^>]+> f2860f5e vmov\.f32 q0, #0\.9375 ; 0x3f700000
-0[0-9a-f]+ <[^>]+> f2870f5e vmov\.f32 q0, #1\.875 ; 0x3ff00000
-0[0-9a-f]+ <[^>]+> f2800f5f vmov\.f32 q0, #3\.875 ; 0x40780000
-0[0-9a-f]+ <[^>]+> f2810f5f vmov\.f32 q0, #7\.75 ; 0x40f80000
-0[0-9a-f]+ <[^>]+> f2820f5f vmov\.f32 q0, #15\.5 ; 0x41780000
-0[0-9a-f]+ <[^>]+> f2830f5f vmov\.f32 q0, #31 ; 0x41f80000
-0[0-9a-f]+ <[^>]+> f2840f5f vmov\.f32 q0, #0\.2421875 ; 0x3e780000
-0[0-9a-f]+ <[^>]+> f2850f5f vmov\.f32 q0, #0\.484375 ; 0x3ef80000
-0[0-9a-f]+ <[^>]+> f2860f5f vmov\.f32 q0, #0\.96875 ; 0x3f780000
-0[0-9a-f]+ <[^>]+> f2870f5f vmov\.f32 q0, #1\.9375 ; 0x3ff80000
-0[0-9a-f]+ <[^>]+> f3800650 vmov\.i32 q0, #-2147483648 ; 0x80000000
-0[0-9a-f]+ <[^>]+> f3800f50 vmov\.f32 q0, #-2 ; 0xc0000000
-0[0-9a-f]+ <[^>]+> f3810f50 vmov\.f32 q0, #-4 ; 0xc0800000
-0[0-9a-f]+ <[^>]+> f3820f50 vmov\.f32 q0, #-8 ; 0xc1000000
-0[0-9a-f]+ <[^>]+> f3830f50 vmov\.f32 q0, #-16 ; 0xc1800000
-0[0-9a-f]+ <[^>]+> f3840f50 vmov\.f32 q0, #-0\.125 ; 0xbe000000
-0[0-9a-f]+ <[^>]+> f3850f50 vmov\.f32 q0, #-0\.25 ; 0xbe800000
-0[0-9a-f]+ <[^>]+> f3860f50 vmov\.f32 q0, #-0\.5 ; 0xbf000000
-0[0-9a-f]+ <[^>]+> f3870f50 vmov\.f32 q0, #-1 ; 0xbf800000
-0[0-9a-f]+ <[^>]+> f3800f51 vmov\.f32 q0, #-2\.125 ; 0xc0080000
-0[0-9a-f]+ <[^>]+> f3810f51 vmov\.f32 q0, #-4\.25 ; 0xc0880000
-0[0-9a-f]+ <[^>]+> f3820f51 vmov\.f32 q0, #-8\.5 ; 0xc1080000
-0[0-9a-f]+ <[^>]+> f3830f51 vmov\.f32 q0, #-17 ; 0xc1880000
-0[0-9a-f]+ <[^>]+> f3840f51 vmov\.f32 q0, #-0\.1328125 ; 0xbe080000
-0[0-9a-f]+ <[^>]+> f3850f51 vmov\.f32 q0, #-0\.265625 ; 0xbe880000
-0[0-9a-f]+ <[^>]+> f3860f51 vmov\.f32 q0, #-0\.53125 ; 0xbf080000
-0[0-9a-f]+ <[^>]+> f3870f51 vmov\.f32 q0, #-1\.0625 ; 0xbf880000
-0[0-9a-f]+ <[^>]+> f3800f52 vmov\.f32 q0, #-2\.25 ; 0xc0100000
-0[0-9a-f]+ <[^>]+> f3810f52 vmov\.f32 q0, #-4\.5 ; 0xc0900000
-0[0-9a-f]+ <[^>]+> f3820f52 vmov\.f32 q0, #-9 ; 0xc1100000
-0[0-9a-f]+ <[^>]+> f3830f52 vmov\.f32 q0, #-18 ; 0xc1900000
-0[0-9a-f]+ <[^>]+> f3840f52 vmov\.f32 q0, #-0\.140625 ; 0xbe100000
-0[0-9a-f]+ <[^>]+> f3850f52 vmov\.f32 q0, #-0\.28125 ; 0xbe900000
-0[0-9a-f]+ <[^>]+> f3860f52 vmov\.f32 q0, #-0\.5625 ; 0xbf100000
-0[0-9a-f]+ <[^>]+> f3870f52 vmov\.f32 q0, #-1\.125 ; 0xbf900000
-0[0-9a-f]+ <[^>]+> f3800f53 vmov\.f32 q0, #-2\.375 ; 0xc0180000
-0[0-9a-f]+ <[^>]+> f3810f53 vmov\.f32 q0, #-4\.75 ; 0xc0980000
-0[0-9a-f]+ <[^>]+> f3820f53 vmov\.f32 q0, #-9\.5 ; 0xc1180000
-0[0-9a-f]+ <[^>]+> f3830f53 vmov\.f32 q0, #-19 ; 0xc1980000
-0[0-9a-f]+ <[^>]+> f3840f53 vmov\.f32 q0, #-0\.1484375 ; 0xbe180000
-0[0-9a-f]+ <[^>]+> f3850f53 vmov\.f32 q0, #-0\.296875 ; 0xbe980000
-0[0-9a-f]+ <[^>]+> f3860f53 vmov\.f32 q0, #-0\.59375 ; 0xbf180000
-0[0-9a-f]+ <[^>]+> f3870f53 vmov\.f32 q0, #-1\.1875 ; 0xbf980000
-0[0-9a-f]+ <[^>]+> f3800f54 vmov\.f32 q0, #-2\.5 ; 0xc0200000
-0[0-9a-f]+ <[^>]+> f3810f54 vmov\.f32 q0, #-5 ; 0xc0a00000
-0[0-9a-f]+ <[^>]+> f3820f54 vmov\.f32 q0, #-10 ; 0xc1200000
-0[0-9a-f]+ <[^>]+> f3830f54 vmov\.f32 q0, #-20 ; 0xc1a00000
-0[0-9a-f]+ <[^>]+> f3840f54 vmov\.f32 q0, #-0\.15625 ; 0xbe200000
-0[0-9a-f]+ <[^>]+> f3850f54 vmov\.f32 q0, #-0\.3125 ; 0xbea00000
-0[0-9a-f]+ <[^>]+> f3860f54 vmov\.f32 q0, #-0\.625 ; 0xbf200000
-0[0-9a-f]+ <[^>]+> f3870f54 vmov\.f32 q0, #-1\.25 ; 0xbfa00000
-0[0-9a-f]+ <[^>]+> f3800f55 vmov\.f32 q0, #-2\.625 ; 0xc0280000
-0[0-9a-f]+ <[^>]+> f3810f55 vmov\.f32 q0, #-5\.25 ; 0xc0a80000
-0[0-9a-f]+ <[^>]+> f3820f55 vmov\.f32 q0, #-10\.5 ; 0xc1280000
-0[0-9a-f]+ <[^>]+> f3830f55 vmov\.f32 q0, #-21 ; 0xc1a80000
-0[0-9a-f]+ <[^>]+> f3840f55 vmov\.f32 q0, #-0\.1640625 ; 0xbe280000
-0[0-9a-f]+ <[^>]+> f3850f55 vmov\.f32 q0, #-0\.328125 ; 0xbea80000
-0[0-9a-f]+ <[^>]+> f3860f55 vmov\.f32 q0, #-0\.65625 ; 0xbf280000
-0[0-9a-f]+ <[^>]+> f3870f55 vmov\.f32 q0, #-1\.3125 ; 0xbfa80000
-0[0-9a-f]+ <[^>]+> f3800f56 vmov\.f32 q0, #-2\.75 ; 0xc0300000
-0[0-9a-f]+ <[^>]+> f3810f56 vmov\.f32 q0, #-5\.5 ; 0xc0b00000
-0[0-9a-f]+ <[^>]+> f3820f56 vmov\.f32 q0, #-11 ; 0xc1300000
-0[0-9a-f]+ <[^>]+> f3830f56 vmov\.f32 q0, #-22 ; 0xc1b00000
-0[0-9a-f]+ <[^>]+> f3840f56 vmov\.f32 q0, #-0\.171875 ; 0xbe300000
-0[0-9a-f]+ <[^>]+> f3850f56 vmov\.f32 q0, #-0\.34375 ; 0xbeb00000
-0[0-9a-f]+ <[^>]+> f3860f56 vmov\.f32 q0, #-0\.6875 ; 0xbf300000
-0[0-9a-f]+ <[^>]+> f3870f56 vmov\.f32 q0, #-1\.375 ; 0xbfb00000
-0[0-9a-f]+ <[^>]+> f3800f57 vmov\.f32 q0, #-2\.875 ; 0xc0380000
-0[0-9a-f]+ <[^>]+> f3810f57 vmov\.f32 q0, #-5\.75 ; 0xc0b80000
-0[0-9a-f]+ <[^>]+> f3820f57 vmov\.f32 q0, #-11\.5 ; 0xc1380000
-0[0-9a-f]+ <[^>]+> f3830f57 vmov\.f32 q0, #-23 ; 0xc1b80000
-0[0-9a-f]+ <[^>]+> f3840f57 vmov\.f32 q0, #-0\.1796875 ; 0xbe380000
-0[0-9a-f]+ <[^>]+> f3850f57 vmov\.f32 q0, #-0\.359375 ; 0xbeb80000
-0[0-9a-f]+ <[^>]+> f3860f57 vmov\.f32 q0, #-0\.71875 ; 0xbf380000
-0[0-9a-f]+ <[^>]+> f3870f57 vmov\.f32 q0, #-1\.4375 ; 0xbfb80000
-0[0-9a-f]+ <[^>]+> f3800f58 vmov\.f32 q0, #-3 ; 0xc0400000
-0[0-9a-f]+ <[^>]+> f3810f58 vmov\.f32 q0, #-6 ; 0xc0c00000
-0[0-9a-f]+ <[^>]+> f3820f58 vmov\.f32 q0, #-12 ; 0xc1400000
-0[0-9a-f]+ <[^>]+> f3830f58 vmov\.f32 q0, #-24 ; 0xc1c00000
-0[0-9a-f]+ <[^>]+> f3840f58 vmov\.f32 q0, #-0\.1875 ; 0xbe400000
-0[0-9a-f]+ <[^>]+> f3850f58 vmov\.f32 q0, #-0\.375 ; 0xbec00000
-0[0-9a-f]+ <[^>]+> f3860f58 vmov\.f32 q0, #-0\.75 ; 0xbf400000
-0[0-9a-f]+ <[^>]+> f3870f58 vmov\.f32 q0, #-1\.5 ; 0xbfc00000
-0[0-9a-f]+ <[^>]+> f3800f59 vmov\.f32 q0, #-3\.125 ; 0xc0480000
-0[0-9a-f]+ <[^>]+> f3810f59 vmov\.f32 q0, #-6\.25 ; 0xc0c80000
-0[0-9a-f]+ <[^>]+> f3820f59 vmov\.f32 q0, #-12\.5 ; 0xc1480000
-0[0-9a-f]+ <[^>]+> f3830f59 vmov\.f32 q0, #-25 ; 0xc1c80000
-0[0-9a-f]+ <[^>]+> f3840f59 vmov\.f32 q0, #-0\.1953125 ; 0xbe480000
-0[0-9a-f]+ <[^>]+> f3850f59 vmov\.f32 q0, #-0\.390625 ; 0xbec80000
-0[0-9a-f]+ <[^>]+> f3860f59 vmov\.f32 q0, #-0\.78125 ; 0xbf480000
-0[0-9a-f]+ <[^>]+> f3870f59 vmov\.f32 q0, #-1\.5625 ; 0xbfc80000
-0[0-9a-f]+ <[^>]+> f3800f5a vmov\.f32 q0, #-3\.25 ; 0xc0500000
-0[0-9a-f]+ <[^>]+> f3810f5a vmov\.f32 q0, #-6\.5 ; 0xc0d00000
-0[0-9a-f]+ <[^>]+> f3820f5a vmov\.f32 q0, #-13 ; 0xc1500000
-0[0-9a-f]+ <[^>]+> f3830f5a vmov\.f32 q0, #-26 ; 0xc1d00000
-0[0-9a-f]+ <[^>]+> f3840f5a vmov\.f32 q0, #-0\.203125 ; 0xbe500000
-0[0-9a-f]+ <[^>]+> f3850f5a vmov\.f32 q0, #-0\.40625 ; 0xbed00000
-0[0-9a-f]+ <[^>]+> f3860f5a vmov\.f32 q0, #-0\.8125 ; 0xbf500000
-0[0-9a-f]+ <[^>]+> f3870f5a vmov\.f32 q0, #-1\.625 ; 0xbfd00000
-0[0-9a-f]+ <[^>]+> f3800f5b vmov\.f32 q0, #-3\.375 ; 0xc0580000
-0[0-9a-f]+ <[^>]+> f3810f5b vmov\.f32 q0, #-6\.75 ; 0xc0d80000
-0[0-9a-f]+ <[^>]+> f3820f5b vmov\.f32 q0, #-13\.5 ; 0xc1580000
-0[0-9a-f]+ <[^>]+> f3830f5b vmov\.f32 q0, #-27 ; 0xc1d80000
-0[0-9a-f]+ <[^>]+> f3840f5b vmov\.f32 q0, #-0\.2109375 ; 0xbe580000
-0[0-9a-f]+ <[^>]+> f3850f5b vmov\.f32 q0, #-0\.421875 ; 0xbed80000
-0[0-9a-f]+ <[^>]+> f3860f5b vmov\.f32 q0, #-0\.84375 ; 0xbf580000
-0[0-9a-f]+ <[^>]+> f3870f5b vmov\.f32 q0, #-1\.6875 ; 0xbfd80000
-0[0-9a-f]+ <[^>]+> f3800f5c vmov\.f32 q0, #-3\.5 ; 0xc0600000
-0[0-9a-f]+ <[^>]+> f3810f5c vmov\.f32 q0, #-7 ; 0xc0e00000
-0[0-9a-f]+ <[^>]+> f3820f5c vmov\.f32 q0, #-14 ; 0xc1600000
-0[0-9a-f]+ <[^>]+> f3830f5c vmov\.f32 q0, #-28 ; 0xc1e00000
-0[0-9a-f]+ <[^>]+> f3840f5c vmov\.f32 q0, #-0\.21875 ; 0xbe600000
-0[0-9a-f]+ <[^>]+> f3850f5c vmov\.f32 q0, #-0\.4375 ; 0xbee00000
-0[0-9a-f]+ <[^>]+> f3860f5c vmov\.f32 q0, #-0\.875 ; 0xbf600000
-0[0-9a-f]+ <[^>]+> f3870f5c vmov\.f32 q0, #-1\.75 ; 0xbfe00000
-0[0-9a-f]+ <[^>]+> f3800f5d vmov\.f32 q0, #-3\.625 ; 0xc0680000
-0[0-9a-f]+ <[^>]+> f3810f5d vmov\.f32 q0, #-7\.25 ; 0xc0e80000
-0[0-9a-f]+ <[^>]+> f3820f5d vmov\.f32 q0, #-14\.5 ; 0xc1680000
-0[0-9a-f]+ <[^>]+> f3830f5d vmov\.f32 q0, #-29 ; 0xc1e80000
-0[0-9a-f]+ <[^>]+> f3840f5d vmov\.f32 q0, #-0\.2265625 ; 0xbe680000
-0[0-9a-f]+ <[^>]+> f3850f5d vmov\.f32 q0, #-0\.453125 ; 0xbee80000
-0[0-9a-f]+ <[^>]+> f3860f5d vmov\.f32 q0, #-0\.90625 ; 0xbf680000
-0[0-9a-f]+ <[^>]+> f3870f5d vmov\.f32 q0, #-1\.8125 ; 0xbfe80000
-0[0-9a-f]+ <[^>]+> f3800f5e vmov\.f32 q0, #-3\.75 ; 0xc0700000
-0[0-9a-f]+ <[^>]+> f3810f5e vmov\.f32 q0, #-7\.5 ; 0xc0f00000
-0[0-9a-f]+ <[^>]+> f3820f5e vmov\.f32 q0, #-15 ; 0xc1700000
-0[0-9a-f]+ <[^>]+> f3830f5e vmov\.f32 q0, #-30 ; 0xc1f00000
-0[0-9a-f]+ <[^>]+> f3840f5e vmov\.f32 q0, #-0\.234375 ; 0xbe700000
-0[0-9a-f]+ <[^>]+> f3850f5e vmov\.f32 q0, #-0\.46875 ; 0xbef00000
-0[0-9a-f]+ <[^>]+> f3860f5e vmov\.f32 q0, #-0\.9375 ; 0xbf700000
-0[0-9a-f]+ <[^>]+> f3870f5e vmov\.f32 q0, #-1\.875 ; 0xbff00000
-0[0-9a-f]+ <[^>]+> f3800f5f vmov\.f32 q0, #-3\.875 ; 0xc0780000
-0[0-9a-f]+ <[^>]+> f3810f5f vmov\.f32 q0, #-7\.75 ; 0xc0f80000
-0[0-9a-f]+ <[^>]+> f3820f5f vmov\.f32 q0, #-15\.5 ; 0xc1780000
-0[0-9a-f]+ <[^>]+> f3830f5f vmov\.f32 q0, #-31 ; 0xc1f80000
-0[0-9a-f]+ <[^>]+> f3840f5f vmov\.f32 q0, #-0\.2421875 ; 0xbe780000
-0[0-9a-f]+ <[^>]+> f3850f5f vmov\.f32 q0, #-0\.484375 ; 0xbef80000
-0[0-9a-f]+ <[^>]+> f3860f5f vmov\.f32 q0, #-0\.96875 ; 0xbf780000
-0[0-9a-f]+ <[^>]+> f3870f5f vmov\.f32 q0, #-1\.9375 ; 0xbff80000
+0[0-9a-f]+ <[^>]+> f2800050 vmov\.i32 q0, #0 @ 0x00000000
+0[0-9a-f]+ <[^>]+> f2800f50 vmov\.f32 q0, #2 @ 0x40000000
+0[0-9a-f]+ <[^>]+> f2810f50 vmov\.f32 q0, #4 @ 0x40800000
+0[0-9a-f]+ <[^>]+> f2820f50 vmov\.f32 q0, #8 @ 0x41000000
+0[0-9a-f]+ <[^>]+> f2830f50 vmov\.f32 q0, #16 @ 0x41800000
+0[0-9a-f]+ <[^>]+> f2840f50 vmov\.f32 q0, #0\.125 @ 0x3e000000
+0[0-9a-f]+ <[^>]+> f2850f50 vmov\.f32 q0, #0\.25 @ 0x3e800000
+0[0-9a-f]+ <[^>]+> f2860f50 vmov\.f32 q0, #0\.5 @ 0x3f000000
+0[0-9a-f]+ <[^>]+> f2870f50 vmov\.f32 q0, #1 @ 0x3f800000
+0[0-9a-f]+ <[^>]+> f2800f51 vmov\.f32 q0, #2\.125 @ 0x40080000
+0[0-9a-f]+ <[^>]+> f2810f51 vmov\.f32 q0, #4\.25 @ 0x40880000
+0[0-9a-f]+ <[^>]+> f2820f51 vmov\.f32 q0, #8\.5 @ 0x41080000
+0[0-9a-f]+ <[^>]+> f2830f51 vmov\.f32 q0, #17 @ 0x41880000
+0[0-9a-f]+ <[^>]+> f2840f51 vmov\.f32 q0, #0\.1328125 @ 0x3e080000
+0[0-9a-f]+ <[^>]+> f2850f51 vmov\.f32 q0, #0\.265625 @ 0x3e880000
+0[0-9a-f]+ <[^>]+> f2860f51 vmov\.f32 q0, #0\.53125 @ 0x3f080000
+0[0-9a-f]+ <[^>]+> f2870f51 vmov\.f32 q0, #1\.0625 @ 0x3f880000
+0[0-9a-f]+ <[^>]+> f2800f52 vmov\.f32 q0, #2\.25 @ 0x40100000
+0[0-9a-f]+ <[^>]+> f2810f52 vmov\.f32 q0, #4\.5 @ 0x40900000
+0[0-9a-f]+ <[^>]+> f2820f52 vmov\.f32 q0, #9 @ 0x41100000
+0[0-9a-f]+ <[^>]+> f2830f52 vmov\.f32 q0, #18 @ 0x41900000
+0[0-9a-f]+ <[^>]+> f2840f52 vmov\.f32 q0, #0\.140625 @ 0x3e100000
+0[0-9a-f]+ <[^>]+> f2850f52 vmov\.f32 q0, #0\.28125 @ 0x3e900000
+0[0-9a-f]+ <[^>]+> f2860f52 vmov\.f32 q0, #0\.5625 @ 0x3f100000
+0[0-9a-f]+ <[^>]+> f2870f52 vmov\.f32 q0, #1\.125 @ 0x3f900000
+0[0-9a-f]+ <[^>]+> f2800f53 vmov\.f32 q0, #2\.375 @ 0x40180000
+0[0-9a-f]+ <[^>]+> f2810f53 vmov\.f32 q0, #4\.75 @ 0x40980000
+0[0-9a-f]+ <[^>]+> f2820f53 vmov\.f32 q0, #9\.5 @ 0x41180000
+0[0-9a-f]+ <[^>]+> f2830f53 vmov\.f32 q0, #19 @ 0x41980000
+0[0-9a-f]+ <[^>]+> f2840f53 vmov\.f32 q0, #0\.1484375 @ 0x3e180000
+0[0-9a-f]+ <[^>]+> f2850f53 vmov\.f32 q0, #0\.296875 @ 0x3e980000
+0[0-9a-f]+ <[^>]+> f2860f53 vmov\.f32 q0, #0\.59375 @ 0x3f180000
+0[0-9a-f]+ <[^>]+> f2870f53 vmov\.f32 q0, #1\.1875 @ 0x3f980000
+0[0-9a-f]+ <[^>]+> f2800f54 vmov\.f32 q0, #2\.5 @ 0x40200000
+0[0-9a-f]+ <[^>]+> f2810f54 vmov\.f32 q0, #5 @ 0x40a00000
+0[0-9a-f]+ <[^>]+> f2820f54 vmov\.f32 q0, #10 @ 0x41200000
+0[0-9a-f]+ <[^>]+> f2830f54 vmov\.f32 q0, #20 @ 0x41a00000
+0[0-9a-f]+ <[^>]+> f2840f54 vmov\.f32 q0, #0\.15625 @ 0x3e200000
+0[0-9a-f]+ <[^>]+> f2850f54 vmov\.f32 q0, #0\.3125 @ 0x3ea00000
+0[0-9a-f]+ <[^>]+> f2860f54 vmov\.f32 q0, #0\.625 @ 0x3f200000
+0[0-9a-f]+ <[^>]+> f2870f54 vmov\.f32 q0, #1\.25 @ 0x3fa00000
+0[0-9a-f]+ <[^>]+> f2800f55 vmov\.f32 q0, #2\.625 @ 0x40280000
+0[0-9a-f]+ <[^>]+> f2810f55 vmov\.f32 q0, #5\.25 @ 0x40a80000
+0[0-9a-f]+ <[^>]+> f2820f55 vmov\.f32 q0, #10\.5 @ 0x41280000
+0[0-9a-f]+ <[^>]+> f2830f55 vmov\.f32 q0, #21 @ 0x41a80000
+0[0-9a-f]+ <[^>]+> f2840f55 vmov\.f32 q0, #0\.1640625 @ 0x3e280000
+0[0-9a-f]+ <[^>]+> f2850f55 vmov\.f32 q0, #0\.328125 @ 0x3ea80000
+0[0-9a-f]+ <[^>]+> f2860f55 vmov\.f32 q0, #0\.65625 @ 0x3f280000
+0[0-9a-f]+ <[^>]+> f2870f55 vmov\.f32 q0, #1\.3125 @ 0x3fa80000
+0[0-9a-f]+ <[^>]+> f2800f56 vmov\.f32 q0, #2\.75 @ 0x40300000
+0[0-9a-f]+ <[^>]+> f2810f56 vmov\.f32 q0, #5\.5 @ 0x40b00000
+0[0-9a-f]+ <[^>]+> f2820f56 vmov\.f32 q0, #11 @ 0x41300000
+0[0-9a-f]+ <[^>]+> f2830f56 vmov\.f32 q0, #22 @ 0x41b00000
+0[0-9a-f]+ <[^>]+> f2840f56 vmov\.f32 q0, #0\.171875 @ 0x3e300000
+0[0-9a-f]+ <[^>]+> f2850f56 vmov\.f32 q0, #0\.34375 @ 0x3eb00000
+0[0-9a-f]+ <[^>]+> f2860f56 vmov\.f32 q0, #0\.6875 @ 0x3f300000
+0[0-9a-f]+ <[^>]+> f2870f56 vmov\.f32 q0, #1\.375 @ 0x3fb00000
+0[0-9a-f]+ <[^>]+> f2800f57 vmov\.f32 q0, #2\.875 @ 0x40380000
+0[0-9a-f]+ <[^>]+> f2810f57 vmov\.f32 q0, #5\.75 @ 0x40b80000
+0[0-9a-f]+ <[^>]+> f2820f57 vmov\.f32 q0, #11\.5 @ 0x41380000
+0[0-9a-f]+ <[^>]+> f2830f57 vmov\.f32 q0, #23 @ 0x41b80000
+0[0-9a-f]+ <[^>]+> f2840f57 vmov\.f32 q0, #0\.1796875 @ 0x3e380000
+0[0-9a-f]+ <[^>]+> f2850f57 vmov\.f32 q0, #0\.359375 @ 0x3eb80000
+0[0-9a-f]+ <[^>]+> f2860f57 vmov\.f32 q0, #0\.71875 @ 0x3f380000
+0[0-9a-f]+ <[^>]+> f2870f57 vmov\.f32 q0, #1\.4375 @ 0x3fb80000
+0[0-9a-f]+ <[^>]+> f2800f58 vmov\.f32 q0, #3 @ 0x40400000
+0[0-9a-f]+ <[^>]+> f2810f58 vmov\.f32 q0, #6 @ 0x40c00000
+0[0-9a-f]+ <[^>]+> f2820f58 vmov\.f32 q0, #12 @ 0x41400000
+0[0-9a-f]+ <[^>]+> f2830f58 vmov\.f32 q0, #24 @ 0x41c00000
+0[0-9a-f]+ <[^>]+> f2840f58 vmov\.f32 q0, #0\.1875 @ 0x3e400000
+0[0-9a-f]+ <[^>]+> f2850f58 vmov\.f32 q0, #0\.375 @ 0x3ec00000
+0[0-9a-f]+ <[^>]+> f2860f58 vmov\.f32 q0, #0\.75 @ 0x3f400000
+0[0-9a-f]+ <[^>]+> f2870f58 vmov\.f32 q0, #1\.5 @ 0x3fc00000
+0[0-9a-f]+ <[^>]+> f2800f59 vmov\.f32 q0, #3\.125 @ 0x40480000
+0[0-9a-f]+ <[^>]+> f2810f59 vmov\.f32 q0, #6\.25 @ 0x40c80000
+0[0-9a-f]+ <[^>]+> f2820f59 vmov\.f32 q0, #12\.5 @ 0x41480000
+0[0-9a-f]+ <[^>]+> f2830f59 vmov\.f32 q0, #25 @ 0x41c80000
+0[0-9a-f]+ <[^>]+> f2840f59 vmov\.f32 q0, #0\.1953125 @ 0x3e480000
+0[0-9a-f]+ <[^>]+> f2850f59 vmov\.f32 q0, #0\.390625 @ 0x3ec80000
+0[0-9a-f]+ <[^>]+> f2860f59 vmov\.f32 q0, #0\.78125 @ 0x3f480000
+0[0-9a-f]+ <[^>]+> f2870f59 vmov\.f32 q0, #1\.5625 @ 0x3fc80000
+0[0-9a-f]+ <[^>]+> f2800f5a vmov\.f32 q0, #3\.25 @ 0x40500000
+0[0-9a-f]+ <[^>]+> f2810f5a vmov\.f32 q0, #6\.5 @ 0x40d00000
+0[0-9a-f]+ <[^>]+> f2820f5a vmov\.f32 q0, #13 @ 0x41500000
+0[0-9a-f]+ <[^>]+> f2830f5a vmov\.f32 q0, #26 @ 0x41d00000
+0[0-9a-f]+ <[^>]+> f2840f5a vmov\.f32 q0, #0\.203125 @ 0x3e500000
+0[0-9a-f]+ <[^>]+> f2850f5a vmov\.f32 q0, #0\.40625 @ 0x3ed00000
+0[0-9a-f]+ <[^>]+> f2860f5a vmov\.f32 q0, #0\.8125 @ 0x3f500000
+0[0-9a-f]+ <[^>]+> f2870f5a vmov\.f32 q0, #1\.625 @ 0x3fd00000
+0[0-9a-f]+ <[^>]+> f2800f5b vmov\.f32 q0, #3\.375 @ 0x40580000
+0[0-9a-f]+ <[^>]+> f2810f5b vmov\.f32 q0, #6\.75 @ 0x40d80000
+0[0-9a-f]+ <[^>]+> f2820f5b vmov\.f32 q0, #13\.5 @ 0x41580000
+0[0-9a-f]+ <[^>]+> f2830f5b vmov\.f32 q0, #27 @ 0x41d80000
+0[0-9a-f]+ <[^>]+> f2840f5b vmov\.f32 q0, #0\.2109375 @ 0x3e580000
+0[0-9a-f]+ <[^>]+> f2850f5b vmov\.f32 q0, #0\.421875 @ 0x3ed80000
+0[0-9a-f]+ <[^>]+> f2860f5b vmov\.f32 q0, #0\.84375 @ 0x3f580000
+0[0-9a-f]+ <[^>]+> f2870f5b vmov\.f32 q0, #1\.6875 @ 0x3fd80000
+0[0-9a-f]+ <[^>]+> f2800f5c vmov\.f32 q0, #3\.5 @ 0x40600000
+0[0-9a-f]+ <[^>]+> f2810f5c vmov\.f32 q0, #7 @ 0x40e00000
+0[0-9a-f]+ <[^>]+> f2820f5c vmov\.f32 q0, #14 @ 0x41600000
+0[0-9a-f]+ <[^>]+> f2830f5c vmov\.f32 q0, #28 @ 0x41e00000
+0[0-9a-f]+ <[^>]+> f2840f5c vmov\.f32 q0, #0\.21875 @ 0x3e600000
+0[0-9a-f]+ <[^>]+> f2850f5c vmov\.f32 q0, #0\.4375 @ 0x3ee00000
+0[0-9a-f]+ <[^>]+> f2860f5c vmov\.f32 q0, #0\.875 @ 0x3f600000
+0[0-9a-f]+ <[^>]+> f2870f5c vmov\.f32 q0, #1\.75 @ 0x3fe00000
+0[0-9a-f]+ <[^>]+> f2800f5d vmov\.f32 q0, #3\.625 @ 0x40680000
+0[0-9a-f]+ <[^>]+> f2810f5d vmov\.f32 q0, #7\.25 @ 0x40e80000
+0[0-9a-f]+ <[^>]+> f2820f5d vmov\.f32 q0, #14\.5 @ 0x41680000
+0[0-9a-f]+ <[^>]+> f2830f5d vmov\.f32 q0, #29 @ 0x41e80000
+0[0-9a-f]+ <[^>]+> f2840f5d vmov\.f32 q0, #0\.2265625 @ 0x3e680000
+0[0-9a-f]+ <[^>]+> f2850f5d vmov\.f32 q0, #0\.453125 @ 0x3ee80000
+0[0-9a-f]+ <[^>]+> f2860f5d vmov\.f32 q0, #0\.90625 @ 0x3f680000
+0[0-9a-f]+ <[^>]+> f2870f5d vmov\.f32 q0, #1\.8125 @ 0x3fe80000
+0[0-9a-f]+ <[^>]+> f2800f5e vmov\.f32 q0, #3\.75 @ 0x40700000
+0[0-9a-f]+ <[^>]+> f2810f5e vmov\.f32 q0, #7\.5 @ 0x40f00000
+0[0-9a-f]+ <[^>]+> f2820f5e vmov\.f32 q0, #15 @ 0x41700000
+0[0-9a-f]+ <[^>]+> f2830f5e vmov\.f32 q0, #30 @ 0x41f00000
+0[0-9a-f]+ <[^>]+> f2840f5e vmov\.f32 q0, #0\.234375 @ 0x3e700000
+0[0-9a-f]+ <[^>]+> f2850f5e vmov\.f32 q0, #0\.46875 @ 0x3ef00000
+0[0-9a-f]+ <[^>]+> f2860f5e vmov\.f32 q0, #0\.9375 @ 0x3f700000
+0[0-9a-f]+ <[^>]+> f2870f5e vmov\.f32 q0, #1\.875 @ 0x3ff00000
+0[0-9a-f]+ <[^>]+> f2800f5f vmov\.f32 q0, #3\.875 @ 0x40780000
+0[0-9a-f]+ <[^>]+> f2810f5f vmov\.f32 q0, #7\.75 @ 0x40f80000
+0[0-9a-f]+ <[^>]+> f2820f5f vmov\.f32 q0, #15\.5 @ 0x41780000
+0[0-9a-f]+ <[^>]+> f2830f5f vmov\.f32 q0, #31 @ 0x41f80000
+0[0-9a-f]+ <[^>]+> f2840f5f vmov\.f32 q0, #0\.2421875 @ 0x3e780000
+0[0-9a-f]+ <[^>]+> f2850f5f vmov\.f32 q0, #0\.484375 @ 0x3ef80000
+0[0-9a-f]+ <[^>]+> f2860f5f vmov\.f32 q0, #0\.96875 @ 0x3f780000
+0[0-9a-f]+ <[^>]+> f2870f5f vmov\.f32 q0, #1\.9375 @ 0x3ff80000
+0[0-9a-f]+ <[^>]+> f3800650 vmov\.i32 q0, #-2147483648 @ 0x80000000
+0[0-9a-f]+ <[^>]+> f3800f50 vmov\.f32 q0, #-2 @ 0xc0000000
+0[0-9a-f]+ <[^>]+> f3810f50 vmov\.f32 q0, #-4 @ 0xc0800000
+0[0-9a-f]+ <[^>]+> f3820f50 vmov\.f32 q0, #-8 @ 0xc1000000
+0[0-9a-f]+ <[^>]+> f3830f50 vmov\.f32 q0, #-16 @ 0xc1800000
+0[0-9a-f]+ <[^>]+> f3840f50 vmov\.f32 q0, #-0\.125 @ 0xbe000000
+0[0-9a-f]+ <[^>]+> f3850f50 vmov\.f32 q0, #-0\.25 @ 0xbe800000
+0[0-9a-f]+ <[^>]+> f3860f50 vmov\.f32 q0, #-0\.5 @ 0xbf000000
+0[0-9a-f]+ <[^>]+> f3870f50 vmov\.f32 q0, #-1 @ 0xbf800000
+0[0-9a-f]+ <[^>]+> f3800f51 vmov\.f32 q0, #-2\.125 @ 0xc0080000
+0[0-9a-f]+ <[^>]+> f3810f51 vmov\.f32 q0, #-4\.25 @ 0xc0880000
+0[0-9a-f]+ <[^>]+> f3820f51 vmov\.f32 q0, #-8\.5 @ 0xc1080000
+0[0-9a-f]+ <[^>]+> f3830f51 vmov\.f32 q0, #-17 @ 0xc1880000
+0[0-9a-f]+ <[^>]+> f3840f51 vmov\.f32 q0, #-0\.1328125 @ 0xbe080000
+0[0-9a-f]+ <[^>]+> f3850f51 vmov\.f32 q0, #-0\.265625 @ 0xbe880000
+0[0-9a-f]+ <[^>]+> f3860f51 vmov\.f32 q0, #-0\.53125 @ 0xbf080000
+0[0-9a-f]+ <[^>]+> f3870f51 vmov\.f32 q0, #-1\.0625 @ 0xbf880000
+0[0-9a-f]+ <[^>]+> f3800f52 vmov\.f32 q0, #-2\.25 @ 0xc0100000
+0[0-9a-f]+ <[^>]+> f3810f52 vmov\.f32 q0, #-4\.5 @ 0xc0900000
+0[0-9a-f]+ <[^>]+> f3820f52 vmov\.f32 q0, #-9 @ 0xc1100000
+0[0-9a-f]+ <[^>]+> f3830f52 vmov\.f32 q0, #-18 @ 0xc1900000
+0[0-9a-f]+ <[^>]+> f3840f52 vmov\.f32 q0, #-0\.140625 @ 0xbe100000
+0[0-9a-f]+ <[^>]+> f3850f52 vmov\.f32 q0, #-0\.28125 @ 0xbe900000
+0[0-9a-f]+ <[^>]+> f3860f52 vmov\.f32 q0, #-0\.5625 @ 0xbf100000
+0[0-9a-f]+ <[^>]+> f3870f52 vmov\.f32 q0, #-1\.125 @ 0xbf900000
+0[0-9a-f]+ <[^>]+> f3800f53 vmov\.f32 q0, #-2\.375 @ 0xc0180000
+0[0-9a-f]+ <[^>]+> f3810f53 vmov\.f32 q0, #-4\.75 @ 0xc0980000
+0[0-9a-f]+ <[^>]+> f3820f53 vmov\.f32 q0, #-9\.5 @ 0xc1180000
+0[0-9a-f]+ <[^>]+> f3830f53 vmov\.f32 q0, #-19 @ 0xc1980000
+0[0-9a-f]+ <[^>]+> f3840f53 vmov\.f32 q0, #-0\.1484375 @ 0xbe180000
+0[0-9a-f]+ <[^>]+> f3850f53 vmov\.f32 q0, #-0\.296875 @ 0xbe980000
+0[0-9a-f]+ <[^>]+> f3860f53 vmov\.f32 q0, #-0\.59375 @ 0xbf180000
+0[0-9a-f]+ <[^>]+> f3870f53 vmov\.f32 q0, #-1\.1875 @ 0xbf980000
+0[0-9a-f]+ <[^>]+> f3800f54 vmov\.f32 q0, #-2\.5 @ 0xc0200000
+0[0-9a-f]+ <[^>]+> f3810f54 vmov\.f32 q0, #-5 @ 0xc0a00000
+0[0-9a-f]+ <[^>]+> f3820f54 vmov\.f32 q0, #-10 @ 0xc1200000
+0[0-9a-f]+ <[^>]+> f3830f54 vmov\.f32 q0, #-20 @ 0xc1a00000
+0[0-9a-f]+ <[^>]+> f3840f54 vmov\.f32 q0, #-0\.15625 @ 0xbe200000
+0[0-9a-f]+ <[^>]+> f3850f54 vmov\.f32 q0, #-0\.3125 @ 0xbea00000
+0[0-9a-f]+ <[^>]+> f3860f54 vmov\.f32 q0, #-0\.625 @ 0xbf200000
+0[0-9a-f]+ <[^>]+> f3870f54 vmov\.f32 q0, #-1\.25 @ 0xbfa00000
+0[0-9a-f]+ <[^>]+> f3800f55 vmov\.f32 q0, #-2\.625 @ 0xc0280000
+0[0-9a-f]+ <[^>]+> f3810f55 vmov\.f32 q0, #-5\.25 @ 0xc0a80000
+0[0-9a-f]+ <[^>]+> f3820f55 vmov\.f32 q0, #-10\.5 @ 0xc1280000
+0[0-9a-f]+ <[^>]+> f3830f55 vmov\.f32 q0, #-21 @ 0xc1a80000
+0[0-9a-f]+ <[^>]+> f3840f55 vmov\.f32 q0, #-0\.1640625 @ 0xbe280000
+0[0-9a-f]+ <[^>]+> f3850f55 vmov\.f32 q0, #-0\.328125 @ 0xbea80000
+0[0-9a-f]+ <[^>]+> f3860f55 vmov\.f32 q0, #-0\.65625 @ 0xbf280000
+0[0-9a-f]+ <[^>]+> f3870f55 vmov\.f32 q0, #-1\.3125 @ 0xbfa80000
+0[0-9a-f]+ <[^>]+> f3800f56 vmov\.f32 q0, #-2\.75 @ 0xc0300000
+0[0-9a-f]+ <[^>]+> f3810f56 vmov\.f32 q0, #-5\.5 @ 0xc0b00000
+0[0-9a-f]+ <[^>]+> f3820f56 vmov\.f32 q0, #-11 @ 0xc1300000
+0[0-9a-f]+ <[^>]+> f3830f56 vmov\.f32 q0, #-22 @ 0xc1b00000
+0[0-9a-f]+ <[^>]+> f3840f56 vmov\.f32 q0, #-0\.171875 @ 0xbe300000
+0[0-9a-f]+ <[^>]+> f3850f56 vmov\.f32 q0, #-0\.34375 @ 0xbeb00000
+0[0-9a-f]+ <[^>]+> f3860f56 vmov\.f32 q0, #-0\.6875 @ 0xbf300000
+0[0-9a-f]+ <[^>]+> f3870f56 vmov\.f32 q0, #-1\.375 @ 0xbfb00000
+0[0-9a-f]+ <[^>]+> f3800f57 vmov\.f32 q0, #-2\.875 @ 0xc0380000
+0[0-9a-f]+ <[^>]+> f3810f57 vmov\.f32 q0, #-5\.75 @ 0xc0b80000
+0[0-9a-f]+ <[^>]+> f3820f57 vmov\.f32 q0, #-11\.5 @ 0xc1380000
+0[0-9a-f]+ <[^>]+> f3830f57 vmov\.f32 q0, #-23 @ 0xc1b80000
+0[0-9a-f]+ <[^>]+> f3840f57 vmov\.f32 q0, #-0\.1796875 @ 0xbe380000
+0[0-9a-f]+ <[^>]+> f3850f57 vmov\.f32 q0, #-0\.359375 @ 0xbeb80000
+0[0-9a-f]+ <[^>]+> f3860f57 vmov\.f32 q0, #-0\.71875 @ 0xbf380000
+0[0-9a-f]+ <[^>]+> f3870f57 vmov\.f32 q0, #-1\.4375 @ 0xbfb80000
+0[0-9a-f]+ <[^>]+> f3800f58 vmov\.f32 q0, #-3 @ 0xc0400000
+0[0-9a-f]+ <[^>]+> f3810f58 vmov\.f32 q0, #-6 @ 0xc0c00000
+0[0-9a-f]+ <[^>]+> f3820f58 vmov\.f32 q0, #-12 @ 0xc1400000
+0[0-9a-f]+ <[^>]+> f3830f58 vmov\.f32 q0, #-24 @ 0xc1c00000
+0[0-9a-f]+ <[^>]+> f3840f58 vmov\.f32 q0, #-0\.1875 @ 0xbe400000
+0[0-9a-f]+ <[^>]+> f3850f58 vmov\.f32 q0, #-0\.375 @ 0xbec00000
+0[0-9a-f]+ <[^>]+> f3860f58 vmov\.f32 q0, #-0\.75 @ 0xbf400000
+0[0-9a-f]+ <[^>]+> f3870f58 vmov\.f32 q0, #-1\.5 @ 0xbfc00000
+0[0-9a-f]+ <[^>]+> f3800f59 vmov\.f32 q0, #-3\.125 @ 0xc0480000
+0[0-9a-f]+ <[^>]+> f3810f59 vmov\.f32 q0, #-6\.25 @ 0xc0c80000
+0[0-9a-f]+ <[^>]+> f3820f59 vmov\.f32 q0, #-12\.5 @ 0xc1480000
+0[0-9a-f]+ <[^>]+> f3830f59 vmov\.f32 q0, #-25 @ 0xc1c80000
+0[0-9a-f]+ <[^>]+> f3840f59 vmov\.f32 q0, #-0\.1953125 @ 0xbe480000
+0[0-9a-f]+ <[^>]+> f3850f59 vmov\.f32 q0, #-0\.390625 @ 0xbec80000
+0[0-9a-f]+ <[^>]+> f3860f59 vmov\.f32 q0, #-0\.78125 @ 0xbf480000
+0[0-9a-f]+ <[^>]+> f3870f59 vmov\.f32 q0, #-1\.5625 @ 0xbfc80000
+0[0-9a-f]+ <[^>]+> f3800f5a vmov\.f32 q0, #-3\.25 @ 0xc0500000
+0[0-9a-f]+ <[^>]+> f3810f5a vmov\.f32 q0, #-6\.5 @ 0xc0d00000
+0[0-9a-f]+ <[^>]+> f3820f5a vmov\.f32 q0, #-13 @ 0xc1500000
+0[0-9a-f]+ <[^>]+> f3830f5a vmov\.f32 q0, #-26 @ 0xc1d00000
+0[0-9a-f]+ <[^>]+> f3840f5a vmov\.f32 q0, #-0\.203125 @ 0xbe500000
+0[0-9a-f]+ <[^>]+> f3850f5a vmov\.f32 q0, #-0\.40625 @ 0xbed00000
+0[0-9a-f]+ <[^>]+> f3860f5a vmov\.f32 q0, #-0\.8125 @ 0xbf500000
+0[0-9a-f]+ <[^>]+> f3870f5a vmov\.f32 q0, #-1\.625 @ 0xbfd00000
+0[0-9a-f]+ <[^>]+> f3800f5b vmov\.f32 q0, #-3\.375 @ 0xc0580000
+0[0-9a-f]+ <[^>]+> f3810f5b vmov\.f32 q0, #-6\.75 @ 0xc0d80000
+0[0-9a-f]+ <[^>]+> f3820f5b vmov\.f32 q0, #-13\.5 @ 0xc1580000
+0[0-9a-f]+ <[^>]+> f3830f5b vmov\.f32 q0, #-27 @ 0xc1d80000
+0[0-9a-f]+ <[^>]+> f3840f5b vmov\.f32 q0, #-0\.2109375 @ 0xbe580000
+0[0-9a-f]+ <[^>]+> f3850f5b vmov\.f32 q0, #-0\.421875 @ 0xbed80000
+0[0-9a-f]+ <[^>]+> f3860f5b vmov\.f32 q0, #-0\.84375 @ 0xbf580000
+0[0-9a-f]+ <[^>]+> f3870f5b vmov\.f32 q0, #-1\.6875 @ 0xbfd80000
+0[0-9a-f]+ <[^>]+> f3800f5c vmov\.f32 q0, #-3\.5 @ 0xc0600000
+0[0-9a-f]+ <[^>]+> f3810f5c vmov\.f32 q0, #-7 @ 0xc0e00000
+0[0-9a-f]+ <[^>]+> f3820f5c vmov\.f32 q0, #-14 @ 0xc1600000
+0[0-9a-f]+ <[^>]+> f3830f5c vmov\.f32 q0, #-28 @ 0xc1e00000
+0[0-9a-f]+ <[^>]+> f3840f5c vmov\.f32 q0, #-0\.21875 @ 0xbe600000
+0[0-9a-f]+ <[^>]+> f3850f5c vmov\.f32 q0, #-0\.4375 @ 0xbee00000
+0[0-9a-f]+ <[^>]+> f3860f5c vmov\.f32 q0, #-0\.875 @ 0xbf600000
+0[0-9a-f]+ <[^>]+> f3870f5c vmov\.f32 q0, #-1\.75 @ 0xbfe00000
+0[0-9a-f]+ <[^>]+> f3800f5d vmov\.f32 q0, #-3\.625 @ 0xc0680000
+0[0-9a-f]+ <[^>]+> f3810f5d vmov\.f32 q0, #-7\.25 @ 0xc0e80000
+0[0-9a-f]+ <[^>]+> f3820f5d vmov\.f32 q0, #-14\.5 @ 0xc1680000
+0[0-9a-f]+ <[^>]+> f3830f5d vmov\.f32 q0, #-29 @ 0xc1e80000
+0[0-9a-f]+ <[^>]+> f3840f5d vmov\.f32 q0, #-0\.2265625 @ 0xbe680000
+0[0-9a-f]+ <[^>]+> f3850f5d vmov\.f32 q0, #-0\.453125 @ 0xbee80000
+0[0-9a-f]+ <[^>]+> f3860f5d vmov\.f32 q0, #-0\.90625 @ 0xbf680000
+0[0-9a-f]+ <[^>]+> f3870f5d vmov\.f32 q0, #-1\.8125 @ 0xbfe80000
+0[0-9a-f]+ <[^>]+> f3800f5e vmov\.f32 q0, #-3\.75 @ 0xc0700000
+0[0-9a-f]+ <[^>]+> f3810f5e vmov\.f32 q0, #-7\.5 @ 0xc0f00000
+0[0-9a-f]+ <[^>]+> f3820f5e vmov\.f32 q0, #-15 @ 0xc1700000
+0[0-9a-f]+ <[^>]+> f3830f5e vmov\.f32 q0, #-30 @ 0xc1f00000
+0[0-9a-f]+ <[^>]+> f3840f5e vmov\.f32 q0, #-0\.234375 @ 0xbe700000
+0[0-9a-f]+ <[^>]+> f3850f5e vmov\.f32 q0, #-0\.46875 @ 0xbef00000
+0[0-9a-f]+ <[^>]+> f3860f5e vmov\.f32 q0, #-0\.9375 @ 0xbf700000
+0[0-9a-f]+ <[^>]+> f3870f5e vmov\.f32 q0, #-1\.875 @ 0xbff00000
+0[0-9a-f]+ <[^>]+> f3800f5f vmov\.f32 q0, #-3\.875 @ 0xc0780000
+0[0-9a-f]+ <[^>]+> f3810f5f vmov\.f32 q0, #-7\.75 @ 0xc0f80000
+0[0-9a-f]+ <[^>]+> f3820f5f vmov\.f32 q0, #-15\.5 @ 0xc1780000
+0[0-9a-f]+ <[^>]+> f3830f5f vmov\.f32 q0, #-31 @ 0xc1f80000
+0[0-9a-f]+ <[^>]+> f3840f5f vmov\.f32 q0, #-0\.2421875 @ 0xbe780000
+0[0-9a-f]+ <[^>]+> f3850f5f vmov\.f32 q0, #-0\.484375 @ 0xbef80000
+0[0-9a-f]+ <[^>]+> f3860f5f vmov\.f32 q0, #-0\.96875 @ 0xbf780000
+0[0-9a-f]+ <[^>]+> f3870f5f vmov\.f32 q0, #-1\.9375 @ 0xbff80000
0[0-9a-f]+ <[^>]+> f3879e3f vmov\.i64 d9, #0xffffffffffffffff
diff --git a/gas/testsuite/gas/arm/neon-cov.d b/gas/testsuite/gas/arm/neon-cov.d
index 3d7a4885fe2..a2ad6c0b8bb 100644
--- a/gas/testsuite/gas/arm/neon-cov.d
+++ b/gas/testsuite/gas/arm/neon-cov.d
@@ -278,210 +278,210 @@ Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> f3000150 veor q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000150 veor q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000110 veor d0, d0, d0
-0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820135 vbic\.i32 d0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820335 vbic\.i32 d0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820535 vbic\.i32 d0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820735 vbic\.i32 d0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387033f vbic\.i32 d0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387053f vbic\.i32 d0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f387073f vbic\.i32 d0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f387093f vbic\.i16 d0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f3870b3f vbic\.i16 d0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f2800930 vbic\.i16 d0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820115 vorr\.i32 d0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820315 vorr\.i32 d0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820515 vorr\.i32 d0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820715 vorr\.i32 d0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387031f vorr\.i32 d0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387051f vorr\.i32 d0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f387071f vorr\.i32 d0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f387091f vorr\.i16 d0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f3870b1f vorr\.i16 d0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f2800910 vorr\.i16 d0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820135 vbic\.i32 d0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820335 vbic\.i32 d0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820535 vbic\.i32 d0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820735 vbic\.i32 d0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387033f vbic\.i32 d0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387053f vbic\.i32 d0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f387073f vbic\.i32 d0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f387093f vbic\.i16 d0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f3870b3f vbic\.i16 d0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f2800930 vbic\.i16 d0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820115 vorr\.i32 d0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820315 vorr\.i32 d0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820515 vorr\.i32 d0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820715 vorr\.i32 d0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387031f vorr\.i32 d0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387051f vorr\.i32 d0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f387071f vorr\.i32 d0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f387091f vorr\.i16 d0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f3870b1f vorr\.i16 d0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f2800910 vorr\.i16 d0, #0 ; 0x0000
+0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820135 vbic\.i32 d0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820335 vbic\.i32 d0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820535 vbic\.i32 d0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820735 vbic\.i32 d0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387033f vbic\.i32 d0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387053f vbic\.i32 d0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f387073f vbic\.i32 d0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f387093f vbic\.i16 d0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f3870b3f vbic\.i16 d0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f2800930 vbic\.i16 d0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820115 vorr\.i32 d0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820315 vorr\.i32 d0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820515 vorr\.i32 d0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820715 vorr\.i32 d0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387031f vorr\.i32 d0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387051f vorr\.i32 d0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f387071f vorr\.i32 d0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f387091f vorr\.i16 d0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f3870b1f vorr\.i16 d0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f2800910 vorr\.i16 d0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820135 vbic\.i32 d0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820335 vbic\.i32 d0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820535 vbic\.i32 d0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820735 vbic\.i32 d0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387033f vbic\.i32 d0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387053f vbic\.i32 d0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f387073f vbic\.i32 d0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f387093f vbic\.i16 d0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f3870b3f vbic\.i16 d0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f2800930 vbic\.i16 d0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820115 vorr\.i32 d0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820315 vorr\.i32 d0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820515 vorr\.i32 d0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820715 vorr\.i32 d0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387031f vorr\.i32 d0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387051f vorr\.i32 d0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f387071f vorr\.i32 d0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f387091f vorr\.i16 d0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f3870b1f vorr\.i16 d0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f2800910 vorr\.i16 d0, #0 @ 0x0000
0[0-9a-f]+ <[^>]+> f3100150 vbsl q0, q0, q0
0[0-9a-f]+ <[^>]+> f3100150 vbsl q0, q0, q0
0[0-9a-f]+ <[^>]+> f3100110 vbsl d0, d0, d0
@@ -1153,86 +1153,86 @@ Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> ee900b30 vmov\.u16 r0, d0\[0\]
0[0-9a-f]+ <[^>]+> ee100b10 vmov\.32 r0, d0\[0\]
0[0-9a-f]+ <[^>]+> ec510b10 vmov r0, r1, d0
-0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870257 vmov\.i32 q0, #30464 ; 0x00007700
-0[0-9a-f]+ <[^>]+> f2870217 vmov\.i32 d0, #30464 ; 0x00007700
-0[0-9a-f]+ <[^>]+> f2870277 vmvn\.i32 q0, #30464 ; 0x00007700
-0[0-9a-f]+ <[^>]+> f2870237 vmvn\.i32 d0, #30464 ; 0x00007700
-0[0-9a-f]+ <[^>]+> f2870457 vmov\.i32 q0, #7798784 ; 0x00770000
-0[0-9a-f]+ <[^>]+> f2870417 vmov\.i32 d0, #7798784 ; 0x00770000
-0[0-9a-f]+ <[^>]+> f2870477 vmvn\.i32 q0, #7798784 ; 0x00770000
-0[0-9a-f]+ <[^>]+> f2870437 vmvn\.i32 d0, #7798784 ; 0x00770000
-0[0-9a-f]+ <[^>]+> f2870657 vmov\.i32 q0, #1996488704 ; 0x77000000
-0[0-9a-f]+ <[^>]+> f2870617 vmov\.i32 d0, #1996488704 ; 0x77000000
-0[0-9a-f]+ <[^>]+> f2870677 vmvn\.i32 q0, #1996488704 ; 0x77000000
-0[0-9a-f]+ <[^>]+> f2870637 vmvn\.i32 d0, #1996488704 ; 0x77000000
-0[0-9a-f]+ <[^>]+> f2870857 vmov\.i16 q0, #119 ; 0x0077
-0[0-9a-f]+ <[^>]+> f2870817 vmov\.i16 d0, #119 ; 0x0077
-0[0-9a-f]+ <[^>]+> f2870877 vmvn\.i16 q0, #119 ; 0x0077
-0[0-9a-f]+ <[^>]+> f2870837 vmvn\.i16 d0, #119 ; 0x0077
-0[0-9a-f]+ <[^>]+> f2870a57 vmov\.i16 q0, #30464 ; 0x7700
-0[0-9a-f]+ <[^>]+> f2870a17 vmov\.i16 d0, #30464 ; 0x7700
-0[0-9a-f]+ <[^>]+> f2870a77 vmvn\.i16 q0, #30464 ; 0x7700
-0[0-9a-f]+ <[^>]+> f2870a37 vmvn\.i16 d0, #30464 ; 0x7700
-0[0-9a-f]+ <[^>]+> f2870c57 vmov\.i32 q0, #30719 ; 0x000077ff
-0[0-9a-f]+ <[^>]+> f2870c17 vmov\.i32 d0, #30719 ; 0x000077ff
-0[0-9a-f]+ <[^>]+> f2870c77 vmvn\.i32 q0, #30719 ; 0x000077ff
-0[0-9a-f]+ <[^>]+> f2870c37 vmvn\.i32 d0, #30719 ; 0x000077ff
-0[0-9a-f]+ <[^>]+> f2870d57 vmov\.i32 q0, #7864319 ; 0x0077ffff
-0[0-9a-f]+ <[^>]+> f2870d17 vmov\.i32 d0, #7864319 ; 0x0077ffff
-0[0-9a-f]+ <[^>]+> f2870d77 vmvn\.i32 q0, #7864319 ; 0x0077ffff
-0[0-9a-f]+ <[^>]+> f2870d37 vmvn\.i32 d0, #7864319 ; 0x0077ffff
-0[0-9a-f]+ <[^>]+> f2870e57 vmov\.i8 q0, #119 ; 0x77
-0[0-9a-f]+ <[^>]+> f2870e17 vmov\.i8 d0, #119 ; 0x77
+0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870257 vmov\.i32 q0, #30464 @ 0x00007700
+0[0-9a-f]+ <[^>]+> f2870217 vmov\.i32 d0, #30464 @ 0x00007700
+0[0-9a-f]+ <[^>]+> f2870277 vmvn\.i32 q0, #30464 @ 0x00007700
+0[0-9a-f]+ <[^>]+> f2870237 vmvn\.i32 d0, #30464 @ 0x00007700
+0[0-9a-f]+ <[^>]+> f2870457 vmov\.i32 q0, #7798784 @ 0x00770000
+0[0-9a-f]+ <[^>]+> f2870417 vmov\.i32 d0, #7798784 @ 0x00770000
+0[0-9a-f]+ <[^>]+> f2870477 vmvn\.i32 q0, #7798784 @ 0x00770000
+0[0-9a-f]+ <[^>]+> f2870437 vmvn\.i32 d0, #7798784 @ 0x00770000
+0[0-9a-f]+ <[^>]+> f2870657 vmov\.i32 q0, #1996488704 @ 0x77000000
+0[0-9a-f]+ <[^>]+> f2870617 vmov\.i32 d0, #1996488704 @ 0x77000000
+0[0-9a-f]+ <[^>]+> f2870677 vmvn\.i32 q0, #1996488704 @ 0x77000000
+0[0-9a-f]+ <[^>]+> f2870637 vmvn\.i32 d0, #1996488704 @ 0x77000000
+0[0-9a-f]+ <[^>]+> f2870857 vmov\.i16 q0, #119 @ 0x0077
+0[0-9a-f]+ <[^>]+> f2870817 vmov\.i16 d0, #119 @ 0x0077
+0[0-9a-f]+ <[^>]+> f2870877 vmvn\.i16 q0, #119 @ 0x0077
+0[0-9a-f]+ <[^>]+> f2870837 vmvn\.i16 d0, #119 @ 0x0077
+0[0-9a-f]+ <[^>]+> f2870a57 vmov\.i16 q0, #30464 @ 0x7700
+0[0-9a-f]+ <[^>]+> f2870a17 vmov\.i16 d0, #30464 @ 0x7700
+0[0-9a-f]+ <[^>]+> f2870a77 vmvn\.i16 q0, #30464 @ 0x7700
+0[0-9a-f]+ <[^>]+> f2870a37 vmvn\.i16 d0, #30464 @ 0x7700
+0[0-9a-f]+ <[^>]+> f2870c57 vmov\.i32 q0, #30719 @ 0x000077ff
+0[0-9a-f]+ <[^>]+> f2870c17 vmov\.i32 d0, #30719 @ 0x000077ff
+0[0-9a-f]+ <[^>]+> f2870c77 vmvn\.i32 q0, #30719 @ 0x000077ff
+0[0-9a-f]+ <[^>]+> f2870c37 vmvn\.i32 d0, #30719 @ 0x000077ff
+0[0-9a-f]+ <[^>]+> f2870d57 vmov\.i32 q0, #7864319 @ 0x0077ffff
+0[0-9a-f]+ <[^>]+> f2870d17 vmov\.i32 d0, #7864319 @ 0x0077ffff
+0[0-9a-f]+ <[^>]+> f2870d77 vmvn\.i32 q0, #7864319 @ 0x0077ffff
+0[0-9a-f]+ <[^>]+> f2870d37 vmvn\.i32 d0, #7864319 @ 0x0077ffff
+0[0-9a-f]+ <[^>]+> f2870e57 vmov\.i8 q0, #119 @ 0x77
+0[0-9a-f]+ <[^>]+> f2870e17 vmov\.i8 d0, #119 @ 0x77
0[0-9a-f]+ <[^>]+> f3810e71 vmov\.i64 q0, #0xff0000ff000000ff
0[0-9a-f]+ <[^>]+> f3810e31 vmov\.i64 d0, #0xff0000ff000000ff
-0[0-9a-f]+ <[^>]+> f2810f51 vmov\.f32 q0, #4\.25 ; 0x40880000
-0[0-9a-f]+ <[^>]+> f2810f11 vmov\.f32 d0, #4\.25 ; 0x40880000
-0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 ; 0xa5
-0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 ; 0xa5
-0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 ; 0x5a
-0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 ; 0x5a
-0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 ; 0xa5
-0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 ; 0xa5
-0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 ; 0x5a
-0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 ; 0x5a
-0[0-9a-f]+ <[^>]+> f3820855 vmov\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820815 vmov\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820a55 vmov\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820a15 vmov\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 ; 0xa5
-0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 ; 0xa5
-0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 ; 0x5a
-0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 ; 0x5a
-0[0-9a-f]+ <[^>]+> f3820855 vmov\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820815 vmov\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820a55 vmov\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820a15 vmov\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820055 vmov\.i32 q0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820015 vmov\.i32 d0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820255 vmov\.i32 q0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820215 vmov\.i32 d0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820455 vmov\.i32 q0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820415 vmov\.i32 d0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820655 vmov\.i32 q0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820615 vmov\.i32 d0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820c55 vmov\.i32 q0, #42495 ; 0x0000a5ff
-0[0-9a-f]+ <[^>]+> f3820c15 vmov\.i32 d0, #42495 ; 0x0000a5ff
-0[0-9a-f]+ <[^>]+> f3820d55 vmov\.i32 q0, #10878975 ; 0x00a5ffff
-0[0-9a-f]+ <[^>]+> f3820d15 vmov\.i32 d0, #10878975 ; 0x00a5ffff
-0[0-9a-f]+ <[^>]+> f285067a vmvn\.i32 q0, #1509949440 ; 0x5a000000
-0[0-9a-f]+ <[^>]+> f285063a vmvn\.i32 d0, #1509949440 ; 0x5a000000
+0[0-9a-f]+ <[^>]+> f2810f51 vmov\.f32 q0, #4\.25 @ 0x40880000
+0[0-9a-f]+ <[^>]+> f2810f11 vmov\.f32 d0, #4\.25 @ 0x40880000
+0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 @ 0xa5
+0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 @ 0xa5
+0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 @ 0x5a
+0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 @ 0x5a
+0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 @ 0xa5
+0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 @ 0xa5
+0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 @ 0x5a
+0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 @ 0x5a
+0[0-9a-f]+ <[^>]+> f3820855 vmov\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820815 vmov\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820a55 vmov\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820a15 vmov\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 @ 0xa5
+0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 @ 0xa5
+0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 @ 0x5a
+0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 @ 0x5a
+0[0-9a-f]+ <[^>]+> f3820855 vmov\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820815 vmov\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820a55 vmov\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820a15 vmov\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820055 vmov\.i32 q0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820015 vmov\.i32 d0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820255 vmov\.i32 q0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820215 vmov\.i32 d0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820455 vmov\.i32 q0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820415 vmov\.i32 d0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820655 vmov\.i32 q0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820615 vmov\.i32 d0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820c55 vmov\.i32 q0, #42495 @ 0x0000a5ff
+0[0-9a-f]+ <[^>]+> f3820c15 vmov\.i32 d0, #42495 @ 0x0000a5ff
+0[0-9a-f]+ <[^>]+> f3820d55 vmov\.i32 q0, #10878975 @ 0x00a5ffff
+0[0-9a-f]+ <[^>]+> f3820d15 vmov\.i32 d0, #10878975 @ 0x00a5ffff
+0[0-9a-f]+ <[^>]+> f285067a vmvn\.i32 q0, #1509949440 @ 0x5a000000
+0[0-9a-f]+ <[^>]+> f285063a vmvn\.i32 d0, #1509949440 @ 0x5a000000
0[0-9a-f]+ <[^>]+> f3b005c0 vmvn q0, q0
0[0-9a-f]+ <[^>]+> f3b005c0 vmvn q0, q0
0[0-9a-f]+ <[^>]+> f3b00580 vmvn d0, d0
diff --git a/gas/testsuite/gas/arm/neon-ldst-rm.d b/gas/testsuite/gas/arm/neon-ldst-rm.d
index 813672cd7bc..677ae2a7af5 100644
--- a/gas/testsuite/gas/arm/neon-ldst-rm.d
+++ b/gas/testsuite/gas/arm/neon-ldst-rm.d
@@ -46,7 +46,7 @@ Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> ed628b10 vstmdb r2!, {d24-d31}
0[0-9a-f]+ <[^>]+> ed223b20 vstmdb r2!, {d3-d18}
0[0-9a-f]+ <backward> 000001f4 .*
-0[0-9a-f]+ <[^>]+> eddf6b0b vldr d22, \[pc, #44\] ; 0[0-9a-f]+ <forward>
+0[0-9a-f]+ <[^>]+> eddf6b0b vldr d22, \[pc, #44\] @ 0[0-9a-f]+ <forward>
0[0-9a-f]+ <[^>]+> ed935b00 vldr d5, \[r3\]
0[0-9a-f]+ <[^>]+> ed135b01 vldr d5, \[r3, #-4\]
0[0-9a-f]+ <[^>]+> ed935b01 vldr d5, \[r3, #4\]
@@ -60,4 +60,4 @@ Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> ed035b40 vstr d5, \[r3, #-256\].*
0[0-9a-f]+ <[^>]+> ed835b40 vstr d5, \[r3, #256\].*
0[0-9a-f]+ <forward> 000002bc .*
-0[0-9a-f]+ <[^>]+> ed1f7b11 vldr d7, \[pc, #-68\] ; 0[0-9a-f]+ <backward>
+0[0-9a-f]+ <[^>]+> ed1f7b11 vldr d7, \[pc, #-68\] @ 0[0-9a-f]+ <backward>
diff --git a/gas/testsuite/gas/arm/neon-logic.d b/gas/testsuite/gas/arm/neon-logic.d
index 8e997fac166..c2e59f10535 100644
--- a/gas/testsuite/gas/arm/neon-logic.d
+++ b/gas/testsuite/gas/arm/neon-logic.d
@@ -6,11 +6,11 @@
Disassembly of section \.text:
-00000000 <.text> f387015f vorr.i32 q0, #255 ; 0x000000ff
-00000004 <.text\+0x4> f387015f vorr.i32 q0, #255 ; 0x000000ff
+00000000 <.text> f387015f vorr.i32 q0, #255 @ 0x000000ff
+00000004 <.text\+0x4> f387015f vorr.i32 q0, #255 @ 0x000000ff
00000008 <.text\+0x8> f2220154 vorr q0, q1, q2
0000000c <.text\+0xc> f2200152 vorr q0, q0, q1
-00000010 <.text\+0x10> f387011f vorr.i32 d0, #255 ; 0x000000ff
-00000014 <.text\+0x14> f387011f vorr.i32 d0, #255 ; 0x000000ff
+00000010 <.text\+0x10> f387011f vorr.i32 d0, #255 @ 0x000000ff
+00000014 <.text\+0x14> f387011f vorr.i32 d0, #255 @ 0x000000ff
00000018 <.text\+0x18> f2210112 vorr d0, d1, d2
0000001c <.text\+0x1c> f2200111 vorr d0, d0, d1
diff --git a/gas/testsuite/gas/arm/nops.d b/gas/testsuite/gas/arm/nops.d
index dc146069e51..bda0c307dce 100644
--- a/gas/testsuite/gas/arm/nops.d
+++ b/gas/testsuite/gas/arm/nops.d
@@ -7,6 +7,6 @@
Disassembly of section \.text:
0+000 <[^>]*> 0320f000 ? nopeq \{0\}
0+004 <[^>]*> 7320f000 ? nopvc \{0\}
-0+008 <[^>]*> 7320d700 ? nopvc \{0\} ; <UNPREDICTABLE>
+0+008 <[^>]*> 7320d700 ? nopvc \{0\} @ <UNPREDICTABLE>
diff --git a/gas/testsuite/gas/arm/offset-1.d b/gas/testsuite/gas/arm/offset-1.d
index bec9386fe98..0b8ee51d6b3 100644
--- a/gas/testsuite/gas/arm/offset-1.d
+++ b/gas/testsuite/gas/arm/offset-1.d
@@ -5,14 +5,14 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0+00 <[^>]+> e51f0000 ? ldr r0, \[pc, #-0\] ; 0+8 <[^>]+>
-0+04 <[^>]+> e59f0000 ? ldr r0, \[pc\] ; 0+c <[^>]+>
+0+00 <[^>]+> e51f0000 ? ldr r0, \[pc, #-0\] @ 0+8 <[^>]+>
+0+04 <[^>]+> e59f0000 ? ldr r0, \[pc\] @ 0+c <[^>]+>
0+08 <[^>]+> e5110000 ? ldr r0, \[r1, #-0\]
0+0c <[^>]+> e5910000 ? ldr r0, \[r1\]
0+10 <[^>]+> e4110000 ? ldr r0, \[r1\], #-0
0+14 <[^>]+> e4910000 ? ldr r0, \[r1\], #0
-0+18 <[^>]+> e15f00b0 ? ldrh r0, \[pc, #-0\] ; 0+20 <[^>]+>
-0+1c <[^>]+> e1df00b0 ? ldrh r0, \[pc\] ; 0+24 <[^>]+>
+0+18 <[^>]+> e15f00b0 ? ldrh r0, \[pc, #-0\] @ 0+20 <[^>]+>
+0+1c <[^>]+> e1df00b0 ? ldrh r0, \[pc\] @ 0+24 <[^>]+>
0+20 <[^>]+> e15100b0 ? ldrh r0, \[r1, #-0\]
0+24 <[^>]+> e1d100b0 ? ldrh r0, \[r1\]
0+28 <[^>]+> e05100b0 ? ldrh r0, \[r1\], #-0
diff --git a/gas/testsuite/gas/arm/offset.d b/gas/testsuite/gas/arm/offset.d
index 1795477f05d..8c58c29414a 100644
--- a/gas/testsuite/gas/arm/offset.d
+++ b/gas/testsuite/gas/arm/offset.d
@@ -5,7 +5,7 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0+0 <[^>]+> e51f0004 ? ldr r0, \[pc, #-4\] ; 0+4 <[^>]+>
-0+4 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
-0+8 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
-0+c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
+0+0 <[^>]+> e51f0004 ? ldr r0, \[pc, #-4\] @ 0+4 <[^>]+>
+0+4 <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
+0+8 <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
+0+c <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/pr21458.d b/gas/testsuite/gas/arm/pr21458.d
index b567d847ddd..bc76c647df4 100644
--- a/gas/testsuite/gas/arm/pr21458.d
+++ b/gas/testsuite/gas/arm/pr21458.d
@@ -9,20 +9,20 @@
Disassembly of section .text:
0+00000 <.*> 4770[ ]+bx[ ]+lr
-0+00002 <.*> 46c0[ ]+nop[ ]+; \(mov r8, r8\)
+0+00002 <.*> 46c0[ ]+nop[ ]+@ \(mov r8, r8\)
0+00004 <.*> e12fff1e[ ]+bx[ ]+lr
0+00008 <.*> f2af 000b[ ]+subw[ ]+r0, pc, #11
0+0000c <.*> 4780[ ]+blx[ ]+r0
0+0000e <.*> f2af 020c[ ]+subw[ ]+r2, pc, #12
0+00012 <.*> 4790[ ]+blx[ ]+r2
0+00014 <.*> e24f401b[ ]+sub[ ]+r4, pc, #27
-0+00018 <.*> e1a00000[ ]+nop[ ]+; \(mov r0, r0\)
+0+00018 <.*> e1a00000[ ]+nop[ ]+@ \(mov r0, r0\)
0+0001c <.*> e12fff34[ ]+blx[ ]+r4
-0+00020 <.*> e24f6024[ ]+sub[ ]+r6, pc, #36[ ]+; 0x24
-0+00024 <.*> e1a00000[ ]+nop[ ]+; \(mov r0, r0\)
+0+00020 <.*> e24f6024[ ]+sub[ ]+r6, pc, #36[ ]+@ 0x24
+0+00024 <.*> e1a00000[ ]+nop[ ]+@ \(mov r0, r0\)
0+00028 <.*> e12fff36[ ]+blx[ ]+r6
-0+0002c <.*> e24f8033[ ]+sub[ ]+r8, pc, #51[ ]+; 0x33
+0+0002c <.*> e24f8033[ ]+sub[ ]+r8, pc, #51[ ]+@ 0x33
0+00030 <.*> e12fff38[ ]+blx[ ]+r8
-0+00034 <.*> e24fa038[ ]+sub[ ]+sl, pc, #56[ ]+; 0x38
+0+00034 <.*> e24fa038[ ]+sub[ ]+sl, pc, #56[ ]+@ 0x38
0+00038 <.*> e12fff3a[ ]+blx[ ]+sl
-0+0003c <.*> 324fc043[ ]+subcc[ ]+ip, pc, #67[ ]+; 0x43
+0+0003c <.*> 324fc043[ ]+subcc[ ]+ip, pc, #67[ ]+@ 0x43
diff --git a/gas/testsuite/gas/arm/pr24907.d b/gas/testsuite/gas/arm/pr24907.d
index 8268d4bdc15..905395dcf2d 100644
--- a/gas/testsuite/gas/arm/pr24907.d
+++ b/gas/testsuite/gas/arm/pr24907.d
@@ -9,11 +9,11 @@
Disassembly of section \.text:
0+000 <foo>:
- 0: 46c0 nop ; .*
+ 0: 46c0 nop @ .*
2: f7ff fffe bl 0 <log_func>
6: e002 b\.n e <func\+0x2>
8: f7ff fffe bl c <func>
0+000c <func>:
- c: 46c0 nop ; .*
- e: 46c0 nop ; .*
+ c: 46c0 nop @ .*
+ e: 46c0 nop @ .*
diff --git a/gas/testsuite/gas/arm/pr25235.d b/gas/testsuite/gas/arm/pr25235.d
index 12695038701..aa71bd8cd4a 100644
--- a/gas/testsuite/gas/arm/pr25235.d
+++ b/gas/testsuite/gas/arm/pr25235.d
@@ -7,18 +7,18 @@
Disassembly of section .text:
00000000 <f1>:
- 0: 46c0 nop ; \(mov r8, r8\)
- 2: 46c0 nop ; \(mov r8, r8\)
+ 0: 46c0 nop @ \(mov r8, r8\)
+ 2: 46c0 nop @ \(mov r8, r8\)
00000004 <f2>:
4: f2af 0107 subw r1, pc, #7
8: f20f 0305 addw r3, pc, #5
- c: a401 add r4, pc, #4 ; \(adr r4, 14 <f4>\)
- e: 46c0 nop ; \(mov r8, r8\)
+ c: a401 add r4, pc, #4 @ \(adr r4, 14 <f4>\)
+ e: 46c0 nop @ \(mov r8, r8\)
00000010 <f3>:
- 10: 46c0 nop ; \(mov r8, r8\)
- 12: 46c0 nop ; \(mov r8, r8\)
+ 10: 46c0 nop @ \(mov r8, r8\)
+ 12: 46c0 nop @ \(mov r8, r8\)
00000014 <f4>:
- 14: e1a00000 nop ; \(mov r0, r0\)
+ 14: e1a00000 nop @ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/push-pop.d b/gas/testsuite/gas/arm/push-pop.d
index 6eabbfaf1ce..ee923e9216f 100644
--- a/gas/testsuite/gas/arm/push-pop.d
+++ b/gas/testsuite/gas/arm/push-pop.d
@@ -6,9 +6,9 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0+000 <.*> e52d0004 push {r0} ; \(str r0, \[sp, #-4\]!\)
+0+000 <.*> e52d0004 push {r0} @ \(str r0, \[sp, #-4\]!\)
0+004 <.*> e92d000e push {r1, r2, r3}
-0+008 <.*> e52d9004 push {r9} ; \(str r9, \[sp, #-4\]!\)
-0+00c <.*> e49d9004 pop {r9} ; \(ldr r9, \[sp\], #4\)
+0+008 <.*> e52d9004 push {r9} @ \(str r9, \[sp, #-4\]!\)
+0+00c <.*> e49d9004 pop {r9} @ \(ldr r9, \[sp\], #4\)
0+010 <.*> e8bd000e pop {r1, r2, r3}
-0+014 <.*> e49d0004 pop {r0} ; \(ldr r0, \[sp\], #4\)
+0+014 <.*> e49d0004 pop {r0} @ \(ldr r0, \[sp\], #4\)
diff --git a/gas/testsuite/gas/arm/reg-alias.d b/gas/testsuite/gas/arm/reg-alias.d
index 06e87d83755..c3eabe1a426 100644
--- a/gas/testsuite/gas/arm/reg-alias.d
+++ b/gas/testsuite/gas/arm/reg-alias.d
@@ -5,6 +5,6 @@
Disassembly of section .text:
0+0 <.*> ee060f10 mcr 15, 0, r0, cr6, cr0, \{0\}
-0+4 <.*> e1a00000 nop ; \(mov r0, r0\)
-0+8 <.*> e1a00000 nop ; \(mov r0, r0\)
-0+c <.*> e1a00000 nop ; \(mov r0, r0\)
+0+4 <.*> e1a00000 nop @ \(mov r0, r0\)
+0+8 <.*> e1a00000 nop @ \(mov r0, r0\)
+0+c <.*> e1a00000 nop @ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/relax_branch_align.d b/gas/testsuite/gas/arm/relax_branch_align.d
index e19857a5876..2d76970452c 100644
--- a/gas/testsuite/gas/arm/relax_branch_align.d
+++ b/gas/testsuite/gas/arm/relax_branch_align.d
@@ -4,10 +4,10 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0+000 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+000 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+002 <[^>]+> f000 8080 beq.w 0+106 <[^>]*>
-0+006 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+006 <[^>]+> 46c0 nop @ \(mov r8, r8\)
#...
-0+100 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+100 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+102 <[^>]+> f47f af80 bne.w 0+006 <[^>]*>
-0+106 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+106 <[^>]+> 46c0 nop @ \(mov r8, r8\)
diff --git a/gas/testsuite/gas/arm/relax_load_align.d b/gas/testsuite/gas/arm/relax_load_align.d
index 776fc3bb473..38ab6c136af 100644
--- a/gas/testsuite/gas/arm/relax_load_align.d
+++ b/gas/testsuite/gas/arm/relax_load_align.d
@@ -4,6 +4,6 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0+000 <[^>]+> f510 707a adds.w r0, r0, #1000 ; 0x3e8
-0+004 <[^>]+> 4800 ldr r0, \[pc, #0\] ; \(0+008 <[^>]+>\)
-0+006 <[^>]+> 4800 ldr r0, \[pc, #0\] ; \(0+008 <[^>]+>\)
+0+000 <[^>]+> f510 707a adds.w r0, r0, #1000 @ 0x3e8
+0+004 <[^>]+> 4800 ldr r0, \[pc, #0\] @ \(0+008 <[^>]+>\)
+0+006 <[^>]+> 4800 ldr r0, \[pc, #0\] @ \(0+008 <[^>]+>\)
diff --git a/gas/testsuite/gas/arm/sp-pc-usage-t.d b/gas/testsuite/gas/arm/sp-pc-usage-t.d
index c9b0800223a..35ed7bfb735 100644
--- a/gas/testsuite/gas/arm/sp-pc-usage-t.d
+++ b/gas/testsuite/gas/arm/sp-pc-usage-t.d
@@ -15,13 +15,13 @@ Disassembly of section .text:
00000016 <foo\+0x16> ebad 0d00 sub.w sp, sp, r0
0000001a <foo\+0x1a> ebad 0d40 sub.w sp, sp, r0, lsl #1
0000001e <foo\+0x1e> 9800 ldr r0, \[sp, #0\]
-00000020 <foo\+0x20> 4800 ldr r0, \[pc, #0\] ; \(00000024 <foo\+0x24>\)
+00000020 <foo\+0x20> 4800 ldr r0, \[pc, #0\] @ \(00000024 <foo\+0x24>\)
00000022 <foo\+0x22> f8d0 f000 ldr.w pc, \[r0\]
00000026 <foo\+0x26> f8d0 d000 ldr.w sp, \[r0\]
-0000002a <foo\+0x2a> f8df f000 ldr.w pc, \[pc\] ; 0000002c <foo\+0x2c>
+0000002a <foo\+0x2a> f8df f000 ldr.w pc, \[pc\] @ 0000002c <foo\+0x2c>
0000002e <foo\+0x2e> f8dd d000 ldr.w sp, \[sp\]
00000032 <foo\+0x32> f8dd f000 ldr.w pc, \[sp\]
-00000036 <foo\+0x36> f8df d000 ldr.w sp, \[pc\] ; 00000038 <foo\+0x38>
+00000036 <foo\+0x36> f8df d000 ldr.w sp, \[pc\] @ 00000038 <foo\+0x38>
0000003a <foo\+0x3a> 9000 str r0, \[sp, #0\]
0000003c <foo\+0x3c> f8c0 d000 str.w sp, \[r0\]
00000040 <foo\+0x40> f8cd d000 str.w sp, \[sp\]
@@ -70,7 +70,7 @@ Disassembly of section .text:
000000d4 <foo\+0xd4> ebbd 0040 subs.w r0, sp, r0, lsl #1
000000d8 <foo\+0xd8> ebad 0d40 sub.w sp, sp, r0, lsl #1
000000dc <foo\+0xdc> ebbd 0d40 subs.w sp, sp, r0, lsl #1
-000000e0 <foo\+0xe0> a001 add r0, pc, #4 ; \(adr r0, 000000e8 <foo\+0xe8>\)
+000000e0 <foo\+0xe0> a001 add r0, pc, #4 @ \(adr r0, 000000e8 <foo\+0xe8>\)
000000e2 <foo\+0xe2> f2af 0004 subw r0, pc, #4
000000e6 <foo\+0xe6> f20f 0004 addw r0, pc, #4
000000ea <foo\+0xea> f2af 0004 subw r0, pc, #4
diff --git a/gas/testsuite/gas/arm/tcompat.d b/gas/testsuite/gas/arm/tcompat.d
index 6e378bfb4ed..c0e74de01a2 100644
--- a/gas/testsuite/gas/arm/tcompat.d
+++ b/gas/testsuite/gas/arm/tcompat.d
@@ -47,8 +47,8 @@ Disassembly of section .text:
0+90 <[^>]*> e1800001 ? orr r0, r0, r1
0+94 <[^>]*> e1c00001 ? bic r0, r0, r1
0+98 <[^>]*> e0000091 ? mul r0, r1, r0
-0+9c <[^>]*> e1a00000 ? nop ; \(mov r0, r0\)
+0+9c <[^>]*> e1a00000 ? nop @ \(mov r0, r0\)
0+a0 <[^>]*> e1a00069 ? rrx r0, r9
0+a4 <[^>]*> e1b09060 ? rrxs r9, r0
-0+a8 <[^>]*> e1a00000 ? nop ; \(mov r0, r0\)
-0+ac <[^>]*> e1a00000 ? nop ; \(mov r0, r0\)
+0+a8 <[^>]*> e1a00000 ? nop @ \(mov r0, r0\)
+0+ac <[^>]*> e1a00000 ? nop @ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/tcompat2.d b/gas/testsuite/gas/arm/tcompat2.d
index 4c6de6160ad..4c28add90bd 100644
--- a/gas/testsuite/gas/arm/tcompat2.d
+++ b/gas/testsuite/gas/arm/tcompat2.d
@@ -20,7 +20,7 @@ Disassembly of section .text:
0+12 <[^>]*> 4308 * orrs r0, r1
0+14 <[^>]*> 4388 * bics r0, r1
0+16 <[^>]*> 4188 * sbcs r0, r1
-0+18 <[^>]*> 46c0 * nop ; \(mov r8, r8\)
-0+1a <[^>]*> 46c0 * nop ; \(mov r8, r8\)
-0+1c <[^>]*> 46c0 * nop ; \(mov r8, r8\)
-0+1e <[^>]*> 46c0 * nop ; \(mov r8, r8\)
+0+18 <[^>]*> 46c0 * nop @ \(mov r8, r8\)
+0+1a <[^>]*> 46c0 * nop @ \(mov r8, r8\)
+0+1c <[^>]*> 46c0 * nop @ \(mov r8, r8\)
+0+1e <[^>]*> 46c0 * nop @ \(mov r8, r8\)
diff --git a/gas/testsuite/gas/arm/thumb-eabi.d b/gas/testsuite/gas/arm/thumb-eabi.d
index c7c8e322273..457e8cc9c20 100644
--- a/gas/testsuite/gas/arm/thumb-eabi.d
+++ b/gas/testsuite/gas/arm/thumb-eabi.d
@@ -47,18 +47,18 @@ Disassembly of section \.text:
0+04a <[^>]+> 45f4 cmp ip, lr
0+04c <[^>]+> 4648 mov r0, r9
0+04e <[^>]+> 46a1 mov r9, r4
-0+050 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+050 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+052 <[^>]+> 4738 bx r7
0+054 <[^>]+> 4740 bx r8
-0+056 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+056 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+058 <[^>]+> 4778 bx pc
-0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] ; \(0+0dc <[^>]+>\)
-0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] ; \(0+068 <[^>]+>\)
+0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] @ \(0+0dc <[^>]+>\)
+0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] @ \(0+068 <[^>]+>\)
0+05e <[^>]+> 5088 str r0, \[r1, r2\]
0+060 <[^>]+> 5511 strb r1, \[r2, r4\]
0+062 <[^>]+> 59f5 ldr r5, \[r6, r7\]
0+064 <[^>]+> 5d62 ldrb r2, \[r4, r5\]
-0+066 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+066 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+068 <[^>]+> 52d1 strh r1, \[r2, r3\]
0+06a <[^>]+> 5a23 ldrh r3, \[r4, r0\]
0+06c <[^>]+> 57f1 ldrsb r1, \[r6, r7\]
@@ -75,7 +75,7 @@ Disassembly of section \.text:
0+082 <[^>]+> 93ff str r3, \[sp, #1020\].*
0+084 <[^>]+> 990b ldr r1, \[sp, #44\].*
0+086 <[^>]+> 9a00 ldr r2, \[sp, #0\]
-0+088 <[^>]+> a7ff add r7, pc, #1020 ; \(adr r7, 0+488 <[^>]+>\)
+0+088 <[^>]+> a7ff add r7, pc, #1020 @ \(adr r7, 0+488 <[^>]+>\)
0+08a <[^>]+> ac80 add r4, sp, #512.*
0+08c <[^>]+> b043 add sp, #268.*
0+08e <[^>]+> b09a sub sp, #104.*
@@ -111,16 +111,16 @@ Disassembly of section \.text:
0+0ca <[^>]+> b07f add sp, #508.*
0+0cc <[^>]+> b0ff sub sp, #508.*
0+0ce <[^>]+> a8ff add r0, sp, #1020.*
-0+0d0 <[^>]+> a0ff add r0, pc, #1020 ; \(adr r0, 0+4d0 <[^>]+>\)
+0+0d0 <[^>]+> a0ff add r0, pc, #1020 @ \(adr r0, 0+4d0 <[^>]+>\)
0+0d2 <[^>]+> b01a add sp, #104.*
0+0d4 <[^>]+> b09a sub sp, #104.*
0+0d6 <[^>]+> a81a add r0, sp, #104.*
-0+0d8 <[^>]+> a01a add r0, pc, #104 ; \(adr r0, 0+144 <[^>]+>\)
+0+0d8 <[^>]+> a01a add r0, pc, #104 @ \(adr r0, 0+144 <[^>]+>\)
0+0da <[^>]+> 3168 adds r1, #104.*
0+0dc <[^>]+> 2668 movs r6, #104.*
0+0de <[^>]+> 2f68 cmp r7, #104.*
-0+0e0 <[^>]+> 46c0 nop ; \(mov r8, r8\)
-0+0e2 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+0e0 <[^>]+> 46c0 nop @ \(mov r8, r8\)
+0+0e2 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+0e4 <[^>]+> eafffffe b 0+0e4 <[^>]+>
0+0e8 <[^>]+> ea000011 b 0+134 <[^>]+>
0+0ec <[^>]+> ebfffffc bl 0+0e4 <[^>]+>
@@ -128,14 +128,14 @@ Disassembly of section \.text:
0+0f4 <[^>]+> e12fff10 bx r0
.*: R_ARM_V4BX.*
0+0f8 <[^>]+> ef123456 (swi|svc) 0x00123456
-0+0fc <[^>]+> a004 add r0, pc, #16 ; \(adr r0, 0+110 <[^>]+>\)
+0+0fc <[^>]+> a004 add r0, pc, #16 @ \(adr r0, 0+110 <[^>]+>\)
0+0fe <[^>]+> e77f b.n 0+000 <[^>]+>
0+100 <[^>]+> e018 b.n 0+134 <[^>]+>
0+102 <[^>]+> f7ff ff7d bl 0+000 <[^>]+>
0+106 <[^>]+> f000 f815 bl 0+134 <[^>]+>
0+10a <[^>]+> 4700 bx r0
0+10c <[^>]+> dfff (swi|svc) 255.*
-0+10e <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+10e <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+110 <[^>]+> d010 beq.n 0+134 <[^>]+>
0+112 <[^>]+> d10f bne.n 0+134 <[^>]+>
0+114 <[^>]+> d20e bcs.n 0+134 <[^>]+>
@@ -157,14 +157,14 @@ Disassembly of section \.text:
0+134 <[^>]+> f000 fc00 bl 0+938 <[^>]+>
\.\.\.
0+938 <[^>]+> f7ff fbfc bl 0+134 <[^>]+>
-0+93c <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+944 <[^>]+>\)
-0+93e <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+944 <[^>]+>\)
-0+940 <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+948 <[^>]+>\)
-0+942 <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+948 <[^>]+>\)
+0+93c <[^>]+> 4801 ldr r0, \[pc, #4\] @ \(0+944 <[^>]+>\)
+0+93e <[^>]+> 4801 ldr r0, \[pc, #4\] @ \(0+944 <[^>]+>\)
+0+940 <[^>]+> 4801 ldr r0, \[pc, #4\] @ \(0+948 <[^>]+>\)
+0+942 <[^>]+> 4801 ldr r0, \[pc, #4\] @ \(0+948 <[^>]+>\)
0+944 <[^>]+> 1c08 adds r0, r1, #0
-0+946 <[^>]+> 46c0 nop ; \(mov r8, r8\)
-0+948 <[^>]+> a001 add r0, pc, #4 ; \(adr r0, 00000950 <[^>]+>\)
-0+94a <[^>]+> a001 add r0, pc, #4 ; \(adr r0, 00000950 <[^>]+>\)
-0+94c <[^>]+> a000 add r0, pc, #0 ; \(adr r0, 00000950 <[^>]+>\)
-0+94e <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+946 <[^>]+> 46c0 nop @ \(mov r8, r8\)
+0+948 <[^>]+> a001 add r0, pc, #4 @ \(adr r0, 00000950 <[^>]+>\)
+0+94a <[^>]+> a001 add r0, pc, #4 @ \(adr r0, 00000950 <[^>]+>\)
+0+94c <[^>]+> a000 add r0, pc, #0 @ \(adr r0, 00000950 <[^>]+>\)
+0+94e <[^>]+> 46c0 nop @ \(mov r8, r8\)
#pass
diff --git a/gas/testsuite/gas/arm/thumb-nop.d b/gas/testsuite/gas/arm/thumb-nop.d
index 648ed986a30..9c50181d7f0 100644
--- a/gas/testsuite/gas/arm/thumb-nop.d
+++ b/gas/testsuite/gas/arm/thumb-nop.d
@@ -7,5 +7,5 @@
.*: +file format .*arm.*
Disassembly of section \.text:
-0+000 <[^>]+> 46c0 nop ; \(mov r8, r8\)
-0+002 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+000 <[^>]+> 46c0 nop @ \(mov r8, r8\)
+0+002 <[^>]+> 46c0 nop @ \(mov r8, r8\)
diff --git a/gas/testsuite/gas/arm/thumb.d b/gas/testsuite/gas/arm/thumb.d
index 1ac12736bd4..3df33a93156 100644
--- a/gas/testsuite/gas/arm/thumb.d
+++ b/gas/testsuite/gas/arm/thumb.d
@@ -48,18 +48,18 @@ Disassembly of section \.text:
0+04a <[^>]+> 45f4 cmp ip, lr
0+04c <[^>]+> 4648 mov r0, r9
0+04e <[^>]+> 46a1 mov r9, r4
-0+050 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+050 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+052 <[^>]+> 4738 bx r7
0+054 <[^>]+> 4740 bx r8
-0+056 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+056 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+058 <[^>]+> 4778 bx pc
-0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] ; \(0+0dc <[^>]+>\)
-0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] ; \(0+068 <[^>]+>\)
+0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] @ \(0+0dc <[^>]+>\)
+0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] @ \(0+068 <[^>]+>\)
0+05e <[^>]+> 5088 str r0, \[r1, r2\]
0+060 <[^>]+> 5511 strb r1, \[r2, r4\]
0+062 <[^>]+> 59f5 ldr r5, \[r6, r7\]
0+064 <[^>]+> 5d62 ldrb r2, \[r4, r5\]
-0+066 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+066 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+068 <[^>]+> 52d1 strh r1, \[r2, r3\]
0+06a <[^>]+> 5a23 ldrh r3, \[r4, r0\]
0+06c <[^>]+> 57f1 ldrsb r1, \[r6, r7\]
@@ -76,7 +76,7 @@ Disassembly of section \.text:
0+082 <[^>]+> 93ff str r3, \[sp, #1020\].*
0+084 <[^>]+> 990b ldr r1, \[sp, #44\].*
0+086 <[^>]+> 9a00 ldr r2, \[sp, #0\]
-0+088 <[^>]+> a7ff add r7, pc, #1020 ; \(adr r7, 0+488 <[^>]+>\)
+0+088 <[^>]+> a7ff add r7, pc, #1020 @ \(adr r7, 0+488 <[^>]+>\)
0+08a <[^>]+> ac80 add r4, sp, #512.*
0+08c <[^>]+> b043 add sp, #268.*
0+08e <[^>]+> b09a sub sp, #104.*
@@ -112,30 +112,30 @@ Disassembly of section \.text:
0+0ca <[^>]+> b07f add sp, #508.*
0+0cc <[^>]+> b0ff sub sp, #508.*
0+0ce <[^>]+> a8ff add r0, sp, #1020.*
-0+0d0 <[^>]+> a0ff add r0, pc, #1020 ; \(adr r0, 0+4d0 <[^>]+>\)
+0+0d0 <[^>]+> a0ff add r0, pc, #1020 @ \(adr r0, 0+4d0 <[^>]+>\)
0+0d2 <[^>]+> b01a add sp, #104.*
0+0d4 <[^>]+> b09a sub sp, #104.*
0+0d6 <[^>]+> a81a add r0, sp, #104.*
-0+0d8 <[^>]+> a01a add r0, pc, #104 ; \(adr r0, 0+144 <[^>]+>\)
+0+0d8 <[^>]+> a01a add r0, pc, #104 @ \(adr r0, 0+144 <[^>]+>\)
0+0da <[^>]+> 3168 adds r1, #104.*
0+0dc <[^>]+> 2668 movs r6, #104.*
0+0de <[^>]+> 2f68 cmp r7, #104.*
-0+0e0 <[^>]+> 46c0 nop ; \(mov r8, r8\)
-0+0e2 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+0e0 <[^>]+> 46c0 nop @ \(mov r8, r8\)
+0+0e2 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+0e4 <[^>]+> eafffffe b 0+0e4 <[^>]+>
0+0e8 <[^>]+> ea000011 b 0+134 <[^>]+>
0+0ec <[^>]+> ebfffffc bl 0+0e4 <[^>]+>
0+0f0 <[^>]+> eb00000f bl 0+134 <[^>]+>
0+0f4 <[^>]+> e12fff10 bx r0
0+0f8 <[^>]+> ef123456 (swi|svc) 0x00123456
-0+0fc <[^>]+> a004 add r0, pc, #16 ; \(adr r0, 0+110 <[^>]+>\)
+0+0fc <[^>]+> a004 add r0, pc, #16 @ \(adr r0, 0+110 <[^>]+>\)
0+0fe <[^>]+> e77f b.n 0+000 <[^>]+>
0+100 <[^>]+> e018 b.n 0+134 <[^>]+>
0+102 <[^>]+> f7ff ff7d bl 0+000 <[^>]+>
0+106 <[^>]+> f000 f815 bl 0+134 <[^>]+>
0+10a <[^>]+> 4700 bx r0
0+10c <[^>]+> dfff (swi|svc) 255.*
-0+10e <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+10e <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+110 <[^>]+> d010 beq.n 0+134 <[^>]+>
0+112 <[^>]+> d10f bne.n 0+134 <[^>]+>
0+114 <[^>]+> d20e bcs.n 0+134 <[^>]+>
@@ -157,14 +157,14 @@ Disassembly of section \.text:
0+134 <[^>]+> f000 fc00 bl 0+938 <[^>]+>
\.\.\.
0+938 <[^>]+> f7ff fbfc bl 0+134 <[^>]+>
-0+93c <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+944 <[^>]+>\)
-0+93e <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+944 <[^>]+>\)
-0+940 <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+948 <[^>]+>\)
-0+942 <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+948 <[^>]+>\)
+0+93c <[^>]+> 4801 ldr r0, \[pc, #4\] @ \(0+944 <[^>]+>\)
+0+93e <[^>]+> 4801 ldr r0, \[pc, #4\] @ \(0+944 <[^>]+>\)
+0+940 <[^>]+> 4801 ldr r0, \[pc, #4\] @ \(0+948 <[^>]+>\)
+0+942 <[^>]+> 4801 ldr r0, \[pc, #4\] @ \(0+948 <[^>]+>\)
0+944 <[^>]+> 1c08 adds r0, r1, #0
-0+946 <[^>]+> 46c0 nop ; \(mov r8, r8\)
-0+948 <[^>]+> a001 add r0, pc, #4 ; \(adr r0, 00000950 <[^>]+>\)
-0+94a <[^>]+> a001 add r0, pc, #4 ; \(adr r0, 00000950 <[^>]+>\)
-0+94c <[^>]+> a000 add r0, pc, #0 ; \(adr r0, 00000950 <[^>]+>\)
-0+94e <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+946 <[^>]+> 46c0 nop @ \(mov r8, r8\)
+0+948 <[^>]+> a001 add r0, pc, #4 @ \(adr r0, 00000950 <[^>]+>\)
+0+94a <[^>]+> a001 add r0, pc, #4 @ \(adr r0, 00000950 <[^>]+>\)
+0+94c <[^>]+> a000 add r0, pc, #0 @ \(adr r0, 00000950 <[^>]+>\)
+0+94e <[^>]+> 46c0 nop @ \(mov r8, r8\)
#pass
diff --git a/gas/testsuite/gas/arm/thumb1_unified.d b/gas/testsuite/gas/arm/thumb1_unified.d
index e34f3978b17..5b82ac58578 100644
--- a/gas/testsuite/gas/arm/thumb1_unified.d
+++ b/gas/testsuite/gas/arm/thumb1_unified.d
@@ -10,8 +10,8 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> 3364 adds r3, #100.*
0[0-9a-f]+ <[^>]+> 3c83 subs r4, #131.*
0[0-9a-f]+ <[^>]+> 2d27 cmp r5, #39.*
-0[0-9a-f]+ <[^>]+> a103 add r1, pc, #12 ; \(adr [^)]*\)
-0[0-9a-f]+ <[^>]+> 4a03 ldr r2, \[pc, #12\] ; \([^)]*\)
+0[0-9a-f]+ <[^>]+> a103 add r1, pc, #12 @ \(adr [^)]*\)
+0[0-9a-f]+ <[^>]+> 4a03 ldr r2, \[pc, #12\] @ \([^)]*\)
0[0-9a-f]+ <[^>]+> 6863 ldr r3, \[r4, #4\]
0[0-9a-f]+ <[^>]+> 9d01 ldr r5, \[sp, #4\]
0[0-9a-f]+ <[^>]+> b001 add sp, #4
diff --git a/gas/testsuite/gas/arm/thumb2_add.d b/gas/testsuite/gas/arm/thumb2_add.d
index 1c438968811..85bbfeb71d5 100644
--- a/gas/testsuite/gas/arm/thumb2_add.d
+++ b/gas/testsuite/gas/arm/thumb2_add.d
@@ -4,27 +4,27 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0+000 <[^>]+> f60f 0000 addw r0, pc, #2048 ; 0x800
+0+000 <[^>]+> f60f 0000 addw r0, pc, #2048 @ 0x800
0+004 <[^>]+> f20f 0900 addw r9, pc, #0
-0+008 <[^>]+> f20f 4900 addw r9, pc, #1024 ; 0x400
-0+00c <[^>]+> f509 6880 add.w r8, r9, #1024 ; 0x400
-0+010 <[^>]+> f209 1801 addw r8, r9, #257 ; 0x101
-0+014 <[^>]+> f201 1301 addw r3, r1, #257 ; 0x101
-0+018 <[^>]+> f6af 0000 subw r0, pc, #2048 ; 0x800
+0+008 <[^>]+> f20f 4900 addw r9, pc, #1024 @ 0x400
+0+00c <[^>]+> f509 6880 add.w r8, r9, #1024 @ 0x400
+0+010 <[^>]+> f209 1801 addw r8, r9, #257 @ 0x101
+0+014 <[^>]+> f201 1301 addw r3, r1, #257 @ 0x101
+0+018 <[^>]+> f6af 0000 subw r0, pc, #2048 @ 0x800
0+01c <[^>]+> f2af 0900 subw r9, pc, #0
-0+020 <[^>]+> f2af 4900 subw r9, pc, #1024 ; 0x400
-0+024 <[^>]+> f5a9 6880 sub.w r8, r9, #1024 ; 0x400
-0+028 <[^>]+> f2a9 1801 subw r8, r9, #257 ; 0x101
-0+02c <[^>]+> f2a1 1301 subw r3, r1, #257 ; 0x101
+0+020 <[^>]+> f2af 4900 subw r9, pc, #1024 @ 0x400
+0+024 <[^>]+> f5a9 6880 sub.w r8, r9, #1024 @ 0x400
+0+028 <[^>]+> f2a9 1801 subw r8, r9, #257 @ 0x101
+0+02c <[^>]+> f2a1 1301 subw r3, r1, #257 @ 0x101
0+030 <[^>]+> f103 0301 add.w r3, r3, #1
0+034 <[^>]+> f1a3 0301 sub.w r3, r3, #1
-0+038 <[^>]+> b0c0 sub sp, #256 ; 0x100
-0+03a <[^>]+> f5ad 7d00 sub.w sp, sp, #512 ; 0x200
-0+03e <[^>]+> f2ad 1d01 subw sp, sp, #257 ; 0x101
-0+042 <[^>]+> b040 add sp, #256 ; 0x100
-0+044 <[^>]+> f50d 7d00 add.w sp, sp, #512 ; 0x200
-0+048 <[^>]+> f20d 1d01 addw sp, sp, #257 ; 0x101
-0+04c <[^>]+> a840 add r0, sp, #256 ; 0x100
-0+04e <[^>]+> f50d 6580 add.w r5, sp, #1024 ; 0x400
-0+052 <[^>]+> f20d 1901 addw r9, sp, #257 ; 0x101
+0+038 <[^>]+> b0c0 sub sp, #256 @ 0x100
+0+03a <[^>]+> f5ad 7d00 sub.w sp, sp, #512 @ 0x200
+0+03e <[^>]+> f2ad 1d01 subw sp, sp, #257 @ 0x101
+0+042 <[^>]+> b040 add sp, #256 @ 0x100
+0+044 <[^>]+> f50d 7d00 add.w sp, sp, #512 @ 0x200
+0+048 <[^>]+> f20d 1d01 addw sp, sp, #257 @ 0x101
+0+04c <[^>]+> a840 add r0, sp, #256 @ 0x100
+0+04e <[^>]+> f50d 6580 add.w r5, sp, #1024 @ 0x400
+0+052 <[^>]+> f20d 1901 addw r9, sp, #257 @ 0x101
0+056 <[^>]+> 4271 negs r1, r6
diff --git a/gas/testsuite/gas/arm/thumb2_invert.d b/gas/testsuite/gas/arm/thumb2_invert.d
index 75a37bae223..99e4fe6aa08 100644
--- a/gas/testsuite/gas/arm/thumb2_invert.d
+++ b/gas/testsuite/gas/arm/thumb2_invert.d
@@ -4,15 +4,15 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0+000 <[^>]+> f517 0f80 cmn.w r7, #4194304 ; 0x400000
-0+004 <[^>]+> f5b8 0f80 cmp.w r8, #4194304 ; 0x400000
-0+008 <[^>]+> f5a4 0980 sub.w r9, r4, #4194304 ; 0x400000
-0+00c <[^>]+> f506 0380 add.w r3, r6, #4194304 ; 0x400000
-0+010 <[^>]+> f160 4500 sbc.w r5, r0, #2147483648 ; 0x80000000
-0+014 <[^>]+> f147 4400 adc.w r4, r7, #2147483648 ; 0x80000000
-0+018 <[^>]+> f022 4600 bic.w r6, r2, #2147483648 ; 0x80000000
-0+01c <[^>]+> f002 4800 and.w r8, r2, #2147483648 ; 0x80000000
-0+020 <[^>]+> f06f 4300 mvn.w r3, #2147483648 ; 0x80000000
-0+024 <[^>]+> f04f 4100 mov.w r1, #2147483648 ; 0x80000000
-0+028 <[^>]+> f062 4600 orn r6, r2, #2147483648 ; 0x80000000
-0+02c <[^>]+> f042 4800 orr.w r8, r2, #2147483648 ; 0x80000000
+0+000 <[^>]+> f517 0f80 cmn.w r7, #4194304 @ 0x400000
+0+004 <[^>]+> f5b8 0f80 cmp.w r8, #4194304 @ 0x400000
+0+008 <[^>]+> f5a4 0980 sub.w r9, r4, #4194304 @ 0x400000
+0+00c <[^>]+> f506 0380 add.w r3, r6, #4194304 @ 0x400000
+0+010 <[^>]+> f160 4500 sbc.w r5, r0, #2147483648 @ 0x80000000
+0+014 <[^>]+> f147 4400 adc.w r4, r7, #2147483648 @ 0x80000000
+0+018 <[^>]+> f022 4600 bic.w r6, r2, #2147483648 @ 0x80000000
+0+01c <[^>]+> f002 4800 and.w r8, r2, #2147483648 @ 0x80000000
+0+020 <[^>]+> f06f 4300 mvn.w r3, #2147483648 @ 0x80000000
+0+024 <[^>]+> f04f 4100 mov.w r1, #2147483648 @ 0x80000000
+0+028 <[^>]+> f062 4600 orn r6, r2, #2147483648 @ 0x80000000
+0+02c <[^>]+> f042 4800 orr.w r8, r2, #2147483648 @ 0x80000000
diff --git a/gas/testsuite/gas/arm/thumb2_pool.d b/gas/testsuite/gas/arm/thumb2_pool.d
index 25b8589f6c5..8a598a7f91c 100644
--- a/gas/testsuite/gas/arm/thumb2_pool.d
+++ b/gas/testsuite/gas/arm/thumb2_pool.d
@@ -6,24 +6,24 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0+000 <[^>]+> 4e04 ldr r6, \[pc, #16\] ; \(00+14 <[^>]+>\)
-0+002 <[^>]+> 4904 ldr r1, \[pc, #16\] ; \(00+14 <[^>]+>\)
-0+004 <[^>]+> f8df 600c ldr\.w r6, \[pc, #12\] ; 00+14 <[^>]+>
-0+008 <[^>]+> f8df 9008 ldr\.w r9, \[pc, #8\] ; 00+14 <[^>]+>
+0+000 <[^>]+> 4e04 ldr r6, \[pc, #16\] @ \(00+14 <[^>]+>\)
+0+002 <[^>]+> 4904 ldr r1, \[pc, #16\] @ \(00+14 <[^>]+>\)
+0+004 <[^>]+> f8df 600c ldr\.w r6, \[pc, #12\] @ 00+14 <[^>]+>
+0+008 <[^>]+> f8df 9008 ldr\.w r9, \[pc, #8\] @ 00+14 <[^>]+>
0+00c <[^>]+> bf00 nop
-0+00e <[^>]+> f8df 5004 ldr\.w r5, \[pc, #4\] ; 00+14 <[^>]+>
-0+012 <[^>]+> 4900 ldr r1, \[pc, #0\] ; \(00+14 <[^>]+>\)
+0+00e <[^>]+> f8df 5004 ldr\.w r5, \[pc, #4\] @ 00+14 <[^>]+>
+0+012 <[^>]+> 4900 ldr r1, \[pc, #0\] @ \(00+14 <[^>]+>\)
0+014 <[^>]+> 12345678 ? .word 0x12345678
-0+018 <[^>]+> 4907 ldr r1, \[pc, #28\] ; \(00000038 <[^>]+>\)
-0+01a <[^>]+> 4c07 ldr r4, \[pc, #28\] ; \(00000038 <[^>]+>\)
-0+01c <[^>]+> f8df 9018 ldr.w r9, \[pc, #24\] ; 00000038 <[^>]+>
-0+020 <[^>]+> f8df c014 ldr.w ip, \[pc, #20\] ; 00000038 <[^>]+>
-0+024 <[^>]+> f8df d010 ldr.w sp, \[pc, #16\] ; 00000038 <[^>]+>
-0+028 <[^>]+> 4904 ldr r1, \[pc, #16\] ; \(0000003c <[^>]+>\)
-0+02a <[^>]+> 4c04 ldr r4, \[pc, #16\] ; \(0000003c <[^>]+>\)
-0+02c <[^>]+> f8df 900c ldr.w r9, \[pc, #12\] ; 0000003c <[^>]+>
-0+030 <[^>]+> f8df c008 ldr.w ip, \[pc, #8\] ; 0000003c <[^>]+>
-0+034 <[^>]+> f8df d004 ldr.w sp, \[pc, #4\] ; 0000003c <[^>]+>
+0+018 <[^>]+> 4907 ldr r1, \[pc, #28\] @ \(00000038 <[^>]+>\)
+0+01a <[^>]+> 4c07 ldr r4, \[pc, #28\] @ \(00000038 <[^>]+>\)
+0+01c <[^>]+> f8df 9018 ldr.w r9, \[pc, #24\] @ 00000038 <[^>]+>
+0+020 <[^>]+> f8df c014 ldr.w ip, \[pc, #20\] @ 00000038 <[^>]+>
+0+024 <[^>]+> f8df d010 ldr.w sp, \[pc, #16\] @ 00000038 <[^>]+>
+0+028 <[^>]+> 4904 ldr r1, \[pc, #16\] @ \(0000003c <[^>]+>\)
+0+02a <[^>]+> 4c04 ldr r4, \[pc, #16\] @ \(0000003c <[^>]+>\)
+0+02c <[^>]+> f8df 900c ldr.w r9, \[pc, #12\] @ 0000003c <[^>]+>
+0+030 <[^>]+> f8df c008 ldr.w ip, \[pc, #8\] @ 0000003c <[^>]+>
+0+034 <[^>]+> f8df d004 ldr.w sp, \[pc, #4\] @ 0000003c <[^>]+>
0+038 <[^>]+> 00000000 .word 0x00000000
38: R_ARM_ABS32 ext_symbol
0+03c <[^>]+> 00001000 .word 0x00001000
diff --git a/gas/testsuite/gas/arm/thumb2_relax.d b/gas/testsuite/gas/arm/thumb2_relax.d
index 53483a7873f..114916e46ad 100644
--- a/gas/testsuite/gas/arm/thumb2_relax.d
+++ b/gas/testsuite/gas/arm/thumb2_relax.d
@@ -15,11 +15,11 @@ Disassembly of section .text:
0+01c <[^>]+> f815 1d1f ldrb.w r1, \[r5, #-31\]!
0+020 <[^>]+> 5d29 ldrb r1, \[r5, r4\]
0+022 <[^>]+> f819 100c ldrb.w r1, \[r9, ip\]
-0+026 <[^>]+> f89f 1014 ldrb.w r1, \[pc, #20\] ; 0+03c <[^>]+>
-0+02a <[^>]+> f89f 1010 ldrb.w r1, \[pc, #16\] ; 0+03c <[^>]+>
-0+02e <[^>]+> f89f 800c ldrb.w r8, \[pc, #12\] ; 0+03c <[^>]+>
-0+032 <[^>]+> f89f 100a ldrb.w r1, \[pc, #10\] ; 0+03e <[^>]+>
-0+036 <[^>]+> f81f 1038 ldrb.w r1, \[pc, #-56\] ; 0+000 <[^>]+>
+0+026 <[^>]+> f89f 1014 ldrb.w r1, \[pc, #20\] @ 0+03c <[^>]+>
+0+02a <[^>]+> f89f 1010 ldrb.w r1, \[pc, #16\] @ 0+03c <[^>]+>
+0+02e <[^>]+> f89f 800c ldrb.w r8, \[pc, #12\] @ 0+03c <[^>]+>
+0+032 <[^>]+> f89f 100a ldrb.w r1, \[pc, #10\] @ 0+03e <[^>]+>
+0+036 <[^>]+> f81f 1038 ldrb.w r1, \[pc, #-56\] @ 0+000 <[^>]+>
0+03a <[^>]+> bf00 nop
0+03c <[^>]+> bf00 nop
0+03e <[^>]+> f995 1000 ldrsb.w r1, \[r5\]
@@ -33,11 +33,11 @@ Disassembly of section .text:
0+05e <[^>]+> f915 1d1f ldrsb.w r1, \[r5, #-31\]!
0+062 <[^>]+> 5729 ldrsb r1, \[r5, r4\]
0+064 <[^>]+> f919 100c ldrsb.w r1, \[r9, ip\]
-0+068 <[^>]+> f99f 1010 ldrsb.w r1, \[pc, #16\] ; 0+07c <[^>]+>
-0+06c <[^>]+> f99f 100c ldrsb.w r1, \[pc, #12\] ; 0+07c <[^>]+>
-0+070 <[^>]+> f99f 8008 ldrsb.w r8, \[pc, #8\] ; 0+07c <[^>]+>
-0+074 <[^>]+> f99f 1006 ldrsb.w r1, \[pc, #6\] ; 0+07e <[^>]+>
-0+078 <[^>]+> f91f 103e ldrsb.w r1, \[pc, #-62\] ; 0+03e <[^>]+>
+0+068 <[^>]+> f99f 1010 ldrsb.w r1, \[pc, #16\] @ 0+07c <[^>]+>
+0+06c <[^>]+> f99f 100c ldrsb.w r1, \[pc, #12\] @ 0+07c <[^>]+>
+0+070 <[^>]+> f99f 8008 ldrsb.w r8, \[pc, #8\] @ 0+07c <[^>]+>
+0+074 <[^>]+> f99f 1006 ldrsb.w r1, \[pc, #6\] @ 0+07e <[^>]+>
+0+078 <[^>]+> f91f 103e ldrsb.w r1, \[pc, #-62\] @ 0+03e <[^>]+>
0+07c <[^>]+> bf00 nop
0+07e <[^>]+> 8829 ldrh r1, \[r5, #0\]
0+080 <[^>]+> f8b5 1042 ldrh.w r1, \[r5, #66\].*
@@ -50,11 +50,11 @@ Disassembly of section .text:
0+09a <[^>]+> f835 1d3e ldrh.w r1, \[r5, #-62\]!.*
0+09e <[^>]+> 5b29 ldrh r1, \[r5, r4\]
0+0a0 <[^>]+> f839 100c ldrh.w r1, \[r9, ip\]
-0+0a4 <[^>]+> f8bf 1010 ldrh.w r1, \[pc, #16\] ; 0+0b8 <[^>]+>
-0+0a8 <[^>]+> f8bf 100c ldrh.w r1, \[pc, #12\] ; 0+0b8 <[^>]+>
-0+0ac <[^>]+> f8bf 8008 ldrh.w r8, \[pc, #8\] ; 0+0b8 <[^>]+>
-0+0b0 <[^>]+> f8bf 1006 ldrh.w r1, \[pc, #6\] ; 0+0ba <[^>]+>
-0+0b4 <[^>]+> f83f 103a ldrh.w r1, \[pc, #-58\] ; 0+07e <[^>]+>
+0+0a4 <[^>]+> f8bf 1010 ldrh.w r1, \[pc, #16\] @ 0+0b8 <[^>]+>
+0+0a8 <[^>]+> f8bf 100c ldrh.w r1, \[pc, #12\] @ 0+0b8 <[^>]+>
+0+0ac <[^>]+> f8bf 8008 ldrh.w r8, \[pc, #8\] @ 0+0b8 <[^>]+>
+0+0b0 <[^>]+> f8bf 1006 ldrh.w r1, \[pc, #6\] @ 0+0ba <[^>]+>
+0+0b4 <[^>]+> f83f 103a ldrh.w r1, \[pc, #-58\] @ 0+07e <[^>]+>
0+0b8 <[^>]+> bf00 nop
0+0ba <[^>]+> f9b5 1000 ldrsh.w r1, \[r5\]
0+0be <[^>]+> f9b5 1042 ldrsh.w r1, \[r5, #66\].*
@@ -67,11 +67,11 @@ Disassembly of section .text:
0+0da <[^>]+> f935 1d3e ldrsh.w r1, \[r5, #-62\]!.*
0+0de <[^>]+> 5f29 ldrsh r1, \[r5, r4\]
0+0e0 <[^>]+> f939 100c ldrsh.w r1, \[r9, ip\]
-0+0e4 <[^>]+> f9bf 1010 ldrsh.w r1, \[pc, #16\] ; 0+0f8 <[^>]+>
-0+0e8 <[^>]+> f9bf 100c ldrsh.w r1, \[pc, #12\] ; 0+0f8 <[^>]+>
-0+0ec <[^>]+> f9bf 8008 ldrsh.w r8, \[pc, #8\] ; 0+0f8 <[^>]+>
-0+0f0 <[^>]+> f9bf 1006 ldrsh.w r1, \[pc, #6\] ; 0+0fa <[^>]+>
-0+0f4 <[^>]+> f93f 103e ldrsh.w r1, \[pc, #-62\] ; 0+0ba <[^>]+>
+0+0e4 <[^>]+> f9bf 1010 ldrsh.w r1, \[pc, #16\] @ 0+0f8 <[^>]+>
+0+0e8 <[^>]+> f9bf 100c ldrsh.w r1, \[pc, #12\] @ 0+0f8 <[^>]+>
+0+0ec <[^>]+> f9bf 8008 ldrsh.w r8, \[pc, #8\] @ 0+0f8 <[^>]+>
+0+0f0 <[^>]+> f9bf 1006 ldrsh.w r1, \[pc, #6\] @ 0+0fa <[^>]+>
+0+0f4 <[^>]+> f93f 103e ldrsh.w r1, \[pc, #-62\] @ 0+0ba <[^>]+>
0+0f8 <[^>]+> bf00 nop
0+0fa <[^>]+> 6829 ldr r1, \[r5, #0\]
0+0fc <[^>]+> f8d5 1080 ldr.w r1, \[r5, #128\].*
@@ -84,14 +84,14 @@ Disassembly of section .text:
0+116 <[^>]+> f855 1d7c ldr.w r1, \[r5, #-124\]!.*
0+11a <[^>]+> 5929 ldr r1, \[r5, r4\]
0+11c <[^>]+> f859 100c ldr.w r1, \[r9, ip\]
-0+120 <[^>]+> 4904 ldr r1, \[pc, #16\] ; \(0+134 <[^>]+>\)
-0+122 <[^>]+> f8df 1010 ldr.w r1, \[pc, #16\] ; 0+134 <[^>]+>
-0+126 <[^>]+> f8df 800c ldr.w r8, \[pc, #12\] ; 0+134 <[^>]+>
-0+12a <[^>]+> f8df 100a ldr.w r1, \[pc, #10\] ; 0+136 <[^>]+>
-0+12e <[^>]+> f85f 1036 ldr.w r1, \[pc, #-54\] ; 0+0fa <[^>]+>
+0+120 <[^>]+> 4904 ldr r1, \[pc, #16\] @ \(0+134 <[^>]+>\)
+0+122 <[^>]+> f8df 1010 ldr.w r1, \[pc, #16\] @ 0+134 <[^>]+>
+0+126 <[^>]+> f8df 800c ldr.w r8, \[pc, #12\] @ 0+134 <[^>]+>
+0+12a <[^>]+> f8df 100a ldr.w r1, \[pc, #10\] @ 0+136 <[^>]+>
+0+12e <[^>]+> f85f 1036 ldr.w r1, \[pc, #-54\] @ 0+0fa <[^>]+>
0+132 <[^>]+> bf00 nop
0+134 <[^>]+> bf00 nop
-0+136 <[^>]+> a104 add r1, pc, #16 ; \(adr r1, 0+148 <[^>]+>\)
+0+136 <[^>]+> a104 add r1, pc, #16 @ \(adr r1, 0+148 <[^>]+>\)
0+138 <[^>]+> f20f 010c addw r1, pc, #12
0+13c <[^>]+> f20f 0808 addw r8, pc, #8
0+140 <[^>]+> f20f 0106 addw r1, pc, #6
diff --git a/gas/testsuite/gas/arm/thumb2_vpool.d b/gas/testsuite/gas/arm/thumb2_vpool.d
index c542d1a8d72..3079636e649 100644
--- a/gas/testsuite/gas/arm/thumb2_vpool.d
+++ b/gas/testsuite/gas/arm/thumb2_vpool.d
@@ -7,42 +7,42 @@
.*: +file format .*arm.*
Disassembly of section .text:
-00000000 <thumb2_ldr> ed9f 0a0f vldr s0, \[pc, #60\] ; 00000040 <thumb2_ldr\+0x40>
-00000004 <thumb2_ldr\+0x4> ed9f 7a0e vldr s14, \[pc, #56\] ; 00000040 <thumb2_ldr\+0x40>
-00000008 <thumb2_ldr\+0x8> ed9f ea0d vldr s28, \[pc, #52\] ; 00000040 <thumb2_ldr\+0x40>
-0000000c <thumb2_ldr\+0xc> eddf fa0c vldr s31, \[pc, #48\] ; 00000040 <thumb2_ldr\+0x40>
-00000010 <thumb2_ldr\+0x10> ed9f 0a0c vldr s0, \[pc, #48\] ; 00000044 <thumb2_ldr\+0x44>
-00000014 <thumb2_ldr\+0x14> ed9f 7a0b vldr s14, \[pc, #44\] ; 00000044 <thumb2_ldr\+0x44>
-00000018 <thumb2_ldr\+0x18> ed9f ea0a vldr s28, \[pc, #40\] ; 00000044 <thumb2_ldr\+0x44>
-0000001c <thumb2_ldr\+0x1c> eddf fa09 vldr s31, \[pc, #36\] ; 00000044 <thumb2_ldr\+0x44>
-00000020 <thumb2_ldr\+0x20> ed9f 0a09 vldr s0, \[pc, #36\] ; 00000048 <thumb2_ldr\+0x48>
-00000024 <thumb2_ldr\+0x24> ed9f 7a08 vldr s14, \[pc, #32\] ; 00000048 <thumb2_ldr\+0x48>
-00000028 <thumb2_ldr\+0x28> ed9f ea07 vldr s28, \[pc, #28\] ; 00000048 <thumb2_ldr\+0x48>
-0000002c <thumb2_ldr\+0x2c> eddf fa06 vldr s31, \[pc, #24\] ; 00000048 <thumb2_ldr\+0x48>
-00000030 <thumb2_ldr\+0x30> ed9f 0a06 vldr s0, \[pc, #24\] ; 0000004c <thumb2_ldr\+0x4c>
-00000034 <thumb2_ldr\+0x34> ed9f 7a05 vldr s14, \[pc, #20\] ; 0000004c <thumb2_ldr\+0x4c>
-00000038 <thumb2_ldr\+0x38> ed9f ea04 vldr s28, \[pc, #16\] ; 0000004c <thumb2_ldr\+0x4c>
-0000003c <thumb2_ldr\+0x3c> eddf fa03 vldr s31, \[pc, #12\] ; 0000004c <thumb2_ldr\+0x4c>
+00000000 <thumb2_ldr> ed9f 0a0f vldr s0, \[pc, #60\] @ 00000040 <thumb2_ldr\+0x40>
+00000004 <thumb2_ldr\+0x4> ed9f 7a0e vldr s14, \[pc, #56\] @ 00000040 <thumb2_ldr\+0x40>
+00000008 <thumb2_ldr\+0x8> ed9f ea0d vldr s28, \[pc, #52\] @ 00000040 <thumb2_ldr\+0x40>
+0000000c <thumb2_ldr\+0xc> eddf fa0c vldr s31, \[pc, #48\] @ 00000040 <thumb2_ldr\+0x40>
+00000010 <thumb2_ldr\+0x10> ed9f 0a0c vldr s0, \[pc, #48\] @ 00000044 <thumb2_ldr\+0x44>
+00000014 <thumb2_ldr\+0x14> ed9f 7a0b vldr s14, \[pc, #44\] @ 00000044 <thumb2_ldr\+0x44>
+00000018 <thumb2_ldr\+0x18> ed9f ea0a vldr s28, \[pc, #40\] @ 00000044 <thumb2_ldr\+0x44>
+0000001c <thumb2_ldr\+0x1c> eddf fa09 vldr s31, \[pc, #36\] @ 00000044 <thumb2_ldr\+0x44>
+00000020 <thumb2_ldr\+0x20> ed9f 0a09 vldr s0, \[pc, #36\] @ 00000048 <thumb2_ldr\+0x48>
+00000024 <thumb2_ldr\+0x24> ed9f 7a08 vldr s14, \[pc, #32\] @ 00000048 <thumb2_ldr\+0x48>
+00000028 <thumb2_ldr\+0x28> ed9f ea07 vldr s28, \[pc, #28\] @ 00000048 <thumb2_ldr\+0x48>
+0000002c <thumb2_ldr\+0x2c> eddf fa06 vldr s31, \[pc, #24\] @ 00000048 <thumb2_ldr\+0x48>
+00000030 <thumb2_ldr\+0x30> ed9f 0a06 vldr s0, \[pc, #24\] @ 0000004c <thumb2_ldr\+0x4c>
+00000034 <thumb2_ldr\+0x34> ed9f 7a05 vldr s14, \[pc, #20\] @ 0000004c <thumb2_ldr\+0x4c>
+00000038 <thumb2_ldr\+0x38> ed9f ea04 vldr s28, \[pc, #16\] @ 0000004c <thumb2_ldr\+0x4c>
+0000003c <thumb2_ldr\+0x3c> eddf fa03 vldr s31, \[pc, #12\] @ 0000004c <thumb2_ldr\+0x4c>
00000040 <thumb2_ldr\+0x40> 00000000 .word 0x00000000
00000044 <thumb2_ldr\+0x44> ff000000 .word 0xff000000
00000048 <thumb2_ldr\+0x48> ffffffff .word 0xffffffff
0000004c <thumb2_ldr\+0x4c> 0fff0000 .word 0x0fff0000
-00000050 <thumb2_ldr\+0x50> ed9f 0a0f vldr s0, \[pc, #60\] ; 00000090 <thumb2_ldr\+0x90>
-00000054 <thumb2_ldr\+0x54> ed9f 7a0e vldr s14, \[pc, #56\] ; 00000090 <thumb2_ldr\+0x90>
-00000058 <thumb2_ldr\+0x58> ed9f ea0d vldr s28, \[pc, #52\] ; 00000090 <thumb2_ldr\+0x90>
-0000005c <thumb2_ldr\+0x5c> eddf fa0c vldr s31, \[pc, #48\] ; 00000090 <thumb2_ldr\+0x90>
-00000060 <thumb2_ldr\+0x60> ed9f 0a0c vldr s0, \[pc, #48\] ; 00000094 <thumb2_ldr\+0x94>
-00000064 <thumb2_ldr\+0x64> ed9f 7a0b vldr s14, \[pc, #44\] ; 00000094 <thumb2_ldr\+0x94>
-00000068 <thumb2_ldr\+0x68> ed9f ea0a vldr s28, \[pc, #40\] ; 00000094 <thumb2_ldr\+0x94>
-0000006c <thumb2_ldr\+0x6c> eddf fa09 vldr s31, \[pc, #36\] ; 00000094 <thumb2_ldr\+0x94>
-00000070 <thumb2_ldr\+0x70> ed9f 0a09 vldr s0, \[pc, #36\] ; 00000098 <thumb2_ldr\+0x98>
-00000074 <thumb2_ldr\+0x74> ed9f 7a08 vldr s14, \[pc, #32\] ; 00000098 <thumb2_ldr\+0x98>
-00000078 <thumb2_ldr\+0x78> ed9f ea07 vldr s28, \[pc, #28\] ; 00000098 <thumb2_ldr\+0x98>
-0000007c <thumb2_ldr\+0x7c> eddf fa06 vldr s31, \[pc, #24\] ; 00000098 <thumb2_ldr\+0x98>
-00000080 <thumb2_ldr\+0x80> ed9f 0a06 vldr s0, \[pc, #24\] ; 0000009c <thumb2_ldr\+0x9c>
-00000084 <thumb2_ldr\+0x84> ed9f 7a05 vldr s14, \[pc, #20\] ; 0000009c <thumb2_ldr\+0x9c>
-00000088 <thumb2_ldr\+0x88> ed9f ea04 vldr s28, \[pc, #16\] ; 0000009c <thumb2_ldr\+0x9c>
-0000008c <thumb2_ldr\+0x8c> eddf fa03 vldr s31, \[pc, #12\] ; 0000009c <thumb2_ldr\+0x9c>
+00000050 <thumb2_ldr\+0x50> ed9f 0a0f vldr s0, \[pc, #60\] @ 00000090 <thumb2_ldr\+0x90>
+00000054 <thumb2_ldr\+0x54> ed9f 7a0e vldr s14, \[pc, #56\] @ 00000090 <thumb2_ldr\+0x90>
+00000058 <thumb2_ldr\+0x58> ed9f ea0d vldr s28, \[pc, #52\] @ 00000090 <thumb2_ldr\+0x90>
+0000005c <thumb2_ldr\+0x5c> eddf fa0c vldr s31, \[pc, #48\] @ 00000090 <thumb2_ldr\+0x90>
+00000060 <thumb2_ldr\+0x60> ed9f 0a0c vldr s0, \[pc, #48\] @ 00000094 <thumb2_ldr\+0x94>
+00000064 <thumb2_ldr\+0x64> ed9f 7a0b vldr s14, \[pc, #44\] @ 00000094 <thumb2_ldr\+0x94>
+00000068 <thumb2_ldr\+0x68> ed9f ea0a vldr s28, \[pc, #40\] @ 00000094 <thumb2_ldr\+0x94>
+0000006c <thumb2_ldr\+0x6c> eddf fa09 vldr s31, \[pc, #36\] @ 00000094 <thumb2_ldr\+0x94>
+00000070 <thumb2_ldr\+0x70> ed9f 0a09 vldr s0, \[pc, #36\] @ 00000098 <thumb2_ldr\+0x98>
+00000074 <thumb2_ldr\+0x74> ed9f 7a08 vldr s14, \[pc, #32\] @ 00000098 <thumb2_ldr\+0x98>
+00000078 <thumb2_ldr\+0x78> ed9f ea07 vldr s28, \[pc, #28\] @ 00000098 <thumb2_ldr\+0x98>
+0000007c <thumb2_ldr\+0x7c> eddf fa06 vldr s31, \[pc, #24\] @ 00000098 <thumb2_ldr\+0x98>
+00000080 <thumb2_ldr\+0x80> ed9f 0a06 vldr s0, \[pc, #24\] @ 0000009c <thumb2_ldr\+0x9c>
+00000084 <thumb2_ldr\+0x84> ed9f 7a05 vldr s14, \[pc, #20\] @ 0000009c <thumb2_ldr\+0x9c>
+00000088 <thumb2_ldr\+0x88> ed9f ea04 vldr s28, \[pc, #16\] @ 0000009c <thumb2_ldr\+0x9c>
+0000008c <thumb2_ldr\+0x8c> eddf fa03 vldr s31, \[pc, #12\] @ 0000009c <thumb2_ldr\+0x9c>
00000090 <thumb2_ldr\+0x90> 00000000 .word 0x00000000
00000094 <thumb2_ldr\+0x94> 00ff0000 .word 0x00ff0000
00000098 <thumb2_ldr\+0x98> ff00ffff .word 0xff00ffff
@@ -51,18 +51,18 @@ Disassembly of section .text:
000000a4 <thumb2_ldr\+0xa4> ef80 ee30 vmov.i64 d14, #0x0000000000000000
000000a8 <thumb2_ldr\+0xa8> efc0 ce30 vmov.i64 d28, #0x0000000000000000
000000ac <thumb2_ldr\+0xac> efc0 fe30 vmov.i64 d31, #0x0000000000000000
-000000b0 <thumb2_ldr\+0xb0> ed9f 0b0b vldr d0, \[pc, #44\] ; 000000e0 <thumb2_ldr\+0xe0>
-000000b4 <thumb2_ldr\+0xb4> ed9f eb0a vldr d14, \[pc, #40\] ; 000000e0 <thumb2_ldr\+0xe0>
-000000b8 <thumb2_ldr\+0xb8> eddf cb09 vldr d28, \[pc, #36\] ; 000000e0 <thumb2_ldr\+0xe0>
-000000bc <thumb2_ldr\+0xbc> eddf fb08 vldr d31, \[pc, #32\] ; 000000e0 <thumb2_ldr\+0xe0>
+000000b0 <thumb2_ldr\+0xb0> ed9f 0b0b vldr d0, \[pc, #44\] @ 000000e0 <thumb2_ldr\+0xe0>
+000000b4 <thumb2_ldr\+0xb4> ed9f eb0a vldr d14, \[pc, #40\] @ 000000e0 <thumb2_ldr\+0xe0>
+000000b8 <thumb2_ldr\+0xb8> eddf cb09 vldr d28, \[pc, #36\] @ 000000e0 <thumb2_ldr\+0xe0>
+000000bc <thumb2_ldr\+0xbc> eddf fb08 vldr d31, \[pc, #32\] @ 000000e0 <thumb2_ldr\+0xe0>
000000c0 <thumb2_ldr\+0xc0> ff87 0e3f vmov.i64 d0, #0xffffffffffffffff
000000c4 <thumb2_ldr\+0xc4> ff87 ee3f vmov.i64 d14, #0xffffffffffffffff
000000c8 <thumb2_ldr\+0xc8> ffc7 ce3f vmov.i64 d28, #0xffffffffffffffff
000000cc <thumb2_ldr\+0xcc> ffc7 fe3f vmov.i64 d31, #0xffffffffffffffff
-000000d0 <thumb2_ldr\+0xd0> ed9f 0b05 vldr d0, \[pc, #20\] ; 000000e8 <thumb2_ldr\+0xe8>
-000000d4 <thumb2_ldr\+0xd4> ed9f eb04 vldr d14, \[pc, #16\] ; 000000e8 <thumb2_ldr\+0xe8>
-000000d8 <thumb2_ldr\+0xd8> eddf cb03 vldr d28, \[pc, #12\] ; 000000e8 <thumb2_ldr\+0xe8>
-000000dc <thumb2_ldr\+0xdc> eddf fb02 vldr d31, \[pc, #8\] ; 000000e8 <thumb2_ldr\+0xe8>
+000000d0 <thumb2_ldr\+0xd0> ed9f 0b05 vldr d0, \[pc, #20\] @ 000000e8 <thumb2_ldr\+0xe8>
+000000d4 <thumb2_ldr\+0xd4> ed9f eb04 vldr d14, \[pc, #16\] @ 000000e8 <thumb2_ldr\+0xe8>
+000000d8 <thumb2_ldr\+0xd8> eddf cb03 vldr d28, \[pc, #12\] @ 000000e8 <thumb2_ldr\+0xe8>
+000000dc <thumb2_ldr\+0xdc> eddf fb02 vldr d31, \[pc, #8\] @ 000000e8 <thumb2_ldr\+0xe8>
000000e0 <thumb2_ldr\+0xe0> ca000000 .word 0xca000000
000000e4 <thumb2_ldr\+0xe4> 00000000 .word 0x00000000
000000e8 <thumb2_ldr\+0xe8> 0fff0000 .word 0x0fff0000
@@ -79,10 +79,10 @@ Disassembly of section .text:
00000114 <thumb2_ldr\+0x114> ef80 ee39 vmov.i64 d14, #0x00000000ff0000ff
00000118 <thumb2_ldr\+0x118> efc0 ce39 vmov.i64 d28, #0x00000000ff0000ff
0000011c <thumb2_ldr\+0x11c> efc0 fe39 vmov.i64 d31, #0x00000000ff0000ff
-00000120 <thumb2_ldr\+0x120> ed9f 0b03 vldr d0, \[pc, #12\] ; 00000130 <thumb2_ldr\+0x130>
-00000124 <thumb2_ldr\+0x124> ed9f eb02 vldr d14, \[pc, #8\] ; 00000130 <thumb2_ldr\+0x130>
-00000128 <thumb2_ldr\+0x128> eddf cb01 vldr d28, \[pc, #4\] ; 00000130 <thumb2_ldr\+0x130>
-0000012c <thumb2_ldr\+0x12c> eddf fb00 vldr d31, \[pc\] ; 00000130 <thumb2_ldr\+0x130>
+00000120 <thumb2_ldr\+0x120> ed9f 0b03 vldr d0, \[pc, #12\] @ 00000130 <thumb2_ldr\+0x130>
+00000124 <thumb2_ldr\+0x124> ed9f eb02 vldr d14, \[pc, #8\] @ 00000130 <thumb2_ldr\+0x130>
+00000128 <thumb2_ldr\+0x128> eddf cb01 vldr d28, \[pc, #4\] @ 00000130 <thumb2_ldr\+0x130>
+0000012c <thumb2_ldr\+0x12c> eddf fb00 vldr d31, \[pc\] @ 00000130 <thumb2_ldr\+0x130>
00000130 <thumb2_ldr\+0x130> 00fff000 .word 0x00fff000
00000134 <thumb2_ldr\+0x134> 00000000 .word 0x00000000
00000138 <thumb2_ldr\+0x138> ef80 0e30 vmov.i64 d0, #0x0000000000000000
@@ -97,56 +97,56 @@ Disassembly of section .text:
0000015c <thumb2_ldr\+0x15c> ff87 ee3f vmov.i64 d14, #0xffffffffffffffff
00000160 <thumb2_ldr\+0x160> ffc7 ce3f vmov.i64 d28, #0xffffffffffffffff
00000164 <thumb2_ldr\+0x164> ffc7 fe3f vmov.i64 d31, #0xffffffffffffffff
-00000168 <thumb2_ldr\+0x168> ed9f 0b03 vldr d0, \[pc, #12\] ; 00000178 <thumb2_ldr\+0x178>
-0000016c <thumb2_ldr\+0x16c> ed9f eb02 vldr d14, \[pc, #8\] ; 00000178 <thumb2_ldr\+0x178>
-00000170 <thumb2_ldr\+0x170> eddf cb01 vldr d28, \[pc, #4\] ; 00000178 <thumb2_ldr\+0x178>
-00000174 <thumb2_ldr\+0x174> eddf fb00 vldr d31, \[pc\] ; 00000178 <thumb2_ldr\+0x178>
+00000168 <thumb2_ldr\+0x168> ed9f 0b03 vldr d0, \[pc, #12\] @ 00000178 <thumb2_ldr\+0x178>
+0000016c <thumb2_ldr\+0x16c> ed9f eb02 vldr d14, \[pc, #8\] @ 00000178 <thumb2_ldr\+0x178>
+00000170 <thumb2_ldr\+0x170> eddf cb01 vldr d28, \[pc, #4\] @ 00000178 <thumb2_ldr\+0x178>
+00000174 <thumb2_ldr\+0x174> eddf fb00 vldr d31, \[pc\] @ 00000178 <thumb2_ldr\+0x178>
00000178 <thumb2_ldr\+0x178> 00000000 .word 0x00000000
0000017c <thumb2_ldr\+0x17c> 0fff0000 .word 0x0fff0000
00000180 <thumb2_ldr\+0x180> ef80 0e30 vmov.i64 d0, #0x0000000000000000
00000184 <thumb2_ldr\+0x184> ef80 ee30 vmov.i64 d14, #0x0000000000000000
00000188 <thumb2_ldr\+0x188> efc0 ce30 vmov.i64 d28, #0x0000000000000000
0000018c <thumb2_ldr\+0x18c> efc0 fe30 vmov.i64 d31, #0x0000000000000000
-00000190 <thumb2_ldr\+0x190> ed9f 0b0b vldr d0, \[pc, #44\] ; 000001c0 <thumb2_ldr\+0x1c0>
-00000194 <thumb2_ldr\+0x194> ed9f eb0a vldr d14, \[pc, #40\] ; 000001c0 <thumb2_ldr\+0x1c0>
-00000198 <thumb2_ldr\+0x198> eddf cb09 vldr d28, \[pc, #36\] ; 000001c0 <thumb2_ldr\+0x1c0>
-0000019c <thumb2_ldr\+0x19c> eddf fb08 vldr d31, \[pc, #32\] ; 000001c0 <thumb2_ldr\+0x1c0>
-000001a0 <thumb2_ldr\+0x1a0> ed9f 0b09 vldr d0, \[pc, #36\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001a4 <thumb2_ldr\+0x1a4> ed9f eb08 vldr d14, \[pc, #32\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001a8 <thumb2_ldr\+0x1a8> eddf cb07 vldr d28, \[pc, #28\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001ac <thumb2_ldr\+0x1ac> eddf fb06 vldr d31, \[pc, #24\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001b0 <thumb2_ldr\+0x1b0> ed9f 0b05 vldr d0, \[pc, #20\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001b4 <thumb2_ldr\+0x1b4> ed9f eb04 vldr d14, \[pc, #16\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001b8 <thumb2_ldr\+0x1b8> eddf cb03 vldr d28, \[pc, #12\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001bc <thumb2_ldr\+0x1bc> eddf fb02 vldr d31, \[pc, #8\] ; 000001c8 <thumb2_ldr\+0x1c8>
+00000190 <thumb2_ldr\+0x190> ed9f 0b0b vldr d0, \[pc, #44\] @ 000001c0 <thumb2_ldr\+0x1c0>
+00000194 <thumb2_ldr\+0x194> ed9f eb0a vldr d14, \[pc, #40\] @ 000001c0 <thumb2_ldr\+0x1c0>
+00000198 <thumb2_ldr\+0x198> eddf cb09 vldr d28, \[pc, #36\] @ 000001c0 <thumb2_ldr\+0x1c0>
+0000019c <thumb2_ldr\+0x19c> eddf fb08 vldr d31, \[pc, #32\] @ 000001c0 <thumb2_ldr\+0x1c0>
+000001a0 <thumb2_ldr\+0x1a0> ed9f 0b09 vldr d0, \[pc, #36\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001a4 <thumb2_ldr\+0x1a4> ed9f eb08 vldr d14, \[pc, #32\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001a8 <thumb2_ldr\+0x1a8> eddf cb07 vldr d28, \[pc, #28\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001ac <thumb2_ldr\+0x1ac> eddf fb06 vldr d31, \[pc, #24\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001b0 <thumb2_ldr\+0x1b0> ed9f 0b05 vldr d0, \[pc, #20\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001b4 <thumb2_ldr\+0x1b4> ed9f eb04 vldr d14, \[pc, #16\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001b8 <thumb2_ldr\+0x1b8> eddf cb03 vldr d28, \[pc, #12\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001bc <thumb2_ldr\+0x1bc> eddf fb02 vldr d31, \[pc, #8\] @ 000001c8 <thumb2_ldr\+0x1c8>
000001c0 <thumb2_ldr\+0x1c0> 00000000 .word 0x00000000
000001c4 <thumb2_ldr\+0x1c4> 000ff000 .word 0x000ff000
000001c8 <thumb2_ldr\+0x1c8> f0000000 .word 0xf0000000
000001cc <thumb2_ldr\+0x1cc> 0ff00fff .word 0x0ff00fff
-000001d0 <thumb2_ldr\+0x1d0> ed9f 1b01 vldr d1, \[pc, #4\] ; 000001d8 <thumb2_ldr\+0x1d8>
+000001d0 <thumb2_ldr\+0x1d0> ed9f 1b01 vldr d1, \[pc, #4\] @ 000001d8 <thumb2_ldr\+0x1d8>
\.\.\.
000001dc <thumb2_ldr\+0x1dc> 0000fff0 .word 0x0000fff0
000001e0 <thumb2_ldr\+0x1e0> f101 0000 add.w r0, r1, #0
-000001e4 <thumb2_ldr\+0x1e4> ed9f 1b00 vldr d1, \[pc\] ; 000001e8 <thumb2_ldr\+0x1e8>
+000001e4 <thumb2_ldr\+0x1e4> ed9f 1b00 vldr d1, \[pc\] @ 000001e8 <thumb2_ldr\+0x1e8>
000001e8 <thumb2_ldr\+0x1e8> 00000000 .word 0x00000000
000001ec <thumb2_ldr\+0x1ec> 0000fff0 .word 0x0000fff0
-000001f0 <thumb2_ldr\+0x1f0> ed9f 1b11 vldr d1, \[pc, #68\] ; 00000238 <thumb2_ldr\+0x238>
-000001f4 <thumb2_ldr\+0x1f4> ed9f 1a12 vldr s2, \[pc, #72\] ; 00000240 <thumb2_ldr\+0x240>
-000001f8 <thumb2_ldr\+0x1f8> ed9f 3b13 vldr d3, \[pc, #76\] ; 00000248 <thumb2_ldr\+0x248>
-000001fc <thumb2_ldr\+0x1fc> ed9f 2a11 vldr s4, \[pc, #68\] ; 00000244 <thumb2_ldr\+0x244>
-00000200 <thumb2_ldr\+0x200> ed9f 5b11 vldr d5, \[pc, #68\] ; 00000248 <thumb2_ldr\+0x248>
-00000204 <thumb2_ldr\+0x204> ed9f 6b12 vldr d6, \[pc, #72\] ; 00000250 <thumb2_ldr\+0x250>
-00000208 <thumb2_ldr\+0x208> ed9f 7b13 vldr d7, \[pc, #76\] ; 00000258 <thumb2_ldr\+0x258>
-0000020c <thumb2_ldr\+0x20c> ed9f 4a14 vldr s8, \[pc, #80\] ; 00000260 <thumb2_ldr\+0x260>
-00000210 <thumb2_ldr\+0x210> ed9f 9b15 vldr d9, \[pc, #84\] ; 00000268 <thumb2_ldr\+0x268>
-00000214 <thumb2_ldr\+0x214> ed9f 5a13 vldr s10, \[pc, #76\] ; 00000264 <thumb2_ldr\+0x264>
-00000218 <thumb2_ldr\+0x218> ed9f bb15 vldr d11, \[pc, #84\] ; 00000270 <thumb2_ldr\+0x270>
-0000021c <thumb2_ldr\+0x21c> ed9f 6a16 vldr s12, \[pc, #88\] ; 00000278 <thumb2_ldr\+0x278>
-00000220 <thumb2_ldr\+0x220> eddf 6a16 vldr s13, \[pc, #88\] ; 0000027c <thumb2_ldr\+0x27c>
-00000224 <thumb2_ldr\+0x224> ed9f 7a07 vldr s14, \[pc, #28\] ; 00000244 <thumb2_ldr\+0x244>
-00000228 <thumb2_ldr\+0x228> eddf 7a04 vldr s15, \[pc, #16\] ; 0000023c <thumb2_ldr\+0x23c>
-0000022c <thumb2_ldr\+0x22c> eddf 0b12 vldr d16, \[pc, #72\] ; 00000278 <thumb2_ldr\+0x278>
-00000230 <thumb2_ldr\+0x230> eddf 1b13 vldr d17, \[pc, #76\] ; 00000280 <thumb2_ldr\+0x280>
+000001f0 <thumb2_ldr\+0x1f0> ed9f 1b11 vldr d1, \[pc, #68\] @ 00000238 <thumb2_ldr\+0x238>
+000001f4 <thumb2_ldr\+0x1f4> ed9f 1a12 vldr s2, \[pc, #72\] @ 00000240 <thumb2_ldr\+0x240>
+000001f8 <thumb2_ldr\+0x1f8> ed9f 3b13 vldr d3, \[pc, #76\] @ 00000248 <thumb2_ldr\+0x248>
+000001fc <thumb2_ldr\+0x1fc> ed9f 2a11 vldr s4, \[pc, #68\] @ 00000244 <thumb2_ldr\+0x244>
+00000200 <thumb2_ldr\+0x200> ed9f 5b11 vldr d5, \[pc, #68\] @ 00000248 <thumb2_ldr\+0x248>
+00000204 <thumb2_ldr\+0x204> ed9f 6b12 vldr d6, \[pc, #72\] @ 00000250 <thumb2_ldr\+0x250>
+00000208 <thumb2_ldr\+0x208> ed9f 7b13 vldr d7, \[pc, #76\] @ 00000258 <thumb2_ldr\+0x258>
+0000020c <thumb2_ldr\+0x20c> ed9f 4a14 vldr s8, \[pc, #80\] @ 00000260 <thumb2_ldr\+0x260>
+00000210 <thumb2_ldr\+0x210> ed9f 9b15 vldr d9, \[pc, #84\] @ 00000268 <thumb2_ldr\+0x268>
+00000214 <thumb2_ldr\+0x214> ed9f 5a13 vldr s10, \[pc, #76\] @ 00000264 <thumb2_ldr\+0x264>
+00000218 <thumb2_ldr\+0x218> ed9f bb15 vldr d11, \[pc, #84\] @ 00000270 <thumb2_ldr\+0x270>
+0000021c <thumb2_ldr\+0x21c> ed9f 6a16 vldr s12, \[pc, #88\] @ 00000278 <thumb2_ldr\+0x278>
+00000220 <thumb2_ldr\+0x220> eddf 6a16 vldr s13, \[pc, #88\] @ 0000027c <thumb2_ldr\+0x27c>
+00000224 <thumb2_ldr\+0x224> ed9f 7a07 vldr s14, \[pc, #28\] @ 00000244 <thumb2_ldr\+0x244>
+00000228 <thumb2_ldr\+0x228> eddf 7a04 vldr s15, \[pc, #16\] @ 0000023c <thumb2_ldr\+0x23c>
+0000022c <thumb2_ldr\+0x22c> eddf 0b12 vldr d16, \[pc, #72\] @ 00000278 <thumb2_ldr\+0x278>
+00000230 <thumb2_ldr\+0x230> eddf 1b13 vldr d17, \[pc, #76\] @ 00000280 <thumb2_ldr\+0x280>
\.\.\.
0000023c <thumb2_ldr\+0x23c> 0000fff0 .word 0x0000fff0
00000240 <thumb2_ldr\+0x240> ff000000 .word 0xff000000
diff --git a/gas/testsuite/gas/arm/thumb2_vpool_be.d b/gas/testsuite/gas/arm/thumb2_vpool_be.d
index d3276e9b5b2..df6ce2f3931 100644
--- a/gas/testsuite/gas/arm/thumb2_vpool_be.d
+++ b/gas/testsuite/gas/arm/thumb2_vpool_be.d
@@ -8,42 +8,42 @@
.*: +file format .*arm.*
Disassembly of section .text:
-00000000 <thumb2_ldr> ed9f 0a0f vldr s0, \[pc, #60\] ; 00000040 <thumb2_ldr\+0x40>
-00000004 <thumb2_ldr\+0x4> ed9f 7a0e vldr s14, \[pc, #56\] ; 00000040 <thumb2_ldr\+0x40>
-00000008 <thumb2_ldr\+0x8> ed9f ea0d vldr s28, \[pc, #52\] ; 00000040 <thumb2_ldr\+0x40>
-0000000c <thumb2_ldr\+0xc> eddf fa0c vldr s31, \[pc, #48\] ; 00000040 <thumb2_ldr\+0x40>
-00000010 <thumb2_ldr\+0x10> ed9f 0a0c vldr s0, \[pc, #48\] ; 00000044 <thumb2_ldr\+0x44>
-00000014 <thumb2_ldr\+0x14> ed9f 7a0b vldr s14, \[pc, #44\] ; 00000044 <thumb2_ldr\+0x44>
-00000018 <thumb2_ldr\+0x18> ed9f ea0a vldr s28, \[pc, #40\] ; 00000044 <thumb2_ldr\+0x44>
-0000001c <thumb2_ldr\+0x1c> eddf fa09 vldr s31, \[pc, #36\] ; 00000044 <thumb2_ldr\+0x44>
-00000020 <thumb2_ldr\+0x20> ed9f 0a09 vldr s0, \[pc, #36\] ; 00000048 <thumb2_ldr\+0x48>
-00000024 <thumb2_ldr\+0x24> ed9f 7a08 vldr s14, \[pc, #32\] ; 00000048 <thumb2_ldr\+0x48>
-00000028 <thumb2_ldr\+0x28> ed9f ea07 vldr s28, \[pc, #28\] ; 00000048 <thumb2_ldr\+0x48>
-0000002c <thumb2_ldr\+0x2c> eddf fa06 vldr s31, \[pc, #24\] ; 00000048 <thumb2_ldr\+0x48>
-00000030 <thumb2_ldr\+0x30> ed9f 0a06 vldr s0, \[pc, #24\] ; 0000004c <thumb2_ldr\+0x4c>
-00000034 <thumb2_ldr\+0x34> ed9f 7a05 vldr s14, \[pc, #20\] ; 0000004c <thumb2_ldr\+0x4c>
-00000038 <thumb2_ldr\+0x38> ed9f ea04 vldr s28, \[pc, #16\] ; 0000004c <thumb2_ldr\+0x4c>
-0000003c <thumb2_ldr\+0x3c> eddf fa03 vldr s31, \[pc, #12\] ; 0000004c <thumb2_ldr\+0x4c>
+00000000 <thumb2_ldr> ed9f 0a0f vldr s0, \[pc, #60\] @ 00000040 <thumb2_ldr\+0x40>
+00000004 <thumb2_ldr\+0x4> ed9f 7a0e vldr s14, \[pc, #56\] @ 00000040 <thumb2_ldr\+0x40>
+00000008 <thumb2_ldr\+0x8> ed9f ea0d vldr s28, \[pc, #52\] @ 00000040 <thumb2_ldr\+0x40>
+0000000c <thumb2_ldr\+0xc> eddf fa0c vldr s31, \[pc, #48\] @ 00000040 <thumb2_ldr\+0x40>
+00000010 <thumb2_ldr\+0x10> ed9f 0a0c vldr s0, \[pc, #48\] @ 00000044 <thumb2_ldr\+0x44>
+00000014 <thumb2_ldr\+0x14> ed9f 7a0b vldr s14, \[pc, #44\] @ 00000044 <thumb2_ldr\+0x44>
+00000018 <thumb2_ldr\+0x18> ed9f ea0a vldr s28, \[pc, #40\] @ 00000044 <thumb2_ldr\+0x44>
+0000001c <thumb2_ldr\+0x1c> eddf fa09 vldr s31, \[pc, #36\] @ 00000044 <thumb2_ldr\+0x44>
+00000020 <thumb2_ldr\+0x20> ed9f 0a09 vldr s0, \[pc, #36\] @ 00000048 <thumb2_ldr\+0x48>
+00000024 <thumb2_ldr\+0x24> ed9f 7a08 vldr s14, \[pc, #32\] @ 00000048 <thumb2_ldr\+0x48>
+00000028 <thumb2_ldr\+0x28> ed9f ea07 vldr s28, \[pc, #28\] @ 00000048 <thumb2_ldr\+0x48>
+0000002c <thumb2_ldr\+0x2c> eddf fa06 vldr s31, \[pc, #24\] @ 00000048 <thumb2_ldr\+0x48>
+00000030 <thumb2_ldr\+0x30> ed9f 0a06 vldr s0, \[pc, #24\] @ 0000004c <thumb2_ldr\+0x4c>
+00000034 <thumb2_ldr\+0x34> ed9f 7a05 vldr s14, \[pc, #20\] @ 0000004c <thumb2_ldr\+0x4c>
+00000038 <thumb2_ldr\+0x38> ed9f ea04 vldr s28, \[pc, #16\] @ 0000004c <thumb2_ldr\+0x4c>
+0000003c <thumb2_ldr\+0x3c> eddf fa03 vldr s31, \[pc, #12\] @ 0000004c <thumb2_ldr\+0x4c>
00000040 <thumb2_ldr\+0x40> 00000000 .word 0x00000000
00000044 <thumb2_ldr\+0x44> ff000000 .word 0xff000000
00000048 <thumb2_ldr\+0x48> ffffffff .word 0xffffffff
0000004c <thumb2_ldr\+0x4c> 0fff0000 .word 0x0fff0000
-00000050 <thumb2_ldr\+0x50> ed9f 0a0f vldr s0, \[pc, #60\] ; 00000090 <thumb2_ldr\+0x90>
-00000054 <thumb2_ldr\+0x54> ed9f 7a0e vldr s14, \[pc, #56\] ; 00000090 <thumb2_ldr\+0x90>
-00000058 <thumb2_ldr\+0x58> ed9f ea0d vldr s28, \[pc, #52\] ; 00000090 <thumb2_ldr\+0x90>
-0000005c <thumb2_ldr\+0x5c> eddf fa0c vldr s31, \[pc, #48\] ; 00000090 <thumb2_ldr\+0x90>
-00000060 <thumb2_ldr\+0x60> ed9f 0a0c vldr s0, \[pc, #48\] ; 00000094 <thumb2_ldr\+0x94>
-00000064 <thumb2_ldr\+0x64> ed9f 7a0b vldr s14, \[pc, #44\] ; 00000094 <thumb2_ldr\+0x94>
-00000068 <thumb2_ldr\+0x68> ed9f ea0a vldr s28, \[pc, #40\] ; 00000094 <thumb2_ldr\+0x94>
-0000006c <thumb2_ldr\+0x6c> eddf fa09 vldr s31, \[pc, #36\] ; 00000094 <thumb2_ldr\+0x94>
-00000070 <thumb2_ldr\+0x70> ed9f 0a09 vldr s0, \[pc, #36\] ; 00000098 <thumb2_ldr\+0x98>
-00000074 <thumb2_ldr\+0x74> ed9f 7a08 vldr s14, \[pc, #32\] ; 00000098 <thumb2_ldr\+0x98>
-00000078 <thumb2_ldr\+0x78> ed9f ea07 vldr s28, \[pc, #28\] ; 00000098 <thumb2_ldr\+0x98>
-0000007c <thumb2_ldr\+0x7c> eddf fa06 vldr s31, \[pc, #24\] ; 00000098 <thumb2_ldr\+0x98>
-00000080 <thumb2_ldr\+0x80> ed9f 0a06 vldr s0, \[pc, #24\] ; 0000009c <thumb2_ldr\+0x9c>
-00000084 <thumb2_ldr\+0x84> ed9f 7a05 vldr s14, \[pc, #20\] ; 0000009c <thumb2_ldr\+0x9c>
-00000088 <thumb2_ldr\+0x88> ed9f ea04 vldr s28, \[pc, #16\] ; 0000009c <thumb2_ldr\+0x9c>
-0000008c <thumb2_ldr\+0x8c> eddf fa03 vldr s31, \[pc, #12\] ; 0000009c <thumb2_ldr\+0x9c>
+00000050 <thumb2_ldr\+0x50> ed9f 0a0f vldr s0, \[pc, #60\] @ 00000090 <thumb2_ldr\+0x90>
+00000054 <thumb2_ldr\+0x54> ed9f 7a0e vldr s14, \[pc, #56\] @ 00000090 <thumb2_ldr\+0x90>
+00000058 <thumb2_ldr\+0x58> ed9f ea0d vldr s28, \[pc, #52\] @ 00000090 <thumb2_ldr\+0x90>
+0000005c <thumb2_ldr\+0x5c> eddf fa0c vldr s31, \[pc, #48\] @ 00000090 <thumb2_ldr\+0x90>
+00000060 <thumb2_ldr\+0x60> ed9f 0a0c vldr s0, \[pc, #48\] @ 00000094 <thumb2_ldr\+0x94>
+00000064 <thumb2_ldr\+0x64> ed9f 7a0b vldr s14, \[pc, #44\] @ 00000094 <thumb2_ldr\+0x94>
+00000068 <thumb2_ldr\+0x68> ed9f ea0a vldr s28, \[pc, #40\] @ 00000094 <thumb2_ldr\+0x94>
+0000006c <thumb2_ldr\+0x6c> eddf fa09 vldr s31, \[pc, #36\] @ 00000094 <thumb2_ldr\+0x94>
+00000070 <thumb2_ldr\+0x70> ed9f 0a09 vldr s0, \[pc, #36\] @ 00000098 <thumb2_ldr\+0x98>
+00000074 <thumb2_ldr\+0x74> ed9f 7a08 vldr s14, \[pc, #32\] @ 00000098 <thumb2_ldr\+0x98>
+00000078 <thumb2_ldr\+0x78> ed9f ea07 vldr s28, \[pc, #28\] @ 00000098 <thumb2_ldr\+0x98>
+0000007c <thumb2_ldr\+0x7c> eddf fa06 vldr s31, \[pc, #24\] @ 00000098 <thumb2_ldr\+0x98>
+00000080 <thumb2_ldr\+0x80> ed9f 0a06 vldr s0, \[pc, #24\] @ 0000009c <thumb2_ldr\+0x9c>
+00000084 <thumb2_ldr\+0x84> ed9f 7a05 vldr s14, \[pc, #20\] @ 0000009c <thumb2_ldr\+0x9c>
+00000088 <thumb2_ldr\+0x88> ed9f ea04 vldr s28, \[pc, #16\] @ 0000009c <thumb2_ldr\+0x9c>
+0000008c <thumb2_ldr\+0x8c> eddf fa03 vldr s31, \[pc, #12\] @ 0000009c <thumb2_ldr\+0x9c>
00000090 <thumb2_ldr\+0x90> 00000000 .word 0x00000000
00000094 <thumb2_ldr\+0x94> 00ff0000 .word 0x00ff0000
00000098 <thumb2_ldr\+0x98> ff00ffff .word 0xff00ffff
@@ -52,18 +52,18 @@ Disassembly of section .text:
000000a4 <thumb2_ldr\+0xa4> ef80 ee30 vmov.i64 d14, #0x0000000000000000
000000a8 <thumb2_ldr\+0xa8> efc0 ce30 vmov.i64 d28, #0x0000000000000000
000000ac <thumb2_ldr\+0xac> efc0 fe30 vmov.i64 d31, #0x0000000000000000
-000000b0 <thumb2_ldr\+0xb0> ed9f 0b0b vldr d0, \[pc, #44\] ; 000000e0 <thumb2_ldr\+0xe0>
-000000b4 <thumb2_ldr\+0xb4> ed9f eb0a vldr d14, \[pc, #40\] ; 000000e0 <thumb2_ldr\+0xe0>
-000000b8 <thumb2_ldr\+0xb8> eddf cb09 vldr d28, \[pc, #36\] ; 000000e0 <thumb2_ldr\+0xe0>
-000000bc <thumb2_ldr\+0xbc> eddf fb08 vldr d31, \[pc, #32\] ; 000000e0 <thumb2_ldr\+0xe0>
+000000b0 <thumb2_ldr\+0xb0> ed9f 0b0b vldr d0, \[pc, #44\] @ 000000e0 <thumb2_ldr\+0xe0>
+000000b4 <thumb2_ldr\+0xb4> ed9f eb0a vldr d14, \[pc, #40\] @ 000000e0 <thumb2_ldr\+0xe0>
+000000b8 <thumb2_ldr\+0xb8> eddf cb09 vldr d28, \[pc, #36\] @ 000000e0 <thumb2_ldr\+0xe0>
+000000bc <thumb2_ldr\+0xbc> eddf fb08 vldr d31, \[pc, #32\] @ 000000e0 <thumb2_ldr\+0xe0>
000000c0 <thumb2_ldr\+0xc0> ff87 0e3f vmov.i64 d0, #0xffffffffffffffff
000000c4 <thumb2_ldr\+0xc4> ff87 ee3f vmov.i64 d14, #0xffffffffffffffff
000000c8 <thumb2_ldr\+0xc8> ffc7 ce3f vmov.i64 d28, #0xffffffffffffffff
000000cc <thumb2_ldr\+0xcc> ffc7 fe3f vmov.i64 d31, #0xffffffffffffffff
-000000d0 <thumb2_ldr\+0xd0> ed9f 0b05 vldr d0, \[pc, #20\] ; 000000e8 <thumb2_ldr\+0xe8>
-000000d4 <thumb2_ldr\+0xd4> ed9f eb04 vldr d14, \[pc, #16\] ; 000000e8 <thumb2_ldr\+0xe8>
-000000d8 <thumb2_ldr\+0xd8> eddf cb03 vldr d28, \[pc, #12\] ; 000000e8 <thumb2_ldr\+0xe8>
-000000dc <thumb2_ldr\+0xdc> eddf fb02 vldr d31, \[pc, #8\] ; 000000e8 <thumb2_ldr\+0xe8>
+000000d0 <thumb2_ldr\+0xd0> ed9f 0b05 vldr d0, \[pc, #20\] @ 000000e8 <thumb2_ldr\+0xe8>
+000000d4 <thumb2_ldr\+0xd4> ed9f eb04 vldr d14, \[pc, #16\] @ 000000e8 <thumb2_ldr\+0xe8>
+000000d8 <thumb2_ldr\+0xd8> eddf cb03 vldr d28, \[pc, #12\] @ 000000e8 <thumb2_ldr\+0xe8>
+000000dc <thumb2_ldr\+0xdc> eddf fb02 vldr d31, \[pc, #8\] @ 000000e8 <thumb2_ldr\+0xe8>
000000e0 <thumb2_ldr\+0xe0> 00000000 .word 0x00000000
000000e4 <thumb2_ldr\+0xe4> ca000000 .word 0xca000000
000000e8 <thumb2_ldr\+0xe8> 00000000 .word 0x00000000
@@ -80,10 +80,10 @@ Disassembly of section .text:
00000114 <thumb2_ldr\+0x114> ef80 ee39 vmov.i64 d14, #0x00000000ff0000ff
00000118 <thumb2_ldr\+0x118> efc0 ce39 vmov.i64 d28, #0x00000000ff0000ff
0000011c <thumb2_ldr\+0x11c> efc0 fe39 vmov.i64 d31, #0x00000000ff0000ff
-00000120 <thumb2_ldr\+0x120> ed9f 0b03 vldr d0, \[pc, #12\] ; 00000130 <thumb2_ldr\+0x130>
-00000124 <thumb2_ldr\+0x124> ed9f eb02 vldr d14, \[pc, #8\] ; 00000130 <thumb2_ldr\+0x130>
-00000128 <thumb2_ldr\+0x128> eddf cb01 vldr d28, \[pc, #4\] ; 00000130 <thumb2_ldr\+0x130>
-0000012c <thumb2_ldr\+0x12c> eddf fb00 vldr d31, \[pc\] ; 00000130 <thumb2_ldr\+0x130>
+00000120 <thumb2_ldr\+0x120> ed9f 0b03 vldr d0, \[pc, #12\] @ 00000130 <thumb2_ldr\+0x130>
+00000124 <thumb2_ldr\+0x124> ed9f eb02 vldr d14, \[pc, #8\] @ 00000130 <thumb2_ldr\+0x130>
+00000128 <thumb2_ldr\+0x128> eddf cb01 vldr d28, \[pc, #4\] @ 00000130 <thumb2_ldr\+0x130>
+0000012c <thumb2_ldr\+0x12c> eddf fb00 vldr d31, \[pc\] @ 00000130 <thumb2_ldr\+0x130>
00000130 <thumb2_ldr\+0x130> 00000000 .word 0x00000000
00000134 <thumb2_ldr\+0x134> 00fff000 .word 0x00fff000
00000138 <thumb2_ldr\+0x138> ef80 0e30 vmov.i64 d0, #0x0000000000000000
@@ -98,57 +98,57 @@ Disassembly of section .text:
0000015c <thumb2_ldr\+0x15c> ff87 ee3f vmov.i64 d14, #0xffffffffffffffff
00000160 <thumb2_ldr\+0x160> ffc7 ce3f vmov.i64 d28, #0xffffffffffffffff
00000164 <thumb2_ldr\+0x164> ffc7 fe3f vmov.i64 d31, #0xffffffffffffffff
-00000168 <thumb2_ldr\+0x168> ed9f 0b03 vldr d0, \[pc, #12\] ; 00000178 <thumb2_ldr\+0x178>
-0000016c <thumb2_ldr\+0x16c> ed9f eb02 vldr d14, \[pc, #8\] ; 00000178 <thumb2_ldr\+0x178>
-00000170 <thumb2_ldr\+0x170> eddf cb01 vldr d28, \[pc, #4\] ; 00000178 <thumb2_ldr\+0x178>
-00000174 <thumb2_ldr\+0x174> eddf fb00 vldr d31, \[pc\] ; 00000178 <thumb2_ldr\+0x178>
+00000168 <thumb2_ldr\+0x168> ed9f 0b03 vldr d0, \[pc, #12\] @ 00000178 <thumb2_ldr\+0x178>
+0000016c <thumb2_ldr\+0x16c> ed9f eb02 vldr d14, \[pc, #8\] @ 00000178 <thumb2_ldr\+0x178>
+00000170 <thumb2_ldr\+0x170> eddf cb01 vldr d28, \[pc, #4\] @ 00000178 <thumb2_ldr\+0x178>
+00000174 <thumb2_ldr\+0x174> eddf fb00 vldr d31, \[pc\] @ 00000178 <thumb2_ldr\+0x178>
00000178 <thumb2_ldr\+0x178> 0fff0000 .word 0x0fff0000
0000017c <thumb2_ldr\+0x17c> 00000000 .word 0x00000000
00000180 <thumb2_ldr\+0x180> ef80 0e30 vmov.i64 d0, #0x0000000000000000
00000184 <thumb2_ldr\+0x184> ef80 ee30 vmov.i64 d14, #0x0000000000000000
00000188 <thumb2_ldr\+0x188> efc0 ce30 vmov.i64 d28, #0x0000000000000000
0000018c <thumb2_ldr\+0x18c> efc0 fe30 vmov.i64 d31, #0x0000000000000000
-00000190 <thumb2_ldr\+0x190> ed9f 0b0b vldr d0, \[pc, #44\] ; 000001c0 <thumb2_ldr\+0x1c0>
-00000194 <thumb2_ldr\+0x194> ed9f eb0a vldr d14, \[pc, #40\] ; 000001c0 <thumb2_ldr\+0x1c0>
-00000198 <thumb2_ldr\+0x198> eddf cb09 vldr d28, \[pc, #36\] ; 000001c0 <thumb2_ldr\+0x1c0>
-0000019c <thumb2_ldr\+0x19c> eddf fb08 vldr d31, \[pc, #32\] ; 000001c0 <thumb2_ldr\+0x1c0>
-000001a0 <thumb2_ldr\+0x1a0> ed9f 0b09 vldr d0, \[pc, #36\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001a4 <thumb2_ldr\+0x1a4> ed9f eb08 vldr d14, \[pc, #32\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001a8 <thumb2_ldr\+0x1a8> eddf cb07 vldr d28, \[pc, #28\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001ac <thumb2_ldr\+0x1ac> eddf fb06 vldr d31, \[pc, #24\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001b0 <thumb2_ldr\+0x1b0> ed9f 0b05 vldr d0, \[pc, #20\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001b4 <thumb2_ldr\+0x1b4> ed9f eb04 vldr d14, \[pc, #16\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001b8 <thumb2_ldr\+0x1b8> eddf cb03 vldr d28, \[pc, #12\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001bc <thumb2_ldr\+0x1bc> eddf fb02 vldr d31, \[pc, #8\] ; 000001c8 <thumb2_ldr\+0x1c8>
+00000190 <thumb2_ldr\+0x190> ed9f 0b0b vldr d0, \[pc, #44\] @ 000001c0 <thumb2_ldr\+0x1c0>
+00000194 <thumb2_ldr\+0x194> ed9f eb0a vldr d14, \[pc, #40\] @ 000001c0 <thumb2_ldr\+0x1c0>
+00000198 <thumb2_ldr\+0x198> eddf cb09 vldr d28, \[pc, #36\] @ 000001c0 <thumb2_ldr\+0x1c0>
+0000019c <thumb2_ldr\+0x19c> eddf fb08 vldr d31, \[pc, #32\] @ 000001c0 <thumb2_ldr\+0x1c0>
+000001a0 <thumb2_ldr\+0x1a0> ed9f 0b09 vldr d0, \[pc, #36\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001a4 <thumb2_ldr\+0x1a4> ed9f eb08 vldr d14, \[pc, #32\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001a8 <thumb2_ldr\+0x1a8> eddf cb07 vldr d28, \[pc, #28\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001ac <thumb2_ldr\+0x1ac> eddf fb06 vldr d31, \[pc, #24\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001b0 <thumb2_ldr\+0x1b0> ed9f 0b05 vldr d0, \[pc, #20\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001b4 <thumb2_ldr\+0x1b4> ed9f eb04 vldr d14, \[pc, #16\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001b8 <thumb2_ldr\+0x1b8> eddf cb03 vldr d28, \[pc, #12\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001bc <thumb2_ldr\+0x1bc> eddf fb02 vldr d31, \[pc, #8\] @ 000001c8 <thumb2_ldr\+0x1c8>
000001c0 <thumb2_ldr\+0x1c0> 000ff000 .word 0x000ff000
000001c4 <thumb2_ldr\+0x1c4> 00000000 .word 0x00000000
000001c8 <thumb2_ldr\+0x1c8> 0ff00fff .word 0x0ff00fff
000001cc <thumb2_ldr\+0x1cc> f0000000 .word 0xf0000000
-000001d0 <thumb2_ldr\+0x1d0> ed9f 1b01 vldr d1, \[pc, #4\] ; 000001d8 <thumb2_ldr\+0x1d8>
+000001d0 <thumb2_ldr\+0x1d0> ed9f 1b01 vldr d1, \[pc, #4\] @ 000001d8 <thumb2_ldr\+0x1d8>
000001d4 <thumb2_ldr\+0x1d4> 00000000 .word 0x00000000
000001d8 <thumb2_ldr\+0x1d8> 0000fff0 .word 0x0000fff0
000001dc <thumb2_ldr\+0x1dc> 00000000 .word 0x00000000
000001e0 <thumb2_ldr\+0x1e0> f101 0000 add.w r0, r1, #0
-000001e4 <thumb2_ldr\+0x1e4> ed9f 1b00 vldr d1, \[pc\] ; 000001e8 <thumb2_ldr\+0x1e8>
+000001e4 <thumb2_ldr\+0x1e4> ed9f 1b00 vldr d1, \[pc\] @ 000001e8 <thumb2_ldr\+0x1e8>
000001e8 <thumb2_ldr\+0x1e8> 0000fff0 .word 0x0000fff0
000001ec <thumb2_ldr\+0x1ec> 00000000 .word 0x00000000
-000001f0 <thumb2_ldr\+0x1f0> ed9f 1b11 vldr d1, \[pc, #68\] ; 00000238 <thumb2_ldr\+0x238>
-000001f4 <thumb2_ldr\+0x1f4> ed9f 1a12 vldr s2, \[pc, #72\] ; 00000240 <thumb2_ldr\+0x240>
-000001f8 <thumb2_ldr\+0x1f8> ed9f 3b13 vldr d3, \[pc, #76\] ; 00000248 <thumb2_ldr\+0x248>
-000001fc <thumb2_ldr\+0x1fc> ed9f 2a11 vldr s4, \[pc, #68\] ; 00000244 <thumb2_ldr\+0x244>
-00000200 <thumb2_ldr\+0x200> ed9f 5b11 vldr d5, \[pc, #68\] ; 00000248 <thumb2_ldr\+0x248>
-00000204 <thumb2_ldr\+0x204> ed9f 6b12 vldr d6, \[pc, #72\] ; 00000250 <thumb2_ldr\+0x250>
-00000208 <thumb2_ldr\+0x208> ed9f 7b13 vldr d7, \[pc, #76\] ; 00000258 <thumb2_ldr\+0x258>
-0000020c <thumb2_ldr\+0x20c> ed9f 4a14 vldr s8, \[pc, #80\] ; 00000260 <thumb2_ldr\+0x260>
-00000210 <thumb2_ldr\+0x210> ed9f 9b15 vldr d9, \[pc, #84\] ; 00000268 <thumb2_ldr\+0x268>
-00000214 <thumb2_ldr\+0x214> ed9f 5a13 vldr s10, \[pc, #76\] ; 00000264 <thumb2_ldr\+0x264>
-00000218 <thumb2_ldr\+0x218> ed9f bb15 vldr d11, \[pc, #84\] ; 00000270 <thumb2_ldr\+0x270>
-0000021c <thumb2_ldr\+0x21c> ed9f 6a16 vldr s12, \[pc, #88\] ; 00000278 <thumb2_ldr\+0x278>
-00000220 <thumb2_ldr\+0x220> eddf 6a16 vldr s13, \[pc, #88\] ; 0000027c <thumb2_ldr\+0x27c>
-00000224 <thumb2_ldr\+0x224> ed9f 7a07 vldr s14, \[pc, #28\] ; 00000244 <thumb2_ldr\+0x244>
-00000228 <thumb2_ldr\+0x228> eddf 7a03 vldr s15, \[pc, #12\] ; 00000238 <thumb2_ldr\+0x238>
-0000022c <thumb2_ldr\+0x22c> eddf 0b14 vldr d16, \[pc, #80\] ; 00000280 <thumb2_ldr\+0x280>
-00000230 <thumb2_ldr\+0x230> eddf 1b15 vldr d17, \[pc, #84\] ; 00000288 <thumb2_ldr\+0x288>
+000001f0 <thumb2_ldr\+0x1f0> ed9f 1b11 vldr d1, \[pc, #68\] @ 00000238 <thumb2_ldr\+0x238>
+000001f4 <thumb2_ldr\+0x1f4> ed9f 1a12 vldr s2, \[pc, #72\] @ 00000240 <thumb2_ldr\+0x240>
+000001f8 <thumb2_ldr\+0x1f8> ed9f 3b13 vldr d3, \[pc, #76\] @ 00000248 <thumb2_ldr\+0x248>
+000001fc <thumb2_ldr\+0x1fc> ed9f 2a11 vldr s4, \[pc, #68\] @ 00000244 <thumb2_ldr\+0x244>
+00000200 <thumb2_ldr\+0x200> ed9f 5b11 vldr d5, \[pc, #68\] @ 00000248 <thumb2_ldr\+0x248>
+00000204 <thumb2_ldr\+0x204> ed9f 6b12 vldr d6, \[pc, #72\] @ 00000250 <thumb2_ldr\+0x250>
+00000208 <thumb2_ldr\+0x208> ed9f 7b13 vldr d7, \[pc, #76\] @ 00000258 <thumb2_ldr\+0x258>
+0000020c <thumb2_ldr\+0x20c> ed9f 4a14 vldr s8, \[pc, #80\] @ 00000260 <thumb2_ldr\+0x260>
+00000210 <thumb2_ldr\+0x210> ed9f 9b15 vldr d9, \[pc, #84\] @ 00000268 <thumb2_ldr\+0x268>
+00000214 <thumb2_ldr\+0x214> ed9f 5a13 vldr s10, \[pc, #76\] @ 00000264 <thumb2_ldr\+0x264>
+00000218 <thumb2_ldr\+0x218> ed9f bb15 vldr d11, \[pc, #84\] @ 00000270 <thumb2_ldr\+0x270>
+0000021c <thumb2_ldr\+0x21c> ed9f 6a16 vldr s12, \[pc, #88\] @ 00000278 <thumb2_ldr\+0x278>
+00000220 <thumb2_ldr\+0x220> eddf 6a16 vldr s13, \[pc, #88\] @ 0000027c <thumb2_ldr\+0x27c>
+00000224 <thumb2_ldr\+0x224> ed9f 7a07 vldr s14, \[pc, #28\] @ 00000244 <thumb2_ldr\+0x244>
+00000228 <thumb2_ldr\+0x228> eddf 7a03 vldr s15, \[pc, #12\] @ 00000238 <thumb2_ldr\+0x238>
+0000022c <thumb2_ldr\+0x22c> eddf 0b14 vldr d16, \[pc, #80\] @ 00000280 <thumb2_ldr\+0x280>
+00000230 <thumb2_ldr\+0x230> eddf 1b15 vldr d17, \[pc, #84\] @ 00000288 <thumb2_ldr\+0x288>
00000234 <thumb2_ldr\+0x234> 00000000 .word 0x00000000
00000238 <thumb2_ldr\+0x238> 0000fff0 .word 0x0000fff0
0000023c <thumb2_ldr\+0x23c> 00000000 .word 0x00000000
diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d
index f265f5af0c1..18573bc3b6f 100644
--- a/gas/testsuite/gas/arm/thumb32.d
+++ b/gas/testsuite/gas/arm/thumb32.d
@@ -7,41 +7,41 @@
Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f041 0000 orr\.w r0, r1, #0
-0[0-9a-f]+ <[^>]+> f041 00a5 orr\.w r0, r1, #165 ; 0xa5
-0[0-9a-f]+ <[^>]+> f041 10a5 orr\.w r0, r1, #10813605 ; 0xa500a5
-0[0-9a-f]+ <[^>]+> f041 20a5 orr\.w r0, r1, #2768282880 ; 0xa500a500
-0[0-9a-f]+ <[^>]+> f041 30a5 orr\.w r0, r1, #2779096485 ; 0xa5a5a5a5
-0[0-9a-f]+ <[^>]+> f041 4000 orr\.w r0, r1, #2147483648 ; 0x80000000
-0[0-9a-f]+ <[^>]+> f041 4080 orr\.w r0, r1, #1073741824 ; 0x40000000
-0[0-9a-f]+ <[^>]+> f041 4020 orr\.w r0, r1, #2684354560 ; 0xa0000000
-0[0-9a-f]+ <[^>]+> f041 40a0 orr\.w r0, r1, #1342177280 ; 0x50000000
-0[0-9a-f]+ <[^>]+> f041 5020 orr\.w r0, r1, #671088640 ; 0x28000000
-0[0-9a-f]+ <[^>]+> f041 4014 orr\.w r0, r1, #2483027968 ; 0x94000000
-0[0-9a-f]+ <[^>]+> f041 4094 orr\.w r0, r1, #1241513984 ; 0x4a000000
-0[0-9a-f]+ <[^>]+> f041 4025 orr\.w r0, r1, #2768240640 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f041 40a5 orr\.w r0, r1, #1384120320 ; 0x52800000
-0[0-9a-f]+ <[^>]+> f041 5025 orr\.w r0, r1, #692060160 ; 0x29400000
-0[0-9a-f]+ <[^>]+> f041 50a5 orr\.w r0, r1, #346030080 ; 0x14a00000
-0[0-9a-f]+ <[^>]+> f041 6025 orr\.w r0, r1, #173015040 ; 0xa500000
-0[0-9a-f]+ <[^>]+> f041 60a5 orr\.w r0, r1, #86507520 ; 0x5280000
-0[0-9a-f]+ <[^>]+> f041 7025 orr\.w r0, r1, #43253760 ; 0x2940000
-0[0-9a-f]+ <[^>]+> f041 70a5 orr\.w r0, r1, #21626880 ; 0x14a0000
-0[0-9a-f]+ <[^>]+> f441 0025 orr\.w r0, r1, #10813440 ; 0xa50000
-0[0-9a-f]+ <[^>]+> f441 00a5 orr\.w r0, r1, #5406720 ; 0x528000
-0[0-9a-f]+ <[^>]+> f441 1025 orr\.w r0, r1, #2703360 ; 0x294000
-0[0-9a-f]+ <[^>]+> f441 10a5 orr\.w r0, r1, #1351680 ; 0x14a000
-0[0-9a-f]+ <[^>]+> f441 2025 orr\.w r0, r1, #675840 ; 0xa5000
-0[0-9a-f]+ <[^>]+> f441 20a5 orr\.w r0, r1, #337920 ; 0x52800
-0[0-9a-f]+ <[^>]+> f441 3025 orr\.w r0, r1, #168960 ; 0x29400
-0[0-9a-f]+ <[^>]+> f441 30a5 orr\.w r0, r1, #84480 ; 0x14a00
-0[0-9a-f]+ <[^>]+> f441 4025 orr\.w r0, r1, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f441 40a5 orr\.w r0, r1, #21120 ; 0x5280
-0[0-9a-f]+ <[^>]+> f441 5025 orr\.w r0, r1, #10560 ; 0x2940
-0[0-9a-f]+ <[^>]+> f441 50a5 orr\.w r0, r1, #5280 ; 0x14a0
-0[0-9a-f]+ <[^>]+> f441 6025 orr\.w r0, r1, #2640 ; 0xa50
-0[0-9a-f]+ <[^>]+> f441 60a5 orr\.w r0, r1, #1320 ; 0x528
-0[0-9a-f]+ <[^>]+> f441 7025 orr\.w r0, r1, #660 ; 0x294
-0[0-9a-f]+ <[^>]+> f441 70a5 orr\.w r0, r1, #330 ; 0x14a
+0[0-9a-f]+ <[^>]+> f041 00a5 orr\.w r0, r1, #165 @ 0xa5
+0[0-9a-f]+ <[^>]+> f041 10a5 orr\.w r0, r1, #10813605 @ 0xa500a5
+0[0-9a-f]+ <[^>]+> f041 20a5 orr\.w r0, r1, #2768282880 @ 0xa500a500
+0[0-9a-f]+ <[^>]+> f041 30a5 orr\.w r0, r1, #2779096485 @ 0xa5a5a5a5
+0[0-9a-f]+ <[^>]+> f041 4000 orr\.w r0, r1, #2147483648 @ 0x80000000
+0[0-9a-f]+ <[^>]+> f041 4080 orr\.w r0, r1, #1073741824 @ 0x40000000
+0[0-9a-f]+ <[^>]+> f041 4020 orr\.w r0, r1, #2684354560 @ 0xa0000000
+0[0-9a-f]+ <[^>]+> f041 40a0 orr\.w r0, r1, #1342177280 @ 0x50000000
+0[0-9a-f]+ <[^>]+> f041 5020 orr\.w r0, r1, #671088640 @ 0x28000000
+0[0-9a-f]+ <[^>]+> f041 4014 orr\.w r0, r1, #2483027968 @ 0x94000000
+0[0-9a-f]+ <[^>]+> f041 4094 orr\.w r0, r1, #1241513984 @ 0x4a000000
+0[0-9a-f]+ <[^>]+> f041 4025 orr\.w r0, r1, #2768240640 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f041 40a5 orr\.w r0, r1, #1384120320 @ 0x52800000
+0[0-9a-f]+ <[^>]+> f041 5025 orr\.w r0, r1, #692060160 @ 0x29400000
+0[0-9a-f]+ <[^>]+> f041 50a5 orr\.w r0, r1, #346030080 @ 0x14a00000
+0[0-9a-f]+ <[^>]+> f041 6025 orr\.w r0, r1, #173015040 @ 0xa500000
+0[0-9a-f]+ <[^>]+> f041 60a5 orr\.w r0, r1, #86507520 @ 0x5280000
+0[0-9a-f]+ <[^>]+> f041 7025 orr\.w r0, r1, #43253760 @ 0x2940000
+0[0-9a-f]+ <[^>]+> f041 70a5 orr\.w r0, r1, #21626880 @ 0x14a0000
+0[0-9a-f]+ <[^>]+> f441 0025 orr\.w r0, r1, #10813440 @ 0xa50000
+0[0-9a-f]+ <[^>]+> f441 00a5 orr\.w r0, r1, #5406720 @ 0x528000
+0[0-9a-f]+ <[^>]+> f441 1025 orr\.w r0, r1, #2703360 @ 0x294000
+0[0-9a-f]+ <[^>]+> f441 10a5 orr\.w r0, r1, #1351680 @ 0x14a000
+0[0-9a-f]+ <[^>]+> f441 2025 orr\.w r0, r1, #675840 @ 0xa5000
+0[0-9a-f]+ <[^>]+> f441 20a5 orr\.w r0, r1, #337920 @ 0x52800
+0[0-9a-f]+ <[^>]+> f441 3025 orr\.w r0, r1, #168960 @ 0x29400
+0[0-9a-f]+ <[^>]+> f441 30a5 orr\.w r0, r1, #84480 @ 0x14a00
+0[0-9a-f]+ <[^>]+> f441 4025 orr\.w r0, r1, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f441 40a5 orr\.w r0, r1, #21120 @ 0x5280
+0[0-9a-f]+ <[^>]+> f441 5025 orr\.w r0, r1, #10560 @ 0x2940
+0[0-9a-f]+ <[^>]+> f441 50a5 orr\.w r0, r1, #5280 @ 0x14a0
+0[0-9a-f]+ <[^>]+> f441 6025 orr\.w r0, r1, #2640 @ 0xa50
+0[0-9a-f]+ <[^>]+> f441 60a5 orr\.w r0, r1, #1320 @ 0x528
+0[0-9a-f]+ <[^>]+> f441 7025 orr\.w r0, r1, #660 @ 0x294
+0[0-9a-f]+ <[^>]+> f441 70a5 orr\.w r0, r1, #330 @ 0x14a
0[0-9a-f]+ <[^>]+> 3000 adds r0, #0
0[0-9a-f]+ <[^>]+> 1c05 adds r5, r0, #0
0[0-9a-f]+ <[^>]+> 1c28 adds r0, r5, #0
@@ -61,9 +61,9 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> eb00 0800 add\.w r8, r0, r0
0[0-9a-f]+ <[^>]+> 4401 add r1, r0
0[0-9a-f]+ <[^>]+> 4408 add r0, r1
-0[0-9a-f]+ <[^>]+> a000 add r0, pc, #0 ; \(adr r0, [0-9a-f]+ <[^>]+>\)
-0[0-9a-f]+ <[^>]+> a500 add r5, pc, #0 ; \(adr r5, [0-9a-f]+ <[^>]+>\)
-0[0-9a-f]+ <[^>]+> a081 add r0, pc, #516 ; \(adr r0, [0-9a-f]+ <[^>]+>\)
+0[0-9a-f]+ <[^>]+> a000 add r0, pc, #0 @ \(adr r0, [0-9a-f]+ <[^>]+>\)
+0[0-9a-f]+ <[^>]+> a500 add r5, pc, #0 @ \(adr r5, [0-9a-f]+ <[^>]+>\)
+0[0-9a-f]+ <[^>]+> a081 add r0, pc, #516 @ \(adr r0, [0-9a-f]+ <[^>]+>\)
0[0-9a-f]+ <[^>]+> a800 add r0, sp, #0
0[0-9a-f]+ <[^>]+> ad00 add r5, sp, #0
0[0-9a-f]+ <[^>]+> a881 add r0, sp, #516.*
@@ -74,8 +74,8 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f110 0000 adds\.w r0, r0, #0
0[0-9a-f]+ <[^>]+> f100 0900 add\.w r9, r0, #0
0[0-9a-f]+ <[^>]+> f109 0000 add\.w r0, r9, #0
-0[0-9a-f]+ <[^>]+> f100 0081 add\.w r0, r0, #129 ; 0x81
-0[0-9a-f]+ <[^>]+> f513 3580 adds\.w r5, r3, #65536 ; 0x10000
+0[0-9a-f]+ <[^>]+> f100 0081 add\.w r0, r0, #129 @ 0x81
+0[0-9a-f]+ <[^>]+> f513 3580 adds\.w r5, r3, #65536 @ 0x10000
0[0-9a-f]+ <[^>]+> f10d 0001 add\.w r0, sp, #1
0[0-9a-f]+ <[^>]+> f10d 0900 add\.w r9, sp, #0
0[0-9a-f]+ <[^>]+> f10d 0d04 add\.w sp, sp, #4
@@ -106,9 +106,9 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> b0c1 sub sp, #260.*
0[0-9a-f]+ <[^>]+> ebb8 0800 subs\.w r8, r8, r0
0[0-9a-f]+ <[^>]+> ebb0 0008 subs\.w r0, r0, r8
-0[0-9a-f]+ <[^>]+> f5b0 7082 subs\.w r0, r0, #260 ; 0x104
+0[0-9a-f]+ <[^>]+> f5b0 7082 subs\.w r0, r0, #260 @ 0x104
0[0-9a-f]+ <[^>]+> f1b2 0104 subs\.w r1, r2, #4
-0[0-9a-f]+ <[^>]+> f5b3 3580 subs\.w r5, r3, #65536 ; 0x10000
+0[0-9a-f]+ <[^>]+> f5b3 3580 subs\.w r5, r3, #65536 @ 0x10000
0[0-9a-f]+ <[^>]+> f1ad 0104 sub\.w r1, sp, #4
0[0-9a-f]+ <[^>]+> f1ad 0900 sub\.w r9, sp, #0
0[0-9a-f]+ <[^>]+> f1ad 0d04 sub\.w sp, sp, #4
@@ -124,7 +124,7 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> eb40 0009 adc\.w r0, r0, r9
0[0-9a-f]+ <[^>]+> eb50 0000 adcs\.w r0, r0, r0
0[0-9a-f]+ <[^>]+> eb41 4062 adc\.w r0, r1, r2, asr #17
-0[0-9a-f]+ <[^>]+> f141 0081 adc\.w r0, r1, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f141 0081 adc\.w r0, r1, #129 @ 0x81
0[0-9a-f]+ <[^>]+> 4000 ands r0, r0
0[0-9a-f]+ <[^>]+> 4005 ands r5, r0
0[0-9a-f]+ <[^>]+> 4028 ands r0, r5
@@ -137,7 +137,7 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> ea00 0009 and\.w r0, r0, r9
0[0-9a-f]+ <[^>]+> ea10 0000 ands\.w r0, r0, r0
0[0-9a-f]+ <[^>]+> ea01 4062 and\.w r0, r1, r2, asr #17
-0[0-9a-f]+ <[^>]+> f001 0081 and\.w r0, r1, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f001 0081 and\.w r0, r1, #129 @ 0x81
0[0-9a-f]+ <[^>]+> 4380 bics r0, r0
0[0-9a-f]+ <[^>]+> 4385 bics r5, r0
0[0-9a-f]+ <[^>]+> 43a8 bics r0, r5
@@ -150,7 +150,7 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> ea20 0009 bic\.w r0, r0, r9
0[0-9a-f]+ <[^>]+> ea30 0000 bics\.w r0, r0, r0
0[0-9a-f]+ <[^>]+> ea21 4062 bic\.w r0, r1, r2, asr #17
-0[0-9a-f]+ <[^>]+> f021 0081 bic\.w r0, r1, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f021 0081 bic\.w r0, r1, #129 @ 0x81
0[0-9a-f]+ <[^>]+> 4040 eors r0, r0
0[0-9a-f]+ <[^>]+> 4045 eors r5, r0
0[0-9a-f]+ <[^>]+> 4068 eors r0, r5
@@ -163,7 +163,7 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> ea80 0009 eor\.w r0, r0, r9
0[0-9a-f]+ <[^>]+> ea90 0000 eors\.w r0, r0, r0
0[0-9a-f]+ <[^>]+> ea81 4062 eor\.w r0, r1, r2, asr #17
-0[0-9a-f]+ <[^>]+> f081 0081 eor\.w r0, r1, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f081 0081 eor\.w r0, r1, #129 @ 0x81
0[0-9a-f]+ <[^>]+> 4300 orrs r0, r0
0[0-9a-f]+ <[^>]+> 4305 orrs r5, r0
0[0-9a-f]+ <[^>]+> 4328 orrs r0, r5
@@ -176,7 +176,7 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> ea40 0009 orr\.w r0, r0, r9
0[0-9a-f]+ <[^>]+> ea50 0000 orrs\.w r0, r0, r0
0[0-9a-f]+ <[^>]+> ea41 4062 orr\.w r0, r1, r2, asr #17
-0[0-9a-f]+ <[^>]+> f041 0081 orr\.w r0, r1, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f041 0081 orr\.w r0, r1, #129 @ 0x81
0[0-9a-f]+ <[^>]+> ebd0 0000 rsbs r0, r0, r0
0[0-9a-f]+ <[^>]+> ebd5 0500 rsbs r5, r5, r0
0[0-9a-f]+ <[^>]+> ebd0 0005 rsbs r0, r0, r5
@@ -189,7 +189,7 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> ebc0 0009 rsb r0, r0, r9
0[0-9a-f]+ <[^>]+> ebd0 0000 rsbs r0, r0, r0
0[0-9a-f]+ <[^>]+> ebc1 4062 rsb r0, r1, r2, asr #17
-0[0-9a-f]+ <[^>]+> f1c1 0081 rsb r0, r1, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f1c1 0081 rsb r0, r1, #129 @ 0x81
0[0-9a-f]+ <[^>]+> 4180 sbcs r0, r0
0[0-9a-f]+ <[^>]+> 4185 sbcs r5, r0
0[0-9a-f]+ <[^>]+> 41a8 sbcs r0, r5
@@ -202,7 +202,7 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> eb60 0009 sbc\.w r0, r0, r9
0[0-9a-f]+ <[^>]+> eb70 0000 sbcs\.w r0, r0, r0
0[0-9a-f]+ <[^>]+> eb61 4062 sbc\.w r0, r1, r2, asr #17
-0[0-9a-f]+ <[^>]+> f161 0081 sbc\.w r0, r1, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f161 0081 sbc\.w r0, r1, #129 @ 0x81
0[0-9a-f]+ <[^>]+> ea70 0000 orns r0, r0, r0
0[0-9a-f]+ <[^>]+> ea75 0500 orns r5, r5, r0
0[0-9a-f]+ <[^>]+> ea70 0005 orns r0, r0, r5
@@ -215,7 +215,7 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> ea60 0009 orn r0, r0, r9
0[0-9a-f]+ <[^>]+> ea70 0000 orns r0, r0, r0
0[0-9a-f]+ <[^>]+> ea61 4062 orn r0, r1, r2, asr #17
-0[0-9a-f]+ <[^>]+> f061 0081 orn r0, r1, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f061 0081 orn r0, r1, #129 @ 0x81
0[0-9a-f]+ <[^>]+> f36f 0000 bfc r0, #0, #1
0[0-9a-f]+ <[^>]+> f36f 0900 bfc r9, #0, #1
0[0-9a-f]+ <[^>]+> f36f 0900 bfc r9, #0, #1
@@ -527,13 +527,13 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f815 fd30 pld \[r5, #-48\]!.*
0[0-9a-f]+ <[^>]+> f815 f004 pld \[r5, r4\]
0[0-9a-f]+ <[^>]+> f819 f00c pld \[r9, ip\]
-0[0-9a-f]+ <[^>]+> f89f f006 pld \[pc, #6\] ; 0+5ee <[^>]+>
-0[0-9a-f]+ <[^>]+> f81f f02a pld \[pc, #-42\] ; 0+5c2 <[^>]+>
+0[0-9a-f]+ <[^>]+> f89f f006 pld \[pc, #6\] @ 0+5ee <[^>]+>
+0[0-9a-f]+ <[^>]+> f81f f02a pld \[pc, #-42\] @ 0+5c2 <[^>]+>
0[0-9a-f]+ <[^>]+> bf00 nop
0[0-9a-f]+ <[^>]+> e9d5 2300 ldrd r2, r3, \[r5\]
0[0-9a-f]+ <[^>]+> e9d5 230c ldrd r2, r3, \[r5, #48\].*
0[0-9a-f]+ <[^>]+> e955 230c ldrd r2, r3, \[r5, #-48\].*
-0[0-9a-f]+ <[^>]+> e95f 4504 ldrd r4, r5, \[pc, #-16\] ; 000005f0 <here>
+0[0-9a-f]+ <[^>]+> e95f 4504 ldrd r4, r5, \[pc, #-16\] @ 000005f0 <here>
0[0-9a-f]+ <[^>]+> e9c5 2300 strd r2, r3, \[r5\]
0[0-9a-f]+ <[^>]+> e9c5 230c strd r2, r3, \[r5, #48\].*
0[0-9a-f]+ <[^>]+> e945 230c strd r2, r3, \[r5, #-48\].*
@@ -586,8 +586,8 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> ea10 0f00 tst\.w r0, r0
0[0-9a-f]+ <[^>]+> ea19 0f00 tst\.w r9, r0
0[0-9a-f]+ <[^>]+> ea10 0f09 tst\.w r0, r9
-0[0-9a-f]+ <[^>]+> f010 0f81 tst\.w r0, #129 ; 0x81
-0[0-9a-f]+ <[^>]+> f015 0f81 tst\.w r5, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f010 0f81 tst\.w r0, #129 @ 0x81
+0[0-9a-f]+ <[^>]+> f015 0f81 tst\.w r5, #129 @ 0x81
0[0-9a-f]+ <[^>]+> ea90 0f00 teq r0, r0
0[0-9a-f]+ <[^>]+> ea90 0f00 teq r0, r0
0[0-9a-f]+ <[^>]+> ea95 0f00 teq r5, r0
@@ -596,8 +596,8 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> ea90 0f00 teq r0, r0
0[0-9a-f]+ <[^>]+> ea99 0f00 teq r9, r0
0[0-9a-f]+ <[^>]+> ea90 0f09 teq r0, r9
-0[0-9a-f]+ <[^>]+> f090 0f81 teq r0, #129 ; 0x81
-0[0-9a-f]+ <[^>]+> f095 0f81 teq r5, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f090 0f81 teq r0, #129 @ 0x81
+0[0-9a-f]+ <[^>]+> f095 0f81 teq r5, #129 @ 0x81
0[0-9a-f]+ <[^>]+> 4280 cmp r0, r0
0[0-9a-f]+ <[^>]+> 4280 cmp r0, r0
0[0-9a-f]+ <[^>]+> 4285 cmp r5, r0
@@ -606,8 +606,8 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> ebb0 0f00 cmp\.w r0, r0
0[0-9a-f]+ <[^>]+> 4581 cmp r9, r0
0[0-9a-f]+ <[^>]+> ebb0 0f09 cmp\.w r0, r9
-0[0-9a-f]+ <[^>]+> f1b0 0f81 cmp\.w r0, #129 ; 0x81
-0[0-9a-f]+ <[^>]+> f1b5 0f81 cmp\.w r5, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f1b0 0f81 cmp\.w r0, #129 @ 0x81
+0[0-9a-f]+ <[^>]+> f1b5 0f81 cmp\.w r5, #129 @ 0x81
0[0-9a-f]+ <[^>]+> 42c0 cmn r0, r0
0[0-9a-f]+ <[^>]+> 42c0 cmn r0, r0
0[0-9a-f]+ <[^>]+> 42c5 cmn r5, r0
@@ -616,8 +616,8 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> eb10 0f00 cmn\.w r0, r0
0[0-9a-f]+ <[^>]+> eb19 0f00 cmn\.w r9, r0
0[0-9a-f]+ <[^>]+> eb10 0f09 cmn\.w r0, r9
-0[0-9a-f]+ <[^>]+> f110 0f81 cmn\.w r0, #129 ; 0x81
-0[0-9a-f]+ <[^>]+> f115 0f81 cmn\.w r5, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f110 0f81 cmn\.w r0, #129 @ 0x81
+0[0-9a-f]+ <[^>]+> f115 0f81 cmn\.w r5, #129 @ 0x81
0[0-9a-f]+ <[^>]+> 0000 movs r0, r0
0[0-9a-f]+ <[^>]+> 4600 mov r0, r0
0[0-9a-f]+ <[^>]+> 0005 movs r5, r0
@@ -626,8 +626,8 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> ea4f 0000 mov\.w r0, r0
0[0-9a-f]+ <[^>]+> ea5f 0900 movs\.w r9, r0
0[0-9a-f]+ <[^>]+> ea5f 0009 movs\.w r0, r9
-0[0-9a-f]+ <[^>]+> f04f 0081 mov\.w r0, #129 ; 0x81
-0[0-9a-f]+ <[^>]+> f04f 0581 mov\.w r5, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f04f 0081 mov\.w r0, #129 @ 0x81
+0[0-9a-f]+ <[^>]+> f04f 0581 mov\.w r5, #129 @ 0x81
0[0-9a-f]+ <[^>]+> 43c0 mvns r0, r0
0[0-9a-f]+ <[^>]+> ea6f 0000 mvn\.w r0, r0
0[0-9a-f]+ <[^>]+> 43c5 mvns r5, r0
@@ -636,16 +636,16 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> ea6f 0000 mvn\.w r0, r0
0[0-9a-f]+ <[^>]+> ea7f 0900 mvns\.w r9, r0
0[0-9a-f]+ <[^>]+> ea7f 0009 mvns\.w r0, r9
-0[0-9a-f]+ <[^>]+> f06f 0081 mvn\.w r0, #129 ; 0x81
-0[0-9a-f]+ <[^>]+> f06f 0581 mvn\.w r5, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f06f 0081 mvn\.w r0, #129 @ 0x81
+0[0-9a-f]+ <[^>]+> f06f 0581 mvn\.w r5, #129 @ 0x81
0[0-9a-f]+ <[^>]+> f240 0000 movw r0, #0
0[0-9a-f]+ <[^>]+> f2c0 0000 movt r0, #0
0[0-9a-f]+ <[^>]+> f240 0900 movw r9, #0
-0[0-9a-f]+ <[^>]+> f249 0000 movw r0, #36864 ; 0x9000
-0[0-9a-f]+ <[^>]+> f640 0000 movw r0, #2048 ; 0x800
-0[0-9a-f]+ <[^>]+> f240 5000 movw r0, #1280 ; 0x500
-0[0-9a-f]+ <[^>]+> f240 0081 movw r0, #129 ; 0x81
-0[0-9a-f]+ <[^>]+> f64f 70ff movw r0, #65535 ; 0xffff
+0[0-9a-f]+ <[^>]+> f249 0000 movw r0, #36864 @ 0x9000
+0[0-9a-f]+ <[^>]+> f640 0000 movw r0, #2048 @ 0x800
+0[0-9a-f]+ <[^>]+> f240 5000 movw r0, #1280 @ 0x500
+0[0-9a-f]+ <[^>]+> f240 0081 movw r0, #129 @ 0x81
+0[0-9a-f]+ <[^>]+> f64f 70ff movw r0, #65535 @ 0xffff
0[0-9a-f]+ <[^>]+> f3ef 8000 mrs r0, CPSR
0[0-9a-f]+ <[^>]+> f3ff 8000 mrs r0, SPSR
0[0-9a-f]+ <[^>]+> f3ef 8900 mrs r9, CPSR
@@ -945,30 +945,30 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> fa52 f183 uxtab r1, r2, r3
0[0-9a-f]+ <[^>]+> fa32 f183 uxtab16 r1, r2, r3
0[0-9a-f]+ <[^>]+> fa12 f183 uxtah r1, r2, r3
-0[0-9a-f]+ <[^>]+> f89f 12aa ldrb\.w r1, \[pc, #682\] ; 0+e86 <[^>]+>
-0[0-9a-f]+ <[^>]+> f89f 1155 ldrb\.w r1, \[pc, #341\] ; 0+d35 <[^>]+>
-0[0-9a-f]+ <[^>]+> f81f 12aa ldrb\.w r1, \[pc, #-682\] ; 0+93a <[^>]+>
-0[0-9a-f]+ <[^>]+> f81f 1155 ldrb\.w r1, \[pc, #-341\] ; 0+a93 <[^>]+>
-0[0-9a-f]+ <[^>]+> f99f 12aa ldrsb\.w r1, \[pc, #682\] ; 0+e96 <[^>]+>
-0[0-9a-f]+ <[^>]+> f99f 1155 ldrsb\.w r1, \[pc, #341\] ; 0+d45 <[^>]+>
-0[0-9a-f]+ <[^>]+> f91f 12aa ldrsb\.w r1, \[pc, #-682\] ; 0+94a <[^>]+>
-0[0-9a-f]+ <[^>]+> f91f 1155 ldrsb\.w r1, \[pc, #-341\] ; 0+aa3 <[^>]+>
-0[0-9a-f]+ <[^>]+> f8bf 12aa ldrh\.w r1, \[pc, #682\] ; 0+ea6 <[^>]+>
-0[0-9a-f]+ <[^>]+> f8bf 1155 ldrh\.w r1, \[pc, #341\] ; 0+d55 <[^>]+>
-0[0-9a-f]+ <[^>]+> f83f 12aa ldrh\.w r1, \[pc, #-682\] ; 0+95a <[^>]+>
-0[0-9a-f]+ <[^>]+> f83f 1155 ldrh\.w r1, \[pc, #-341\] ; 0+ab3 <[^>]+>
-0[0-9a-f]+ <[^>]+> f9bf 12aa ldrsh\.w r1, \[pc, #682\] ; 0+eb6 <[^>]+>
-0[0-9a-f]+ <[^>]+> f9bf 1155 ldrsh\.w r1, \[pc, #341\] ; 0+d65 <[^>]+>
-0[0-9a-f]+ <[^>]+> f93f 12aa ldrsh\.w r1, \[pc, #-682\] ; 0+96a <[^>]+>
-0[0-9a-f]+ <[^>]+> f93f 1155 ldrsh\.w r1, \[pc, #-341\] ; 0+ac3 <[^>]+>
-0[0-9a-f]+ <[^>]+> f8df 12aa ldr\.w r1, \[pc, #682\] ; 0+ec6 <[^>]+>
-0[0-9a-f]+ <[^>]+> f8df 1155 ldr\.w r1, \[pc, #341\] ; 0+d75 <[^>]+>
-0[0-9a-f]+ <[^>]+> f85f 12aa ldr\.w r1, \[pc, #-682\] ; 0+97a <[^>]+>
-0[0-9a-f]+ <[^>]+> f85f 1155 ldr\.w r1, \[pc, #-341\] ; 0+ad3 <[^>]+>
+0[0-9a-f]+ <[^>]+> f89f 12aa ldrb\.w r1, \[pc, #682\] @ 0+e86 <[^>]+>
+0[0-9a-f]+ <[^>]+> f89f 1155 ldrb\.w r1, \[pc, #341\] @ 0+d35 <[^>]+>
+0[0-9a-f]+ <[^>]+> f81f 12aa ldrb\.w r1, \[pc, #-682\] @ 0+93a <[^>]+>
+0[0-9a-f]+ <[^>]+> f81f 1155 ldrb\.w r1, \[pc, #-341\] @ 0+a93 <[^>]+>
+0[0-9a-f]+ <[^>]+> f99f 12aa ldrsb\.w r1, \[pc, #682\] @ 0+e96 <[^>]+>
+0[0-9a-f]+ <[^>]+> f99f 1155 ldrsb\.w r1, \[pc, #341\] @ 0+d45 <[^>]+>
+0[0-9a-f]+ <[^>]+> f91f 12aa ldrsb\.w r1, \[pc, #-682\] @ 0+94a <[^>]+>
+0[0-9a-f]+ <[^>]+> f91f 1155 ldrsb\.w r1, \[pc, #-341\] @ 0+aa3 <[^>]+>
+0[0-9a-f]+ <[^>]+> f8bf 12aa ldrh\.w r1, \[pc, #682\] @ 0+ea6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f8bf 1155 ldrh\.w r1, \[pc, #341\] @ 0+d55 <[^>]+>
+0[0-9a-f]+ <[^>]+> f83f 12aa ldrh\.w r1, \[pc, #-682\] @ 0+95a <[^>]+>
+0[0-9a-f]+ <[^>]+> f83f 1155 ldrh\.w r1, \[pc, #-341\] @ 0+ab3 <[^>]+>
+0[0-9a-f]+ <[^>]+> f9bf 12aa ldrsh\.w r1, \[pc, #682\] @ 0+eb6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f9bf 1155 ldrsh\.w r1, \[pc, #341\] @ 0+d65 <[^>]+>
+0[0-9a-f]+ <[^>]+> f93f 12aa ldrsh\.w r1, \[pc, #-682\] @ 0+96a <[^>]+>
+0[0-9a-f]+ <[^>]+> f93f 1155 ldrsh\.w r1, \[pc, #-341\] @ 0+ac3 <[^>]+>
+0[0-9a-f]+ <[^>]+> f8df 12aa ldr\.w r1, \[pc, #682\] @ 0+ec6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f8df 1155 ldr\.w r1, \[pc, #341\] @ 0+d75 <[^>]+>
+0[0-9a-f]+ <[^>]+> f85f 12aa ldr\.w r1, \[pc, #-682\] @ 0+97a <[^>]+>
+0[0-9a-f]+ <[^>]+> f85f 1155 ldr\.w r1, \[pc, #-341\] @ 0+ad3 <[^>]+>
0[0-9a-f]+ <[^>]+> f200 0900 addw r9, r0, #0
-0[0-9a-f]+ <[^>]+> f60f 76ff addw r6, pc, #4095 ; 0xfff
-0[0-9a-f]+ <[^>]+> f6a9 2685 subw r6, r9, #2693 ; 0xa85
-0[0-9a-f]+ <[^>]+> f2a9 567a subw r6, r9, #1402 ; 0x57a
+0[0-9a-f]+ <[^>]+> f60f 76ff addw r6, pc, #4095 @ 0xfff
+0[0-9a-f]+ <[^>]+> f6a9 2685 subw r6, r9, #2693 @ 0xa85
+0[0-9a-f]+ <[^>]+> f2a9 567a subw r6, r9, #1402 @ 0x57a
0[0-9a-f]+ <[^>]+> e8df f006 tbb \[pc, r6\]
0[0-9a-f]+ <[^>]+> e8d0 f009 tbb \[r0, r9\]
0[0-9a-f]+ <[^>]+> e8df f017 tbh \[pc, r7, lsl #1\]
diff --git a/gas/testsuite/gas/arm/thumbv6.d b/gas/testsuite/gas/arm/thumbv6.d
index 5da70351c23..d189537b4a8 100644
--- a/gas/testsuite/gas/arm/thumbv6.d
+++ b/gas/testsuite/gas/arm/thumbv6.d
@@ -17,7 +17,7 @@ Disassembly of section .text:
0+012 <[^>]*> b251 * sxtb r1, r2
0+014 <[^>]*> b2a3 * uxth r3, r4
0+016 <[^>]*> b2f5 * uxtb r5, r6
-0+018 <[^>]*> 46c0 * nop[ ]+; \(mov r8, r8\)
-0+01a <[^>]*> 46c0 * nop[ ]+; \(mov r8, r8\)
-0+01c <[^>]*> 46c0 * nop[ ]+; \(mov r8, r8\)
-0+01e <[^>]*> 46c0 * nop[ ]+; \(mov r8, r8\)
+0+018 <[^>]*> 46c0 * nop[ ]+@ \(mov r8, r8\)
+0+01a <[^>]*> 46c0 * nop[ ]+@ \(mov r8, r8\)
+0+01c <[^>]*> 46c0 * nop[ ]+@ \(mov r8, r8\)
+0+01e <[^>]*> 46c0 * nop[ ]+@ \(mov r8, r8\)
diff --git a/gas/testsuite/gas/arm/thumbv6k.d b/gas/testsuite/gas/arm/thumbv6k.d
index 1dd30eca8c0..3fe172cd799 100644
--- a/gas/testsuite/gas/arm/thumbv6k.d
+++ b/gas/testsuite/gas/arm/thumbv6k.d
@@ -9,7 +9,7 @@ Disassembly of section .text:
0+002 <[^>]*> bf20 * wfe
0+004 <[^>]*> bf30 * wfi
0+006 <[^>]*> bf40 * sev
-0+008 <[^>]*> 46c0 * nop[ \t]+; \(mov r8, r8\)
-0+00a <[^>]*> 46c0 * nop[ \t]+; \(mov r8, r8\)
-0+00c <[^>]*> 46c0 * nop[ \t]+; \(mov r8, r8\)
-0+00e <[^>]*> 46c0 * nop[ \t]+; \(mov r8, r8\)
+0+008 <[^>]*> 46c0 * nop[ \t]+@ \(mov r8, r8\)
+0+00a <[^>]*> 46c0 * nop[ \t]+@ \(mov r8, r8\)
+0+00c <[^>]*> 46c0 * nop[ \t]+@ \(mov r8, r8\)
+0+00e <[^>]*> 46c0 * nop[ \t]+@ \(mov r8, r8\)
diff --git a/gas/testsuite/gas/arm/tls.d b/gas/testsuite/gas/arm/tls.d
index 23cb903f20a..7eb7af2e970 100644
--- a/gas/testsuite/gas/arm/tls.d
+++ b/gas/testsuite/gas/arm/tls.d
@@ -12,12 +12,12 @@
Disassembly of section .text:
0+00 <arm_fn>:
- 0: e1a00000 nop ; .*
+ 0: e1a00000 nop @ .*
0: R_ARM_TLS_DESCSEQ af
- 4: e59f0014 ldr r0, \[pc, #20\] ; 20 .*
+ 4: e59f0014 ldr r0, \[pc, #20\] @ 20 .*
8: fa000000 blx 8 <ae.*>
8: R_ARM_TLS_CALL ae
- c: e1a00000 nop ; .*
+ c: e1a00000 nop @ .*
0+10 <.arm_pool>:
10: 00000008 .word 0x00000008
10: R_ARM_TLS_GD32 aa
@@ -30,13 +30,13 @@ Disassembly of section .text:
20: 00000018 .word 0x00000018
20: R_ARM_TLS_GOTDESC ae
0+24 <thumb_fn>:
- 24: 46c0 nop ; .*
- 26: 46c0 nop ; .*
+ 24: 46c0 nop @ .*
+ 26: 46c0 nop @ .*
26: R_ARM_THM_TLS_DESCSEQ tf
- 28: 4805 ldr r0, \[pc, #20\] ; \(40 .*\)
+ 28: 4805 ldr r0, \[pc, #20\] @ \(40 .*\)
2a: f000 e800 blx 4 <te.*>
2a: R_ARM_THM_TLS_CALL te
- 2e: 46c0 nop ; .*
+ 2e: 46c0 nop @ .*
30: 00000002 .word 0x00000002
30: R_ARM_TLS_GD32 ta
34: 00000006 .word 0x00000006
diff --git a/gas/testsuite/gas/arm/tls_vxworks.d b/gas/testsuite/gas/arm/tls_vxworks.d
index 80108ac9950..b69326054d8 100644
--- a/gas/testsuite/gas/arm/tls_vxworks.d
+++ b/gas/testsuite/gas/arm/tls_vxworks.d
@@ -13,16 +13,16 @@
Disassembly of section .text:
00+0 <arm_fn>:
- 0: e1a00000 nop \; \(mov r0, r0\)
+ 0: e1a00000 nop \@ \(mov r0, r0\)
0: R_ARM_TLS_DESCSEQ af
- 4: e59f0014 ldr r0, \[pc, \#20\] ; 20 <\.arm_pool\+0x10>
+ 4: e59f0014 ldr r0, \[pc, \#20\] @ 20 <\.arm_pool\+0x10>
8: fa000000 blx 8 <ae\+0x8>
8: R_ARM_TLS_CALL ae
# ??? The addend is appearing in both the RELA field and the
# contents. Shouldn't it be just one? bfd_install_relocation
# appears to write the addend into the contents unconditionally,
# yet somehow this does not happen for the majority of relocations.
- c: e1a00000 nop \; \(mov r0, r0\)
+ c: e1a00000 nop \@ \(mov r0, r0\)
00000010 <.arm_pool>:
10: 00000008 .word 0x00000008
10: R_ARM_TLS_GD32 aa\+0x8
diff --git a/gas/testsuite/gas/arm/udf.d b/gas/testsuite/gas/arm/udf.d
index a6a021e4d03..4e22d7f203a 100644
--- a/gas/testsuite/gas/arm/udf.d
+++ b/gas/testsuite/gas/arm/udf.d
@@ -8,21 +8,21 @@
Disassembly of section \.text:
[^<]*<arm> e7f000f0 udf #0
-[^<]*<arm\+0x4> e7fabcfd udf #43981 ; 0xabcd
-[^<]*<thumb> deab udf #171 ; 0xab
-[^<]*<thumb\+0x2> decd udf #205 ; 0xcd
+[^<]*<arm\+0x4> e7fabcfd udf #43981 @ 0xabcd
+[^<]*<thumb> deab udf #171 @ 0xab
+[^<]*<thumb\+0x2> decd udf #205 @ 0xcd
[^<]*<thumb\+0x4> de00 udf #0
[^<]*<thumb\+0x6> bf00 nop
[^<]*<thumb\+0x8> f7f0 a000 udf.w #0
-[^<]*<thumb\+0xc> f7f1 a234 udf.w #4660 ; 0x1234
-[^<]*<thumb\+0x10> f7fc acdd udf.w #52445 ; 0xccdd
+[^<]*<thumb\+0xc> f7f1 a234 udf.w #4660 @ 0x1234
+[^<]*<thumb\+0x10> f7fc acdd udf.w #52445 @ 0xccdd
[^<]*<thumb\+0x14> bf08 it eq
[^<]*<thumb\+0x16> de12 udfeq #18
-[^<]*<thumb\+0x18> de23 udf #35 ; 0x23
-[^<]*<thumb\+0x1a> de34 udf #52 ; 0x34
-[^<]*<thumb\+0x1c> de56 udf #86 ; 0x56
+[^<]*<thumb\+0x18> de23 udf #35 @ 0x23
+[^<]*<thumb\+0x1a> de34 udf #52 @ 0x34
+[^<]*<thumb\+0x1c> de56 udf #86 @ 0x56
[^<]*<thumb\+0x1e> bf18 it ne
-[^<]*<thumb\+0x20> f7f1 a234 udfne.w #4660 ; 0x1234
-[^<]*<thumb\+0x24> f7f2 a345 udf.w #9029 ; 0x2345
-[^<]*<thumb\+0x28> f7f3 a456 udf.w #13398 ; 0x3456
-[^<]*<thumb\+0x2c> f7f5 a678 udf.w #22136 ; 0x5678
+[^<]*<thumb\+0x20> f7f1 a234 udfne.w #4660 @ 0x1234
+[^<]*<thumb\+0x24> f7f2 a345 udf.w #9029 @ 0x2345
+[^<]*<thumb\+0x28> f7f3 a456 udf.w #13398 @ 0x3456
+[^<]*<thumb\+0x2c> f7f5 a678 udf.w #22136 @ 0x5678
diff --git a/gas/testsuite/gas/arm/unpredictable.d b/gas/testsuite/gas/arm/unpredictable.d
index e78727a44b4..0781c18377c 100644
--- a/gas/testsuite/gas/arm/unpredictable.d
+++ b/gas/testsuite/gas/arm/unpredictable.d
@@ -70,5 +70,5 @@ Disassembly of section .text:
0+0fc <[^>]+> [^<]+<UNPREDICTABLE>
0+100 <[^>]+> [^<]+<UNPREDICTABLE>
0+104 <[^>]+> [^<]+<UNPREDICTABLE>
-0+108 <[^>]+> e1a00000[ ]+nop[ ]+; \(mov r0, r0\)
+0+108 <[^>]+> e1a00000[ ]+nop[ ]+@ \(mov r0, r0\)
#pass
diff --git a/gas/testsuite/gas/arm/vfp-mov-enc.d b/gas/testsuite/gas/arm/vfp-mov-enc.d
index fda47f2b438..962d319c47a 100644
--- a/gas/testsuite/gas/arm/vfp-mov-enc.d
+++ b/gas/testsuite/gas/arm/vfp-mov-enc.d
@@ -5,12 +5,12 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> 4ef2da06 vmovmi.f32 s27, #38 ; 0x41300000 11.0
-0[0-9a-f]+ <[^>]+> 4ef2da06 vmovmi.f32 s27, #38 ; 0x41300000 11.0
-0[0-9a-f]+ <[^>]+> 4ef7da00 vmovmi.f32 s27, #112 ; 0x3f800000 1.0
-0[0-9a-f]+ <[^>]+> 4ef7da00 vmovmi.f32 s27, #112 ; 0x3f800000 1.0
-0[0-9a-f]+ <[^>]+> cebb1b04 vmovgt.f64 d1, #180 ; 0xc1a00000 -20.0
-0[0-9a-f]+ <[^>]+> ceb81b00 vmovgt.f64 d1, #128 ; 0xc0000000 -2.0
-0[0-9a-f]+ <[^>]+> eef0aa00 vmov.f32 s21, #0 ; 0x40000000 2.0
-0[0-9a-f]+ <[^>]+> eef97a07 vmov.f32 s15, #151 ; 0xc0b80000 -5.750
-0[0-9a-f]+ <[^>]+> eefc4a05 vmov.f32 s9, #197 ; 0xbe280000 -0.1640625
+0[0-9a-f]+ <[^>]+> 4ef2da06 vmovmi.f32 s27, #38 @ 0x41300000 11.0
+0[0-9a-f]+ <[^>]+> 4ef2da06 vmovmi.f32 s27, #38 @ 0x41300000 11.0
+0[0-9a-f]+ <[^>]+> 4ef7da00 vmovmi.f32 s27, #112 @ 0x3f800000 1.0
+0[0-9a-f]+ <[^>]+> 4ef7da00 vmovmi.f32 s27, #112 @ 0x3f800000 1.0
+0[0-9a-f]+ <[^>]+> cebb1b04 vmovgt.f64 d1, #180 @ 0xc1a00000 -20.0
+0[0-9a-f]+ <[^>]+> ceb81b00 vmovgt.f64 d1, #128 @ 0xc0000000 -2.0
+0[0-9a-f]+ <[^>]+> eef0aa00 vmov.f32 s21, #0 @ 0x40000000 2.0
+0[0-9a-f]+ <[^>]+> eef97a07 vmov.f32 s15, #151 @ 0xc0b80000 -5.750
+0[0-9a-f]+ <[^>]+> eefc4a05 vmov.f32 s9, #197 @ 0xbe280000 -0.1640625
diff --git a/gas/testsuite/gas/arm/vfp-neon-overlap.d b/gas/testsuite/gas/arm/vfp-neon-overlap.d
index 6c328d3f1e5..16c3e0ade01 100644
--- a/gas/testsuite/gas/arm/vfp-neon-overlap.d
+++ b/gas/testsuite/gas/arm/vfp-neon-overlap.d
@@ -9,10 +9,10 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> ec410b10 vmov d0, r0, r1
0[0-9a-f]+ <[^>]+> ec510b10 vmov r0, r1, d0
0[0-9a-f]+ <[^>]+> ec510b10 vmov r0, r1, d0
-0[0-9a-f]+ <[^>]+> ec900b09 fldmiax r0, {d0-d3}( ;@ Deprecated|)
-0[0-9a-f]+ <[^>]+> ed300b09 fldmdbx r0!, {d0-d3}( ;@ Deprecated|)
-0[0-9a-f]+ <[^>]+> ec800b09 fstmiax r0, {d0-d3}( ;@ Deprecated|)
-0[0-9a-f]+ <[^>]+> ed200b09 fstmdbx r0!, {d0-d3}( ;@ Deprecated|)
+0[0-9a-f]+ <[^>]+> ec900b09 fldmiax r0, {d0-d3}( @ Deprecated|)
+0[0-9a-f]+ <[^>]+> ed300b09 fldmdbx r0!, {d0-d3}( @ Deprecated|)
+0[0-9a-f]+ <[^>]+> ec800b09 fstmiax r0, {d0-d3}( @ Deprecated|)
+0[0-9a-f]+ <[^>]+> ed200b09 fstmdbx r0!, {d0-d3}( @ Deprecated|)
0[0-9a-f]+ <[^>]+> ed900b00 vldr d0, \[r0\]
0[0-9a-f]+ <[^>]+> ed900b00 vldr d0, \[r0\]
0[0-9a-f]+ <[^>]+> ed800b00 vstr d0, \[r0\]
diff --git a/gas/testsuite/gas/arm/vfp1.d b/gas/testsuite/gas/arm/vfp1.d
index a7a127a3da9..e07fe8b785b 100644
--- a/gas/testsuite/gas/arm/vfp1.d
+++ b/gas/testsuite/gas/arm/vfp1.d
@@ -188,6 +188,6 @@ Disassembly of section .text:
0+2c8 <[^>]*> 0e1f7b10 vmoveq\.32 r7, d15\[0\]
0+2cc <[^>]*> 0e21fb10 vmoveq\.32 d1\[1\], pc
0+2d0 <[^>]*> 0e0f1b10 vmoveq\.32 d15\[0\], r1
-0+2d4 <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\)
-0+2d8 <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\)
-0+2dc <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\)
+0+2d4 <[^>]*> e1a00000 ? nop[ ]+@ \(mov r0, r0\)
+0+2d8 <[^>]*> e1a00000 ? nop[ ]+@ \(mov r0, r0\)
+0+2dc <[^>]*> e1a00000 ? nop[ ]+@ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/vfp1xD.d b/gas/testsuite/gas/arm/vfp1xD.d
index 079f7a17e59..5e679d47823 100644
--- a/gas/testsuite/gas/arm/vfp1xD.d
+++ b/gas/testsuite/gas/arm/vfp1xD.d
@@ -33,24 +33,24 @@ Disassembly of section .text:
0+05c <[^>]*> ecb00a01 (vldmia|fldmias) r0!, {s0}
0+060 <[^>]*> ed300a01 (vldmdb|fldmdbs) r0!, {s0}
0+064 <[^>]*> ed300a01 (vldmdb|fldmdbs) r0!, {s0}
-0+068 <[^>]*> ec900b03 fldmiax r0, {d0}( ;@ Deprecated|)
-0+06c <[^>]*> ec900b03 fldmiax r0, {d0}( ;@ Deprecated|)
-0+070 <[^>]*> ecb00b03 fldmiax r0!, {d0}( ;@ Deprecated|)
-0+074 <[^>]*> ecb00b03 fldmiax r0!, {d0}( ;@ Deprecated|)
-0+078 <[^>]*> ed300b03 fldmdbx r0!, {d0}( ;@ Deprecated|)
-0+07c <[^>]*> ed300b03 fldmdbx r0!, {d0}( ;@ Deprecated|)
+0+068 <[^>]*> ec900b03 fldmiax r0, {d0}( @ Deprecated|)
+0+06c <[^>]*> ec900b03 fldmiax r0, {d0}( @ Deprecated|)
+0+070 <[^>]*> ecb00b03 fldmiax r0!, {d0}( @ Deprecated|)
+0+074 <[^>]*> ecb00b03 fldmiax r0!, {d0}( @ Deprecated|)
+0+078 <[^>]*> ed300b03 fldmdbx r0!, {d0}( @ Deprecated|)
+0+07c <[^>]*> ed300b03 fldmdbx r0!, {d0}( @ Deprecated|)
0+080 <[^>]*> ec800a01 (vstmia|fstmias) r0, {s0}
0+084 <[^>]*> ec800a01 (vstmia|fstmias) r0, {s0}
0+088 <[^>]*> eca00a01 (vstmia|fstmias) r0!, {s0}
0+08c <[^>]*> eca00a01 (vstmia|fstmias) r0!, {s0}
0+090 <[^>]*> ed200a01 (vstmdb|fstmdbs) r0!, {s0}
0+094 <[^>]*> ed200a01 (vstmdb|fstmdbs) r0!, {s0}
-0+098 <[^>]*> ec800b03 fstmiax r0, {d0}( ;@ Deprecated|)
-0+09c <[^>]*> ec800b03 fstmiax r0, {d0}( ;@ Deprecated|)
-0+0a0 <[^>]*> eca00b03 fstmiax r0!, {d0}( ;@ Deprecated|)
-0+0a4 <[^>]*> eca00b03 fstmiax r0!, {d0}( ;@ Deprecated|)
-0+0a8 <[^>]*> ed200b03 fstmdbx r0!, {d0}( ;@ Deprecated|)
-0+0ac <[^>]*> ed200b03 fstmdbx r0!, {d0}( ;@ Deprecated|)
+0+098 <[^>]*> ec800b03 fstmiax r0, {d0}( @ Deprecated|)
+0+09c <[^>]*> ec800b03 fstmiax r0, {d0}( @ Deprecated|)
+0+0a0 <[^>]*> eca00b03 fstmiax r0!, {d0}( @ Deprecated|)
+0+0a4 <[^>]*> eca00b03 fstmiax r0!, {d0}( @ Deprecated|)
+0+0a8 <[^>]*> ed200b03 fstmdbx r0!, {d0}( @ Deprecated|)
+0+0ac <[^>]*> ed200b03 fstmdbx r0!, {d0}( @ Deprecated|)
0+0b0 <[^>]*> eeb80ac0 (vcvt\.f32\.s32|fsitos) s0, s0
0+0b4 <[^>]*> eeb80a40 (vcvt\.f32\.u32|fuitos) s0, s0
0+0b8 <[^>]*> eebd0a40 (vcvtr\.s32\.f32|ftosis) s0, s0
@@ -142,17 +142,17 @@ Disassembly of section .text:
0+210 <[^>]*> ec90fa02 (vldmia|fldmias) r0, {s30-s31}
0+214 <[^>]*> ec910a01 (vldmia|fldmias) r1, {s0}
0+218 <[^>]*> ec9e0a01 (vldmia|fldmias) lr, {s0}
-0+21c <[^>]*> ec801b03 fstmiax r0, {d1}( ;@ Deprecated|)
-0+220 <[^>]*> ec802b03 fstmiax r0, {d2}( ;@ Deprecated|)
-0+224 <[^>]*> ec80fb03 fstmiax r0, {d15}( ;@ Deprecated|)
-0+228 <[^>]*> ec800b05 fstmiax r0, {d0-d1}( ;@ Deprecated|)
-0+22c <[^>]*> ec800b07 fstmiax r0, {d0-d2}( ;@ Deprecated|)
-0+230 <[^>]*> ec800b21 fstmiax r0, {d0-d15}( ;@ Deprecated|)
-0+234 <[^>]*> ec801b1f fstmiax r0, {d1-d15}( ;@ Deprecated|)
-0+238 <[^>]*> ec802b1d fstmiax r0, {d2-d15}( ;@ Deprecated|)
-0+23c <[^>]*> ec80eb05 fstmiax r0, {d14-d15}( ;@ Deprecated|)
-0+240 <[^>]*> ec810b03 fstmiax r1, {d0}( ;@ Deprecated|)
-0+244 <[^>]*> ec8e0b03 fstmiax lr, {d0}( ;@ Deprecated|)
+0+21c <[^>]*> ec801b03 fstmiax r0, {d1}( @ Deprecated|)
+0+220 <[^>]*> ec802b03 fstmiax r0, {d2}( @ Deprecated|)
+0+224 <[^>]*> ec80fb03 fstmiax r0, {d15}( @ Deprecated|)
+0+228 <[^>]*> ec800b05 fstmiax r0, {d0-d1}( @ Deprecated|)
+0+22c <[^>]*> ec800b07 fstmiax r0, {d0-d2}( @ Deprecated|)
+0+230 <[^>]*> ec800b21 fstmiax r0, {d0-d15}( @ Deprecated|)
+0+234 <[^>]*> ec801b1f fstmiax r0, {d1-d15}( @ Deprecated|)
+0+238 <[^>]*> ec802b1d fstmiax r0, {d2-d15}( @ Deprecated|)
+0+23c <[^>]*> ec80eb05 fstmiax r0, {d14-d15}( @ Deprecated|)
+0+240 <[^>]*> ec810b03 fstmiax r1, {d0}( @ Deprecated|)
+0+244 <[^>]*> ec8e0b03 fstmiax lr, {d0}( @ Deprecated|)
0+248 <[^>]*> eeb50a40 (vcmp\.f32 s0, #0.0|fcmpzs s0)
0+24c <[^>]*> eef50a40 (vcmp\.f32 s1, #0.0|fcmpzs s1)
0+250 <[^>]*> eeb51a40 (vcmp\.f32 s2, #0.0|fcmpzs s2)
@@ -211,24 +211,24 @@ Disassembly of section .text:
0+324 <[^>]*> 0cf42a01 (vldmiaeq|fldmiaseq) r4!, {s5}
0+328 <[^>]*> 0d352a01 (vldmdbeq|fldmdbseq) r5!, {s4}
0+32c <[^>]*> 0d761a01 (vldmdbeq|fldmdbseq) r6!, {s3}
-0+330 <[^>]*> 0c971b03 fldmiaxeq r7, {d1}( ;@ Deprecated|)
-0+334 <[^>]*> 0c982b03 fldmiaxeq r8, {d2}( ;@ Deprecated|)
-0+338 <[^>]*> 0cb93b03 fldmiaxeq r9!, {d3}( ;@ Deprecated|)
-0+33c <[^>]*> 0cba4b03 fldmiaxeq sl!, {d4}( ;@ Deprecated|)
-0+340 <[^>]*> 0d3b5b03 fldmdbxeq fp!, {d5}( ;@ Deprecated|)
-0+344 <[^>]*> 0d3c6b03 fldmdbxeq ip!, {d6}( ;@ Deprecated|)
+0+330 <[^>]*> 0c971b03 fldmiaxeq r7, {d1}( @ Deprecated|)
+0+334 <[^>]*> 0c982b03 fldmiaxeq r8, {d2}( @ Deprecated|)
+0+338 <[^>]*> 0cb93b03 fldmiaxeq r9!, {d3}( @ Deprecated|)
+0+33c <[^>]*> 0cba4b03 fldmiaxeq sl!, {d4}( @ Deprecated|)
+0+340 <[^>]*> 0d3b5b03 fldmdbxeq fp!, {d5}( @ Deprecated|)
+0+344 <[^>]*> 0d3c6b03 fldmdbxeq ip!, {d6}( @ Deprecated|)
0+348 <[^>]*> 0c8d1a01 (vstmiaeq|fstmiaseq) sp, {s2}
0+34c <[^>]*> 0cce0a01 (vstmiaeq|fstmiaseq) lr, {s1}
0+350 <[^>]*> 0ce1fa01 (vstmiaeq|fstmiaseq) r1!, {s31}
0+354 <[^>]*> 0ca2fa01 (vstmiaeq|fstmiaseq) r2!, {s30}
0+358 <[^>]*> 0d63ea01 (vstmdbeq|fstmdbseq) r3!, {s29}
0+35c <[^>]*> 0d24ea01 (vstmdbeq|fstmdbseq) r4!, {s28}
-0+360 <[^>]*> 0c857b03 fstmiaxeq r5, {d7}( ;@ Deprecated|)
-0+364 <[^>]*> 0c868b03 fstmiaxeq r6, {d8}( ;@ Deprecated|)
-0+368 <[^>]*> 0ca79b03 fstmiaxeq r7!, {d9}( ;@ Deprecated|)
-0+36c <[^>]*> 0ca8ab03 fstmiaxeq r8!, {d10}( ;@ Deprecated|)
-0+370 <[^>]*> 0d29bb03 fstmdbxeq r9!, {d11}( ;@ Deprecated|)
-0+374 <[^>]*> 0d2acb03 fstmdbxeq sl!, {d12}( ;@ Deprecated|)
+0+360 <[^>]*> 0c857b03 fstmiaxeq r5, {d7}( @ Deprecated|)
+0+364 <[^>]*> 0c868b03 fstmiaxeq r6, {d8}( @ Deprecated|)
+0+368 <[^>]*> 0ca79b03 fstmiaxeq r7!, {d9}( @ Deprecated|)
+0+36c <[^>]*> 0ca8ab03 fstmiaxeq r8!, {d10}( @ Deprecated|)
+0+370 <[^>]*> 0d29bb03 fstmdbxeq r9!, {d11}( @ Deprecated|)
+0+374 <[^>]*> 0d2acb03 fstmdbxeq sl!, {d12}( @ Deprecated|)
0+378 <[^>]*> 0ef8dac3 (vcvteq\.f32\.s32|fsitoseq) s27, s6
0+37c <[^>]*> 0efdca62 (vcvtreq\.s32\.f32|ftosiseq) s25, s5
0+380 <[^>]*> 0efdbac2 (vcvteq\.s32\.f32|ftosizseq) s23, s4
@@ -290,6 +290,6 @@ Disassembly of section .text:
0+460 <[^>]*> eef97a10 vmrs r7, fpinst @ Impl def
0+464 <[^>]*> eefa8a10 vmrs r8, fpinst2 @ Impl def
0+468 <[^>]*> eeff9a10 vmrs r9, (c15|<impl def 0xf>|fpcxt_s)
-0+46c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
-0+470 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
-0+474 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
+0+46c <[^>]*> e1a00000 nop @ \(mov r0, r0\)
+0+470 <[^>]*> e1a00000 nop @ \(mov r0, r0\)
+0+474 <[^>]*> e1a00000 nop @ \(mov r0, r0\)
diff --git a/gas/testsuite/gas/arm/vfp1xD_t2.d b/gas/testsuite/gas/arm/vfp1xD_t2.d
index 248185d4486..4ac2550681c 100644
--- a/gas/testsuite/gas/arm/vfp1xD_t2.d
+++ b/gas/testsuite/gas/arm/vfp1xD_t2.d
@@ -33,24 +33,24 @@ Disassembly of section .text:
0+05c <[^>]*> ecb0 0a01 (vldmia|fldmias) r0!, {s0}
0+060 <[^>]*> ed30 0a01 (vldmdb|fldmdbs) r0!, {s0}
0+064 <[^>]*> ed30 0a01 (vldmdb|fldmdbs) r0!, {s0}
-0+068 <[^>]*> ec90 0b03 fldmiax r0, {d0}( ;@ Deprecated|)
-0+06c <[^>]*> ec90 0b03 fldmiax r0, {d0}( ;@ Deprecated|)
-0+070 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( ;@ Deprecated|)
-0+074 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( ;@ Deprecated|)
-0+078 <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( ;@ Deprecated|)
-0+07c <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( ;@ Deprecated|)
+0+068 <[^>]*> ec90 0b03 fldmiax r0, {d0}( @ Deprecated|)
+0+06c <[^>]*> ec90 0b03 fldmiax r0, {d0}( @ Deprecated|)
+0+070 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( @ Deprecated|)
+0+074 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( @ Deprecated|)
+0+078 <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( @ Deprecated|)
+0+07c <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( @ Deprecated|)
0+080 <[^>]*> ec80 0a01 (vstmia|fstmias) r0, {s0}
0+084 <[^>]*> ec80 0a01 (vstmia|fstmias) r0, {s0}
0+088 <[^>]*> eca0 0a01 (vstmia|fstmias) r0!, {s0}
0+08c <[^>]*> eca0 0a01 (vstmia|fstmias) r0!, {s0}
0+090 <[^>]*> ed20 0a01 (vstmdb|fstmdbs) r0!, {s0}
0+094 <[^>]*> ed20 0a01 (vstmdb|fstmdbs) r0!, {s0}
-0+098 <[^>]*> ec80 0b03 fstmiax r0, {d0}( ;@ Deprecated|)
-0+09c <[^>]*> ec80 0b03 fstmiax r0, {d0}( ;@ Deprecated|)
-0+0a0 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( ;@ Deprecated|)
-0+0a4 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( ;@ Deprecated|)
-0+0a8 <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( ;@ Deprecated|)
-0+0ac <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( ;@ Deprecated|)
+0+098 <[^>]*> ec80 0b03 fstmiax r0, {d0}( @ Deprecated|)
+0+09c <[^>]*> ec80 0b03 fstmiax r0, {d0}( @ Deprecated|)
+0+0a0 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( @ Deprecated|)
+0+0a4 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( @ Deprecated|)
+0+0a8 <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( @ Deprecated|)
+0+0ac <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( @ Deprecated|)
0+0b0 <[^>]*> eeb8 0ac0 (vcvt\.f32\.s32|fsitos) s0, s0
0+0b4 <[^>]*> eeb8 0a40 (vcvt\.f32\.u32|fuitos) s0, s0
0+0b8 <[^>]*> eebd 0a40 (vcvtr\.s32\.f32|ftosis) s0, s0
@@ -142,17 +142,17 @@ Disassembly of section .text:
0+210 <[^>]*> ec90 fa02 (vldmia|fldmias) r0, {s30-s31}
0+214 <[^>]*> ec91 0a01 (vldmia|fldmias) r1, {s0}
0+218 <[^>]*> ec9e 0a01 (vldmia|fldmias) lr, {s0}
-0+21c <[^>]*> ec80 1b03 fstmiax r0, {d1}( ;@ Deprecated|)
-0+220 <[^>]*> ec80 2b03 fstmiax r0, {d2}( ;@ Deprecated|)
-0+224 <[^>]*> ec80 fb03 fstmiax r0, {d15}( ;@ Deprecated|)
-0+228 <[^>]*> ec80 0b05 fstmiax r0, {d0-d1}( ;@ Deprecated|)
-0+22c <[^>]*> ec80 0b07 fstmiax r0, {d0-d2}( ;@ Deprecated|)
-0+230 <[^>]*> ec80 0b21 fstmiax r0, {d0-d15}( ;@ Deprecated|)
-0+234 <[^>]*> ec80 1b1f fstmiax r0, {d1-d15}( ;@ Deprecated|)
-0+238 <[^>]*> ec80 2b1d fstmiax r0, {d2-d15}( ;@ Deprecated|)
-0+23c <[^>]*> ec80 eb05 fstmiax r0, {d14-d15}( ;@ Deprecated|)
-0+240 <[^>]*> ec81 0b03 fstmiax r1, {d0}( ;@ Deprecated|)
-0+244 <[^>]*> ec8e 0b03 fstmiax lr, {d0}( ;@ Deprecated|)
+0+21c <[^>]*> ec80 1b03 fstmiax r0, {d1}( @ Deprecated|)
+0+220 <[^>]*> ec80 2b03 fstmiax r0, {d2}( @ Deprecated|)
+0+224 <[^>]*> ec80 fb03 fstmiax r0, {d15}( @ Deprecated|)
+0+228 <[^>]*> ec80 0b05 fstmiax r0, {d0-d1}( @ Deprecated|)
+0+22c <[^>]*> ec80 0b07 fstmiax r0, {d0-d2}( @ Deprecated|)
+0+230 <[^>]*> ec80 0b21 fstmiax r0, {d0-d15}( @ Deprecated|)
+0+234 <[^>]*> ec80 1b1f fstmiax r0, {d1-d15}( @ Deprecated|)
+0+238 <[^>]*> ec80 2b1d fstmiax r0, {d2-d15}( @ Deprecated|)
+0+23c <[^>]*> ec80 eb05 fstmiax r0, {d14-d15}( @ Deprecated|)
+0+240 <[^>]*> ec81 0b03 fstmiax r1, {d0}( @ Deprecated|)
+0+244 <[^>]*> ec8e 0b03 fstmiax lr, {d0}( @ Deprecated|)
0+248 <[^>]*> eeb5 0a40 (vcmp\.f32 s0, #0.0|fcmpzs s0)
0+24c <[^>]*> eef5 0a40 (vcmp\.f32 s1, #0.0|fcmpzs s1)
0+250 <[^>]*> eeb5 1a40 (vcmp\.f32 s2, #0.0|fcmpzs s2)
@@ -218,13 +218,13 @@ Disassembly of section .text:
0+334 <[^>]*> bf01 itttt eq
0+336 <[^>]*> ed35 2a01 (vldmdbeq|fldmdbseq) r5!, {s4}
0+33a <[^>]*> ed76 1a01 (vldmdbeq|fldmdbseq) r6!, {s3}
-0+33e <[^>]*> ec97 1b03 fldmiaxeq r7, {d1}( ;@ Deprecated|)
-0+342 <[^>]*> ec98 2b03 fldmiaxeq r8, {d2}( ;@ Deprecated|)
+0+33e <[^>]*> ec97 1b03 fldmiaxeq r7, {d1}( @ Deprecated|)
+0+342 <[^>]*> ec98 2b03 fldmiaxeq r8, {d2}( @ Deprecated|)
0+346 <[^>]*> bf01 itttt eq
-0+348 <[^>]*> ecb9 3b03 fldmiaxeq r9!, {d3}( ;@ Deprecated|)
-0+34c <[^>]*> ecba 4b03 fldmiaxeq sl!, {d4}( ;@ Deprecated|)
-0+350 <[^>]*> ed3b 5b03 fldmdbxeq fp!, {d5}( ;@ Deprecated|)
-0+354 <[^>]*> ed3c 6b03 fldmdbxeq ip!, {d6}( ;@ Deprecated|)
+0+348 <[^>]*> ecb9 3b03 fldmiaxeq r9!, {d3}( @ Deprecated|)
+0+34c <[^>]*> ecba 4b03 fldmiaxeq sl!, {d4}( @ Deprecated|)
+0+350 <[^>]*> ed3b 5b03 fldmdbxeq fp!, {d5}( @ Deprecated|)
+0+354 <[^>]*> ed3c 6b03 fldmdbxeq ip!, {d6}( @ Deprecated|)
0+358 <[^>]*> bf01 itttt eq
0+35a <[^>]*> ec8d 1a01 (vstmiaeq|fstmiaseq) sp, {s2}
0+35e <[^>]*> ecce 0a01 (vstmiaeq|fstmiaseq) lr, {s1}
@@ -233,13 +233,13 @@ Disassembly of section .text:
0+36a <[^>]*> bf01 itttt eq
0+36c <[^>]*> ed63 ea01 (vstmdbeq|fstmdbseq) r3!, {s29}
0+370 <[^>]*> ed24 ea01 (vstmdbeq|fstmdbseq) r4!, {s28}
-0+374 <[^>]*> ec85 7b03 fstmiaxeq r5, {d7}( ;@ Deprecated|)
-0+378 <[^>]*> ec86 8b03 fstmiaxeq r6, {d8}( ;@ Deprecated|)
+0+374 <[^>]*> ec85 7b03 fstmiaxeq r5, {d7}( @ Deprecated|)
+0+378 <[^>]*> ec86 8b03 fstmiaxeq r6, {d8}( @ Deprecated|)
0+37c <[^>]*> bf01 itttt eq
-0+37e <[^>]*> eca7 9b03 fstmiaxeq r7!, {d9}( ;@ Deprecated|)
-0+382 <[^>]*> eca8 ab03 fstmiaxeq r8!, {d10}( ;@ Deprecated|)
-0+386 <[^>]*> ed29 bb03 fstmdbxeq r9!, {d11}( ;@ Deprecated|)
-0+38a <[^>]*> ed2a cb03 fstmdbxeq sl!, {d12}( ;@ Deprecated|)
+0+37e <[^>]*> eca7 9b03 fstmiaxeq r7!, {d9}( @ Deprecated|)
+0+382 <[^>]*> eca8 ab03 fstmiaxeq r8!, {d10}( @ Deprecated|)
+0+386 <[^>]*> ed29 bb03 fstmdbxeq r9!, {d11}( @ Deprecated|)
+0+38a <[^>]*> ed2a cb03 fstmdbxeq sl!, {d12}( @ Deprecated|)
0+38e <[^>]*> bf01 itttt eq
0+390 <[^>]*> eef8 dac3 (vcvteq\.f32\.s32|fsitoseq) s27, s6
0+394 <[^>]*> eefd ca62 (vcvtreq\.s32\.f32|ftosiseq) s25, s5
diff --git a/gas/testsuite/gas/arm/vfpv3-32drs.d b/gas/testsuite/gas/arm/vfpv3-32drs.d
index 1f67f0299ef..656a9f07325 100644
--- a/gas/testsuite/gas/arm/vfpv3-32drs.d
+++ b/gas/testsuite/gas/arm/vfpv3-32drs.d
@@ -23,9 +23,9 @@ Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> edca5b01 vstr d21, \[sl, #4\]
0[0-9a-f]+ <[^>]+> ecba5b04 vldmia sl!, {d5-d6}
0[0-9a-f]+ <[^>]+> ecfa2b06 vldmia sl!, {d18-d20}
-0[0-9a-f]+ <[^>]+> ecba5b05 fldmiax sl!, {d5-d6}( ;@ Deprecated|)
-0[0-9a-f]+ <[^>]+> ecfa2b07 fldmiax sl!, {d18-d20}( ;@ Deprecated|)
-0[0-9a-f]+ <[^>]+> ed7a2b05 fldmdbx sl!, {d18-d19}( ;@ Deprecated|)
+0[0-9a-f]+ <[^>]+> ecba5b05 fldmiax sl!, {d5-d6}( @ Deprecated|)
+0[0-9a-f]+ <[^>]+> ecfa2b07 fldmiax sl!, {d18-d20}( @ Deprecated|)
+0[0-9a-f]+ <[^>]+> ed7a2b05 fldmdbx sl!, {d18-d19}( @ Deprecated|)
0[0-9a-f]+ <[^>]+> ecc94b0a vstmia r9, {d20-d24}
0[0-9a-f]+ <[^>]+> eeb03bc5 (vabs\.f64|fabsd) d3, d5
0[0-9a-f]+ <[^>]+> eeb0cbe2 (vabs\.f64|fabsd) d12, d18
diff --git a/gas/testsuite/gas/arm/vldconst.d b/gas/testsuite/gas/arm/vldconst.d
index 74483cc0d72..25a89a14dec 100644
--- a/gas/testsuite/gas/arm/vldconst.d
+++ b/gas/testsuite/gas/arm/vldconst.d
@@ -6,82 +6,82 @@
.*: +file format .*arm.*
Disassembly of section .text:
-00000000 <foo> ed9f0a0e vldr s0, \[pc, #56\] ; 00000040 <foo\+0x40>
-00000004 <foo\+0x4> ed9f7a0d vldr s14, \[pc, #52\] ; 00000040 <foo\+0x40>
-00000008 <foo\+0x8> ed9fea0c vldr s28, \[pc, #48\] ; 00000040 <foo\+0x40>
-0000000c <foo\+0xc> eddffa0b vldr s31, \[pc, #44\] ; 00000040 <foo\+0x40>
-00000010 <foo\+0x10> ed9f0a0b vldr s0, \[pc, #44\] ; 00000044 <foo\+0x44>
-00000014 <foo\+0x14> ed9f7a0a vldr s14, \[pc, #40\] ; 00000044 <foo\+0x44>
-00000018 <foo\+0x18> ed9fea09 vldr s28, \[pc, #36\] ; 00000044 <foo\+0x44>
-0000001c <foo\+0x1c> eddffa08 vldr s31, \[pc, #32\] ; 00000044 <foo\+0x44>
-00000020 <foo\+0x20> ed9f0a08 vldr s0, \[pc, #32\] ; 00000048 <foo\+0x48>
-00000024 <foo\+0x24> ed9f7a07 vldr s14, \[pc, #28\] ; 00000048 <foo\+0x48>
-00000028 <foo\+0x28> ed9fea06 vldr s28, \[pc, #24\] ; 00000048 <foo\+0x48>
-0000002c <foo\+0x2c> eddffa05 vldr s31, \[pc, #20\] ; 00000048 <foo\+0x48>
-00000030 <foo\+0x30> ed9f0a05 vldr s0, \[pc, #20\] ; 0000004c <foo\+0x4c>
-00000034 <foo\+0x34> ed9f7a04 vldr s14, \[pc, #16\] ; 0000004c <foo\+0x4c>
-00000038 <foo\+0x38> ed9fea03 vldr s28, \[pc, #12\] ; 0000004c <foo\+0x4c>
-0000003c <foo\+0x3c> eddffa02 vldr s31, \[pc, #8\] ; 0000004c <foo\+0x4c>
+00000000 <foo> ed9f0a0e vldr s0, \[pc, #56\] @ 00000040 <foo\+0x40>
+00000004 <foo\+0x4> ed9f7a0d vldr s14, \[pc, #52\] @ 00000040 <foo\+0x40>
+00000008 <foo\+0x8> ed9fea0c vldr s28, \[pc, #48\] @ 00000040 <foo\+0x40>
+0000000c <foo\+0xc> eddffa0b vldr s31, \[pc, #44\] @ 00000040 <foo\+0x40>
+00000010 <foo\+0x10> ed9f0a0b vldr s0, \[pc, #44\] @ 00000044 <foo\+0x44>
+00000014 <foo\+0x14> ed9f7a0a vldr s14, \[pc, #40\] @ 00000044 <foo\+0x44>
+00000018 <foo\+0x18> ed9fea09 vldr s28, \[pc, #36\] @ 00000044 <foo\+0x44>
+0000001c <foo\+0x1c> eddffa08 vldr s31, \[pc, #32\] @ 00000044 <foo\+0x44>
+00000020 <foo\+0x20> ed9f0a08 vldr s0, \[pc, #32\] @ 00000048 <foo\+0x48>
+00000024 <foo\+0x24> ed9f7a07 vldr s14, \[pc, #28\] @ 00000048 <foo\+0x48>
+00000028 <foo\+0x28> ed9fea06 vldr s28, \[pc, #24\] @ 00000048 <foo\+0x48>
+0000002c <foo\+0x2c> eddffa05 vldr s31, \[pc, #20\] @ 00000048 <foo\+0x48>
+00000030 <foo\+0x30> ed9f0a05 vldr s0, \[pc, #20\] @ 0000004c <foo\+0x4c>
+00000034 <foo\+0x34> ed9f7a04 vldr s14, \[pc, #16\] @ 0000004c <foo\+0x4c>
+00000038 <foo\+0x38> ed9fea03 vldr s28, \[pc, #12\] @ 0000004c <foo\+0x4c>
+0000003c <foo\+0x3c> eddffa02 vldr s31, \[pc, #8\] @ 0000004c <foo\+0x4c>
00000040 <foo\+0x40> 00000000 .word 0x00000000
00000044 <foo\+0x44> ff000000 .word 0xff000000
00000048 <foo\+0x48> ffffffff .word 0xffffffff
0000004c <foo\+0x4c> 0fff0000 .word 0x0fff0000
-00000050 <foo\+0x50> ed9f0a0e vldr s0, \[pc, #56\] ; 00000090 <foo\+0x90>
-00000054 <foo\+0x54> ed9f7a0d vldr s14, \[pc, #52\] ; 00000090 <foo\+0x90>
-00000058 <foo\+0x58> ed9fea0c vldr s28, \[pc, #48\] ; 00000090 <foo\+0x90>
-0000005c <foo\+0x5c> eddffa0b vldr s31, \[pc, #44\] ; 00000090 <foo\+0x90>
-00000060 <foo\+0x60> ed9f0a0b vldr s0, \[pc, #44\] ; 00000094 <foo\+0x94>
-00000064 <foo\+0x64> ed9f7a0a vldr s14, \[pc, #40\] ; 00000094 <foo\+0x94>
-00000068 <foo\+0x68> ed9fea09 vldr s28, \[pc, #36\] ; 00000094 <foo\+0x94>
-0000006c <foo\+0x6c> eddffa08 vldr s31, \[pc, #32\] ; 00000094 <foo\+0x94>
-00000070 <foo\+0x70> ed9f0a08 vldr s0, \[pc, #32\] ; 00000098 <foo\+0x98>
-00000074 <foo\+0x74> ed9f7a07 vldr s14, \[pc, #28\] ; 00000098 <foo\+0x98>
-00000078 <foo\+0x78> ed9fea06 vldr s28, \[pc, #24\] ; 00000098 <foo\+0x98>
-0000007c <foo\+0x7c> eddffa05 vldr s31, \[pc, #20\] ; 00000098 <foo\+0x98>
-00000080 <foo\+0x80> ed9f0a05 vldr s0, \[pc, #20\] ; 0000009c <foo\+0x9c>
-00000084 <foo\+0x84> ed9f7a04 vldr s14, \[pc, #16\] ; 0000009c <foo\+0x9c>
-00000088 <foo\+0x88> ed9fea03 vldr s28, \[pc, #12\] ; 0000009c <foo\+0x9c>
-0000008c <foo\+0x8c> eddffa02 vldr s31, \[pc, #8\] ; 0000009c <foo\+0x9c>
+00000050 <foo\+0x50> ed9f0a0e vldr s0, \[pc, #56\] @ 00000090 <foo\+0x90>
+00000054 <foo\+0x54> ed9f7a0d vldr s14, \[pc, #52\] @ 00000090 <foo\+0x90>
+00000058 <foo\+0x58> ed9fea0c vldr s28, \[pc, #48\] @ 00000090 <foo\+0x90>
+0000005c <foo\+0x5c> eddffa0b vldr s31, \[pc, #44\] @ 00000090 <foo\+0x90>
+00000060 <foo\+0x60> ed9f0a0b vldr s0, \[pc, #44\] @ 00000094 <foo\+0x94>
+00000064 <foo\+0x64> ed9f7a0a vldr s14, \[pc, #40\] @ 00000094 <foo\+0x94>
+00000068 <foo\+0x68> ed9fea09 vldr s28, \[pc, #36\] @ 00000094 <foo\+0x94>
+0000006c <foo\+0x6c> eddffa08 vldr s31, \[pc, #32\] @ 00000094 <foo\+0x94>
+00000070 <foo\+0x70> ed9f0a08 vldr s0, \[pc, #32\] @ 00000098 <foo\+0x98>
+00000074 <foo\+0x74> ed9f7a07 vldr s14, \[pc, #28\] @ 00000098 <foo\+0x98>
+00000078 <foo\+0x78> ed9fea06 vldr s28, \[pc, #24\] @ 00000098 <foo\+0x98>
+0000007c <foo\+0x7c> eddffa05 vldr s31, \[pc, #20\] @ 00000098 <foo\+0x98>
+00000080 <foo\+0x80> ed9f0a05 vldr s0, \[pc, #20\] @ 0000009c <foo\+0x9c>
+00000084 <foo\+0x84> ed9f7a04 vldr s14, \[pc, #16\] @ 0000009c <foo\+0x9c>
+00000088 <foo\+0x88> ed9fea03 vldr s28, \[pc, #12\] @ 0000009c <foo\+0x9c>
+0000008c <foo\+0x8c> eddffa02 vldr s31, \[pc, #8\] @ 0000009c <foo\+0x9c>
00000090 <foo\+0x90> 00000000 .word 0x00000000
00000094 <foo\+0x94> 00ff0000 .word 0x00ff0000
00000098 <foo\+0x98> ff00ffff .word 0xff00ffff
0000009c <foo\+0x9c> 00fff000 .word 0x00fff000
-000000a0 <foo\+0xa0> 0d9f0a0e vldreq s0, \[pc, #56\] ; 000000e0 <foo\+0xe0>
-000000a4 <foo\+0xa4> 0d9f7a0d vldreq s14, \[pc, #52\] ; 000000e0 <foo\+0xe0>
-000000a8 <foo\+0xa8> 0d9fea0c vldreq s28, \[pc, #48\] ; 000000e0 <foo\+0xe0>
-000000ac <foo\+0xac> 0ddffa0b vldreq s31, \[pc, #44\] ; 000000e0 <foo\+0xe0>
-000000b0 <foo\+0xb0> 0d9f0a0b vldreq s0, \[pc, #44\] ; 000000e4 <foo\+0xe4>
-000000b4 <foo\+0xb4> 0d9f7a0a vldreq s14, \[pc, #40\] ; 000000e4 <foo\+0xe4>
-000000b8 <foo\+0xb8> 0d9fea09 vldreq s28, \[pc, #36\] ; 000000e4 <foo\+0xe4>
-000000bc <foo\+0xbc> 0ddffa08 vldreq s31, \[pc, #32\] ; 000000e4 <foo\+0xe4>
-000000c0 <foo\+0xc0> 0d9f0a08 vldreq s0, \[pc, #32\] ; 000000e8 <foo\+0xe8>
-000000c4 <foo\+0xc4> 0d9f7a07 vldreq s14, \[pc, #28\] ; 000000e8 <foo\+0xe8>
-000000c8 <foo\+0xc8> 0d9fea06 vldreq s28, \[pc, #24\] ; 000000e8 <foo\+0xe8>
-000000cc <foo\+0xcc> 0ddffa05 vldreq s31, \[pc, #20\] ; 000000e8 <foo\+0xe8>
-000000d0 <foo\+0xd0> 0d9f0a05 vldreq s0, \[pc, #20\] ; 000000ec <foo\+0xec>
-000000d4 <foo\+0xd4> 0d9f7a04 vldreq s14, \[pc, #16\] ; 000000ec <foo\+0xec>
-000000d8 <foo\+0xd8> 0d9fea03 vldreq s28, \[pc, #12\] ; 000000ec <foo\+0xec>
-000000dc <foo\+0xdc> 0ddffa02 vldreq s31, \[pc, #8\] ; 000000ec <foo\+0xec>
+000000a0 <foo\+0xa0> 0d9f0a0e vldreq s0, \[pc, #56\] @ 000000e0 <foo\+0xe0>
+000000a4 <foo\+0xa4> 0d9f7a0d vldreq s14, \[pc, #52\] @ 000000e0 <foo\+0xe0>
+000000a8 <foo\+0xa8> 0d9fea0c vldreq s28, \[pc, #48\] @ 000000e0 <foo\+0xe0>
+000000ac <foo\+0xac> 0ddffa0b vldreq s31, \[pc, #44\] @ 000000e0 <foo\+0xe0>
+000000b0 <foo\+0xb0> 0d9f0a0b vldreq s0, \[pc, #44\] @ 000000e4 <foo\+0xe4>
+000000b4 <foo\+0xb4> 0d9f7a0a vldreq s14, \[pc, #40\] @ 000000e4 <foo\+0xe4>
+000000b8 <foo\+0xb8> 0d9fea09 vldreq s28, \[pc, #36\] @ 000000e4 <foo\+0xe4>
+000000bc <foo\+0xbc> 0ddffa08 vldreq s31, \[pc, #32\] @ 000000e4 <foo\+0xe4>
+000000c0 <foo\+0xc0> 0d9f0a08 vldreq s0, \[pc, #32\] @ 000000e8 <foo\+0xe8>
+000000c4 <foo\+0xc4> 0d9f7a07 vldreq s14, \[pc, #28\] @ 000000e8 <foo\+0xe8>
+000000c8 <foo\+0xc8> 0d9fea06 vldreq s28, \[pc, #24\] @ 000000e8 <foo\+0xe8>
+000000cc <foo\+0xcc> 0ddffa05 vldreq s31, \[pc, #20\] @ 000000e8 <foo\+0xe8>
+000000d0 <foo\+0xd0> 0d9f0a05 vldreq s0, \[pc, #20\] @ 000000ec <foo\+0xec>
+000000d4 <foo\+0xd4> 0d9f7a04 vldreq s14, \[pc, #16\] @ 000000ec <foo\+0xec>
+000000d8 <foo\+0xd8> 0d9fea03 vldreq s28, \[pc, #12\] @ 000000ec <foo\+0xec>
+000000dc <foo\+0xdc> 0ddffa02 vldreq s31, \[pc, #8\] @ 000000ec <foo\+0xec>
000000e0 <foo\+0xe0> 00000000 .word 0x00000000
000000e4 <foo\+0xe4> 0000ff00 .word 0x0000ff00
000000e8 <foo\+0xe8> ffff00ff .word 0xffff00ff
000000ec <foo\+0xec> 000fff00 .word 0x000fff00
-000000f0 <foo\+0xf0> 4d9f0a0e vldrmi s0, \[pc, #56\] ; 00000130 <foo\+0x130>
-000000f4 <foo\+0xf4> 4d9f7a0d vldrmi s14, \[pc, #52\] ; 00000130 <foo\+0x130>
-000000f8 <foo\+0xf8> 4d9fea0c vldrmi s28, \[pc, #48\] ; 00000130 <foo\+0x130>
-000000fc <foo\+0xfc> 4ddffa0b vldrmi s31, \[pc, #44\] ; 00000130 <foo\+0x130>
-00000100 <foo\+0x100> 4d9f0a0b vldrmi s0, \[pc, #44\] ; 00000134 <foo\+0x134>
-00000104 <foo\+0x104> 4d9f7a0a vldrmi s14, \[pc, #40\] ; 00000134 <foo\+0x134>
-00000108 <foo\+0x108> 4d9fea09 vldrmi s28, \[pc, #36\] ; 00000134 <foo\+0x134>
-0000010c <foo\+0x10c> 4ddffa08 vldrmi s31, \[pc, #32\] ; 00000134 <foo\+0x134>
-00000110 <foo\+0x110> 4d9f0a08 vldrmi s0, \[pc, #32\] ; 00000138 <foo\+0x138>
-00000114 <foo\+0x114> 4d9f7a07 vldrmi s14, \[pc, #28\] ; 00000138 <foo\+0x138>
-00000118 <foo\+0x118> 4d9fea06 vldrmi s28, \[pc, #24\] ; 00000138 <foo\+0x138>
-0000011c <foo\+0x11c> 4ddffa05 vldrmi s31, \[pc, #20\] ; 00000138 <foo\+0x138>
-00000120 <foo\+0x120> 4d9f0a05 vldrmi s0, \[pc, #20\] ; 0000013c <foo\+0x13c>
-00000124 <foo\+0x124> 4d9f7a04 vldrmi s14, \[pc, #16\] ; 0000013c <foo\+0x13c>
-00000128 <foo\+0x128> 4d9fea03 vldrmi s28, \[pc, #12\] ; 0000013c <foo\+0x13c>
-0000012c <foo\+0x12c> 4ddffa02 vldrmi s31, \[pc, #8\] ; 0000013c <foo\+0x13c>
+000000f0 <foo\+0xf0> 4d9f0a0e vldrmi s0, \[pc, #56\] @ 00000130 <foo\+0x130>
+000000f4 <foo\+0xf4> 4d9f7a0d vldrmi s14, \[pc, #52\] @ 00000130 <foo\+0x130>
+000000f8 <foo\+0xf8> 4d9fea0c vldrmi s28, \[pc, #48\] @ 00000130 <foo\+0x130>
+000000fc <foo\+0xfc> 4ddffa0b vldrmi s31, \[pc, #44\] @ 00000130 <foo\+0x130>
+00000100 <foo\+0x100> 4d9f0a0b vldrmi s0, \[pc, #44\] @ 00000134 <foo\+0x134>
+00000104 <foo\+0x104> 4d9f7a0a vldrmi s14, \[pc, #40\] @ 00000134 <foo\+0x134>
+00000108 <foo\+0x108> 4d9fea09 vldrmi s28, \[pc, #36\] @ 00000134 <foo\+0x134>
+0000010c <foo\+0x10c> 4ddffa08 vldrmi s31, \[pc, #32\] @ 00000134 <foo\+0x134>
+00000110 <foo\+0x110> 4d9f0a08 vldrmi s0, \[pc, #32\] @ 00000138 <foo\+0x138>
+00000114 <foo\+0x114> 4d9f7a07 vldrmi s14, \[pc, #28\] @ 00000138 <foo\+0x138>
+00000118 <foo\+0x118> 4d9fea06 vldrmi s28, \[pc, #24\] @ 00000138 <foo\+0x138>
+0000011c <foo\+0x11c> 4ddffa05 vldrmi s31, \[pc, #20\] @ 00000138 <foo\+0x138>
+00000120 <foo\+0x120> 4d9f0a05 vldrmi s0, \[pc, #20\] @ 0000013c <foo\+0x13c>
+00000124 <foo\+0x124> 4d9f7a04 vldrmi s14, \[pc, #16\] @ 0000013c <foo\+0x13c>
+00000128 <foo\+0x128> 4d9fea03 vldrmi s28, \[pc, #12\] @ 0000013c <foo\+0x13c>
+0000012c <foo\+0x12c> 4ddffa02 vldrmi s31, \[pc, #8\] @ 0000013c <foo\+0x13c>
00000130 <foo\+0x130> 00000000 .word 0x00000000
00000134 <foo\+0x134> 000000ff .word 0x000000ff
00000138 <foo\+0x138> ffffff00 .word 0xffffff00
@@ -90,18 +90,18 @@ Disassembly of section .text:
00000144 <foo\+0x144> f280ee30 vmov.i64 d14, #0x0000000000000000
00000148 <foo\+0x148> f2c0ce30 vmov.i64 d28, #0x0000000000000000
0000014c <foo\+0x14c> f2c0fe30 vmov.i64 d31, #0x0000000000000000
-00000150 <foo\+0x150> ed9f0b0a vldr d0, \[pc, #40\] ; 00000180 <foo\+0x180>
-00000154 <foo\+0x154> ed9feb09 vldr d14, \[pc, #36\] ; 00000180 <foo\+0x180>
-00000158 <foo\+0x158> eddfcb08 vldr d28, \[pc, #32\] ; 00000180 <foo\+0x180>
-0000015c <foo\+0x15c> eddffb07 vldr d31, \[pc, #28\] ; 00000180 <foo\+0x180>
+00000150 <foo\+0x150> ed9f0b0a vldr d0, \[pc, #40\] @ 00000180 <foo\+0x180>
+00000154 <foo\+0x154> ed9feb09 vldr d14, \[pc, #36\] @ 00000180 <foo\+0x180>
+00000158 <foo\+0x158> eddfcb08 vldr d28, \[pc, #32\] @ 00000180 <foo\+0x180>
+0000015c <foo\+0x15c> eddffb07 vldr d31, \[pc, #28\] @ 00000180 <foo\+0x180>
00000160 <foo\+0x160> f3870e3f vmov.i64 d0, #0xffffffffffffffff
00000164 <foo\+0x164> f387ee3f vmov.i64 d14, #0xffffffffffffffff
00000168 <foo\+0x168> f3c7ce3f vmov.i64 d28, #0xffffffffffffffff
0000016c <foo\+0x16c> f3c7fe3f vmov.i64 d31, #0xffffffffffffffff
-00000170 <foo\+0x170> ed9f0b04 vldr d0, \[pc, #16\] ; 00000188 <foo\+0x188>
-00000174 <foo\+0x174> ed9feb03 vldr d14, \[pc, #12\] ; 00000188 <foo\+0x188>
-00000178 <foo\+0x178> eddfcb02 vldr d28, \[pc, #8\] ; 00000188 <foo\+0x188>
-0000017c <foo\+0x17c> eddffb01 vldr d31, \[pc, #4\] ; 00000188 <foo\+0x188>
+00000170 <foo\+0x170> ed9f0b04 vldr d0, \[pc, #16\] @ 00000188 <foo\+0x188>
+00000174 <foo\+0x174> ed9feb03 vldr d14, \[pc, #12\] @ 00000188 <foo\+0x188>
+00000178 <foo\+0x178> eddfcb02 vldr d28, \[pc, #8\] @ 00000188 <foo\+0x188>
+0000017c <foo\+0x17c> eddffb01 vldr d31, \[pc, #4\] @ 00000188 <foo\+0x188>
00000180 <foo\+0x180> ca000000 .word 0xca000000
00000184 <foo\+0x184> 00000000 .word 0x00000000
00000188 <foo\+0x188> 0fff0000 .word 0x0fff0000
@@ -118,10 +118,10 @@ Disassembly of section .text:
000001b4 <foo\+0x1b4> f280ee39 vmov.i64 d14, #0x00000000ff0000ff
000001b8 <foo\+0x1b8> f2c0ce39 vmov.i64 d28, #0x00000000ff0000ff
000001bc <foo\+0x1bc> f2c0fe39 vmov.i64 d31, #0x00000000ff0000ff
-000001c0 <foo\+0x1c0> ed9f0b02 vldr d0, \[pc, #8\] ; 000001d0 <foo\+0x1d0>
-000001c4 <foo\+0x1c4> ed9feb01 vldr d14, \[pc, #4\] ; 000001d0 <foo\+0x1d0>
-000001c8 <foo\+0x1c8> eddfcb00 vldr d28, \[pc\] ; 000001d0 <foo\+0x1d0>
-000001cc <foo\+0x1cc> ed5ffb01 vldr d31, \[pc, #-4\] ; 000001d0 <foo\+0x1d0>
+000001c0 <foo\+0x1c0> ed9f0b02 vldr d0, \[pc, #8\] @ 000001d0 <foo\+0x1d0>
+000001c4 <foo\+0x1c4> ed9feb01 vldr d14, \[pc, #4\] @ 000001d0 <foo\+0x1d0>
+000001c8 <foo\+0x1c8> eddfcb00 vldr d28, \[pc\] @ 000001d0 <foo\+0x1d0>
+000001cc <foo\+0x1cc> ed5ffb01 vldr d31, \[pc, #-4\] @ 000001d0 <foo\+0x1d0>
000001d0 <foo\+0x1d0> 00fff000 .word 0x00fff000
000001d4 <foo\+0x1d4> 00000000 .word 0x00000000
000001d8 <foo\+0x1d8> f2800e30 vmov.i64 d0, #0x0000000000000000
@@ -136,10 +136,10 @@ Disassembly of section .text:
000001fc <foo\+0x1fc> f280ee3d vmov.i64 d14, #0x00000000ffff00ff
00000200 <foo\+0x200> f2c0ce3d vmov.i64 d28, #0x00000000ffff00ff
00000204 <foo\+0x204> f2c0fe3d vmov.i64 d31, #0x00000000ffff00ff
-00000208 <foo\+0x208> 0d9f0b02 vldreq d0, \[pc, #8\] ; 00000218 <foo\+0x218>
-0000020c <foo\+0x20c> 0d9feb01 vldreq d14, \[pc, #4\] ; 00000218 <foo\+0x218>
-00000210 <foo\+0x210> 0ddfcb00 vldreq d28, \[pc\] ; 00000218 <foo\+0x218>
-00000214 <foo\+0x214> 0d5ffb01 vldreq d31, \[pc, #-4\] ; 00000218 <foo\+0x218>
+00000208 <foo\+0x208> 0d9f0b02 vldreq d0, \[pc, #8\] @ 00000218 <foo\+0x218>
+0000020c <foo\+0x20c> 0d9feb01 vldreq d14, \[pc, #4\] @ 00000218 <foo\+0x218>
+00000210 <foo\+0x210> 0ddfcb00 vldreq d28, \[pc\] @ 00000218 <foo\+0x218>
+00000214 <foo\+0x214> 0d5ffb01 vldreq d31, \[pc, #-4\] @ 00000218 <foo\+0x218>
00000218 <foo\+0x218> 000fff00 .word 0x000fff00
0000021c <foo\+0x21c> 00000000 .word 0x00000000
00000220 <foo\+0x220> f2800e30 vmov.i64 d0, #0x0000000000000000
@@ -170,28 +170,28 @@ Disassembly of section .text:
00000284 <foo\+0x284> f387ee3f vmov.i64 d14, #0xffffffffffffffff
00000288 <foo\+0x288> f3c7ce3f vmov.i64 d28, #0xffffffffffffffff
0000028c <foo\+0x28c> f3c7fe3f vmov.i64 d31, #0xffffffffffffffff
-00000290 <foo\+0x290> ed9f0b02 vldr d0, \[pc, #8\] ; 000002a0 <foo\+0x2a0>
-00000294 <foo\+0x294> ed9feb01 vldr d14, \[pc, #4\] ; 000002a0 <foo\+0x2a0>
-00000298 <foo\+0x298> eddfcb00 vldr d28, \[pc\] ; 000002a0 <foo\+0x2a0>
-0000029c <foo\+0x29c> ed5ffb01 vldr d31, \[pc, #-4\] ; 000002a0 <foo\+0x2a0>
+00000290 <foo\+0x290> ed9f0b02 vldr d0, \[pc, #8\] @ 000002a0 <foo\+0x2a0>
+00000294 <foo\+0x294> ed9feb01 vldr d14, \[pc, #4\] @ 000002a0 <foo\+0x2a0>
+00000298 <foo\+0x298> eddfcb00 vldr d28, \[pc\] @ 000002a0 <foo\+0x2a0>
+0000029c <foo\+0x29c> ed5ffb01 vldr d31, \[pc, #-4\] @ 000002a0 <foo\+0x2a0>
000002a0 <foo\+0x2a0> 00000000 .word 0x00000000
000002a4 <foo\+0x2a4> 0fff0000 .word 0x0fff0000
000002a8 <foo\+0x2a8> f2800e30 vmov.i64 d0, #0x0000000000000000
000002ac <foo\+0x2ac> f280ee30 vmov.i64 d14, #0x0000000000000000
000002b0 <foo\+0x2b0> f2c0ce30 vmov.i64 d28, #0x0000000000000000
000002b4 <foo\+0x2b4> f2c0fe30 vmov.i64 d31, #0x0000000000000000
-000002b8 <foo\+0x2b8> ed9f0b0a vldr d0, \[pc, #40\] ; 000002e8 <foo\+0x2e8>
-000002bc <foo\+0x2bc> ed9feb09 vldr d14, \[pc, #36\] ; 000002e8 <foo\+0x2e8>
-000002c0 <foo\+0x2c0> eddfcb08 vldr d28, \[pc, #32\] ; 000002e8 <foo\+0x2e8>
-000002c4 <foo\+0x2c4> eddffb07 vldr d31, \[pc, #28\] ; 000002e8 <foo\+0x2e8>
-000002c8 <foo\+0x2c8> ed9f0b08 vldr d0, \[pc, #32\] ; 000002f0 <foo\+0x2f0>
-000002cc <foo\+0x2cc> ed9feb07 vldr d14, \[pc, #28\] ; 000002f0 <foo\+0x2f0>
-000002d0 <foo\+0x2d0> eddfcb06 vldr d28, \[pc, #24\] ; 000002f0 <foo\+0x2f0>
-000002d4 <foo\+0x2d4> eddffb05 vldr d31, \[pc, #20\] ; 000002f0 <foo\+0x2f0>
-000002d8 <foo\+0x2d8> ed9f0b06 vldr d0, \[pc, #24\] ; 000002f8 <foo\+0x2f8>
-000002dc <foo\+0x2dc> ed9feb05 vldr d14, \[pc, #20\] ; 000002f8 <foo\+0x2f8>
-000002e0 <foo\+0x2e0> eddfcb04 vldr d28, \[pc, #16\] ; 000002f8 <foo\+0x2f8>
-000002e4 <foo\+0x2e4> eddffb03 vldr d31, \[pc, #12\] ; 000002f8 <foo\+0x2f8>
+000002b8 <foo\+0x2b8> ed9f0b0a vldr d0, \[pc, #40\] @ 000002e8 <foo\+0x2e8>
+000002bc <foo\+0x2bc> ed9feb09 vldr d14, \[pc, #36\] @ 000002e8 <foo\+0x2e8>
+000002c0 <foo\+0x2c0> eddfcb08 vldr d28, \[pc, #32\] @ 000002e8 <foo\+0x2e8>
+000002c4 <foo\+0x2c4> eddffb07 vldr d31, \[pc, #28\] @ 000002e8 <foo\+0x2e8>
+000002c8 <foo\+0x2c8> ed9f0b08 vldr d0, \[pc, #32\] @ 000002f0 <foo\+0x2f0>
+000002cc <foo\+0x2cc> ed9feb07 vldr d14, \[pc, #28\] @ 000002f0 <foo\+0x2f0>
+000002d0 <foo\+0x2d0> eddfcb06 vldr d28, \[pc, #24\] @ 000002f0 <foo\+0x2f0>
+000002d4 <foo\+0x2d4> eddffb05 vldr d31, \[pc, #20\] @ 000002f0 <foo\+0x2f0>
+000002d8 <foo\+0x2d8> ed9f0b06 vldr d0, \[pc, #24\] @ 000002f8 <foo\+0x2f8>
+000002dc <foo\+0x2dc> ed9feb05 vldr d14, \[pc, #20\] @ 000002f8 <foo\+0x2f8>
+000002e0 <foo\+0x2e0> eddfcb04 vldr d28, \[pc, #16\] @ 000002f8 <foo\+0x2f8>
+000002e4 <foo\+0x2e4> eddffb03 vldr d31, \[pc, #12\] @ 000002f8 <foo\+0x2f8>
000002e8 <foo\+0x2e8> 00000000 .word 0x00000000
000002ec <foo\+0x2ec> 000ff000 .word 0x000ff000
000002f0 <foo\+0x2f0> f0000000 .word 0xf0000000
@@ -210,10 +210,10 @@ Disassembly of section .text:
00000324 <foo\+0x324> f385ee30 vmov.i64 d14, #0xffff00ff00000000
00000328 <foo\+0x328> f3c5ce30 vmov.i64 d28, #0xffff00ff00000000
0000032c <foo\+0x32c> f3c5fe30 vmov.i64 d31, #0xffff00ff00000000
-00000330 <foo\+0x330> 0d9f0b02 vldreq d0, \[pc, #8\] ; 00000340 <foo\+0x340>
-00000334 <foo\+0x334> 0d9feb01 vldreq d14, \[pc, #4\] ; 00000340 <foo\+0x340>
-00000338 <foo\+0x338> 0ddfcb00 vldreq d28, \[pc\] ; 00000340 <foo\+0x340>
-0000033c <foo\+0x33c> 0d5ffb01 vldreq d31, \[pc, #-4\] ; 00000340 <foo\+0x340>
+00000330 <foo\+0x330> 0d9f0b02 vldreq d0, \[pc, #8\] @ 00000340 <foo\+0x340>
+00000334 <foo\+0x334> 0d9feb01 vldreq d14, \[pc, #4\] @ 00000340 <foo\+0x340>
+00000338 <foo\+0x338> 0ddfcb00 vldreq d28, \[pc\] @ 00000340 <foo\+0x340>
+0000033c <foo\+0x33c> 0d5ffb01 vldreq d31, \[pc, #-4\] @ 00000340 <foo\+0x340>
00000340 <foo\+0x340> 00000000 .word 0x00000000
00000344 <foo\+0x344> 000fff00 .word 0x000fff00
00000348 <foo\+0x348> f2800e30 vmov.i64 d0, #0x0000000000000000
@@ -228,36 +228,36 @@ Disassembly of section .text:
0000036c <foo\+0x36c> f386ee30 vmov.i64 d14, #0xffffff0000000000
00000370 <foo\+0x370> f3c6ce30 vmov.i64 d28, #0xffffff0000000000
00000374 <foo\+0x374> f3c6fe30 vmov.i64 d31, #0xffffff0000000000
-00000378 <foo\+0x378> 4d9f0b02 vldrmi d0, \[pc, #8\] ; 00000388 <foo\+0x388>
-0000037c <foo\+0x37c> 4d9feb01 vldrmi d14, \[pc, #4\] ; 00000388 <foo\+0x388>
-00000380 <foo\+0x380> 4ddfcb00 vldrmi d28, \[pc\] ; 00000388 <foo\+0x388>
-00000384 <foo\+0x384> 4d5ffb01 vldrmi d31, \[pc, #-4\] ; 00000388 <foo\+0x388>
+00000378 <foo\+0x378> 4d9f0b02 vldrmi d0, \[pc, #8\] @ 00000388 <foo\+0x388>
+0000037c <foo\+0x37c> 4d9feb01 vldrmi d14, \[pc, #4\] @ 00000388 <foo\+0x388>
+00000380 <foo\+0x380> 4ddfcb00 vldrmi d28, \[pc\] @ 00000388 <foo\+0x388>
+00000384 <foo\+0x384> 4d5ffb01 vldrmi d31, \[pc, #-4\] @ 00000388 <foo\+0x388>
00000388 <foo\+0x388> 00000000 .word 0x00000000
0000038c <foo\+0x38c> 0000fff0 .word 0x0000fff0
-00000390 <foo\+0x390> ed9f1b00 vldr d1, \[pc\] ; 00000398 <foo\+0x398>
+00000390 <foo\+0x390> ed9f1b00 vldr d1, \[pc\] @ 00000398 <foo\+0x398>
\.\.\.
0000039c <foo\+0x39c> 0000fff0 .word 0x0000fff0
000003a0 <foo\+0x3a0> e2810000 add r0, r1, #0
-000003a4 <foo\+0x3a4> ed1f1b01 vldr d1, \[pc, #-4\] ; 000003a8 <foo\+0x3a8>
+000003a4 <foo\+0x3a4> ed1f1b01 vldr d1, \[pc, #-4\] @ 000003a8 <foo\+0x3a8>
000003a8 <foo\+0x3a8> 00000000 .word 0x00000000
000003ac <foo\+0x3ac> 0000fff0 .word 0x0000fff0
-000003b0 <foo\+0x3b0> ed9f1b10 vldr d1, \[pc, #64\] ; 000003f8 <foo\+0x3f8>
-000003b4 <foo\+0x3b4> ed9f1a11 vldr s2, \[pc, #68\] ; 00000400 <foo\+0x400>
-000003b8 <foo\+0x3b8> ed9f3b12 vldr d3, \[pc, #72\] ; 00000408 <foo\+0x408>
-000003bc <foo\+0x3bc> ed9f2a10 vldr s4, \[pc, #64\] ; 00000404 <foo\+0x404>
-000003c0 <foo\+0x3c0> ed9f5b10 vldr d5, \[pc, #64\] ; 00000408 <foo\+0x408>
-000003c4 <foo\+0x3c4> ed9f6b11 vldr d6, \[pc, #68\] ; 00000410 <foo\+0x410>
-000003c8 <foo\+0x3c8> ed9f7b12 vldr d7, \[pc, #72\] ; 00000418 <foo\+0x418>
-000003cc <foo\+0x3cc> ed9f4a13 vldr s8, \[pc, #76\] ; 00000420 <foo\+0x420>
-000003d0 <foo\+0x3d0> ed9f9b14 vldr d9, \[pc, #80\] ; 00000428 <foo\+0x428>
-000003d4 <foo\+0x3d4> ed9f5a12 vldr s10, \[pc, #72\] ; 00000424 <foo\+0x424>
-000003d8 <foo\+0x3d8> ed9fbb14 vldr d11, \[pc, #80\] ; 00000430 <foo\+0x430>
-000003dc <foo\+0x3dc> ed9f6a15 vldr s12, \[pc, #84\] ; 00000438 <foo\+0x438>
-000003e0 <foo\+0x3e0> eddf6a15 vldr s13, \[pc, #84\] ; 0000043c <foo\+0x43c>
-000003e4 <foo\+0x3e4> ed9f7a06 vldr s14, \[pc, #24\] ; 00000404 <foo\+0x404>
-000003e8 <foo\+0x3e8> eddf7a03 vldr s15, \[pc, #12\] ; 000003fc <foo\+0x3fc>
-000003ec <foo\+0x3ec> eddf0b11 vldr d16, \[pc, #68\] ; 00000438 <foo\+0x438>
-000003f0 <foo\+0x3f0> eddf1b12 vldr d17, \[pc, #72\] ; 00000440 <foo\+0x440>
+000003b0 <foo\+0x3b0> ed9f1b10 vldr d1, \[pc, #64\] @ 000003f8 <foo\+0x3f8>
+000003b4 <foo\+0x3b4> ed9f1a11 vldr s2, \[pc, #68\] @ 00000400 <foo\+0x400>
+000003b8 <foo\+0x3b8> ed9f3b12 vldr d3, \[pc, #72\] @ 00000408 <foo\+0x408>
+000003bc <foo\+0x3bc> ed9f2a10 vldr s4, \[pc, #64\] @ 00000404 <foo\+0x404>
+000003c0 <foo\+0x3c0> ed9f5b10 vldr d5, \[pc, #64\] @ 00000408 <foo\+0x408>
+000003c4 <foo\+0x3c4> ed9f6b11 vldr d6, \[pc, #68\] @ 00000410 <foo\+0x410>
+000003c8 <foo\+0x3c8> ed9f7b12 vldr d7, \[pc, #72\] @ 00000418 <foo\+0x418>
+000003cc <foo\+0x3cc> ed9f4a13 vldr s8, \[pc, #76\] @ 00000420 <foo\+0x420>
+000003d0 <foo\+0x3d0> ed9f9b14 vldr d9, \[pc, #80\] @ 00000428 <foo\+0x428>
+000003d4 <foo\+0x3d4> ed9f5a12 vldr s10, \[pc, #72\] @ 00000424 <foo\+0x424>
+000003d8 <foo\+0x3d8> ed9fbb14 vldr d11, \[pc, #80\] @ 00000430 <foo\+0x430>
+000003dc <foo\+0x3dc> ed9f6a15 vldr s12, \[pc, #84\] @ 00000438 <foo\+0x438>
+000003e0 <foo\+0x3e0> eddf6a15 vldr s13, \[pc, #84\] @ 0000043c <foo\+0x43c>
+000003e4 <foo\+0x3e4> ed9f7a06 vldr s14, \[pc, #24\] @ 00000404 <foo\+0x404>
+000003e8 <foo\+0x3e8> eddf7a03 vldr s15, \[pc, #12\] @ 000003fc <foo\+0x3fc>
+000003ec <foo\+0x3ec> eddf0b11 vldr d16, \[pc, #68\] @ 00000438 <foo\+0x438>
+000003f0 <foo\+0x3f0> eddf1b12 vldr d17, \[pc, #72\] @ 00000440 <foo\+0x440>
\.\.\.
000003fc <foo\+0x3fc> 0000fff0 .word 0x0000fff0
00000400 <foo\+0x400> ff000000 .word 0xff000000
diff --git a/gas/testsuite/gas/arm/vldconst_be.d b/gas/testsuite/gas/arm/vldconst_be.d
index 63f3c2faa2d..f0eb4387081 100644
--- a/gas/testsuite/gas/arm/vldconst_be.d
+++ b/gas/testsuite/gas/arm/vldconst_be.d
@@ -7,82 +7,82 @@
.*: +file format .*arm.*
Disassembly of section .text:
-00000000 <foo> ed9f0a0e vldr s0, \[pc, #56\] ; 00000040 <foo\+0x40>
-00000004 <foo\+0x4> ed9f7a0d vldr s14, \[pc, #52\] ; 00000040 <foo\+0x40>
-00000008 <foo\+0x8> ed9fea0c vldr s28, \[pc, #48\] ; 00000040 <foo\+0x40>
-0000000c <foo\+0xc> eddffa0b vldr s31, \[pc, #44\] ; 00000040 <foo\+0x40>
-00000010 <foo\+0x10> ed9f0a0b vldr s0, \[pc, #44\] ; 00000044 <foo\+0x44>
-00000014 <foo\+0x14> ed9f7a0a vldr s14, \[pc, #40\] ; 00000044 <foo\+0x44>
-00000018 <foo\+0x18> ed9fea09 vldr s28, \[pc, #36\] ; 00000044 <foo\+0x44>
-0000001c <foo\+0x1c> eddffa08 vldr s31, \[pc, #32\] ; 00000044 <foo\+0x44>
-00000020 <foo\+0x20> ed9f0a08 vldr s0, \[pc, #32\] ; 00000048 <foo\+0x48>
-00000024 <foo\+0x24> ed9f7a07 vldr s14, \[pc, #28\] ; 00000048 <foo\+0x48>
-00000028 <foo\+0x28> ed9fea06 vldr s28, \[pc, #24\] ; 00000048 <foo\+0x48>
-0000002c <foo\+0x2c> eddffa05 vldr s31, \[pc, #20\] ; 00000048 <foo\+0x48>
-00000030 <foo\+0x30> ed9f0a05 vldr s0, \[pc, #20\] ; 0000004c <foo\+0x4c>
-00000034 <foo\+0x34> ed9f7a04 vldr s14, \[pc, #16\] ; 0000004c <foo\+0x4c>
-00000038 <foo\+0x38> ed9fea03 vldr s28, \[pc, #12\] ; 0000004c <foo\+0x4c>
-0000003c <foo\+0x3c> eddffa02 vldr s31, \[pc, #8\] ; 0000004c <foo\+0x4c>
+00000000 <foo> ed9f0a0e vldr s0, \[pc, #56\] @ 00000040 <foo\+0x40>
+00000004 <foo\+0x4> ed9f7a0d vldr s14, \[pc, #52\] @ 00000040 <foo\+0x40>
+00000008 <foo\+0x8> ed9fea0c vldr s28, \[pc, #48\] @ 00000040 <foo\+0x40>
+0000000c <foo\+0xc> eddffa0b vldr s31, \[pc, #44\] @ 00000040 <foo\+0x40>
+00000010 <foo\+0x10> ed9f0a0b vldr s0, \[pc, #44\] @ 00000044 <foo\+0x44>
+00000014 <foo\+0x14> ed9f7a0a vldr s14, \[pc, #40\] @ 00000044 <foo\+0x44>
+00000018 <foo\+0x18> ed9fea09 vldr s28, \[pc, #36\] @ 00000044 <foo\+0x44>
+0000001c <foo\+0x1c> eddffa08 vldr s31, \[pc, #32\] @ 00000044 <foo\+0x44>
+00000020 <foo\+0x20> ed9f0a08 vldr s0, \[pc, #32\] @ 00000048 <foo\+0x48>
+00000024 <foo\+0x24> ed9f7a07 vldr s14, \[pc, #28\] @ 00000048 <foo\+0x48>
+00000028 <foo\+0x28> ed9fea06 vldr s28, \[pc, #24\] @ 00000048 <foo\+0x48>
+0000002c <foo\+0x2c> eddffa05 vldr s31, \[pc, #20\] @ 00000048 <foo\+0x48>
+00000030 <foo\+0x30> ed9f0a05 vldr s0, \[pc, #20\] @ 0000004c <foo\+0x4c>
+00000034 <foo\+0x34> ed9f7a04 vldr s14, \[pc, #16\] @ 0000004c <foo\+0x4c>
+00000038 <foo\+0x38> ed9fea03 vldr s28, \[pc, #12\] @ 0000004c <foo\+0x4c>
+0000003c <foo\+0x3c> eddffa02 vldr s31, \[pc, #8\] @ 0000004c <foo\+0x4c>
00000040 <foo\+0x40> 00000000 .word 0x00000000
00000044 <foo\+0x44> ff000000 .word 0xff000000
00000048 <foo\+0x48> ffffffff .word 0xffffffff
0000004c <foo\+0x4c> 0fff0000 .word 0x0fff0000
-00000050 <foo\+0x50> ed9f0a0e vldr s0, \[pc, #56\] ; 00000090 <foo\+0x90>
-00000054 <foo\+0x54> ed9f7a0d vldr s14, \[pc, #52\] ; 00000090 <foo\+0x90>
-00000058 <foo\+0x58> ed9fea0c vldr s28, \[pc, #48\] ; 00000090 <foo\+0x90>
-0000005c <foo\+0x5c> eddffa0b vldr s31, \[pc, #44\] ; 00000090 <foo\+0x90>
-00000060 <foo\+0x60> ed9f0a0b vldr s0, \[pc, #44\] ; 00000094 <foo\+0x94>
-00000064 <foo\+0x64> ed9f7a0a vldr s14, \[pc, #40\] ; 00000094 <foo\+0x94>
-00000068 <foo\+0x68> ed9fea09 vldr s28, \[pc, #36\] ; 00000094 <foo\+0x94>
-0000006c <foo\+0x6c> eddffa08 vldr s31, \[pc, #32\] ; 00000094 <foo\+0x94>
-00000070 <foo\+0x70> ed9f0a08 vldr s0, \[pc, #32\] ; 00000098 <foo\+0x98>
-00000074 <foo\+0x74> ed9f7a07 vldr s14, \[pc, #28\] ; 00000098 <foo\+0x98>
-00000078 <foo\+0x78> ed9fea06 vldr s28, \[pc, #24\] ; 00000098 <foo\+0x98>
-0000007c <foo\+0x7c> eddffa05 vldr s31, \[pc, #20\] ; 00000098 <foo\+0x98>
-00000080 <foo\+0x80> ed9f0a05 vldr s0, \[pc, #20\] ; 0000009c <foo\+0x9c>
-00000084 <foo\+0x84> ed9f7a04 vldr s14, \[pc, #16\] ; 0000009c <foo\+0x9c>
-00000088 <foo\+0x88> ed9fea03 vldr s28, \[pc, #12\] ; 0000009c <foo\+0x9c>
-0000008c <foo\+0x8c> eddffa02 vldr s31, \[pc, #8\] ; 0000009c <foo\+0x9c>
+00000050 <foo\+0x50> ed9f0a0e vldr s0, \[pc, #56\] @ 00000090 <foo\+0x90>
+00000054 <foo\+0x54> ed9f7a0d vldr s14, \[pc, #52\] @ 00000090 <foo\+0x90>
+00000058 <foo\+0x58> ed9fea0c vldr s28, \[pc, #48\] @ 00000090 <foo\+0x90>
+0000005c <foo\+0x5c> eddffa0b vldr s31, \[pc, #44\] @ 00000090 <foo\+0x90>
+00000060 <foo\+0x60> ed9f0a0b vldr s0, \[pc, #44\] @ 00000094 <foo\+0x94>
+00000064 <foo\+0x64> ed9f7a0a vldr s14, \[pc, #40\] @ 00000094 <foo\+0x94>
+00000068 <foo\+0x68> ed9fea09 vldr s28, \[pc, #36\] @ 00000094 <foo\+0x94>
+0000006c <foo\+0x6c> eddffa08 vldr s31, \[pc, #32\] @ 00000094 <foo\+0x94>
+00000070 <foo\+0x70> ed9f0a08 vldr s0, \[pc, #32\] @ 00000098 <foo\+0x98>
+00000074 <foo\+0x74> ed9f7a07 vldr s14, \[pc, #28\] @ 00000098 <foo\+0x98>
+00000078 <foo\+0x78> ed9fea06 vldr s28, \[pc, #24\] @ 00000098 <foo\+0x98>
+0000007c <foo\+0x7c> eddffa05 vldr s31, \[pc, #20\] @ 00000098 <foo\+0x98>
+00000080 <foo\+0x80> ed9f0a05 vldr s0, \[pc, #20\] @ 0000009c <foo\+0x9c>
+00000084 <foo\+0x84> ed9f7a04 vldr s14, \[pc, #16\] @ 0000009c <foo\+0x9c>
+00000088 <foo\+0x88> ed9fea03 vldr s28, \[pc, #12\] @ 0000009c <foo\+0x9c>
+0000008c <foo\+0x8c> eddffa02 vldr s31, \[pc, #8\] @ 0000009c <foo\+0x9c>
00000090 <foo\+0x90> 00000000 .word 0x00000000
00000094 <foo\+0x94> 00ff0000 .word 0x00ff0000
00000098 <foo\+0x98> ff00ffff .word 0xff00ffff
0000009c <foo\+0x9c> 00fff000 .word 0x00fff000
-000000a0 <foo\+0xa0> 0d9f0a0e vldreq s0, \[pc, #56\] ; 000000e0 <foo\+0xe0>
-000000a4 <foo\+0xa4> 0d9f7a0d vldreq s14, \[pc, #52\] ; 000000e0 <foo\+0xe0>
-000000a8 <foo\+0xa8> 0d9fea0c vldreq s28, \[pc, #48\] ; 000000e0 <foo\+0xe0>
-000000ac <foo\+0xac> 0ddffa0b vldreq s31, \[pc, #44\] ; 000000e0 <foo\+0xe0>
-000000b0 <foo\+0xb0> 0d9f0a0b vldreq s0, \[pc, #44\] ; 000000e4 <foo\+0xe4>
-000000b4 <foo\+0xb4> 0d9f7a0a vldreq s14, \[pc, #40\] ; 000000e4 <foo\+0xe4>
-000000b8 <foo\+0xb8> 0d9fea09 vldreq s28, \[pc, #36\] ; 000000e4 <foo\+0xe4>
-000000bc <foo\+0xbc> 0ddffa08 vldreq s31, \[pc, #32\] ; 000000e4 <foo\+0xe4>
-000000c0 <foo\+0xc0> 0d9f0a08 vldreq s0, \[pc, #32\] ; 000000e8 <foo\+0xe8>
-000000c4 <foo\+0xc4> 0d9f7a07 vldreq s14, \[pc, #28\] ; 000000e8 <foo\+0xe8>
-000000c8 <foo\+0xc8> 0d9fea06 vldreq s28, \[pc, #24\] ; 000000e8 <foo\+0xe8>
-000000cc <foo\+0xcc> 0ddffa05 vldreq s31, \[pc, #20\] ; 000000e8 <foo\+0xe8>
-000000d0 <foo\+0xd0> 0d9f0a05 vldreq s0, \[pc, #20\] ; 000000ec <foo\+0xec>
-000000d4 <foo\+0xd4> 0d9f7a04 vldreq s14, \[pc, #16\] ; 000000ec <foo\+0xec>
-000000d8 <foo\+0xd8> 0d9fea03 vldreq s28, \[pc, #12\] ; 000000ec <foo\+0xec>
-000000dc <foo\+0xdc> 0ddffa02 vldreq s31, \[pc, #8\] ; 000000ec <foo\+0xec>
+000000a0 <foo\+0xa0> 0d9f0a0e vldreq s0, \[pc, #56\] @ 000000e0 <foo\+0xe0>
+000000a4 <foo\+0xa4> 0d9f7a0d vldreq s14, \[pc, #52\] @ 000000e0 <foo\+0xe0>
+000000a8 <foo\+0xa8> 0d9fea0c vldreq s28, \[pc, #48\] @ 000000e0 <foo\+0xe0>
+000000ac <foo\+0xac> 0ddffa0b vldreq s31, \[pc, #44\] @ 000000e0 <foo\+0xe0>
+000000b0 <foo\+0xb0> 0d9f0a0b vldreq s0, \[pc, #44\] @ 000000e4 <foo\+0xe4>
+000000b4 <foo\+0xb4> 0d9f7a0a vldreq s14, \[pc, #40\] @ 000000e4 <foo\+0xe4>
+000000b8 <foo\+0xb8> 0d9fea09 vldreq s28, \[pc, #36\] @ 000000e4 <foo\+0xe4>
+000000bc <foo\+0xbc> 0ddffa08 vldreq s31, \[pc, #32\] @ 000000e4 <foo\+0xe4>
+000000c0 <foo\+0xc0> 0d9f0a08 vldreq s0, \[pc, #32\] @ 000000e8 <foo\+0xe8>
+000000c4 <foo\+0xc4> 0d9f7a07 vldreq s14, \[pc, #28\] @ 000000e8 <foo\+0xe8>
+000000c8 <foo\+0xc8> 0d9fea06 vldreq s28, \[pc, #24\] @ 000000e8 <foo\+0xe8>
+000000cc <foo\+0xcc> 0ddffa05 vldreq s31, \[pc, #20\] @ 000000e8 <foo\+0xe8>
+000000d0 <foo\+0xd0> 0d9f0a05 vldreq s0, \[pc, #20\] @ 000000ec <foo\+0xec>
+000000d4 <foo\+0xd4> 0d9f7a04 vldreq s14, \[pc, #16\] @ 000000ec <foo\+0xec>
+000000d8 <foo\+0xd8> 0d9fea03 vldreq s28, \[pc, #12\] @ 000000ec <foo\+0xec>
+000000dc <foo\+0xdc> 0ddffa02 vldreq s31, \[pc, #8\] @ 000000ec <foo\+0xec>
000000e0 <foo\+0xe0> 00000000 .word 0x00000000
000000e4 <foo\+0xe4> 0000ff00 .word 0x0000ff00
000000e8 <foo\+0xe8> ffff00ff .word 0xffff00ff
000000ec <foo\+0xec> 000fff00 .word 0x000fff00
-000000f0 <foo\+0xf0> 4d9f0a0e vldrmi s0, \[pc, #56\] ; 00000130 <foo\+0x130>
-000000f4 <foo\+0xf4> 4d9f7a0d vldrmi s14, \[pc, #52\] ; 00000130 <foo\+0x130>
-000000f8 <foo\+0xf8> 4d9fea0c vldrmi s28, \[pc, #48\] ; 00000130 <foo\+0x130>
-000000fc <foo\+0xfc> 4ddffa0b vldrmi s31, \[pc, #44\] ; 00000130 <foo\+0x130>
-00000100 <foo\+0x100> 4d9f0a0b vldrmi s0, \[pc, #44\] ; 00000134 <foo\+0x134>
-00000104 <foo\+0x104> 4d9f7a0a vldrmi s14, \[pc, #40\] ; 00000134 <foo\+0x134>
-00000108 <foo\+0x108> 4d9fea09 vldrmi s28, \[pc, #36\] ; 00000134 <foo\+0x134>
-0000010c <foo\+0x10c> 4ddffa08 vldrmi s31, \[pc, #32\] ; 00000134 <foo\+0x134>
-00000110 <foo\+0x110> 4d9f0a08 vldrmi s0, \[pc, #32\] ; 00000138 <foo\+0x138>
-00000114 <foo\+0x114> 4d9f7a07 vldrmi s14, \[pc, #28\] ; 00000138 <foo\+0x138>
-00000118 <foo\+0x118> 4d9fea06 vldrmi s28, \[pc, #24\] ; 00000138 <foo\+0x138>
-0000011c <foo\+0x11c> 4ddffa05 vldrmi s31, \[pc, #20\] ; 00000138 <foo\+0x138>
-00000120 <foo\+0x120> 4d9f0a05 vldrmi s0, \[pc, #20\] ; 0000013c <foo\+0x13c>
-00000124 <foo\+0x124> 4d9f7a04 vldrmi s14, \[pc, #16\] ; 0000013c <foo\+0x13c>
-00000128 <foo\+0x128> 4d9fea03 vldrmi s28, \[pc, #12\] ; 0000013c <foo\+0x13c>
-0000012c <foo\+0x12c> 4ddffa02 vldrmi s31, \[pc, #8\] ; 0000013c <foo\+0x13c>
+000000f0 <foo\+0xf0> 4d9f0a0e vldrmi s0, \[pc, #56\] @ 00000130 <foo\+0x130>
+000000f4 <foo\+0xf4> 4d9f7a0d vldrmi s14, \[pc, #52\] @ 00000130 <foo\+0x130>
+000000f8 <foo\+0xf8> 4d9fea0c vldrmi s28, \[pc, #48\] @ 00000130 <foo\+0x130>
+000000fc <foo\+0xfc> 4ddffa0b vldrmi s31, \[pc, #44\] @ 00000130 <foo\+0x130>
+00000100 <foo\+0x100> 4d9f0a0b vldrmi s0, \[pc, #44\] @ 00000134 <foo\+0x134>
+00000104 <foo\+0x104> 4d9f7a0a vldrmi s14, \[pc, #40\] @ 00000134 <foo\+0x134>
+00000108 <foo\+0x108> 4d9fea09 vldrmi s28, \[pc, #36\] @ 00000134 <foo\+0x134>
+0000010c <foo\+0x10c> 4ddffa08 vldrmi s31, \[pc, #32\] @ 00000134 <foo\+0x134>
+00000110 <foo\+0x110> 4d9f0a08 vldrmi s0, \[pc, #32\] @ 00000138 <foo\+0x138>
+00000114 <foo\+0x114> 4d9f7a07 vldrmi s14, \[pc, #28\] @ 00000138 <foo\+0x138>
+00000118 <foo\+0x118> 4d9fea06 vldrmi s28, \[pc, #24\] @ 00000138 <foo\+0x138>
+0000011c <foo\+0x11c> 4ddffa05 vldrmi s31, \[pc, #20\] @ 00000138 <foo\+0x138>
+00000120 <foo\+0x120> 4d9f0a05 vldrmi s0, \[pc, #20\] @ 0000013c <foo\+0x13c>
+00000124 <foo\+0x124> 4d9f7a04 vldrmi s14, \[pc, #16\] @ 0000013c <foo\+0x13c>
+00000128 <foo\+0x128> 4d9fea03 vldrmi s28, \[pc, #12\] @ 0000013c <foo\+0x13c>
+0000012c <foo\+0x12c> 4ddffa02 vldrmi s31, \[pc, #8\] @ 0000013c <foo\+0x13c>
00000130 <foo\+0x130> 00000000 .word 0x00000000
00000134 <foo\+0x134> 000000ff .word 0x000000ff
00000138 <foo\+0x138> ffffff00 .word 0xffffff00
@@ -91,18 +91,18 @@ Disassembly of section .text:
00000144 <foo\+0x144> f280ee30 vmov.i64 d14, #0x0000000000000000
00000148 <foo\+0x148> f2c0ce30 vmov.i64 d28, #0x0000000000000000
0000014c <foo\+0x14c> f2c0fe30 vmov.i64 d31, #0x0000000000000000
-00000150 <foo\+0x150> ed9f0b0a vldr d0, \[pc, #40\] ; 00000180 <foo\+0x180>
-00000154 <foo\+0x154> ed9feb09 vldr d14, \[pc, #36\] ; 00000180 <foo\+0x180>
-00000158 <foo\+0x158> eddfcb08 vldr d28, \[pc, #32\] ; 00000180 <foo\+0x180>
-0000015c <foo\+0x15c> eddffb07 vldr d31, \[pc, #28\] ; 00000180 <foo\+0x180>
+00000150 <foo\+0x150> ed9f0b0a vldr d0, \[pc, #40\] @ 00000180 <foo\+0x180>
+00000154 <foo\+0x154> ed9feb09 vldr d14, \[pc, #36\] @ 00000180 <foo\+0x180>
+00000158 <foo\+0x158> eddfcb08 vldr d28, \[pc, #32\] @ 00000180 <foo\+0x180>
+0000015c <foo\+0x15c> eddffb07 vldr d31, \[pc, #28\] @ 00000180 <foo\+0x180>
00000160 <foo\+0x160> f3870e3f vmov.i64 d0, #0xffffffffffffffff
00000164 <foo\+0x164> f387ee3f vmov.i64 d14, #0xffffffffffffffff
00000168 <foo\+0x168> f3c7ce3f vmov.i64 d28, #0xffffffffffffffff
0000016c <foo\+0x16c> f3c7fe3f vmov.i64 d31, #0xffffffffffffffff
-00000170 <foo\+0x170> ed9f0b04 vldr d0, \[pc, #16\] ; 00000188 <foo\+0x188>
-00000174 <foo\+0x174> ed9feb03 vldr d14, \[pc, #12\] ; 00000188 <foo\+0x188>
-00000178 <foo\+0x178> eddfcb02 vldr d28, \[pc, #8\] ; 00000188 <foo\+0x188>
-0000017c <foo\+0x17c> eddffb01 vldr d31, \[pc, #4\] ; 00000188 <foo\+0x188>
+00000170 <foo\+0x170> ed9f0b04 vldr d0, \[pc, #16\] @ 00000188 <foo\+0x188>
+00000174 <foo\+0x174> ed9feb03 vldr d14, \[pc, #12\] @ 00000188 <foo\+0x188>
+00000178 <foo\+0x178> eddfcb02 vldr d28, \[pc, #8\] @ 00000188 <foo\+0x188>
+0000017c <foo\+0x17c> eddffb01 vldr d31, \[pc, #4\] @ 00000188 <foo\+0x188>
00000180 <foo\+0x180> 00000000 .word 0x00000000
00000184 <foo\+0x184> ca000000 .word 0xca000000
00000188 <foo\+0x188> 00000000 .word 0x00000000
@@ -119,10 +119,10 @@ Disassembly of section .text:
000001b4 <foo\+0x1b4> f280ee39 vmov.i64 d14, #0x00000000ff0000ff
000001b8 <foo\+0x1b8> f2c0ce39 vmov.i64 d28, #0x00000000ff0000ff
000001bc <foo\+0x1bc> f2c0fe39 vmov.i64 d31, #0x00000000ff0000ff
-000001c0 <foo\+0x1c0> ed9f0b02 vldr d0, \[pc, #8\] ; 000001d0 <foo\+0x1d0>
-000001c4 <foo\+0x1c4> ed9feb01 vldr d14, \[pc, #4\] ; 000001d0 <foo\+0x1d0>
-000001c8 <foo\+0x1c8> eddfcb00 vldr d28, \[pc\] ; 000001d0 <foo\+0x1d0>
-000001cc <foo\+0x1cc> ed5ffb01 vldr d31, \[pc, #-4\] ; 000001d0 <foo\+0x1d0>
+000001c0 <foo\+0x1c0> ed9f0b02 vldr d0, \[pc, #8\] @ 000001d0 <foo\+0x1d0>
+000001c4 <foo\+0x1c4> ed9feb01 vldr d14, \[pc, #4\] @ 000001d0 <foo\+0x1d0>
+000001c8 <foo\+0x1c8> eddfcb00 vldr d28, \[pc\] @ 000001d0 <foo\+0x1d0>
+000001cc <foo\+0x1cc> ed5ffb01 vldr d31, \[pc, #-4\] @ 000001d0 <foo\+0x1d0>
000001d0 <foo\+0x1d0> 00000000 .word 0x00000000
000001d4 <foo\+0x1d4> 00fff000 .word 0x00fff000
000001d8 <foo\+0x1d8> f2800e30 vmov.i64 d0, #0x0000000000000000
@@ -137,10 +137,10 @@ Disassembly of section .text:
000001fc <foo\+0x1fc> f280ee3d vmov.i64 d14, #0x00000000ffff00ff
00000200 <foo\+0x200> f2c0ce3d vmov.i64 d28, #0x00000000ffff00ff
00000204 <foo\+0x204> f2c0fe3d vmov.i64 d31, #0x00000000ffff00ff
-00000208 <foo\+0x208> 0d9f0b02 vldreq d0, \[pc, #8\] ; 00000218 <foo\+0x218>
-0000020c <foo\+0x20c> 0d9feb01 vldreq d14, \[pc, #4\] ; 00000218 <foo\+0x218>
-00000210 <foo\+0x210> 0ddfcb00 vldreq d28, \[pc\] ; 00000218 <foo\+0x218>
-00000214 <foo\+0x214> 0d5ffb01 vldreq d31, \[pc, #-4\] ; 00000218 <foo\+0x218>
+00000208 <foo\+0x208> 0d9f0b02 vldreq d0, \[pc, #8\] @ 00000218 <foo\+0x218>
+0000020c <foo\+0x20c> 0d9feb01 vldreq d14, \[pc, #4\] @ 00000218 <foo\+0x218>
+00000210 <foo\+0x210> 0ddfcb00 vldreq d28, \[pc\] @ 00000218 <foo\+0x218>
+00000214 <foo\+0x214> 0d5ffb01 vldreq d31, \[pc, #-4\] @ 00000218 <foo\+0x218>
00000218 <foo\+0x218> 00000000 .word 0x00000000
0000021c <foo\+0x21c> 000fff00 .word 0x000fff00
00000220 <foo\+0x220> f2800e30 vmov.i64 d0, #0x0000000000000000
@@ -171,28 +171,28 @@ Disassembly of section .text:
00000284 <foo\+0x284> f387ee3f vmov.i64 d14, #0xffffffffffffffff
00000288 <foo\+0x288> f3c7ce3f vmov.i64 d28, #0xffffffffffffffff
0000028c <foo\+0x28c> f3c7fe3f vmov.i64 d31, #0xffffffffffffffff
-00000290 <foo\+0x290> ed9f0b02 vldr d0, \[pc, #8\] ; 000002a0 <foo\+0x2a0>
-00000294 <foo\+0x294> ed9feb01 vldr d14, \[pc, #4\] ; 000002a0 <foo\+0x2a0>
-00000298 <foo\+0x298> eddfcb00 vldr d28, \[pc\] ; 000002a0 <foo\+0x2a0>
-0000029c <foo\+0x29c> ed5ffb01 vldr d31, \[pc, #-4\] ; 000002a0 <foo\+0x2a0>
+00000290 <foo\+0x290> ed9f0b02 vldr d0, \[pc, #8\] @ 000002a0 <foo\+0x2a0>
+00000294 <foo\+0x294> ed9feb01 vldr d14, \[pc, #4\] @ 000002a0 <foo\+0x2a0>
+00000298 <foo\+0x298> eddfcb00 vldr d28, \[pc\] @ 000002a0 <foo\+0x2a0>
+0000029c <foo\+0x29c> ed5ffb01 vldr d31, \[pc, #-4\] @ 000002a0 <foo\+0x2a0>
000002a0 <foo\+0x2a0> 0fff0000 .word 0x0fff0000
000002a4 <foo\+0x2a4> 00000000 .word 0x00000000
000002a8 <foo\+0x2a8> f2800e30 vmov.i64 d0, #0x0000000000000000
000002ac <foo\+0x2ac> f280ee30 vmov.i64 d14, #0x0000000000000000
000002b0 <foo\+0x2b0> f2c0ce30 vmov.i64 d28, #0x0000000000000000
000002b4 <foo\+0x2b4> f2c0fe30 vmov.i64 d31, #0x0000000000000000
-000002b8 <foo\+0x2b8> ed9f0b0a vldr d0, \[pc, #40\] ; 000002e8 <foo\+0x2e8>
-000002bc <foo\+0x2bc> ed9feb09 vldr d14, \[pc, #36\] ; 000002e8 <foo\+0x2e8>
-000002c0 <foo\+0x2c0> eddfcb08 vldr d28, \[pc, #32\] ; 000002e8 <foo\+0x2e8>
-000002c4 <foo\+0x2c4> eddffb07 vldr d31, \[pc, #28\] ; 000002e8 <foo\+0x2e8>
-000002c8 <foo\+0x2c8> ed9f0b08 vldr d0, \[pc, #32\] ; 000002f0 <foo\+0x2f0>
-000002cc <foo\+0x2cc> ed9feb07 vldr d14, \[pc, #28\] ; 000002f0 <foo\+0x2f0>
-000002d0 <foo\+0x2d0> eddfcb06 vldr d28, \[pc, #24\] ; 000002f0 <foo\+0x2f0>
-000002d4 <foo\+0x2d4> eddffb05 vldr d31, \[pc, #20\] ; 000002f0 <foo\+0x2f0>
-000002d8 <foo\+0x2d8> ed9f0b06 vldr d0, \[pc, #24\] ; 000002f8 <foo\+0x2f8>
-000002dc <foo\+0x2dc> ed9feb05 vldr d14, \[pc, #20\] ; 000002f8 <foo\+0x2f8>
-000002e0 <foo\+0x2e0> eddfcb04 vldr d28, \[pc, #16\] ; 000002f8 <foo\+0x2f8>
-000002e4 <foo\+0x2e4> eddffb03 vldr d31, \[pc, #12\] ; 000002f8 <foo\+0x2f8>
+000002b8 <foo\+0x2b8> ed9f0b0a vldr d0, \[pc, #40\] @ 000002e8 <foo\+0x2e8>
+000002bc <foo\+0x2bc> ed9feb09 vldr d14, \[pc, #36\] @ 000002e8 <foo\+0x2e8>
+000002c0 <foo\+0x2c0> eddfcb08 vldr d28, \[pc, #32\] @ 000002e8 <foo\+0x2e8>
+000002c4 <foo\+0x2c4> eddffb07 vldr d31, \[pc, #28\] @ 000002e8 <foo\+0x2e8>
+000002c8 <foo\+0x2c8> ed9f0b08 vldr d0, \[pc, #32\] @ 000002f0 <foo\+0x2f0>
+000002cc <foo\+0x2cc> ed9feb07 vldr d14, \[pc, #28\] @ 000002f0 <foo\+0x2f0>
+000002d0 <foo\+0x2d0> eddfcb06 vldr d28, \[pc, #24\] @ 000002f0 <foo\+0x2f0>
+000002d4 <foo\+0x2d4> eddffb05 vldr d31, \[pc, #20\] @ 000002f0 <foo\+0x2f0>
+000002d8 <foo\+0x2d8> ed9f0b06 vldr d0, \[pc, #24\] @ 000002f8 <foo\+0x2f8>
+000002dc <foo\+0x2dc> ed9feb05 vldr d14, \[pc, #20\] @ 000002f8 <foo\+0x2f8>
+000002e0 <foo\+0x2e0> eddfcb04 vldr d28, \[pc, #16\] @ 000002f8 <foo\+0x2f8>
+000002e4 <foo\+0x2e4> eddffb03 vldr d31, \[pc, #12\] @ 000002f8 <foo\+0x2f8>
000002e8 <foo\+0x2e8> 000ff000 .word 0x000ff000
000002ec <foo\+0x2ec> 00000000 .word 0x00000000
000002f0 <foo\+0x2f0> 0ff00fff .word 0x0ff00fff
@@ -211,10 +211,10 @@ Disassembly of section .text:
00000324 <foo\+0x324> f385ee30 vmov.i64 d14, #0xffff00ff00000000
00000328 <foo\+0x328> f3c5ce30 vmov.i64 d28, #0xffff00ff00000000
0000032c <foo\+0x32c> f3c5fe30 vmov.i64 d31, #0xffff00ff00000000
-00000330 <foo\+0x330> 0d9f0b02 vldreq d0, \[pc, #8\] ; 00000340 <foo\+0x340>
-00000334 <foo\+0x334> 0d9feb01 vldreq d14, \[pc, #4\] ; 00000340 <foo\+0x340>
-00000338 <foo\+0x338> 0ddfcb00 vldreq d28, \[pc\] ; 00000340 <foo\+0x340>
-0000033c <foo\+0x33c> 0d5ffb01 vldreq d31, \[pc, #-4\] ; 00000340 <foo\+0x340>
+00000330 <foo\+0x330> 0d9f0b02 vldreq d0, \[pc, #8\] @ 00000340 <foo\+0x340>
+00000334 <foo\+0x334> 0d9feb01 vldreq d14, \[pc, #4\] @ 00000340 <foo\+0x340>
+00000338 <foo\+0x338> 0ddfcb00 vldreq d28, \[pc\] @ 00000340 <foo\+0x340>
+0000033c <foo\+0x33c> 0d5ffb01 vldreq d31, \[pc, #-4\] @ 00000340 <foo\+0x340>
00000340 <foo\+0x340> 000fff00 .word 0x000fff00
00000344 <foo\+0x344> 00000000 .word 0x00000000
00000348 <foo\+0x348> f2800e30 vmov.i64 d0, #0x0000000000000000
@@ -229,37 +229,37 @@ Disassembly of section .text:
0000036c <foo\+0x36c> f386ee30 vmov.i64 d14, #0xffffff0000000000
00000370 <foo\+0x370> f3c6ce30 vmov.i64 d28, #0xffffff0000000000
00000374 <foo\+0x374> f3c6fe30 vmov.i64 d31, #0xffffff0000000000
-00000378 <foo\+0x378> 4d9f0b02 vldrmi d0, \[pc, #8\] ; 00000388 <foo\+0x388>
-0000037c <foo\+0x37c> 4d9feb01 vldrmi d14, \[pc, #4\] ; 00000388 <foo\+0x388>
-00000380 <foo\+0x380> 4ddfcb00 vldrmi d28, \[pc\] ; 00000388 <foo\+0x388>
-00000384 <foo\+0x384> 4d5ffb01 vldrmi d31, \[pc, #-4\] ; 00000388 <foo\+0x388>
+00000378 <foo\+0x378> 4d9f0b02 vldrmi d0, \[pc, #8\] @ 00000388 <foo\+0x388>
+0000037c <foo\+0x37c> 4d9feb01 vldrmi d14, \[pc, #4\] @ 00000388 <foo\+0x388>
+00000380 <foo\+0x380> 4ddfcb00 vldrmi d28, \[pc\] @ 00000388 <foo\+0x388>
+00000384 <foo\+0x384> 4d5ffb01 vldrmi d31, \[pc, #-4\] @ 00000388 <foo\+0x388>
00000388 <foo\+0x388> 0000fff0 .word 0x0000fff0
0000038c <foo\+0x38c> 00000000 .word 0x00000000
-00000390 <foo\+0x390> ed9f1b00 vldr d1, \[pc\] ; 00000398 <foo\+0x398>
+00000390 <foo\+0x390> ed9f1b00 vldr d1, \[pc\] @ 00000398 <foo\+0x398>
00000394 <foo\+0x394> 00000000 .word 0x00000000
00000398 <foo\+0x398> 0000fff0 .word 0x0000fff0
0000039c <foo\+0x39c> 00000000 .word 0x00000000
000003a0 <foo\+0x3a0> e2810000 add r0, r1, #0
-000003a4 <foo\+0x3a4> ed1f1b01 vldr d1, \[pc, #-4\] ; 000003a8 <foo\+0x3a8>
+000003a4 <foo\+0x3a4> ed1f1b01 vldr d1, \[pc, #-4\] @ 000003a8 <foo\+0x3a8>
000003a8 <foo\+0x3a8> 0000fff0 .word 0x0000fff0
000003ac <foo\+0x3ac> 00000000 .word 0x00000000
-000003b0 <foo\+0x3b0> ed9f1b10 vldr d1, \[pc, #64\] ; 000003f8 <foo\+0x3f8>
-000003b4 <foo\+0x3b4> ed9f1a11 vldr s2, \[pc, #68\] ; 00000400 <foo\+0x400>
-000003b8 <foo\+0x3b8> ed9f3b12 vldr d3, \[pc, #72\] ; 00000408 <foo\+0x408>
-000003bc <foo\+0x3bc> ed9f2a10 vldr s4, \[pc, #64\] ; 00000404 <foo\+0x404>
-000003c0 <foo\+0x3c0> ed9f5b10 vldr d5, \[pc, #64\] ; 00000408 <foo\+0x408>
-000003c4 <foo\+0x3c4> ed9f6b11 vldr d6, \[pc, #68\] ; 00000410 <foo\+0x410>
-000003c8 <foo\+0x3c8> ed9f7b12 vldr d7, \[pc, #72\] ; 00000418 <foo\+0x418>
-000003cc <foo\+0x3cc> ed9f4a13 vldr s8, \[pc, #76\] ; 00000420 <foo\+0x420>
-000003d0 <foo\+0x3d0> ed9f9b14 vldr d9, \[pc, #80\] ; 00000428 <foo\+0x428>
-000003d4 <foo\+0x3d4> ed9f5a12 vldr s10, \[pc, #72\] ; 00000424 <foo\+0x424>
-000003d8 <foo\+0x3d8> ed9fbb14 vldr d11, \[pc, #80\] ; 00000430 <foo\+0x430>
-000003dc <foo\+0x3dc> ed9f6a15 vldr s12, \[pc, #84\] ; 00000438 <foo\+0x438>
-000003e0 <foo\+0x3e0> eddf6a15 vldr s13, \[pc, #84\] ; 0000043c <foo\+0x43c>
-000003e4 <foo\+0x3e4> ed9f7a06 vldr s14, \[pc, #24\] ; 00000404 <foo\+0x404>
-000003e8 <foo\+0x3e8> eddf7a02 vldr s15, \[pc, #8\] ; 000003f8 <foo\+0x3f8>
-000003ec <foo\+0x3ec> eddf0b13 vldr d16, \[pc, #76\] ; 00000440 <foo\+0x440>
-000003f0 <foo\+0x3f0> eddf1b14 vldr d17, \[pc, #80\] ; 00000448 <foo\+0x448>
+000003b0 <foo\+0x3b0> ed9f1b10 vldr d1, \[pc, #64\] @ 000003f8 <foo\+0x3f8>
+000003b4 <foo\+0x3b4> ed9f1a11 vldr s2, \[pc, #68\] @ 00000400 <foo\+0x400>
+000003b8 <foo\+0x3b8> ed9f3b12 vldr d3, \[pc, #72\] @ 00000408 <foo\+0x408>
+000003bc <foo\+0x3bc> ed9f2a10 vldr s4, \[pc, #64\] @ 00000404 <foo\+0x404>
+000003c0 <foo\+0x3c0> ed9f5b10 vldr d5, \[pc, #64\] @ 00000408 <foo\+0x408>
+000003c4 <foo\+0x3c4> ed9f6b11 vldr d6, \[pc, #68\] @ 00000410 <foo\+0x410>
+000003c8 <foo\+0x3c8> ed9f7b12 vldr d7, \[pc, #72\] @ 00000418 <foo\+0x418>
+000003cc <foo\+0x3cc> ed9f4a13 vldr s8, \[pc, #76\] @ 00000420 <foo\+0x420>
+000003d0 <foo\+0x3d0> ed9f9b14 vldr d9, \[pc, #80\] @ 00000428 <foo\+0x428>
+000003d4 <foo\+0x3d4> ed9f5a12 vldr s10, \[pc, #72\] @ 00000424 <foo\+0x424>
+000003d8 <foo\+0x3d8> ed9fbb14 vldr d11, \[pc, #80\] @ 00000430 <foo\+0x430>
+000003dc <foo\+0x3dc> ed9f6a15 vldr s12, \[pc, #84\] @ 00000438 <foo\+0x438>
+000003e0 <foo\+0x3e0> eddf6a15 vldr s13, \[pc, #84\] @ 0000043c <foo\+0x43c>
+000003e4 <foo\+0x3e4> ed9f7a06 vldr s14, \[pc, #24\] @ 00000404 <foo\+0x404>
+000003e8 <foo\+0x3e8> eddf7a02 vldr s15, \[pc, #8\] @ 000003f8 <foo\+0x3f8>
+000003ec <foo\+0x3ec> eddf0b13 vldr d16, \[pc, #76\] @ 00000440 <foo\+0x440>
+000003f0 <foo\+0x3f0> eddf1b14 vldr d17, \[pc, #80\] @ 00000448 <foo\+0x448>
000003f4 <foo\+0x3f4> 00000000 .word 0x00000000
000003f8 <foo\+0x3f8> 0000fff0 .word 0x0000fff0
000003fc <foo\+0x3fc> 00000000 .word 0x00000000
diff --git a/gas/testsuite/gas/arm/vldr.d b/gas/testsuite/gas/arm/vldr.d
index 61ba87e1e8f..20a7798cd35 100644
--- a/gas/testsuite/gas/arm/vldr.d
+++ b/gas/testsuite/gas/arm/vldr.d
@@ -8,8 +8,8 @@
Disassembly of section .text:
0[0-9a-f]+ <[^>]+> bf00 nop
-0[0-9a-f]+ <[^>]+> ed9f 0b03 vldr d0, \[pc, #12\] ; 00000010 <float>
-0[0-9a-f]+ <[^>]+> ed9f 0b02 vldr d0, \[pc, #8\] ; 00000010 <float>
+0[0-9a-f]+ <[^>]+> ed9f 0b03 vldr d0, \[pc, #12\] @ 00000010 <float>
+0[0-9a-f]+ <[^>]+> ed9f 0b02 vldr d0, \[pc, #8\] @ 00000010 <float>
0[0-9a-f]+ <[^>]+> bf00 nop
0[0-9a-f]+ <[^>]+> bf00 nop
0[0-9a-f]+ <[^>]+> bf00 nop
diff --git a/gas/testsuite/gas/arm/wince.d b/gas/testsuite/gas/arm/wince.d
index cb84aecf0a1..e5bac1de9c6 100644
--- a/gas/testsuite/gas/arm/wince.d
+++ b/gas/testsuite/gas/arm/wince.d
@@ -11,9 +11,9 @@
Disassembly of section .text:
0+000 <global_data> 00000007 andeq r0, r0, r7
0: ARM_32 global_data
-0+004 <global_sym> e1a00000 nop ; \(mov r0, r0\)
-0+008 <global_sym\+0x4> e1a00000 nop ; \(mov r0, r0\)
-0+00c <global_sym\+0x8> e1a00000 nop ; \(mov r0, r0\)
+0+004 <global_sym> e1a00000 nop @ \(mov r0, r0\)
+0+008 <global_sym\+0x4> e1a00000 nop @ \(mov r0, r0\)
+0+00c <global_sym\+0x8> e1a00000 nop @ \(mov r0, r0\)
0+010 <global_sym\+0xc> eafffffb b f+ff8 <global_sym\+0xf+ff4>
10: ARM_26D global_sym-0x4
0+014 <global_sym\+0x10> ebfffffa bl f+ff4 <global_sym\+0xf+ff0>
@@ -25,6 +25,6 @@ Disassembly of section .text:
0+024 <global_sym\+0x20> 0afffff6 beq 0+004 <global_sym>
0+028 <global_sym\+0x24> eafffff5 b 0+004 <global_sym>
0+02c <global_sym\+0x28> ebfffff4 bl 0+004 <global_sym>
-0+030 <global_sym\+0x2c> e51f0034 ldr r0, \[pc, #-52\] ; 0+004 <global_sym>
-0+034 <global_sym\+0x30> e51f0038 ldr r0, \[pc, #-56\] ; 0+004 <global_sym>
-0+038 <global_sym\+0x34> e51f003c ldr r0, \[pc, #-60\] ; 0+004 <global_sym>
+0+030 <global_sym\+0x2c> e51f0034 ldr r0, \[pc, #-52\] @ 0+004 <global_sym>
+0+034 <global_sym\+0x30> e51f0038 ldr r0, \[pc, #-56\] @ 0+004 <global_sym>
+0+038 <global_sym\+0x34> e51f003c ldr r0, \[pc, #-60\] @ 0+004 <global_sym>
diff --git a/gas/testsuite/gas/arm/wince_inst.d b/gas/testsuite/gas/arm/wince_inst.d
index 6ed6f867c83..390e4536ae6 100644
--- a/gas/testsuite/gas/arm/wince_inst.d
+++ b/gas/testsuite/gas/arm/wince_inst.d
@@ -97,22 +97,22 @@ Disassembly of section .text:
0+14c <[^>]*> e1720004 ? cmn r2, r4
0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5
0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1
-0+158 <[^>]*> e330f00a ? teq r0, #10 ; <UNPREDICTABLE>
-0+15c <[^>]*> e132f004 ? teq r2, r4 ; <UNPREDICTABLE>
-0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5 ; <UNPREDICTABLE>
-0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1 ; <UNPREDICTABLE>
-0+168 <[^>]*> e370f00a ? cmn r0, #10 ; <UNPREDICTABLE>
-0+16c <[^>]*> e172f004 ? cmn r2, r4 ; <UNPREDICTABLE>
-0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5 ; <UNPREDICTABLE>
-0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1 ; <UNPREDICTABLE>
-0+178 <[^>]*> e350f00a ? cmp r0, #10 ; <UNPREDICTABLE>
-0+17c <[^>]*> e152f004 ? cmp r2, r4 ; <UNPREDICTABLE>
-0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5 ; <UNPREDICTABLE>
-0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1 ; <UNPREDICTABLE>
-0+188 <[^>]*> e310f00a ? tst r0, #10 ; <UNPREDICTABLE>
-0+18c <[^>]*> e112f004 ? tst r2, r4 ; <UNPREDICTABLE>
-0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5 ; <UNPREDICTABLE>
-0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1 ; <UNPREDICTABLE>
+0+158 <[^>]*> e330f00a ? teq r0, #10 @ <UNPREDICTABLE>
+0+15c <[^>]*> e132f004 ? teq r2, r4 @ <UNPREDICTABLE>
+0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5 @ <UNPREDICTABLE>
+0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1 @ <UNPREDICTABLE>
+0+168 <[^>]*> e370f00a ? cmn r0, #10 @ <UNPREDICTABLE>
+0+16c <[^>]*> e172f004 ? cmn r2, r4 @ <UNPREDICTABLE>
+0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5 @ <UNPREDICTABLE>
+0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1 @ <UNPREDICTABLE>
+0+178 <[^>]*> e350f00a ? cmp r0, #10 @ <UNPREDICTABLE>
+0+17c <[^>]*> e152f004 ? cmp r2, r4 @ <UNPREDICTABLE>
+0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5 @ <UNPREDICTABLE>
+0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1 @ <UNPREDICTABLE>
+0+188 <[^>]*> e310f00a ? tst r0, #10 @ <UNPREDICTABLE>
+0+18c <[^>]*> e112f004 ? tst r2, r4 @ <UNPREDICTABLE>
+0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5 @ <UNPREDICTABLE>
+0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1 @ <UNPREDICTABLE>
0+198 <[^>]*> e0000291 ? mul r0, r1, r2
0+19c <[^>]*> e0110392 ? muls r1, r2, r3
0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0
@@ -130,7 +130,7 @@ Disassembly of section .text:
0+1d0 <[^>]*> 14954006 ? ldrne r4, \[r5\], #6
0+1d4 <[^>]*> e6b21003 ? ldrt r1, \[r2\], r3
0+1d8 <[^>]*> e6942425 ? ldr r2, \[r4\], r5, lsr #8
-0+1dc <[^>]*> e51f0008 ? ldr r0, \[pc, #-8\] ; 0+1dc <[^>]*>
+0+1dc <[^>]*> e51f0008 ? ldr r0, \[pc, #-8\] @ 0+1dc <[^>]*>
0+1e0 <[^>]*> e5d43000 ? ldrb r3, \[r4\]
0+1e4 <[^>]*> 14f85000 ? ldrbtne r5, \[r8\], #0
0+1e8 <[^>]*> e5810000 ? str r0, \[r1\]
@@ -142,7 +142,7 @@ Disassembly of section .text:
0+200 <[^>]*> 14854006 ? strne r4, \[r5\], #6
0+204 <[^>]*> e6821003 ? str r1, \[r2\], r3
0+208 <[^>]*> e6a42425 ? strt r2, \[r4\], r5, lsr #8
-0+20c <[^>]*> e50f1004 ? str r1, \[pc, #-4\] ; 0+210 <[^>]*>
+0+20c <[^>]*> e50f1004 ? str r1, \[pc, #-4\] @ 0+210 <[^>]*>
0+210 <[^>]*> e5c71000 ? strb r1, \[r7\]
0+214 <[^>]*> e4e02000 ? strbt r2, \[r0\], #0
0+218 <[^>]*> e8900002 ? ldm r0, {r1}
diff --git a/gas/testsuite/gas/arm/xscale.d b/gas/testsuite/gas/arm/xscale.d
index da4d1d7bfe9..04f2b449ed6 100644
--- a/gas/testsuite/gas/arm/xscale.d
+++ b/gas/testsuite/gas/arm/xscale.d
@@ -33,5 +33,5 @@ Disassembly of section .text:
0+5c <[^>]*> e5910000 ldr r0, \[r1\]
0+60 <[^>]*> e5832000 str r2, \[r3\]
0+64 <[^>]*> e321f011 msr CPSR_c, #17
-0+68 <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\)
-0+6c <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\)
+0+68 <[^>]*> e1a00000 ? nop[ ]+@ \(mov r0, r0\)
+0+6c <[^>]*> e1a00000 ? nop[ ]+@ \(mov r0, r0\)
diff --git a/ld/testsuite/ld-arm/arm-app-abs32.d b/ld/testsuite/ld-arm/arm-app-abs32.d
index d8889293762..916f90c10d8 100644
--- a/ld/testsuite/ld-arm/arm-app-abs32.d
+++ b/ld/testsuite/ld-arm/arm-app-abs32.d
@@ -7,21 +7,21 @@ start address .*
Disassembly of section .plt:
.* <.plt>:
- +.*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- +.*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ +.*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ +.*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
+.*: e08fe00e add lr, pc, lr
+.*: e5bef008 ldr pc, \[lr, #8\]!
+.*: .* .*
.* <lib_func1@plt>:
+.*: e28fc6.* add ip, pc, #.*
- +.*: e28cca.* add ip, ip, #.* ; .*
+ +.*: e28cca.* add ip, ip, #.* @ .*
+.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.* <_start>:
+.*: e1a0c00d mov ip, sp
+.*: e92dd800 push {fp, ip, lr, pc}
- +.*: e59f0004 ldr r0, \[pc, #4\] ; .* <_start\+0x14>
+ +.*: e59f0004 ldr r0, \[pc, #4\] @ .* <_start\+0x14>
+.*: e89d6800 ldm sp, {fp, sp, lr}
+.*: e12fff1e bx lr
+.*: .* .*
diff --git a/ld/testsuite/ld-arm/arm-app.d b/ld/testsuite/ld-arm/arm-app.d
index dd4cf81bc9c..a9bd7edb731 100644
--- a/ld/testsuite/ld-arm/arm-app.d
+++ b/ld/testsuite/ld-arm/arm-app.d
@@ -7,14 +7,14 @@ start address 0x.*
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.* <lib_func1@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
diff --git a/ld/testsuite/ld-arm/arm-be8.d b/ld/testsuite/ld-arm/arm-be8.d
index 16090b3d663..072cc7c2aa8 100644
--- a/ld/testsuite/ld-arm/arm-be8.d
+++ b/ld/testsuite/ld-arm/arm-be8.d
@@ -8,7 +8,7 @@ Disassembly of section .text:
8004: e12fff1e bx lr
00008008 <thumb>:
- 8008: 46c0 nop ; \(mov r8, r8\)
+ 8008: 46c0 nop @ \(mov r8, r8\)
800a: 4770 bx lr
800c: f7ff fffc bl 8008 <thumb>
diff --git a/ld/testsuite/ld-arm/arm-call.d b/ld/testsuite/ld-arm/arm-call.d
index a3207430b79..4ae34382232 100644
--- a/ld/testsuite/ld-arm/arm-call.d
+++ b/ld/testsuite/ld-arm/arm-call.d
@@ -26,7 +26,7 @@ Disassembly of section .text:
00008038 <t4>:
8038: 4770 bx lr
- 803a: 46c0 nop ; \(mov r8, r8\)
+ 803a: 46c0 nop @ \(mov r8, r8\)
0000803c <arm>:
803c: e12fff1e bx lr
@@ -40,7 +40,7 @@ Disassembly of section .text:
0000804a <t5>:
804a: f000 f801 bl 8050 <local_thumb>
- 804e: 46c0 nop ; \(mov r8, r8\)
+ 804e: 46c0 nop @ \(mov r8, r8\)
00008050 <local_thumb>:
8050: f7ff fff1 bl 8036 <t3>
@@ -50,9 +50,9 @@ Disassembly of section .text:
...
00008060 <__t1_from_arm>:
- 8060: e51ff004 ldr pc, \[pc, #-4\] ; 8064 <__t1_from_arm\+0x4>
+ 8060: e51ff004 ldr pc, \[pc, #-4\] @ 8064 <__t1_from_arm\+0x4>
8064: 00008041 .word 0x00008041
00008068 <__t2_from_arm>:
- 8068: e51ff004 ldr pc, \[pc, #-4\] ; 806c <__t2_from_arm\+0x4>
+ 8068: e51ff004 ldr pc, \[pc, #-4\] @ 806c <__t2_from_arm\+0x4>
806c: 00008043 .word 0x00008043
diff --git a/ld/testsuite/ld-arm/arm-lib-plt32.d b/ld/testsuite/ld-arm/arm-lib-plt32.d
index 2eaf89ab512..7a9a3ab53b7 100644
--- a/ld/testsuite/ld-arm/arm-lib-plt32.d
+++ b/ld/testsuite/ld-arm/arm-lib-plt32.d
@@ -7,14 +7,14 @@ start address 0x.*
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.* <app_func2@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
diff --git a/ld/testsuite/ld-arm/arm-lib.d b/ld/testsuite/ld-arm/arm-lib.d
index ac439ea3d1b..8f56477cbba 100644
--- a/ld/testsuite/ld-arm/arm-lib.d
+++ b/ld/testsuite/ld-arm/arm-lib.d
@@ -7,14 +7,14 @@ start address 0x.*
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.* <app_func2@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
diff --git a/ld/testsuite/ld-arm/arm-movwt.d b/ld/testsuite/ld-arm/arm-movwt.d
index 7d558b76170..64f4fde57e4 100644
--- a/ld/testsuite/ld-arm/arm-movwt.d
+++ b/ld/testsuite/ld-arm/arm-movwt.d
@@ -5,35 +5,35 @@ Disassembly of section .text:
00008000 <[^>]*>:
8000: e3000000 movw r0, #0
- 8004: e3411234 movt r1, #4660 ; 0x1234
- 8008: e3082000 movw r2, #32768 ; 0x8000
- 800c: e3413233 movt r3, #4659 ; 0x1233
+ 8004: e3411234 movt r1, #4660 @ 0x1234
+ 8008: e3082000 movw r2, #32768 @ 0x8000
+ 800c: e3413233 movt r3, #4659 @ 0x1233
8010: e3004011 movw r4, #17
- 8014: e3415234 movt r5, #4660 ; 0x1234
- 8018: e3086011 movw r6, #32785 ; 0x8011
- 801c: e3417233 movt r7, #4659 ; 0x1233
+ 8014: e3415234 movt r5, #4660 @ 0x1234
+ 8018: e3086011 movw r6, #32785 @ 0x8011
+ 801c: e3417233 movt r7, #4659 @ 0x1233
00008020 <[^>]*>:
8020: f240 0700 movw r7, #0
- 8024: f2c1 2634 movt r6, #4660 ; 0x1234
- 8028: f248 0500 movw r5, #32768 ; 0x8000
- 802c: f2c1 2433 movt r4, #4659 ; 0x1233
+ 8024: f2c1 2634 movt r6, #4660 @ 0x1234
+ 8028: f248 0500 movw r5, #32768 @ 0x8000
+ 802c: f2c1 2433 movt r4, #4659 @ 0x1233
8030: f240 0311 movw r3, #17
- 8034: f2c1 2234 movt r2, #4660 ; 0x1234
- 8038: f248 0111 movw r1, #32785 ; 0x8011
- 803c: f2c1 2033 movt r0, #4659 ; 0x1233
+ 8034: f2c1 2234 movt r2, #4660 @ 0x1234
+ 8038: f248 0111 movw r1, #32785 @ 0x8011
+ 803c: f2c1 2033 movt r0, #4659 @ 0x1233
Disassembly of section .far:
12340000 <[^>]*>:
-12340000: e3080000 movw r0, #32768 ; 0x8000
-12340004: e34e0dcc movt r0, #60876 ; 0xedcc
-12340008: e3080021 movw r0, #32801 ; 0x8021
-1234000c: e34e0dcc movt r0, #60876 ; 0xedcc
+12340000: e3080000 movw r0, #32768 @ 0x8000
+12340004: e34e0dcc movt r0, #60876 @ 0xedcc
+12340008: e3080021 movw r0, #32801 @ 0x8021
+1234000c: e34e0dcc movt r0, #60876 @ 0xedcc
12340010 <[^>]*>:
-12340010: f248 0000 movw r0, #32768 ; 0x8000
-12340014: f6ce 50cc movt r0, #60876 ; 0xedcc
-12340018: f248 0021 movw r0, #32801 ; 0x8021
-1234001c: f6ce 50cc movt r0, #60876 ; 0xedcc
+12340010: f248 0000 movw r0, #32768 @ 0x8000
+12340014: f6ce 50cc movt r0, #60876 @ 0xedcc
+12340018: f248 0021 movw r0, #32801 @ 0x8021
+1234001c: f6ce 50cc movt r0, #60876 @ 0xedcc
diff --git a/ld/testsuite/ld-arm/arm-pic-veneer.d b/ld/testsuite/ld-arm/arm-pic-veneer.d
index 08e107b6626..b80f30fd44d 100644
--- a/ld/testsuite/ld-arm/arm-pic-veneer.d
+++ b/ld/testsuite/ld-arm/arm-pic-veneer.d
@@ -7,11 +7,11 @@ Disassembly of section .text:
8000: ea...... b 800. <.*>
00008004 <foo>:
- 8004: 46c0 nop ; \(mov r8, r8\)
+ 8004: 46c0 nop @ \(mov r8, r8\)
8006: 4770 bx lr
00008008 <__foo_from_arm>:
- 8008: e59fc004 ldr ip, \[pc, #4\] ; 8014 <__foo_from_arm\+0xc>
+ 8008: e59fc004 ldr ip, \[pc, #4\] @ 8014 <__foo_from_arm\+0xc>
800c: e08fc00c add ip, pc, ip
8010: e12fff1c bx ip
8014: fffffff1 .word 0xfffffff1
diff --git a/ld/testsuite/ld-arm/armthumb-lib.d b/ld/testsuite/ld-arm/armthumb-lib.d
index 4f43b8ebe0c..fd9cd959eaf 100644
--- a/ld/testsuite/ld-arm/armthumb-lib.d
+++ b/ld/testsuite/ld-arm/armthumb-lib.d
@@ -7,14 +7,14 @@ start address 0x.*
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.* <app_func2@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
@@ -24,16 +24,16 @@ Disassembly of section .text:
.*: ebfffff. bl .* <app_func2@plt>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <__real_lib_func2>:
.*: 4770 bx lr
- .*: 46c0 nop ; \(mov r8, r8\)
+ .*: 46c0 nop @ \(mov r8, r8\)
.* <lib_func2>:
- .*: e59fc004 ldr ip, \[pc, #4\] ; .* <lib_func2\+0xc>
+ .*: e59fc004 ldr ip, \[pc, #4\] @ .* <lib_func2\+0xc>
.*: e08cc00f add ip, ip, pc
.*: e12fff1c bx ip
.*: fffffff1 .*
diff --git a/ld/testsuite/ld-arm/attr-merge-wchar-24.d b/ld/testsuite/ld-arm/attr-merge-wchar-24.d
index 46d6c66f353..92a26ab505b 100644
--- a/ld/testsuite/ld-arm/attr-merge-wchar-24.d
+++ b/ld/testsuite/ld-arm/attr-merge-wchar-24.d
@@ -2,4 +2,4 @@
#source: attr-merge-wchar-4.s
#as:
#ld: -r
-#warning: warning: .* uses 4-byte wchar_t yet the output is to use 2-byte wchar_t; use of wchar_t values across objects may fail
+#warning: warning: .* uses 4-byte wchar_t yet the output is to use 2-byte wchar_t@ use of wchar_t values across objects may fail
diff --git a/ld/testsuite/ld-arm/attr-merge-wchar-42.d b/ld/testsuite/ld-arm/attr-merge-wchar-42.d
index c2aca5e67cc..274cdc84fbc 100644
--- a/ld/testsuite/ld-arm/attr-merge-wchar-42.d
+++ b/ld/testsuite/ld-arm/attr-merge-wchar-42.d
@@ -2,4 +2,4 @@
#source: attr-merge-wchar-2.s
#as:
#ld: -r
-#warning: warning: .* uses 2-byte wchar_t yet the output is to use 4-byte wchar_t; use of wchar_t values across objects may fail
+#warning: warning: .* uses 2-byte wchar_t yet the output is to use 4-byte wchar_t@ use of wchar_t values across objects may fail
diff --git a/ld/testsuite/ld-arm/callweak.d b/ld/testsuite/ld-arm/callweak.d
index 89cb4a5cb72..698942f4e5c 100644
--- a/ld/testsuite/ld-arm/callweak.d
+++ b/ld/testsuite/ld-arm/callweak.d
@@ -4,7 +4,7 @@
Disassembly of section .far:
12340000 <[^>]*>:
-12340000: e1a00000 nop ; \(mov r0, r0\)
+12340000: e1a00000 nop @ \(mov r0, r0\)
12340004: 01a00000 moveq r0, r0
12340008 <[^>]*>:
diff --git a/ld/testsuite/ld-arm/cortex-a8-far.d b/ld/testsuite/ld-arm/cortex-a8-far.d
index 9b106597079..a87cd5da503 100644
--- a/ld/testsuite/ld-arm/cortex-a8-far.d
+++ b/ld/testsuite/ld-arm/cortex-a8-far.d
@@ -10,7 +10,7 @@ Disassembly of section \.text:
...
#...
00800008 <__far_fn_from_thumb>:
- 800008: e51ff004 ldr pc, \[pc, #-4\] ; 80000c <__far_fn_from_thumb\+0x4>
+ 800008: e51ff004 ldr pc, \[pc, #-4\] @ 80000c <__far_fn_from_thumb\+0x4>
80000c: 7fff0000 .word 0x7fff0000
00800010 <three>:
@@ -30,11 +30,11 @@ Disassembly of section \.text:
...
00801018 <__far_fn2_from_thumb>:
- 801018: e51ff004 ldr pc, \[pc, #-4\] ; 80101c <__far_fn2_from_thumb\+0x4>
+ 801018: e51ff004 ldr pc, \[pc, #-4\] @ 80101c <__far_fn2_from_thumb\+0x4>
80101c: 80000004 .word 0x80000004
00801020 <__far_fn1_from_thumb>:
- 801020: e51ff004 ldr pc, \[pc, #-4\] ; 801024 <__far_fn1_from_thumb\+0x4>
+ 801020: e51ff004 ldr pc, \[pc, #-4\] @ 801024 <__far_fn1_from_thumb\+0x4>
801024: 80000000 .word 0x80000000
801028: d001 beq.n 80102e <__far_fn1_from_thumb\+0xe>
80102a: f7ff bfea b.w 801002 <label1\+0x8>
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.d b/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.d
index 54f56e4ccbc..d524c8c57cb 100644
--- a/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.d
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.d
@@ -5,8 +5,8 @@
Disassembly of section \.plt:
00008000 <.*>:
- 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <.*>
+ 8000: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ 8004: e59fe004 ldr lr, \[pc, #4\] @ 8010 <.*>
8008: e08fe00e add lr, pc, lr
800c: e5bef008 ldr pc, \[lr, #8\]!
8010: 00000ffc \.word 0x00000ffc
@@ -15,12 +15,12 @@ Disassembly of section \.plt:
8016: e7fd b.n .+ <.+>
8018: e28fc600 add ip, pc, #0, 12
801c: e28cca00 add ip, ip, #0, 20
- 8020: e5bcfff8 ldr pc, \[ip, #4088\]! ; 0xff8
+ 8020: e5bcfff8 ldr pc, \[ip, #4088\]! @ 0xff8
Disassembly of section \.text:
00008ff0 <foo>:
- 8ff0: 46c0 nop ; \(mov r8, r8\)
+ 8ff0: 46c0 nop @ \(mov r8, r8\)
8ff2: f240 0000 movw r0, #0
8ff6: f240 0000 movw r0, #0
8ffa: f240 0000 movw r0, #0
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.d b/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.d
index 425c10207f6..4abb6f456cf 100644
--- a/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.d
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.d
@@ -5,8 +5,8 @@
Disassembly of section \.plt:
00008000 <.plt>:
- 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <.*>
+ 8000: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ 8004: e59fe004 ldr lr, \[pc, #4\] @ 8010 <.*>
8008: e08fe00e add lr, pc, lr
800c: e5bef008 ldr pc, \[lr, #8\]!
8010: 00001004 \.word 0x00001004
@@ -14,13 +14,13 @@ Disassembly of section \.plt:
8014: 4778 bx pc
8016: e7fd b.n .+ <.+>
8018: e28fc600 add ip, pc, #0, 12
- 801c: e28cca01 add ip, ip, #4096 ; 0x1000
+ 801c: e28cca01 add ip, ip, #4096 @ 0x1000
8020: e5bcf000 ldr pc, \[ip, #0\]!
Disassembly of section \.text:
00008ff0 <foo>:
- 8ff0: 46c0 nop ; \(mov r8, r8\)
+ 8ff0: 46c0 nop @ \(mov r8, r8\)
8ff2: f240 0000 movw r0, #0
8ff6: f240 0000 movw r0, #0
8ffa: f240 0000 movw r0, #0
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.d b/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.d
index e4e67607383..275a877449b 100644
--- a/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.d
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.d
@@ -5,20 +5,20 @@
Disassembly of section \.plt:
00008000 <.plt>:
- 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <.*>
+ 8000: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ 8004: e59fe004 ldr lr, \[pc, #4\] @ 8010 <.*>
8008: e08fe00e add lr, pc, lr
800c: e5bef008 ldr pc, \[lr, #8\]!
8010: 00000ffc \.word 0x00000ffc
00008014 <bar@plt>:
8014: e28fc600 add ip, pc, #0, 12
8018: e28cca00 add ip, ip, #0, 20
- 801c: e5bcfffc ldr pc, \[ip, #4092\]! ; 0xffc
+ 801c: e5bcfffc ldr pc, \[ip, #4092\]! @ 0xffc
Disassembly of section \.text:
00008ff0 <foo>:
- 8ff0: 46c0 nop ; \(mov r8, r8\)
+ 8ff0: 46c0 nop @ \(mov r8, r8\)
8ff2: f240 0000 movw r0, #0
8ff6: f240 0000 movw r0, #0
8ffa: f240 0000 movw r0, #0
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d b/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d
index 4a5be273fad..5605a71fe8f 100644
--- a/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d
@@ -5,15 +5,15 @@
Disassembly of section \.plt:
00008e00 <.plt>:
- 8e00: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- 8e04: e59fe004 ldr lr, \[pc, #4\] ; 8e10 <.*>
+ 8e00: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ 8e04: e59fe004 ldr lr, \[pc, #4\] @ 8e10 <.*>
8e08: e08fe00e add lr, pc, lr
8e0c: e5bef008 ldr pc, \[lr, #8\]!
8e10: 0001027c \.word 0x0001027c
00008e14 <targetfn@plt>:
8e14: e28fc600 add ip, pc, #0, 12
- 8e18: e28cca10 add ip, ip, #16, 20 ; 0x10000
- 8e1c: e5bcf27c ldr pc, \[ip, #636\]! ; 0x27c
+ 8e18: e28cca10 add ip, ip, #16, 20 @ 0x10000
+ 8e1c: e5bcf27c ldr pc, \[ip, #636\]! @ 0x27c
Disassembly of section \.text:
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.d b/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.d
index e4e67607383..275a877449b 100644
--- a/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.d
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.d
@@ -5,20 +5,20 @@
Disassembly of section \.plt:
00008000 <.plt>:
- 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <.*>
+ 8000: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ 8004: e59fe004 ldr lr, \[pc, #4\] @ 8010 <.*>
8008: e08fe00e add lr, pc, lr
800c: e5bef008 ldr pc, \[lr, #8\]!
8010: 00000ffc \.word 0x00000ffc
00008014 <bar@plt>:
8014: e28fc600 add ip, pc, #0, 12
8018: e28cca00 add ip, ip, #0, 20
- 801c: e5bcfffc ldr pc, \[ip, #4092\]! ; 0xffc
+ 801c: e5bcfffc ldr pc, \[ip, #4092\]! @ 0xffc
Disassembly of section \.text:
00008ff0 <foo>:
- 8ff0: 46c0 nop ; \(mov r8, r8\)
+ 8ff0: 46c0 nop @ \(mov r8, r8\)
8ff2: f240 0000 movw r0, #0
8ff6: f240 0000 movw r0, #0
8ffa: f240 0000 movw r0, #0
diff --git a/ld/testsuite/ld-arm/farcall-arm-arm-pic-veneer.d b/ld/testsuite/ld-arm/farcall-arm-arm-pic-veneer.d
index 881a0ae20e6..844880af73e 100644
--- a/ld/testsuite/ld-arm/farcall-arm-arm-pic-veneer.d
+++ b/ld/testsuite/ld-arm/farcall-arm-arm-pic-veneer.d
@@ -7,7 +7,7 @@ Disassembly of section .text:
1004: 00000000 andeq r0, r0, r0
00001008 <__bar_veneer>:
- 1008: e59fc000 ldr ip, \[pc\] ; 1010 <__bar_veneer\+0x8>
+ 1008: e59fc000 ldr ip, \[pc\] @ 1010 <__bar_veneer\+0x8>
100c: e08ff00c add pc, pc, ip
1010: 0200000c .word 0x0200000c
1014: 00000000 .word 0x00000000
diff --git a/ld/testsuite/ld-arm/farcall-arm-arm.d b/ld/testsuite/ld-arm/farcall-arm-arm.d
index 7ee6d66c598..76a13351bcb 100644
--- a/ld/testsuite/ld-arm/farcall-arm-arm.d
+++ b/ld/testsuite/ld-arm/farcall-arm-arm.d
@@ -7,7 +7,7 @@ Disassembly of section .text:
1004: 00000000 andeq r0, r0, r0
00001008 <__bar_veneer>:
- 1008: e51ff004 ldr pc, \[pc, #-4\] ; 100c <__bar_veneer\+0x4>
+ 1008: e51ff004 ldr pc, \[pc, #-4\] @ 100c <__bar_veneer\+0x4>
100c: 02001020 .word 0x02001020
Disassembly of section .foo:
diff --git a/ld/testsuite/ld-arm/farcall-arm-nacl-pic.d b/ld/testsuite/ld-arm/farcall-arm-nacl-pic.d
index 62d342121f3..a39a468da31 100644
--- a/ld/testsuite/ld-arm/farcall-arm-nacl-pic.d
+++ b/ld/testsuite/ld-arm/farcall-arm-nacl-pic.d
@@ -7,9 +7,9 @@ Disassembly of section \.text:
#...
0+1010 <__bar_veneer>:
-\s*1010:\s+e59fc00c\s+ldr\s+ip, \[pc, #12\]\s+; 1024 <__bar_veneer\+0x14>
+\s*1010:\s+e59fc00c\s+ldr\s+ip, \[pc, #12\]\s+@ 1024 <__bar_veneer\+0x14>
\s*1014:\s+e08cc00f\s+add\s+ip, ip, pc
-\s*1018:\s+e3ccc13f\s+bic\s+ip, ip, #-1073741809\s+; 0xc000000f
+\s*1018:\s+e3ccc13f\s+bic\s+ip, ip, #-1073741809\s+@ 0xc000000f
\s*101c:\s+e12fff1c\s+bx\s+ip
\s*1020:\s+e125be70\s+bkpt\s+0x5be0
\s*1024:\s+02000004\s+.word\s+0x02000004
diff --git a/ld/testsuite/ld-arm/farcall-arm-nacl.d b/ld/testsuite/ld-arm/farcall-arm-nacl.d
index 58f2a58c4be..0431f4a517d 100644
--- a/ld/testsuite/ld-arm/farcall-arm-nacl.d
+++ b/ld/testsuite/ld-arm/farcall-arm-nacl.d
@@ -7,8 +7,8 @@ Disassembly of section \.text:
#...
0+1010 <__bar_veneer>:
-\s*1010:\s+e59fc00c\s+ldr\s+ip, \[pc, #12\]\s+; 1024 <__bar_veneer\+0x14>
-\s*1014:\s+e3ccc13f\s+bic\s+ip, ip, #-1073741809\s+; 0xc000000f
+\s*1010:\s+e59fc00c\s+ldr\s+ip, \[pc, #12\]\s+@ 1024 <__bar_veneer\+0x14>
+\s*1014:\s+e3ccc13f\s+bic\s+ip, ip, #-1073741809\s+@ 0xc000000f
\s*1018:\s+e12fff1c\s+bx\s+ip
\s*101c:\s+e320f000\s+nop\s+\{0\}
\s*1020:\s+e125be70\s+bkpt\s+0x5be0
diff --git a/ld/testsuite/ld-arm/farcall-arm-thumb-blx-pic-veneer.d b/ld/testsuite/ld-arm/farcall-arm-thumb-blx-pic-veneer.d
index 45bc01c7a8f..92480b97aa1 100644
--- a/ld/testsuite/ld-arm/farcall-arm-thumb-blx-pic-veneer.d
+++ b/ld/testsuite/ld-arm/farcall-arm-thumb-blx-pic-veneer.d
@@ -7,7 +7,7 @@ Disassembly of section .text:
1004: 00000000 andeq r0, r0, r0
00001008 <__bar_from_arm>:
- 1008: e59fc004 ldr ip, \[pc, #4\] ; 1014 <__bar_from_arm\+0xc>
+ 1008: e59fc004 ldr ip, \[pc, #4\] @ 1014 <__bar_from_arm\+0xc>
100c: e08fc00c add ip, pc, ip
1010: e12fff1c bx ip
1014: 02000001 .word 0x02000001
diff --git a/ld/testsuite/ld-arm/farcall-arm-thumb-blx.d b/ld/testsuite/ld-arm/farcall-arm-thumb-blx.d
index 993a028651a..b47bfe07b7d 100644
--- a/ld/testsuite/ld-arm/farcall-arm-thumb-blx.d
+++ b/ld/testsuite/ld-arm/farcall-arm-thumb-blx.d
@@ -7,7 +7,7 @@ Disassembly of section .text:
1004: 00000000 andeq r0, r0, r0
00001008 <__bar_from_arm>:
- 1008: e51ff004 ldr pc, \[pc, #-4\] ; 100c <__bar_from_arm\+0x4>
+ 1008: e51ff004 ldr pc, \[pc, #-4\] @ 100c <__bar_from_arm\+0x4>
100c: 02001015 .word 0x02001015
Disassembly of section .foo:
diff --git a/ld/testsuite/ld-arm/farcall-arm-thumb-pic-veneer.d b/ld/testsuite/ld-arm/farcall-arm-thumb-pic-veneer.d
index 45bc01c7a8f..92480b97aa1 100644
--- a/ld/testsuite/ld-arm/farcall-arm-thumb-pic-veneer.d
+++ b/ld/testsuite/ld-arm/farcall-arm-thumb-pic-veneer.d
@@ -7,7 +7,7 @@ Disassembly of section .text:
1004: 00000000 andeq r0, r0, r0
00001008 <__bar_from_arm>:
- 1008: e59fc004 ldr ip, \[pc, #4\] ; 1014 <__bar_from_arm\+0xc>
+ 1008: e59fc004 ldr ip, \[pc, #4\] @ 1014 <__bar_from_arm\+0xc>
100c: e08fc00c add ip, pc, ip
1010: e12fff1c bx ip
1014: 02000001 .word 0x02000001
diff --git a/ld/testsuite/ld-arm/farcall-arm-thumb.d b/ld/testsuite/ld-arm/farcall-arm-thumb.d
index 3fc02e3bc25..03449964ac3 100644
--- a/ld/testsuite/ld-arm/farcall-arm-thumb.d
+++ b/ld/testsuite/ld-arm/farcall-arm-thumb.d
@@ -7,7 +7,7 @@ Disassembly of section .text:
1004: 00000000 andeq r0, r0, r0
00001008 <__bar_from_arm>:
- 1008: e59fc000 ldr ip, \[pc\] ; 1010 <__bar_from_arm\+0x8>
+ 1008: e59fc000 ldr ip, \[pc\] @ 1010 <__bar_from_arm\+0x8>
100c: e12fff1c bx ip
1010: 02001015 .word 0x02001015
1014: 00000000 .word 0x00000000
diff --git a/ld/testsuite/ld-arm/farcall-data-nacl.d b/ld/testsuite/ld-arm/farcall-data-nacl.d
index 1524fa67aba..2c51fe8ecf9 100644
--- a/ld/testsuite/ld-arm/farcall-data-nacl.d
+++ b/ld/testsuite/ld-arm/farcall-data-nacl.d
@@ -7,8 +7,8 @@ Disassembly of section .text:
#...
0+8010 <__far_veneer>:
-\s*8010:\s+e59fc00c\s+ldr\s+ip, \[pc, #12\]\s+; 8024 <__far_veneer\+0x14>
-\s*8014:\s+e3ccc13f\s+bic\s+ip, ip, #-1073741809\s+; 0xc000000f
+\s*8010:\s+e59fc00c\s+ldr\s+ip, \[pc, #12\]\s+@ 8024 <__far_veneer\+0x14>
+\s*8014:\s+e3ccc13f\s+bic\s+ip, ip, #-1073741809\s+@ 0xc000000f
\s*8018:\s+e12fff1c\s+bx\s+ip
\s*801c:\s+e320f000\s+nop\s+\{0\}
\s*8020:\s+e125be70\s+bkpt\s+0x5be0
diff --git a/ld/testsuite/ld-arm/farcall-data.d b/ld/testsuite/ld-arm/farcall-data.d
index a8b231c5126..b431613caaa 100644
--- a/ld/testsuite/ld-arm/farcall-data.d
+++ b/ld/testsuite/ld-arm/farcall-data.d
@@ -7,7 +7,7 @@ Disassembly of section .text:
8004: 00000000 andeq r0, r0, r0
00008008 <__far_veneer>:
- 8008: e51ff004 ldr pc, \[pc, #-4\] ; 800c <__far_veneer\+0x4>
+ 8008: e51ff004 ldr pc, \[pc, #-4\] @ 800c <__far_veneer\+0x4>
800c: 12340000 \.word 0x12340000
00008010 <after>:
diff --git a/ld/testsuite/ld-arm/farcall-group-limit.d b/ld/testsuite/ld-arm/farcall-group-limit.d
index 204dcd8120f..143896f18d4 100644
--- a/ld/testsuite/ld-arm/farcall-group-limit.d
+++ b/ld/testsuite/ld-arm/farcall-group-limit.d
@@ -8,7 +8,7 @@ Disassembly of section .text:
1004: 00000000 andeq r0, r0, r0
00001008 <__bar_veneer>:
- 1008: e51ff004 ldr pc, \[pc, #-4\] ; 100c <__bar_veneer\+0x4>
+ 1008: e51ff004 ldr pc, \[pc, #-4\] @ 100c <__bar_veneer\+0x4>
100c: 02003020 .word 0x02003020
00001010 <myfunc>:
diff --git a/ld/testsuite/ld-arm/farcall-group-size2.d b/ld/testsuite/ld-arm/farcall-group-size2.d
index 26283343a4d..17bab09908e 100644
--- a/ld/testsuite/ld-arm/farcall-group-size2.d
+++ b/ld/testsuite/ld-arm/farcall-group-size2.d
@@ -8,12 +8,12 @@ Disassembly of section .text:
1004: eb000002 bl 1014 <__bar2_veneer>
00001008 <__bar_from_arm>:
- 1008: e59fc000 ldr ip, \[pc\] ; 1010 <__bar_from_arm\+0x8>
+ 1008: e59fc000 ldr ip, \[pc\] @ 1010 <__bar_from_arm\+0x8>
100c: e12fff1c bx ip
1010: 02003021 .word 0x02003021
00001014 <__bar2_veneer>:
- 1014: e51ff004 ldr pc, \[pc, #-4\] ; 1018 <__bar2_veneer\+0x4>
+ 1014: e51ff004 ldr pc, \[pc, #-4\] @ 1018 <__bar2_veneer\+0x4>
1018: 02003024 .word 0x02003024
101c: 00000000 .word 0x00000000
@@ -24,17 +24,17 @@ Disassembly of section .text:
102c: 00000000 andeq r0, r0, r0
00001030 <__bar4_from_arm>:
- 1030: e59fc000 ldr ip, \[pc\] ; 1038 <__bar4_from_arm\+0x8>
+ 1030: e59fc000 ldr ip, \[pc\] @ 1038 <__bar4_from_arm\+0x8>
1034: e12fff1c bx ip
1038: 0200302d .word 0x0200302d
0000103c <__bar5_from_arm>:
- 103c: e59fc000 ldr ip, \[pc\] ; 1044 <__bar5_from_arm\+0x8>
+ 103c: e59fc000 ldr ip, \[pc\] @ 1044 <__bar5_from_arm\+0x8>
1040: e12fff1c bx ip
1044: 0200302f .word 0x0200302f
00001048 <__bar3_veneer>:
- 1048: e51ff004 ldr pc, \[pc, #-4\] ; 104c <__bar3_veneer\+0x4>
+ 1048: e51ff004 ldr pc, \[pc, #-4\] @ 104c <__bar3_veneer\+0x4>
104c: 02003028 .word 0x02003028
...
diff --git a/ld/testsuite/ld-arm/farcall-group.d b/ld/testsuite/ld-arm/farcall-group.d
index 2d76e1bf0bf..accc091f541 100644
--- a/ld/testsuite/ld-arm/farcall-group.d
+++ b/ld/testsuite/ld-arm/farcall-group.d
@@ -14,26 +14,26 @@ Disassembly of section .text:
+[0-9a-f]+: 00000000 andeq r0, r0, r0
[0-9a-f]+ <__bar4_from_arm>:
- +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar4_from_arm\+0x8>
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] @ [0-9a-f]+ <__bar4_from_arm\+0x8>
+[0-9a-f]+: e12fff1c bx ip
+[0-9a-f]+: 0200302d .word 0x0200302d
[0-9a-f]+ <__bar2_veneer>:
- +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; [0-9a-f]+ <__bar2_veneer\+0x4>
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] @ [0-9a-f]+ <__bar2_veneer\+0x4>
+[0-9a-f]+: 02003024 .word 0x02003024
[0-9a-f]+ <__bar_from_arm>:
- +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar_from_arm\+0x8>
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] @ [0-9a-f]+ <__bar_from_arm\+0x8>
+[0-9a-f]+: e12fff1c bx ip
+[0-9a-f]+: 02003021 .word 0x02003021
[0-9a-f]+ <__bar5_from_arm>:
- +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar5_from_arm\+0x8>
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] @ [0-9a-f]+ <__bar5_from_arm\+0x8>
+[0-9a-f]+: e12fff1c bx ip
+[0-9a-f]+: 0200302f .word 0x0200302f
[0-9a-f]+ <__bar3_veneer>:
- +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; [0-9a-f]+ <__bar3_veneer\+0x4>
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] @ [0-9a-f]+ <__bar3_veneer\+0x4>
+[0-9a-f]+: 02003028 .word 0x02003028
...
diff --git a/ld/testsuite/ld-arm/farcall-mix.d b/ld/testsuite/ld-arm/farcall-mix.d
index ffeffb935b1..3fb6eb25955 100644
--- a/ld/testsuite/ld-arm/farcall-mix.d
+++ b/ld/testsuite/ld-arm/farcall-mix.d
@@ -12,23 +12,23 @@ Disassembly of section .text:
+[0-9a-f]+: 00000000 andeq r0, r0, r0
[0-9a-f]+ <__bar_from_arm>:
- +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar_from_arm\+0x8>
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] @ [0-9a-f]+ <__bar_from_arm\+0x8>
+[0-9a-f]+: e12fff1c bx ip
+[0-9a-f]+: 02002021 .word 0x02002021
[0-9a-f]+ <__bar3_veneer>:
- +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; [0-9a-f]+ <__bar3_veneer\+0x4>
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] @ [0-9a-f]+ <__bar3_veneer\+0x4>
+[0-9a-f]+: 02002028 .word 0x02002028
[0-9a-f]+ <__bar5_from_arm>:
- +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar5_from_arm\+0x8>
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] @ [0-9a-f]+ <__bar5_from_arm\+0x8>
+[0-9a-f]+: e12fff1c bx ip
+[0-9a-f]+: 0200202f .word 0x0200202f
[0-9a-f]+ <__bar4_from_arm>:
- +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar4_from_arm\+0x8>
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] @ [0-9a-f]+ <__bar4_from_arm\+0x8>
+[0-9a-f]+: e12fff1c bx ip
+[0-9a-f]+: 0200202d .word 0x0200202d
[0-9a-f]+ <__bar2_veneer>:
- +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; [0-9a-f]+ <__bar2_veneer\+0x4>
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] @ [0-9a-f]+ <__bar2_veneer\+0x4>
+[0-9a-f]+: 02002024 .word 0x02002024
...
diff --git a/ld/testsuite/ld-arm/farcall-mix2.d b/ld/testsuite/ld-arm/farcall-mix2.d
index 192a2a071a8..bd5510e1455 100644
--- a/ld/testsuite/ld-arm/farcall-mix2.d
+++ b/ld/testsuite/ld-arm/farcall-mix2.d
@@ -8,11 +8,11 @@ Disassembly of section .text:
+[0-9a-f]+: eb000002 bl [0-9a-f]+ <__bar2_veneer>
[0-9a-f]+ <__bar_from_arm>:
- +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar_from_arm\+0x8>
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] @ [0-9a-f]+ <__bar_from_arm\+0x8>
+[0-9a-f]+: e12fff1c bx ip
+[0-9a-f]+: 02003021 .word 0x02003021
[0-9a-f]+ <__bar2_veneer>:
- +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; [0-9a-f]+ <__bar2_veneer\+0x4>
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] @ [0-9a-f]+ <__bar2_veneer\+0x4>
+[0-9a-f]+: 02003024 .word 0x02003024
+[0-9a-f]+: 00000000 .word 0x00000000
Disassembly of section .mytext:
@@ -24,16 +24,16 @@ Disassembly of section .mytext:
+[0-9a-f]+: 00000000 andeq r0, r0, r0
[0-9a-f]+ <__bar3_veneer>:
- +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; [0-9a-f]+ <__bar3_veneer\+0x4>
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] @ [0-9a-f]+ <__bar3_veneer\+0x4>
+[0-9a-f]+: 02003028 .word 0x02003028
[0-9a-f]+ <__bar4_from_arm>:
- +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar4_from_arm\+0x8>
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] @ [0-9a-f]+ <__bar4_from_arm\+0x8>
+[0-9a-f]+: e12fff1c bx ip
+[0-9a-f]+: 0200302d .word 0x0200302d
[0-9a-f]+ <__bar5_from_arm>:
- +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar5_from_arm\+0x8>
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] @ [0-9a-f]+ <__bar5_from_arm\+0x8>
+[0-9a-f]+: e12fff1c bx ip
+[0-9a-f]+: 0200302f .word 0x0200302f
...
diff --git a/ld/testsuite/ld-arm/farcall-mixed-app-v5.d b/ld/testsuite/ld-arm/farcall-mixed-app-v5.d
index af4419874a5..ca83b24ad16 100644
--- a/ld/testsuite/ld-arm/farcall-mixed-app-v5.d
+++ b/ld/testsuite/ld-arm/farcall-mixed-app-v5.d
@@ -7,18 +7,18 @@ start address 0x.*
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.* <lib_func2@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.* <lib_func1@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
@@ -31,18 +31,18 @@ Disassembly of section .text:
.*: ebfffff1 bl .* <lib_func2@plt>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <app_tfunc_close>:
.*: b500 push {lr}
.*: f7ff efdc blx .* <lib_func2@plt>
.*: bd00 pop {pc}
.*: 4770 bx lr
- .*: 46c0 nop ; \(mov r8, r8\)
+ .*: 46c0 nop @ \(mov r8, r8\)
#...
.* <__app_func_veneer>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__app_func_veneer\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ .* <__app_func_veneer\+0x4>
.*: 02100000 .word 0x02100000
Disassembly of section .far_arm:
@@ -54,18 +54,18 @@ Disassembly of section .far_arm:
.*: eb00000(7|5) bl .* <__lib_func2_veneer>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <app_func2>:
.*: e12fff1e bx lr
#...
.* <__lib_func(1|2)_veneer>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func(1|2)_veneer\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ .* <__lib_func(1|2)_veneer\+0x4>
.*: 000081(e8|dc) .word 0x000081(e8|dc)
.* <__lib_func(2|1)_veneer>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func(2|1)_veneer\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ .* <__lib_func(2|1)_veneer\+0x4>
.*: 000081(dc|e8) .word 0x000081(dc|e8)
Disassembly of section .far_thumb:
@@ -75,9 +75,9 @@ Disassembly of section .far_thumb:
.*: f000 e806 blx .* <__lib_func2_from_thumb>
.*: bd00 pop {pc}
.*: 4770 bx lr
- .*: 46c0 nop ; \(mov r8, r8\)
+ .*: 46c0 nop @ \(mov r8, r8\)
#...
.* <__lib_func2_from_thumb>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; 2200014 <__lib_func2_from_thumb\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ 2200014 <__lib_func2_from_thumb\+0x4>
.*: 000081dc .word 0x000081dc
diff --git a/ld/testsuite/ld-arm/farcall-mixed-app.d b/ld/testsuite/ld-arm/farcall-mixed-app.d
index 0160f46d3a4..7070dcbad78 100644
--- a/ld/testsuite/ld-arm/farcall-mixed-app.d
+++ b/ld/testsuite/ld-arm/farcall-mixed-app.d
@@ -7,8 +7,8 @@ start address 0x.*
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
@@ -16,11 +16,11 @@ Disassembly of section .plt:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.* <lib_func1@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
@@ -33,18 +33,18 @@ Disassembly of section .text:
.*: ebfffff2 bl .* <lib_func2@plt\+0x4>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <app_tfunc_close>:
.*: b500 push {lr}
.*: f7ff ffdb bl 81dc <lib_func2@plt>
.*: bd00 pop {pc}
.*: 4770 bx lr
- .*: 46c0 nop ; \(mov r8, r8\)
+ .*: 46c0 nop @ \(mov r8, r8\)
#...
.* <__app_func_veneer>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; 8234 <__app_func_veneer\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ 8234 <__app_func_veneer\+0x4>
.*: 02100000 .word 0x02100000
Disassembly of section .far_arm:
@@ -56,18 +56,18 @@ Disassembly of section .far_arm:
.*: eb00000(7|5) bl .* <__lib_func2_veneer>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <app_func2>:
.*: e12fff1e bx lr
#...
.* <__lib_func(1|2)_veneer>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func(1|2)_veneer\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ .* <__lib_func(1|2)_veneer\+0x4>
.*: 000081e(c|0) .word 0x000081e(c|0)
.* <__lib_func(2|1)_veneer>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func(2|1)_veneer\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ .* <__lib_func(2|1)_veneer\+0x4>
.*: 000081e(0|c) .word 0x000081e(0|c)
Disassembly of section .far_thumb:
@@ -77,12 +77,12 @@ Disassembly of section .far_thumb:
.*: f000 f805 bl .* <__lib_func2_from_thumb>
.*: bd00 pop {pc}
.*: 4770 bx lr
- .*: 46c0 nop ; \(mov r8, r8\)
+ .*: 46c0 nop @ \(mov r8, r8\)
#...
.* <__lib_func2_from_thumb>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
- .*: e51ff004 ldr pc, \[pc, #-4\] ; 2200018 <__lib_func2_from_thumb\+0x8>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ 2200018 <__lib_func2_from_thumb\+0x8>
.*: 000081e0 .word 0x000081e0
.*: 00000000 .word 0x00000000
diff --git a/ld/testsuite/ld-arm/farcall-mixed-app2.d b/ld/testsuite/ld-arm/farcall-mixed-app2.d
index 0c701485152..ff6bc27ddc7 100644
--- a/ld/testsuite/ld-arm/farcall-mixed-app2.d
+++ b/ld/testsuite/ld-arm/farcall-mixed-app2.d
@@ -7,8 +7,8 @@ start address 0x.*
Disassembly of section .plt:
.* <.*>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
@@ -16,11 +16,11 @@ Disassembly of section .plt:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.* <lib_func1@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
@@ -33,18 +33,18 @@ Disassembly of section .text:
.*: ebfffff2 bl .* <lib_func2@plt\+0x4>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <app_tfunc_close>:
.*: b500 push {lr}
.*: f7ff efde blx 81e0 <lib_func2@plt\+0x4>
.*: bd00 pop {pc}
.*: 4770 bx lr
- .*: 46c0 nop ; \(mov r8, r8\)
+ .*: 46c0 nop @ \(mov r8, r8\)
#...
.* <__app_func_veneer>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; 8234 <__app_func_veneer\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ 8234 <__app_func_veneer\+0x4>
.*: 02100000 .word 0x02100000
Disassembly of section .mid_thumb:
@@ -57,7 +57,7 @@ Disassembly of section .mid_thumb:
.* <__lib_func2_from_thumb>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
- .*: e51ff004 ldr pc, \[pc, #-4\] ; 10081e8 <__lib_func2_from_thumb\+0x8>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ 10081e8 <__lib_func2_from_thumb\+0x8>
.*: 000081e0 .word 0x000081e0
.*: 00000000 .word 0x00000000
@@ -70,18 +70,18 @@ Disassembly of section .far_arm:
.*: eb000007 bl .* <__lib_func2_veneer>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <app_func2>:
.*: e12fff1e bx lr
#...
.* <__lib_func1_veneer>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func1_veneer\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ .* <__lib_func1_veneer\+0x4>
.*: 000081ec .word 0x000081ec
.* <__lib_func2_veneer>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func2_veneer\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ .* <__lib_func2_veneer\+0x4>
.*: 000081e0 .word 0x000081e0
Disassembly of section .far_thumb:
@@ -91,9 +91,9 @@ Disassembly of section .far_thumb:
.*: f000 e806 blx .* <__lib_func2_from_thumb>
.*: bd00 pop {pc}
.*: 4770 bx lr
- .*: 46c0 nop ; \(mov r8, r8\)
+ .*: 46c0 nop @ \(mov r8, r8\)
#...
.* <__lib_func2_from_thumb>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; 2200014 <__lib_func2_from_thumb\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ 2200014 <__lib_func2_from_thumb\+0x4>
.*: 000081e0 .word 0x000081e0
diff --git a/ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d b/ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d
index 1b15879b253..6e2fbc937af 100644
--- a/ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d
+++ b/ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d
@@ -6,8 +6,8 @@ start address 0x.*
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .* .word .*
@@ -15,26 +15,26 @@ Disassembly of section .plt:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
- .*: e5bcf.* ldr pc, \[ip, #.*\]! ; .*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
+ .*: e5bcf.* ldr pc, \[ip, #.*\]! @ .*
.* <app_func_weak@plt>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
- .*: e5bcf.* ldr pc, \[ip, #.*\]! ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
+ .*: e5bcf.* ldr pc, \[ip, #.*\]! @ 0x.*
.* <lib_func3@plt>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
- .*: e5bcf.* ldr pc, \[ip, #.*\]! ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
+ .*: e5bcf.* ldr pc, \[ip, #.*\]! @ 0x.*
.* <lib_func4@plt>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
- .*: e5bcf.* ldr pc, \[ip, #.*\]! ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
+ .*: e5bcf.* ldr pc, \[ip, #.*\]! @ 0x.*
Disassembly of section .text:
@@ -60,28 +60,28 @@ Disassembly of section .text:
.* <__app_func_from_thumb>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
- .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_from_thumb\+0xc>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__app_func_from_thumb\+0xc>
.*: e08cf00f add pc, ip, pc
.*: feffff.. .word 0xfeffff..
.* <__lib_func4_from_thumb>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
- .*: e59fc000 ldr ip, \[pc\] ; .* <__lib_func4_from_thumb\+0xc>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__lib_func4_from_thumb\+0xc>
.*: e08cf00f add pc, ip, pc
.*: feffff.. .word 0xfeffff..
.* <__app_func_weak_from_thumb>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
- .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_weak_from_thumb\+0xc>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__app_func_weak_from_thumb\+0xc>
.*: e08cf00f add pc, ip, pc
.*: feffff.. .word 0xfeffff..
.* <__lib_func3_from_thumb>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
- .*: e59fc000 ldr ip, \[pc\] ; .* <__lib_func3_from_thumb\+0xc>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__lib_func3_from_thumb\+0xc>
.*: e08cf00f add pc, ip, pc
.*: feffff.. .word 0xfeffff..
...
@@ -95,25 +95,25 @@ Disassembly of section .text:
.* <__app_func_weak_from_thumb>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
- .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_weak_from_thumb\+0xc>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__app_func_weak_from_thumb\+0xc>
.*: e08cf00f add pc, ip, pc
.*: fdffff34 .word 0xfdffff34
.* <__app_func_from_thumb>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
- .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_from_thumb\+0xc>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__app_func_from_thumb\+0xc>
.*: e08cf00f add pc, ip, pc
.*: fdffff14 .word 0xfdffff14
.* <lib_func3>:
- .*: e59fc004 ldr ip, \[pc, #4\] ; .* <lib_func3\+0xc>
+ .*: e59fc004 ldr ip, \[pc, #4\] @ .* <lib_func3\+0xc>
.*: e08cc00f add ip, ip, pc
.*: e12fff1c bx ip
.*: ffffffc5 .word 0xffffffc5
.* <lib_func2>:
- .*: e59fc004 ldr ip, \[pc, #4\] ; .* <lib_func2\+0xc>
+ .*: e59fc004 ldr ip, \[pc, #4\] @ .* <lib_func2\+0xc>
.*: e08cc00f add ip, ip, pc
.*: e12fff1c bx ip
.*: feffff55 .word 0xfeffff55
diff --git a/ld/testsuite/ld-arm/farcall-mixed-lib.d b/ld/testsuite/ld-arm/farcall-mixed-lib.d
index ef214287f42..3925e7ddfd3 100644
--- a/ld/testsuite/ld-arm/farcall-mixed-lib.d
+++ b/ld/testsuite/ld-arm/farcall-mixed-lib.d
@@ -6,26 +6,26 @@ start address 0x.*
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.* <app_func@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.* <app_func_weak@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.* <lib_func3@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.* <lib_func4@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
@@ -51,22 +51,22 @@ Disassembly of section .text:
#...
.* <__lib_func3_from_thumb>:
- .*: e59fc000 ldr ip, \[pc\] ; .* <__lib_func3_from_thumb\+0x8>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__lib_func3_from_thumb\+0x8>
.*: e08ff00c add pc, pc, ip
.*: feffff.. .word 0xfeffff..
.* <__app_func_weak_from_thumb>:
- .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_weak_from_thumb\+0x8>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__app_func_weak_from_thumb\+0x8>
.*: e08ff00c add pc, pc, ip
.*: feffff.. .word 0xfeffff..
.* <__lib_func4_from_thumb>:
- .*: e59fc000 ldr ip, \[pc\] ; .* <__lib_func4_from_thumb\+0x8>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__lib_func4_from_thumb\+0x8>
.*: e08ff00c add pc, pc, ip
.*: feffff.. .word 0xfeffff..
.* <__app_func_from_thumb>:
- .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_from_thumb\+0x8>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__app_func_from_thumb\+0x8>
.*: e08ff00c add pc, pc, ip
.*: feffff.. .word 0xfeffff..
...
@@ -78,12 +78,12 @@ Disassembly of section .text:
#...
.* <__app_func_weak_from_thumb>:
- .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_weak_from_thumb\+0x8>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__app_func_weak_from_thumb\+0x8>
.*: e08ff00c add pc, pc, ip
.*: fdffff40 .word 0xfdffff40
.* <__app_func_from_thumb>:
- .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_from_thumb\+0x8>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__app_func_from_thumb\+0x8>
.*: e08ff00c add pc, pc, ip
.*: fdffff28 .word 0xfdffff28
...
diff --git a/ld/testsuite/ld-arm/farcall-thumb-arm-blx-pic-veneer.d b/ld/testsuite/ld-arm/farcall-thumb-arm-blx-pic-veneer.d
index ba103568c58..fec54478d6f 100644
--- a/ld/testsuite/ld-arm/farcall-thumb-arm-blx-pic-veneer.d
+++ b/ld/testsuite/ld-arm/farcall-thumb-arm-blx-pic-veneer.d
@@ -8,7 +8,7 @@ Disassembly of section .text:
1f01014: f0ff effe blx 2001014 <bar>
01f01018 <__bar_from_thumb>:
- 1f01018: e59fc000 ldr ip, \[pc\] ; 1f01020 <__bar_from_thumb\+0x8>
+ 1f01018: e59fc000 ldr ip, \[pc\] @ 1f01020 <__bar_from_thumb\+0x8>
1f0101c: e08ff00c add pc, pc, ip
1f01020: 000ffff0 .word 0x000ffff0
1f01024: 00000000 .word 0x00000000
diff --git a/ld/testsuite/ld-arm/farcall-thumb-arm-blx.d b/ld/testsuite/ld-arm/farcall-thumb-arm-blx.d
index 4a2b36aeb5d..e3693545f1c 100644
--- a/ld/testsuite/ld-arm/farcall-thumb-arm-blx.d
+++ b/ld/testsuite/ld-arm/farcall-thumb-arm-blx.d
@@ -8,7 +8,7 @@ Disassembly of section .text:
1f01014: f0ff effe blx 2001014 <bar>
01f01018 <__bar_from_thumb>:
- 1f01018: e51ff004 ldr pc, \[pc, #-4\] ; 1f0101c <__bar_from_thumb\+0x4>
+ 1f01018: e51ff004 ldr pc, \[pc, #-4\] @ 1f0101c <__bar_from_thumb\+0x4>
1f0101c: 02001014 .word 0x02001014
Disassembly of section .foo:
diff --git a/ld/testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d b/ld/testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d
index f96d467cea2..d3fa40bc13f 100644
--- a/ld/testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d
+++ b/ld/testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
01f01018 <__bar_from_thumb>:
1f01018: 4778 bx pc
1f0101a: e7fd b.n .+ <.+>
- 1f0101c: e59fc000 ldr ip, \[pc\] ; 1f01024 <__bar_from_thumb\+0xc>
+ 1f0101c: e59fc000 ldr ip, \[pc\] @ 1f01024 <__bar_from_thumb\+0xc>
1f01020: e08cf00f add pc, ip, pc
1f01024: 000fffec .word 0x000fffec
diff --git a/ld/testsuite/ld-arm/farcall-thumb-arm.d b/ld/testsuite/ld-arm/farcall-thumb-arm.d
index d62649d838a..84ec1afb2db 100644
--- a/ld/testsuite/ld-arm/farcall-thumb-arm.d
+++ b/ld/testsuite/ld-arm/farcall-thumb-arm.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
01f01018 <__bar_from_thumb>:
1f01018: 4778 bx pc
1f0101a: e7fd b.n .+ <.+>
- 1f0101c: e51ff004 ldr pc, \[pc, #-4\] ; 1f01020 <__bar_from_thumb\+0x8>
+ 1f0101c: e51ff004 ldr pc, \[pc, #-4\] @ 1f01020 <__bar_from_thumb\+0x8>
1f01020: 02001014 .word 0x02001014
01f01024 <__bar_from_thumb>:
diff --git a/ld/testsuite/ld-arm/farcall-thumb-thumb-blx-pic-veneer.d b/ld/testsuite/ld-arm/farcall-thumb-thumb-blx-pic-veneer.d
index 27b208e72bf..c3bf1da9e89 100644
--- a/ld/testsuite/ld-arm/farcall-thumb-thumb-blx-pic-veneer.d
+++ b/ld/testsuite/ld-arm/farcall-thumb-thumb-blx-pic-veneer.d
@@ -8,7 +8,7 @@ Disassembly of section .text:
\.\.\.
00001008 <__bar_veneer>:
- 1008: e59fc004 ldr ip, \[pc, #4\] ; 1014 <__bar_veneer\+0xc>
+ 1008: e59fc004 ldr ip, \[pc, #4\] @ 1014 <__bar_veneer\+0xc>
100c: e08fc00c add ip, pc, ip
1010: e12fff1c bx ip
1014: 02000001 .word 0x02000001
diff --git a/ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d b/ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d
index 7998746fd0c..5661c4c80f3 100644
--- a/ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d
+++ b/ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d
@@ -8,7 +8,7 @@ Disassembly of section .text:
\.\.\.
00001008 <__bar_veneer>:
- 1008: e51ff004 ldr pc, \[pc, #-4\] ; 100c <__bar_veneer\+0x4>
+ 1008: e51ff004 ldr pc, \[pc, #-4\] @ 100c <__bar_veneer\+0x4>
100c: 02001015 .word 0x02001015
Disassembly of section .foo:
diff --git a/ld/testsuite/ld-arm/farcall-thumb-thumb-m-no-profile.d b/ld/testsuite/ld-arm/farcall-thumb-thumb-m-no-profile.d
index 7d89b52e020..ee412a1f348 100644
--- a/ld/testsuite/ld-arm/farcall-thumb-thumb-m-no-profile.d
+++ b/ld/testsuite/ld-arm/farcall-thumb-thumb-m-no-profile.d
@@ -9,7 +9,7 @@ Disassembly of section .text:
00001008 <__myfunc_veneer>:
1008: b401 push {r0}
- 100a: 4802 ldr r0, \[pc, #8\] ; \(1014 <__myfunc_veneer\+0xc>\)
+ 100a: 4802 ldr r0, \[pc, #8\] @ \(1014 <__myfunc_veneer\+0xc>\)
100c: 4684 mov ip, r0
100e: bc01 pop {r0}
1010: 4760 bx ip
diff --git a/ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d b/ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d
index 974c1e9c416..40c25110102 100644
--- a/ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d
+++ b/ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d
@@ -9,7 +9,7 @@ Disassembly of section .text:
00001008 <__bar_veneer>:
1008: b401 push {r0}
- 100a: 4802 ldr r0, \[pc, #8\] ; \(1014 <__bar_veneer\+0xc>\)
+ 100a: 4802 ldr r0, \[pc, #8\] @ \(1014 <__bar_veneer\+0xc>\)
100c: 46fc mov ip, pc
100e: 4484 add ip, r0
1010: bc01 pop {r0}
diff --git a/ld/testsuite/ld-arm/farcall-thumb-thumb-m.d b/ld/testsuite/ld-arm/farcall-thumb-thumb-m.d
index e63b3f8fdf6..9316075b23f 100644
--- a/ld/testsuite/ld-arm/farcall-thumb-thumb-m.d
+++ b/ld/testsuite/ld-arm/farcall-thumb-thumb-m.d
@@ -9,7 +9,7 @@ Disassembly of section .text:
00001008 <__bar_veneer>:
1008: b401 push {r0}
- 100a: 4802 ldr r0, \[pc, #8\] ; \(1014 <__bar_veneer\+0xc>\)
+ 100a: 4802 ldr r0, \[pc, #8\] @ \(1014 <__bar_veneer\+0xc>\)
100c: 4684 mov ip, r0
100e: bc01 pop {r0}
1010: 4760 bx ip
diff --git a/ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d b/ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d
index 0b7184bba2c..6174c648e76 100644
--- a/ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d
+++ b/ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
00001008 <__bar_veneer>:
1008: 4778 bx pc
100a: e7fd b.n .+ <.+>
- 100c: e59fc004 ldr ip, \[pc, #4\] ; 1018 <__bar_veneer\+0x10>
+ 100c: e59fc004 ldr ip, \[pc, #4\] @ 1018 <__bar_veneer\+0x10>
1010: e08fc00c add ip, pc, ip
1014: e12fff1c bx ip
1018: 01fffffd .word 0x01fffffd
diff --git a/ld/testsuite/ld-arm/farcall-thumb-thumb.d b/ld/testsuite/ld-arm/farcall-thumb-thumb.d
index 0d9a898eff4..7680ce2ff21 100644
--- a/ld/testsuite/ld-arm/farcall-thumb-thumb.d
+++ b/ld/testsuite/ld-arm/farcall-thumb-thumb.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
00001008 <__bar_veneer>:
1008: 4778 bx pc
100a: e7fd b.n .+ <.+>
- 100c: e59fc000 ldr ip, \[pc\] ; 1014 <__bar_veneer\+0xc>
+ 100c: e59fc000 ldr ip, \[pc\] @ 1014 <__bar_veneer\+0xc>
1010: e12fff1c bx ip
1014: 02001015 .word 0x02001015
Disassembly of section .foo:
diff --git a/ld/testsuite/ld-arm/farcall-thumb2-purecode.d b/ld/testsuite/ld-arm/farcall-thumb2-purecode.d
index 2a62fe4cdd4..451832678e9 100644
--- a/ld/testsuite/ld-arm/farcall-thumb2-purecode.d
+++ b/ld/testsuite/ld-arm/farcall-thumb2-purecode.d
@@ -13,7 +13,7 @@ Disassembly of section .foo:
\.\.\.
02001028 <__bar_veneer>:
- 2001028: f241 0c01 movw ip, #4097 ; 0x1001
+ 2001028: f241 0c01 movw ip, #4097 @ 0x1001
200102c: f2c0 0c00 movt ip, #0
2001030: 4760 bx ip
2001032: 0000 movs r0, r0
diff --git a/ld/testsuite/ld-arm/farcall-thumb2-thumb2-m.d b/ld/testsuite/ld-arm/farcall-thumb2-thumb2-m.d
index 58099417943..45133ec2d58 100644
--- a/ld/testsuite/ld-arm/farcall-thumb2-thumb2-m.d
+++ b/ld/testsuite/ld-arm/farcall-thumb2-thumb2-m.d
@@ -8,7 +8,7 @@ Disassembly of section .text:
\.\.\.
00001008 <__bar_veneer>:
- 1008: f85f f000 ldr.w pc, \[pc\] ; 100c <__bar_veneer\+0x4>
+ 1008: f85f f000 ldr.w pc, \[pc\] @ 100c <__bar_veneer\+0x4>
100c: 02001015 .word 0x02001015
Disassembly of section .foo:
diff --git a/ld/testsuite/ld-arm/fdpic-main-m.d b/ld/testsuite/ld-arm/fdpic-main-m.d
index ed0f41a24cc..ada628b4f5f 100644
--- a/ld/testsuite/ld-arm/fdpic-main-m.d
+++ b/ld/testsuite/ld-arm/fdpic-main-m.d
@@ -7,23 +7,23 @@ start address 0x.*
Disassembly of section .plt:
.* <.plt>:
- .*: f8df c00c ldr.w ip, \[pc, #12\] ; .* <.plt\+0x10>
+ .*: f8df c00c ldr.w ip, \[pc, #12\] @ .* <.plt\+0x10>
.*: eb0c 0c09 add.w ip, ip, r9
.*: f8dc 9004 ldr.w r9, \[ip, #4\]
.*: f8dc f000 ldr.w pc, \[ip\]
.*: 0000000c .word 0x0000000c
.*: 00000000 .word 0x00000000
- .*: f85f c008 ldr.w ip, \[pc, #-8\] ; .* <.plt\+0x14>
+ .*: f85f c008 ldr.w ip, \[pc, #-8\] @ .* <.plt\+0x14>
.*: f84d cd04 str.w ip, \[sp, #-4\]!
.*: f8d9 c004 ldr.w ip, \[r9, #4\]
.*: f8d9 f000 ldr.w pc, \[r9\]
- .*: f8df c00c ldr.w ip, \[pc, #12\] ; .* <.plt\+0x38>
+ .*: f8df c00c ldr.w ip, \[pc, #12\] @ .* <.plt\+0x38>
.*: eb0c 0c09 add.w ip, ip, r9
.*: f8dc 9004 ldr.w r9, \[ip, #4\]
.*: f8dc f000 ldr.w pc, \[ip]
.*: 00000014 .word 0x00000014
.*: 00000008 .word 0x00000008
- .*: f85f c008 ldr.w ip, \[pc, #-8\] ; .* <.plt\+0x3c>
+ .*: f85f c008 ldr.w ip, \[pc, #-8\] @ .* <.plt\+0x3c>
.*: f84d cd04 str.w ip, \[sp, #-4\]!
.*: f8d9 c004 ldr.w ip, \[r9, #4\]
.*: f8d9 f000 ldr.w pc, \[r9\]
@@ -34,8 +34,8 @@ Disassembly of section .text:
.*: f000 b800 b.w .* <main>
.* <main>:
- .*: 4a11 ldr r2, \[pc, #68\] ; .* <main\+0x48>.*
- .*: 4b12 ldr r3, \[pc, #72\] ; .* <main\+0x4c>.*
+ .*: 4a11 ldr r2, \[pc, #68\] @ .* <main\+0x48>.*
+ .*: 4b12 ldr r3, \[pc, #72\] @ .* <main\+0x4c>.*
.*: b570 push {r4, r5, r6, lr}
.*: f859 5002 ldr.w r5, \[r9, r2\]
.*: 464c mov r4, r9
@@ -47,14 +47,14 @@ Disassembly of section .text:
.*: 6828 ldr r0, \[r5, #0\]
.*: 46a1 mov r9, r4
.*: f7ff ffd9 bl .* <.plt\+0x28>
- .*: 4b0b ldr r3, \[pc, #44\] ; .* <main\+0x50>.*
+ .*: 4b0b ldr r3, \[pc, #44\] @ .* <main\+0x50>.*
.*: 46a1 mov r9, r4
.*: 444b add r3, r9
.*: 4618 mov r0, r3
.*: 602b str r3, \[r5, #0\]
.*: 46a1 mov r9, r4
.*: f7ff ffd1 bl .* <.plt\+0x28>
- .*: 4b08 ldr