[PATCH 0/5] RISC-V: Requirements for disassembler optimizations 1 (Tidying part)

[PATCH 0/5] RISC-V: Requirements for disassembler optimizations 1 (Tidying part)

[Tsukasa OI]

Hello,

To improve the core disassembler (both for performance and feature), this
patchset now prepares for it.

This is the part 1 of (planned) 4 part patchsets.

1.  Tidying (you are here)
2.  Reorganization of the disassembler architecture
    (including some small optimizations)
3.  Optimization 1
4.  Optimization 2

Project:
<https://github.com/a4lg/binutils-gdb/wiki/proj_dis_perf_improvements_1>

Batch 1, Part 1 is the only hardly-functional part of the whole patchsets
and considered non-debatable.

-   Adds/fixes some comments
-   Fixes some formatting / typing
-   Removes/makes static some local variables

Again, this is mostly a tidying patchset.

Thanks,
Tsukasa




Tsukasa OI (5):
  opcodes/riscv-dis.c: Tidying with comments/clarity
  opcodes/riscv-dis.c: Tidying with spacing
  opcodes/riscv-dis.c: Use bool type whenever possible
  opcodes/riscv-dis.c: Make XLEN variable static
  opcodes/riscv-dis.c: Remove last_map_state

 opcodes/riscv-dis.c | 40 +++++++++++++++++++++++++++-------------
 1 file changed, 27 insertions(+), 13 deletions(-)


base-commit: 4cbfd0daabd68516651ee37a19d0e24ca4789ea3
-- 
2.34.1

[PATCH 1/5] opcodes/riscv-dis.c: Tidying with comments/clarity

[Tsukasa OI]

Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.

First, we need to clarify the roles of variables and code portions.

opcodes/ChangeLog:

	* riscv-dis.c (xlen): Move before default_isa_spec. Add comment.
	(default_isa_spec, default_priv_spec): Add comment.
	(riscv_gpr_names, riscv_fpr_names): Likewise.
	(parse_riscv_dis_option_without_args): Likewise.
	(parse_riscv_dis_option, parse_riscv_dis_options): Likewise.
	(maybe_print_address): Likewise.
	(riscv_disassemble_insn): Fix comment about the Zfinx "extension".
	Add comment about the riscv_multi_subset_supports call.
---
 opcodes/riscv-dis.c | 25 +++++++++++++++++++++----
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 27a6bfe2283..2d1faf26eb3 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -32,10 +32,15 @@
 #include <stdint.h>
 #include <ctype.h>
 
+/* Current XLEN for the disassembler.  */
+unsigned xlen = 0;
+
+/* Default ISA specification version (constant as of now).  */
 static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_DRAFT - 1;
-static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
 
-unsigned xlen = 0;
+/* Default privileged specification
+   (as specified by the ELF attributes or the `priv-spec' option).  */
+static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
 
 static riscv_subset_list_t riscv_subsets;
 static riscv_parse_subset_t riscv_rps_dis =
@@ -61,12 +66,16 @@ static int last_map_symbol = -1;
 static bfd_vma last_stop_offset = 0;
 enum riscv_seg_mstate last_map_state;
 
+/* Register names as used by the disassembler.  */
 static const char * const *riscv_gpr_names;
 static const char * const *riscv_fpr_names;
 
 /* If set, disassemble as most general instruction.  */
 static int no_aliases;
 
+
+/* Set default RISC-V disassembler options.  */
+
 static void
 set_default_riscv_dis_options (void)
 {
@@ -75,6 +84,8 @@ set_default_riscv_dis_options (void)
   no_aliases = 0;
 }
 
+/* Parse RISC-V disassembler option (without arguments).  */
+
 static bool
 parse_riscv_dis_option_without_args (const char *option)
 {
@@ -90,6 +101,8 @@ parse_riscv_dis_option_without_args (const char *option)
   return true;
 }
 
+/* Parse RISC-V disassembler option (possibly with arguments).  */
+
 static void
 parse_riscv_dis_option (const char *option)
 {
@@ -143,6 +156,8 @@ parse_riscv_dis_option (const char *option)
     }
 }
 
+/* Parse RISC-V disassembler options.  */
+
 static void
 parse_riscv_dis_options (const char *opts_in)
 {
@@ -170,6 +185,8 @@ arg_print (struct disassemble_info *info, unsigned long val,
   (*info->fprintf_styled_func) (info->stream, dis_style_text, "%s", s);
 }
 
+/* If we need to print an address, set its value and state.  */
+
 static void
 maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
 		     int wide)
@@ -697,7 +714,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 	  xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
 	}
 
-      /* If arch has ZFINX flags, use gpr for disassemble.  */
+      /* If arch has the Zfinx extension, replace FPR with GPR.  */
       if(riscv_subset_supports (&riscv_rps_dis, "zfinx"))
 	riscv_fpr_names = riscv_gpr_names;
 
@@ -712,7 +729,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 	  /* Is this instruction restricted to a certain value of XLEN?  */
 	  if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
 	    continue;
-
+	  /* Is this instruction supported by the current architecture?  */
 	  if (!riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class))
 	    continue;
 
-- 
2.34.1

[PATCH 2/5] opcodes/riscv-dis.c: Tidying with spacing

[Tsukasa OI]

Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.

This commit takes care of improper spacing for code clarity.

opcodes/ChangeLog:

	* riscv-dis.c (riscv_disassemble_insn): Tidying with spacing.
---
 opcodes/riscv-dis.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 2d1faf26eb3..088d0d91080 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -715,7 +715,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 	}
 
       /* If arch has the Zfinx extension, replace FPR with GPR.  */
-      if(riscv_subset_supports (&riscv_rps_dis, "zfinx"))
+      if (riscv_subset_supports (&riscv_rps_dis, "zfinx"))
 	riscv_fpr_names = riscv_gpr_names;
 
       for (; op->name; op++)
-- 
2.34.1

[PATCH 3/5] opcodes/riscv-dis.c: Use bool type whenever possible

[Tsukasa OI]

Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.

This commit replaces uses of int with bool whenever possible.

opcodes/ChangeLog:

	* riscv-dis.c (no_aliases) Change type to bool.
	(set_default_riscv_dis_options): Use boolean.
	(parse_riscv_dis_option_without_args): Likewise.
	(riscv_disassemble_insn): Use boolean keywords.
---
 opcodes/riscv-dis.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 088d0d91080..608670bed7f 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -71,7 +71,7 @@ static const char * const *riscv_gpr_names;
 static const char * const *riscv_fpr_names;
 
 /* If set, disassemble as most general instruction.  */
-static int no_aliases;
+static bool no_aliases = false;
 
 
 /* Set default RISC-V disassembler options.  */
@@ -81,7 +81,7 @@ set_default_riscv_dis_options (void)
 {
   riscv_gpr_names = riscv_gpr_names_abi;
   riscv_fpr_names = riscv_fpr_names_abi;
-  no_aliases = 0;
+  no_aliases = false;
 }
 
 /* Parse RISC-V disassembler option (without arguments).  */
@@ -90,7 +90,7 @@ static bool
 parse_riscv_dis_option_without_args (const char *option)
 {
   if (strcmp (option, "no-aliases") == 0)
-    no_aliases = 1;
+    no_aliases = true;
   else if (strcmp (option, "numeric") == 0)
     {
       riscv_gpr_names = riscv_gpr_names_numeric;
@@ -645,7 +645,7 @@ static int
 riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 {
   const struct riscv_opcode *op;
-  static bool init = 0;
+  static bool init = false;
   static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
   struct riscv_private_data *pd;
   int insnlen;
@@ -659,7 +659,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 	if (!riscv_hash[OP_HASH_IDX (op->match)])
 	  riscv_hash[OP_HASH_IDX (op->match)] = op;
 
-      init = 1;
+      init = true;
     }
 
   if (info->private_data == NULL)
-- 
2.34.1

[PATCH 4/5] opcodes/riscv-dis.c: Make XLEN variable static

[Tsukasa OI]

Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.

Since xlen variable is not (and should not) used outside riscv-dis.c,
this commit makes this variable static.

opcodes/ChangeLog:

	* riscv-dis.c (xlen): Make this variable static.
---
 opcodes/riscv-dis.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 608670bed7f..27e1978d428 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -33,7 +33,7 @@
 #include <ctype.h>
 
 /* Current XLEN for the disassembler.  */
-unsigned xlen = 0;
+static unsigned xlen = 0;
 
 /* Default ISA specification version (constant as of now).  */
 static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_DRAFT - 1;
-- 
2.34.1

[PATCH 5/5] opcodes/riscv-dis.c: Remove last_map_state

[Tsukasa OI]

Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.

This commit removes unused variable last_map_state (set by the
print_insn_riscv function but not read anywhere else).

opcodes/ChangeLog:

	* riscv-dis.c (last_map_state): Remove.
	(print_insn_riscv): Remove setting last_map_state.
---
 opcodes/riscv-dis.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 27e1978d428..daeb1b5fd15 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -64,7 +64,6 @@ struct riscv_private_data
 /* Used for mapping symbols.  */
 static int last_map_symbol = -1;
 static bfd_vma last_stop_offset = 0;
-enum riscv_seg_mstate last_map_state;
 
 /* Register names as used by the disassembler.  */
 static const char * const *riscv_gpr_names;
@@ -1041,8 +1040,6 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info)
     set_default_riscv_dis_options ();
 
   mstate = riscv_search_mapping_symbol (memaddr, info);
-  /* Save the last mapping state.  */
-  last_map_state = mstate;
 
   /* Set the size to dump.  */
   if (mstate == MAP_DATA
-- 
2.34.1

Re: [PATCH 0/5] RISC-V: Requirements for disassembler optimizations 1 (Tidying part)

[Nelson Chu]

On Sat, Oct 8, 2022 at 12:34 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> Hello,
>
> To improve the core disassembler (both for performance and feature), this
> patchset now prepares for it.
>
> This is the part 1 of (planned) 4 part patchsets.
>
> 1.  Tidying (you are here)
> 2.  Reorganization of the disassembler architecture
>     (including some small optimizations)
> 3.  Optimization 1
> 4.  Optimization 2
>
> Project:
> <https://github.com/a4lg/binutils-gdb/wiki/proj_dis_perf_improvements_1>
>
> Batch 1, Part 1 is the only hardly-functional part of the whole patchsets
> and considered non-debatable.
>
> -   Adds/fixes some comments
> -   Fixes some formatting / typing
> -   Removes/makes static some local variables
>
> Again, this is mostly a tidying patchset.
>
> Thanks,
> Tsukasa
>
>
>
>
> Tsukasa OI (5):
>   opcodes/riscv-dis.c: Tidying with comments/clarity
>   opcodes/riscv-dis.c: Tidying with spacing
>   opcodes/riscv-dis.c: Use bool type whenever possible
>   opcodes/riscv-dis.c: Make XLEN variable static
>   opcodes/riscv-dis.c: Remove last_map_state

OK, looks good.  Although I am not sure what optimization you want to
do, at least the tidy patches are always welcome and independent, so
please commit.

Thanks
Nelson

>  opcodes/riscv-dis.c | 40 +++++++++++++++++++++++++++-------------
>  1 file changed, 27 insertions(+), 13 deletions(-)
>
>
> base-commit: 4cbfd0daabd68516651ee37a19d0e24ca4789ea3
> --
> 2.34.1
>