* [PATCH 0/3] RISC-V: Fix CSR accessibility and implications
@ 2022-09-07 5:53 Tsukasa OI
2022-09-07 5:53 ` [PATCH 1/3] RISC-V: Fix vector CSR requirements and imply Tsukasa OI
` (4 more replies)
0 siblings, 5 replies; 17+ messages in thread
From: Tsukasa OI @ 2022-09-07 5:53 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_fix_csr_access_and_imply>
While I'm reorganizing "b-ext*" and "k-ext*" tests (to make sure that they
are able to be removed since there are neither 'B' nor 'K' extensions),
I found something interesting.
If we assemble a file with "csrr a0, seed" (uses "seed" CSR from the 'Zkr'
extension) with "-march=rv32i_zkr", it causes an error to require 'Zicsr'.
Yes, current GNU Binutils does not imply 'Zicsr' from 'Zkr' so that adding
'Zkr' extension alone is not enough to access corresponding CSRs
(current version requires an option like "-march=rv32i_zicsr_zkr").
"k-ext.d" does not give 'Zicsr' either (and does not test the seed CSR) and
adding the line "csrr a0, seed" to this test file resulted the same.
That means something. If an extension adds CSR(s), we should imply 'Zicsr'
from that extension (just like 'F'). So, we have to imply 'Zicsr' from
following extensions:
- 'H'
- 'Zkr'
- 'Zve32x' (I'll talk later)
- 'Smstateen'
- 'Sscofpmf'
- 'Sstc'
'Zkr' is fixed in PATCH 2/3 and 'H' and 'S*' are fixed in PATCH 3/3.
The only remaining extension is 'Zve32x' but I need to talk more to explain
actual changes (specific to vectors) in PATCH 1/3.
On the current version of GNU Binutils, CSRs with CSR_CLASS_V means they
require the 'V' extension. However, there are a few vector subextensions
that implement vector subsets (intended for embedded processors).
- 'Zve64d' (superset of 'Zve64f')
- 'Zve64f' (superset of 'Zve32f' and 'Zve64x')
- 'Zve64x' (superset of 'Zve32x')
- 'Zve32f' (superset of 'Zve32x')
- 'Zve32x'
: Graph: Dependency graph of some vector/FP extensions
:
: +-------> D --------> F -----> Zicsr
: | ^ ^
: | | |
: V ---> Zve64d ---> Zve64f ---> Zve64x
: | |
: V V
: Zve32f ---> Zve32x
: |
: |
: +---> (Zicsr [added in PATCH 1/3])
They also require general purpose vector CSRs (vstart, vl, vtype and vlenb).
So, corresponding CSR_CLASS_V with the 'V' extension is inappropriate
(they should require 'Zve32x' instead, the minimum vector subset).
Remaining CSRs are:
- vxsat
- vxrm
- vcsr
They are related to fixed-point arithmetic and 18.2 "Zve*: Vector Extensions
for Embedded Processors" says:
> All Zve* extensions support all vector fixed-point arithmetic instructions
> (Vector Fixed-Point Arithmetic Instructions), except that vsmul.vv and
> vsmul.vx are not supported for EEW=64 in Zve64*.
So, their minimum requirement shall be also 'Zve32x', not 'V'.
As a consequence, we can conclude that changing requirements of CSR_CLASS_V
from 'V' to 'Zve32x' is sufficient to avoid CSR accessibility warnings.
Also, 'Zve32x' must imply 'Zicsr' (just like the rest) to avoid CSR
instruction errors. This is only effective on 'Zve32x' and 'Zve64x'
because, for instance, 'Zve32f' implies 'F' and 'F' implies 'Zicsr'
(see the graph above).
I didn't rename CSR_CLASS_V to CSR_CLASS_ZVE32X because the name gets
difficult and there's already INSN_CLASS_V (effectively requires 'Zve32x'
with some exceptions).
Tsukasa OI (3):
RISC-V: Fix vector CSR requirements and imply
RISC-V: Imply 'Zicsr' from 'Zkr'
RISC-V: Imply 'Zicsr' from some privileged extensions
bfd/elfxx-riscv.c | 6 +++++
gas/config/tc-riscv.c | 2 +-
gas/testsuite/gas/riscv/csr-version-1p10.l | 28 ++++++++++----------
gas/testsuite/gas/riscv/csr-version-1p11.l | 28 ++++++++++----------
gas/testsuite/gas/riscv/csr-version-1p12.l | 28 ++++++++++----------
gas/testsuite/gas/riscv/csr-version-1p9p1.l | 28 ++++++++++----------
gas/testsuite/gas/riscv/march-imply-h.d | 6 +++++
gas/testsuite/gas/riscv/vector-csrs-zve32f.d | 21 +++++++++++++++
gas/testsuite/gas/riscv/vector-csrs-zve32x.d | 21 +++++++++++++++
gas/testsuite/gas/riscv/vector-csrs-zve64d.d | 21 +++++++++++++++
gas/testsuite/gas/riscv/vector-csrs-zve64f.d | 21 +++++++++++++++
gas/testsuite/gas/riscv/vector-csrs-zve64x.d | 21 +++++++++++++++
gas/testsuite/gas/riscv/vector-csrs.s | 12 +++++++++
gas/testsuite/gas/riscv/zkr.d | 10 +++++++
gas/testsuite/gas/riscv/zkr.s | 2 ++
15 files changed, 198 insertions(+), 57 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/march-imply-h.d
create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32f.d
create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32x.d
create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64d.d
create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64f.d
create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64x.d
create mode 100644 gas/testsuite/gas/riscv/vector-csrs.s
create mode 100644 gas/testsuite/gas/riscv/zkr.d
create mode 100644 gas/testsuite/gas/riscv/zkr.s
base-commit: f555b327d41ed72ffae28caae550f5f86312db43
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 1/3] RISC-V: Fix vector CSR requirements and imply 2022-09-07 5:53 [PATCH 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI @ 2022-09-07 5:53 ` Tsukasa OI 2022-09-07 5:53 ` [PATCH 2/3] RISC-V: Imply 'Zicsr' from 'Zkr' Tsukasa OI ` (3 subsequent siblings) 4 siblings, 0 replies; 17+ messages in thread From: Tsukasa OI @ 2022-09-07 5:53 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils Vector CSRs are also required on smaller vector subsets. It caused assembler errors when only integer-only vector subextensions ('Zve32x'/ 'Zve64x') are enabled. It also caused warnings when CSR checking is enabled on subsets with floating-point arithmetic ('Zve32f'/'Zve64f'/'Zve64d') Not only that the most of vector CSRs are general purpose (and must be accessible for every vector subsets), current minimum vector subset 'Zve32x' requires fixed point arithmetic, making remaining non-general purpose (fixed point arithmetic only) CSRs mandatory for such subsets. So, those CSRs must be accessible from 'Zve32x', not just from 'V'. This commit fixes this issue which caused CSR accessibility warnings. Also, 'Zve32x' does not imply 'Zicsr' so accessing vector CSRs with "-march=rv32i_zve32x" does not work ('Zve64x' does not work as well). This commit fixes this issue by implying 'Zicsr' from 'Zve32x' ('Zve64x' implies 'Zve32x' so adding an implication from 'Zve32x' is sufficient). bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Make 'Zve32x' extension to imply 'Zicsr'. gas/ChangeLog: * config/tc-riscv.c (riscv_csr_address): Change vector CSR requirement from 'V' to 'Zve32x'. * testsuite/gas/riscv/csr-version-1p9p1.l: Change vector CSR requirement from 'V' to 'Zve32x'. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/vector-csrs.s: New test. * testsuite/gas/riscv/vector-csrs-zve32x.d: Likewise. * testsuite/gas/riscv/vector-csrs-zve32f.d: Likewise. * testsuite/gas/riscv/vector-csrs-zve64x.d: Likewise. * testsuite/gas/riscv/vector-csrs-zve64f.d: Likewise. * testsuite/gas/riscv/vector-csrs-zve64d.d: Likewise. --- bfd/elfxx-riscv.c | 1 + gas/config/tc-riscv.c | 2 +- gas/testsuite/gas/riscv/csr-version-1p10.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p11.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p12.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p9p1.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/vector-csrs-zve32f.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve32x.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve64d.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve64f.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve64x.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs.s | 12 +++++++++ 12 files changed, 175 insertions(+), 57 deletions(-) create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32f.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32x.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64d.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64f.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64x.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 8cb3c8d4930..fb742dc9272 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1062,6 +1062,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zve64x", "zve32x", check_implicit_always}, {"zve64x", "zvl64b", check_implicit_always}, {"zve32x", "zvl32b", check_implicit_always}, + {"zve32x", "zicsr", check_implicit_always}, {"zvl65536b", "zvl32768b", check_implicit_always}, {"zvl32768b", "zvl16384b", check_implicit_always}, {"zvl16384b", "zvl8192b", check_implicit_always}, diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 34ce68e8252..df2e201fb74 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -935,7 +935,7 @@ riscv_csr_address (const char *csr_name, extension = "zkr"; break; case CSR_CLASS_V: - extension = "v"; + extension = "zve32x"; break; case CSR_CLASS_SMSTATEEN: case CSR_CLASS_SMSTATEEN_AND_H: diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l index b778453b556..999e9af1520 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p10.l +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l @@ -652,20 +652,20 @@ .*Warning: invalid CSR `fcsr', needs `f' extension .*Warning: invalid CSR `seed', needs `zkr' extension .*Warning: invalid CSR `seed', needs `zkr' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vl,a1' -.*Warning: invalid CSR `vtype', needs `v' extension -.*Warning: invalid CSR `vtype', needs `v' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vtype,a1' -.*Warning: invalid CSR `vlenb', needs `v' extension -.*Warning: invalid CSR `vlenb', needs `v' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vlenb,a1' diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l index 78bae817470..a099e4ecc93 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p11.l +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l @@ -650,20 +650,20 @@ .*Warning: invalid CSR `fcsr', needs `f' extension .*Warning: invalid CSR `seed', needs `zkr' extension .*Warning: invalid CSR `seed', needs `zkr' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vl,a1' -.*Warning: invalid CSR `vtype', needs `v' extension -.*Warning: invalid CSR `vtype', needs `v' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vtype,a1' -.*Warning: invalid CSR `vlenb', needs `v' extension -.*Warning: invalid CSR `vlenb', needs `v' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vlenb,a1' diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l index cb026bb55e0..cf8f2e25634 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p12.l +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l @@ -532,20 +532,20 @@ .*Warning: invalid CSR `fcsr', needs `f' extension .*Warning: invalid CSR `seed', needs `zkr' extension .*Warning: invalid CSR `seed', needs `zkr' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vl,a1' -.*Warning: invalid CSR `vtype', needs `v' extension -.*Warning: invalid CSR `vtype', needs `v' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vtype,a1' -.*Warning: invalid CSR `vlenb', needs `v' extension -.*Warning: invalid CSR `vlenb', needs `v' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vlenb,a1' diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l index 4fac40fb589..5f298c1dda9 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l @@ -678,20 +678,20 @@ .*Warning: invalid CSR `fcsr', needs `f' extension .*Warning: invalid CSR `seed', needs `zkr' extension .*Warning: invalid CSR `seed', needs `zkr' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vl,a1' -.*Warning: invalid CSR `vtype', needs `v' extension -.*Warning: invalid CSR `vtype', needs `v' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vtype,a1' -.*Warning: invalid CSR `vlenb', needs `v' extension -.*Warning: invalid CSR `vlenb', needs `v' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vlenb,a1' diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve32f.d b/gas/testsuite/gas/riscv/vector-csrs-zve32f.d new file mode 100644 index 00000000000..9613915713b --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs-zve32f.d @@ -0,0 +1,21 @@ +#as: -march=rv32i_zve32f -mcsr-check +#source: vector-csrs.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve32x.d b/gas/testsuite/gas/riscv/vector-csrs-zve32x.d new file mode 100644 index 00000000000..a608efbfb0b --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs-zve32x.d @@ -0,0 +1,21 @@ +#as: -march=rv32i_zve32x -mcsr-check +#source: vector-csrs.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64d.d b/gas/testsuite/gas/riscv/vector-csrs-zve64d.d new file mode 100644 index 00000000000..f42e670699a --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64d.d @@ -0,0 +1,21 @@ +#as: -march=rv32i_zve64d -mcsr-check +#source: vector-csrs.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64f.d b/gas/testsuite/gas/riscv/vector-csrs-zve64f.d new file mode 100644 index 00000000000..e88b5a3ff6e --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64f.d @@ -0,0 +1,21 @@ +#as: -march=rv32i_zve64f -mcsr-check +#source: vector-csrs.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64x.d b/gas/testsuite/gas/riscv/vector-csrs-zve64x.d new file mode 100644 index 00000000000..83aa1bba341 --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64x.d @@ -0,0 +1,21 @@ +#as: -march=rv32i_zve64x -mcsr-check +#source: vector-csrs.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/vector-csrs.s b/gas/testsuite/gas/riscv/vector-csrs.s new file mode 100644 index 00000000000..7019a0588ef --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs.s @@ -0,0 +1,12 @@ +target: + csrr a0, vstart + csrw vstart, zero + csrr a0, vxsat + csrwi vxsat, 1 + csrr a0, vxrm + csrwi vxrm, 3 + csrr a0, vcsr + csrwi vcsr, 7 + csrr a0, vl + csrr a0, vtype + csrr a0, vlenb -- 2.34.1 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/3] RISC-V: Imply 'Zicsr' from 'Zkr' 2022-09-07 5:53 [PATCH 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI 2022-09-07 5:53 ` [PATCH 1/3] RISC-V: Fix vector CSR requirements and imply Tsukasa OI @ 2022-09-07 5:53 ` Tsukasa OI 2022-09-07 5:53 ` [PATCH 3/3] RISC-V: Imply 'Zicsr' from some privileged extensions Tsukasa OI ` (2 subsequent siblings) 4 siblings, 0 replies; 17+ messages in thread From: Tsukasa OI @ 2022-09-07 5:53 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils Because the 'Zkr' extension implements a CSR, seed, it requires 'Zicsr' as a prerequisite. On such cases, it's natural to imply required extension. This commit adds Zkr -> Zicsr to the extension implication list. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Imply 'Zicsr' from 'Zkr'. gas/ChangeLog: * testsuite/gas/riscv/zkr.s: Separate test for 'Zkr' extension. * testsuite/gas/riscv/zkr.d: Likewise. --- bfd/elfxx-riscv.c | 1 + gas/testsuite/gas/riscv/zkr.d | 10 ++++++++++ gas/testsuite/gas/riscv/zkr.s | 2 ++ 3 files changed, 13 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zkr.d create mode 100644 gas/testsuite/gas/riscv/zkr.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index fb742dc9272..2e91963bbfb 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1092,6 +1092,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zkn", "zkne", check_implicit_always}, {"zkn", "zknd", check_implicit_always}, {"zkn", "zknh", check_implicit_always}, + {"zkr", "zicsr", check_implicit_always}, {"zks", "zbkb", check_implicit_always}, {"zks", "zbkc", check_implicit_always}, {"zks", "zbkx", check_implicit_always}, diff --git a/gas/testsuite/gas/riscv/zkr.d b/gas/testsuite/gas/riscv/zkr.d new file mode 100644 index 00000000000..d5ebe799040 --- /dev/null +++ b/gas/testsuite/gas/riscv/zkr.d @@ -0,0 +1,10 @@ +#as: -march=rv32i_zkr +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed diff --git a/gas/testsuite/gas/riscv/zkr.s b/gas/testsuite/gas/riscv/zkr.s new file mode 100644 index 00000000000..96a38fbf49f --- /dev/null +++ b/gas/testsuite/gas/riscv/zkr.s @@ -0,0 +1,2 @@ +target: + csrr a0, seed -- 2.34.1 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/3] RISC-V: Imply 'Zicsr' from some privileged extensions 2022-09-07 5:53 [PATCH 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI 2022-09-07 5:53 ` [PATCH 1/3] RISC-V: Fix vector CSR requirements and imply Tsukasa OI 2022-09-07 5:53 ` [PATCH 2/3] RISC-V: Imply 'Zicsr' from 'Zkr' Tsukasa OI @ 2022-09-07 5:53 ` Tsukasa OI 2022-09-07 6:21 ` [PATCH v2 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI 2022-09-07 8:49 ` [PATCH 0/3] RISC-V: Fix CSR accessibility and implications Nelson Chu 4 siblings, 0 replies; 17+ messages in thread From: Tsukasa OI @ 2022-09-07 5:53 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils As 'H', 'Smstateen', 'Sscofpmf' and 'Sstc' define their own CSRs, they implicitly require 'Zicsr' in the process. This commit adds such implicications. gas/ChangeLog: * testsuite/gas/riscv/march-imply-h.d: New test, at least for 'H'. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add 'Zicsr' implicications for privileged extensions 'H', 'Smstateen', 'Sscofpmf' and 'Sstc'. --- bfd/elfxx-riscv.c | 4 ++++ gas/testsuite/gas/riscv/march-imply-h.d | 6 ++++++ 2 files changed, 10 insertions(+) create mode 100644 gas/testsuite/gas/riscv/march-imply-h.d diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 2e91963bbfb..73848f725e6 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1047,6 +1047,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"g", "d", check_implicit_always}, {"g", "zicsr", check_implicit_always}, {"g", "zifencei", check_implicit_always}, + {"h", "zicsr", check_implicit_always}, {"q", "d", check_implicit_always}, {"v", "d", check_implicit_always}, {"v", "zve64d", check_implicit_always}, @@ -1098,6 +1099,9 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zks", "zbkx", check_implicit_always}, {"zks", "zksed", check_implicit_always}, {"zks", "zksh", check_implicit_always}, + {"smstateen", "zicsr", check_implicit_always}, + {"sscofpmf", "zicsr", check_implicit_always}, + {"sstc", "zicsr", check_implicit_always}, {NULL, NULL, NULL} }; diff --git a/gas/testsuite/gas/riscv/march-imply-h.d b/gas/testsuite/gas/riscv/march-imply-h.d new file mode 100644 index 00000000000..04ad9f6c0a5 --- /dev/null +++ b/gas/testsuite/gas/riscv/march-imply-h.d @@ -0,0 +1,6 @@ +#as: -march=rv32ih -march-attr -misa-spec=20191213 -mpriv-spec=1.12 +#readelf: -A +#source: empty.s +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: "rv32i2p1_h1p0_zicsr2p0" -- 2.34.1 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 0/3] RISC-V: Fix CSR accessibility and implications 2022-09-07 5:53 [PATCH 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI ` (2 preceding siblings ...) 2022-09-07 5:53 ` [PATCH 3/3] RISC-V: Imply 'Zicsr' from some privileged extensions Tsukasa OI @ 2022-09-07 6:21 ` Tsukasa OI 2022-09-07 6:21 ` [PATCH v2 1/3] RISC-V: Fix vector CSR requirements and imply Tsukasa OI ` (3 more replies) 2022-09-07 8:49 ` [PATCH 0/3] RISC-V: Fix CSR accessibility and implications Nelson Chu 4 siblings, 4 replies; 17+ messages in thread From: Tsukasa OI @ 2022-09-07 6:21 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils Tracker on GitHub: <https://github.com/a4lg/binutils-gdb/wiki/riscv_fix_csr_access_and_imply> [Changes: v1 -> v2] - PATCH 2/3 - Add "-mcsr-check" option to make sure that seed CSR is accessible with no warnings. - Cover Letter: - Fix references (to "k-ext.s", not "k-ext.d") - Fix dependency graph (Add Zve32f -> F) While I'm reorganizing "b-ext*" and "k-ext*" tests (to make sure that they are able to be removed since there are neither 'B' nor 'K' extensions), I found something interesting. If we assemble a file with "csrr a0, seed" (uses "seed" CSR from the 'Zkr' extension) with "-march=rv32i_zkr", it causes an error to require 'Zicsr'. Yes, current GNU Binutils does not imply 'Zicsr' from 'Zkr' so that adding 'Zkr' extension alone is not enough to access corresponding CSRs (current version requires an option like "-march=rv32i_zicsr_zkr"). "k-ext.d" does not give 'Zicsr' either (and does not test the seed CSR) and adding the line "csrr a0, seed" to the corresponding test file ("k-ext.s") resulted the same. That means something. If an extension adds CSR(s), we should imply 'Zicsr' from that extension (just like 'F'). So, we have to imply 'Zicsr' from following extensions: - 'H' - 'Zkr' - 'Zve32x' (I'll talk later) - 'Smstateen' - 'Sscofpmf' - 'Sstc' 'Zkr' is fixed in PATCH 2/3 and 'H' and 'S*' are fixed in PATCH 3/3. The only remaining extension is 'Zve32x' but I need to talk more to explain actual changes (specific to vectors) in PATCH 1/3. On the current version of GNU Binutils, CSRs with CSR_CLASS_V means they require the 'V' extension. However, there are a few vector subextensions that implement vector subsets (intended for embedded processors). - 'Zve64d' (superset of 'Zve64f') - 'Zve64f' (superset of 'Zve32f' and 'Zve64x') - 'Zve64x' (superset of 'Zve32x') - 'Zve32f' (superset of 'Zve32x') - 'Zve32x' : Graph: Dependency graph of some vector/FP extensions : : +-------> D ---+----> F -----> Zicsr : | ^ | ^ : | | / | : V ---> Zve64d ---> Zve64f ---> Zve64x : \ | | : | V V : +-- Zve32f ---> Zve32x : | : | : +---> (Zicsr [added in PATCH 1/3]) They also require general purpose vector CSRs (vstart, vl, vtype and vlenb). So, corresponding CSR_CLASS_V with the 'V' extension is inappropriate (they should require 'Zve32x' instead, the minimum vector subset). Remaining CSRs are: - vxsat - vxrm - vcsr They are related to fixed-point arithmetic and 18.2 "Zve*: Vector Extensions for Embedded Processors" says: > All Zve* extensions support all vector fixed-point arithmetic instructions > (Vector Fixed-Point Arithmetic Instructions), except that vsmul.vv and > vsmul.vx are not supported for EEW=64 in Zve64*. So, their minimum requirement shall be also 'Zve32x', not 'V'. As a consequence, we can conclude that changing requirements of CSR_CLASS_V from 'V' to 'Zve32x' is sufficient to avoid CSR accessibility warnings. Also, 'Zve32x' must imply 'Zicsr' (just like the rest) to avoid CSR instruction errors. This is only effective on 'Zve32x' and 'Zve64x' because, for instance, 'Zve32f' implies 'F' and 'F' implies 'Zicsr' (see the graph above). I didn't rename CSR_CLASS_V to CSR_CLASS_ZVE32X because the name gets difficult and there's already INSN_CLASS_V (effectively requires 'Zve32x' with some exceptions). Tsukasa OI (3): RISC-V: Fix vector CSR requirements and imply RISC-V: Imply 'Zicsr' from 'Zkr' RISC-V: Imply 'Zicsr' from some privileged extensions bfd/elfxx-riscv.c | 6 +++++ gas/config/tc-riscv.c | 2 +- gas/testsuite/gas/riscv/csr-version-1p10.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p11.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p12.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p9p1.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/march-imply-h.d | 6 +++++ gas/testsuite/gas/riscv/vector-csrs-zve32f.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve32x.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve64d.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve64f.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve64x.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs.s | 12 +++++++++ gas/testsuite/gas/riscv/zkr.d | 10 +++++++ gas/testsuite/gas/riscv/zkr.s | 2 ++ 15 files changed, 198 insertions(+), 57 deletions(-) create mode 100644 gas/testsuite/gas/riscv/march-imply-h.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32f.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32x.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64d.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64f.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64x.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs.s create mode 100644 gas/testsuite/gas/riscv/zkr.d create mode 100644 gas/testsuite/gas/riscv/zkr.s base-commit: f555b327d41ed72ffae28caae550f5f86312db43 -- 2.34.1 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 1/3] RISC-V: Fix vector CSR requirements and imply 2022-09-07 6:21 ` [PATCH v2 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI @ 2022-09-07 6:21 ` Tsukasa OI 2022-09-07 9:34 ` Kito Cheng 2022-09-07 6:21 ` [PATCH v2 2/3] RISC-V: Imply 'Zicsr' from 'Zkr' Tsukasa OI ` (2 subsequent siblings) 3 siblings, 1 reply; 17+ messages in thread From: Tsukasa OI @ 2022-09-07 6:21 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils Vector CSRs are also required on smaller vector subsets. It caused assembler errors when only integer-only vector subextensions ('Zve32x'/ 'Zve64x') are enabled. It also caused warnings when CSR checking is enabled on subsets with floating-point arithmetic ('Zve32f'/'Zve64f'/'Zve64d') Not only that the most of vector CSRs are general purpose (and must be accessible for every vector subsets), current minimum vector subset 'Zve32x' requires fixed point arithmetic, making remaining non-general purpose (fixed point arithmetic only) CSRs mandatory for such subsets. So, those CSRs must be accessible from 'Zve32x', not just from 'V'. This commit fixes this issue which caused CSR accessibility warnings. Also, 'Zve32x' does not imply 'Zicsr' so accessing vector CSRs with "-march=rv32i_zve32x" does not work ('Zve64x' does not work as well). This commit fixes this issue by implying 'Zicsr' from 'Zve32x' ('Zve64x' implies 'Zve32x' so adding an implication from 'Zve32x' is sufficient). bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Make 'Zve32x' extension to imply 'Zicsr'. gas/ChangeLog: * config/tc-riscv.c (riscv_csr_address): Change vector CSR requirement from 'V' to 'Zve32x'. * testsuite/gas/riscv/csr-version-1p9p1.l: Change vector CSR requirement from 'V' to 'Zve32x'. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/vector-csrs.s: New test. * testsuite/gas/riscv/vector-csrs-zve32x.d: Likewise. * testsuite/gas/riscv/vector-csrs-zve32f.d: Likewise. * testsuite/gas/riscv/vector-csrs-zve64x.d: Likewise. * testsuite/gas/riscv/vector-csrs-zve64f.d: Likewise. * testsuite/gas/riscv/vector-csrs-zve64d.d: Likewise. --- bfd/elfxx-riscv.c | 1 + gas/config/tc-riscv.c | 2 +- gas/testsuite/gas/riscv/csr-version-1p10.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p11.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p12.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p9p1.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/vector-csrs-zve32f.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve32x.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve64d.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve64f.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve64x.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs.s | 12 +++++++++ 12 files changed, 175 insertions(+), 57 deletions(-) create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32f.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32x.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64d.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64f.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64x.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 8cb3c8d4930..fb742dc9272 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1062,6 +1062,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zve64x", "zve32x", check_implicit_always}, {"zve64x", "zvl64b", check_implicit_always}, {"zve32x", "zvl32b", check_implicit_always}, + {"zve32x", "zicsr", check_implicit_always}, {"zvl65536b", "zvl32768b", check_implicit_always}, {"zvl32768b", "zvl16384b", check_implicit_always}, {"zvl16384b", "zvl8192b", check_implicit_always}, diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 34ce68e8252..df2e201fb74 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -935,7 +935,7 @@ riscv_csr_address (const char *csr_name, extension = "zkr"; break; case CSR_CLASS_V: - extension = "v"; + extension = "zve32x"; break; case CSR_CLASS_SMSTATEEN: case CSR_CLASS_SMSTATEEN_AND_H: diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l index b778453b556..999e9af1520 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p10.l +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l @@ -652,20 +652,20 @@ .*Warning: invalid CSR `fcsr', needs `f' extension .*Warning: invalid CSR `seed', needs `zkr' extension .*Warning: invalid CSR `seed', needs `zkr' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vl,a1' -.*Warning: invalid CSR `vtype', needs `v' extension -.*Warning: invalid CSR `vtype', needs `v' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vtype,a1' -.*Warning: invalid CSR `vlenb', needs `v' extension -.*Warning: invalid CSR `vlenb', needs `v' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vlenb,a1' diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l index 78bae817470..a099e4ecc93 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p11.l +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l @@ -650,20 +650,20 @@ .*Warning: invalid CSR `fcsr', needs `f' extension .*Warning: invalid CSR `seed', needs `zkr' extension .*Warning: invalid CSR `seed', needs `zkr' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vl,a1' -.*Warning: invalid CSR `vtype', needs `v' extension -.*Warning: invalid CSR `vtype', needs `v' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vtype,a1' -.*Warning: invalid CSR `vlenb', needs `v' extension -.*Warning: invalid CSR `vlenb', needs `v' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vlenb,a1' diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l index cb026bb55e0..cf8f2e25634 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p12.l +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l @@ -532,20 +532,20 @@ .*Warning: invalid CSR `fcsr', needs `f' extension .*Warning: invalid CSR `seed', needs `zkr' extension .*Warning: invalid CSR `seed', needs `zkr' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vl,a1' -.*Warning: invalid CSR `vtype', needs `v' extension -.*Warning: invalid CSR `vtype', needs `v' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vtype,a1' -.*Warning: invalid CSR `vlenb', needs `v' extension -.*Warning: invalid CSR `vlenb', needs `v' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vlenb,a1' diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l index 4fac40fb589..5f298c1dda9 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l @@ -678,20 +678,20 @@ .*Warning: invalid CSR `fcsr', needs `f' extension .*Warning: invalid CSR `seed', needs `zkr' extension .*Warning: invalid CSR `seed', needs `zkr' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vl,a1' -.*Warning: invalid CSR `vtype', needs `v' extension -.*Warning: invalid CSR `vtype', needs `v' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vtype,a1' -.*Warning: invalid CSR `vlenb', needs `v' extension -.*Warning: invalid CSR `vlenb', needs `v' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vlenb,a1' diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve32f.d b/gas/testsuite/gas/riscv/vector-csrs-zve32f.d new file mode 100644 index 00000000000..9613915713b --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs-zve32f.d @@ -0,0 +1,21 @@ +#as: -march=rv32i_zve32f -mcsr-check +#source: vector-csrs.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve32x.d b/gas/testsuite/gas/riscv/vector-csrs-zve32x.d new file mode 100644 index 00000000000..a608efbfb0b --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs-zve32x.d @@ -0,0 +1,21 @@ +#as: -march=rv32i_zve32x -mcsr-check +#source: vector-csrs.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64d.d b/gas/testsuite/gas/riscv/vector-csrs-zve64d.d new file mode 100644 index 00000000000..f42e670699a --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64d.d @@ -0,0 +1,21 @@ +#as: -march=rv32i_zve64d -mcsr-check +#source: vector-csrs.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64f.d b/gas/testsuite/gas/riscv/vector-csrs-zve64f.d new file mode 100644 index 00000000000..e88b5a3ff6e --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64f.d @@ -0,0 +1,21 @@ +#as: -march=rv32i_zve64f -mcsr-check +#source: vector-csrs.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64x.d b/gas/testsuite/gas/riscv/vector-csrs-zve64x.d new file mode 100644 index 00000000000..83aa1bba341 --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64x.d @@ -0,0 +1,21 @@ +#as: -march=rv32i_zve64x -mcsr-check +#source: vector-csrs.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/vector-csrs.s b/gas/testsuite/gas/riscv/vector-csrs.s new file mode 100644 index 00000000000..7019a0588ef --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs.s @@ -0,0 +1,12 @@ +target: + csrr a0, vstart + csrw vstart, zero + csrr a0, vxsat + csrwi vxsat, 1 + csrr a0, vxrm + csrwi vxrm, 3 + csrr a0, vcsr + csrwi vcsr, 7 + csrr a0, vl + csrr a0, vtype + csrr a0, vlenb -- 2.34.1 ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 1/3] RISC-V: Fix vector CSR requirements and imply 2022-09-07 6:21 ` [PATCH v2 1/3] RISC-V: Fix vector CSR requirements and imply Tsukasa OI @ 2022-09-07 9:34 ` Kito Cheng 2022-09-09 11:10 ` Tsukasa OI 0 siblings, 1 reply; 17+ messages in thread From: Kito Cheng @ 2022-09-07 9:34 UTC (permalink / raw) To: Tsukasa OI; +Cc: Nelson Chu, Palmer Dabbelt, Binutils [-- Attachment #1: Type: text/plain, Size: 19738 bytes --] I am +1 on this change, *BUT* I would like to clarify that on ISA spec first, maybe create an issue on riscv-v-spec? On Wed, Sep 7, 2022 at 2:22 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote: > Vector CSRs are also required on smaller vector subsets. It caused > assembler errors when only integer-only vector subextensions ('Zve32x'/ > 'Zve64x') are enabled. It also caused warnings when CSR checking is > enabled on subsets with floating-point arithmetic > ('Zve32f'/'Zve64f'/'Zve64d') > > Not only that the most of vector CSRs are general purpose (and must be > accessible for every vector subsets), current minimum vector subset > 'Zve32x' > requires fixed point arithmetic, making remaining non-general purpose > (fixed point arithmetic only) CSRs mandatory for such subsets. > > So, those CSRs must be accessible from 'Zve32x', not just from 'V'. > This commit fixes this issue which caused CSR accessibility warnings. > > Also, 'Zve32x' does not imply 'Zicsr' so accessing vector CSRs with > "-march=rv32i_zve32x" does not work ('Zve64x' does not work as well). > This commit fixes this issue by implying 'Zicsr' from 'Zve32x' ('Zve64x' > implies 'Zve32x' so adding an implication from 'Zve32x' is sufficient). > > bfd/ChangeLog: > > * elfxx-riscv.c (riscv_implicit_subsets): Make 'Zve32x' extension > to imply 'Zicsr'. > > gas/ChangeLog: > > * config/tc-riscv.c (riscv_csr_address): Change vector CSR > requirement from 'V' to 'Zve32x'. > * testsuite/gas/riscv/csr-version-1p9p1.l: Change vector CSR > requirement from 'V' to 'Zve32x'. > * testsuite/gas/riscv/csr-version-1p10.l: Likewise. > * testsuite/gas/riscv/csr-version-1p11.l: Likewise. > * testsuite/gas/riscv/csr-version-1p12.l: Likewise. > * testsuite/gas/riscv/vector-csrs.s: New test. > * testsuite/gas/riscv/vector-csrs-zve32x.d: Likewise. > * testsuite/gas/riscv/vector-csrs-zve32f.d: Likewise. > * testsuite/gas/riscv/vector-csrs-zve64x.d: Likewise. > * testsuite/gas/riscv/vector-csrs-zve64f.d: Likewise. > * testsuite/gas/riscv/vector-csrs-zve64d.d: Likewise. > --- > bfd/elfxx-riscv.c | 1 + > gas/config/tc-riscv.c | 2 +- > gas/testsuite/gas/riscv/csr-version-1p10.l | 28 ++++++++++---------- > gas/testsuite/gas/riscv/csr-version-1p11.l | 28 ++++++++++---------- > gas/testsuite/gas/riscv/csr-version-1p12.l | 28 ++++++++++---------- > gas/testsuite/gas/riscv/csr-version-1p9p1.l | 28 ++++++++++---------- > gas/testsuite/gas/riscv/vector-csrs-zve32f.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs-zve32x.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs-zve64d.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs-zve64f.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs-zve64x.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs.s | 12 +++++++++ > 12 files changed, 175 insertions(+), 57 deletions(-) > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32f.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32x.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64d.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64f.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64x.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs.s > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index 8cb3c8d4930..fb742dc9272 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -1062,6 +1062,7 @@ static struct riscv_implicit_subset > riscv_implicit_subsets[] = > {"zve64x", "zve32x", check_implicit_always}, > {"zve64x", "zvl64b", check_implicit_always}, > {"zve32x", "zvl32b", check_implicit_always}, > + {"zve32x", "zicsr", check_implicit_always}, > {"zvl65536b", "zvl32768b", check_implicit_always}, > {"zvl32768b", "zvl16384b", check_implicit_always}, > {"zvl16384b", "zvl8192b", check_implicit_always}, > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index 34ce68e8252..df2e201fb74 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -935,7 +935,7 @@ riscv_csr_address (const char *csr_name, > extension = "zkr"; > break; > case CSR_CLASS_V: > - extension = "v"; > + extension = "zve32x"; > break; > case CSR_CLASS_SMSTATEEN: > case CSR_CLASS_SMSTATEEN_AND_H: > diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l > b/gas/testsuite/gas/riscv/csr-version-1p10.l > index b778453b556..999e9af1520 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p10.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l > @@ -652,20 +652,20 @@ > .*Warning: invalid CSR `fcsr', needs `f' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vl,a1' > -.*Warning: invalid CSR `vtype', needs `v' extension > -.*Warning: invalid CSR `vtype', needs `v' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vtype,a1' > -.*Warning: invalid CSR `vlenb', needs `v' extension > -.*Warning: invalid CSR `vlenb', needs `v' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vlenb,a1' > diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l > b/gas/testsuite/gas/riscv/csr-version-1p11.l > index 78bae817470..a099e4ecc93 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p11.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l > @@ -650,20 +650,20 @@ > .*Warning: invalid CSR `fcsr', needs `f' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vl,a1' > -.*Warning: invalid CSR `vtype', needs `v' extension > -.*Warning: invalid CSR `vtype', needs `v' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vtype,a1' > -.*Warning: invalid CSR `vlenb', needs `v' extension > -.*Warning: invalid CSR `vlenb', needs `v' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vlenb,a1' > diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l > b/gas/testsuite/gas/riscv/csr-version-1p12.l > index cb026bb55e0..cf8f2e25634 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p12.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l > @@ -532,20 +532,20 @@ > .*Warning: invalid CSR `fcsr', needs `f' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vl,a1' > -.*Warning: invalid CSR `vtype', needs `v' extension > -.*Warning: invalid CSR `vtype', needs `v' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vtype,a1' > -.*Warning: invalid CSR `vlenb', needs `v' extension > -.*Warning: invalid CSR `vlenb', needs `v' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vlenb,a1' > diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l > b/gas/testsuite/gas/riscv/csr-version-1p9p1.l > index 4fac40fb589..5f298c1dda9 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l > @@ -678,20 +678,20 @@ > .*Warning: invalid CSR `fcsr', needs `f' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vl,a1' > -.*Warning: invalid CSR `vtype', needs `v' extension > -.*Warning: invalid CSR `vtype', needs `v' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vtype,a1' > -.*Warning: invalid CSR `vlenb', needs `v' extension > -.*Warning: invalid CSR `vlenb', needs `v' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vlenb,a1' > diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve32f.d > b/gas/testsuite/gas/riscv/vector-csrs-zve32f.d > new file mode 100644 > index 00000000000..9613915713b > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs-zve32f.d > @@ -0,0 +1,21 @@ > +#as: -march=rv32i_zve32f -mcsr-check > +#source: vector-csrs.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart > +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero > +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat > +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 > +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm > +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 > +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr > +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 > +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl > +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype > +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve32x.d > b/gas/testsuite/gas/riscv/vector-csrs-zve32x.d > new file mode 100644 > index 00000000000..a608efbfb0b > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs-zve32x.d > @@ -0,0 +1,21 @@ > +#as: -march=rv32i_zve32x -mcsr-check > +#source: vector-csrs.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart > +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero > +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat > +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 > +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm > +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 > +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr > +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 > +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl > +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype > +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64d.d > b/gas/testsuite/gas/riscv/vector-csrs-zve64d.d > new file mode 100644 > index 00000000000..f42e670699a > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64d.d > @@ -0,0 +1,21 @@ > +#as: -march=rv32i_zve64d -mcsr-check > +#source: vector-csrs.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart > +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero > +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat > +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 > +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm > +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 > +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr > +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 > +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl > +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype > +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64f.d > b/gas/testsuite/gas/riscv/vector-csrs-zve64f.d > new file mode 100644 > index 00000000000..e88b5a3ff6e > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64f.d > @@ -0,0 +1,21 @@ > +#as: -march=rv32i_zve64f -mcsr-check > +#source: vector-csrs.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart > +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero > +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat > +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 > +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm > +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 > +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr > +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 > +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl > +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype > +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64x.d > b/gas/testsuite/gas/riscv/vector-csrs-zve64x.d > new file mode 100644 > index 00000000000..83aa1bba341 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64x.d > @@ -0,0 +1,21 @@ > +#as: -march=rv32i_zve64x -mcsr-check > +#source: vector-csrs.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart > +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero > +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat > +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 > +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm > +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 > +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr > +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 > +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl > +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype > +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > diff --git a/gas/testsuite/gas/riscv/vector-csrs.s > b/gas/testsuite/gas/riscv/vector-csrs.s > new file mode 100644 > index 00000000000..7019a0588ef > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs.s > @@ -0,0 +1,12 @@ > +target: > + csrr a0, vstart > + csrw vstart, zero > + csrr a0, vxsat > + csrwi vxsat, 1 > + csrr a0, vxrm > + csrwi vxrm, 3 > + csrr a0, vcsr > + csrwi vcsr, 7 > + csrr a0, vl > + csrr a0, vtype > + csrr a0, vlenb > -- > 2.34.1 > > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 1/3] RISC-V: Fix vector CSR requirements and imply 2022-09-07 9:34 ` Kito Cheng @ 2022-09-09 11:10 ` Tsukasa OI 0 siblings, 0 replies; 17+ messages in thread From: Tsukasa OI @ 2022-09-09 11:10 UTC (permalink / raw) To: Kito Cheng, Andrew Waterman; +Cc: Nelson Chu, Palmer Dabbelt, Binutils On 2022/09/07 18:34, Kito Cheng wrote: > I am +1 on this change, *BUT* I would like to clarify that on ISA spec > first, maybe create an issue on riscv-v-spec? (I'm forwarding this topic to Andrew) Understood. So, new general question raised: "If an extension defines CSRs, does it have to define explicit dependency to 'Zicsr' or do we have implicit one?" So, I investigated the current situation. It seems, explicitly stating that an extension requires the 'Zicsr' extension is seen on the draft RISC-V ISA Manual, 'Zicntr' and 'Zihpm' extensions (for 'Zicntr', things will get more complex since 'Zicntr' pseudoinstructions were a part of 'I' so preserving the toolchain compatibility may be a new problem). For privileged extensions, I found something new I missed. From The RISC-V Instruction Set Manual Volume II: Privileged Architecture, > Chapter 2: Control and Status Registers (CSRs) > ... > The privileged architecture requires the Zicsr extension; which other > privileged instructions are required depends on the privileged- > architecture feature set. So, for 'H', 'Smstateen', 'Sscofpmf' and 'Sstc', my views seem valid because they are privileged extensions (that depend on the privileged architecture, indirectly depending on 'Zicsr'). I'll submit new patchset for only privileged extensions (more general solution will be required in the future, though). The problem is unprivileged ones: There are 3 extensions already with CSRs are ratified with no direct/indirect dependencies to 'Zicsr'. I think it's more natural to have that dependency or adding a general implicit dependency rule about 'Zicsr' to ... somewhere very general (RISC-V ISA Manual doesn't seem right but as general as this). - 'Zkr' - 'Zve32x' - 'Zve64x' Also, packed SIMD and the pointer masking proposal ('Zjpm') will have a similar problem because they either define their new CSRs and/or reuse the existing ones (like in packed SIMD, which reuses "vxsat" from 'V'). Note that Zjpm defines both privileged/unprivileged CSRs. The thing is, this is not just about riscv-v-spec. If we are able, we need to talk about it in more general place. Any ideas? Thanks, Tsukasa > > On Wed, Sep 7, 2022 at 2:22 PM Tsukasa OI <research_trasio@irq.a4lg.com > <mailto:research_trasio@irq.a4lg.com>> wrote: > > Vector CSRs are also required on smaller vector subsets. It caused > assembler errors when only integer-only vector subextensions ('Zve32x'/ > 'Zve64x') are enabled. It also caused warnings when CSR checking is > enabled on subsets with floating-point arithmetic > ('Zve32f'/'Zve64f'/'Zve64d') > > Not only that the most of vector CSRs are general purpose (and must be > accessible for every vector subsets), current minimum vector subset > 'Zve32x' > requires fixed point arithmetic, making remaining non-general purpose > (fixed point arithmetic only) CSRs mandatory for such subsets. > > So, those CSRs must be accessible from 'Zve32x', not just from 'V'. > This commit fixes this issue which caused CSR accessibility warnings. > > Also, 'Zve32x' does not imply 'Zicsr' so accessing vector CSRs with > "-march=rv32i_zve32x" does not work ('Zve64x' does not work as well). > This commit fixes this issue by implying 'Zicsr' from 'Zve32x' ('Zve64x' > implies 'Zve32x' so adding an implication from 'Zve32x' is sufficient). > > bfd/ChangeLog: > > * elfxx-riscv.c (riscv_implicit_subsets): Make 'Zve32x' > extension > to imply 'Zicsr'. > > gas/ChangeLog: > > * config/tc-riscv.c (riscv_csr_address): Change vector CSR > requirement from 'V' to 'Zve32x'. > * testsuite/gas/riscv/csr-version-1p9p1.l: Change vector CSR > requirement from 'V' to 'Zve32x'. > * testsuite/gas/riscv/csr-version-1p10.l: Likewise. > * testsuite/gas/riscv/csr-version-1p11.l: Likewise. > * testsuite/gas/riscv/csr-version-1p12.l: Likewise. > * testsuite/gas/riscv/vector-csrs.s: New test. > * testsuite/gas/riscv/vector-csrs-zve32x.d: Likewise. > * testsuite/gas/riscv/vector-csrs-zve32f.d: Likewise. > * testsuite/gas/riscv/vector-csrs-zve64x.d: Likewise. > * testsuite/gas/riscv/vector-csrs-zve64f.d: Likewise. > * testsuite/gas/riscv/vector-csrs-zve64d.d: Likewise. > --- > bfd/elfxx-riscv.c | 1 + > gas/config/tc-riscv.c | 2 +- > gas/testsuite/gas/riscv/csr-version-1p10.l | 28 ++++++++++---------- > gas/testsuite/gas/riscv/csr-version-1p11.l | 28 ++++++++++---------- > gas/testsuite/gas/riscv/csr-version-1p12.l | 28 ++++++++++---------- > gas/testsuite/gas/riscv/csr-version-1p9p1.l | 28 ++++++++++---------- > gas/testsuite/gas/riscv/vector-csrs-zve32f.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs-zve32x.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs-zve64d.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs-zve64f.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs-zve64x.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs.s | 12 +++++++++ > 12 files changed, 175 insertions(+), 57 deletions(-) > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32f.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32x.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64d.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64f.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64x.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs.s > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index 8cb3c8d4930..fb742dc9272 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -1062,6 +1062,7 @@ static struct riscv_implicit_subset > riscv_implicit_subsets[] = > {"zve64x", "zve32x", check_implicit_always}, > {"zve64x", "zvl64b", check_implicit_always}, > {"zve32x", "zvl32b", check_implicit_always}, > + {"zve32x", "zicsr", check_implicit_always}, > {"zvl65536b", "zvl32768b", check_implicit_always}, > {"zvl32768b", "zvl16384b", check_implicit_always}, > {"zvl16384b", "zvl8192b", check_implicit_always}, > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index 34ce68e8252..df2e201fb74 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -935,7 +935,7 @@ riscv_csr_address (const char *csr_name, > extension = "zkr"; > break; > case CSR_CLASS_V: > - extension = "v"; > + extension = "zve32x"; > break; > case CSR_CLASS_SMSTATEEN: > case CSR_CLASS_SMSTATEEN_AND_H: > diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l > b/gas/testsuite/gas/riscv/csr-version-1p10.l > index b778453b556..999e9af1520 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p10.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l > @@ -652,20 +652,20 @@ > .*Warning: invalid CSR `fcsr', needs `f' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vl,a1' > -.*Warning: invalid CSR `vtype', needs `v' extension > -.*Warning: invalid CSR `vtype', needs `v' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vtype,a1' > -.*Warning: invalid CSR `vlenb', needs `v' extension > -.*Warning: invalid CSR `vlenb', needs `v' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vlenb,a1' > diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l > b/gas/testsuite/gas/riscv/csr-version-1p11.l > index 78bae817470..a099e4ecc93 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p11.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l > @@ -650,20 +650,20 @@ > .*Warning: invalid CSR `fcsr', needs `f' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vl,a1' > -.*Warning: invalid CSR `vtype', needs `v' extension > -.*Warning: invalid CSR `vtype', needs `v' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vtype,a1' > -.*Warning: invalid CSR `vlenb', needs `v' extension > -.*Warning: invalid CSR `vlenb', needs `v' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vlenb,a1' > diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l > b/gas/testsuite/gas/riscv/csr-version-1p12.l > index cb026bb55e0..cf8f2e25634 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p12.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l > @@ -532,20 +532,20 @@ > .*Warning: invalid CSR `fcsr', needs `f' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vl,a1' > -.*Warning: invalid CSR `vtype', needs `v' extension > -.*Warning: invalid CSR `vtype', needs `v' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vtype,a1' > -.*Warning: invalid CSR `vlenb', needs `v' extension > -.*Warning: invalid CSR `vlenb', needs `v' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vlenb,a1' > diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l > b/gas/testsuite/gas/riscv/csr-version-1p9p1.l > index 4fac40fb589..5f298c1dda9 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l > @@ -678,20 +678,20 @@ > .*Warning: invalid CSR `fcsr', needs `f' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vl,a1' > -.*Warning: invalid CSR `vtype', needs `v' extension > -.*Warning: invalid CSR `vtype', needs `v' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vtype,a1' > -.*Warning: invalid CSR `vlenb', needs `v' extension > -.*Warning: invalid CSR `vlenb', needs `v' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vlenb,a1' > diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve32f.d > b/gas/testsuite/gas/riscv/vector-csrs-zve32f.d > new file mode 100644 > index 00000000000..9613915713b > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs-zve32f.d > @@ -0,0 +1,21 @@ > +#as: -march=rv32i_zve32f -mcsr-check > +#source: vector-csrs.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart > +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero > +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat > +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 > +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm > +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 > +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr > +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 > +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl > +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype > +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve32x.d > b/gas/testsuite/gas/riscv/vector-csrs-zve32x.d > new file mode 100644 > index 00000000000..a608efbfb0b > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs-zve32x.d > @@ -0,0 +1,21 @@ > +#as: -march=rv32i_zve32x -mcsr-check > +#source: vector-csrs.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart > +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero > +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat > +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 > +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm > +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 > +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr > +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 > +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl > +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype > +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64d.d > b/gas/testsuite/gas/riscv/vector-csrs-zve64d.d > new file mode 100644 > index 00000000000..f42e670699a > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64d.d > @@ -0,0 +1,21 @@ > +#as: -march=rv32i_zve64d -mcsr-check > +#source: vector-csrs.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart > +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero > +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat > +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 > +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm > +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 > +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr > +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 > +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl > +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype > +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64f.d > b/gas/testsuite/gas/riscv/vector-csrs-zve64f.d > new file mode 100644 > index 00000000000..e88b5a3ff6e > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64f.d > @@ -0,0 +1,21 @@ > +#as: -march=rv32i_zve64f -mcsr-check > +#source: vector-csrs.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart > +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero > +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat > +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 > +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm > +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 > +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr > +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 > +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl > +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype > +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64x.d > b/gas/testsuite/gas/riscv/vector-csrs-zve64x.d > new file mode 100644 > index 00000000000..83aa1bba341 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64x.d > @@ -0,0 +1,21 @@ > +#as: -march=rv32i_zve64x -mcsr-check > +#source: vector-csrs.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart > +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero > +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat > +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 > +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm > +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 > +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr > +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 > +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl > +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype > +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > diff --git a/gas/testsuite/gas/riscv/vector-csrs.s > b/gas/testsuite/gas/riscv/vector-csrs.s > new file mode 100644 > index 00000000000..7019a0588ef > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs.s > @@ -0,0 +1,12 @@ > +target: > + csrr a0, vstart > + csrw vstart, zero > + csrr a0, vxsat > + csrwi vxsat, 1 > + csrr a0, vxrm > + csrwi vxrm, 3 > + csrr a0, vcsr > + csrwi vcsr, 7 > + csrr a0, vl > + csrr a0, vtype > + csrr a0, vlenb > -- > 2.34.1 > ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 2/3] RISC-V: Imply 'Zicsr' from 'Zkr' 2022-09-07 6:21 ` [PATCH v2 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI 2022-09-07 6:21 ` [PATCH v2 1/3] RISC-V: Fix vector CSR requirements and imply Tsukasa OI @ 2022-09-07 6:21 ` Tsukasa OI 2022-09-07 6:21 ` [PATCH v2 3/3] RISC-V: Imply 'Zicsr' from some privileged extensions Tsukasa OI 2022-09-08 6:53 ` [PATCH 0/1] RISC-V: Fix CSR accessibility on vectors Tsukasa OI 3 siblings, 0 replies; 17+ messages in thread From: Tsukasa OI @ 2022-09-07 6:21 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils Because the 'Zkr' extension implements a CSR, seed, it requires 'Zicsr' as a prerequisite. On such cases, it's natural to imply required extension. This commit adds Zkr -> Zicsr to the extension implication list. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Imply 'Zicsr' from 'Zkr'. gas/ChangeLog: * testsuite/gas/riscv/zkr.s: Separate test for the 'Zkr' extension. * testsuite/gas/riscv/zkr.d: Likewise. --- bfd/elfxx-riscv.c | 1 + gas/testsuite/gas/riscv/zkr.d | 10 ++++++++++ gas/testsuite/gas/riscv/zkr.s | 2 ++ 3 files changed, 13 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zkr.d create mode 100644 gas/testsuite/gas/riscv/zkr.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index fb742dc9272..2e91963bbfb 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1092,6 +1092,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zkn", "zkne", check_implicit_always}, {"zkn", "zknd", check_implicit_always}, {"zkn", "zknh", check_implicit_always}, + {"zkr", "zicsr", check_implicit_always}, {"zks", "zbkb", check_implicit_always}, {"zks", "zbkc", check_implicit_always}, {"zks", "zbkx", check_implicit_always}, diff --git a/gas/testsuite/gas/riscv/zkr.d b/gas/testsuite/gas/riscv/zkr.d new file mode 100644 index 00000000000..4c0471835a1 --- /dev/null +++ b/gas/testsuite/gas/riscv/zkr.d @@ -0,0 +1,10 @@ +#as: -march=rv32i_zkr -mcsr-check +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed diff --git a/gas/testsuite/gas/riscv/zkr.s b/gas/testsuite/gas/riscv/zkr.s new file mode 100644 index 00000000000..96a38fbf49f --- /dev/null +++ b/gas/testsuite/gas/riscv/zkr.s @@ -0,0 +1,2 @@ +target: + csrr a0, seed -- 2.34.1 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 3/3] RISC-V: Imply 'Zicsr' from some privileged extensions 2022-09-07 6:21 ` [PATCH v2 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI 2022-09-07 6:21 ` [PATCH v2 1/3] RISC-V: Fix vector CSR requirements and imply Tsukasa OI 2022-09-07 6:21 ` [PATCH v2 2/3] RISC-V: Imply 'Zicsr' from 'Zkr' Tsukasa OI @ 2022-09-07 6:21 ` Tsukasa OI 2022-09-08 6:53 ` [PATCH 0/1] RISC-V: Fix CSR accessibility on vectors Tsukasa OI 3 siblings, 0 replies; 17+ messages in thread From: Tsukasa OI @ 2022-09-07 6:21 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils As 'H', 'Smstateen', 'Sscofpmf' and 'Sstc' define their own CSRs, they implicitly require 'Zicsr' in the process. This commit adds such implicications. gas/ChangeLog: * testsuite/gas/riscv/march-imply-h.d: New test, at least for 'H'. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add 'Zicsr' implicications for privileged extensions 'H', 'Smstateen', 'Sscofpmf' and 'Sstc'. --- bfd/elfxx-riscv.c | 4 ++++ gas/testsuite/gas/riscv/march-imply-h.d | 6 ++++++ 2 files changed, 10 insertions(+) create mode 100644 gas/testsuite/gas/riscv/march-imply-h.d diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 2e91963bbfb..73848f725e6 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1047,6 +1047,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"g", "d", check_implicit_always}, {"g", "zicsr", check_implicit_always}, {"g", "zifencei", check_implicit_always}, + {"h", "zicsr", check_implicit_always}, {"q", "d", check_implicit_always}, {"v", "d", check_implicit_always}, {"v", "zve64d", check_implicit_always}, @@ -1098,6 +1099,9 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zks", "zbkx", check_implicit_always}, {"zks", "zksed", check_implicit_always}, {"zks", "zksh", check_implicit_always}, + {"smstateen", "zicsr", check_implicit_always}, + {"sscofpmf", "zicsr", check_implicit_always}, + {"sstc", "zicsr", check_implicit_always}, {NULL, NULL, NULL} }; diff --git a/gas/testsuite/gas/riscv/march-imply-h.d b/gas/testsuite/gas/riscv/march-imply-h.d new file mode 100644 index 00000000000..04ad9f6c0a5 --- /dev/null +++ b/gas/testsuite/gas/riscv/march-imply-h.d @@ -0,0 +1,6 @@ +#as: -march=rv32ih -march-attr -misa-spec=20191213 -mpriv-spec=1.12 +#readelf: -A +#source: empty.s +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: "rv32i2p1_h1p0_zicsr2p0" -- 2.34.1 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 0/1] RISC-V: Fix CSR accessibility on vectors 2022-09-07 6:21 ` [PATCH v2 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI ` (2 preceding siblings ...) 2022-09-07 6:21 ` [PATCH v2 3/3] RISC-V: Imply 'Zicsr' from some privileged extensions Tsukasa OI @ 2022-09-08 6:53 ` Tsukasa OI 2022-09-08 6:53 ` [PATCH 1/1] RISC-V: Fix vector CSR requirements Tsukasa OI 3 siblings, 1 reply; 17+ messages in thread From: Tsukasa OI @ 2022-09-08 6:53 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils Tracker on GitHub: <https://github.com/a4lg/binutils-gdb/wiki/riscv_fix_csr_access_on_vector> Previous: <https://sourceware.org/pipermail/binutils/2022-September/122761.html> This is a subset of previous CSR accessibility and implication patchset. It seems making requirement of CSR_CLASS_V from 'V' to 'Zve32x' is less debatable, I splitted this part as a separate patchset. (Not strictly a subset; I added CSR accessibility test for 'V') An excerpt (slightly modified) from previous cover letter follows: On the current version of GNU Binutils, CSRs with CSR_CLASS_V means they require the 'V' extension. However, there are a few vector subextensions that implement vector subsets (intended for embedded processors). - 'Zve64d' (superset of 'Zve64f') - 'Zve64f' (superset of 'Zve32f' and 'Zve64x') - 'Zve64x' (superset of 'Zve32x') - 'Zve32f' (superset of 'Zve32x') - 'Zve32x' | Graph: Dependency graph of some vector/FP extensions and Zicsr | | +-------> D ---+----> F -----> Zicsr | | ^ | ^ | | | / | | V ---> Zve64d ---> Zve64f ---> Zve64x | \ | | | | V V | +-- Zve32f ---> Zve32x | | | | | +---> (Zicsr [should be added?]) They also require general purpose vector CSRs (vstart, vl, vtype and vlenb). So, corresponding CSR_CLASS_V with the 'V' extension is inappropriate (they should require 'Zve32x' instead, the minimum vector subset). Remaining CSRs are: - vxsat - vxrm - vcsr They are related to fixed-point arithmetic and 18.2 "Zve*: Vector Extensions for Embedded Processors" says: > All Zve* extensions support all vector fixed-point arithmetic instructions > (Vector Fixed-Point Arithmetic Instructions), except that vsmul.vv and > vsmul.vx are not supported for EEW=64 in Zve64*. So, their minimum requirement shall be also 'Zve32x', not 'V'. As a consequence, we can conclude that changing requirements of CSR_CLASS_V from 'V' to 'Zve32x' is sufficient to avoid CSR accessibility warnings. I didn't rename CSR_CLASS_V to CSR_CLASS_ZVE32X because the name gets difficult and there's already INSN_CLASS_V (effectively requires 'Zve32x' with some exceptions). Tsukasa OI (1): RISC-V: Fix vector CSR requirements gas/config/tc-riscv.c | 2 +- gas/testsuite/gas/riscv/csr-version-1p10.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p11.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p12.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p9p1.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/vector-csrs-v.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve32f.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve32x.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve64d.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve64f.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve64x.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs.s | 12 +++++++++ 12 files changed, 195 insertions(+), 57 deletions(-) create mode 100644 gas/testsuite/gas/riscv/vector-csrs-v.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32f.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32x.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64d.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64f.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64x.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs.s base-commit: f42546b6cc7468ac7d929181ed7b965ab60958ac -- 2.34.1 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/1] RISC-V: Fix vector CSR requirements 2022-09-08 6:53 ` [PATCH 0/1] RISC-V: Fix CSR accessibility on vectors Tsukasa OI @ 2022-09-08 6:53 ` Tsukasa OI 2022-09-08 7:12 ` Nelson Chu 0 siblings, 1 reply; 17+ messages in thread From: Tsukasa OI @ 2022-09-08 6:53 UTC (permalink / raw) To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils Vector CSRs are also required on smaller vector subsets. Not only that the most of vector CSRs are general purpose (and must be accessible for every vector subsets), current minimum vector subset 'Zve32x' requires fixed point arithmetic, making remaining non-general purpose (fixed point arithmetic only) CSRs mandatory for such subsets. So, those CSRs must be accessible from 'Zve32x', not just from 'V'. This commit fixes this issue which caused CSR accessibility warnings. gas/ChangeLog: * config/tc-riscv.c (riscv_csr_address): Change vector CSR requirement from 'V' to 'Zve32x'. * testsuite/gas/riscv/csr-version-1p9p1.l: Change vector CSR requirement from 'V' to 'Zve32x'. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/vector-csrs.s: New test. * testsuite/gas/riscv/vector-csrs-v.d: Likewise. * testsuite/gas/riscv/vector-csrs-zve32x.d: Likewise. * testsuite/gas/riscv/vector-csrs-zve32f.d: Likewise. * testsuite/gas/riscv/vector-csrs-zve64x.d: Likewise. * testsuite/gas/riscv/vector-csrs-zve64f.d: Likewise. * testsuite/gas/riscv/vector-csrs-zve64d.d: Likewise. --- gas/config/tc-riscv.c | 2 +- gas/testsuite/gas/riscv/csr-version-1p10.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p11.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p12.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p9p1.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/vector-csrs-v.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve32f.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve32x.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve64d.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve64f.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve64x.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs.s | 12 +++++++++ 12 files changed, 195 insertions(+), 57 deletions(-) create mode 100644 gas/testsuite/gas/riscv/vector-csrs-v.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32f.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32x.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64d.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64f.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64x.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs.s diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 34ce68e8252..df2e201fb74 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -935,7 +935,7 @@ riscv_csr_address (const char *csr_name, extension = "zkr"; break; case CSR_CLASS_V: - extension = "v"; + extension = "zve32x"; break; case CSR_CLASS_SMSTATEEN: case CSR_CLASS_SMSTATEEN_AND_H: diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l index b778453b556..999e9af1520 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p10.l +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l @@ -652,20 +652,20 @@ .*Warning: invalid CSR `fcsr', needs `f' extension .*Warning: invalid CSR `seed', needs `zkr' extension .*Warning: invalid CSR `seed', needs `zkr' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vl,a1' -.*Warning: invalid CSR `vtype', needs `v' extension -.*Warning: invalid CSR `vtype', needs `v' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vtype,a1' -.*Warning: invalid CSR `vlenb', needs `v' extension -.*Warning: invalid CSR `vlenb', needs `v' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vlenb,a1' diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l index 78bae817470..a099e4ecc93 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p11.l +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l @@ -650,20 +650,20 @@ .*Warning: invalid CSR `fcsr', needs `f' extension .*Warning: invalid CSR `seed', needs `zkr' extension .*Warning: invalid CSR `seed', needs `zkr' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vl,a1' -.*Warning: invalid CSR `vtype', needs `v' extension -.*Warning: invalid CSR `vtype', needs `v' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vtype,a1' -.*Warning: invalid CSR `vlenb', needs `v' extension -.*Warning: invalid CSR `vlenb', needs `v' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vlenb,a1' diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l index cb026bb55e0..cf8f2e25634 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p12.l +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l @@ -532,20 +532,20 @@ .*Warning: invalid CSR `fcsr', needs `f' extension .*Warning: invalid CSR `seed', needs `zkr' extension .*Warning: invalid CSR `seed', needs `zkr' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vl,a1' -.*Warning: invalid CSR `vtype', needs `v' extension -.*Warning: invalid CSR `vtype', needs `v' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vtype,a1' -.*Warning: invalid CSR `vlenb', needs `v' extension -.*Warning: invalid CSR `vlenb', needs `v' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vlenb,a1' diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l index 4fac40fb589..5f298c1dda9 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l @@ -678,20 +678,20 @@ .*Warning: invalid CSR `fcsr', needs `f' extension .*Warning: invalid CSR `seed', needs `zkr' extension .*Warning: invalid CSR `seed', needs `zkr' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vstart', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxsat', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vxrm', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vcsr', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension -.*Warning: invalid CSR `vl', needs `v' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vstart', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxsat', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vxrm', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vcsr', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension +.*Warning: invalid CSR `vl', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vl,a1' -.*Warning: invalid CSR `vtype', needs `v' extension -.*Warning: invalid CSR `vtype', needs `v' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension +.*Warning: invalid CSR `vtype', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vtype,a1' -.*Warning: invalid CSR `vlenb', needs `v' extension -.*Warning: invalid CSR `vlenb', needs `v' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension +.*Warning: invalid CSR `vlenb', needs `zve32x' extension .*Warning: read-only CSR is written `csrw vlenb,a1' diff --git a/gas/testsuite/gas/riscv/vector-csrs-v.d b/gas/testsuite/gas/riscv/vector-csrs-v.d new file mode 100644 index 00000000000..1376f01d83e --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs-v.d @@ -0,0 +1,21 @@ +#as: -march=rv32iv -mcsr-check +#source: vector-csrs.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve32f.d b/gas/testsuite/gas/riscv/vector-csrs-zve32f.d new file mode 100644 index 00000000000..9613915713b --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs-zve32f.d @@ -0,0 +1,21 @@ +#as: -march=rv32i_zve32f -mcsr-check +#source: vector-csrs.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve32x.d b/gas/testsuite/gas/riscv/vector-csrs-zve32x.d new file mode 100644 index 00000000000..1e18d923e8c --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs-zve32x.d @@ -0,0 +1,21 @@ +#as: -march=rv32i_zicsr_zve32x -mcsr-check +#source: vector-csrs.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64d.d b/gas/testsuite/gas/riscv/vector-csrs-zve64d.d new file mode 100644 index 00000000000..f42e670699a --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64d.d @@ -0,0 +1,21 @@ +#as: -march=rv32i_zve64d -mcsr-check +#source: vector-csrs.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64f.d b/gas/testsuite/gas/riscv/vector-csrs-zve64f.d new file mode 100644 index 00000000000..e88b5a3ff6e --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64f.d @@ -0,0 +1,21 @@ +#as: -march=rv32i_zve64f -mcsr-check +#source: vector-csrs.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64x.d b/gas/testsuite/gas/riscv/vector-csrs-zve64x.d new file mode 100644 index 00000000000..023dafb0364 --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64x.d @@ -0,0 +1,21 @@ +#as: -march=rv32i_zicsr_zve64x -mcsr-check +#source: vector-csrs.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/vector-csrs.s b/gas/testsuite/gas/riscv/vector-csrs.s new file mode 100644 index 00000000000..7019a0588ef --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-csrs.s @@ -0,0 +1,12 @@ +target: + csrr a0, vstart + csrw vstart, zero + csrr a0, vxsat + csrwi vxsat, 1 + csrr a0, vxrm + csrwi vxrm, 3 + csrr a0, vcsr + csrwi vcsr, 7 + csrr a0, vl + csrr a0, vtype + csrr a0, vlenb -- 2.34.1 ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/1] RISC-V: Fix vector CSR requirements 2022-09-08 6:53 ` [PATCH 1/1] RISC-V: Fix vector CSR requirements Tsukasa OI @ 2022-09-08 7:12 ` Nelson Chu 2022-09-08 7:15 ` Tsukasa OI 0 siblings, 1 reply; 17+ messages in thread From: Nelson Chu @ 2022-09-08 7:12 UTC (permalink / raw) To: Tsukasa OI; +Cc: Kito Cheng, Palmer Dabbelt, binutils On Thu, Sep 8, 2022 at 2:54 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote: > > Vector CSRs are also required on smaller vector subsets. > > Not only that the most of vector CSRs are general purpose (and must be > accessible for every vector subsets), current minimum vector subset 'Zve32x' > requires fixed point arithmetic, making remaining non-general purpose > (fixed point arithmetic only) CSRs mandatory for such subsets. > > So, those CSRs must be accessible from 'Zve32x', not just from 'V'. > This commit fixes this issue which caused CSR accessibility warnings. > > gas/ChangeLog: > > * config/tc-riscv.c (riscv_csr_address): Change vector CSR > requirement from 'V' to 'Zve32x'. > * testsuite/gas/riscv/csr-version-1p9p1.l: Change vector CSR > requirement from 'V' to 'Zve32x'. > * testsuite/gas/riscv/csr-version-1p10.l: Likewise. > * testsuite/gas/riscv/csr-version-1p11.l: Likewise. > * testsuite/gas/riscv/csr-version-1p12.l: Likewise. > * testsuite/gas/riscv/vector-csrs.s: New test. > * testsuite/gas/riscv/vector-csrs-v.d: Likewise. > * testsuite/gas/riscv/vector-csrs-zve32x.d: Likewise. > * testsuite/gas/riscv/vector-csrs-zve32f.d: Likewise. > * testsuite/gas/riscv/vector-csrs-zve64x.d: Likewise. > * testsuite/gas/riscv/vector-csrs-zve64f.d: Likewise. > * testsuite/gas/riscv/vector-csrs-zve64d.d: Likewise. These seem to test the implied rules of vector extensions, not so related to the csr tests. Otherwise looks good to me. Please update and then commit when you think it's time. Thanks Nelson > --- > gas/config/tc-riscv.c | 2 +- > gas/testsuite/gas/riscv/csr-version-1p10.l | 28 ++++++++++---------- > gas/testsuite/gas/riscv/csr-version-1p11.l | 28 ++++++++++---------- > gas/testsuite/gas/riscv/csr-version-1p12.l | 28 ++++++++++---------- > gas/testsuite/gas/riscv/csr-version-1p9p1.l | 28 ++++++++++---------- > gas/testsuite/gas/riscv/vector-csrs-v.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs-zve32f.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs-zve32x.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs-zve64d.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs-zve64f.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs-zve64x.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs.s | 12 +++++++++ > 12 files changed, 195 insertions(+), 57 deletions(-) > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-v.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32f.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32x.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64d.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64f.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64x.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs.s > > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index 34ce68e8252..df2e201fb74 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -935,7 +935,7 @@ riscv_csr_address (const char *csr_name, > extension = "zkr"; > break; > case CSR_CLASS_V: > - extension = "v"; > + extension = "zve32x"; > break; > case CSR_CLASS_SMSTATEEN: > case CSR_CLASS_SMSTATEEN_AND_H: > diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l > index b778453b556..999e9af1520 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p10.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l > @@ -652,20 +652,20 @@ > .*Warning: invalid CSR `fcsr', needs `f' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vl,a1' > -.*Warning: invalid CSR `vtype', needs `v' extension > -.*Warning: invalid CSR `vtype', needs `v' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vtype,a1' > -.*Warning: invalid CSR `vlenb', needs `v' extension > -.*Warning: invalid CSR `vlenb', needs `v' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vlenb,a1' > diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l > index 78bae817470..a099e4ecc93 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p11.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l > @@ -650,20 +650,20 @@ > .*Warning: invalid CSR `fcsr', needs `f' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vl,a1' > -.*Warning: invalid CSR `vtype', needs `v' extension > -.*Warning: invalid CSR `vtype', needs `v' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vtype,a1' > -.*Warning: invalid CSR `vlenb', needs `v' extension > -.*Warning: invalid CSR `vlenb', needs `v' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vlenb,a1' > diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l > index cb026bb55e0..cf8f2e25634 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p12.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l > @@ -532,20 +532,20 @@ > .*Warning: invalid CSR `fcsr', needs `f' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vl,a1' > -.*Warning: invalid CSR `vtype', needs `v' extension > -.*Warning: invalid CSR `vtype', needs `v' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vtype,a1' > -.*Warning: invalid CSR `vlenb', needs `v' extension > -.*Warning: invalid CSR `vlenb', needs `v' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vlenb,a1' > diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l > index 4fac40fb589..5f298c1dda9 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l > @@ -678,20 +678,20 @@ > .*Warning: invalid CSR `fcsr', needs `f' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > .*Warning: invalid CSR `seed', needs `zkr' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vstart', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxsat', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vxrm', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vcsr', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > -.*Warning: invalid CSR `vl', needs `v' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vstart', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxsat', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vxrm', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vcsr', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > +.*Warning: invalid CSR `vl', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vl,a1' > -.*Warning: invalid CSR `vtype', needs `v' extension > -.*Warning: invalid CSR `vtype', needs `v' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > +.*Warning: invalid CSR `vtype', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vtype,a1' > -.*Warning: invalid CSR `vlenb', needs `v' extension > -.*Warning: invalid CSR `vlenb', needs `v' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > +.*Warning: invalid CSR `vlenb', needs `zve32x' extension > .*Warning: read-only CSR is written `csrw vlenb,a1' > diff --git a/gas/testsuite/gas/riscv/vector-csrs-v.d b/gas/testsuite/gas/riscv/vector-csrs-v.d > new file mode 100644 > index 00000000000..1376f01d83e > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs-v.d > @@ -0,0 +1,21 @@ > +#as: -march=rv32iv -mcsr-check > +#source: vector-csrs.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart > +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero > +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat > +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 > +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm > +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 > +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr > +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 > +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl > +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype > +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve32f.d b/gas/testsuite/gas/riscv/vector-csrs-zve32f.d > new file mode 100644 > index 00000000000..9613915713b > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs-zve32f.d > @@ -0,0 +1,21 @@ > +#as: -march=rv32i_zve32f -mcsr-check > +#source: vector-csrs.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart > +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero > +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat > +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 > +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm > +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 > +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr > +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 > +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl > +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype > +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve32x.d b/gas/testsuite/gas/riscv/vector-csrs-zve32x.d > new file mode 100644 > index 00000000000..1e18d923e8c > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs-zve32x.d > @@ -0,0 +1,21 @@ > +#as: -march=rv32i_zicsr_zve32x -mcsr-check > +#source: vector-csrs.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart > +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero > +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat > +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 > +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm > +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 > +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr > +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 > +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl > +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype > +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64d.d b/gas/testsuite/gas/riscv/vector-csrs-zve64d.d > new file mode 100644 > index 00000000000..f42e670699a > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64d.d > @@ -0,0 +1,21 @@ > +#as: -march=rv32i_zve64d -mcsr-check > +#source: vector-csrs.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart > +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero > +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat > +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 > +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm > +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 > +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr > +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 > +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl > +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype > +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64f.d b/gas/testsuite/gas/riscv/vector-csrs-zve64f.d > new file mode 100644 > index 00000000000..e88b5a3ff6e > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64f.d > @@ -0,0 +1,21 @@ > +#as: -march=rv32i_zve64f -mcsr-check > +#source: vector-csrs.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart > +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero > +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat > +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 > +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm > +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 > +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr > +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 > +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl > +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype > +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64x.d b/gas/testsuite/gas/riscv/vector-csrs-zve64x.d > new file mode 100644 > index 00000000000..023dafb0364 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64x.d > @@ -0,0 +1,21 @@ > +#as: -march=rv32i_zicsr_zve64x -mcsr-check > +#source: vector-csrs.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 <target>: > +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart > +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero > +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat > +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 > +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm > +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 > +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr > +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 > +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl > +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype > +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > diff --git a/gas/testsuite/gas/riscv/vector-csrs.s b/gas/testsuite/gas/riscv/vector-csrs.s > new file mode 100644 > index 00000000000..7019a0588ef > --- /dev/null > +++ b/gas/testsuite/gas/riscv/vector-csrs.s > @@ -0,0 +1,12 @@ > +target: > + csrr a0, vstart > + csrw vstart, zero > + csrr a0, vxsat > + csrwi vxsat, 1 > + csrr a0, vxrm > + csrwi vxrm, 3 > + csrr a0, vcsr > + csrwi vcsr, 7 > + csrr a0, vl > + csrr a0, vtype > + csrr a0, vlenb > -- > 2.34.1 > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/1] RISC-V: Fix vector CSR requirements 2022-09-08 7:12 ` Nelson Chu @ 2022-09-08 7:15 ` Tsukasa OI 2022-09-08 7:20 ` Tsukasa OI 0 siblings, 1 reply; 17+ messages in thread From: Tsukasa OI @ 2022-09-08 7:15 UTC (permalink / raw) To: Nelson Chu; +Cc: Kito Cheng, Palmer Dabbelt, binutils On 2022/09/08 16:12, Nelson Chu wrote: > On Thu, Sep 8, 2022 at 2:54 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote: >> >> Vector CSRs are also required on smaller vector subsets. >> >> Not only that the most of vector CSRs are general purpose (and must be >> accessible for every vector subsets), current minimum vector subset 'Zve32x' >> requires fixed point arithmetic, making remaining non-general purpose >> (fixed point arithmetic only) CSRs mandatory for such subsets. >> >> So, those CSRs must be accessible from 'Zve32x', not just from 'V'. >> This commit fixes this issue which caused CSR accessibility warnings. >> >> gas/ChangeLog: >> >> * config/tc-riscv.c (riscv_csr_address): Change vector CSR >> requirement from 'V' to 'Zve32x'. >> * testsuite/gas/riscv/csr-version-1p9p1.l: Change vector CSR >> requirement from 'V' to 'Zve32x'. >> * testsuite/gas/riscv/csr-version-1p10.l: Likewise. >> * testsuite/gas/riscv/csr-version-1p11.l: Likewise. >> * testsuite/gas/riscv/csr-version-1p12.l: Likewise. > >> * testsuite/gas/riscv/vector-csrs.s: New test. >> * testsuite/gas/riscv/vector-csrs-v.d: Likewise. >> * testsuite/gas/riscv/vector-csrs-zve32x.d: Likewise. >> * testsuite/gas/riscv/vector-csrs-zve32f.d: Likewise. >> * testsuite/gas/riscv/vector-csrs-zve64x.d: Likewise. >> * testsuite/gas/riscv/vector-csrs-zve64f.d: Likewise. >> * testsuite/gas/riscv/vector-csrs-zve64d.d: Likewise. > > These seem to test the implied rules of vector extensions, not so > related to the csr tests. Otherwise looks good to me. Please update > and then commit when you think it's time. vector-csrs-zve32x.d and vector-csrs-zve64x.d has additional 'Zicsr' as I removed a CSR implication rule. Having six tests may be too much but can I at least keep vector-csrs-zve32x.d? Thanks, Tsukasa > > Thanks > Nelson > >> --- >> gas/config/tc-riscv.c | 2 +- >> gas/testsuite/gas/riscv/csr-version-1p10.l | 28 ++++++++++---------- >> gas/testsuite/gas/riscv/csr-version-1p11.l | 28 ++++++++++---------- >> gas/testsuite/gas/riscv/csr-version-1p12.l | 28 ++++++++++---------- >> gas/testsuite/gas/riscv/csr-version-1p9p1.l | 28 ++++++++++---------- >> gas/testsuite/gas/riscv/vector-csrs-v.d | 21 +++++++++++++++ >> gas/testsuite/gas/riscv/vector-csrs-zve32f.d | 21 +++++++++++++++ >> gas/testsuite/gas/riscv/vector-csrs-zve32x.d | 21 +++++++++++++++ >> gas/testsuite/gas/riscv/vector-csrs-zve64d.d | 21 +++++++++++++++ >> gas/testsuite/gas/riscv/vector-csrs-zve64f.d | 21 +++++++++++++++ >> gas/testsuite/gas/riscv/vector-csrs-zve64x.d | 21 +++++++++++++++ >> gas/testsuite/gas/riscv/vector-csrs.s | 12 +++++++++ >> 12 files changed, 195 insertions(+), 57 deletions(-) >> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-v.d >> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32f.d >> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32x.d >> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64d.d >> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64f.d >> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64x.d >> create mode 100644 gas/testsuite/gas/riscv/vector-csrs.s >> >> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c >> index 34ce68e8252..df2e201fb74 100644 >> --- a/gas/config/tc-riscv.c >> +++ b/gas/config/tc-riscv.c >> @@ -935,7 +935,7 @@ riscv_csr_address (const char *csr_name, >> extension = "zkr"; >> break; >> case CSR_CLASS_V: >> - extension = "v"; >> + extension = "zve32x"; >> break; >> case CSR_CLASS_SMSTATEEN: >> case CSR_CLASS_SMSTATEEN_AND_H: >> diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l >> index b778453b556..999e9af1520 100644 >> --- a/gas/testsuite/gas/riscv/csr-version-1p10.l >> +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l >> @@ -652,20 +652,20 @@ >> .*Warning: invalid CSR `fcsr', needs `f' extension >> .*Warning: invalid CSR `seed', needs `zkr' extension >> .*Warning: invalid CSR `seed', needs `zkr' extension >> -.*Warning: invalid CSR `vstart', needs `v' extension >> -.*Warning: invalid CSR `vstart', needs `v' extension >> -.*Warning: invalid CSR `vxsat', needs `v' extension >> -.*Warning: invalid CSR `vxsat', needs `v' extension >> -.*Warning: invalid CSR `vxrm', needs `v' extension >> -.*Warning: invalid CSR `vxrm', needs `v' extension >> -.*Warning: invalid CSR `vcsr', needs `v' extension >> -.*Warning: invalid CSR `vcsr', needs `v' extension >> -.*Warning: invalid CSR `vl', needs `v' extension >> -.*Warning: invalid CSR `vl', needs `v' extension >> +.*Warning: invalid CSR `vstart', needs `zve32x' extension >> +.*Warning: invalid CSR `vstart', needs `zve32x' extension >> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension >> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension >> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension >> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension >> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension >> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension >> +.*Warning: invalid CSR `vl', needs `zve32x' extension >> +.*Warning: invalid CSR `vl', needs `zve32x' extension >> .*Warning: read-only CSR is written `csrw vl,a1' >> -.*Warning: invalid CSR `vtype', needs `v' extension >> -.*Warning: invalid CSR `vtype', needs `v' extension >> +.*Warning: invalid CSR `vtype', needs `zve32x' extension >> +.*Warning: invalid CSR `vtype', needs `zve32x' extension >> .*Warning: read-only CSR is written `csrw vtype,a1' >> -.*Warning: invalid CSR `vlenb', needs `v' extension >> -.*Warning: invalid CSR `vlenb', needs `v' extension >> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension >> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension >> .*Warning: read-only CSR is written `csrw vlenb,a1' >> diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l >> index 78bae817470..a099e4ecc93 100644 >> --- a/gas/testsuite/gas/riscv/csr-version-1p11.l >> +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l >> @@ -650,20 +650,20 @@ >> .*Warning: invalid CSR `fcsr', needs `f' extension >> .*Warning: invalid CSR `seed', needs `zkr' extension >> .*Warning: invalid CSR `seed', needs `zkr' extension >> -.*Warning: invalid CSR `vstart', needs `v' extension >> -.*Warning: invalid CSR `vstart', needs `v' extension >> -.*Warning: invalid CSR `vxsat', needs `v' extension >> -.*Warning: invalid CSR `vxsat', needs `v' extension >> -.*Warning: invalid CSR `vxrm', needs `v' extension >> -.*Warning: invalid CSR `vxrm', needs `v' extension >> -.*Warning: invalid CSR `vcsr', needs `v' extension >> -.*Warning: invalid CSR `vcsr', needs `v' extension >> -.*Warning: invalid CSR `vl', needs `v' extension >> -.*Warning: invalid CSR `vl', needs `v' extension >> +.*Warning: invalid CSR `vstart', needs `zve32x' extension >> +.*Warning: invalid CSR `vstart', needs `zve32x' extension >> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension >> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension >> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension >> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension >> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension >> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension >> +.*Warning: invalid CSR `vl', needs `zve32x' extension >> +.*Warning: invalid CSR `vl', needs `zve32x' extension >> .*Warning: read-only CSR is written `csrw vl,a1' >> -.*Warning: invalid CSR `vtype', needs `v' extension >> -.*Warning: invalid CSR `vtype', needs `v' extension >> +.*Warning: invalid CSR `vtype', needs `zve32x' extension >> +.*Warning: invalid CSR `vtype', needs `zve32x' extension >> .*Warning: read-only CSR is written `csrw vtype,a1' >> -.*Warning: invalid CSR `vlenb', needs `v' extension >> -.*Warning: invalid CSR `vlenb', needs `v' extension >> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension >> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension >> .*Warning: read-only CSR is written `csrw vlenb,a1' >> diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l >> index cb026bb55e0..cf8f2e25634 100644 >> --- a/gas/testsuite/gas/riscv/csr-version-1p12.l >> +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l >> @@ -532,20 +532,20 @@ >> .*Warning: invalid CSR `fcsr', needs `f' extension >> .*Warning: invalid CSR `seed', needs `zkr' extension >> .*Warning: invalid CSR `seed', needs `zkr' extension >> -.*Warning: invalid CSR `vstart', needs `v' extension >> -.*Warning: invalid CSR `vstart', needs `v' extension >> -.*Warning: invalid CSR `vxsat', needs `v' extension >> -.*Warning: invalid CSR `vxsat', needs `v' extension >> -.*Warning: invalid CSR `vxrm', needs `v' extension >> -.*Warning: invalid CSR `vxrm', needs `v' extension >> -.*Warning: invalid CSR `vcsr', needs `v' extension >> -.*Warning: invalid CSR `vcsr', needs `v' extension >> -.*Warning: invalid CSR `vl', needs `v' extension >> -.*Warning: invalid CSR `vl', needs `v' extension >> +.*Warning: invalid CSR `vstart', needs `zve32x' extension >> +.*Warning: invalid CSR `vstart', needs `zve32x' extension >> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension >> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension >> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension >> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension >> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension >> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension >> +.*Warning: invalid CSR `vl', needs `zve32x' extension >> +.*Warning: invalid CSR `vl', needs `zve32x' extension >> .*Warning: read-only CSR is written `csrw vl,a1' >> -.*Warning: invalid CSR `vtype', needs `v' extension >> -.*Warning: invalid CSR `vtype', needs `v' extension >> +.*Warning: invalid CSR `vtype', needs `zve32x' extension >> +.*Warning: invalid CSR `vtype', needs `zve32x' extension >> .*Warning: read-only CSR is written `csrw vtype,a1' >> -.*Warning: invalid CSR `vlenb', needs `v' extension >> -.*Warning: invalid CSR `vlenb', needs `v' extension >> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension >> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension >> .*Warning: read-only CSR is written `csrw vlenb,a1' >> diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l >> index 4fac40fb589..5f298c1dda9 100644 >> --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l >> +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l >> @@ -678,20 +678,20 @@ >> .*Warning: invalid CSR `fcsr', needs `f' extension >> .*Warning: invalid CSR `seed', needs `zkr' extension >> .*Warning: invalid CSR `seed', needs `zkr' extension >> -.*Warning: invalid CSR `vstart', needs `v' extension >> -.*Warning: invalid CSR `vstart', needs `v' extension >> -.*Warning: invalid CSR `vxsat', needs `v' extension >> -.*Warning: invalid CSR `vxsat', needs `v' extension >> -.*Warning: invalid CSR `vxrm', needs `v' extension >> -.*Warning: invalid CSR `vxrm', needs `v' extension >> -.*Warning: invalid CSR `vcsr', needs `v' extension >> -.*Warning: invalid CSR `vcsr', needs `v' extension >> -.*Warning: invalid CSR `vl', needs `v' extension >> -.*Warning: invalid CSR `vl', needs `v' extension >> +.*Warning: invalid CSR `vstart', needs `zve32x' extension >> +.*Warning: invalid CSR `vstart', needs `zve32x' extension >> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension >> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension >> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension >> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension >> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension >> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension >> +.*Warning: invalid CSR `vl', needs `zve32x' extension >> +.*Warning: invalid CSR `vl', needs `zve32x' extension >> .*Warning: read-only CSR is written `csrw vl,a1' >> -.*Warning: invalid CSR `vtype', needs `v' extension >> -.*Warning: invalid CSR `vtype', needs `v' extension >> +.*Warning: invalid CSR `vtype', needs `zve32x' extension >> +.*Warning: invalid CSR `vtype', needs `zve32x' extension >> .*Warning: read-only CSR is written `csrw vtype,a1' >> -.*Warning: invalid CSR `vlenb', needs `v' extension >> -.*Warning: invalid CSR `vlenb', needs `v' extension >> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension >> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension >> .*Warning: read-only CSR is written `csrw vlenb,a1' >> diff --git a/gas/testsuite/gas/riscv/vector-csrs-v.d b/gas/testsuite/gas/riscv/vector-csrs-v.d >> new file mode 100644 >> index 00000000000..1376f01d83e >> --- /dev/null >> +++ b/gas/testsuite/gas/riscv/vector-csrs-v.d >> @@ -0,0 +1,21 @@ >> +#as: -march=rv32iv -mcsr-check >> +#source: vector-csrs.s >> +#objdump: -d >> + >> +.*:[ ]+file format .* >> + >> + >> +Disassembly of section .text: >> + >> +0+000 <target>: >> +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart >> +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero >> +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat >> +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 >> +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm >> +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 >> +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr >> +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 >> +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl >> +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype >> +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb >> diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve32f.d b/gas/testsuite/gas/riscv/vector-csrs-zve32f.d >> new file mode 100644 >> index 00000000000..9613915713b >> --- /dev/null >> +++ b/gas/testsuite/gas/riscv/vector-csrs-zve32f.d >> @@ -0,0 +1,21 @@ >> +#as: -march=rv32i_zve32f -mcsr-check >> +#source: vector-csrs.s >> +#objdump: -d >> + >> +.*:[ ]+file format .* >> + >> + >> +Disassembly of section .text: >> + >> +0+000 <target>: >> +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart >> +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero >> +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat >> +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 >> +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm >> +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 >> +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr >> +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 >> +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl >> +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype >> +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb >> diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve32x.d b/gas/testsuite/gas/riscv/vector-csrs-zve32x.d >> new file mode 100644 >> index 00000000000..1e18d923e8c >> --- /dev/null >> +++ b/gas/testsuite/gas/riscv/vector-csrs-zve32x.d >> @@ -0,0 +1,21 @@ >> +#as: -march=rv32i_zicsr_zve32x -mcsr-check >> +#source: vector-csrs.s >> +#objdump: -d >> + >> +.*:[ ]+file format .* >> + >> + >> +Disassembly of section .text: >> + >> +0+000 <target>: >> +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart >> +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero >> +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat >> +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 >> +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm >> +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 >> +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr >> +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 >> +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl >> +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype >> +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb >> diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64d.d b/gas/testsuite/gas/riscv/vector-csrs-zve64d.d >> new file mode 100644 >> index 00000000000..f42e670699a >> --- /dev/null >> +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64d.d >> @@ -0,0 +1,21 @@ >> +#as: -march=rv32i_zve64d -mcsr-check >> +#source: vector-csrs.s >> +#objdump: -d >> + >> +.*:[ ]+file format .* >> + >> + >> +Disassembly of section .text: >> + >> +0+000 <target>: >> +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart >> +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero >> +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat >> +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 >> +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm >> +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 >> +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr >> +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 >> +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl >> +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype >> +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb >> diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64f.d b/gas/testsuite/gas/riscv/vector-csrs-zve64f.d >> new file mode 100644 >> index 00000000000..e88b5a3ff6e >> --- /dev/null >> +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64f.d >> @@ -0,0 +1,21 @@ >> +#as: -march=rv32i_zve64f -mcsr-check >> +#source: vector-csrs.s >> +#objdump: -d >> + >> +.*:[ ]+file format .* >> + >> + >> +Disassembly of section .text: >> + >> +0+000 <target>: >> +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart >> +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero >> +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat >> +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 >> +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm >> +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 >> +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr >> +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 >> +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl >> +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype >> +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb >> diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64x.d b/gas/testsuite/gas/riscv/vector-csrs-zve64x.d >> new file mode 100644 >> index 00000000000..023dafb0364 >> --- /dev/null >> +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64x.d >> @@ -0,0 +1,21 @@ >> +#as: -march=rv32i_zicsr_zve64x -mcsr-check >> +#source: vector-csrs.s >> +#objdump: -d >> + >> +.*:[ ]+file format .* >> + >> + >> +Disassembly of section .text: >> + >> +0+000 <target>: >> +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart >> +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero >> +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat >> +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 >> +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm >> +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 >> +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr >> +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 >> +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl >> +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype >> +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb >> diff --git a/gas/testsuite/gas/riscv/vector-csrs.s b/gas/testsuite/gas/riscv/vector-csrs.s >> new file mode 100644 >> index 00000000000..7019a0588ef >> --- /dev/null >> +++ b/gas/testsuite/gas/riscv/vector-csrs.s >> @@ -0,0 +1,12 @@ >> +target: >> + csrr a0, vstart >> + csrw vstart, zero >> + csrr a0, vxsat >> + csrwi vxsat, 1 >> + csrr a0, vxrm >> + csrwi vxrm, 3 >> + csrr a0, vcsr >> + csrwi vcsr, 7 >> + csrr a0, vl >> + csrr a0, vtype >> + csrr a0, vlenb >> -- >> 2.34.1 >> > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/1] RISC-V: Fix vector CSR requirements 2022-09-08 7:15 ` Tsukasa OI @ 2022-09-08 7:20 ` Tsukasa OI 0 siblings, 0 replies; 17+ messages in thread From: Tsukasa OI @ 2022-09-08 7:20 UTC (permalink / raw) To: Nelson Chu; +Cc: Kito Cheng, Palmer Dabbelt, binutils On 2022/09/08 16:15, Tsukasa OI wrote: > On 2022/09/08 16:12, Nelson Chu wrote: >> On Thu, Sep 8, 2022 at 2:54 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote: >>> >>> Vector CSRs are also required on smaller vector subsets. >>> >>> Not only that the most of vector CSRs are general purpose (and must be >>> accessible for every vector subsets), current minimum vector subset 'Zve32x' >>> requires fixed point arithmetic, making remaining non-general purpose >>> (fixed point arithmetic only) CSRs mandatory for such subsets. >>> >>> So, those CSRs must be accessible from 'Zve32x', not just from 'V'. >>> This commit fixes this issue which caused CSR accessibility warnings. >>> >>> gas/ChangeLog: >>> >>> * config/tc-riscv.c (riscv_csr_address): Change vector CSR >>> requirement from 'V' to 'Zve32x'. >>> * testsuite/gas/riscv/csr-version-1p9p1.l: Change vector CSR >>> requirement from 'V' to 'Zve32x'. >>> * testsuite/gas/riscv/csr-version-1p10.l: Likewise. >>> * testsuite/gas/riscv/csr-version-1p11.l: Likewise. >>> * testsuite/gas/riscv/csr-version-1p12.l: Likewise. >> >>> * testsuite/gas/riscv/vector-csrs.s: New test. >>> * testsuite/gas/riscv/vector-csrs-v.d: Likewise. >>> * testsuite/gas/riscv/vector-csrs-zve32x.d: Likewise. >>> * testsuite/gas/riscv/vector-csrs-zve32f.d: Likewise. >>> * testsuite/gas/riscv/vector-csrs-zve64x.d: Likewise. >>> * testsuite/gas/riscv/vector-csrs-zve64f.d: Likewise. >>> * testsuite/gas/riscv/vector-csrs-zve64d.d: Likewise. >> >> These seem to test the implied rules of vector extensions, not so >> related to the csr tests. Otherwise looks good to me. Please update >> and then commit when you think it's time. > > vector-csrs-zve32x.d and vector-csrs-zve64x.d has additional 'Zicsr' as > I removed a CSR implication rule. Having six tests may be too much but > can I at least keep vector-csrs-zve32x.d? ... and vector-csrs-v.d (to make sure that the 'V' extension is not broken). > > Thanks, > Tsukasa > >> >> Thanks >> Nelson >> >>> --- >>> gas/config/tc-riscv.c | 2 +- >>> gas/testsuite/gas/riscv/csr-version-1p10.l | 28 ++++++++++---------- >>> gas/testsuite/gas/riscv/csr-version-1p11.l | 28 ++++++++++---------- >>> gas/testsuite/gas/riscv/csr-version-1p12.l | 28 ++++++++++---------- >>> gas/testsuite/gas/riscv/csr-version-1p9p1.l | 28 ++++++++++---------- >>> gas/testsuite/gas/riscv/vector-csrs-v.d | 21 +++++++++++++++ >>> gas/testsuite/gas/riscv/vector-csrs-zve32f.d | 21 +++++++++++++++ >>> gas/testsuite/gas/riscv/vector-csrs-zve32x.d | 21 +++++++++++++++ >>> gas/testsuite/gas/riscv/vector-csrs-zve64d.d | 21 +++++++++++++++ >>> gas/testsuite/gas/riscv/vector-csrs-zve64f.d | 21 +++++++++++++++ >>> gas/testsuite/gas/riscv/vector-csrs-zve64x.d | 21 +++++++++++++++ >>> gas/testsuite/gas/riscv/vector-csrs.s | 12 +++++++++ >>> 12 files changed, 195 insertions(+), 57 deletions(-) >>> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-v.d >>> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32f.d >>> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32x.d >>> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64d.d >>> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64f.d >>> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64x.d >>> create mode 100644 gas/testsuite/gas/riscv/vector-csrs.s >>> >>> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c >>> index 34ce68e8252..df2e201fb74 100644 >>> --- a/gas/config/tc-riscv.c >>> +++ b/gas/config/tc-riscv.c >>> @@ -935,7 +935,7 @@ riscv_csr_address (const char *csr_name, >>> extension = "zkr"; >>> break; >>> case CSR_CLASS_V: >>> - extension = "v"; >>> + extension = "zve32x"; >>> break; >>> case CSR_CLASS_SMSTATEEN: >>> case CSR_CLASS_SMSTATEEN_AND_H: >>> diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l >>> index b778453b556..999e9af1520 100644 >>> --- a/gas/testsuite/gas/riscv/csr-version-1p10.l >>> +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l >>> @@ -652,20 +652,20 @@ >>> .*Warning: invalid CSR `fcsr', needs `f' extension >>> .*Warning: invalid CSR `seed', needs `zkr' extension >>> .*Warning: invalid CSR `seed', needs `zkr' extension >>> -.*Warning: invalid CSR `vstart', needs `v' extension >>> -.*Warning: invalid CSR `vstart', needs `v' extension >>> -.*Warning: invalid CSR `vxsat', needs `v' extension >>> -.*Warning: invalid CSR `vxsat', needs `v' extension >>> -.*Warning: invalid CSR `vxrm', needs `v' extension >>> -.*Warning: invalid CSR `vxrm', needs `v' extension >>> -.*Warning: invalid CSR `vcsr', needs `v' extension >>> -.*Warning: invalid CSR `vcsr', needs `v' extension >>> -.*Warning: invalid CSR `vl', needs `v' extension >>> -.*Warning: invalid CSR `vl', needs `v' extension >>> +.*Warning: invalid CSR `vstart', needs `zve32x' extension >>> +.*Warning: invalid CSR `vstart', needs `zve32x' extension >>> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension >>> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension >>> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension >>> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension >>> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension >>> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension >>> +.*Warning: invalid CSR `vl', needs `zve32x' extension >>> +.*Warning: invalid CSR `vl', needs `zve32x' extension >>> .*Warning: read-only CSR is written `csrw vl,a1' >>> -.*Warning: invalid CSR `vtype', needs `v' extension >>> -.*Warning: invalid CSR `vtype', needs `v' extension >>> +.*Warning: invalid CSR `vtype', needs `zve32x' extension >>> +.*Warning: invalid CSR `vtype', needs `zve32x' extension >>> .*Warning: read-only CSR is written `csrw vtype,a1' >>> -.*Warning: invalid CSR `vlenb', needs `v' extension >>> -.*Warning: invalid CSR `vlenb', needs `v' extension >>> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension >>> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension >>> .*Warning: read-only CSR is written `csrw vlenb,a1' >>> diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l >>> index 78bae817470..a099e4ecc93 100644 >>> --- a/gas/testsuite/gas/riscv/csr-version-1p11.l >>> +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l >>> @@ -650,20 +650,20 @@ >>> .*Warning: invalid CSR `fcsr', needs `f' extension >>> .*Warning: invalid CSR `seed', needs `zkr' extension >>> .*Warning: invalid CSR `seed', needs `zkr' extension >>> -.*Warning: invalid CSR `vstart', needs `v' extension >>> -.*Warning: invalid CSR `vstart', needs `v' extension >>> -.*Warning: invalid CSR `vxsat', needs `v' extension >>> -.*Warning: invalid CSR `vxsat', needs `v' extension >>> -.*Warning: invalid CSR `vxrm', needs `v' extension >>> -.*Warning: invalid CSR `vxrm', needs `v' extension >>> -.*Warning: invalid CSR `vcsr', needs `v' extension >>> -.*Warning: invalid CSR `vcsr', needs `v' extension >>> -.*Warning: invalid CSR `vl', needs `v' extension >>> -.*Warning: invalid CSR `vl', needs `v' extension >>> +.*Warning: invalid CSR `vstart', needs `zve32x' extension >>> +.*Warning: invalid CSR `vstart', needs `zve32x' extension >>> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension >>> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension >>> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension >>> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension >>> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension >>> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension >>> +.*Warning: invalid CSR `vl', needs `zve32x' extension >>> +.*Warning: invalid CSR `vl', needs `zve32x' extension >>> .*Warning: read-only CSR is written `csrw vl,a1' >>> -.*Warning: invalid CSR `vtype', needs `v' extension >>> -.*Warning: invalid CSR `vtype', needs `v' extension >>> +.*Warning: invalid CSR `vtype', needs `zve32x' extension >>> +.*Warning: invalid CSR `vtype', needs `zve32x' extension >>> .*Warning: read-only CSR is written `csrw vtype,a1' >>> -.*Warning: invalid CSR `vlenb', needs `v' extension >>> -.*Warning: invalid CSR `vlenb', needs `v' extension >>> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension >>> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension >>> .*Warning: read-only CSR is written `csrw vlenb,a1' >>> diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l >>> index cb026bb55e0..cf8f2e25634 100644 >>> --- a/gas/testsuite/gas/riscv/csr-version-1p12.l >>> +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l >>> @@ -532,20 +532,20 @@ >>> .*Warning: invalid CSR `fcsr', needs `f' extension >>> .*Warning: invalid CSR `seed', needs `zkr' extension >>> .*Warning: invalid CSR `seed', needs `zkr' extension >>> -.*Warning: invalid CSR `vstart', needs `v' extension >>> -.*Warning: invalid CSR `vstart', needs `v' extension >>> -.*Warning: invalid CSR `vxsat', needs `v' extension >>> -.*Warning: invalid CSR `vxsat', needs `v' extension >>> -.*Warning: invalid CSR `vxrm', needs `v' extension >>> -.*Warning: invalid CSR `vxrm', needs `v' extension >>> -.*Warning: invalid CSR `vcsr', needs `v' extension >>> -.*Warning: invalid CSR `vcsr', needs `v' extension >>> -.*Warning: invalid CSR `vl', needs `v' extension >>> -.*Warning: invalid CSR `vl', needs `v' extension >>> +.*Warning: invalid CSR `vstart', needs `zve32x' extension >>> +.*Warning: invalid CSR `vstart', needs `zve32x' extension >>> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension >>> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension >>> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension >>> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension >>> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension >>> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension >>> +.*Warning: invalid CSR `vl', needs `zve32x' extension >>> +.*Warning: invalid CSR `vl', needs `zve32x' extension >>> .*Warning: read-only CSR is written `csrw vl,a1' >>> -.*Warning: invalid CSR `vtype', needs `v' extension >>> -.*Warning: invalid CSR `vtype', needs `v' extension >>> +.*Warning: invalid CSR `vtype', needs `zve32x' extension >>> +.*Warning: invalid CSR `vtype', needs `zve32x' extension >>> .*Warning: read-only CSR is written `csrw vtype,a1' >>> -.*Warning: invalid CSR `vlenb', needs `v' extension >>> -.*Warning: invalid CSR `vlenb', needs `v' extension >>> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension >>> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension >>> .*Warning: read-only CSR is written `csrw vlenb,a1' >>> diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l >>> index 4fac40fb589..5f298c1dda9 100644 >>> --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l >>> +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l >>> @@ -678,20 +678,20 @@ >>> .*Warning: invalid CSR `fcsr', needs `f' extension >>> .*Warning: invalid CSR `seed', needs `zkr' extension >>> .*Warning: invalid CSR `seed', needs `zkr' extension >>> -.*Warning: invalid CSR `vstart', needs `v' extension >>> -.*Warning: invalid CSR `vstart', needs `v' extension >>> -.*Warning: invalid CSR `vxsat', needs `v' extension >>> -.*Warning: invalid CSR `vxsat', needs `v' extension >>> -.*Warning: invalid CSR `vxrm', needs `v' extension >>> -.*Warning: invalid CSR `vxrm', needs `v' extension >>> -.*Warning: invalid CSR `vcsr', needs `v' extension >>> -.*Warning: invalid CSR `vcsr', needs `v' extension >>> -.*Warning: invalid CSR `vl', needs `v' extension >>> -.*Warning: invalid CSR `vl', needs `v' extension >>> +.*Warning: invalid CSR `vstart', needs `zve32x' extension >>> +.*Warning: invalid CSR `vstart', needs `zve32x' extension >>> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension >>> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension >>> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension >>> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension >>> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension >>> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension >>> +.*Warning: invalid CSR `vl', needs `zve32x' extension >>> +.*Warning: invalid CSR `vl', needs `zve32x' extension >>> .*Warning: read-only CSR is written `csrw vl,a1' >>> -.*Warning: invalid CSR `vtype', needs `v' extension >>> -.*Warning: invalid CSR `vtype', needs `v' extension >>> +.*Warning: invalid CSR `vtype', needs `zve32x' extension >>> +.*Warning: invalid CSR `vtype', needs `zve32x' extension >>> .*Warning: read-only CSR is written `csrw vtype,a1' >>> -.*Warning: invalid CSR `vlenb', needs `v' extension >>> -.*Warning: invalid CSR `vlenb', needs `v' extension >>> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension >>> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension >>> .*Warning: read-only CSR is written `csrw vlenb,a1' >>> diff --git a/gas/testsuite/gas/riscv/vector-csrs-v.d b/gas/testsuite/gas/riscv/vector-csrs-v.d >>> new file mode 100644 >>> index 00000000000..1376f01d83e >>> --- /dev/null >>> +++ b/gas/testsuite/gas/riscv/vector-csrs-v.d >>> @@ -0,0 +1,21 @@ >>> +#as: -march=rv32iv -mcsr-check >>> +#source: vector-csrs.s >>> +#objdump: -d >>> + >>> +.*:[ ]+file format .* >>> + >>> + >>> +Disassembly of section .text: >>> + >>> +0+000 <target>: >>> +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart >>> +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero >>> +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat >>> +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 >>> +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm >>> +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 >>> +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr >>> +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 >>> +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl >>> +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype >>> +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb >>> diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve32f.d b/gas/testsuite/gas/riscv/vector-csrs-zve32f.d >>> new file mode 100644 >>> index 00000000000..9613915713b >>> --- /dev/null >>> +++ b/gas/testsuite/gas/riscv/vector-csrs-zve32f.d >>> @@ -0,0 +1,21 @@ >>> +#as: -march=rv32i_zve32f -mcsr-check >>> +#source: vector-csrs.s >>> +#objdump: -d >>> + >>> +.*:[ ]+file format .* >>> + >>> + >>> +Disassembly of section .text: >>> + >>> +0+000 <target>: >>> +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart >>> +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero >>> +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat >>> +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 >>> +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm >>> +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 >>> +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr >>> +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 >>> +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl >>> +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype >>> +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb >>> diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve32x.d b/gas/testsuite/gas/riscv/vector-csrs-zve32x.d >>> new file mode 100644 >>> index 00000000000..1e18d923e8c >>> --- /dev/null >>> +++ b/gas/testsuite/gas/riscv/vector-csrs-zve32x.d >>> @@ -0,0 +1,21 @@ >>> +#as: -march=rv32i_zicsr_zve32x -mcsr-check >>> +#source: vector-csrs.s >>> +#objdump: -d >>> + >>> +.*:[ ]+file format .* >>> + >>> + >>> +Disassembly of section .text: >>> + >>> +0+000 <target>: >>> +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart >>> +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero >>> +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat >>> +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 >>> +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm >>> +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 >>> +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr >>> +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 >>> +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl >>> +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype >>> +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb >>> diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64d.d b/gas/testsuite/gas/riscv/vector-csrs-zve64d.d >>> new file mode 100644 >>> index 00000000000..f42e670699a >>> --- /dev/null >>> +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64d.d >>> @@ -0,0 +1,21 @@ >>> +#as: -march=rv32i_zve64d -mcsr-check >>> +#source: vector-csrs.s >>> +#objdump: -d >>> + >>> +.*:[ ]+file format .* >>> + >>> + >>> +Disassembly of section .text: >>> + >>> +0+000 <target>: >>> +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart >>> +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero >>> +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat >>> +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 >>> +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm >>> +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 >>> +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr >>> +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 >>> +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl >>> +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype >>> +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb >>> diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64f.d b/gas/testsuite/gas/riscv/vector-csrs-zve64f.d >>> new file mode 100644 >>> index 00000000000..e88b5a3ff6e >>> --- /dev/null >>> +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64f.d >>> @@ -0,0 +1,21 @@ >>> +#as: -march=rv32i_zve64f -mcsr-check >>> +#source: vector-csrs.s >>> +#objdump: -d >>> + >>> +.*:[ ]+file format .* >>> + >>> + >>> +Disassembly of section .text: >>> + >>> +0+000 <target>: >>> +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart >>> +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero >>> +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat >>> +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 >>> +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm >>> +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 >>> +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr >>> +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 >>> +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl >>> +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype >>> +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb >>> diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64x.d b/gas/testsuite/gas/riscv/vector-csrs-zve64x.d >>> new file mode 100644 >>> index 00000000000..023dafb0364 >>> --- /dev/null >>> +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64x.d >>> @@ -0,0 +1,21 @@ >>> +#as: -march=rv32i_zicsr_zve64x -mcsr-check >>> +#source: vector-csrs.s >>> +#objdump: -d >>> + >>> +.*:[ ]+file format .* >>> + >>> + >>> +Disassembly of section .text: >>> + >>> +0+000 <target>: >>> +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart >>> +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero >>> +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat >>> +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1 >>> +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm >>> +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3 >>> +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr >>> +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7 >>> +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl >>> +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype >>> +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb >>> diff --git a/gas/testsuite/gas/riscv/vector-csrs.s b/gas/testsuite/gas/riscv/vector-csrs.s >>> new file mode 100644 >>> index 00000000000..7019a0588ef >>> --- /dev/null >>> +++ b/gas/testsuite/gas/riscv/vector-csrs.s >>> @@ -0,0 +1,12 @@ >>> +target: >>> + csrr a0, vstart >>> + csrw vstart, zero >>> + csrr a0, vxsat >>> + csrwi vxsat, 1 >>> + csrr a0, vxrm >>> + csrwi vxrm, 3 >>> + csrr a0, vcsr >>> + csrwi vcsr, 7 >>> + csrr a0, vl >>> + csrr a0, vtype >>> + csrr a0, vlenb >>> -- >>> 2.34.1 >>> >> ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/3] RISC-V: Fix CSR accessibility and implications 2022-09-07 5:53 [PATCH 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI ` (3 preceding siblings ...) 2022-09-07 6:21 ` [PATCH v2 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI @ 2022-09-07 8:49 ` Nelson Chu 2022-09-07 9:08 ` Tsukasa OI 4 siblings, 1 reply; 17+ messages in thread From: Nelson Chu @ 2022-09-07 8:49 UTC (permalink / raw) To: Tsukasa OI; +Cc: Kito Cheng, Palmer Dabbelt, binutils On Wed, Sep 7, 2022 at 1:54 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote: > > Tracker on GitHub: > <https://github.com/a4lg/binutils-gdb/wiki/riscv_fix_csr_access_and_imply> > > While I'm reorganizing "b-ext*" and "k-ext*" tests (to make sure that they > are able to be removed since there are neither 'B' nor 'K' extensions), > I found something interesting. > > If we assemble a file with "csrr a0, seed" (uses "seed" CSR from the 'Zkr' > extension) with "-march=rv32i_zkr", it causes an error to require 'Zicsr'. > Yes, current GNU Binutils does not imply 'Zicsr' from 'Zkr' so that adding > 'Zkr' extension alone is not enough to access corresponding CSRs > (current version requires an option like "-march=rv32i_zicsr_zkr"). > "k-ext.d" does not give 'Zicsr' either (and does not test the seed CSR) and > adding the line "csrr a0, seed" to this test file resulted the same. According to the ISA spec, Zicsr is the sub-extension of i, and is used to control the csr instructions, so I don't see any conflict for the current toolchain. Though it looks weird that we allow csrs but need to enable csr instruction by another extension. If you still have problems, you can create and raise an issue maybe in riscv-isa-manual or riscv-v-spec, to clarify if the zicsr controls both csr and csr instructions. Maybe it's worth clarifying this, since LLVM doesn't recognize zicsr in the main branch. > That means something. If an extension adds CSR(s), we should imply 'Zicsr' > from that extension (just like 'F'). So, we have to imply 'Zicsr' from > following extensions: > > - 'H' > - 'Zkr' > - 'Zve32x' (I'll talk later) > - 'Smstateen' > - 'Sscofpmf' > - 'Sstc' > > 'Zkr' is fixed in PATCH 2/3 and 'H' and 'S*' are fixed in PATCH 3/3. > The only remaining extension is 'Zve32x' but I need to talk more to explain > actual changes (specific to vectors) in PATCH 1/3. > > On the current version of GNU Binutils, CSRs with CSR_CLASS_V means they > require the 'V' extension. However, there are a few vector subextensions > that implement vector subsets (intended for embedded processors). Check zve32x for vcsr should be enough, since LLVM looks to did the similar thing for vector instructions, https://github.com/llvm/llvm-project/blob/7167a4207ee2c07cb192da1788f919332f83b456/llvm/lib/Support/RISCVISAInfo.cpp#L708 > - 'Zve64d' (superset of 'Zve64f') > - 'Zve64f' (superset of 'Zve32f' and 'Zve64x') > - 'Zve64x' (superset of 'Zve32x') > - 'Zve32f' (superset of 'Zve32x') > - 'Zve32x' > > : Graph: Dependency graph of some vector/FP extensions > : > : +-------> D --------> F -----> Zicsr > : | ^ ^ > : | | | > : V ---> Zve64d ---> Zve64f ---> Zve64x > : | | > : V V > : Zve32f ---> Zve32x > : | > : | > : +---> (Zicsr [added in PATCH 1/3]) > > They also require general purpose vector CSRs (vstart, vl, vtype and vlenb). > So, corresponding CSR_CLASS_V with the 'V' extension is inappropriate > (they should require 'Zve32x' instead, the minimum vector subset). > > Remaining CSRs are: > > - vxsat > - vxrm > - vcsr > > They are related to fixed-point arithmetic and 18.2 "Zve*: Vector Extensions > for Embedded Processors" says: > > > All Zve* extensions support all vector fixed-point arithmetic instructions > > (Vector Fixed-Point Arithmetic Instructions), except that vsmul.vv and > > vsmul.vx are not supported for EEW=64 in Zve64*. > > So, their minimum requirement shall be also 'Zve32x', not 'V'. > > As a consequence, we can conclude that changing requirements of CSR_CLASS_V > from 'V' to 'Zve32x' is sufficient to avoid CSR accessibility warnings. > > Also, 'Zve32x' must imply 'Zicsr' (just like the rest) to avoid CSR > instruction errors. This is only effective on 'Zve32x' and 'Zve64x' > because, for instance, 'Zve32f' implies 'F' and 'F' implies 'Zicsr' > (see the graph above). > > I didn't rename CSR_CLASS_V to CSR_CLASS_ZVE32X because the name gets > difficult and there's already INSN_CLASS_V (effectively requires 'Zve32x' > with some exceptions). > > > > > Tsukasa OI (3): > RISC-V: Fix vector CSR requirements and imply > RISC-V: Imply 'Zicsr' from 'Zkr' > RISC-V: Imply 'Zicsr' from some privileged extensions > > bfd/elfxx-riscv.c | 6 +++++ > gas/config/tc-riscv.c | 2 +- > gas/testsuite/gas/riscv/csr-version-1p10.l | 28 ++++++++++---------- > gas/testsuite/gas/riscv/csr-version-1p11.l | 28 ++++++++++---------- > gas/testsuite/gas/riscv/csr-version-1p12.l | 28 ++++++++++---------- > gas/testsuite/gas/riscv/csr-version-1p9p1.l | 28 ++++++++++---------- > gas/testsuite/gas/riscv/march-imply-h.d | 6 +++++ > gas/testsuite/gas/riscv/vector-csrs-zve32f.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs-zve32x.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs-zve64d.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs-zve64f.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs-zve64x.d | 21 +++++++++++++++ > gas/testsuite/gas/riscv/vector-csrs.s | 12 +++++++++ > gas/testsuite/gas/riscv/zkr.d | 10 +++++++ > gas/testsuite/gas/riscv/zkr.s | 2 ++ > 15 files changed, 198 insertions(+), 57 deletions(-) > create mode 100644 gas/testsuite/gas/riscv/march-imply-h.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32f.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32x.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64d.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64f.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64x.d > create mode 100644 gas/testsuite/gas/riscv/vector-csrs.s > create mode 100644 gas/testsuite/gas/riscv/zkr.d > create mode 100644 gas/testsuite/gas/riscv/zkr.s > > > base-commit: f555b327d41ed72ffae28caae550f5f86312db43 > -- > 2.34.1 > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/3] RISC-V: Fix CSR accessibility and implications 2022-09-07 8:49 ` [PATCH 0/3] RISC-V: Fix CSR accessibility and implications Nelson Chu @ 2022-09-07 9:08 ` Tsukasa OI 0 siblings, 0 replies; 17+ messages in thread From: Tsukasa OI @ 2022-09-07 9:08 UTC (permalink / raw) To: Nelson Chu; +Cc: binutils On 2022/09/07 17:49, Nelson Chu wrote: > On Wed, Sep 7, 2022 at 1:54 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote: >> >> Tracker on GitHub: >> <https://github.com/a4lg/binutils-gdb/wiki/riscv_fix_csr_access_and_imply> >> >> While I'm reorganizing "b-ext*" and "k-ext*" tests (to make sure that they >> are able to be removed since there are neither 'B' nor 'K' extensions), >> I found something interesting. >> >> If we assemble a file with "csrr a0, seed" (uses "seed" CSR from the 'Zkr' >> extension) with "-march=rv32i_zkr", it causes an error to require 'Zicsr'. >> Yes, current GNU Binutils does not imply 'Zicsr' from 'Zkr' so that adding >> 'Zkr' extension alone is not enough to access corresponding CSRs >> (current version requires an option like "-march=rv32i_zicsr_zkr"). >> "k-ext.d" does not give 'Zicsr' either (and does not test the seed CSR) and >> adding the line "csrr a0, seed" to this test file resulted the same. > > According to the ISA spec, Zicsr is the sub-extension of i, and is > used to control the csr instructions, so I don't see any conflict for > the current toolchain. Though it looks weird that we allow csrs but > need to enable csr instruction by another extension. If you still > have problems, you can create and raise an issue maybe in > riscv-isa-manual or riscv-v-spec, to clarify if the zicsr controls > both csr and csr instructions. Maybe it's worth clarifying this, > since LLVM doesn't recognize zicsr in the main branch. I remember I asked something similar to Andrew Waterman already but I forgot where and when. I'll figure it out later. > >> That means something. If an extension adds CSR(s), we should imply 'Zicsr' >> from that extension (just like 'F'). So, we have to imply 'Zicsr' from >> following extensions: >> >> - 'H' >> - 'Zkr' >> - 'Zve32x' (I'll talk later) >> - 'Smstateen' >> - 'Sscofpmf' >> - 'Sstc' >> >> 'Zkr' is fixed in PATCH 2/3 and 'H' and 'S*' are fixed in PATCH 3/3. >> The only remaining extension is 'Zve32x' but I need to talk more to explain >> actual changes (specific to vectors) in PATCH 1/3. >> >> On the current version of GNU Binutils, CSRs with CSR_CLASS_V means they >> require the 'V' extension. However, there are a few vector subextensions >> that implement vector subsets (intended for embedded processors). > > Check zve32x for vcsr should be enough, since LLVM looks to did the > similar thing for vector instructions, > https://github.com/llvm/llvm-project/blob/7167a4207ee2c07cb192da1788f919332f83b456/llvm/lib/Support/RISCVISAInfo.cpp#L708 I agree and that's what a part of PATCH 1/3 is doing. It looks changing vector CSR requirement from 'V' to 'Zve32x' is acceptable to you. If so, I'll submit separate patch for this part. Thanks, Tsukasa > >> - 'Zve64d' (superset of 'Zve64f') >> - 'Zve64f' (superset of 'Zve32f' and 'Zve64x') >> - 'Zve64x' (superset of 'Zve32x') >> - 'Zve32f' (superset of 'Zve32x') >> - 'Zve32x' >> >> : Graph: Dependency graph of some vector/FP extensions >> : >> : +-------> D --------> F -----> Zicsr >> : | ^ ^ >> : | | | >> : V ---> Zve64d ---> Zve64f ---> Zve64x >> : | | >> : V V >> : Zve32f ---> Zve32x >> : | >> : | >> : +---> (Zicsr [added in PATCH 1/3]) >> >> They also require general purpose vector CSRs (vstart, vl, vtype and vlenb). >> So, corresponding CSR_CLASS_V with the 'V' extension is inappropriate >> (they should require 'Zve32x' instead, the minimum vector subset). >> >> Remaining CSRs are: >> >> - vxsat >> - vxrm >> - vcsr >> >> They are related to fixed-point arithmetic and 18.2 "Zve*: Vector Extensions >> for Embedded Processors" says: >> >>> All Zve* extensions support all vector fixed-point arithmetic instructions >>> (Vector Fixed-Point Arithmetic Instructions), except that vsmul.vv and >>> vsmul.vx are not supported for EEW=64 in Zve64*. >> >> So, their minimum requirement shall be also 'Zve32x', not 'V'. >> >> As a consequence, we can conclude that changing requirements of CSR_CLASS_V >> from 'V' to 'Zve32x' is sufficient to avoid CSR accessibility warnings. >> >> Also, 'Zve32x' must imply 'Zicsr' (just like the rest) to avoid CSR >> instruction errors. This is only effective on 'Zve32x' and 'Zve64x' >> because, for instance, 'Zve32f' implies 'F' and 'F' implies 'Zicsr' >> (see the graph above). >> >> I didn't rename CSR_CLASS_V to CSR_CLASS_ZVE32X because the name gets >> difficult and there's already INSN_CLASS_V (effectively requires 'Zve32x' >> with some exceptions). >> >> >> >> >> Tsukasa OI (3): >> RISC-V: Fix vector CSR requirements and imply >> RISC-V: Imply 'Zicsr' from 'Zkr' >> RISC-V: Imply 'Zicsr' from some privileged extensions >> >> bfd/elfxx-riscv.c | 6 +++++ >> gas/config/tc-riscv.c | 2 +- >> gas/testsuite/gas/riscv/csr-version-1p10.l | 28 ++++++++++---------- >> gas/testsuite/gas/riscv/csr-version-1p11.l | 28 ++++++++++---------- >> gas/testsuite/gas/riscv/csr-version-1p12.l | 28 ++++++++++---------- >> gas/testsuite/gas/riscv/csr-version-1p9p1.l | 28 ++++++++++---------- >> gas/testsuite/gas/riscv/march-imply-h.d | 6 +++++ >> gas/testsuite/gas/riscv/vector-csrs-zve32f.d | 21 +++++++++++++++ >> gas/testsuite/gas/riscv/vector-csrs-zve32x.d | 21 +++++++++++++++ >> gas/testsuite/gas/riscv/vector-csrs-zve64d.d | 21 +++++++++++++++ >> gas/testsuite/gas/riscv/vector-csrs-zve64f.d | 21 +++++++++++++++ >> gas/testsuite/gas/riscv/vector-csrs-zve64x.d | 21 +++++++++++++++ >> gas/testsuite/gas/riscv/vector-csrs.s | 12 +++++++++ >> gas/testsuite/gas/riscv/zkr.d | 10 +++++++ >> gas/testsuite/gas/riscv/zkr.s | 2 ++ >> 15 files changed, 198 insertions(+), 57 deletions(-) >> create mode 100644 gas/testsuite/gas/riscv/march-imply-h.d >> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32f.d >> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32x.d >> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64d.d >> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64f.d >> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64x.d >> create mode 100644 gas/testsuite/gas/riscv/vector-csrs.s >> create mode 100644 gas/testsuite/gas/riscv/zkr.d >> create mode 100644 gas/testsuite/gas/riscv/zkr.s >> >> >> base-commit: f555b327d41ed72ffae28caae550f5f86312db43 >> -- >> 2.34.1 >> > ^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2022-09-09 11:10 UTC | newest] Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-09-07 5:53 [PATCH 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI 2022-09-07 5:53 ` [PATCH 1/3] RISC-V: Fix vector CSR requirements and imply Tsukasa OI 2022-09-07 5:53 ` [PATCH 2/3] RISC-V: Imply 'Zicsr' from 'Zkr' Tsukasa OI 2022-09-07 5:53 ` [PATCH 3/3] RISC-V: Imply 'Zicsr' from some privileged extensions Tsukasa OI 2022-09-07 6:21 ` [PATCH v2 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI 2022-09-07 6:21 ` [PATCH v2 1/3] RISC-V: Fix vector CSR requirements and imply Tsukasa OI 2022-09-07 9:34 ` Kito Cheng 2022-09-09 11:10 ` Tsukasa OI 2022-09-07 6:21 ` [PATCH v2 2/3] RISC-V: Imply 'Zicsr' from 'Zkr' Tsukasa OI 2022-09-07 6:21 ` [PATCH v2 3/3] RISC-V: Imply 'Zicsr' from some privileged extensions Tsukasa OI 2022-09-08 6:53 ` [PATCH 0/1] RISC-V: Fix CSR accessibility on vectors Tsukasa OI 2022-09-08 6:53 ` [PATCH 1/1] RISC-V: Fix vector CSR requirements Tsukasa OI 2022-09-08 7:12 ` Nelson Chu 2022-09-08 7:15 ` Tsukasa OI 2022-09-08 7:20 ` Tsukasa OI 2022-09-07 8:49 ` [PATCH 0/3] RISC-V: Fix CSR accessibility and implications Nelson Chu 2022-09-07 9:08 ` Tsukasa OI
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