[Bug target/114810] New: [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[Bug target/114810] New: [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[kocelfc at tutanota dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

            Bug ID: 114810
           Summary: [14 Regression] internal compiler error: in
                    lra_split_hard_reg_for, at lra-assigns.cc:1868
                    (unable to find a register to spill)
                    {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2
                    -mbmi -fno-exceptions -fno-plt
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: kocelfc at tutanota dot com
  Target Milestone: ---

Created attachment 58010
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58010&action=edit
preprocessed sources

g++ -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt
aco_instruction_selection.cpp.ii

../mesa-9999/src/amd/compiler/aco_instruction_selection.cpp: In function ‘void
aco::{anonymous}::visit_load_push_constant(aco::isel_context*,
nir_intrinsic_instr*)’:
../mesa-9999/src/amd/compiler/aco_instruction_selection.cpp:5965:1: error:
unable to find a register to spill
../mesa-9999/src/amd/compiler/aco_instruction_selection.cpp:5965:1: error: this
is the insn:
(insn 1702 2054 2077 12 (parallel [
            (set (reg:DI 1118 [830])
                (and:DI (not:DI (reg:DI 876 [829]))
                    (reg:DI 1096 [orig:398 mask_81 ] [398])))
            (clobber (reg:CC 17 flags))
        ]) "../mesa-9999/src/amd/compiler/aco_instruction_selection.cpp":5894:7
703 {*andndi3_doubleword_bmi}
     (expr_list:REG_DEAD (reg:DI 1096 [orig:398 mask_81 ] [398])
        (expr_list:REG_DEAD (reg:DI 876 [829])
            (expr_list:REG_UNUSED (reg:CC 17 flags)
                (nil)))))
during RTL pass: reload
../mesa-9999/src/amd/compiler/aco_instruction_selection.cpp:5965:1: internal
compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868
0x55a783a03d4f _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
       
/usr/src/debug/sys-devel/gcc-14.0.1_pre20240421/gcc-14-20240421/gcc/rtl-error.cc:108
0x55a784895f66 lra_split_hard_reg_for()
       
/usr/src/debug/sys-devel/gcc-14.0.1_pre20240421/gcc-14-20240421/gcc/lra-assigns.cc:1868
0x55a78488ecb7 lra(_IO_FILE*, int)
       
/usr/src/debug/sys-devel/gcc-14.0.1_pre20240421/gcc-14-20240421/gcc/lra.cc:2518
0x55a784838a79 do_reload
       
/usr/src/debug/sys-devel/gcc-14.0.1_pre20240421/gcc-14-20240421/gcc/ira.cc:5973
0x55a784838a79 execute
       
/usr/src/debug/sys-devel/gcc-14.0.1_pre20240421/gcc-14-20240421/gcc/ira.cc:6161

Configured with:
/var/tmp/portage/sys-devel/gcc-14.0.1_pre20240421/work/gcc-14-20240421/configure
--host=x86_64-pc-linux-gnu --build=x86_64-pc-linux-gnu --prefix=/usr
--bindir=/usr/x86_64-pc-linux-gnu/gcc-bin/14
--includedir=/usr/lib/gcc/x86_64-pc-linux-gnu/14/include
--datadir=/usr/share/gcc-data/x86_64-pc-linux-gnu/14
--mandir=/usr/share/gcc-data/x86_64-pc-linux-gnu/14/man
--infodir=/usr/share/gcc-data/x86_64-pc-linux-gnu/14/info
--with-gxx-include-dir=/usr/lib/gcc/x86_64-pc-linux-gnu/14/include/g++-v14
--disable-silent-rules --disable-dependency-tracking
--with-python-dir=/share/gcc-data/x86_64-pc-linux-gnu/14/python
--enable-languages=c,c++ --enable-obsolete --enable-secureplt --disable-werror
--with-system-zlib --enable-nls --without-included-gettext
--disable-libunwind-exceptions --enable-checking=yes,extra,rtl
--with-bugurl=https://bugs.gentoo.org/ --with-pkgversion='Gentoo
14.0.1_pre20240421 p26' --with-gcc-major-version-only --enable-libstdcxx-time
--enable-lto --disable-libstdcxx-pch --enable-shared --enable-threads=posix
--enable-__cxa_atexit --enable-clocale=gnu --enable-multilib
--with-multilib-list=m32,m64 --disable-fixed-point --enable-targets=all
--disable-libgomp --disable-libssp --disable-libada --disable-cet
--disable-systemtap --disable-valgrind-annotations --disable-vtable-verify
--disable-libvtv --with-zstd --without-isl --enable-default-pie
--enable-host-pie --enable-host-bind-now --enable-default-ssp
--disable-fixincludes
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 14.0.1 20240421 (experimental) (Gentoo 14.0.1_pre20240421 p26)

[Bug target/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[kocelfc at tutanota dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

--- Comment #1 from Kostadin Shishmanov <kocelfc at tutanota dot com> ---
Created attachment 58011
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58011&action=edit
reduced testcase

[Bug target/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |14.0
           Priority|P3                          |P1
                 CC|                            |jakub at gcc dot gnu.org,
                   |                            |uros at gcc dot gnu.org,
                   |                            |vmakarov at gcc dot gnu.org

--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Started with r14-5109-ga291237b628f419d7f7ac264dd7b42947b565222 which means it
was latent before.
I need -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt -fpie
-march=x86-64 -w
to reproduce.

[Bug target/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2024-04-22
     Ever confirmed|0                           |1

--- Comment #3 from Uroš Bizjak <ubizjak at gmail dot com> ---
It is alternative 0 (=&r,r,ro) that causes the spill failure. Following
definition works OK:

(define_insn_and_split "*andn<dwi>3_doubleword_bmi"
  [(set (match_operand:<DWI> 0 "register_operand" "=r,r")
        (and:<DWI>
          (not:<DWI> (match_operand:<DWI> 1 "register_operand" "0,r"))
          (match_operand:<DWI> 2 "nonimmediate_operand" "ro,0")))
   (clobber (reg:CC FLAGS_REG))]

and compiles to:

(insn 1150 1108 987 7 (set (reg:DI 2 cx [453])
        (reg:DI 3 bx [452])) "pr114810.C":296:6 84 {*movdi_internal}
     (nil))
(insn 987 1150 1151 7 (parallel [
            (set (reg:DI 2 cx [453])
                (and:DI (not:DI (reg:DI 2 cx [453]))
                    (reg:DI 0 ax [orig:217 _13 ] [217])))
            (clobber (reg:CC 17 flags))
        ]) "pr114810.C":296:6 703 {*andndi3_doubleword_bmi}
     (nil))

[Bug target/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

--- Comment #4 from Uroš Bizjak <ubizjak at gmail dot com> ---
An interesting observation, when the insn is defined only with problematic
alternative:

(define_insn_and_split "*andn<dwi>3_doubleword_bmi"
  [(set (match_operand:<DWI> 0 "register_operand" "=&r")
        (and:<DWI>
          (not:<DWI> (match_operand:<DWI> 1 "register_operand" "r"))
          (match_operand:<DWI> 2 "nonimmediate_operand" "ro")))
   (clobber (reg:CC FLAGS_REG))]

the compilation succeeds, and a spill to memory is emitted:


(insn 1170 65 1177 7 (set (mem/c:DI (plus:SI (reg/f:SI 6 bp)
                (const_int -168 [0xffffffffffffff58])) [71 %sfp+-144 S8 A64])
        (reg:DI 0 ax [orig:217 _13 ] [217])) "pr114810.C":296:36 84
{*movdi_internal}
     (nil))

...

(insn 987 1154 1111 7 (parallel [
            (set (reg:DI 3 bx [453])
                (and:DI (not:DI (reg:DI 0 ax [452]))
                    (mem/c:DI (plus:SI (reg/f:SI 6 bp)
                            (const_int -168 [0xffffffffffffff58])) [71
%sfp+-144 S8 A64])))
            (clobber (reg:CC 17 flags))
        ]) "pr114810.C":296:6 703 {*andndi3_doubleword_bmi}
     (nil))

[Bug rtl-optimization/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |ra
          Component|target                      |rtl-optimization

--- Comment #5 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Uroš Bizjak from comment #4)

> the compilation succeeds, and a spill to memory is emitted:

I think RA should emit a similar spill with the original instruction when
alternative (=&r,r,ro) is used. There is nothing wrong with the original insn
definition.

Re-confirmed as RA problem.

[Bug rtl-optimization/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[vmakarov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

--- Comment #6 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
(In reply to Uroš Bizjak from comment #4)
> An interesting observation, when the insn is defined only with problematic
> alternative:
> 
> (define_insn_and_split "*andn<dwi>3_doubleword_bmi"
>   [(set (match_operand:<DWI> 0 "register_operand" "=&r")
> 	(and:<DWI>
> 	  (not:<DWI> (match_operand:<DWI> 1 "register_operand" "r"))
> 	  (match_operand:<DWI> 2 "nonimmediate_operand" "ro")))
>    (clobber (reg:CC FLAGS_REG))]
> 
> the compilation succeeds, and a spill to memory is emitted:
> 
> 
> (insn 1170 65 1177 7 (set (mem/c:DI (plus:SI (reg/f:SI 6 bp)
>                 (const_int -168 [0xffffffffffffff58])) [71 %sfp+-144 S8 A64])
>         (reg:DI 0 ax [orig:217 _13 ] [217])) "pr114810.C":296:36 84
> {*movdi_internal}
>      (nil))
> 
> ...
> 
> (insn 987 1154 1111 7 (parallel [
>             (set (reg:DI 3 bx [453])
>                 (and:DI (not:DI (reg:DI 0 ax [452]))
>                     (mem/c:DI (plus:SI (reg/f:SI 6 bp)
>                             (const_int -168 [0xffffffffffffff58])) [71
> %sfp+-144 S8 A64])))
>             (clobber (reg:CC 17 flags))
>         ]) "pr114810.C":296:6 703 {*andndi3_doubleword_bmi}
>      (nil))

The problem is that the alternative assumes 3 DI values live simultaneously. 
This means 6 regs and we have only 6 available ones. One input reg is assigned
to 0 another one is to 3.  So we have [01]2[34]5, where regs in brackets are
taken by the operands.  Although there are still 2 regs but they can not be
used as they are not adjacent.

The one solution is to somehow penalize the chosen alternative by changing
alternative heuristics in lra-constraints.cc.  But it definitely can affect
other targets in some unpredicted way.  So the solution is too risky especially
at this stage.  Also it might be possible that there is no alternative with
less 3 living pseudos for some different insn case.

I don't see non-risky solution right now.  I'll be thinking how to better fix
this.

[Bug rtl-optimization/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

--- Comment #7 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Vladimir Makarov from comment #6)
> The problem is that the alternative assumes 3 DI values live simultaneously.
> This means 6 regs and we have only 6 available ones. One input reg is
> assigned to 0 another one is to 3.  So we have [01]2[34]5, where regs in
> brackets are taken by the operands.  Although there are still 2 regs but
> they can not be used as they are not adjacent.
> 
> The one solution is to somehow penalize the chosen alternative by changing
> alternative heuristics in lra-constraints.cc.  But it definitely can affect
> other targets in some unpredicted way.  So the solution is too risky
> especially at this stage.  Also it might be possible that there is no
> alternative with less 3 living pseudos for some different insn case.
> 
> I don't see non-risky solution right now.  I'll be thinking how to better
> fix this.

Please note that the insn is defined as:

(define_insn_and_split "*andn<dwi>3_doubleword_bmi"
  [(set (match_operand:<DWI> 0 "register_operand" "=&r,r,r")
        (and:<DWI>
          (not:<DWI> (match_operand:<DWI> 1 "register_operand" "r,0,r"))
          (match_operand:<DWI> 2 "nonimmediate_operand" "ro,ro,0")))
   (clobber (reg:CC FLAGS_REG))]

where the problematic alternative (=&r,r,ro) allows a memory input in its
operand 2 constraint. The allocator could spill a DImode value to a stack in
advance and reload the value from the memory in this particular alternative.

[Bug rtl-optimization/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

--- Comment #8 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
(In reply to Uroš Bizjak from comment #7)
> (define_insn_and_split "*andn<dwi>3_doubleword_bmi"
>   [(set (match_operand:<DWI> 0 "register_operand" "=&r,r,r")
> 	(and:<DWI>
> 	  (not:<DWI> (match_operand:<DWI> 1 "register_operand" "r,0,r"))
> 	  (match_operand:<DWI> 2 "nonimmediate_operand" "ro,ro,0")))
>    (clobber (reg:CC FLAGS_REG))]
> 
> where the problematic alternative (=&r,r,ro) allows a memory input in its
> operand 2 constraint. The allocator could spill a DImode value to a stack in
> advance and reload the value from the memory in this particular alternative.

So, given the known ia32 register starvation, can't we split that first
alternative to
=&r,r,o with "nox64" isa and =&r,r,ro with "x64" isa?

[Bug rtl-optimization/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[vmakarov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

--- Comment #9 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
(In reply to Uroš Bizjak from comment #7)
>
> 
> Please note that the insn is defined as:
> 
> (define_insn_and_split "*andn<dwi>3_doubleword_bmi"
>   [(set (match_operand:<DWI> 0 "register_operand" "=&r,r,r")
> 	(and:<DWI>
> 	  (not:<DWI> (match_operand:<DWI> 1 "register_operand" "r,0,r"))
> 	  (match_operand:<DWI> 2 "nonimmediate_operand" "ro,ro,0")))
>    (clobber (reg:CC FLAGS_REG))]
> 
> where the problematic alternative (=&r,r,ro) allows a memory input in its
> operand 2 constraint. The allocator could spill a DImode value to a stack in
> advance and reload the value from the memory in this particular alternative.

That is not how LRA (and the old reload) works.  If an operand matches the
constraint (r in ro), it does not change its location (do reloads).

In general, it is possible to implement reloads for operands already matched to
a constraint but this would significantly complicate already too complicated
code.  And probably heuristics based on reload costs would reject such reloads
anyway.

I probably could implement reg starvation recognition in process_alt_operand
and penalize the alternative and most probably it will not affect other
targets.  Still it is not easy because of different possible class subsets or
intersections.

Still I think Jakub's solution is reasonable at this stage.  If I implement my
proposed solution we could commit it after the release.

[Bug rtl-optimization/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

--- Comment #10 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
(In reply to Jakub Jelinek from comment #8)
> So, given the known ia32 register starvation, can't we split that first
> alternative to
> =&r,r,o with "nox64" isa and =&r,r,ro with "x64" isa?

Better make it a
(define_mode_attr andn_ro [(DI "o") (TI "ro")])
and use <andn_ro> instead of the first ro (or some better name).

[Bug rtl-optimization/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

--- Comment #11 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Jakub Jelinek from comment #8)
> (In reply to Uroš Bizjak from comment #7)
> > (define_insn_and_split "*andn<dwi>3_doubleword_bmi"
> >   [(set (match_operand:<DWI> 0 "register_operand" "=&r,r,r")
> > 	(and:<DWI>
> > 	  (not:<DWI> (match_operand:<DWI> 1 "register_operand" "r,0,r"))
> > 	  (match_operand:<DWI> 2 "nonimmediate_operand" "ro,ro,0")))
> >    (clobber (reg:CC FLAGS_REG))]
> > 
> > where the problematic alternative (=&r,r,ro) allows a memory input in its
> > operand 2 constraint. The allocator could spill a DImode value to a stack in
> > advance and reload the value from the memory in this particular alternative.
> 
> So, given the known ia32 register starvation, can't we split that first
> alternative to
> =&r,r,o with "nox64" isa and =&r,r,ro with "x64" isa?

Yes, IMO this is an acceptable workaround, but please split the constraint to
(=&r,r,r) and (=&r,r,o), with the former limited to "x64" isa. This is what the
other patterns do, new mode attribute just hides the obvious fact.

[Bug rtl-optimization/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

--- Comment #12 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Vladimir Makarov from comment #9)
> (In reply to Uroš Bizjak from comment #7)
> >
> > 
> > Please note that the insn is defined as:
> > 
> > (define_insn_and_split "*andn<dwi>3_doubleword_bmi"
> >   [(set (match_operand:<DWI> 0 "register_operand" "=&r,r,r")
> > 	(and:<DWI>
> > 	  (not:<DWI> (match_operand:<DWI> 1 "register_operand" "r,0,r"))
> > 	  (match_operand:<DWI> 2 "nonimmediate_operand" "ro,ro,0")))
> >    (clobber (reg:CC FLAGS_REG))]
> > 
> > where the problematic alternative (=&r,r,ro) allows a memory input in its
> > operand 2 constraint. The allocator could spill a DImode value to a stack in
> > advance and reload the value from the memory in this particular alternative.
> 
> That is not how LRA (and the old reload) works.  If an operand matches the
> constraint (r in ro), it does not change its location (do reloads).
> 
> In general, it is possible to implement reloads for operands already matched
> to a constraint but this would significantly complicate already too
> complicated code.  And probably heuristics based on reload costs would
> reject such reloads anyway.
> 
> I probably could implement reg starvation recognition in process_alt_operand
> and penalize the alternative and most probably it will not affect other
> targets.  Still it is not easy because of different possible class subsets
> or intersections.
> 
> Still I think Jakub's solution is reasonable at this stage.  If I implement
> my proposed solution we could commit it after the release.

Yes, I agree. Not knowing the internals of the RA, it looked "obvious" that RA
could use memory operand here, and using this solution in the
target-independent code could solve the issue also for other register starved
targets.

Another long-term improvement in the RA could be allocating multi-regs in a
random order. As far as x86 is concerned, apart from passing function
parameters in registers and perhaps some asm constraint ("A"), there is no need
for double-word registers to be allocated in any specific order. The
double-word value could be allocated in {hi,lo} register tuplet, where hi and
lo can be any register. Using this approach, the RA could allocate a
double-word value also in [01]2[34]5 situation.

[Bug rtl-optimization/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |ASSIGNED
           Assignee|unassigned at gcc dot gnu.org      |jakub at gcc dot gnu.org

--- Comment #13 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Created attachment 58013
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58013&action=edit
gcc14-pr114810.patch

So like this?  Tried hard to reduce the testcase, but it didn't progress at
all, so at least tried manually using cvise's clex to rename tokens a little
bit.

[Bug rtl-optimization/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

--- Comment #14 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Jakub Jelinek from comment #13)
> Created attachment 58013 [details]
> gcc14-pr114810.patch
> 
> So like this?  Tried hard to reduce the testcase, but it didn't progress at
> all, so at least tried manually using cvise's clex to rename tokens a little
> bit.

LGTM.

[Bug rtl-optimization/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

--- Comment #15 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:628c2221d38715a64f828e3635317293d150e001

commit r14-10099-g628c2221d38715a64f828e3635317293d150e001
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Apr 23 23:30:27 2024 +0200

    i386: Avoid =&r,r,r andn double-word alternative for ia32 [PR114810]

    As discussed in the PR, on ia32 with its 8 GPRs, where 1 is always fixed
    and other 2 often are as well having an alternative which needs 3
    double-word registers is just too much for RA.
    The following patch splits that alternative into two, one with o is used
    even on ia32, but one with the 3x r is used just for -m64/-mx32.
    Tried to reduce the testcase further, but it wasn't easily possible.

    2024-04-23  Jakub Jelinek  <jakub@redhat.com>

            PR target/114810
            * config/i386/i386.md (*andn<dwi>3_doubleword_bmi): Split the
=&r,r,ro
            alternative into =&r,r,r enabled only for x64 and =&r,r,o.

            * g++.target/i386/pr114810.C: New test.

[Bug rtl-optimization/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #16 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Fixed.

[Bug rtl-optimization/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

--- Comment #17 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Vladimir Makarov <vmakarov@gcc.gnu.org>:

https://gcc.gnu.org/g:2f00e6caca1a14dfe26e94f608e9d79a787ebe08

commit r15-330-g2f00e6caca1a14dfe26e94f608e9d79a787ebe08
Author: Vladimir N. Makarov <vmakarov@redhat.com>
Date:   Wed May 8 10:39:04 2024 -0400

    [PR114810][LRA]: Recognize alternatives with lack of available registers
for insn and demote them.

      PR114810 was fixed in machine-dependent way.  This patch is a fix of
    the PR on LRA side.  LRA chose alternative with constraints `&r,r,ro`
    on i686 when all operands of DImode and there are only 6 available
    general regs.  The patch recognizes such case and significantly
    increase the alternative cost.  It does not reject alternative
    completely.  So the fix is safe but it might not work for all
    potentially possible cases of registers lack as register classes can
    have any relations including subsets and intersections.

    gcc/ChangeLog:

            PR target/114810
            * lra-constraints.cc (process_alt_operands): Calculate union reg
            class for the alternative, peak matched regs and required reload
            regs.  Recognize alternatives with lack of available registers and
            make them costly.  Add debug print about this case.