From: Jeff Law <jlaw@ventanamicro.com>
To: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>,
"kito.cheng" <kito.cheng@gmail.com>
Cc: jeffreyalaw <jeffreyalaw@gmail.com>, palmer <palmer@dabbelt.com>,
vineetg <vineetg@rivosinc.com>,
"Kito.cheng" <kito.cheng@sifive.com>,
gcc-patches <gcc-patches@gcc.gnu.org>,
Patrick O'Neill <patrick@rivosinc.com>,
macro <macro@embecosm.com>
Subject: Re: RISC-V Bootstrap problems
Date: Thu, 25 May 2023 07:55:15 -0600 [thread overview]
Message-ID: <07ba448b-d3f5-37be-8715-0c38554112a4@ventanamicro.com> (raw)
In-Reply-To: <8E35CC71575965B0+20230525121910161040251@rivai.ai>
On 5/24/23 22:19, juzhe.zhong@rivai.ai wrote:
> >> It's highly unlikely we'll switch from the mechanisms we're using.
>>>They're pretty deeply embedded into how all the ports are developed and
>>>work.
>
> We just take a look at the build file. It seems that the functions
> generated by define_insn
> are so many. Do we have the chance optimize it?
> I believe the tablegen mechanism in LLVM is well optimized in case of
> generated files and functions
> so that they won't be affected to much as instructions go up.
Any define_insn or define_expand with a name that does not begin with a
'*' will result in a function in insn-emit.
Those functions allow us to generate those patterns either from generic
parts of the compiler or from within the target. So if I have
(define_insn "fubar" ...)
I can say
rtx x = gen_fubar (...);
To constuct RTL matching the pattern for "fubar".
So if there are patterns with names that are not used in this way, you
can prefix their name with '*' to suppress creation of the generator
function. I have not looked to see if this would help our situation.
jeff
next prev parent reply other threads:[~2023-05-25 13:55 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-22 6:41 [PATCH] RISC-V: Add missing torture-init and torture-finish for rvv.exp Kito Cheng
2023-05-22 9:17 ` Kito Cheng
2023-05-23 3:52 ` Vineet Gupta
2023-05-24 18:18 ` Vineet Gupta
2023-05-24 20:34 ` Thomas Schwinge
2023-05-24 22:13 ` Vineet Gupta
2023-05-24 23:12 ` Vineet Gupta
2023-05-24 23:13 ` Palmer Dabbelt
2023-05-25 3:43 ` RISC-V Bootstrap problems Jeff Law
2023-05-25 3:46 ` juzhe.zhong
2023-05-25 3:53 ` Kito Cheng
2023-05-25 3:54 ` juzhe.zhong
2023-05-25 4:07 ` Jeff Law
2023-05-25 4:19 ` juzhe.zhong
2023-05-25 13:55 ` Jeff Law [this message]
2023-05-25 4:06 ` Jeff Law
2023-05-25 4:08 ` Kito Cheng
2023-05-25 3:51 ` juzhe.zhong
2023-05-24 23:15 ` [PATCH] RISC-V: Add missing torture-init and torture-finish for rvv.exp Jeff Law
2023-05-25 20:26 ` Thomas Schwinge
2023-05-26 23:38 ` Vineet Gupta
2023-05-30 18:43 ` Vineet Gupta
2023-05-31 16:28 ` Vineet Gupta
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