* [v4 PATCH 0/4] RISC-V: Support z*inx extensions.
@ 2022-10-20 9:32 jiawei
2022-10-20 9:32 ` [v4 PATCH 1/4] RISC-V: Minimal support of z*inx extension jiawei
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: jiawei @ 2022-10-20 9:32 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, christoph.muellner, wuwei2016, jiawei
Zfinx extension[1] had already ratified. Here is the
implementation patch set that reuse floating point pattern and ban
the use of fpr when use z*inx as a target.
Current works can be find in follow links, binutils and simulator
works already supported on upstream.
https://github.com/pz9115/riscv-gcc/tree/zfinx-rebase
Thanks for Tariq Kurd, Kito Cheng, Jim Willson,
Jeremy Bennett helped us a lot with this work.
[1] https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0-rc.pdf
Version log:
v2: As Kito Cheng's comment, add Changelog part in patches, update imply
info in riscv-common.c, remove useless check and update annotation in
riscv.c.
v3: Update with new isa-spec version 20191213, make zfinx imply zicsr as
default, fix the lack of fcsr use in zfinx.
v4: Rebase patch with upstream, add zhinx/zhinxmin extensions support.
Add additional zhinx/zhinxmin same like zfh/zfhmin.
Jiawei (4):
RISC-V: Minimal support of z*inx extension.
RISC-V: Target support for z*inx extension.
RISC-V: Limit regs use for z*inx extension.
RISC-V: Add zhinx/zhinxmin testcases.
gcc/common/config/riscv/riscv-common.cc | 18 +++++
gcc/config/riscv/arch-canonicalize | 5 ++
gcc/config/riscv/constraints.md | 5 +-
gcc/config/riscv/iterators.md | 6 +-
gcc/config/riscv/riscv-builtins.cc | 4 +-
gcc/config/riscv/riscv-c.cc | 2 +-
gcc/config/riscv/riscv-opts.h | 10 +++
gcc/config/riscv/riscv.cc | 21 ++++-
gcc/config/riscv/riscv.md | 78 ++++++++++---------
gcc/config/riscv/riscv.opt | 3 +
.../gcc.target/riscv/_Float16-zhinx-1.c | 10 +++
.../gcc.target/riscv/_Float16-zhinx-2.c | 9 +++
.../gcc.target/riscv/_Float16-zhinx-3.c | 9 +++
.../gcc.target/riscv/_Float16-zhinxmin-1.c | 10 +++
.../gcc.target/riscv/_Float16-zhinxmin-2.c | 10 +++
.../gcc.target/riscv/_Float16-zhinxmin-3.c | 10 +++
16 files changed, 160 insertions(+), 50 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [v4 PATCH 1/4] RISC-V: Minimal support of z*inx extension.
2022-10-20 9:32 [v4 PATCH 0/4] RISC-V: Support z*inx extensions jiawei
@ 2022-10-20 9:32 ` jiawei
2022-10-20 9:32 ` [v4 PATCH 2/4] RISC-V: Target support for " jiawei
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: jiawei @ 2022-10-20 9:32 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, christoph.muellner, wuwei2016, Jiawei
From: Jiawei <jiawei@iscas.ac.cn>
Minimal support of z*inx extension, include 'zfinx'， 'zdinx' and 'zhinx/zhinxmin'
corresponding to 'f', 'd' and 'zfh/zfhmin', the 'zdinx' will imply 'zfinx'
same as 'd' imply 'f', 'zhinx' will aslo imply 'zfinx', all zfinx extension imply 'zicsr'.
Co-Authored-By: Sinan Lin.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extensions.
* config/riscv/arch-canonicalize: New imply relations.
* config/riscv/riscv-opts.h (MASK_ZFINX): New mask.
(MASK_ZDINX): Ditto.
(MASK_ZHINX): Ditto.
(MASK_ZHINXMIN): Ditto.
(TARGET_ZFINX): New target.
(TARGET_ZDINX): Ditto.
(TARGET_ZHINX): Ditto.
(TARGET_ZHINXMIN): Ditto.
* config/riscv/riscv.opt: New target variable.
---
gcc/common/config/riscv/riscv-common.cc | 18 ++++++++++++++++++
gcc/config/riscv/arch-canonicalize | 5 +++++
gcc/config/riscv/riscv-opts.h | 10 ++++++++++
gcc/config/riscv/riscv.opt | 3 +++
4 files changed, 36 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index c39ed2e2696..55f3328df7a 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -51,6 +51,11 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"d", "f"},
{"f", "zicsr"},
{"d", "zicsr"},
+
+ {"zdinx", "zfinx"},
+ {"zfinx", "zicsr"},
+ {"zdinx", "zicsr"},
+
{"zk", "zkn"},
{"zk", "zkr"},
{"zk", "zkt"},
@@ -99,6 +104,9 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zfh", "zfhmin"},
{"zfhmin", "f"},
+
+ {"zhinx", "zhinxmin"},
+ {"zhinxmin", "zfinx"},
{NULL, NULL}
};
@@ -158,6 +166,11 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zhinx", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zhinxmin", ISA_SPEC_CLASS_NONE, 1, 0},
+
{"zbkb", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbkc", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbkx", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1168,6 +1181,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC},
{"zbs", &gcc_options::x_riscv_zb_subext, MASK_ZBS},
+ {"zfinx", &gcc_options::x_riscv_zinx_subext, MASK_ZFINX},
+ {"zdinx", &gcc_options::x_riscv_zinx_subext, MASK_ZDINX},
+ {"zhinx", &gcc_options::x_riscv_zinx_subext, MASK_ZHINX},
+ {"zhinxmin", &gcc_options::x_riscv_zinx_subext, MASK_ZHINXMIN},
+
{"zbkb", &gcc_options::x_riscv_zk_subext, MASK_ZBKB},
{"zbkc", &gcc_options::x_riscv_zk_subext, MASK_ZBKC},
{"zbkx", &gcc_options::x_riscv_zk_subext, MASK_ZBKX},
diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize
index fd7651ac491..2498db506b7 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -41,6 +41,11 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
IMPLIED_EXT = {
"d" : ["f", "zicsr"],
"f" : ["zicsr"],
+ "zdinx" : ["zfinx", "zicsr"],
+ "zfinx" : ["zicsr"],
+ "zhinx" : ["zhinxmin", "zfinx", "zicsr"],
+ "zhinxmin" : ["zfinx", "zicsr"],
+
"zk" : ["zkn", "zkr", "zkt"],
"zkn" : ["zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"],
"zks" : ["zbkb", "zbkc", "zbkx", "zksed", "zksh"],
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 55e0bc0a0e9..bb2322ad182 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -83,6 +83,16 @@ enum stack_protector_guard {
#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
+#define MASK_ZFINX (1 << 0)
+#define MASK_ZDINX (1 << 1)
+#define MASK_ZHINX (1 << 2)
+#define MASK_ZHINXMIN (1 << 3)
+
+#define TARGET_ZFINX ((riscv_zinx_subext & MASK_ZFINX) != 0)
+#define TARGET_ZDINX ((riscv_zinx_subext & MASK_ZDINX) != 0)
+#define TARGET_ZHINX ((riscv_zinx_subext & MASK_ZHINX) != 0)
+#define TARGET_ZHINXMIN ((riscv_zinx_subext & MASK_ZHINXMIN) != 0)
+
#define MASK_ZBKB (1 << 0)
#define MASK_ZBKC (1 << 1)
#define MASK_ZBKX (1 << 2)
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 8923a11a97d..7c1e0ed5f2d 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -206,6 +206,9 @@ int riscv_zi_subext
TargetVariable
int riscv_zb_subext
+TargetVariable
+int riscv_zinx_subext
+
TargetVariable
int riscv_zk_subext
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [v4 PATCH 2/4] RISC-V: Target support for z*inx extension.
2022-10-20 9:32 [v4 PATCH 0/4] RISC-V: Support z*inx extensions jiawei
2022-10-20 9:32 ` [v4 PATCH 1/4] RISC-V: Minimal support of z*inx extension jiawei
@ 2022-10-20 9:32 ` jiawei
2022-10-20 9:32 ` [v4 PATCH 3/4] RISC-V: Limit regs use " jiawei
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: jiawei @ 2022-10-20 9:32 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, christoph.muellner, wuwei2016, Jiawei
From: Jiawei <jiawei@iscas.ac.cn>
Support 'TARGET_ZFINX' with float instruction pattern and builtin function.
Reuse 'TARGET_HADR_FLOAT', 'TARGET_DOUBLE_FLOAT' and 'TARGET_ZHINX' patterns.
gcc/ChangeLog:
* config/riscv/iterators.md (TARGET_ZFINX):New target.
(TARGET_ZDINX): Ditto.
(TARGET_ZHINX): Ditto.
* config/riscv/riscv-builtins.cc (AVAIL): Ditto.
(riscv_atomic_assign_expand_fenv): Ditto.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Ditto.
* config/riscv/riscv.md: Ditto.
---
gcc/config/riscv/iterators.md | 6 +--
gcc/config/riscv/riscv-builtins.cc | 4 +-
gcc/config/riscv/riscv-c.cc | 2 +-
gcc/config/riscv/riscv.md | 78 +++++++++++++++---------------
4 files changed, 46 insertions(+), 44 deletions(-)
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 39dffabc235..50380ecfac9 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -59,9 +59,9 @@
(define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")])
;; Iterator for hardware-supported floating-point modes.
-(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
- (DF "TARGET_DOUBLE_FLOAT")
- (HF "TARGET_ZFH")])
+(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX")
+ (DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")
+ (HF "TARGET_ZFH || TARGET_ZHINX")])
;; Iterator for floating-point modes that can be loaded into X registers.
(define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")])
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index 14865d70955..1534cfd860b 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -87,7 +87,7 @@ struct riscv_builtin_description {
unsigned int (*avail) (void);
};
-AVAIL (hard_float, TARGET_HARD_FLOAT)
+AVAIL (hard_float, TARGET_HARD_FLOAT || TARGET_ZFINX)
AVAIL (clean32, TARGET_ZICBOM && !TARGET_64BIT)
@@ -322,7 +322,7 @@ riscv_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
void
riscv_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
{
- if (!TARGET_HARD_FLOAT)
+ if (!(TARGET_HARD_FLOAT || TARGET_ZFINX))
return;
tree frflags = GET_BUILTIN_DECL (CODE_FOR_riscv_frflags);
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 78f6eacb068..826ae0067bb 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -61,7 +61,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
if (TARGET_HARD_FLOAT)
builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
- if (TARGET_HARD_FLOAT && TARGET_FDIV)
+ if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV)
{
builtin_define ("__riscv_fdiv");
builtin_define ("__riscv_fsqrt");
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 2d1cda2b98f..09ca91fb2c3 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -434,7 +434,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(plus:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fadd.<fmt>\t%0,%1,%2"
[(set_attr "type" "fadd")
(set_attr "mode" "<UNITMODE>")])
@@ -565,7 +565,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fsub.<fmt>\t%0,%1,%2"
[(set_attr "type" "fadd")
(set_attr "mode" "<UNITMODE>")])
@@ -735,7 +735,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(mult:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fmul.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "<UNITMODE>")])
@@ -1042,7 +1042,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(div:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT && TARGET_FDIV"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV"
"fdiv.<fmt>\t%0,%1,%2"
[(set_attr "type" "fdiv")
(set_attr "mode" "<UNITMODE>")])
@@ -1057,7 +1057,7 @@
(define_insn "sqrt<mode>2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(sqrt:ANYF (match_operand:ANYF 1 "register_operand" " f")))]
- "TARGET_HARD_FLOAT && TARGET_FDIV"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV"
{
return "fsqrt.<fmt>\t%0,%1";
}
@@ -1072,7 +1072,7 @@
(fma:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")
(match_operand:ANYF 3 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fmadd.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1083,7 +1083,7 @@
(fma:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")
(neg:ANYF (match_operand:ANYF 3 "register_operand" " f"))))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1095,7 +1095,7 @@
(neg:ANYF (match_operand:ANYF 1 "register_operand" " f"))
(match_operand:ANYF 2 "register_operand" " f")
(neg:ANYF (match_operand:ANYF 3 "register_operand" " f"))))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fnmadd.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1107,7 +1107,7 @@
(neg:ANYF (match_operand:ANYF 1 "register_operand" " f"))
(match_operand:ANYF 2 "register_operand" " f")
(match_operand:ANYF 3 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fnmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1120,7 +1120,7 @@
(neg:ANYF (match_operand:ANYF 1 "register_operand" " f"))
(match_operand:ANYF 2 "register_operand" " f")
(neg:ANYF (match_operand:ANYF 3 "register_operand" " f")))))]
- "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)"
"fmadd.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1133,7 +1133,7 @@
(neg:ANYF (match_operand:ANYF 1 "register_operand" " f"))
(match_operand:ANYF 2 "register_operand" " f")
(match_operand:ANYF 3 "register_operand" " f"))))]
- "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)"
"fmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1146,7 +1146,7 @@
(match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")
(match_operand:ANYF 3 "register_operand" " f"))))]
- "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)"
"fnmadd.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1159,7 +1159,7 @@
(match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")
(neg:ANYF (match_operand:ANYF 3 "register_operand" " f")))))]
- "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)"
"fnmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
@@ -1174,7 +1174,7 @@
(define_insn "abs<mode>2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(abs:ANYF (match_operand:ANYF 1 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fabs.<fmt>\t%0,%1"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1184,7 +1184,7 @@
(unspec:ANYF [(match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")]
UNSPEC_COPYSIGN))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fsgnj.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1192,7 +1192,7 @@
(define_insn "neg<mode>2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(neg:ANYF (match_operand:ANYF 1 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fneg.<fmt>\t%0,%1"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1209,7 +1209,7 @@
(unspec:ANYF [(use (match_operand:ANYF 1 "register_operand" " f"))
(use (match_operand:ANYF 2 "register_operand" " f"))]
UNSPEC_FMIN))]
- "TARGET_HARD_FLOAT && !HONOR_SNANS (<MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (<MODE>mode)"
"fmin.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1219,7 +1219,7 @@
(unspec:ANYF [(use (match_operand:ANYF 1 "register_operand" " f"))
(use (match_operand:ANYF 2 "register_operand" " f"))]
UNSPEC_FMAX))]
- "TARGET_HARD_FLOAT && !HONOR_SNANS (<MODE>mode)"
+ "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (<MODE>mode)"
"fmax.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1228,7 +1228,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(smin:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fmin.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1237,7 +1237,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(smax:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fmax.<fmt>\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
@@ -1298,7 +1298,7 @@
[(set (match_operand:SF 0 "register_operand" "=f")
(float_truncate:SF
(match_operand:DF 1 "register_operand" " f")))]
- "TARGET_DOUBLE_FLOAT"
+ "TARGET_DOUBLE_FLOAT || TARGET_ZDINX"
"fcvt.s.d\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")])
@@ -1307,7 +1307,7 @@
[(set (match_operand:HF 0 "register_operand" "=f")
(float_truncate:HF
(match_operand:SF 1 "register_operand" " f")))]
- "TARGET_ZFHMIN"
+ "TARGET_ZFHMIN || TARGET_ZHINXMIN"
"fcvt.h.s\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "HF")])
@@ -1316,7 +1316,8 @@
[(set (match_operand:HF 0 "register_operand" "=f")
(float_truncate:HF
(match_operand:DF 1 "register_operand" " f")))]
- "TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT"
+ "(TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT) ||
+ (TARGET_ZHINXMIN && TARGET_ZDINX)"
"fcvt.h.d\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "HF")])
@@ -1442,7 +1443,7 @@
[(set (match_operand:SF 0 "register_operand" "=f")
(float_extend:SF
(match_operand:HF 1 "register_operand" " f")))]
- "TARGET_ZFHMIN"
+ "TARGET_ZFHMIN || TARGET_ZHINXMIN"
"fcvt.s.h\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")])
@@ -1451,7 +1452,7 @@
[(set (match_operand:DF 0 "register_operand" "=f")
(float_extend:DF
(match_operand:SF 1 "register_operand" " f")))]
- "TARGET_DOUBLE_FLOAT"
+ "TARGET_DOUBLE_FLOAT || TARGET_ZDINX"
"fcvt.d.s\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")])
@@ -1460,7 +1461,8 @@
[(set (match_operand:DF 0 "register_operand" "=f")
(float_extend:DF
(match_operand:HF 1 "register_operand" " f")))]
- "TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT"
+ "(TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT) ||
+ (TARGET_ZHINXMIN && TARGET_ZDINX)"
"fcvt.d.h\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")])
@@ -1506,7 +1508,7 @@
[(set (match_operand:GPR 0 "register_operand" "=r")
(fix:GPR
(match_operand:ANYF 1 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fcvt.<GPR:ifmt>.<ANYF:fmt> %0,%1,rtz"
[(set_attr "type" "fcvt")
(set_attr "mode" "<ANYF:MODE>")])
@@ -1515,7 +1517,7 @@
[(set (match_operand:GPR 0 "register_operand" "=r")
(unsigned_fix:GPR
(match_operand:ANYF 1 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fcvt.<GPR:ifmt>u.<ANYF:fmt> %0,%1,rtz"
[(set_attr "type" "fcvt")
(set_attr "mode" "<ANYF:MODE>")])
@@ -1524,7 +1526,7 @@
[(set (match_operand:ANYF 0 "register_operand" "= f")
(float:ANYF
(match_operand:GPR 1 "reg_or_0_operand" " rJ")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fcvt.<ANYF:fmt>.<GPR:ifmt>\t%0,%z1"
[(set_attr "type" "fcvt")
(set_attr "mode" "<ANYF:MODE>")])
@@ -1533,7 +1535,7 @@
[(set (match_operand:ANYF 0 "register_operand" "= f")
(unsigned_float:ANYF
(match_operand:GPR 1 "reg_or_0_operand" " rJ")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fcvt.<ANYF:fmt>.<GPR:ifmt>u\t%0,%z1"
[(set_attr "type" "fcvt")
(set_attr "mode" "<ANYF:MODE>")])
@@ -1543,7 +1545,7 @@
(unspec:GPR
[(match_operand:ANYF 1 "register_operand" " f")]
RINT))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fcvt.<GPR:ifmt>.<ANYF:fmt> %0,%1,<rint_rm>"
[(set_attr "type" "fcvt")
(set_attr "mode" "<ANYF:MODE>")])
@@ -2271,7 +2273,7 @@
(match_operand:ANYF 2 "register_operand")])
(label_ref (match_operand 3 ""))
(pc)))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
{
riscv_expand_conditional_branch (operands[3], GET_CODE (operands[0]),
operands[1], operands[2]);
@@ -2360,7 +2362,7 @@
(match_operator:SI 1 "fp_scc_comparison"
[(match_operand:ANYF 2 "register_operand")
(match_operand:ANYF 3 "register_operand")]))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
{
riscv_expand_float_scc (operands[0], GET_CODE (operands[1]), operands[2],
operands[3]);
@@ -2372,7 +2374,7 @@
(match_operator:X 1 "fp_native_comparison"
[(match_operand:ANYF 2 "register_operand" " f")
(match_operand:ANYF 3 "register_operand" " f")]))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"f%C1.<fmt>\t%0,%2,%3"
[(set_attr "type" "fcmp")
(set_attr "mode" "<UNITMODE>")])
@@ -2382,7 +2384,7 @@
(unspec:X [(match_operand:ANYF 1 "register_operand")
(match_operand:ANYF 2 "register_operand")]
QUIET_COMPARISON))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
{
rtx op0 = operands[0];
rtx op1 = operands[1];
@@ -2802,19 +2804,19 @@
(define_insn "riscv_frflags"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec_volatile [(const_int 0)] UNSPECV_FRFLAGS))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"frflags\t%0")
(define_insn "riscv_fsflags"
[(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")] UNSPECV_FSFLAGS)]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fsflags\t%0")
(define_insn "*riscv_fsnvsnan<mode>2"
[(unspec_volatile [(match_operand:ANYF 0 "register_operand" "f")
(match_operand:ANYF 1 "register_operand" "f")]
UNSPECV_FSNVSNAN)]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"feq.<fmt>\tzero,%0,%1"
[(set_attr "type" "fcmp")
(set_attr "mode" "<UNITMODE>")])
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [v4 PATCH 3/4] RISC-V: Limit regs use for z*inx extension.
2022-10-20 9:32 [v4 PATCH 0/4] RISC-V: Support z*inx extensions jiawei
2022-10-20 9:32 ` [v4 PATCH 1/4] RISC-V: Minimal support of z*inx extension jiawei
2022-10-20 9:32 ` [v4 PATCH 2/4] RISC-V: Target support for " jiawei
@ 2022-10-20 9:32 ` jiawei
2022-10-27 3:12 ` Kito Cheng
2022-10-20 9:32 ` [v4 PATCH 4/4] RISC-V: Add zhinx/zhinxmin testcases jiawei
2022-10-27 3:12 ` [v4 PATCH 0/4] RISC-V: Support z*inx extensions Kito Cheng
4 siblings, 1 reply; 8+ messages in thread
From: jiawei @ 2022-10-20 9:32 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, christoph.muellner, wuwei2016, Jiawei
From: Jiawei <jiawei@iscas.ac.cn>
Limit z*inx abi support with 'ilp32','ilp32e','lp64' only.
Use GPR instead FPR when 'zfinx' enable, Only use even registers
in RV32 when 'zdinx' enable.
Enable FLOAT16 when Zhinx/Zhinxmin enabled.
Co-Authored-By: Sinan Lin.
gcc/ChangeLog:
* config/riscv/constraints.md (TARGET_ZFINX ? GR_REGS): Set GPRS
use while Zfinx is enable.
* config/riscv/riscv.cc (riscv_hard_regno_mode_ok): Limit odd
registers use when Zdinx enable in RV32 cases.
(riscv_option_override): New target enable MASK_FDIV.
(riscv_libgcc_floating_mode_supported_p): New error info when
use incompatible arch&abi.
(riscv_excess_precision): New target enable FLOAT16.
---
gcc/config/riscv/constraints.md | 5 +++--
gcc/config/riscv/riscv.cc | 21 +++++++++++++++++----
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 8997284f32e..c53e0f38920 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -21,8 +21,9 @@
;; Register constraints
-(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
- "A floating-point register (if available).")
+(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS :
+ (TARGET_ZFINX ? GR_REGS) : NO_REGS"
+ "A floating-point register (if available, reuse GPR as FPR when use zfinx).")
(define_register_constraint "j" "SIBCALL_REGS"
"@internal")
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ad57b995e7b..38631605b2c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5356,6 +5356,13 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
!= call_used_or_fixed_reg_p (regno + i))
return false;
+ /* Only use even registers in RV32 ZDINX */
+ if (!TARGET_64BIT && TARGET_ZDINX){
+ if (GET_MODE_CLASS (mode) == MODE_FLOAT &&
+ GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode))
+ return !(regno & 1);
+ }
+
return true;
}
@@ -5595,7 +5602,7 @@ riscv_option_override (void)
error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
/* Likewise floating-point division and square root. */
- if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0)
+ if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & MASK_FDIV) == 0)
target_flags |= MASK_FDIV;
/* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
@@ -5641,6 +5648,11 @@ riscv_option_override (void)
if (TARGET_RVE && riscv_abi != ABI_ILP32E)
error ("rv32e requires ilp32e ABI");
+ // Zfinx require abi ilp32,ilp32e or lp64.
+ if (TARGET_ZFINX && riscv_abi != ABI_ILP32
+ && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E)
+ error ("z*inx requires ABI ilp32, ilp32e or lp64");
+
/* We do not yet support ILP32 on RV64. */
if (BITS_PER_WORD != POINTER_SIZE)
error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
@@ -6273,7 +6285,7 @@ riscv_libgcc_floating_mode_supported_p (scalar_float_mode mode)
precision of the _FloatN type; evaluate all other operations and
constants to the range and precision of the semantic type;
- If we have the zfh extensions then we support _Float16 in native
+ If we have the zfh/zhinx extensions then we support _Float16 in native
precision, so we should set this to 16. */
static enum flt_eval_method
riscv_excess_precision (enum excess_precision_type type)
@@ -6282,8 +6294,9 @@ riscv_excess_precision (enum excess_precision_type type)
{
case EXCESS_PRECISION_TYPE_FAST:
case EXCESS_PRECISION_TYPE_STANDARD:
- return (TARGET_ZFH ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
- : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT);
+ return ((TARGET_ZFH || TARGET_ZHINX || TARGET_ZHINXMIN)
+ ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
+ : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT);
case EXCESS_PRECISION_TYPE_IMPLICIT:
case EXCESS_PRECISION_TYPE_FLOAT16:
return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16;
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [v4 PATCH 4/4] RISC-V: Add zhinx/zhinxmin testcases.
2022-10-20 9:32 [v4 PATCH 0/4] RISC-V: Support z*inx extensions jiawei
` (2 preceding siblings ...)
2022-10-20 9:32 ` [v4 PATCH 3/4] RISC-V: Limit regs use " jiawei
@ 2022-10-20 9:32 ` jiawei
2022-10-30 10:49 ` Andreas Schwab
2022-10-27 3:12 ` [v4 PATCH 0/4] RISC-V: Support z*inx extensions Kito Cheng
4 siblings, 1 reply; 8+ messages in thread
From: jiawei @ 2022-10-20 9:32 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, christoph.muellner, wuwei2016, Jiawei
From: Jiawei <jiawei@iscas.ac.cn>
Test zhinx/zhinxmin support, same like with zfh/zfhmin testcases
but use gprs and don't use fmv instruction.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/_Float16-zhinx-1.c: New test.
* gcc.target/riscv/_Float16-zhinx-2.c: New test.
* gcc.target/riscv/_Float16-zhinx-3.c: New test.
* gcc.target/riscv/_Float16-zhinxmin-1.c: New test.
* gcc.target/riscv/_Float16-zhinxmin-2.c: New test.
* gcc.target/riscv/_Float16-zhinxmin-3.c: New test.
---
gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c | 10 ++++++++++
gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c | 9 +++++++++
gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c | 9 +++++++++
gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c | 10 ++++++++++
gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c | 10 ++++++++++
gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c | 10 ++++++++++
6 files changed, 58 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
new file mode 100644
index 00000000000..90172b57e05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinx -mabi=lp64 -O" } */
+
+_Float16 foo1 (_Float16 a, _Float16 b)
+{
+ return b;
+}
+
+/* { dg-final { scan-assembler-not "fmv.h" } } */
+/* { dg-final { scan-assembler-times "mv" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c
new file mode 100644
index 00000000000..26f01198c97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinx -mabi=lp64 -O" } */
+
+_Float16 foo1 (_Float16 a, _Float16 b)
+{
+ /* { dg-final { scan-assembler-not "fadd.h fa" } } */
+ /* { dg-final { scan-assembler-times "fadd.h a" 1 } } */
+ return a + b;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c
new file mode 100644
index 00000000000..573913568e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinx -mabi=lp64 -O" } */
+
+int foo1 (_Float16 a, _Float16 b)
+{
+ /* { dg-final { scan-assembler-not "fgt.h fa" } } */
+ /* { dg-final { scan-assembler-times "fgt.h a" 1 } } */
+ return a > b;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c
new file mode 100644
index 00000000000..0070ebf616c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinxmin -mabi=lp64 -O" } */
+
+_Float16 foo1 (_Float16 a, _Float16 b)
+{
+ /* { dg-final { scan-assembler-not "fmv.h" } } */
+ /* { dg-final { scan-assembler-not "fmv.s" } } */
+ /* { dg-final { scan-assembler-times "mv" 1 } } */
+ return b;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c
new file mode 100644
index 00000000000..17f45a938d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinxmin -mabi=lp64 -O" } */
+
+_Float16 foo1 (_Float16 a, _Float16 b)
+{
+ /* { dg-final { scan-assembler-not "fadd.h" } } */
+ /* { dg-final { scan-assembler-not "fadd.s fa" } } */
+ /* { dg-final { scan-assembler-times "fadd.s a" 1 } } */
+ return a + b;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c
new file mode 100644
index 00000000000..7a43641a5a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64if_zfhmin -mabi=lp64f -O" } */
+
+int foo1 (_Float16 a, _Float16 b)
+{
+ /* { dg-final { scan-assembler-not "fgt.h" } } */
+ /* { dg-final { scan-assembler-not "fgt.s fa" } } */
+ /* { dg-final { scan-assembler-times "fgt.s a" 1 } } */
+ return a > b;
+}
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [v4 PATCH 3/4] RISC-V: Limit regs use for z*inx extension.
2022-10-20 9:32 ` [v4 PATCH 3/4] RISC-V: Limit regs use " jiawei
@ 2022-10-27 3:12 ` Kito Cheng
0 siblings, 0 replies; 8+ messages in thread
From: Kito Cheng @ 2022-10-27 3:12 UTC (permalink / raw)
To: jiawei; +Cc: gcc-patches, kito.cheng, wuwei2016
Hmmm 2 issue, but I fixed that anyway, otherwise LGTM.
> From: Jiawei <jiawei@iscas.ac.cn>
>
> Limit z*inx abi support with 'ilp32','ilp32e','lp64' only.
> Use GPR instead FPR when 'zfinx' enable, Only use even registers
> in RV32 when 'zdinx' enable.
> Enable FLOAT16 when Zhinx/Zhinxmin enabled.
>
> Co-Authored-By: Sinan Lin.
>
> gcc/ChangeLog:
>
> * config/riscv/constraints.md (TARGET_ZFINX ? GR_REGS): Set GPRS
> use while Zfinx is enable.
> * config/riscv/riscv.cc (riscv_hard_regno_mode_ok): Limit odd
> registers use when Zdinx enable in RV32 cases.
> (riscv_option_override): New target enable MASK_FDIV.
> (riscv_libgcc_floating_mode_supported_p): New error info when
> use incompatible arch&abi.
> (riscv_excess_precision): New target enable FLOAT16.
>
> ---
> gcc/config/riscv/constraints.md | 5 +++--
> gcc/config/riscv/riscv.cc | 21 +++++++++++++++++----
> 2 files changed, 20 insertions(+), 6 deletions(-)
>
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index 8997284f32e..c53e0f38920 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -21,8 +21,9 @@
>
> ;; Register constraints
>
> -(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
> - "A floating-point register (if available).")
> +(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS :
> + (TARGET_ZFINX ? GR_REGS) : NO_REGS"
(TARGET_ZFINX ? GR_REGS : NO_REGS)"
> + "A floating-point register (if available, reuse GPR as FPR when use zfinx).")
>
> (define_register_constraint "j" "SIBCALL_REGS"
> "@internal")
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index ad57b995e7b..38631605b2c 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -5356,6 +5356,13 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
> != call_used_or_fixed_reg_p (regno + i))
> return false;
>
> + /* Only use even registers in RV32 ZDINX */
> + if (!TARGET_64BIT && TARGET_ZDINX){
> + if (GET_MODE_CLASS (mode) == MODE_FLOAT &&
> + GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode))
> + return !(regno & 1);
> + }
> +
> return true;
> }
>
> @@ -5595,7 +5602,7 @@ riscv_option_override (void)
> error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
>
> /* Likewise floating-point division and square root. */
> - if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0)
> + if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & MASK_FDIV) == 0)
> target_flags |= MASK_FDIV;
>
> /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
> @@ -5641,6 +5648,11 @@ riscv_option_override (void)
> if (TARGET_RVE && riscv_abi != ABI_ILP32E)
> error ("rv32e requires ilp32e ABI");
>
> + // Zfinx require abi ilp32,ilp32e or lp64.
> + if (TARGET_ZFINX && riscv_abi != ABI_ILP32
> + && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E)
> + error ("z*inx requires ABI ilp32, ilp32e or lp64");
> +
> /* We do not yet support ILP32 on RV64. */
> if (BITS_PER_WORD != POINTER_SIZE)
> error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
> @@ -6273,7 +6285,7 @@ riscv_libgcc_floating_mode_supported_p (scalar_float_mode mode)
> precision of the _FloatN type; evaluate all other operations and
> constants to the range and precision of the semantic type;
>
> - If we have the zfh extensions then we support _Float16 in native
> + If we have the zfh/zhinx extensions then we support _Float16 in native
> precision, so we should set this to 16. */
> static enum flt_eval_method
> riscv_excess_precision (enum excess_precision_type type)
> @@ -6282,8 +6294,9 @@ riscv_excess_precision (enum excess_precision_type type)
> {
> case EXCESS_PRECISION_TYPE_FAST:
> case EXCESS_PRECISION_TYPE_STANDARD:
> - return (TARGET_ZFH ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
> - : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT);
> + return ((TARGET_ZFH || TARGET_ZHINX || TARGET_ZHINXMIN)
Should be (TARGET_ZFH || TARGET_ZHINX)
> + ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
> + : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT);
> case EXCESS_PRECISION_TYPE_IMPLICIT:
> case EXCESS_PRECISION_TYPE_FLOAT16:
> return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16;
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [v4 PATCH 0/4] RISC-V: Support z*inx extensions.
2022-10-20 9:32 [v4 PATCH 0/4] RISC-V: Support z*inx extensions jiawei
` (3 preceding siblings ...)
2022-10-20 9:32 ` [v4 PATCH 4/4] RISC-V: Add zhinx/zhinxmin testcases jiawei
@ 2022-10-27 3:12 ` Kito Cheng
4 siblings, 0 replies; 8+ messages in thread
From: Kito Cheng @ 2022-10-27 3:12 UTC (permalink / raw)
To: jiawei; +Cc: gcc-patches, kito.cheng, wuwei2016
Verified with qemu, committed to master, thanks!
On Thu, Oct 20, 2022 at 5:43 PM jiawei <jiawei@iscas.ac.cn> wrote:
>
> Zfinx extension[1] had already ratified. Here is the
> implementation patch set that reuse floating point pattern and ban
> the use of fpr when use z*inx as a target.
>
> Current works can be find in follow links, binutils and simulator
> works already supported on upstream.
> https://github.com/pz9115/riscv-gcc/tree/zfinx-rebase
>
> Thanks for Tariq Kurd, Kito Cheng, Jim Willson,
> Jeremy Bennett helped us a lot with this work.
>
> [1] https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0-rc.pdf
>
> Version log:
>
> v2: As Kito Cheng's comment, add Changelog part in patches, update imply
> info in riscv-common.c, remove useless check and update annotation in
> riscv.c.
>
> v3: Update with new isa-spec version 20191213, make zfinx imply zicsr as
> default, fix the lack of fcsr use in zfinx.
>
> v4: Rebase patch with upstream, add zhinx/zhinxmin extensions support.
> Add additional zhinx/zhinxmin same like zfh/zfhmin.
>
> Jiawei (4):
> RISC-V: Minimal support of z*inx extension.
> RISC-V: Target support for z*inx extension.
> RISC-V: Limit regs use for z*inx extension.
> RISC-V: Add zhinx/zhinxmin testcases.
>
> gcc/common/config/riscv/riscv-common.cc | 18 +++++
> gcc/config/riscv/arch-canonicalize | 5 ++
> gcc/config/riscv/constraints.md | 5 +-
> gcc/config/riscv/iterators.md | 6 +-
> gcc/config/riscv/riscv-builtins.cc | 4 +-
> gcc/config/riscv/riscv-c.cc | 2 +-
> gcc/config/riscv/riscv-opts.h | 10 +++
> gcc/config/riscv/riscv.cc | 21 ++++-
> gcc/config/riscv/riscv.md | 78 ++++++++++---------
> gcc/config/riscv/riscv.opt | 3 +
> .../gcc.target/riscv/_Float16-zhinx-1.c | 10 +++
> .../gcc.target/riscv/_Float16-zhinx-2.c | 9 +++
> .../gcc.target/riscv/_Float16-zhinx-3.c | 9 +++
> .../gcc.target/riscv/_Float16-zhinxmin-1.c | 10 +++
> .../gcc.target/riscv/_Float16-zhinxmin-2.c | 10 +++
> .../gcc.target/riscv/_Float16-zhinxmin-3.c | 10 +++
> 16 files changed, 160 insertions(+), 50 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [v4 PATCH 4/4] RISC-V: Add zhinx/zhinxmin testcases.
2022-10-20 9:32 ` [v4 PATCH 4/4] RISC-V: Add zhinx/zhinxmin testcases jiawei
@ 2022-10-30 10:49 ` Andreas Schwab
0 siblings, 0 replies; 8+ messages in thread
From: Andreas Schwab @ 2022-10-30 10:49 UTC (permalink / raw)
To: jiawei; +Cc: gcc-patches, kito.cheng, wuwei2016
On Okt 20 2022, jiawei wrote:
> diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
> new file mode 100644
> index 00000000000..90172b57e05
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
> @@ -0,0 +1,10 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64i_zhinx -mabi=lp64 -O" } */
> +
> +_Float16 foo1 (_Float16 a, _Float16 b)
> +{
> + return b;
> +}
> +
> +/* { dg-final { scan-assembler-not "fmv.h" } } */
> +/* { dg-final { scan-assembler-times "mv" 1 } } */
This fails with -flto (mv is found twice).
--
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
"And now for something completely different."
^ permalink raw reply [flat|nested] 8+ messages in thread
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2022-10-20 9:32 [v4 PATCH 0/4] RISC-V: Support z*inx extensions jiawei
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2022-10-20 9:32 ` [v4 PATCH 2/4] RISC-V: Target support for " jiawei
2022-10-20 9:32 ` [v4 PATCH 3/4] RISC-V: Limit regs use " jiawei
2022-10-27 3:12 ` Kito Cheng
2022-10-20 9:32 ` [v4 PATCH 4/4] RISC-V: Add zhinx/zhinxmin testcases jiawei
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