* [PATCH 01/20] sim: avr: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
@ 2022-12-23 6:06 ` Mike Frysinger
2022-12-23 6:06 ` [PATCH 02/20] sim: aarch64: " Mike Frysinger
` (19 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:06 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to a new header which only
this port will include.
---
sim/avr/avr-sim.h | 41 +++++++++++++++++++++++++++++++++++++++++
sim/avr/interp.c | 1 +
sim/avr/sim-main.h | 18 ------------------
3 files changed, 42 insertions(+), 18 deletions(-)
create mode 100644 sim/avr/avr-sim.h
diff --git a/sim/avr/avr-sim.h b/sim/avr/avr-sim.h
new file mode 100644
index 000000000000..479ef04fb42f
--- /dev/null
+++ b/sim/avr/avr-sim.h
@@ -0,0 +1,41 @@
+/* AVR Simulator definition.
+ Copyright (C) 2009-2022 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef AVR_SIM_H
+#define AVR_SIM_H
+
+#include <stdint.h>
+
+struct avr_sim_cpu {
+ /* The only real register. */
+ uint32_t pc;
+
+ /* We update a cycle counter. */
+ uint32_t cycles;
+};
+
+#define AVR_SIM_CPU(cpu) ((struct avr_sim_cpu *) CPU_ARCH_DATA (cpu))
+
+struct avr_sim_state {
+ /* If true, the pc needs more than 2 bytes. */
+ int avr_pc22;
+};
+
+#define AVR_SIM_STATE(sd) ((struct avr_sim_state *) STATE_ARCH_DATA (sd))
+
+#endif
diff --git a/sim/avr/interp.c b/sim/avr/interp.c
index b72da5363080..ddd9e1ff1eae 100644
--- a/sim/avr/interp.c
+++ b/sim/avr/interp.c
@@ -30,6 +30,7 @@
#include "sim-base.h"
#include "sim-options.h"
#include "sim-signal.h"
+#include "avr-sim.h"
/* As AVR is a 8/16 bits processor, define handy types. */
typedef unsigned short int word;
diff --git a/sim/avr/sim-main.h b/sim/avr/sim-main.h
index 97129ec91836..0c005370c091 100644
--- a/sim/avr/sim-main.h
+++ b/sim/avr/sim-main.h
@@ -20,24 +20,6 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#define SIM_MAIN_H
#include "sim-basics.h"
-
#include "sim-base.h"
-struct avr_sim_cpu {
- /* The only real register. */
- uint32_t pc;
-
- /* We update a cycle counter. */
- uint32_t cycles;
-};
-
-#define AVR_SIM_CPU(cpu) ((struct avr_sim_cpu *) CPU_ARCH_DATA (cpu))
-
-struct avr_sim_state {
- /* If true, the pc needs more than 2 bytes. */
- int avr_pc22;
-};
-
-#define AVR_SIM_STATE(sd) ((struct avr_sim_state *) STATE_ARCH_DATA (sd))
-
#endif
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 02/20] sim: aarch64: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
2022-12-23 6:06 ` [PATCH 01/20] sim: avr: move arch-specific settings to internal header Mike Frysinger
@ 2022-12-23 6:06 ` Mike Frysinger
2022-12-23 6:06 ` [PATCH 03/20] sim: arm: " Mike Frysinger
` (18 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:06 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to a new header which only
this port will include.
While we're here, drop redundant includes from sim-main.h:
* sim-types.h is included by sim-base.h already
* sim-base.h is included twice
* sim-io.h is included by sim-base.h already
---
sim/aarch64/aarch64-sim.h | 60 +++++++++++++++++++++++++++++++++++++++
sim/aarch64/cpustate.c | 2 ++
sim/aarch64/cpustate.h | 1 +
sim/aarch64/interp.c | 2 ++
sim/aarch64/sim-main.h | 35 -----------------------
sim/aarch64/simulator.c | 1 +
6 files changed, 66 insertions(+), 35 deletions(-)
create mode 100644 sim/aarch64/aarch64-sim.h
diff --git a/sim/aarch64/aarch64-sim.h b/sim/aarch64/aarch64-sim.h
new file mode 100644
index 000000000000..fe3820ffe09c
--- /dev/null
+++ b/sim/aarch64/aarch64-sim.h
@@ -0,0 +1,60 @@
+/* aarch64-sim.h -- Internal aarch64 settings.
+
+ Copyright (C) 2015-2022 Free Software Foundation, Inc.
+
+ Contributed by Red Hat.
+
+ This file is part of the GNU simulators.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef AARCH64_SIM_H
+#define AARCH64_SIM_H
+
+#include <stdint.h>
+
+#include "cpustate.h"
+
+/* A per-core state structure. */
+struct aarch64_sim_cpu
+{
+ GRegister gr[33]; /* Extra register at index 32 is used to hold zero value. */
+ FRegister fr[32];
+
+ uint64_t pc;
+ uint32_t CPSR;
+ uint32_t FPSR; /* Floating point Status register. */
+ uint32_t FPCR; /* Floating point Control register. */
+
+ uint64_t nextpc;
+ uint32_t instr;
+
+ uint64_t tpidr; /* Thread pointer id. */
+};
+
+#define AARCH64_SIM_CPU(cpu) ((struct aarch64_sim_cpu *) CPU_ARCH_DATA (cpu))
+
+typedef enum
+{
+ AARCH64_MIN_GR = 0,
+ AARCH64_MAX_GR = 31,
+ AARCH64_MIN_FR = 32,
+ AARCH64_MAX_FR = 63,
+ AARCH64_PC_REGNO = 64,
+ AARCH64_CPSR_REGNO = 65,
+ AARCH64_FPSR_REGNO = 66,
+ AARCH64_MAX_REGNO = 67
+} aarch64_regno;
+
+#endif /* AARCH64_SIM_H */
diff --git a/sim/aarch64/cpustate.c b/sim/aarch64/cpustate.c
index 24be34c49d9a..05f0d26f90a5 100644
--- a/sim/aarch64/cpustate.c
+++ b/sim/aarch64/cpustate.c
@@ -31,6 +31,8 @@
#include "simulator.h"
#include "libiberty.h"
+#include "aarch64-sim.h"
+
/* Some operands are allowed to access the stack pointer (reg 31).
For others a read from r31 always returns 0, and a write to r31 is ignored. */
#define reg_num(reg) (((reg) == R31 && !r31_is_sp) ? 32 : (reg))
diff --git a/sim/aarch64/cpustate.h b/sim/aarch64/cpustate.h
index 95c9d561fdb7..fe2a5819456e 100644
--- a/sim/aarch64/cpustate.h
+++ b/sim/aarch64/cpustate.h
@@ -27,6 +27,7 @@
#include <inttypes.h>
#include "sim/sim.h"
+#include "sim-main.h"
/* Symbolic names used to identify general registers which also match
the registers indices in machine code.
diff --git a/sim/aarch64/interp.c b/sim/aarch64/interp.c
index 99e84aa0adc6..234d978a7685 100644
--- a/sim/aarch64/interp.c
+++ b/sim/aarch64/interp.c
@@ -42,6 +42,8 @@
#include "simulator.h"
#include "sim-assert.h"
+#include "aarch64-sim.h"
+
/* Filter out (in place) symbols that are useless for disassembly.
COUNT is the number of elements in SYMBOLS.
Return the number of useful symbols. */
diff --git a/sim/aarch64/sim-main.h b/sim/aarch64/sim-main.h
index 211685f8864b..6b8da2df1f9a 100644
--- a/sim/aarch64/sim-main.h
+++ b/sim/aarch64/sim-main.h
@@ -23,41 +23,6 @@
#define _SIM_MAIN_H
#include "sim-basics.h"
-#include "sim-types.h"
#include "sim-base.h"
-#include "sim-base.h"
-#include "sim-io.h"
-#include "cpustate.h"
-
-/* A per-core state structure. */
-struct aarch64_sim_cpu
-{
- GRegister gr[33]; /* Extra register at index 32 is used to hold zero value. */
- FRegister fr[32];
-
- uint64_t pc;
- uint32_t CPSR;
- uint32_t FPSR; /* Floating point Status register. */
- uint32_t FPCR; /* Floating point Control register. */
-
- uint64_t nextpc;
- uint32_t instr;
-
- uint64_t tpidr; /* Thread pointer id. */
-};
-
-#define AARCH64_SIM_CPU(cpu) ((struct aarch64_sim_cpu *) CPU_ARCH_DATA (cpu))
-
-typedef enum
-{
- AARCH64_MIN_GR = 0,
- AARCH64_MAX_GR = 31,
- AARCH64_MIN_FR = 32,
- AARCH64_MAX_FR = 63,
- AARCH64_PC_REGNO = 64,
- AARCH64_CPSR_REGNO = 65,
- AARCH64_FPSR_REGNO = 66,
- AARCH64_MAX_REGNO = 67
-} aarch64_regno;
#endif /* _SIM_MAIN_H */
diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c
index 0a4fde1a9b26..6818e9731160 100644
--- a/sim/aarch64/simulator.c
+++ b/sim/aarch64/simulator.c
@@ -30,6 +30,7 @@
#include <time.h>
#include <limits.h>
+#include "aarch64-sim.h"
#include "simulator.h"
#include "cpustate.h"
#include "memory.h"
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 03/20] sim: arm: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
2022-12-23 6:06 ` [PATCH 01/20] sim: avr: move arch-specific settings to internal header Mike Frysinger
2022-12-23 6:06 ` [PATCH 02/20] sim: aarch64: " Mike Frysinger
@ 2022-12-23 6:06 ` Mike Frysinger
2022-12-23 6:06 ` [PATCH 04/20] sim: cr16: " Mike Frysinger
` (17 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:06 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to a new header which only
this port will include.
The BIT override would be better in the place where it's redefined, so
move it to armdefs.h instead.
---
sim/arm/arm-sim.h | 26 ++++++++++++++++++++++++++
sim/arm/armdefs.h | 6 ++++++
sim/arm/armemu.h | 2 ++
sim/arm/sim-main.h | 5 -----
sim/arm/wrapper.c | 1 +
5 files changed, 35 insertions(+), 5 deletions(-)
create mode 100644 sim/arm/arm-sim.h
diff --git a/sim/arm/arm-sim.h b/sim/arm/arm-sim.h
new file mode 100644
index 000000000000..65a1c676e8e9
--- /dev/null
+++ b/sim/arm/arm-sim.h
@@ -0,0 +1,26 @@
+/* Simulation code for the ARM processor.
+ Copyright (C) 2009-2022 Free Software Foundation, Inc.
+
+ This file is part of the GNU simulators.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef ARM_SIM_H
+#define ARM_SIM_H
+
+#include "armdefs.h"
+
+extern struct ARMul_State *state;
+
+#endif
diff --git a/sim/arm/armdefs.h b/sim/arm/armdefs.h
index 7df5d022942b..d87220bf29b6 100644
--- a/sim/arm/armdefs.h
+++ b/sim/arm/armdefs.h
@@ -14,6 +14,9 @@
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/>. */
+#ifndef ARMDEFS_H
+#define ARMDEFS_H
+
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
@@ -183,6 +186,7 @@ struct ARMul_State
* Macros to extract instruction fields *
\***************************************************************************/
+#undef BIT /* common/sim-bits.h conflict :( */
#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */
#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */
#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */
@@ -418,3 +422,5 @@ extern void ARMul_FixSPSR (ARMul_State *, ARMword, ARMword);
extern void ARMul_ConsolePrint (ARMul_State *, const char *, ...)
ATTRIBUTE_PRINTF (2, 3);
extern void ARMul_SelectProcessor (ARMul_State *, unsigned);
+
+#endif
diff --git a/sim/arm/armemu.h b/sim/arm/armemu.h
index 7f25b94d51cb..318f1b76d203 100644
--- a/sim/arm/armemu.h
+++ b/sim/arm/armemu.h
@@ -14,6 +14,8 @@
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/>. */
+#include "armdefs.h"
+
extern ARMword isize;
extern int trace;
extern int disas;
diff --git a/sim/arm/sim-main.h b/sim/arm/sim-main.h
index 5ca01eb91c5f..a08729b74608 100644
--- a/sim/arm/sim-main.h
+++ b/sim/arm/sim-main.h
@@ -22,9 +22,4 @@
#include "sim-basics.h"
#include "sim-base.h"
-#undef BIT
-#include "armdefs.h"
-
-extern struct ARMul_State *state;
-
#endif
diff --git a/sim/arm/wrapper.c b/sim/arm/wrapper.c
index 7b1153298f1d..5eb61df14378 100644
--- a/sim/arm/wrapper.c
+++ b/sim/arm/wrapper.c
@@ -41,6 +41,7 @@
#include "libiberty.h"
#include "iwmmxt.h"
#include "maverick.h"
+#include "arm-sim.h"
/* TODO: This should get pulled from the SIM_DESC. */
host_callback *sim_callback;
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 04/20] sim: cr16: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
` (2 preceding siblings ...)
2022-12-23 6:06 ` [PATCH 03/20] sim: arm: " Mike Frysinger
@ 2022-12-23 6:06 ` Mike Frysinger
2022-12-23 6:06 ` [PATCH 05/20] sim: d10v: " Mike Frysinger
` (16 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:06 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so drop the cr16_sim.h include and move it to
the few files that actually need it.
Also rename the file to standardize it a bit better with other ports.
---
sim/cr16/{cr16_sim.h => cr16-sim.h} | 1 +
sim/cr16/gencode.c | 3 ++-
sim/cr16/interp.c | 2 ++
sim/cr16/sim-main.h | 2 --
sim/cr16/simops.c | 2 ++
5 files changed, 7 insertions(+), 3 deletions(-)
rename sim/cr16/{cr16_sim.h => cr16-sim.h} (99%)
diff --git a/sim/cr16/cr16_sim.h b/sim/cr16/cr16-sim.h
similarity index 99%
rename from sim/cr16/cr16_sim.h
rename to sim/cr16/cr16-sim.h
index 86ee50a24ae2..0481f843308c 100644
--- a/sim/cr16/cr16_sim.h
+++ b/sim/cr16/cr16-sim.h
@@ -25,6 +25,7 @@
#include "sim/callback.h"
#include "opcode/cr16.h"
#include "bfd.h"
+#include "sim-main.h"
#define DEBUG_TRACE 0x00000001
#define DEBUG_VALUES 0x00000002
diff --git a/sim/cr16/gencode.c b/sim/cr16/gencode.c
index 210bc2f730b1..9b7b346c0d78 100644
--- a/sim/cr16/gencode.c
+++ b/sim/cr16/gencode.c
@@ -70,6 +70,7 @@ write_template (void)
printf ("#include \"defs.h\"\n");
printf ("#include \"sim-main.h\"\n");
+ printf ("#include \"cr16-sim.h\"\n");
printf ("#include \"simops.h\"\n\n");
for ( ; i < NUMOPCODES; i++)
@@ -134,7 +135,7 @@ write_opcodes (void)
/* write out opcode table. */
printf ("#include \"defs.h\"\n");
- printf ("#include \"sim-main.h\"\n");
+ printf ("#include \"cr16-sim.h\"\n");
printf ("#include \"simops.h\"\n\n");
printf ("struct simops Simops[] = {\n");
diff --git a/sim/cr16/interp.c b/sim/cr16/interp.c
index 1522ca4fa587..1830e348a060 100644
--- a/sim/cr16/interp.c
+++ b/sim/cr16/interp.c
@@ -38,6 +38,8 @@
#include "target-newlib-syscall.h"
+#include "cr16-sim.h"
+
struct _state State;
int cr16_debug;
diff --git a/sim/cr16/sim-main.h b/sim/cr16/sim-main.h
index a54a36559814..625d0505ec67 100644
--- a/sim/cr16/sim-main.h
+++ b/sim/cr16/sim-main.h
@@ -22,6 +22,4 @@
#include "sim-basics.h"
#include "sim-base.h"
-#include "cr16_sim.h"
-
#endif
diff --git a/sim/cr16/simops.c b/sim/cr16/simops.c
index 6eefe1bff60f..39a7214028f2 100644
--- a/sim/cr16/simops.c
+++ b/sim/cr16/simops.c
@@ -38,6 +38,8 @@
#include "simops.h"
#include "target-newlib-syscall.h"
+#include "cr16-sim.h"
+
#ifdef HAVE_UTIME_H
#include <utime.h>
#endif
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 05/20] sim: d10v: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
` (3 preceding siblings ...)
2022-12-23 6:06 ` [PATCH 04/20] sim: cr16: " Mike Frysinger
@ 2022-12-23 6:06 ` Mike Frysinger
2022-12-23 6:06 ` [PATCH 06/20] sim: ft32: " Mike Frysinger
` (15 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:06 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so drop the d10v_sim.h include and move it to
the few files that actually need it.
Also rename the file to standardize it a bit better with other ports.
---
sim/d10v/{d10v_sim.h => d10v-sim.h} | 5 +++++
sim/d10v/endian.c | 4 +++-
sim/d10v/gencode.c | 3 ++-
sim/d10v/interp.c | 2 ++
sim/d10v/sim-main.h | 2 --
sim/d10v/simops.c | 2 ++
6 files changed, 14 insertions(+), 4 deletions(-)
rename sim/d10v/{d10v_sim.h => d10v-sim.h} (99%)
diff --git a/sim/d10v/d10v_sim.h b/sim/d10v/d10v-sim.h
similarity index 99%
rename from sim/d10v/d10v_sim.h
rename to sim/d10v/d10v-sim.h
index e78ea2fe9df8..df12fe2757e6 100644
--- a/sim/d10v/d10v_sim.h
+++ b/sim/d10v/d10v-sim.h
@@ -1,3 +1,6 @@
+#ifndef D10V_SIM_H
+#define D10V_SIM_H
+
#include <stdio.h>
#include <ctype.h>
#include <limits.h>
@@ -476,3 +479,5 @@ extern void write_longlong (uint8_t *addr, int64_t data);
PSW is masked for zero bits. */
extern reg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, reg_t mask, reg_t val, int psw_hw_p);
+
+#endif
diff --git a/sim/d10v/endian.c b/sim/d10v/endian.c
index 44e80e6d6530..e6212babdaa9 100644
--- a/sim/d10v/endian.c
+++ b/sim/d10v/endian.c
@@ -1,5 +1,5 @@
/* If we're being compiled as a .c file, rather than being included in
- d10v_sim.h, then ENDIAN_INLINE won't be defined yet. */
+ d10v-sim.h, then ENDIAN_INLINE won't be defined yet. */
/* This must come before any other includes. */
#include "defs.h"
@@ -10,6 +10,8 @@
#define ENDIAN_INLINE
#endif
+#include "d10v-sim.h"
+
ENDIAN_INLINE uint16_t
get_word (const uint8_t *x)
{
diff --git a/sim/d10v/gencode.c b/sim/d10v/gencode.c
index 6e006d089a67..3a37bac62563 100644
--- a/sim/d10v/gencode.c
+++ b/sim/d10v/gencode.c
@@ -42,7 +42,7 @@ write_template (void)
struct d10v_opcode *opcode;
int i,j;
- printf ("#include \"sim-main.h\"\n");
+ printf ("#include \"d10v-sim.h\"\n");
printf ("#include \"simops.h\"\n");
for (opcode = (struct d10v_opcode *)d10v_opcodes; opcode->name; opcode++)
@@ -103,6 +103,7 @@ write_opcodes (void)
/* write out opcode table */
printf ("#include \"sim-main.h\"\n");
+ printf ("#include \"d10v-sim.h\"\n");
printf ("#include \"simops.h\"\n\n");
printf ("struct simops Simops[] = {\n");
diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c
index ae8b6707ed4b..9beedf8f445e 100644
--- a/sim/d10v/interp.c
+++ b/sim/d10v/interp.c
@@ -18,6 +18,8 @@
#include <stdlib.h>
#include <assert.h>
+#include "d10v-sim.h"
+
#include "target-newlib-syscall.h"
enum _leftright { LEFT_FIRST, RIGHT_FIRST };
diff --git a/sim/d10v/sim-main.h b/sim/d10v/sim-main.h
index 4e6771af70fc..3e0b74c63a40 100644
--- a/sim/d10v/sim-main.h
+++ b/sim/d10v/sim-main.h
@@ -22,6 +22,4 @@
#include "sim-basics.h"
#include "sim-base.h"
-#include "d10v_sim.h"
-
#endif
diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c
index a2eb3677e7e2..96ed29f6abe1 100644
--- a/sim/d10v/simops.c
+++ b/sim/d10v/simops.c
@@ -17,6 +17,8 @@
#include "simops.h"
#include "target-newlib-syscall.h"
+#include "d10v-sim.h"
+
#define EXCEPTION(sig) sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, sig)
enum op_types {
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 06/20] sim: ft32: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
` (4 preceding siblings ...)
2022-12-23 6:06 ` [PATCH 05/20] sim: d10v: " Mike Frysinger
@ 2022-12-23 6:06 ` Mike Frysinger
2022-12-23 6:07 ` [PATCH 07/20] sim: msp430: " Mike Frysinger
` (14 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:06 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so drop the ft32-sim.h include and move it to
the few files that actually need it.
---
sim/ft32/interp.c | 2 ++
sim/ft32/sim-main.h | 2 --
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/sim/ft32/interp.c b/sim/ft32/interp.c
index 9324475709e2..dfea4720c220 100644
--- a/sim/ft32/interp.c
+++ b/sim/ft32/interp.c
@@ -37,6 +37,8 @@
#include "opcode/ft32.h"
+#include "ft32-sim.h"
+
/*
* FT32 is a Harvard architecture: RAM and code occupy
* different address spaces.
diff --git a/sim/ft32/sim-main.h b/sim/ft32/sim-main.h
index 5c84f9e2f219..4529d0187560 100644
--- a/sim/ft32/sim-main.h
+++ b/sim/ft32/sim-main.h
@@ -24,6 +24,4 @@
#include "sim-basics.h"
#include "sim-base.h"
-#include "ft32-sim.h"
-
#endif
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 07/20] sim: msp430: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
` (5 preceding siblings ...)
2022-12-23 6:06 ` [PATCH 06/20] sim: ft32: " Mike Frysinger
@ 2022-12-23 6:07 ` Mike Frysinger
2022-12-23 6:07 ` [PATCH 08/20] sim: v850: standardize the arch-specific settings a little Mike Frysinger
` (13 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:07 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so drop the msp430-sim.h include and move it to
the few files that actually need it.
While we're here, drop redundant includes from sim-main.h:
* sim-config.h & sim-types.h included by sim-basics.h already
* sim-engine.h included by sim-base.h already
And move sim-options.h to the one file that needs it.
---
sim/msp430/msp430-sim.c | 2 ++
sim/msp430/msp430-sim.h | 2 ++
sim/msp430/sim-main.h | 8 --------
3 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/sim/msp430/msp430-sim.c b/sim/msp430/msp430-sim.c
index a13a0fe044a5..d402be77eb40 100644
--- a/sim/msp430/msp430-sim.c
+++ b/sim/msp430/msp430-sim.c
@@ -30,8 +30,10 @@
#include <assert.h>
#include "opcode/msp430-decode.h"
#include "sim-main.h"
+#include "sim-options.h"
#include "sim-signal.h"
#include "sim-syscall.h"
+#include "msp430-sim.h"
static sim_cia
msp430_pc_fetch (SIM_CPU *cpu)
diff --git a/sim/msp430/msp430-sim.h b/sim/msp430/msp430-sim.h
index 96af91d44163..e0933e58d1df 100644
--- a/sim/msp430/msp430-sim.h
+++ b/sim/msp430/msp430-sim.h
@@ -46,4 +46,6 @@ struct msp430_cpu_state
#define HWMULT(sd, field) MSP430_SIM_CPU (STATE_CPU (sd, 0))->field
+#define MSP430_SIM_CPU(cpu) ((struct msp430_cpu_state *) CPU_ARCH_DATA (cpu))
+
#endif
diff --git a/sim/msp430/sim-main.h b/sim/msp430/sim-main.h
index 5603d411df7b..92fce3cfbb9d 100644
--- a/sim/msp430/sim-main.h
+++ b/sim/msp430/sim-main.h
@@ -22,14 +22,6 @@
#define _MSP430_MAIN_SIM_H_
#include "sim-basics.h"
-#include "msp430-sim.h"
#include "sim-base.h"
-#define MSP430_SIM_CPU(cpu) ((struct msp430_cpu_state *) CPU_ARCH_DATA (cpu))
-
-#include "sim-config.h"
-#include "sim-types.h"
-#include "sim-engine.h"
-#include "sim-options.h"
-
#endif /* _MSP430_MAIN_SIM_H_ */
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 08/20] sim: v850: standardize the arch-specific settings a little
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
` (6 preceding siblings ...)
2022-12-23 6:07 ` [PATCH 07/20] sim: msp430: " Mike Frysinger
@ 2022-12-23 6:07 ` Mike Frysinger
2022-12-23 6:07 ` [PATCH 09/20] sim: riscv: move arch-specific settings to internal header Mike Frysinger
` (12 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:07 UTC (permalink / raw)
To: gdb-patches
Rename v850_sim.h to v850-sim.h to match other ports, and move most
of the arch-specific content out of sim-main.h to it. This isn't a
big win though as we still have to include the header in sim-main.h
due to the igen interface: it hardcodes including sim-main.h in its
files. So until we can fix that, we have to keep bleeding these
settings into the common codes.
---
sim/v850/interp.c | 2 +-
sim/v850/sim-main.h | 721 +------------------------------------------
sim/v850/simops.c | 2 +-
sim/v850/simops.h | 3 +
sim/v850/v850-sim.h | 722 ++++++++++++++++++++++++++++++++++++++++++++
sim/v850/v850_sim.h | 8 -
6 files changed, 733 insertions(+), 725 deletions(-)
create mode 100644 sim/v850/v850-sim.h
delete mode 100644 sim/v850/v850_sim.h
diff --git a/sim/v850/interp.c b/sim/v850/interp.c
index 4fa900eef2b7..efe35c606ffb 100644
--- a/sim/v850/interp.c
+++ b/sim/v850/interp.c
@@ -3,7 +3,7 @@
#include "sim-main.h"
#include "sim-options.h"
-#include "v850_sim.h"
+#include "v850-sim.h"
#include "sim-assert.h"
#include "itable.h"
diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h
index 9d56469d6665..6cd7ecce2c62 100644
--- a/sim/v850/sim-main.h
+++ b/sim/v850/sim-main.h
@@ -6,722 +6,13 @@
#define WITH_TARGET_WORD_MSB 31
#include "sim-basics.h"
-#include "sim-signal.h"
-#include "sim-fpu.h"
#include "sim-base.h"
-#include "simops.h"
-
-typedef uint32_t reg_t;
-typedef uint64_t reg64_t;
-
-
-/* The current state of the processor; registers, memory, etc. */
-
-typedef struct _v850_regs {
- reg_t regs[32]; /* general-purpose registers */
- reg_t sregs[32]; /* system registers, including psw */
- reg_t pc;
- int dummy_mem; /* where invalid accesses go */
- reg_t mpu0_sregs[28]; /* mpu0 system registers */
- reg_t mpu1_sregs[28]; /* mpu1 system registers */
- reg_t fpu_sregs[28]; /* fpu system registers */
- reg_t selID_sregs[7][32]; /* system registers, selID 1 thru selID 7 */
- reg64_t vregs[32]; /* vector registers. */
-} v850_regs;
-
-struct v850_sim_cpu {
- v850_regs reg;
- reg_t psw_mask; /* only allow non-reserved bits to be set */
- sim_event *pending_nmi;
-};
-
-#define V850_SIM_CPU(cpu) ((struct v850_sim_cpu *) CPU_ARCH_DATA (cpu))
-
-/* For compatibility, until all functions converted to passing
- SIM_DESC as an argument */
-extern SIM_DESC simulator;
-
-
-#define V850_ROM_SIZE 0x8000
-#define V850_LOW_END 0x200000
-#define V850_HIGH_START 0xffe000
-
-
-/* Because we are still using the old semantic table, provide compat
- macro's that store the instruction where the old simops expects
- it. */
-
-extern uint32_t OP[4];
-#if 0
-OP[0] = inst & 0x1f; /* RRRRR -> reg1 */
-OP[1] = (inst >> 11) & 0x1f; /* rrrrr -> reg2 */
-OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
-OP[3] = inst;
-#endif
-
-#define SAVE_1 \
-PC = cia; \
-OP[0] = instruction_0 & 0x1f; \
-OP[1] = (instruction_0 >> 11) & 0x1f; \
-OP[2] = 0; \
-OP[3] = instruction_0
-
-#define COMPAT_1(CALL) \
-SAVE_1; \
-PC += (CALL); \
-nia = PC
-
-#define SAVE_2 \
-PC = cia; \
-OP[0] = instruction_0 & 0x1f; \
-OP[1] = (instruction_0 >> 11) & 0x1f; \
-OP[2] = instruction_1; \
-OP[3] = (instruction_1 << 16) | instruction_0
-
-#define COMPAT_2(CALL) \
-SAVE_2; \
-PC += (CALL); \
-nia = PC
-
-
-/* new */
-#define GR (V850_SIM_CPU (CPU)->reg.regs)
-#define SR (V850_SIM_CPU (CPU)->reg.sregs)
-#define VR (V850_SIM_CPU (CPU)->reg.vregs)
-#define MPU0_SR (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.mpu0_sregs)
-#define MPU1_SR (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.mpu1_sregs)
-#define FPU_SR (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.fpu_sregs)
-
-/* old */
-#define State (V850_SIM_CPU (STATE_CPU (simulator, 0))->reg)
-#define PC (State.pc)
-#define SP_REGNO 3
-#define SP (State.regs[SP_REGNO])
-#define EP (State.regs[30])
-
-#define EIPC (State.sregs[0])
-#define EIPSW (State.sregs[1])
-#define FEPC (State.sregs[2])
-#define FEPSW (State.sregs[3])
-#define ECR (State.sregs[4])
-#define PSW (State.sregs[5])
-#define PSW_REGNO 5
-#define EIIC (State.sregs[13])
-#define FEIC (State.sregs[14])
-#define DBIC (SR[15])
-#define CTPC (SR[16])
-#define CTPSW (SR[17])
-#define DBPC (State.sregs[18])
-#define DBPSW (State.sregs[19])
-#define CTBP (State.sregs[20])
-#define DIR (SR[21])
-#define EIWR (SR[28])
-#define FEWR (SR[29])
-#define DBWR (SR[30])
-#define BSEL (SR[31])
-
-#define PSW_US BIT32 (8)
-#define PSW_NP 0x80
-#define PSW_EP 0x40
-#define PSW_ID 0x20
-#define PSW_SAT 0x10
-#define PSW_CY 0x8
-#define PSW_OV 0x4
-#define PSW_S 0x2
-#define PSW_Z 0x1
-
-#define PSW_NPV (1<<18)
-#define PSW_DMP (1<<17)
-#define PSW_IMP (1<<16)
-
-#define ECR_EICC 0x0000ffff
-#define ECR_FECC 0xffff0000
-
-/* FPU */
-
-#define FPSR (FPU_SR[6])
-#define FPSR_REGNO 6
-#define FPEPC (FPU_SR[7])
-#define FPST (FPU_SR[8])
-#define FPST_REGNO 8
-#define FPCC (FPU_SR[9])
-#define FPCFG (FPU_SR[10])
-#define FPCFG_REGNO 10
-
-#define FPSR_DEM 0x00200000
-#define FPSR_SEM 0x00100000
-#define FPSR_RM 0x000c0000
-#define FPSR_RN 0x00000000
-#define FPSR_FS 0x00020000
-#define FPSR_PR 0x00010000
-
-#define FPSR_XC 0x0000fc00
-#define FPSR_XCE 0x00008000
-#define FPSR_XCV 0x00004000
-#define FPSR_XCZ 0x00002000
-#define FPSR_XCO 0x00001000
-#define FPSR_XCU 0x00000800
-#define FPSR_XCI 0x00000400
-
-#define FPSR_XE 0x000003e0
-#define FPSR_XEV 0x00000200
-#define FPSR_XEZ 0x00000100
-#define FPSR_XEO 0x00000080
-#define FPSR_XEU 0x00000040
-#define FPSR_XEI 0x00000020
-
-#define FPSR_XP 0x0000001f
-#define FPSR_XPV 0x00000010
-#define FPSR_XPZ 0x00000008
-#define FPSR_XPO 0x00000004
-#define FPSR_XPU 0x00000002
-#define FPSR_XPI 0x00000001
-
-#define FPST_PR 0x00008000
-#define FPST_XCE 0x00002000
-#define FPST_XCV 0x00001000
-#define FPST_XCZ 0x00000800
-#define FPST_XCO 0x00000400
-#define FPST_XCU 0x00000200
-#define FPST_XCI 0x00000100
-
-#define FPST_XPV 0x00000010
-#define FPST_XPZ 0x00000008
-#define FPST_XPO 0x00000004
-#define FPST_XPU 0x00000002
-#define FPST_XPI 0x00000001
-
-#define FPCFG_RM 0x00000180
-#define FPCFG_XEV 0x00000010
-#define FPCFG_XEZ 0x00000008
-#define FPCFG_XEO 0x00000004
-#define FPCFG_XEU 0x00000002
-#define FPCFG_XEI 0x00000001
-
-#define GET_FPCC()\
- ((FPSR >> 24) &0xf)
-
-#define CLEAR_FPCC(bbb)\
- (FPSR &= ~(1 << (bbb+24)))
-
-#define SET_FPCC(bbb)\
- (FPSR |= 1 << (bbb+24))
-
-#define TEST_FPCC(bbb)\
- ((FPSR & (1 << (bbb+24))) != 0)
-
-#define FPSR_GET_ROUND() \
- (((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near \
- : ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up \
- : ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down \
- : sim_fpu_round_zero)
-
-
-enum FPU_COMPARE {
- FPU_CMP_F = 0,
- FPU_CMP_UN,
- FPU_CMP_EQ,
- FPU_CMP_UEQ,
- FPU_CMP_OLT,
- FPU_CMP_ULT,
- FPU_CMP_OLE,
- FPU_CMP_ULE,
- FPU_CMP_SF,
- FPU_CMP_NGLE,
- FPU_CMP_SEQ,
- FPU_CMP_NGL,
- FPU_CMP_LT,
- FPU_CMP_NGE,
- FPU_CMP_LE,
- FPU_CMP_NGT
-};
-
-
-/* MPU */
-#define MPM (MPU1_SR[0])
-#define MPC (MPU1_SR[1])
-#define MPC_REGNO 1
-#define TID (MPU1_SR[2])
-#define PPA (MPU1_SR[3])
-#define PPM (MPU1_SR[4])
-#define PPC (MPU1_SR[5])
-#define DCC (MPU1_SR[6])
-#define DCV0 (MPU1_SR[7])
-#define DCV1 (MPU1_SR[8])
-#define SPAL (MPU1_SR[10])
-#define SPAU (MPU1_SR[11])
-#define IPA0L (MPU1_SR[12])
-#define IPA0U (MPU1_SR[13])
-#define IPA1L (MPU1_SR[14])
-#define IPA1U (MPU1_SR[15])
-#define IPA2L (MPU1_SR[16])
-#define IPA2U (MPU1_SR[17])
-#define IPA3L (MPU1_SR[18])
-#define IPA3U (MPU1_SR[19])
-#define DPA0L (MPU1_SR[20])
-#define DPA0U (MPU1_SR[21])
-#define DPA1L (MPU1_SR[22])
-#define DPA1U (MPU1_SR[23])
-#define DPA2L (MPU1_SR[24])
-#define DPA2U (MPU1_SR[25])
-#define DPA3L (MPU1_SR[26])
-#define DPA3U (MPU1_SR[27])
-
-#define PPC_PPE 0x1
-#define SPAL_SPE 0x1
-#define SPAL_SPS 0x10
-
-#define VIP (MPU0_SR[0])
-#define VMECR (MPU0_SR[4])
-#define VMTID (MPU0_SR[5])
-#define VMADR (MPU0_SR[6])
-#define VPECR (MPU0_SR[8])
-#define VPTID (MPU0_SR[9])
-#define VPADR (MPU0_SR[10])
-#define VDECR (MPU0_SR[12])
-#define VDTID (MPU0_SR[13])
-
-#define MPM_AUE 0x2
-#define MPM_MPE 0x1
-
-#define VMECR_VMX 0x2
-#define VMECR_VMR 0x4
-#define VMECR_VMW 0x8
-#define VMECR_VMS 0x10
-#define VMECR_VMRMW 0x20
-#define VMECR_VMMS 0x40
-
-#define IPA2ADDR(IPA) ((IPA) & 0x1fffff80)
-#define IPA_IPE 0x1
-#define IPA_IPX 0x2
-#define IPA_IPR 0x4
-#define IPE0 (IPA0L & IPA_IPE)
-#define IPE1 (IPA1L & IPA_IPE)
-#define IPE2 (IPA2L & IPA_IPE)
-#define IPE3 (IPA3L & IPA_IPE)
-#define IPX0 (IPA0L & IPA_IPX)
-#define IPX1 (IPA1L & IPA_IPX)
-#define IPX2 (IPA2L & IPA_IPX)
-#define IPX3 (IPA3L & IPA_IPX)
-#define IPR0 (IPA0L & IPA_IPR)
-#define IPR1 (IPA1L & IPA_IPR)
-#define IPR2 (IPA2L & IPA_IPR)
-#define IPR3 (IPA3L & IPA_IPR)
-
-#define DPA2ADDR(DPA) ((DPA) & 0x1fffff80)
-#define DPA_DPE 0x1
-#define DPA_DPR 0x4
-#define DPA_DPW 0x8
-#define DPE0 (DPA0L & DPA_DPE)
-#define DPE1 (DPA1L & DPA_DPE)
-#define DPE2 (DPA2L & DPA_DPE)
-#define DPE3 (DPA3L & DPA_DPE)
-#define DPR0 (DPA0L & DPA_DPR)
-#define DPR1 (DPA1L & DPA_DPR)
-#define DPR2 (DPA2L & DPA_DPR)
-#define DPR3 (DPA3L & DPA_DPR)
-#define DPW0 (DPA0L & DPA_DPW)
-#define DPW1 (DPA1L & DPA_DPW)
-#define DPW2 (DPA2L & DPA_DPW)
-#define DPW3 (DPA3L & DPA_DPW)
-
-#define DCC_DCE0 0x1
-#define DCC_DCE1 0x10000
-
-#define PPA2ADDR(PPA) ((PPA) & 0x1fffff80)
-#define PPC_PPC 0xfffffffe
-#define PPC_PPE 0x1
-#define PPC_PPM 0x0000fff8
-
-
-#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
-
-/* sign-extend a 4-bit number */
-#define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
-
-/* sign-extend a 5-bit number */
-#define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
-
-/* sign-extend a 9-bit number */
-#define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
-
-/* sign-extend a 22-bit number */
-#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
-
-/* sign extend a 40 bit number */
-#define SEXT40(x) ((((x) & UNSIGNED64 (0xffffffffff)) \
- ^ (~UNSIGNED64 (0x7fffffffff))) \
- + UNSIGNED64 (0x8000000000))
-
-/* sign extend a 44 bit number */
-#define SEXT44(x) ((((x) & UNSIGNED64 (0xfffffffffff)) \
- ^ (~ UNSIGNED64 (0x7ffffffffff))) \
- + UNSIGNED64 (0x80000000000))
-
-/* sign extend a 60 bit number */
-#define SEXT60(x) ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
- ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
- + UNSIGNED64 (0x800000000000000))
-
-/* No sign extension */
-#define NOP(x) (x)
-
-#define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
-
-#define RLW(x) load_mem (x, 4)
-
-/* Function declarations. */
-
-#define IMEM16(EA) \
-sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
-
-#define IMEM16_IMMED(EA,N) \
-sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
- PC, exec_map, (EA) + (N) * 2)
-
-#define load_mem(ADDR,LEN) \
-sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
- PC, read_map, (ADDR))
-
-#define store_mem(ADDR,LEN,DATA) \
-sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
- PC, write_map, (ADDR), (DATA))
-
-
-/* compare cccc field against PSW */
-int condition_met (unsigned code);
-
-
-/* Debug/tracing calls */
-
-enum op_types
-{
- OP_UNKNOWN,
- OP_NONE,
- OP_TRAP,
- OP_REG,
- OP_REG_REG,
- OP_REG_REG_CMP,
- OP_REG_REG_MOVE,
- OP_IMM_REG,
- OP_IMM_REG_CMP,
- OP_IMM_REG_MOVE,
- OP_COND_BR,
- OP_LOAD16,
- OP_STORE16,
- OP_LOAD32,
- OP_STORE32,
- OP_JUMP,
- OP_IMM_REG_REG,
- OP_UIMM_REG_REG,
- OP_IMM16_REG_REG,
- OP_UIMM16_REG_REG,
- OP_BIT,
- OP_EX1,
- OP_EX2,
- OP_LDSR,
- OP_STSR,
- OP_BIT_CHANGE,
- OP_REG_REG_REG,
- OP_REG_REG3,
- OP_IMM_REG_REG_REG,
- OP_PUSHPOP1,
- OP_PUSHPOP2,
- OP_PUSHPOP3,
-};
-
-#if WITH_TRACE_ANY_P
-void trace_input (char *name, enum op_types type, int size);
-void trace_output (enum op_types result);
-void trace_result (int has_result, uint32_t result);
-
-extern int trace_num_values;
-extern uint32_t trace_values[];
-extern uint32_t trace_pc;
-extern const char *trace_name;
-extern int trace_module;
-
-#define TRACE_BRANCH0() \
-do { \
- if (TRACE_BRANCH_P (CPU)) { \
- trace_module = TRACE_BRANCH_IDX; \
- trace_pc = cia; \
- trace_name = itable[MY_INDEX].name; \
- trace_num_values = 0; \
- trace_result (1, (nia)); \
- } \
-} while (0)
-
-#define TRACE_BRANCH1(IN1) \
-do { \
- if (TRACE_BRANCH_P (CPU)) { \
- trace_module = TRACE_BRANCH_IDX; \
- trace_pc = cia; \
- trace_name = itable[MY_INDEX].name; \
- trace_values[0] = (IN1); \
- trace_num_values = 1; \
- trace_result (1, (nia)); \
- } \
-} while (0)
-
-#define TRACE_BRANCH2(IN1, IN2) \
-do { \
- if (TRACE_BRANCH_P (CPU)) { \
- trace_module = TRACE_BRANCH_IDX; \
- trace_pc = cia; \
- trace_name = itable[MY_INDEX].name; \
- trace_values[0] = (IN1); \
- trace_values[1] = (IN2); \
- trace_num_values = 2; \
- trace_result (1, (nia)); \
- } \
-} while (0)
-
-#define TRACE_BRANCH3(IN1, IN2, IN3) \
-do { \
- if (TRACE_BRANCH_P (CPU)) { \
- trace_module = TRACE_BRANCH_IDX; \
- trace_pc = cia; \
- trace_name = itable[MY_INDEX].name; \
- trace_values[0] = (IN1); \
- trace_values[1] = (IN2); \
- trace_values[2] = (IN3); \
- trace_num_values = 3; \
- trace_result (1, (nia)); \
- } \
-} while (0)
-
-#define TRACE_LD(ADDR,RESULT) \
-do { \
- if (TRACE_MEMORY_P (CPU)) { \
- trace_module = TRACE_MEMORY_IDX; \
- trace_pc = cia; \
- trace_name = itable[MY_INDEX].name; \
- trace_values[0] = (ADDR); \
- trace_num_values = 1; \
- trace_result (1, (RESULT)); \
- } \
-} while (0)
-
-#define TRACE_LD_NAME(NAME, ADDR,RESULT) \
-do { \
- if (TRACE_MEMORY_P (CPU)) { \
- trace_module = TRACE_MEMORY_IDX; \
- trace_pc = cia; \
- trace_name = (NAME); \
- trace_values[0] = (ADDR); \
- trace_num_values = 1; \
- trace_result (1, (RESULT)); \
- } \
-} while (0)
-
-#define TRACE_ST(ADDR,RESULT) \
-do { \
- if (TRACE_MEMORY_P (CPU)) { \
- trace_module = TRACE_MEMORY_IDX; \
- trace_pc = cia; \
- trace_name = itable[MY_INDEX].name; \
- trace_values[0] = (ADDR); \
- trace_num_values = 1; \
- trace_result (1, (RESULT)); \
- } \
-} while (0)
-
-#define TRACE_FP_INPUT_FPU1(V0) \
-do { \
- if (TRACE_FPU_P (CPU)) \
- { \
- uint64_t f0; \
- sim_fpu_to64 (&f0, (V0)); \
- trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
- } \
-} while (0)
-
-#define TRACE_FP_INPUT_FPU2(V0, V1) \
-do { \
- if (TRACE_FPU_P (CPU)) \
- { \
- uint64_t f0, f1; \
- sim_fpu_to64 (&f0, (V0)); \
- sim_fpu_to64 (&f1, (V1)); \
- trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \
- } \
-} while (0)
-
-#define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
-do { \
- if (TRACE_FPU_P (CPU)) \
- { \
- uint64_t f0, f1, f2; \
- sim_fpu_to64 (&f0, (V0)); \
- sim_fpu_to64 (&f1, (V1)); \
- sim_fpu_to64 (&f2, (V2)); \
- trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \
- } \
-} while (0)
-
-#define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
-do { \
- if (TRACE_FPU_P (CPU)) \
- { \
- int d0 = (V0); \
- uint64_t f1, f2; \
- TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
- TRACE_IDX (data) = TRACE_FPU_IDX; \
- sim_fpu_to64 (&f1, (V1)); \
- sim_fpu_to64 (&f2, (V2)); \
- save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \
- save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \
- save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \
- } \
-} while (0)
-
-#define TRACE_FP_INPUT_WORD2(V0, V1) \
-do { \
- if (TRACE_FPU_P (CPU)) \
- trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \
-} while (0)
-
-#define TRACE_FP_RESULT_FPU1(R0) \
-do { \
- if (TRACE_FPU_P (CPU)) \
- { \
- uint64_t f0; \
- sim_fpu_to64 (&f0, (R0)); \
- trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
- } \
-} while (0)
-
-#define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0)
-
-#define TRACE_FP_RESULT_WORD2(R0, R1) \
-do { \
- if (TRACE_FPU_P (CPU)) \
- trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \
-} while (0)
-
-#else
-#define trace_input(NAME, IN1, IN2)
-#define trace_output(RESULT)
-#define trace_result(HAS_RESULT, RESULT)
-
-#define TRACE_ALU_INPUT0()
-#define TRACE_ALU_INPUT1(IN0)
-#define TRACE_ALU_INPUT2(IN0, IN1)
-#define TRACE_ALU_INPUT2(IN0, IN1)
-#define TRACE_ALU_INPUT2(IN0, IN1 INS2)
-#define TRACE_ALU_RESULT(RESULT)
-
-#define TRACE_BRANCH0()
-#define TRACE_BRANCH1(IN1)
-#define TRACE_BRANCH2(IN1, IN2)
-#define TRACE_BRANCH2(IN1, IN2, IN3)
-
-#define TRACE_LD(ADDR,RESULT)
-#define TRACE_ST(ADDR,RESULT)
-
-#endif
-
-#define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
-#define GPR_CLEAR(N) (State.regs[(N)] = 0)
-
-extern void divun ( unsigned int N,
- unsigned long int als,
- unsigned long int sfi,
- uint32_t /*unsigned long int*/ * quotient_ptr,
- uint32_t /*unsigned long int*/ * remainder_ptr,
- int *overflow_ptr
- );
-extern void divn ( unsigned int N,
- unsigned long int als,
- unsigned long int sfi,
- int32_t /*signed long int*/ * quotient_ptr,
- int32_t /*signed long int*/ * remainder_ptr,
- int *overflow_ptr
- );
-extern int type1_regs[];
-extern int type2_regs[];
-extern int type3_regs[];
-
-#define SESR_OV (1 << 0)
-#define SESR_SOV (1 << 1)
-
-#define SESR (State.sregs[12])
-
-#define ROUND_Q62_Q31(X) ((((X) + (1 << 30)) >> 31) & 0xffffffff)
-#define ROUND_Q62_Q15(X) ((((X) + (1 << 30)) >> 47) & 0xffff)
-#define ROUND_Q31_Q15(X) ((((X) + (1 << 15)) >> 15) & 0xffff)
-#define ROUND_Q30_Q15(X) ((((X) + (1 << 14)) >> 15) & 0xffff)
-
-#define SAT16(X) \
- do \
- { \
- int64_t z = (X); \
- if (z > 0x7fff) \
- { \
- SESR |= SESR_OV | SESR_SOV; \
- z = 0x7fff; \
- } \
- else if (z < -0x8000) \
- { \
- SESR |= SESR_OV | SESR_SOV; \
- z = - 0x8000; \
- } \
- (X) = z; \
- } \
- while (0)
-
-#define SAT32(X) \
- do \
- { \
- int64_t z = (X); \
- if (z > 0x7fffffff) \
- { \
- SESR |= SESR_OV | SESR_SOV; \
- z = 0x7fffffff; \
- } \
- else if (z < -0x80000000) \
- { \
- SESR |= SESR_OV | SESR_SOV; \
- z = - 0x80000000; \
- } \
- (X) = z; \
- } \
- while (0)
-
-#define ABS16(X) \
- do \
- { \
- int64_t z = (X) & 0xffff; \
- if (z == 0x8000) \
- { \
- SESR |= SESR_OV | SESR_SOV; \
- z = 0x7fff; \
- } \
- else if (z & 0x8000) \
- { \
- z = (- z) & 0xffff; \
- } \
- (X) = z; \
- } \
- while (0)
-
-#define ABS32(X) \
- do \
- { \
- int64_t z = (X) & 0xffffffff; \
- if (z == 0x80000000) \
- { \
- SESR |= SESR_OV | SESR_SOV; \
- z = 0x7fffffff; \
- } \
- else if (z & 0x80000000) \
- { \
- z = (- z) & 0xffffffff; \
- } \
- (X) = z; \
- } \
- while (0)
+/**
+ * TODO: Move these includes to the igen files that need them.
+ * This requires extending the igen syntax to support header includes.
+ */
+#include "sim-signal.h"
+#include "v850-sim.h"
#endif
diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index 67656d398c80..5783f8606b30 100644
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -3,7 +3,7 @@
#include "sim-main.h"
#include "sim-signal.h"
-#include "v850_sim.h"
+#include "v850-sim.h"
#include "simops.h"
#include <sys/types.h>
diff --git a/sim/v850/simops.h b/sim/v850/simops.h
index 85339f55cbe1..bdcba6921f75 100644
--- a/sim/v850/simops.h
+++ b/sim/v850/simops.h
@@ -1,5 +1,8 @@
#ifndef SIMOPS_H
#define SIMOPS_H
+
+#include "sim-fpu.h"
+
int OP_380 (void);
int OP_480 (void);
int OP_501 (void);
diff --git a/sim/v850/v850-sim.h b/sim/v850/v850-sim.h
new file mode 100644
index 000000000000..35032306235f
--- /dev/null
+++ b/sim/v850/v850-sim.h
@@ -0,0 +1,722 @@
+#ifndef V850_SIM_H
+#define V850_SIM_H
+
+#include <stdint.h>
+
+struct simops
+{
+ unsigned long opcode;
+ unsigned long mask;
+ int (* func) (void);
+ int numops;
+ int operands[12];
+};
+
+#include "simops.h"
+
+typedef uint32_t reg_t;
+typedef uint64_t reg64_t;
+
+
+/* The current state of the processor; registers, memory, etc. */
+
+typedef struct _v850_regs {
+ reg_t regs[32]; /* general-purpose registers */
+ reg_t sregs[32]; /* system registers, including psw */
+ reg_t pc;
+ int dummy_mem; /* where invalid accesses go */
+ reg_t mpu0_sregs[28]; /* mpu0 system registers */
+ reg_t mpu1_sregs[28]; /* mpu1 system registers */
+ reg_t fpu_sregs[28]; /* fpu system registers */
+ reg_t selID_sregs[7][32]; /* system registers, selID 1 thru selID 7 */
+ reg64_t vregs[32]; /* vector registers. */
+} v850_regs;
+
+struct v850_sim_cpu {
+ v850_regs reg;
+ reg_t psw_mask; /* only allow non-reserved bits to be set */
+ sim_event *pending_nmi;
+};
+
+#define V850_SIM_CPU(cpu) ((struct v850_sim_cpu *) CPU_ARCH_DATA (cpu))
+
+/* For compatibility, until all functions converted to passing
+ SIM_DESC as an argument */
+extern SIM_DESC simulator;
+
+
+#define V850_ROM_SIZE 0x8000
+#define V850_LOW_END 0x200000
+#define V850_HIGH_START 0xffe000
+
+
+/* Because we are still using the old semantic table, provide compat
+ macro's that store the instruction where the old simops expects
+ it. */
+
+extern uint32_t OP[4];
+#if 0
+OP[0] = inst & 0x1f; /* RRRRR -> reg1 */
+OP[1] = (inst >> 11) & 0x1f; /* rrrrr -> reg2 */
+OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
+OP[3] = inst;
+#endif
+
+#define SAVE_1 \
+PC = cia; \
+OP[0] = instruction_0 & 0x1f; \
+OP[1] = (instruction_0 >> 11) & 0x1f; \
+OP[2] = 0; \
+OP[3] = instruction_0
+
+#define COMPAT_1(CALL) \
+SAVE_1; \
+PC += (CALL); \
+nia = PC
+
+#define SAVE_2 \
+PC = cia; \
+OP[0] = instruction_0 & 0x1f; \
+OP[1] = (instruction_0 >> 11) & 0x1f; \
+OP[2] = instruction_1; \
+OP[3] = (instruction_1 << 16) | instruction_0
+
+#define COMPAT_2(CALL) \
+SAVE_2; \
+PC += (CALL); \
+nia = PC
+
+
+/* new */
+#define GR (V850_SIM_CPU (CPU)->reg.regs)
+#define SR (V850_SIM_CPU (CPU)->reg.sregs)
+#define VR (V850_SIM_CPU (CPU)->reg.vregs)
+#define MPU0_SR (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.mpu0_sregs)
+#define MPU1_SR (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.mpu1_sregs)
+#define FPU_SR (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.fpu_sregs)
+
+/* old */
+#define State (V850_SIM_CPU (STATE_CPU (simulator, 0))->reg)
+#define PC (State.pc)
+#define SP_REGNO 3
+#define SP (State.regs[SP_REGNO])
+#define EP (State.regs[30])
+
+#define EIPC (State.sregs[0])
+#define EIPSW (State.sregs[1])
+#define FEPC (State.sregs[2])
+#define FEPSW (State.sregs[3])
+#define ECR (State.sregs[4])
+#define PSW (State.sregs[5])
+#define PSW_REGNO 5
+#define EIIC (State.sregs[13])
+#define FEIC (State.sregs[14])
+#define DBIC (SR[15])
+#define CTPC (SR[16])
+#define CTPSW (SR[17])
+#define DBPC (State.sregs[18])
+#define DBPSW (State.sregs[19])
+#define CTBP (State.sregs[20])
+#define DIR (SR[21])
+#define EIWR (SR[28])
+#define FEWR (SR[29])
+#define DBWR (SR[30])
+#define BSEL (SR[31])
+
+#define PSW_US BIT32 (8)
+#define PSW_NP 0x80
+#define PSW_EP 0x40
+#define PSW_ID 0x20
+#define PSW_SAT 0x10
+#define PSW_CY 0x8
+#define PSW_OV 0x4
+#define PSW_S 0x2
+#define PSW_Z 0x1
+
+#define PSW_NPV (1<<18)
+#define PSW_DMP (1<<17)
+#define PSW_IMP (1<<16)
+
+#define ECR_EICC 0x0000ffff
+#define ECR_FECC 0xffff0000
+
+/* FPU */
+
+#define FPSR (FPU_SR[6])
+#define FPSR_REGNO 6
+#define FPEPC (FPU_SR[7])
+#define FPST (FPU_SR[8])
+#define FPST_REGNO 8
+#define FPCC (FPU_SR[9])
+#define FPCFG (FPU_SR[10])
+#define FPCFG_REGNO 10
+
+#define FPSR_DEM 0x00200000
+#define FPSR_SEM 0x00100000
+#define FPSR_RM 0x000c0000
+#define FPSR_RN 0x00000000
+#define FPSR_FS 0x00020000
+#define FPSR_PR 0x00010000
+
+#define FPSR_XC 0x0000fc00
+#define FPSR_XCE 0x00008000
+#define FPSR_XCV 0x00004000
+#define FPSR_XCZ 0x00002000
+#define FPSR_XCO 0x00001000
+#define FPSR_XCU 0x00000800
+#define FPSR_XCI 0x00000400
+
+#define FPSR_XE 0x000003e0
+#define FPSR_XEV 0x00000200
+#define FPSR_XEZ 0x00000100
+#define FPSR_XEO 0x00000080
+#define FPSR_XEU 0x00000040
+#define FPSR_XEI 0x00000020
+
+#define FPSR_XP 0x0000001f
+#define FPSR_XPV 0x00000010
+#define FPSR_XPZ 0x00000008
+#define FPSR_XPO 0x00000004
+#define FPSR_XPU 0x00000002
+#define FPSR_XPI 0x00000001
+
+#define FPST_PR 0x00008000
+#define FPST_XCE 0x00002000
+#define FPST_XCV 0x00001000
+#define FPST_XCZ 0x00000800
+#define FPST_XCO 0x00000400
+#define FPST_XCU 0x00000200
+#define FPST_XCI 0x00000100
+
+#define FPST_XPV 0x00000010
+#define FPST_XPZ 0x00000008
+#define FPST_XPO 0x00000004
+#define FPST_XPU 0x00000002
+#define FPST_XPI 0x00000001
+
+#define FPCFG_RM 0x00000180
+#define FPCFG_XEV 0x00000010
+#define FPCFG_XEZ 0x00000008
+#define FPCFG_XEO 0x00000004
+#define FPCFG_XEU 0x00000002
+#define FPCFG_XEI 0x00000001
+
+#define GET_FPCC()\
+ ((FPSR >> 24) &0xf)
+
+#define CLEAR_FPCC(bbb)\
+ (FPSR &= ~(1 << (bbb+24)))
+
+#define SET_FPCC(bbb)\
+ (FPSR |= 1 << (bbb+24))
+
+#define TEST_FPCC(bbb)\
+ ((FPSR & (1 << (bbb+24))) != 0)
+
+#define FPSR_GET_ROUND() \
+ (((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near \
+ : ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up \
+ : ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down \
+ : sim_fpu_round_zero)
+
+
+enum FPU_COMPARE {
+ FPU_CMP_F = 0,
+ FPU_CMP_UN,
+ FPU_CMP_EQ,
+ FPU_CMP_UEQ,
+ FPU_CMP_OLT,
+ FPU_CMP_ULT,
+ FPU_CMP_OLE,
+ FPU_CMP_ULE,
+ FPU_CMP_SF,
+ FPU_CMP_NGLE,
+ FPU_CMP_SEQ,
+ FPU_CMP_NGL,
+ FPU_CMP_LT,
+ FPU_CMP_NGE,
+ FPU_CMP_LE,
+ FPU_CMP_NGT
+};
+
+
+/* MPU */
+#define MPM (MPU1_SR[0])
+#define MPC (MPU1_SR[1])
+#define MPC_REGNO 1
+#define TID (MPU1_SR[2])
+#define PPA (MPU1_SR[3])
+#define PPM (MPU1_SR[4])
+#define PPC (MPU1_SR[5])
+#define DCC (MPU1_SR[6])
+#define DCV0 (MPU1_SR[7])
+#define DCV1 (MPU1_SR[8])
+#define SPAL (MPU1_SR[10])
+#define SPAU (MPU1_SR[11])
+#define IPA0L (MPU1_SR[12])
+#define IPA0U (MPU1_SR[13])
+#define IPA1L (MPU1_SR[14])
+#define IPA1U (MPU1_SR[15])
+#define IPA2L (MPU1_SR[16])
+#define IPA2U (MPU1_SR[17])
+#define IPA3L (MPU1_SR[18])
+#define IPA3U (MPU1_SR[19])
+#define DPA0L (MPU1_SR[20])
+#define DPA0U (MPU1_SR[21])
+#define DPA1L (MPU1_SR[22])
+#define DPA1U (MPU1_SR[23])
+#define DPA2L (MPU1_SR[24])
+#define DPA2U (MPU1_SR[25])
+#define DPA3L (MPU1_SR[26])
+#define DPA3U (MPU1_SR[27])
+
+#define PPC_PPE 0x1
+#define SPAL_SPE 0x1
+#define SPAL_SPS 0x10
+
+#define VIP (MPU0_SR[0])
+#define VMECR (MPU0_SR[4])
+#define VMTID (MPU0_SR[5])
+#define VMADR (MPU0_SR[6])
+#define VPECR (MPU0_SR[8])
+#define VPTID (MPU0_SR[9])
+#define VPADR (MPU0_SR[10])
+#define VDECR (MPU0_SR[12])
+#define VDTID (MPU0_SR[13])
+
+#define MPM_AUE 0x2
+#define MPM_MPE 0x1
+
+#define VMECR_VMX 0x2
+#define VMECR_VMR 0x4
+#define VMECR_VMW 0x8
+#define VMECR_VMS 0x10
+#define VMECR_VMRMW 0x20
+#define VMECR_VMMS 0x40
+
+#define IPA2ADDR(IPA) ((IPA) & 0x1fffff80)
+#define IPA_IPE 0x1
+#define IPA_IPX 0x2
+#define IPA_IPR 0x4
+#define IPE0 (IPA0L & IPA_IPE)
+#define IPE1 (IPA1L & IPA_IPE)
+#define IPE2 (IPA2L & IPA_IPE)
+#define IPE3 (IPA3L & IPA_IPE)
+#define IPX0 (IPA0L & IPA_IPX)
+#define IPX1 (IPA1L & IPA_IPX)
+#define IPX2 (IPA2L & IPA_IPX)
+#define IPX3 (IPA3L & IPA_IPX)
+#define IPR0 (IPA0L & IPA_IPR)
+#define IPR1 (IPA1L & IPA_IPR)
+#define IPR2 (IPA2L & IPA_IPR)
+#define IPR3 (IPA3L & IPA_IPR)
+
+#define DPA2ADDR(DPA) ((DPA) & 0x1fffff80)
+#define DPA_DPE 0x1
+#define DPA_DPR 0x4
+#define DPA_DPW 0x8
+#define DPE0 (DPA0L & DPA_DPE)
+#define DPE1 (DPA1L & DPA_DPE)
+#define DPE2 (DPA2L & DPA_DPE)
+#define DPE3 (DPA3L & DPA_DPE)
+#define DPR0 (DPA0L & DPA_DPR)
+#define DPR1 (DPA1L & DPA_DPR)
+#define DPR2 (DPA2L & DPA_DPR)
+#define DPR3 (DPA3L & DPA_DPR)
+#define DPW0 (DPA0L & DPA_DPW)
+#define DPW1 (DPA1L & DPA_DPW)
+#define DPW2 (DPA2L & DPA_DPW)
+#define DPW3 (DPA3L & DPA_DPW)
+
+#define DCC_DCE0 0x1
+#define DCC_DCE1 0x10000
+
+#define PPA2ADDR(PPA) ((PPA) & 0x1fffff80)
+#define PPC_PPC 0xfffffffe
+#define PPC_PPE 0x1
+#define PPC_PPM 0x0000fff8
+
+
+#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
+
+/* sign-extend a 4-bit number */
+#define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
+
+/* sign-extend a 5-bit number */
+#define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
+
+/* sign-extend a 9-bit number */
+#define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
+
+/* sign-extend a 22-bit number */
+#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
+
+/* sign extend a 40 bit number */
+#define SEXT40(x) ((((x) & UNSIGNED64 (0xffffffffff)) \
+ ^ (~UNSIGNED64 (0x7fffffffff))) \
+ + UNSIGNED64 (0x8000000000))
+
+/* sign extend a 44 bit number */
+#define SEXT44(x) ((((x) & UNSIGNED64 (0xfffffffffff)) \
+ ^ (~ UNSIGNED64 (0x7ffffffffff))) \
+ + UNSIGNED64 (0x80000000000))
+
+/* sign extend a 60 bit number */
+#define SEXT60(x) ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
+ ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
+ + UNSIGNED64 (0x800000000000000))
+
+/* No sign extension */
+#define NOP(x) (x)
+
+#define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
+
+#define RLW(x) load_mem (x, 4)
+
+/* Function declarations. */
+
+#define IMEM16(EA) \
+sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
+
+#define IMEM16_IMMED(EA,N) \
+sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
+ PC, exec_map, (EA) + (N) * 2)
+
+#define load_mem(ADDR,LEN) \
+sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
+ PC, read_map, (ADDR))
+
+#define store_mem(ADDR,LEN,DATA) \
+sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
+ PC, write_map, (ADDR), (DATA))
+
+
+/* compare cccc field against PSW */
+int condition_met (unsigned code);
+
+
+/* Debug/tracing calls */
+
+enum op_types
+{
+ OP_UNKNOWN,
+ OP_NONE,
+ OP_TRAP,
+ OP_REG,
+ OP_REG_REG,
+ OP_REG_REG_CMP,
+ OP_REG_REG_MOVE,
+ OP_IMM_REG,
+ OP_IMM_REG_CMP,
+ OP_IMM_REG_MOVE,
+ OP_COND_BR,
+ OP_LOAD16,
+ OP_STORE16,
+ OP_LOAD32,
+ OP_STORE32,
+ OP_JUMP,
+ OP_IMM_REG_REG,
+ OP_UIMM_REG_REG,
+ OP_IMM16_REG_REG,
+ OP_UIMM16_REG_REG,
+ OP_BIT,
+ OP_EX1,
+ OP_EX2,
+ OP_LDSR,
+ OP_STSR,
+ OP_BIT_CHANGE,
+ OP_REG_REG_REG,
+ OP_REG_REG3,
+ OP_IMM_REG_REG_REG,
+ OP_PUSHPOP1,
+ OP_PUSHPOP2,
+ OP_PUSHPOP3,
+};
+
+#if WITH_TRACE_ANY_P
+void trace_input (char *name, enum op_types type, int size);
+void trace_output (enum op_types result);
+void trace_result (int has_result, uint32_t result);
+
+extern int trace_num_values;
+extern uint32_t trace_values[];
+extern uint32_t trace_pc;
+extern const char *trace_name;
+extern int trace_module;
+
+#define TRACE_BRANCH0() \
+do { \
+ if (TRACE_BRANCH_P (CPU)) { \
+ trace_module = TRACE_BRANCH_IDX; \
+ trace_pc = cia; \
+ trace_name = itable[MY_INDEX].name; \
+ trace_num_values = 0; \
+ trace_result (1, (nia)); \
+ } \
+} while (0)
+
+#define TRACE_BRANCH1(IN1) \
+do { \
+ if (TRACE_BRANCH_P (CPU)) { \
+ trace_module = TRACE_BRANCH_IDX; \
+ trace_pc = cia; \
+ trace_name = itable[MY_INDEX].name; \
+ trace_values[0] = (IN1); \
+ trace_num_values = 1; \
+ trace_result (1, (nia)); \
+ } \
+} while (0)
+
+#define TRACE_BRANCH2(IN1, IN2) \
+do { \
+ if (TRACE_BRANCH_P (CPU)) { \
+ trace_module = TRACE_BRANCH_IDX; \
+ trace_pc = cia; \
+ trace_name = itable[MY_INDEX].name; \
+ trace_values[0] = (IN1); \
+ trace_values[1] = (IN2); \
+ trace_num_values = 2; \
+ trace_result (1, (nia)); \
+ } \
+} while (0)
+
+#define TRACE_BRANCH3(IN1, IN2, IN3) \
+do { \
+ if (TRACE_BRANCH_P (CPU)) { \
+ trace_module = TRACE_BRANCH_IDX; \
+ trace_pc = cia; \
+ trace_name = itable[MY_INDEX].name; \
+ trace_values[0] = (IN1); \
+ trace_values[1] = (IN2); \
+ trace_values[2] = (IN3); \
+ trace_num_values = 3; \
+ trace_result (1, (nia)); \
+ } \
+} while (0)
+
+#define TRACE_LD(ADDR,RESULT) \
+do { \
+ if (TRACE_MEMORY_P (CPU)) { \
+ trace_module = TRACE_MEMORY_IDX; \
+ trace_pc = cia; \
+ trace_name = itable[MY_INDEX].name; \
+ trace_values[0] = (ADDR); \
+ trace_num_values = 1; \
+ trace_result (1, (RESULT)); \
+ } \
+} while (0)
+
+#define TRACE_LD_NAME(NAME, ADDR,RESULT) \
+do { \
+ if (TRACE_MEMORY_P (CPU)) { \
+ trace_module = TRACE_MEMORY_IDX; \
+ trace_pc = cia; \
+ trace_name = (NAME); \
+ trace_values[0] = (ADDR); \
+ trace_num_values = 1; \
+ trace_result (1, (RESULT)); \
+ } \
+} while (0)
+
+#define TRACE_ST(ADDR,RESULT) \
+do { \
+ if (TRACE_MEMORY_P (CPU)) { \
+ trace_module = TRACE_MEMORY_IDX; \
+ trace_pc = cia; \
+ trace_name = itable[MY_INDEX].name; \
+ trace_values[0] = (ADDR); \
+ trace_num_values = 1; \
+ trace_result (1, (RESULT)); \
+ } \
+} while (0)
+
+#define TRACE_FP_INPUT_FPU1(V0) \
+do { \
+ if (TRACE_FPU_P (CPU)) \
+ { \
+ uint64_t f0; \
+ sim_fpu_to64 (&f0, (V0)); \
+ trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
+ } \
+} while (0)
+
+#define TRACE_FP_INPUT_FPU2(V0, V1) \
+do { \
+ if (TRACE_FPU_P (CPU)) \
+ { \
+ uint64_t f0, f1; \
+ sim_fpu_to64 (&f0, (V0)); \
+ sim_fpu_to64 (&f1, (V1)); \
+ trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \
+ } \
+} while (0)
+
+#define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
+do { \
+ if (TRACE_FPU_P (CPU)) \
+ { \
+ uint64_t f0, f1, f2; \
+ sim_fpu_to64 (&f0, (V0)); \
+ sim_fpu_to64 (&f1, (V1)); \
+ sim_fpu_to64 (&f2, (V2)); \
+ trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \
+ } \
+} while (0)
+
+#define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
+do { \
+ if (TRACE_FPU_P (CPU)) \
+ { \
+ int d0 = (V0); \
+ uint64_t f1, f2; \
+ TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
+ TRACE_IDX (data) = TRACE_FPU_IDX; \
+ sim_fpu_to64 (&f1, (V1)); \
+ sim_fpu_to64 (&f2, (V2)); \
+ save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \
+ save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \
+ save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \
+ } \
+} while (0)
+
+#define TRACE_FP_INPUT_WORD2(V0, V1) \
+do { \
+ if (TRACE_FPU_P (CPU)) \
+ trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \
+} while (0)
+
+#define TRACE_FP_RESULT_FPU1(R0) \
+do { \
+ if (TRACE_FPU_P (CPU)) \
+ { \
+ uint64_t f0; \
+ sim_fpu_to64 (&f0, (R0)); \
+ trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
+ } \
+} while (0)
+
+#define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0)
+
+#define TRACE_FP_RESULT_WORD2(R0, R1) \
+do { \
+ if (TRACE_FPU_P (CPU)) \
+ trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \
+} while (0)
+
+#else
+#define trace_input(NAME, IN1, IN2)
+#define trace_output(RESULT)
+#define trace_result(HAS_RESULT, RESULT)
+
+#define TRACE_BRANCH0()
+#define TRACE_BRANCH1(IN1)
+#define TRACE_BRANCH2(IN1, IN2)
+#define TRACE_BRANCH3(IN1, IN2, IN3)
+
+#define TRACE_LD(ADDR,RESULT)
+#define TRACE_ST(ADDR,RESULT)
+
+#endif
+
+#define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
+#define GPR_CLEAR(N) (State.regs[(N)] = 0)
+
+extern void divun ( unsigned int N,
+ unsigned long int als,
+ unsigned long int sfi,
+ uint32_t /*unsigned long int*/ * quotient_ptr,
+ uint32_t /*unsigned long int*/ * remainder_ptr,
+ int *overflow_ptr
+ );
+extern void divn ( unsigned int N,
+ unsigned long int als,
+ unsigned long int sfi,
+ int32_t /*signed long int*/ * quotient_ptr,
+ int32_t /*signed long int*/ * remainder_ptr,
+ int *overflow_ptr
+ );
+extern int type1_regs[];
+extern int type2_regs[];
+extern int type3_regs[];
+
+#define SESR_OV (1 << 0)
+#define SESR_SOV (1 << 1)
+
+#define SESR (State.sregs[12])
+
+#define ROUND_Q62_Q31(X) ((((X) + (1 << 30)) >> 31) & 0xffffffff)
+#define ROUND_Q62_Q15(X) ((((X) + (1 << 30)) >> 47) & 0xffff)
+#define ROUND_Q31_Q15(X) ((((X) + (1 << 15)) >> 15) & 0xffff)
+#define ROUND_Q30_Q15(X) ((((X) + (1 << 14)) >> 15) & 0xffff)
+
+#define SAT16(X) \
+ do \
+ { \
+ int64_t z = (X); \
+ if (z > 0x7fff) \
+ { \
+ SESR |= SESR_OV | SESR_SOV; \
+ z = 0x7fff; \
+ } \
+ else if (z < -0x8000) \
+ { \
+ SESR |= SESR_OV | SESR_SOV; \
+ z = - 0x8000; \
+ } \
+ (X) = z; \
+ } \
+ while (0)
+
+#define SAT32(X) \
+ do \
+ { \
+ int64_t z = (X); \
+ if (z > 0x7fffffff) \
+ { \
+ SESR |= SESR_OV | SESR_SOV; \
+ z = 0x7fffffff; \
+ } \
+ else if (z < -0x80000000) \
+ { \
+ SESR |= SESR_OV | SESR_SOV; \
+ z = - 0x80000000; \
+ } \
+ (X) = z; \
+ } \
+ while (0)
+
+#define ABS16(X) \
+ do \
+ { \
+ int64_t z = (X) & 0xffff; \
+ if (z == 0x8000) \
+ { \
+ SESR |= SESR_OV | SESR_SOV; \
+ z = 0x7fff; \
+ } \
+ else if (z & 0x8000) \
+ { \
+ z = (- z) & 0xffff; \
+ } \
+ (X) = z; \
+ } \
+ while (0)
+
+#define ABS32(X) \
+ do \
+ { \
+ int64_t z = (X) & 0xffffffff; \
+ if (z == 0x80000000) \
+ { \
+ SESR |= SESR_OV | SESR_SOV; \
+ z = 0x7fffffff; \
+ } \
+ else if (z & 0x80000000) \
+ { \
+ z = (- z) & 0xffffffff; \
+ } \
+ (X) = z; \
+ } \
+ while (0)
+
+#endif
diff --git a/sim/v850/v850_sim.h b/sim/v850/v850_sim.h
deleted file mode 100644
index b1dddfdd41b9..000000000000
--- a/sim/v850/v850_sim.h
+++ /dev/null
@@ -1,8 +0,0 @@
-struct simops
-{
- unsigned long opcode;
- unsigned long mask;
- int (* func) (void);
- int numops;
- int operands[12];
-};
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 09/20] sim: riscv: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
` (7 preceding siblings ...)
2022-12-23 6:07 ` [PATCH 08/20] sim: v850: standardize the arch-specific settings a little Mike Frysinger
@ 2022-12-23 6:07 ` Mike Frysinger
2022-12-23 6:07 ` [PATCH 10/20] sim: moxie: " Mike Frysinger
` (11 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:07 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to a new header which only
this port will include.
We can also move the machs.h include out since the model logic was all
generalized from compile-time to runtime last year.
---
sim/riscv/interp.c | 2 ++
sim/riscv/machs.c | 1 +
sim/riscv/riscv-sim.h | 78 +++++++++++++++++++++++++++++++++++++++++++
sim/riscv/sim-main.c | 2 ++
sim/riscv/sim-main.h | 55 ------------------------------
5 files changed, 83 insertions(+), 55 deletions(-)
create mode 100644 sim/riscv/riscv-sim.h
diff --git a/sim/riscv/interp.c b/sim/riscv/interp.c
index 6bd0bf2a41a6..a49ad0476c45 100644
--- a/sim/riscv/interp.c
+++ b/sim/riscv/interp.c
@@ -27,6 +27,8 @@
#include "sim-main.h"
#include "sim-options.h"
#include "target-newlib-syscall.h"
+
+#include "riscv-sim.h"
\f
void
sim_engine_run (SIM_DESC sd,
diff --git a/sim/riscv/machs.c b/sim/riscv/machs.c
index ea099ed02dea..4951f480e311 100644
--- a/sim/riscv/machs.c
+++ b/sim/riscv/machs.c
@@ -22,6 +22,7 @@
#include "defs.h"
#include "sim-main.h"
+#include "machs.h"
static void
riscv_model_init (SIM_CPU *cpu)
diff --git a/sim/riscv/riscv-sim.h b/sim/riscv/riscv-sim.h
new file mode 100644
index 000000000000..2139e3758c8d
--- /dev/null
+++ b/sim/riscv/riscv-sim.h
@@ -0,0 +1,78 @@
+/* RISC-V simulator.
+
+ Copyright (C) 2005-2022 Free Software Foundation, Inc.
+ Contributed by Mike Frysinger.
+
+ This file is part of the GNU simulators.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef RISCV_MAIN_H
+#define RISCV_MAIN_H
+
+struct riscv_sim_cpu {
+ union {
+ unsigned_word regs[32];
+ struct {
+ /* These are the ABI names. */
+ unsigned_word zero, ra, sp, gp, tp;
+ unsigned_word t0, t1, t2;
+ unsigned_word s0, s1;
+ unsigned_word a0, a1, a2, a3, a4, a5, a6, a7;
+ unsigned_word s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
+ unsigned_word t3, t4, t5, t6;
+ };
+ };
+ union {
+ unsigned_word fpregs[32];
+ struct {
+ /* These are the ABI names. */
+ unsigned_word ft0, ft1, ft2, ft3, ft4, ft5, ft6, ft7;
+ unsigned_word fs0, fs1;
+ unsigned_word fa0, fa1, fa2, fa3, fa4, fa5, fa6, fa7;
+ unsigned_word fs2, fs3, fs4, fs5, fs6, fs7, fs8, fs9, fs10, fs11;
+ unsigned_word ft8, ft9, ft10, ft11;
+ };
+ };
+ sim_cia pc;
+
+ struct {
+#define DECLARE_CSR(name, ...) unsigned_word name;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+ } csr;
+};
+#define RISCV_SIM_CPU(cpu) ((struct riscv_sim_cpu *) CPU_ARCH_DATA (cpu))
+
+struct atomic_mem_reserved_list;
+struct atomic_mem_reserved_list {
+ struct atomic_mem_reserved_list *next;
+ address_word addr;
+};
+
+struct riscv_sim_state {
+ struct atomic_mem_reserved_list *amo_reserved_list;
+};
+#define RISCV_SIM_STATE(sd) ((struct riscv_sim_state *) STATE_ARCH_DATA (sd))
+
+extern void step_once (SIM_CPU *);
+extern void initialize_cpu (SIM_DESC, SIM_CPU *, int);
+extern void initialize_env (SIM_DESC, const char * const *argv,
+ const char * const *env);
+
+#define DEFAULT_MEM_SIZE (64 * 1024 * 1024)
+
+#define RISCV_XLEN(cpu) MACH_WORD_BITSIZE (CPU_MACH (cpu))
+
+#endif
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 4e7358b113a5..95950ee5977b 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -34,6 +34,8 @@
#include "opcode/riscv.h"
#include "sim/sim-riscv.h"
+
+#include "riscv-sim.h"
\f
#define TRACE_REG(cpu, reg) \
TRACE_REGISTER (cpu, "wrote %s = %#" PRIxTW, riscv_gpr_names_abi[reg], \
diff --git a/sim/riscv/sim-main.h b/sim/riscv/sim-main.h
index 48ea452fb0b1..a6de53cdccdb 100644
--- a/sim/riscv/sim-main.h
+++ b/sim/riscv/sim-main.h
@@ -22,61 +22,6 @@
#define SIM_MAIN_H
#include "sim-basics.h"
-#include "machs.h"
#include "sim-base.h"
-struct riscv_sim_cpu {
- union {
- unsigned_word regs[32];
- struct {
- /* These are the ABI names. */
- unsigned_word zero, ra, sp, gp, tp;
- unsigned_word t0, t1, t2;
- unsigned_word s0, s1;
- unsigned_word a0, a1, a2, a3, a4, a5, a6, a7;
- unsigned_word s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
- unsigned_word t3, t4, t5, t6;
- };
- };
- union {
- unsigned_word fpregs[32];
- struct {
- /* These are the ABI names. */
- unsigned_word ft0, ft1, ft2, ft3, ft4, ft5, ft6, ft7;
- unsigned_word fs0, fs1;
- unsigned_word fa0, fa1, fa2, fa3, fa4, fa5, fa6, fa7;
- unsigned_word fs2, fs3, fs4, fs5, fs6, fs7, fs8, fs9, fs10, fs11;
- unsigned_word ft8, ft9, ft10, ft11;
- };
- };
- sim_cia pc;
-
- struct {
-#define DECLARE_CSR(name, ...) unsigned_word name;
-#include "opcode/riscv-opc.h"
-#undef DECLARE_CSR
- } csr;
-};
-#define RISCV_SIM_CPU(cpu) ((struct riscv_sim_cpu *) CPU_ARCH_DATA (cpu))
-
-struct atomic_mem_reserved_list;
-struct atomic_mem_reserved_list {
- struct atomic_mem_reserved_list *next;
- address_word addr;
-};
-
-struct riscv_sim_state {
- struct atomic_mem_reserved_list *amo_reserved_list;
-};
-#define RISCV_SIM_STATE(sd) ((struct riscv_sim_state *) STATE_ARCH_DATA (sd))
-
-extern void step_once (SIM_CPU *);
-extern void initialize_cpu (SIM_DESC, SIM_CPU *, int);
-extern void initialize_env (SIM_DESC, const char * const *argv,
- const char * const *env);
-
-#define DEFAULT_MEM_SIZE (64 * 1024 * 1024)
-
-#define RISCV_XLEN(cpu) MACH_WORD_BITSIZE (CPU_MACH (cpu))
-
#endif
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 10/20] sim: moxie: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
` (8 preceding siblings ...)
2022-12-23 6:07 ` [PATCH 09/20] sim: riscv: move arch-specific settings to internal header Mike Frysinger
@ 2022-12-23 6:07 ` Mike Frysinger
2022-12-23 6:07 ` [PATCH 11/20] sim: example-synacor: " Mike Frysinger
` (10 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:07 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to a new header which only
this port will include.
---
sim/moxie/interp.c | 2 ++
sim/moxie/moxie-sim.h | 34 ++++++++++++++++++++++++++++++++++
sim/moxie/sim-main.h | 11 -----------
3 files changed, 36 insertions(+), 11 deletions(-)
create mode 100644 sim/moxie/moxie-sim.h
diff --git a/sim/moxie/interp.c b/sim/moxie/interp.c
index 74a6fda433bd..144d83cbe8e7 100644
--- a/sim/moxie/interp.c
+++ b/sim/moxie/interp.c
@@ -37,6 +37,8 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "sim-signal.h"
#include "target-newlib-syscall.h"
+#include "moxie-sim.h"
+
/* Extract the signed 10-bit offset from a 16-bit branch
instruction. */
#define INST2OFFSET(o) ((((signed short)((o & ((1<<10)-1))<<6))>>6)<<1)
diff --git a/sim/moxie/moxie-sim.h b/sim/moxie/moxie-sim.h
new file mode 100644
index 000000000000..761ac3220ec3
--- /dev/null
+++ b/sim/moxie/moxie-sim.h
@@ -0,0 +1,34 @@
+/* Moxie Simulator definition.
+ Copyright (C) 2009-2022 Free Software Foundation, Inc.
+ Contributed by Anthony Green <green@moxielogic.com>
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef MOXIE_SIM_H
+#define MOXIE_SIM_H
+
+#define PCIDX 17
+
+struct moxie_sim_cpu {
+ /* To keep this default simulator simple, and fast, we use a direct
+ vector of registers. The internal simulator engine then uses
+ manifests to access the correct slot. */
+ unsigned_word registers[19];
+};
+
+#define MOXIE_SIM_CPU(cpu) ((struct moxie_sim_cpu *) CPU_ARCH_DATA (cpu))
+
+#endif
diff --git a/sim/moxie/sim-main.h b/sim/moxie/sim-main.h
index d0df1e927cd1..ad0b2b66949a 100644
--- a/sim/moxie/sim-main.h
+++ b/sim/moxie/sim-main.h
@@ -23,15 +23,4 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "sim-basics.h"
#include "sim-base.h"
-#define PCIDX 17
-
-struct moxie_sim_cpu {
- /* To keep this default simulator simple, and fast, we use a direct
- vector of registers. The internal simulator engine then uses
- manifests to access the correct slot. */
- unsigned_word registers[19];
-};
-
-#define MOXIE_SIM_CPU(cpu) ((struct moxie_sim_cpu *) CPU_ARCH_DATA (cpu))
-
#endif
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 11/20] sim: example-synacor: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
` (9 preceding siblings ...)
2022-12-23 6:07 ` [PATCH 10/20] sim: moxie: " Mike Frysinger
@ 2022-12-23 6:07 ` Mike Frysinger
2022-12-23 6:07 ` [PATCH 12/20] sim: microblaze: " Mike Frysinger
` (9 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:07 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to a new header which only
this port will include.
---
sim/example-synacor/example-synacor-sim.h | 38 +++++++++++++++++++++++
sim/example-synacor/interp.c | 2 ++
sim/example-synacor/sim-main.c | 2 ++
sim/example-synacor/sim-main.h | 14 ---------
4 files changed, 42 insertions(+), 14 deletions(-)
create mode 100644 sim/example-synacor/example-synacor-sim.h
diff --git a/sim/example-synacor/example-synacor-sim.h b/sim/example-synacor/example-synacor-sim.h
new file mode 100644
index 000000000000..55701a7f0d57
--- /dev/null
+++ b/sim/example-synacor/example-synacor-sim.h
@@ -0,0 +1,38 @@
+/* Example synacor simulator.
+
+ Copyright (C) 2005-2022 Free Software Foundation, Inc.
+ Contributed by Mike Frysinger.
+
+ This file is part of the GNU simulators.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef EXAMPLE_SYNACOR_SIM_H
+#define EXAMPLE_SYNACOR_SIM_H
+
+struct example_sim_cpu {
+ uint16_t regs[8];
+ sim_cia pc;
+
+ /* This isn't a real register, and the stack is not directly addressable,
+ so use memory outside of the 16-bit address space. */
+ uint32_t sp;
+};
+
+#define EXAMPLE_SIM_CPU(cpu) ((struct example_sim_cpu *) CPU_ARCH_DATA (cpu))
+
+extern void step_once (SIM_CPU *);
+extern void initialize_cpu (SIM_DESC, SIM_CPU *);
+
+#endif
diff --git a/sim/example-synacor/interp.c b/sim/example-synacor/interp.c
index cbde166c9b32..20ae057d43a1 100644
--- a/sim/example-synacor/interp.c
+++ b/sim/example-synacor/interp.c
@@ -31,6 +31,8 @@
#include "sim/callback.h"
#include "sim-main.h"
#include "sim-options.h"
+
+#include "example-synacor-sim.h"
\f
/* This function is the main loop. It should process ticks and decode+execute
a single instruction.
diff --git a/sim/example-synacor/sim-main.c b/sim/example-synacor/sim-main.c
index 0757d6925c8f..2971c7ffd227 100644
--- a/sim/example-synacor/sim-main.c
+++ b/sim/example-synacor/sim-main.c
@@ -26,6 +26,8 @@
#include "sim-main.h"
#include "sim-signal.h"
+
+#include "example-synacor-sim.h"
\f
/* Get the register number from the number. */
static uint16_t
diff --git a/sim/example-synacor/sim-main.h b/sim/example-synacor/sim-main.h
index 258d61879cc9..ffd695ea226a 100644
--- a/sim/example-synacor/sim-main.h
+++ b/sim/example-synacor/sim-main.h
@@ -24,18 +24,4 @@
#include "sim-basics.h"
#include "sim-base.h"
-struct example_sim_cpu {
- uint16_t regs[8];
- sim_cia pc;
-
- /* This isn't a real register, and the stack is not directly addressable,
- so use memory outside of the 16-bit address space. */
- uint32_t sp;
-};
-
-#define EXAMPLE_SIM_CPU(cpu) ((struct example_sim_cpu *) CPU_ARCH_DATA (cpu))
-
-extern void step_once (SIM_CPU *);
-extern void initialize_cpu (SIM_DESC, SIM_CPU *);
-
#endif
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 12/20] sim: microblaze: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
` (10 preceding siblings ...)
2022-12-23 6:07 ` [PATCH 11/20] sim: example-synacor: " Mike Frysinger
@ 2022-12-23 6:07 ` Mike Frysinger
2022-12-23 6:07 ` [PATCH 13/20] sim: mn10300: standardize the arch-specific settings a little Mike Frysinger
` (8 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:07 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to a new header which only
this port will include.
---
sim/microblaze/interp.c | 1 +
sim/microblaze/microblaze-sim.h | 46 +++++++++++++++++++++++++++++++++
sim/microblaze/sim-main.h | 24 -----------------
3 files changed, 47 insertions(+), 24 deletions(-)
create mode 100644 sim/microblaze/microblaze-sim.h
diff --git a/sim/microblaze/interp.c b/sim/microblaze/interp.c
index 3d7fde0af3e3..8a8cb9f2b832 100644
--- a/sim/microblaze/interp.c
+++ b/sim/microblaze/interp.c
@@ -33,6 +33,7 @@
#include "sim-signal.h"
#include "sim-syscall.h"
+#include "microblaze-sim.h"
#include "microblaze-dis.h"
#define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
diff --git a/sim/microblaze/microblaze-sim.h b/sim/microblaze/microblaze-sim.h
new file mode 100644
index 000000000000..9e5fb0711c58
--- /dev/null
+++ b/sim/microblaze/microblaze-sim.h
@@ -0,0 +1,46 @@
+/* Copyright 2009-2022 Free Software Foundation, Inc.
+
+ This file is part of the Xilinx MicroBlaze simulator.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef MICROBLAZE_SIM_H
+#define MICROBLAZE_SIM_H
+
+#include "microblaze.h"
+
+/* The machine state.
+ This state is maintained in host byte order. The
+ fetch/store register functions must translate between host
+ byte order and the target processor byte order.
+ Keeping this data in target byte order simplifies the register
+ read/write functions. Keeping this data in native order improves
+ the performance of the simulator. Simulation speed is deemed more
+ important. */
+
+/* The ordering of the microblaze_regset structure is matched in the
+ gdb/config/microblaze/tm-microblaze.h file in the REGISTER_NAMES macro. */
+ struct microblaze_regset
+{
+ signed_4 regs[32]; /* primary registers */
+ signed_4 spregs[2]; /* pc + msr */
+ int cycles;
+ int insts;
+ unsigned_1 imm_enable;
+ signed_2 imm_high;
+};
+
+#define MICROBLAZE_SIM_CPU(cpu) ((struct microblaze_regset *) CPU_ARCH_DATA (cpu))
+
+#endif /* MICROBLAZE_SIM_H */
diff --git a/sim/microblaze/sim-main.h b/sim/microblaze/sim-main.h
index 160f10156fff..7646dad044fe 100644
--- a/sim/microblaze/sim-main.h
+++ b/sim/microblaze/sim-main.h
@@ -18,31 +18,7 @@
#ifndef MICROBLAZE_SIM_MAIN
#define MICROBLAZE_SIM_MAIN
-#include "microblaze.h"
#include "sim-basics.h"
#include "sim-base.h"
-/* The machine state.
- This state is maintained in host byte order. The
- fetch/store register functions must translate between host
- byte order and the target processor byte order.
- Keeping this data in target byte order simplifies the register
- read/write functions. Keeping this data in native order improves
- the performance of the simulator. Simulation speed is deemed more
- important. */
-
-/* The ordering of the microblaze_regset structure is matched in the
- gdb/config/microblaze/tm-microblaze.h file in the REGISTER_NAMES macro. */
- struct microblaze_regset
-{
- signed_4 regs[32]; /* primary registers */
- signed_4 spregs[2]; /* pc + msr */
- int cycles;
- int insts;
- unsigned_1 imm_enable;
- signed_2 imm_high;
-};
-
-#define MICROBLAZE_SIM_CPU(cpu) ((struct microblaze_regset *) CPU_ARCH_DATA (cpu))
-
#endif /* MICROBLAZE_SIM_MAIN */
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 13/20] sim: mn10300: standardize the arch-specific settings a little
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
` (11 preceding siblings ...)
2022-12-23 6:07 ` [PATCH 12/20] sim: microblaze: " Mike Frysinger
@ 2022-12-23 6:07 ` Mike Frysinger
2022-12-23 6:07 ` [PATCH 14/20] sim: pru: move arch-specific settings to internal header Mike Frysinger
` (7 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:07 UTC (permalink / raw)
To: gdb-patches
Rename mn10300_sim.h to mn10300-sim.h to match other ports, and move most
of the arch-specific content out of sim-main.h to it. This isn't a big
win though as we still have to include the header in sim-main.h due to the
igen interface: it hardcodes including sim-main.h in its files. So until
we can fix that, we have to keep bleeding these settings into the common
codes.
Also take the opportunity to purge a lot of unused headers from these.
The local modules should already include the right headers, so there's
no need to force everyone to pull them in. A lot of this is a hold over
from the pre-igen days of this port.
---
sim/mn10300/interp.c | 2 --
sim/mn10300/{mn10300_sim.h => mn10300-sim.h} | 24 ++++++++------
sim/mn10300/op_utils.c | 10 +++---
sim/mn10300/sim-main.h | 34 ++++----------------
4 files changed, 27 insertions(+), 43 deletions(-)
rename sim/mn10300/{mn10300_sim.h => mn10300-sim.h} (94%)
diff --git a/sim/mn10300/interp.c b/sim/mn10300/interp.c
index 3ea8079b1fa7..8467070addb6 100644
--- a/sim/mn10300/interp.c
+++ b/sim/mn10300/interp.c
@@ -14,8 +14,6 @@
#include <stdlib.h>
#include <string.h>
-#include "bfd.h"
-
struct _state State;
diff --git a/sim/mn10300/mn10300_sim.h b/sim/mn10300/mn10300-sim.h
similarity index 94%
rename from sim/mn10300/mn10300_sim.h
rename to sim/mn10300/mn10300-sim.h
index f1ab23ffe4fb..f6e4d854a144 100644
--- a/sim/mn10300/mn10300_sim.h
+++ b/sim/mn10300/mn10300-sim.h
@@ -1,14 +1,8 @@
-#include <stdio.h>
-#include <ctype.h>
-#include "ansidecl.h"
-#include "sim/callback.h"
-#include "opcode/mn10300.h"
-#include <limits.h>
-#include "sim/sim.h"
-#include "bfd.h"
-#include "sim-fpu.h"
-#include "sim-signal.h"
+#ifndef MN10300_SIM_H
+#define MN10300_SIM_H
+/* For compatibility, until all functions converted to passing
+ SIM_DESC as an argument */
extern SIM_DESC simulator;
typedef struct
@@ -185,6 +179,14 @@ dw2u64 (dword data)
return data.low | (((uint64_t)data.high) << 32);
}
+/* Bring data in from the cold */
+
+#define IMEM8(EA) \
+(sim_core_read_aligned_1(STATE_CPU(sd, 0), EA, exec_map, (EA)))
+
+#define IMEM8_IMMED(EA, N) \
+(sim_core_read_aligned_1(STATE_CPU(sd, 0), EA, exec_map, (EA) + (N)))
+
/* Function declarations. */
INLINE_SIM_MAIN (void) genericAdd (uint32_t source, uint32_t destReg);
@@ -225,3 +227,5 @@ void fpu_fmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *,
void fpu_fmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
void fpu_fnmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
void fpu_fnmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
+
+#endif
diff --git a/sim/mn10300/op_utils.c b/sim/mn10300/op_utils.c
index 2fccf2da207f..b29b803d8e7f 100644
--- a/sim/mn10300/op_utils.c
+++ b/sim/mn10300/op_utils.c
@@ -1,10 +1,7 @@
/* This must come before any other includes. */
#include "defs.h"
-#include "sim-main.h"
-#include "sim-signal.h"
-#include "sim-syscall.h"
-
+#include <errno.h>
#include <time.h>
#ifdef HAVE_UNISTD_H
#include <unistd.h>
@@ -13,6 +10,11 @@
#include <sys/stat.h>
#include <sys/time.h>
+#include "sim/callback.h"
+
+#include "sim-main.h"
+#include "sim-signal.h"
+#include "sim-syscall.h"
#define REG0(X) ((X) & 0x3)
diff --git a/sim/mn10300/sim-main.h b/sim/mn10300/sim-main.h
index 77a7ba8ea0d4..09887b592379 100644
--- a/sim/mn10300/sim-main.h
+++ b/sim/mn10300/sim-main.h
@@ -26,40 +26,20 @@
#include "sim-basics.h"
-#include <signal.h> /* For kill() in insns:do_trap */
-
-#include <errno.h>
-#ifdef HAVE_UNISTD_H
-#include <unistd.h>
-#endif
-
-/* These are generated files. */
-#include "itable.h"
-#include "idecode.h"
-
#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
mn10300_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
-
#include "sim-base.h"
-#include "mn10300_sim.h"
-
-/* Bring data in from the cold */
-
-#define IMEM8(EA) \
-(sim_core_read_aligned_1(STATE_CPU(sd, 0), EA, exec_map, (EA)))
-
-#define IMEM8_IMMED(EA, N) \
-(sim_core_read_aligned_1(STATE_CPU(sd, 0), EA, exec_map, (EA) + (N)))
-
-/* For compatibility, until all functions converted to passing
- SIM_DESC as an argument */
-extern SIM_DESC simulator;
+/**
+ * TODO: Move these includes to the igen files that need them.
+ * This requires extending the igen syntax to support header includes.
+ */
+#include "sim-fpu.h"
+#include "sim-signal.h"
-/* (re) initialize the simulator */
+#include "mn10300-sim.h"
-extern void engine_init(SIM_DESC sd);
extern SIM_CORE_SIGNAL_FN mn10300_core_signal;
#endif
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 14/20] sim: pru: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
` (12 preceding siblings ...)
2022-12-23 6:07 ` [PATCH 13/20] sim: mn10300: standardize the arch-specific settings a little Mike Frysinger
@ 2022-12-23 6:07 ` Mike Frysinger
2022-12-23 6:07 ` [PATCH 15/20] sim: h8300: " Mike Frysinger
` (6 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:07 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so drop the pru.h include and move the remaining
pru-specific settings into it.
---
sim/pru/pru.h | 56 ++++++++++++++++++++++++++++++++++++++++++++
sim/pru/sim-main.h | 58 ----------------------------------------------
2 files changed, 56 insertions(+), 58 deletions(-)
diff --git a/sim/pru/pru.h b/sim/pru/pru.h
index f6b633b29bd0..375a988ddc1f 100644
--- a/sim/pru/pru.h
+++ b/sim/pru/pru.h
@@ -19,6 +19,8 @@
#ifndef PRU_H
#define PRU_H
+#include <stdint.h>
+
#include "opcode/pru.h"
/* Needed for handling the dual PRU address space. */
@@ -108,4 +110,58 @@
/* 32 GP registers plus PC. */
#define NUM_REGS 33
+/* The machine state.
+ This state is maintained in host byte order. The
+ fetch/store register functions must translate between host
+ byte order and the target processor byte order.
+ Keeping this data in target byte order simplifies the register
+ read/write functions. Keeping this data in host order improves
+ the performance of the simulator. Simulation speed is deemed more
+ important. */
+
+/* For clarity, please keep the same relative order in this enum as in the
+ corresponding group of GP registers.
+
+ In PRU ISA, Multiplier-Accumulator-Unit's registers are like "shadows" of
+ the GP registers. MAC registers are implicitly addressed when executing
+ the XIN/XOUT instructions to access them. Transfer to/from a MAC register
+ can happen only from/to its corresponding GP peer register. */
+
+enum pru_macreg_id {
+ /* MAC register CPU GP register Description. */
+ PRU_MACREG_MODE, /* r25 */ /* Mode (MUL/MAC). */
+ PRU_MACREG_PROD_L, /* r26 */ /* Lower 32 bits of product. */
+ PRU_MACREG_PROD_H, /* r27 */ /* Higher 32 bits of product. */
+ PRU_MACREG_OP_0, /* r28 */ /* First operand. */
+ PRU_MACREG_OP_1, /* r29 */ /* Second operand. */
+ PRU_MACREG_ACC_L, /* N/A */ /* Accumulator (not exposed) */
+ PRU_MACREG_ACC_H, /* N/A */ /* Higher 32 bits of MAC
+ accumulator. */
+ PRU_MAC_NREGS
+};
+
+struct pru_regset
+{
+ uint32_t regs[32]; /* Primary registers. */
+ uint16_t pc; /* IMEM _word_ address. */
+ uint32_t pc_addr_space_marker; /* IMEM virtual linker offset. This
+ is the artificial offset that
+ we invent in order to "separate"
+ the DMEM and IMEM memory spaces. */
+ unsigned int carry : 1;
+ uint32_t ctable[32]; /* Constant offsets table for xBCO. */
+ uint32_t macregs[PRU_MAC_NREGS];
+ uint32_t scratchpads[XFRID_MAX + 1][32];
+ struct {
+ uint16_t looptop; /* LOOP top (PC of loop instr). */
+ uint16_t loopend; /* LOOP end (PC of loop end label). */
+ int loop_in_progress; /* Whether to check for PC==loopend. */
+ uint32_t loop_counter; /* LOOP counter. */
+ } loop;
+ int cycles;
+ int insts;
+};
+
+#define PRU_SIM_CPU(cpu) ((struct pru_regset *) CPU_ARCH_DATA (cpu))
+
#endif /* PRU_H */
diff --git a/sim/pru/sim-main.h b/sim/pru/sim-main.h
index ada1e3886278..0925c3a120d9 100644
--- a/sim/pru/sim-main.h
+++ b/sim/pru/sim-main.h
@@ -19,65 +19,7 @@
#ifndef PRU_SIM_MAIN
#define PRU_SIM_MAIN
-#include <stdint.h>
-#include <stddef.h>
-#include "pru.h"
#include "sim-basics.h"
-
#include "sim-base.h"
-/* The machine state.
- This state is maintained in host byte order. The
- fetch/store register functions must translate between host
- byte order and the target processor byte order.
- Keeping this data in target byte order simplifies the register
- read/write functions. Keeping this data in host order improves
- the performance of the simulator. Simulation speed is deemed more
- important. */
-
-/* For clarity, please keep the same relative order in this enum as in the
- corresponding group of GP registers.
-
- In PRU ISA, Multiplier-Accumulator-Unit's registers are like "shadows" of
- the GP registers. MAC registers are implicitly addressed when executing
- the XIN/XOUT instructions to access them. Transfer to/from a MAC register
- can happen only from/to its corresponding GP peer register. */
-
-enum pru_macreg_id {
- /* MAC register CPU GP register Description. */
- PRU_MACREG_MODE, /* r25 */ /* Mode (MUL/MAC). */
- PRU_MACREG_PROD_L, /* r26 */ /* Lower 32 bits of product. */
- PRU_MACREG_PROD_H, /* r27 */ /* Higher 32 bits of product. */
- PRU_MACREG_OP_0, /* r28 */ /* First operand. */
- PRU_MACREG_OP_1, /* r29 */ /* Second operand. */
- PRU_MACREG_ACC_L, /* N/A */ /* Accumulator (not exposed) */
- PRU_MACREG_ACC_H, /* N/A */ /* Higher 32 bits of MAC
- accumulator. */
- PRU_MAC_NREGS
-};
-
-struct pru_regset
-{
- uint32_t regs[32]; /* Primary registers. */
- uint16_t pc; /* IMEM _word_ address. */
- uint32_t pc_addr_space_marker; /* IMEM virtual linker offset. This
- is the artificial offset that
- we invent in order to "separate"
- the DMEM and IMEM memory spaces. */
- unsigned int carry : 1;
- uint32_t ctable[32]; /* Constant offsets table for xBCO. */
- uint32_t macregs[PRU_MAC_NREGS];
- uint32_t scratchpads[XFRID_MAX + 1][32];
- struct {
- uint16_t looptop; /* LOOP top (PC of loop instr). */
- uint16_t loopend; /* LOOP end (PC of loop end label). */
- int loop_in_progress; /* Whether to check for PC==loopend. */
- uint32_t loop_counter; /* LOOP counter. */
- } loop;
- int cycles;
- int insts;
-};
-
-#define PRU_SIM_CPU(cpu) ((struct pru_regset *) CPU_ARCH_DATA (cpu))
-
#endif /* PRU_SIM_MAIN */
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 15/20] sim: h8300: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
` (13 preceding siblings ...)
2022-12-23 6:07 ` [PATCH 14/20] sim: pru: move arch-specific settings to internal header Mike Frysinger
@ 2022-12-23 6:07 ` Mike Frysinger
2022-12-23 6:07 ` [PATCH 16/20] sim: mcore: " Mike Frysinger
` (5 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:07 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to a new header which only
this port will include.
---
sim/h8300/compile.c | 2 +
sim/h8300/h8300-sim.h | 153 ++++++++++++++++++++++++++++++++++++++++++
sim/h8300/sim-main.h | 147 ----------------------------------------
3 files changed, 155 insertions(+), 147 deletions(-)
create mode 100644 sim/h8300/h8300-sim.h
diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c
index 077bc6dff097..cc8b52c5d654 100644
--- a/sim/h8300/compile.c
+++ b/sim/h8300/compile.c
@@ -36,6 +36,8 @@
#include "sim-signal.h"
#include "sim/callback.h"
+#include "h8300-sim.h"
+
#ifndef SIGTRAP
# define SIGTRAP 5
#endif
diff --git a/sim/h8300/h8300-sim.h b/sim/h8300/h8300-sim.h
new file mode 100644
index 000000000000..a6bea633d242
--- /dev/null
+++ b/sim/h8300/h8300-sim.h
@@ -0,0 +1,153 @@
+/* Main header for the Hitachi h8/300 architecture. */
+
+#ifndef H8300_SIM_H
+#define H8300_SIM_H
+
+#define DEBUG
+
+/* These define the size of main memory for the simulator.
+
+ Note the size of main memory for the H8/300H is only 256k. Keeping it
+ small makes the simulator run much faster and consume less memory.
+
+ The linker knows about the limited size of the simulator's main memory
+ on the H8/300H (via the h8300h.sc linker script). So if you change
+ H8300H_MSIZE, be sure to fix the linker script too.
+
+ Also note that there's a separate "eightbit" area aside from main
+ memory. For simplicity, the simulator assumes any data memory reference
+ outside of main memory refers to the eightbit area (in theory, this
+ can only happen when simulating H8/300H programs). We make no attempt
+ to catch overlapping addresses, wrapped addresses, etc etc. */
+
+#define H8300_MSIZE (1 << 16)
+
+/* avolkov:
+ Next 2 macros are ugly for any workstation, but while they're work.
+ Memory size MUST be configurable. */
+#define H8300H_MSIZE (1 << 24)
+#define H8300S_MSIZE (1 << 24)
+
+#define CSIZE 1024
+
+enum h8_regnum {
+ R0_REGNUM = 0,
+ R1_REGNUM = 1,
+ R2_REGNUM = 2,
+ R3_REGNUM = 3,
+ R4_REGNUM = 4,
+ R5_REGNUM = 5,
+ R6_REGNUM = 6,
+ R7_REGNUM = 7,
+
+ SP_REGNUM = R7_REGNUM, /* Contains address of top of stack */
+ FP_REGNUM = R6_REGNUM, /* Contains address of executing
+ stack frame */
+ CCR_REGNUM = 8, /* Contains processor status */
+ PC_REGNUM = 9, /* Contains program counter */
+ CYCLE_REGNUM = 10,
+ EXR_REGNUM = 11,
+ INST_REGNUM = 12,
+ TICK_REGNUM = 13,
+ MACH_REGNUM = 14,
+ MACL_REGNUM = 15,
+ SBR_REGNUM = 16,
+ VBR_REGNUM = 17,
+
+ ZERO_REGNUM = 18
+};
+
+enum h8_typecodes {
+ OP_NULL,
+ OP_REG, /* Register direct. */
+ OP_LOWREG, /* Special reg syntax for "bra". */
+ OP_DISP, /* Register indirect w/displacement. */
+ /* Note: h8300, h8300h, and h8300s permit only pre-decr and post-incr. */
+ OP_PREDEC, /* Register indirect w/pre-decrement. */
+ OP_POSTDEC, /* Register indirect w/post-decrement. */
+ OP_PREINC, /* Register indirect w/pre-increment. */
+ OP_POSTINC, /* Register indirect w/post-increment. */
+ OP_PCREL, /* PC Relative. */
+ OP_MEM, /* Absolute memory address. */
+ OP_CCR, /* Condition Code Register. */
+ OP_IMM, /* Immediate value. */
+ /*OP_ABS*/ /* Un-used (duplicates op_mem?). */
+ OP_EXR, /* EXtended control Register. */
+ OP_SBR, /* Vector Base Register. */
+ OP_VBR, /* Short-address Base Register. */
+ OP_MACH, /* Multiply Accumulator - high. */
+ OP_MACL, /* Multiply Accumulator - low. */
+ /* FIXME: memory indirect? */
+ OP_INDEXB, /* Byte index mode */
+ OP_INDEXW, /* Word index mode */
+ OP_INDEXL, /* Long index mode */
+ OP_REG_DEC, /* Register direct. affect address decrement. */
+ OP_REG_INC, /* Register direct. affect address increment. */
+};
+
+/* Structure used to describe addressing */
+
+typedef struct
+{
+ int type;
+ int reg;
+ int literal;
+} ea_type;
+
+/* Struct for instruction decoder. */
+typedef struct
+{
+ ea_type src;
+ ea_type dst;
+ ea_type op3;
+ int opcode;
+ int next_pc;
+ int oldpc;
+ int cycles;
+#ifdef DEBUG
+ struct h8_opcode *op;
+#endif
+} decoded_inst;
+
+struct h8300_sim_cpu {
+ unsigned int regs[20]; /* 8 GR's plus ZERO, SBR, and VBR. */
+ unsigned int pc;
+
+ int macS; /* MAC Saturating mode */
+ int macV; /* MAC Overflow */
+ int macN; /* MAC Negative */
+ int macZ; /* MAC Zero */
+
+ int delayed_branch;
+ char **command_line; /* Pointer to command line arguments. */
+
+ unsigned char *memory;
+ int mask;
+};
+#define H8300_SIM_CPU(sd) ((struct h8300_sim_cpu *) CPU_ARCH_DATA (sd))
+
+struct h8300_sim_state {
+ unsigned long memory_size;
+#ifdef ADEBUG
+ int stats[O_LAST];
+#endif
+};
+#define H8300_SIM_STATE(sd) ((struct h8300_sim_state *) STATE_ARCH_DATA (sd))
+
+/* The current state of the processor; registers, memory, etc. */
+
+#define cpu_set_pc(cpu, val) (H8300_SIM_CPU (cpu)->pc = (val))
+#define cpu_get_pc(cpu) (H8300_SIM_CPU (cpu)->pc)
+
+/* Magic numbers used to distinguish an exit from a breakpoint. */
+#define LIBC_EXIT_MAGIC1 0xdead
+#define LIBC_EXIT_MAGIC2 0xbeef
+/* Local version of macros for decoding exit status.
+ (included here rather than try to find target version of wait.h)
+*/
+#define SIM_WIFEXITED(V) (((V) & 0xff) == 0)
+#define SIM_WIFSTOPPED(V) (!SIM_WIFEXITED (V))
+#define SIM_WEXITSTATUS(V) (((V) >> 8) & 0xff)
+#define SIM_WSTOPSIG(V) ((V) & 0x7f)
+
+#endif /* H8300_SIM_H */
diff --git a/sim/h8300/sim-main.h b/sim/h8300/sim-main.h
index c034699e5c55..003e19ce512f 100644
--- a/sim/h8300/sim-main.h
+++ b/sim/h8300/sim-main.h
@@ -3,154 +3,7 @@
#ifndef SIM_MAIN_H
#define SIM_MAIN_H
-#define DEBUG
-
-/* These define the size of main memory for the simulator.
-
- Note the size of main memory for the H8/300H is only 256k. Keeping it
- small makes the simulator run much faster and consume less memory.
-
- The linker knows about the limited size of the simulator's main memory
- on the H8/300H (via the h8300h.sc linker script). So if you change
- H8300H_MSIZE, be sure to fix the linker script too.
-
- Also note that there's a separate "eightbit" area aside from main
- memory. For simplicity, the simulator assumes any data memory reference
- outside of main memory refers to the eightbit area (in theory, this
- can only happen when simulating H8/300H programs). We make no attempt
- to catch overlapping addresses, wrapped addresses, etc etc. */
-
-#define H8300_MSIZE (1 << 16)
-
-/* avolkov:
- Next 2 macros are ugly for any workstation, but while they're work.
- Memory size MUST be configurable. */
-#define H8300H_MSIZE (1 << 24)
-#define H8300S_MSIZE (1 << 24)
-
-#define CSIZE 1024
-
-enum h8_regnum {
- R0_REGNUM = 0,
- R1_REGNUM = 1,
- R2_REGNUM = 2,
- R3_REGNUM = 3,
- R4_REGNUM = 4,
- R5_REGNUM = 5,
- R6_REGNUM = 6,
- R7_REGNUM = 7,
-
- SP_REGNUM = R7_REGNUM, /* Contains address of top of stack */
- FP_REGNUM = R6_REGNUM, /* Contains address of executing
- stack frame */
- CCR_REGNUM = 8, /* Contains processor status */
- PC_REGNUM = 9, /* Contains program counter */
- CYCLE_REGNUM = 10,
- EXR_REGNUM = 11,
- INST_REGNUM = 12,
- TICK_REGNUM = 13,
- MACH_REGNUM = 14,
- MACL_REGNUM = 15,
- SBR_REGNUM = 16,
- VBR_REGNUM = 17,
-
- ZERO_REGNUM = 18
-};
-
-enum h8_typecodes {
- OP_NULL,
- OP_REG, /* Register direct. */
- OP_LOWREG, /* Special reg syntax for "bra". */
- OP_DISP, /* Register indirect w/displacement. */
- /* Note: h8300, h8300h, and h8300s permit only pre-decr and post-incr. */
- OP_PREDEC, /* Register indirect w/pre-decrement. */
- OP_POSTDEC, /* Register indirect w/post-decrement. */
- OP_PREINC, /* Register indirect w/pre-increment. */
- OP_POSTINC, /* Register indirect w/post-increment. */
- OP_PCREL, /* PC Relative. */
- OP_MEM, /* Absolute memory address. */
- OP_CCR, /* Condition Code Register. */
- OP_IMM, /* Immediate value. */
- /*OP_ABS*/ /* Un-used (duplicates op_mem?). */
- OP_EXR, /* EXtended control Register. */
- OP_SBR, /* Vector Base Register. */
- OP_VBR, /* Short-address Base Register. */
- OP_MACH, /* Multiply Accumulator - high. */
- OP_MACL, /* Multiply Accumulator - low. */
- /* FIXME: memory indirect? */
- OP_INDEXB, /* Byte index mode */
- OP_INDEXW, /* Word index mode */
- OP_INDEXL, /* Long index mode */
- OP_REG_DEC, /* Register direct. affect address decrement. */
- OP_REG_INC, /* Register direct. affect address increment. */
-};
-
#include "sim-basics.h"
#include "sim-base.h"
-/* Structure used to describe addressing */
-
-typedef struct
-{
- int type;
- int reg;
- int literal;
-} ea_type;
-
-/* Struct for instruction decoder. */
-typedef struct
-{
- ea_type src;
- ea_type dst;
- ea_type op3;
- int opcode;
- int next_pc;
- int oldpc;
- int cycles;
-#ifdef DEBUG
- struct h8_opcode *op;
-#endif
-} decoded_inst;
-
-struct h8300_sim_cpu {
- unsigned int regs[20]; /* 8 GR's plus ZERO, SBR, and VBR. */
- unsigned int pc;
-
- int macS; /* MAC Saturating mode */
- int macV; /* MAC Overflow */
- int macN; /* MAC Negative */
- int macZ; /* MAC Zero */
-
- int delayed_branch;
- char **command_line; /* Pointer to command line arguments. */
-
- unsigned char *memory;
- int mask;
-};
-#define H8300_SIM_CPU(sd) ((struct h8300_sim_cpu *) CPU_ARCH_DATA (sd))
-
-struct h8300_sim_state {
- unsigned long memory_size;
-#ifdef ADEBUG
- int stats[O_LAST];
-#endif
-};
-#define H8300_SIM_STATE(sd) ((struct h8300_sim_state *) STATE_ARCH_DATA (sd))
-
-/* The current state of the processor; registers, memory, etc. */
-
-#define cpu_set_pc(cpu, val) (H8300_SIM_CPU (cpu)->pc = (val))
-#define cpu_get_pc(cpu) (H8300_SIM_CPU (cpu)->pc)
-
-/* Magic numbers used to distinguish an exit from a breakpoint. */
-#define LIBC_EXIT_MAGIC1 0xdead
-#define LIBC_EXIT_MAGIC2 0xbeef
-/* Local version of macros for decoding exit status.
- (included here rather than try to find target version of wait.h)
-*/
-#define SIM_WIFEXITED(V) (((V) & 0xff) == 0)
-#define SIM_WIFSTOPPED(V) (!SIM_WIFEXITED (V))
-#define SIM_WEXITSTATUS(V) (((V) >> 8) & 0xff)
-#define SIM_WSTOPSIG(V) ((V) & 0x7f)
-
#endif /* SIM_MAIN_H */
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 16/20] sim: mcore: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
` (14 preceding siblings ...)
2022-12-23 6:07 ` [PATCH 15/20] sim: h8300: " Mike Frysinger
@ 2022-12-23 6:07 ` Mike Frysinger
2022-12-23 6:07 ` [PATCH 17/20] sim: sh: " Mike Frysinger
` (4 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:07 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to a new header which only
this port will include.
---
sim/mcore/interp.c | 2 ++
sim/mcore/mcore-sim.h | 64 +++++++++++++++++++++++++++++++++++++++++++
sim/mcore/sim-main.h | 40 ---------------------------
3 files changed, 66 insertions(+), 40 deletions(-)
create mode 100644 sim/mcore/mcore-sim.h
diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c
index 8465f56d2d7c..84b243f07059 100644
--- a/sim/mcore/interp.c
+++ b/sim/mcore/interp.c
@@ -38,6 +38,8 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "target-newlib-syscall.h"
+#include "mcore-sim.h"
+
#define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
diff --git a/sim/mcore/mcore-sim.h b/sim/mcore/mcore-sim.h
new file mode 100644
index 000000000000..239a079ebb3a
--- /dev/null
+++ b/sim/mcore/mcore-sim.h
@@ -0,0 +1,64 @@
+/* Simulator for Motorola's MCore processor
+ Copyright (C) 2009-2022 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef MCORE_SIM_H
+#define MCORE_SIM_H
+
+#include <stdint.h>
+
+/* The machine state.
+ This state is maintained in host byte order. The
+ fetch/store register functions must translate between host
+ byte order and the target processor byte order.
+ Keeping this data in target byte order simplifies the register
+ read/write functions. Keeping this data in native order improves
+ the performance of the simulator. Simulation speed is deemed more
+ important. */
+
+/* The ordering of the mcore_regset structure is matched in the
+ gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro. */
+struct mcore_regset
+{
+ int32_t gregs[16]; /* primary registers */
+ int32_t alt_gregs[16]; /* alt register file */
+ int32_t cregs[32]; /* control registers */
+ int32_t pc;
+};
+#define LAST_VALID_CREG 32 /* only 0..12 implemented */
+#define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1)
+
+struct mcore_sim_cpu {
+ union
+ {
+ struct mcore_regset regs;
+ /* Used by the fetch/store reg helpers to access registers linearly. */
+ int32_t asints[NUM_MCORE_REGS];
+ };
+
+ /* Used to switch between gregs/alt_gregs based on the control state. */
+ int32_t *active_gregs;
+
+ int ticks;
+ int stalls;
+ int cycles;
+ int insts;
+};
+
+#define MCORE_SIM_CPU(cpu) ((struct mcore_sim_cpu *) CPU_ARCH_DATA (cpu))
+
+#endif
diff --git a/sim/mcore/sim-main.h b/sim/mcore/sim-main.h
index 684ec39354be..fc48834feb45 100644
--- a/sim/mcore/sim-main.h
+++ b/sim/mcore/sim-main.h
@@ -22,45 +22,5 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "sim-basics.h"
#include "sim-base.h"
-/* The machine state.
- This state is maintained in host byte order. The
- fetch/store register functions must translate between host
- byte order and the target processor byte order.
- Keeping this data in target byte order simplifies the register
- read/write functions. Keeping this data in native order improves
- the performance of the simulator. Simulation speed is deemed more
- important. */
-
-/* The ordering of the mcore_regset structure is matched in the
- gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro. */
-struct mcore_regset
-{
- int32_t gregs[16]; /* primary registers */
- int32_t alt_gregs[16]; /* alt register file */
- int32_t cregs[32]; /* control registers */
- int32_t pc;
-};
-#define LAST_VALID_CREG 32 /* only 0..12 implemented */
-#define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1)
-
-struct mcore_sim_cpu {
- union
- {
- struct mcore_regset regs;
- /* Used by the fetch/store reg helpers to access registers linearly. */
- int32_t asints[NUM_MCORE_REGS];
- };
-
- /* Used to switch between gregs/alt_gregs based on the control state. */
- int32_t *active_gregs;
-
- int ticks;
- int stalls;
- int cycles;
- int insts;
-};
-
-#define MCORE_SIM_CPU(cpu) ((struct mcore_sim_cpu *) CPU_ARCH_DATA (cpu))
-
#endif
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 17/20] sim: sh: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
` (15 preceding siblings ...)
2022-12-23 6:07 ` [PATCH 16/20] sim: mcore: " Mike Frysinger
@ 2022-12-23 6:07 ` Mike Frysinger
2022-12-23 6:07 ` [PATCH 18/20] sim: m68hc11: " Mike Frysinger
` (3 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:07 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to a new header which only
this port will include.
---
sim/sh/interp.c | 2 +
sim/sh/sh-sim.h | 118 ++++++++++++++++++++++++++++++++++++++++++++++
sim/sh/sim-main.h | 96 -------------------------------------
3 files changed, 120 insertions(+), 96 deletions(-)
create mode 100644 sim/sh/sh-sim.h
diff --git a/sim/sh/interp.c b/sim/sh/interp.c
index 7784ca7aa40f..b2d30e386c1a 100644
--- a/sim/sh/interp.c
+++ b/sim/sh/interp.c
@@ -63,6 +63,8 @@
#include "target-newlib-syscall.h"
+#include "sh-sim.h"
+
#include <math.h>
#ifdef _WIN32
diff --git a/sim/sh/sh-sim.h b/sim/sh/sh-sim.h
new file mode 100644
index 000000000000..7f315b780af0
--- /dev/null
+++ b/sim/sh/sh-sim.h
@@ -0,0 +1,118 @@
+/* Moxie Simulator definition.
+ Copyright (C) 2009-2022 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef SH_SIM_H
+#define SH_SIM_H
+
+typedef struct
+{
+ int regs[20];
+} regstacktype;
+
+typedef union
+{
+
+ struct
+ {
+ int regs[16];
+ int pc;
+
+ /* System registers. For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1
+ which are located in fregs. Probably should include pc too - to avoid
+ alignment repercussions. */
+ union {
+ struct {
+ int mach;
+ int macl;
+ int pr;
+ int dummy3, dummy4;
+ int fpul; /* A1 for sh-dsp - but only for movs etc. */
+ int fpscr; /* dsr for sh-dsp */
+
+ /* sh3e / sh-dsp */
+ union fregs_u {
+ float f[16];
+ double d[8];
+ int i[16];
+ } fregs[2];
+ };
+ int sregs[39];
+ };
+
+ /* Control registers; on the SH4, ldc / stc is privileged, except when
+ accessing gbr. */
+ union
+ {
+ struct
+ {
+ int sr;
+ int gbr;
+ int vbr;
+ int ssr;
+ int spc;
+ int mod;
+ /* sh-dsp */
+ int rs;
+ int re;
+ /* sh3 */
+ int bank[8];
+ int dbr; /* debug base register */
+ int sgr; /* saved gr15 */
+ int ldst; /* load/store flag (boolean) */
+ int tbr;
+ int ibcr; /* sh2a bank control register */
+ int ibnr; /* sh2a bank number register */
+ };
+ int cregs[16];
+ };
+
+ unsigned char *insn_end;
+
+ int ticks;
+ int stalls;
+ int memstalls;
+ int cycles;
+ int insts;
+
+ int prevlock;
+ int thislock;
+ int exception;
+
+ int end_of_registers;
+
+ int msize;
+#define PROFILE_FREQ 1
+#define PROFILE_SHIFT 2
+ int profile;
+ unsigned short *profile_hist;
+ unsigned char *memory;
+ int xyram_select, xram_start, yram_start;
+ unsigned char *xmem;
+ unsigned char *ymem;
+ unsigned char *xmem_offset;
+ unsigned char *ymem_offset;
+ unsigned long bfd_mach;
+ regstacktype *regstack;
+ } asregs;
+ int asints[40];
+} saved_state_type;
+
+/* TODO: Move into sim_cpu. */
+extern saved_state_type saved_state;
+
+#endif
diff --git a/sim/sh/sim-main.h b/sim/sh/sim-main.h
index 6008b6997129..0c005370c091 100644
--- a/sim/sh/sim-main.h
+++ b/sim/sh/sim-main.h
@@ -22,100 +22,4 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "sim-basics.h"
#include "sim-base.h"
-typedef struct
-{
- int regs[20];
-} regstacktype;
-
-typedef union
-{
-
- struct
- {
- int regs[16];
- int pc;
-
- /* System registers. For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1
- which are located in fregs. Probably should include pc too - to avoid
- alignment repercussions. */
- union {
- struct {
- int mach;
- int macl;
- int pr;
- int dummy3, dummy4;
- int fpul; /* A1 for sh-dsp - but only for movs etc. */
- int fpscr; /* dsr for sh-dsp */
-
- /* sh3e / sh-dsp */
- union fregs_u {
- float f[16];
- double d[8];
- int i[16];
- } fregs[2];
- };
- int sregs[39];
- };
-
- /* Control registers; on the SH4, ldc / stc is privileged, except when
- accessing gbr. */
- union
- {
- struct
- {
- int sr;
- int gbr;
- int vbr;
- int ssr;
- int spc;
- int mod;
- /* sh-dsp */
- int rs;
- int re;
- /* sh3 */
- int bank[8];
- int dbr; /* debug base register */
- int sgr; /* saved gr15 */
- int ldst; /* load/store flag (boolean) */
- int tbr;
- int ibcr; /* sh2a bank control register */
- int ibnr; /* sh2a bank number register */
- };
- int cregs[16];
- };
-
- unsigned char *insn_end;
-
- int ticks;
- int stalls;
- int memstalls;
- int cycles;
- int insts;
-
- int prevlock;
- int thislock;
- int exception;
-
- int end_of_registers;
-
- int msize;
-#define PROFILE_FREQ 1
-#define PROFILE_SHIFT 2
- int profile;
- unsigned short *profile_hist;
- unsigned char *memory;
- int xyram_select, xram_start, yram_start;
- unsigned char *xmem;
- unsigned char *ymem;
- unsigned char *xmem_offset;
- unsigned char *ymem_offset;
- unsigned long bfd_mach;
- regstacktype *regstack;
- } asregs;
- int asints[40];
-} saved_state_type;
-
-/* TODO: Move into sim_cpu. */
-extern saved_state_type saved_state;
-
#endif
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 18/20] sim: m68hc11: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
` (16 preceding siblings ...)
2022-12-23 6:07 ` [PATCH 17/20] sim: sh: " Mike Frysinger
@ 2022-12-23 6:07 ` Mike Frysinger
2022-12-23 6:07 ` [PATCH 19/20] sim: bfin: " Mike Frysinger
` (2 subsequent siblings)
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:07 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to a new header which only
this port will include.
---
sim/m68hc11/dv-m68hc11.c | 2 +
sim/m68hc11/dv-m68hc11eepr.c | 2 +-
sim/m68hc11/dv-m68hc11sio.c | 1 +
sim/m68hc11/dv-m68hc11spi.c | 1 +
sim/m68hc11/dv-m68hc11tim.c | 2 +
sim/m68hc11/dv-nvram.c | 1 +
sim/m68hc11/emulos.c | 2 +
sim/m68hc11/gencode.c | 2 +-
sim/m68hc11/interp.c | 2 +
sim/m68hc11/interrupts.c | 2 +
sim/m68hc11/m68hc11-sim.h | 565 +++++++++++++++++++++++++++++++++++
sim/m68hc11/m68hc11_sim.c | 4 +-
sim/m68hc11/sim-main.h | 541 ---------------------------------
13 files changed, 583 insertions(+), 544 deletions(-)
create mode 100644 sim/m68hc11/m68hc11-sim.h
diff --git a/sim/m68hc11/dv-m68hc11.c b/sim/m68hc11/dv-m68hc11.c
index 1a39c9fa51d4..c8e1e5a0b2b2 100644
--- a/sim/m68hc11/dv-m68hc11.c
+++ b/sim/m68hc11/dv-m68hc11.c
@@ -29,6 +29,8 @@
#include <limits.h>
#include <stdlib.h>
+#include "m68hc11-sim.h"
+
/* DEVICE
m68hc11cpu - m68hc11 cpu virtual device
diff --git a/sim/m68hc11/dv-m68hc11eepr.c b/sim/m68hc11/dv-m68hc11eepr.c
index 5e6c4e187551..17da98770bb7 100644
--- a/sim/m68hc11/dv-m68hc11eepr.c
+++ b/sim/m68hc11/dv-m68hc11eepr.c
@@ -31,7 +31,7 @@
#include <fcntl.h>
#include <errno.h>
-
+#include "m68hc11-sim.h"
/* DEVICE
diff --git a/sim/m68hc11/dv-m68hc11sio.c b/sim/m68hc11/dv-m68hc11sio.c
index f61d284184a8..e063de93e980 100644
--- a/sim/m68hc11/dv-m68hc11sio.c
+++ b/sim/m68hc11/dv-m68hc11sio.c
@@ -28,6 +28,7 @@
#include "dv-sockser.h"
#include "sim-assert.h"
+#include "m68hc11-sim.h"
/* DEVICE
diff --git a/sim/m68hc11/dv-m68hc11spi.c b/sim/m68hc11/dv-m68hc11spi.c
index f9d482bff413..fcb4886c2db9 100644
--- a/sim/m68hc11/dv-m68hc11spi.c
+++ b/sim/m68hc11/dv-m68hc11spi.c
@@ -28,6 +28,7 @@
#include "dv-sockser.h"
#include "sim-assert.h"
+#include "m68hc11-sim.h"
/* DEVICE
diff --git a/sim/m68hc11/dv-m68hc11tim.c b/sim/m68hc11/dv-m68hc11tim.c
index 15080c579623..ff7028d59318 100644
--- a/sim/m68hc11/dv-m68hc11tim.c
+++ b/sim/m68hc11/dv-m68hc11tim.c
@@ -28,6 +28,8 @@
#include "sim-assert.h"
#include <limits.h>
+#include "m68hc11-sim.h"
+
/* DEVICE
m68hc11tim - m68hc11 timer devices
diff --git a/sim/m68hc11/dv-nvram.c b/sim/m68hc11/dv-nvram.c
index f02160833047..d184bb453c47 100644
--- a/sim/m68hc11/dv-nvram.c
+++ b/sim/m68hc11/dv-nvram.c
@@ -29,6 +29,7 @@
#include <fcntl.h>
#include <errno.h>
+#include "m68hc11-sim.h"
/* DEVICE
diff --git a/sim/m68hc11/emulos.c b/sim/m68hc11/emulos.c
index 7ee72cb9040c..f4582f66274c 100644
--- a/sim/m68hc11/emulos.c
+++ b/sim/m68hc11/emulos.c
@@ -25,6 +25,8 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include <unistd.h>
#endif
+#include "m68hc11-sim.h"
+
#ifndef WIN32
#include <errno.h>
#include <stdio.h>
diff --git a/sim/m68hc11/gencode.c b/sim/m68hc11/gencode.c
index fcc4b05b6ac5..cde336d94706 100644
--- a/sim/m68hc11/gencode.c
+++ b/sim/m68hc11/gencode.c
@@ -2048,7 +2048,7 @@ gen_interpreter (FILE *fp)
/* Generate header of interpretor. */
print (fp, col, "/* File generated automatically by gencode. */\n");
- print (fp, col, "#include \"sim-main.h\"\n\n");
+ print (fp, col, "#include \"m68hc11-sim.h\"\n\n");
if (cpu_type & cpu6811)
{
diff --git a/sim/m68hc11/interp.c b/sim/m68hc11/interp.c
index 89c6449dfe1a..b80f5cb82bb0 100644
--- a/sim/m68hc11/interp.c
+++ b/sim/m68hc11/interp.c
@@ -31,6 +31,8 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "hw-ports.h"
#include "elf32-m68hc1x.h"
+#include "m68hc11-sim.h"
+
#ifndef MONITOR_BASE
# define MONITOR_BASE (0x0C000)
# define MONITOR_SIZE (0x04000)
diff --git a/sim/m68hc11/interrupts.c b/sim/m68hc11/interrupts.c
index 5b3d48faa9b4..a9443b5d749d 100644
--- a/sim/m68hc11/interrupts.c
+++ b/sim/m68hc11/interrupts.c
@@ -26,6 +26,8 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "sim-options.h"
#include "sim-signal.h"
+#include "m68hc11-sim.h"
+
static const char *interrupt_names[] = {
"R1",
"R2",
diff --git a/sim/m68hc11/m68hc11-sim.h b/sim/m68hc11/m68hc11-sim.h
new file mode 100644
index 000000000000..36a96c70c616
--- /dev/null
+++ b/sim/m68hc11/m68hc11-sim.h
@@ -0,0 +1,565 @@
+/* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
+ Copyright (C) 1999-2022 Free Software Foundation, Inc.
+ Written by Stephane Carrez (stcarrez@nerim.fr)
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef M68HC11_SIM_H
+#define M68HC11_SIM_H
+
+#include "sim-basics.h"
+#include "sim-base.h"
+
+#include "opcode/m68hc11.h"
+
+#include "sim/sim.h"
+#include "opcode/m68hc11.h"
+#include "sim-signal.h"
+#include "sim-types.h"
+
+#include "interrupts.h"
+#include <setjmp.h>
+
+/* Specifies the level of mapping for the IO, EEprom, nvram and external
+ RAM. IO registers are mapped over everything and the external RAM
+ is last (ie, it can be hidden by everything above it in the list). */
+enum m68hc11_map_level
+{
+ M6811_IO_LEVEL,
+ M6811_EEPROM_LEVEL,
+ M6811_NVRAM_LEVEL,
+ M6811_RAM_LEVEL
+};
+
+enum cpu_type
+{
+ CPU_M6811,
+ CPU_M6812
+};
+
+#define X_REGNUM 0
+#define D_REGNUM 1
+#define Y_REGNUM 2
+#define SP_REGNUM 3
+#define PC_REGNUM 4
+#define A_REGNUM 5
+#define B_REGNUM 6
+#define PSW_REGNUM 7
+#define PAGE_REGNUM 8
+#define Z_REGNUM 9
+
+typedef struct m6811_regs {
+ unsigned short d;
+ unsigned short ix;
+ unsigned short iy;
+ unsigned short sp;
+ unsigned short pc;
+ unsigned char ccr;
+ unsigned short page;
+} m6811_regs;
+
+
+/* Description of 68HC11 IO registers. Such description is only provided
+ for the info command to display the current setting of IO registers
+ from GDB. */
+struct io_reg_desc
+{
+ int mask;
+ const char *short_name;
+ const char *long_name;
+};
+typedef struct io_reg_desc io_reg_desc;
+
+extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
+ int mode);
+extern void print_io_byte (SIM_DESC sd, const char *name,
+ io_reg_desc *desc, uint8_t val, uint16_t addr);
+extern void print_io_word (SIM_DESC sd, const char *name,
+ io_reg_desc *desc, uint16_t val, uint16_t addr);
+
+
+/* List of special 68HC11&68HC12 instructions that are not handled by the
+ 'gencode.c' generator. These complex instructions are implemented
+ by 'cpu_special'. */
+enum M6811_Special
+{
+ /* 68HC11 instructions. */
+ M6811_DAA,
+ M6811_EMUL_SYSCALL,
+ M6811_ILLEGAL,
+ M6811_RTI,
+ M6811_STOP,
+ M6811_SWI,
+ M6811_TEST,
+ M6811_WAI,
+
+ /* 68HC12 instructions. */
+ M6812_BGND,
+ M6812_CALL,
+ M6812_CALL_INDIRECT,
+ M6812_IDIVS,
+ M6812_EDIV,
+ M6812_EDIVS,
+ M6812_EMACS,
+ M6812_EMUL,
+ M6812_EMULS,
+ M6812_ETBL,
+ M6812_MEM,
+ M6812_REV,
+ M6812_REVW,
+ M6812_RTC,
+ M6812_RTI,
+ M6812_WAV
+};
+
+#define M6811_MAX_PORTS (0x03f+1)
+#define M6812_MAX_PORTS (0x3ff+1)
+#define MAX_PORTS (M6812_MAX_PORTS)
+
+typedef void (* cpu_interp) (sim_cpu *);
+
+struct m68hc11_sim_cpu {
+ /* CPU registers. */
+ struct m6811_regs cpu_regs;
+
+ /* CPU interrupts. */
+ struct interrupts cpu_interrupts;
+
+ /* Pointer to the interpretor routine. */
+ cpu_interp cpu_interpretor;
+
+ /* Pointer to the architecture currently configured in the simulator. */
+ const struct bfd_arch_info *cpu_configured_arch;
+
+ /* CPU absolute cycle time. The cycle time is updated after
+ each instruction, by the number of cycles taken by the instruction.
+ It is cleared only when reset occurs. */
+ int64_t cpu_absolute_cycle;
+
+ /* Number of cycles to increment after the current instruction.
+ This is also the number of ticks for the generic event scheduler. */
+ uint8_t cpu_current_cycle;
+ int cpu_emul_syscall;
+ int cpu_is_initialized;
+ int cpu_running;
+ int cpu_check_memory;
+ int cpu_stop_on_interrupt;
+
+ /* When this is set, start execution of program at address specified
+ in the ELF header. This is used for testing some programs that do not
+ have an interrupt table linked with them. Programs created during the
+ GCC validation are like this. A normal 68HC11 does not behave like
+ this (unless there is some OS or downloadable feature). */
+ int cpu_use_elf_start;
+
+ /* The starting address specified in ELF header. */
+ int cpu_elf_start;
+
+ uint16_t cpu_insn_pc;
+
+ /* CPU frequency. This is the quartz frequency. It is divided by 4 to
+ get the cycle time. This is used for the timer rate and for the baud
+ rate generation. */
+ unsigned long cpu_frequency;
+
+ /* The mode in which the CPU is configured (MODA and MODB pins). */
+ unsigned int cpu_mode;
+ const char* cpu_start_mode;
+
+ /* The cpu being configured. */
+ enum cpu_type cpu_type;
+
+ /* Initial value of the CONFIG register. */
+ uint8_t cpu_config;
+ uint8_t cpu_use_local_config;
+
+ uint8_t ios[MAX_PORTS];
+
+ /* Memory bank parameters which describe how the memory bank window
+ is mapped in memory and how to convert it in virtual address. */
+ uint16_t bank_start;
+ uint16_t bank_end;
+ address_word bank_virtual;
+ unsigned bank_shift;
+
+
+ struct hw *hw_cpu;
+};
+#define M68HC11_SIM_CPU(cpu) ((struct m68hc11_sim_cpu *) CPU_ARCH_DATA (cpu))
+
+/* Returns the cpu absolute cycle time (A virtual counter incremented
+ at each 68HC11 E clock). */
+#define cpu_current_cycle(cpu) (M68HC11_SIM_CPU (cpu)->cpu_absolute_cycle)
+#define cpu_add_cycles(cpu, T) (M68HC11_SIM_CPU (cpu)->cpu_current_cycle += (int64_t) (T))
+#define cpu_is_running(cpu) (M68HC11_SIM_CPU (cpu)->cpu_running)
+
+/* Get the IO/RAM base addresses depending on the M6811_INIT register. */
+#define cpu_get_io_base(cpu) \
+ (((uint16_t)((M68HC11_SIM_CPU (cpu)->ios[M6811_INIT]) & 0x0F)) << 12)
+#define cpu_get_reg_base(cpu) \
+ (((uint16_t)((M68HC11_SIM_CPU (cpu)->ios[M6811_INIT]) & 0xF0)) << 8)
+
+/* Returns the different CPU registers. */
+#define cpu_get_ccr(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.ccr)
+#define cpu_get_pc(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.pc)
+#define cpu_get_d(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.d)
+#define cpu_get_x(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.ix)
+#define cpu_get_y(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.iy)
+#define cpu_get_sp(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.sp)
+#define cpu_get_a(cpu) ((M68HC11_SIM_CPU (cpu)->cpu_regs.d >> 8) & 0x0FF)
+#define cpu_get_b(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.d & 0x0FF)
+#define cpu_get_page(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.page)
+
+/* 68HC12 specific and Motorola internal registers. */
+#define cpu_get_tmp3(cpu) (0)
+#define cpu_get_tmp2(cpu) (0)
+
+#define cpu_set_d(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.d = (val))
+#define cpu_set_x(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.ix = (val))
+#define cpu_set_y(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.iy = (val))
+#define cpu_set_page(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.page = (val))
+
+/* 68HC12 specific and Motorola internal registers. */
+#define cpu_set_tmp3(cpu, val) (0)
+#define cpu_set_tmp2(cpu, val) (void) (0)
+
+#if 0
+/* This is a function in m68hc11_sim.c to keep track of the frame. */
+#define cpu_set_sp(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.sp = (val))
+#endif
+
+#define cpu_set_pc(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.pc = (val))
+
+#define cpu_set_a(cpu, val) \
+ cpu_set_d(cpu, ((val) << 8) | cpu_get_b (cpu))
+#define cpu_set_b(cpu, val) \
+ cpu_set_d(cpu, ((cpu_get_a (cpu)) << 8) | ((val) & 0x0FF))
+
+#define cpu_set_ccr(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.ccr = (val))
+#define cpu_get_ccr_H(cpu) ((cpu_get_ccr (cpu) & M6811_H_BIT) ? 1 : 0)
+#define cpu_get_ccr_X(cpu) ((cpu_get_ccr (cpu) & M6811_X_BIT) ? 1 : 0)
+#define cpu_get_ccr_S(cpu) ((cpu_get_ccr (cpu) & M6811_S_BIT) ? 1 : 0)
+#define cpu_get_ccr_N(cpu) ((cpu_get_ccr (cpu) & M6811_N_BIT) ? 1 : 0)
+#define cpu_get_ccr_V(cpu) ((cpu_get_ccr (cpu) & M6811_V_BIT) ? 1 : 0)
+#define cpu_get_ccr_C(cpu) ((cpu_get_ccr (cpu) & M6811_C_BIT) ? 1 : 0)
+#define cpu_get_ccr_Z(cpu) ((cpu_get_ccr (cpu) & M6811_Z_BIT) ? 1 : 0)
+#define cpu_get_ccr_I(cpu) ((cpu_get_ccr (cpu) & M6811_I_BIT) ? 1 : 0)
+
+#define cpu_set_ccr_flag(S, B, V) \
+ cpu_set_ccr (S, (cpu_get_ccr (S) & ~(B)) | ((V) ? (B) : 0))
+
+#define cpu_set_ccr_H(cpu, val) cpu_set_ccr_flag (cpu, M6811_H_BIT, val)
+#define cpu_set_ccr_X(cpu, val) cpu_set_ccr_flag (cpu, M6811_X_BIT, val)
+#define cpu_set_ccr_S(cpu, val) cpu_set_ccr_flag (cpu, M6811_S_BIT, val)
+#define cpu_set_ccr_N(cpu, val) cpu_set_ccr_flag (cpu, M6811_N_BIT, val)
+#define cpu_set_ccr_V(cpu, val) cpu_set_ccr_flag (cpu, M6811_V_BIT, val)
+#define cpu_set_ccr_C(cpu, val) cpu_set_ccr_flag (cpu, M6811_C_BIT, val)
+#define cpu_set_ccr_Z(cpu, val) cpu_set_ccr_flag (cpu, M6811_Z_BIT, val)
+#define cpu_set_ccr_I(cpu, val) cpu_set_ccr_flag (cpu, M6811_I_BIT, val)
+
+extern void cpu_memory_exception (sim_cpu *cpu,
+ SIM_SIGNAL excep,
+ uint16_t addr,
+ const char *message);
+
+STATIC_INLINE UNUSED address_word
+phys_to_virt (sim_cpu *cpu, address_word addr)
+{
+ struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
+
+ if (addr >= m68hc11_cpu->bank_start && addr < m68hc11_cpu->bank_end)
+ return ((address_word) (addr - m68hc11_cpu->bank_start)
+ + (((address_word) m68hc11_cpu->cpu_regs.page) << m68hc11_cpu->bank_shift)
+ + m68hc11_cpu->bank_virtual);
+ else
+ return (address_word) (addr);
+}
+
+STATIC_INLINE UNUSED uint8_t
+memory_read8 (sim_cpu *cpu, uint16_t addr)
+{
+ uint8_t val;
+
+ if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
+ {
+ cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
+ "Read error");
+ }
+ return val;
+}
+
+STATIC_INLINE UNUSED void
+memory_write8 (sim_cpu *cpu, uint16_t addr, uint8_t val)
+{
+ if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
+ {
+ cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
+ "Write error");
+ }
+}
+
+STATIC_INLINE UNUSED uint16_t
+memory_read16 (sim_cpu *cpu, uint16_t addr)
+{
+ uint8_t b[2];
+
+ if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
+ {
+ cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
+ "Read error");
+ }
+ return (((uint16_t) (b[0])) << 8) | ((uint16_t) b[1]);
+}
+
+STATIC_INLINE UNUSED void
+memory_write16 (sim_cpu *cpu, uint16_t addr, uint16_t val)
+{
+ uint8_t b[2];
+
+ b[0] = val >> 8;
+ b[1] = val;
+ if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
+ {
+ cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
+ "Write error");
+ }
+}
+extern void
+cpu_ccr_update_tst8 (sim_cpu *cpu, uint8_t val);
+
+STATIC_INLINE UNUSED void
+cpu_ccr_update_tst16 (sim_cpu *cpu, uint16_t val)
+{
+ cpu_set_ccr_V (cpu, 0);
+ cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
+ cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
+}
+
+STATIC_INLINE UNUSED void
+cpu_ccr_update_shift8 (sim_cpu *cpu, uint8_t val)
+{
+ cpu_set_ccr_N (cpu, val & 0x80 ? 1 : 0);
+ cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
+ cpu_set_ccr_V (cpu, cpu_get_ccr_N (cpu) ^ cpu_get_ccr_C (cpu));
+}
+
+STATIC_INLINE UNUSED void
+cpu_ccr_update_shift16 (sim_cpu *cpu, uint16_t val)
+{
+ cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
+ cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
+ cpu_set_ccr_V (cpu, cpu_get_ccr_N (cpu) ^ cpu_get_ccr_C (cpu));
+}
+
+STATIC_INLINE UNUSED void
+cpu_ccr_update_add8 (sim_cpu *cpu, uint8_t r, uint8_t a, uint8_t b)
+{
+ cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
+ cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
+ cpu_set_ccr_Z (cpu, r == 0);
+ cpu_set_ccr_N (cpu, r & 0x80 ? 1 : 0);
+}
+
+
+STATIC_INLINE UNUSED void
+cpu_ccr_update_sub8 (sim_cpu *cpu, uint8_t r, uint8_t a, uint8_t b)
+{
+ cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
+ cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
+ cpu_set_ccr_Z (cpu, r == 0);
+ cpu_set_ccr_N (cpu, r & 0x80 ? 1 : 0);
+}
+
+STATIC_INLINE UNUSED void
+cpu_ccr_update_add16 (sim_cpu *cpu, uint16_t r, uint16_t a, uint16_t b)
+{
+ cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
+ cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
+ cpu_set_ccr_Z (cpu, r == 0);
+ cpu_set_ccr_N (cpu, r & 0x8000 ? 1 : 0);
+}
+
+STATIC_INLINE UNUSED void
+cpu_ccr_update_sub16 (sim_cpu *cpu, uint16_t r, uint16_t a, uint16_t b)
+{
+ cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
+ cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
+ cpu_set_ccr_Z (cpu, r == 0);
+ cpu_set_ccr_N (cpu, r & 0x8000 ? 1 : 0);
+}
+
+/* Push and pop instructions for 68HC11 (next-available stack mode). */
+STATIC_INLINE UNUSED void
+cpu_m68hc11_push_uint8 (sim_cpu *cpu, uint8_t val)
+{
+ struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
+ uint16_t addr = m68hc11_cpu->cpu_regs.sp;
+
+ memory_write8 (cpu, addr, val);
+ m68hc11_cpu->cpu_regs.sp = addr - 1;
+}
+
+STATIC_INLINE UNUSED void
+cpu_m68hc11_push_uint16 (sim_cpu *cpu, uint16_t val)
+{
+ struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
+ uint16_t addr = m68hc11_cpu->cpu_regs.sp - 1;
+
+ memory_write16 (cpu, addr, val);
+ m68hc11_cpu->cpu_regs.sp = addr - 1;
+}
+
+STATIC_INLINE UNUSED uint8_t
+cpu_m68hc11_pop_uint8 (sim_cpu *cpu)
+{
+ struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
+ uint16_t addr = m68hc11_cpu->cpu_regs.sp;
+ uint8_t val;
+
+ val = memory_read8 (cpu, addr + 1);
+ m68hc11_cpu->cpu_regs.sp = addr + 1;
+ return val;
+}
+
+STATIC_INLINE UNUSED uint16_t
+cpu_m68hc11_pop_uint16 (sim_cpu *cpu)
+{
+ struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
+ uint16_t addr = m68hc11_cpu->cpu_regs.sp;
+ uint16_t val;
+
+ val = memory_read16 (cpu, addr + 1);
+ m68hc11_cpu->cpu_regs.sp = addr + 2;
+ return val;
+}
+
+/* Push and pop instructions for 68HC12 (last-used stack mode). */
+STATIC_INLINE UNUSED void
+cpu_m68hc12_push_uint8 (sim_cpu *cpu, uint8_t val)
+{
+ struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
+ uint16_t addr = m68hc11_cpu->cpu_regs.sp;
+
+ addr --;
+ memory_write8 (cpu, addr, val);
+ m68hc11_cpu->cpu_regs.sp = addr;
+}
+
+STATIC_INLINE UNUSED void
+cpu_m68hc12_push_uint16 (sim_cpu *cpu, uint16_t val)
+{
+ struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
+ uint16_t addr = m68hc11_cpu->cpu_regs.sp;
+
+ addr -= 2;
+ memory_write16 (cpu, addr, val);
+ m68hc11_cpu->cpu_regs.sp = addr;
+}
+
+STATIC_INLINE UNUSED uint8_t
+cpu_m68hc12_pop_uint8 (sim_cpu *cpu)
+{
+ struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
+ uint16_t addr = m68hc11_cpu->cpu_regs.sp;
+ uint8_t val;
+
+ val = memory_read8 (cpu, addr);
+ m68hc11_cpu->cpu_regs.sp = addr + 1;
+ return val;
+}
+
+STATIC_INLINE UNUSED uint16_t
+cpu_m68hc12_pop_uint16 (sim_cpu *cpu)
+{
+ struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
+ uint16_t addr = m68hc11_cpu->cpu_regs.sp;
+ uint16_t val;
+
+ val = memory_read16 (cpu, addr);
+ m68hc11_cpu->cpu_regs.sp = addr + 2;
+ return val;
+}
+
+/* Fetch a 8/16 bit value and update the PC. */
+STATIC_INLINE UNUSED uint8_t
+cpu_fetch8 (sim_cpu *cpu)
+{
+ struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
+ uint16_t addr = m68hc11_cpu->cpu_regs.pc;
+ uint8_t val;
+
+ val = memory_read8 (cpu, addr);
+ m68hc11_cpu->cpu_regs.pc = addr + 1;
+ return val;
+}
+
+STATIC_INLINE UNUSED uint16_t
+cpu_fetch16 (sim_cpu *cpu)
+{
+ struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
+ uint16_t addr = m68hc11_cpu->cpu_regs.pc;
+ uint16_t val;
+
+ val = memory_read16 (cpu, addr);
+ m68hc11_cpu->cpu_regs.pc = addr + 2;
+ return val;
+}
+
+extern void cpu_call (sim_cpu *cpu, uint16_t addr);
+extern void cpu_exg (sim_cpu *cpu, uint8_t code);
+extern void cpu_dbcc (sim_cpu *cpu);
+extern void cpu_special (sim_cpu *cpu, enum M6811_Special special);
+extern void cpu_move8 (sim_cpu *cpu, uint8_t op);
+extern void cpu_move16 (sim_cpu *cpu, uint8_t op);
+
+extern uint16_t cpu_fetch_relbranch (sim_cpu *cpu);
+extern uint16_t cpu_fetch_relbranch16 (sim_cpu *cpu);
+extern void cpu_push_all (sim_cpu *cpu);
+extern void cpu_single_step (sim_cpu *cpu);
+
+extern void cpu_info (SIM_DESC sd, sim_cpu *cpu);
+
+extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
+
+/* Returns the address of a 68HC12 indexed operand.
+ Pre and post modifications are handled on the source register. */
+extern uint16_t cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);
+
+extern void cpu_return (sim_cpu *cpu);
+extern void cpu_set_sp (sim_cpu *cpu, uint16_t val);
+extern int cpu_reset (sim_cpu *cpu);
+extern int cpu_restart (sim_cpu *cpu);
+extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
+ uint16_t addr, const char *message, ...)
+ ATTRIBUTE_PRINTF (4, 5);
+extern void emul_os (int op, sim_cpu *cpu);
+extern void cpu_interp_m6811 (sim_cpu *cpu);
+extern void cpu_interp_m6812 (sim_cpu *cpu);
+
+extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
+ double ton, double toff,
+ int64_t repeat);
+extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
+extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
+ unsigned addr, uint8_t val);
+
+extern void sim_board_reset (SIM_DESC sd);
+
+#define PRINT_TIME 0x01
+#define PRINT_CYCLE 0x02
+extern const char *cycle_to_string (sim_cpu *cpu, int64_t t, int flags);
+
+#endif
diff --git a/sim/m68hc11/m68hc11_sim.c b/sim/m68hc11/m68hc11_sim.c
index ef3093ef1e6b..781b598b89c4 100644
--- a/sim/m68hc11/m68hc11_sim.c
+++ b/sim/m68hc11/m68hc11_sim.c
@@ -20,13 +20,15 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* This must come before any other includes. */
#include "defs.h"
+#include <stdlib.h>
+
#include "sim-main.h"
#include "sim-assert.h"
#include "sim-module.h"
#include "sim-options.h"
#include "sim-signal.h"
-#include <stdlib.h>
+#include "m68hc11-sim.h"
enum {
OPTION_CPU_RESET = OPTION_START,
diff --git a/sim/m68hc11/sim-main.h b/sim/m68hc11/sim-main.h
index f320bf10b08c..2714da40c78b 100644
--- a/sim/m68hc11/sim-main.h
+++ b/sim/m68hc11/sim-main.h
@@ -23,545 +23,4 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "sim-basics.h"
#include "sim-base.h"
-#include "opcode/m68hc11.h"
-
-#include "sim/sim.h"
-#include "opcode/m68hc11.h"
-#include "sim-signal.h"
-#include "sim-types.h"
-
-#include "interrupts.h"
-#include <setjmp.h>
-
-/* Specifies the level of mapping for the IO, EEprom, nvram and external
- RAM. IO registers are mapped over everything and the external RAM
- is last (ie, it can be hidden by everything above it in the list). */
-enum m68hc11_map_level
-{
- M6811_IO_LEVEL,
- M6811_EEPROM_LEVEL,
- M6811_NVRAM_LEVEL,
- M6811_RAM_LEVEL
-};
-
-enum cpu_type
-{
- CPU_M6811,
- CPU_M6812
-};
-
-#define X_REGNUM 0
-#define D_REGNUM 1
-#define Y_REGNUM 2
-#define SP_REGNUM 3
-#define PC_REGNUM 4
-#define A_REGNUM 5
-#define B_REGNUM 6
-#define PSW_REGNUM 7
-#define PAGE_REGNUM 8
-#define Z_REGNUM 9
-
-typedef struct m6811_regs {
- unsigned short d;
- unsigned short ix;
- unsigned short iy;
- unsigned short sp;
- unsigned short pc;
- unsigned char ccr;
- unsigned short page;
-} m6811_regs;
-
-
-/* Description of 68HC11 IO registers. Such description is only provided
- for the info command to display the current setting of IO registers
- from GDB. */
-struct io_reg_desc
-{
- int mask;
- const char *short_name;
- const char *long_name;
-};
-typedef struct io_reg_desc io_reg_desc;
-
-extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
- int mode);
-extern void print_io_byte (SIM_DESC sd, const char *name,
- io_reg_desc *desc, uint8_t val, uint16_t addr);
-extern void print_io_word (SIM_DESC sd, const char *name,
- io_reg_desc *desc, uint16_t val, uint16_t addr);
-
-
-/* List of special 68HC11&68HC12 instructions that are not handled by the
- 'gencode.c' generator. These complex instructions are implemented
- by 'cpu_special'. */
-enum M6811_Special
-{
- /* 68HC11 instructions. */
- M6811_DAA,
- M6811_EMUL_SYSCALL,
- M6811_ILLEGAL,
- M6811_RTI,
- M6811_STOP,
- M6811_SWI,
- M6811_TEST,
- M6811_WAI,
-
- /* 68HC12 instructions. */
- M6812_BGND,
- M6812_CALL,
- M6812_CALL_INDIRECT,
- M6812_IDIVS,
- M6812_EDIV,
- M6812_EDIVS,
- M6812_EMACS,
- M6812_EMUL,
- M6812_EMULS,
- M6812_ETBL,
- M6812_MEM,
- M6812_REV,
- M6812_REVW,
- M6812_RTC,
- M6812_RTI,
- M6812_WAV
-};
-
-#define M6811_MAX_PORTS (0x03f+1)
-#define M6812_MAX_PORTS (0x3ff+1)
-#define MAX_PORTS (M6812_MAX_PORTS)
-
-typedef void (* cpu_interp) (sim_cpu *);
-
-struct m68hc11_sim_cpu {
- /* CPU registers. */
- struct m6811_regs cpu_regs;
-
- /* CPU interrupts. */
- struct interrupts cpu_interrupts;
-
- /* Pointer to the interpretor routine. */
- cpu_interp cpu_interpretor;
-
- /* Pointer to the architecture currently configured in the simulator. */
- const struct bfd_arch_info *cpu_configured_arch;
-
- /* CPU absolute cycle time. The cycle time is updated after
- each instruction, by the number of cycles taken by the instruction.
- It is cleared only when reset occurs. */
- int64_t cpu_absolute_cycle;
-
- /* Number of cycles to increment after the current instruction.
- This is also the number of ticks for the generic event scheduler. */
- uint8_t cpu_current_cycle;
- int cpu_emul_syscall;
- int cpu_is_initialized;
- int cpu_running;
- int cpu_check_memory;
- int cpu_stop_on_interrupt;
-
- /* When this is set, start execution of program at address specified
- in the ELF header. This is used for testing some programs that do not
- have an interrupt table linked with them. Programs created during the
- GCC validation are like this. A normal 68HC11 does not behave like
- this (unless there is some OS or downloadable feature). */
- int cpu_use_elf_start;
-
- /* The starting address specified in ELF header. */
- int cpu_elf_start;
-
- uint16_t cpu_insn_pc;
-
- /* CPU frequency. This is the quartz frequency. It is divided by 4 to
- get the cycle time. This is used for the timer rate and for the baud
- rate generation. */
- unsigned long cpu_frequency;
-
- /* The mode in which the CPU is configured (MODA and MODB pins). */
- unsigned int cpu_mode;
- const char* cpu_start_mode;
-
- /* The cpu being configured. */
- enum cpu_type cpu_type;
-
- /* Initial value of the CONFIG register. */
- uint8_t cpu_config;
- uint8_t cpu_use_local_config;
-
- uint8_t ios[MAX_PORTS];
-
- /* Memory bank parameters which describe how the memory bank window
- is mapped in memory and how to convert it in virtual address. */
- uint16_t bank_start;
- uint16_t bank_end;
- address_word bank_virtual;
- unsigned bank_shift;
-
-
- struct hw *hw_cpu;
-};
-#define M68HC11_SIM_CPU(cpu) ((struct m68hc11_sim_cpu *) CPU_ARCH_DATA (cpu))
-
-/* Returns the cpu absolute cycle time (A virtual counter incremented
- at each 68HC11 E clock). */
-#define cpu_current_cycle(cpu) (M68HC11_SIM_CPU (cpu)->cpu_absolute_cycle)
-#define cpu_add_cycles(cpu, T) (M68HC11_SIM_CPU (cpu)->cpu_current_cycle += (int64_t) (T))
-#define cpu_is_running(cpu) (M68HC11_SIM_CPU (cpu)->cpu_running)
-
-/* Get the IO/RAM base addresses depending on the M6811_INIT register. */
-#define cpu_get_io_base(cpu) \
- (((uint16_t)((M68HC11_SIM_CPU (cpu)->ios[M6811_INIT]) & 0x0F)) << 12)
-#define cpu_get_reg_base(cpu) \
- (((uint16_t)((M68HC11_SIM_CPU (cpu)->ios[M6811_INIT]) & 0xF0)) << 8)
-
-/* Returns the different CPU registers. */
-#define cpu_get_ccr(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.ccr)
-#define cpu_get_pc(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.pc)
-#define cpu_get_d(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.d)
-#define cpu_get_x(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.ix)
-#define cpu_get_y(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.iy)
-#define cpu_get_sp(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.sp)
-#define cpu_get_a(cpu) ((M68HC11_SIM_CPU (cpu)->cpu_regs.d >> 8) & 0x0FF)
-#define cpu_get_b(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.d & 0x0FF)
-#define cpu_get_page(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.page)
-
-/* 68HC12 specific and Motorola internal registers. */
-#define cpu_get_tmp3(cpu) (0)
-#define cpu_get_tmp2(cpu) (0)
-
-#define cpu_set_d(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.d = (val))
-#define cpu_set_x(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.ix = (val))
-#define cpu_set_y(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.iy = (val))
-#define cpu_set_page(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.page = (val))
-
-/* 68HC12 specific and Motorola internal registers. */
-#define cpu_set_tmp3(cpu, val) (0)
-#define cpu_set_tmp2(cpu, val) (void) (0)
-
-#if 0
-/* This is a function in m68hc11_sim.c to keep track of the frame. */
-#define cpu_set_sp(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.sp = (val))
#endif
-
-#define cpu_set_pc(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.pc = (val))
-
-#define cpu_set_a(cpu, val) \
- cpu_set_d(cpu, ((val) << 8) | cpu_get_b (cpu))
-#define cpu_set_b(cpu, val) \
- cpu_set_d(cpu, ((cpu_get_a (cpu)) << 8) | ((val) & 0x0FF))
-
-#define cpu_set_ccr(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.ccr = (val))
-#define cpu_get_ccr_H(cpu) ((cpu_get_ccr (cpu) & M6811_H_BIT) ? 1 : 0)
-#define cpu_get_ccr_X(cpu) ((cpu_get_ccr (cpu) & M6811_X_BIT) ? 1 : 0)
-#define cpu_get_ccr_S(cpu) ((cpu_get_ccr (cpu) & M6811_S_BIT) ? 1 : 0)
-#define cpu_get_ccr_N(cpu) ((cpu_get_ccr (cpu) & M6811_N_BIT) ? 1 : 0)
-#define cpu_get_ccr_V(cpu) ((cpu_get_ccr (cpu) & M6811_V_BIT) ? 1 : 0)
-#define cpu_get_ccr_C(cpu) ((cpu_get_ccr (cpu) & M6811_C_BIT) ? 1 : 0)
-#define cpu_get_ccr_Z(cpu) ((cpu_get_ccr (cpu) & M6811_Z_BIT) ? 1 : 0)
-#define cpu_get_ccr_I(cpu) ((cpu_get_ccr (cpu) & M6811_I_BIT) ? 1 : 0)
-
-#define cpu_set_ccr_flag(S, B, V) \
- cpu_set_ccr (S, (cpu_get_ccr (S) & ~(B)) | ((V) ? (B) : 0))
-
-#define cpu_set_ccr_H(cpu, val) cpu_set_ccr_flag (cpu, M6811_H_BIT, val)
-#define cpu_set_ccr_X(cpu, val) cpu_set_ccr_flag (cpu, M6811_X_BIT, val)
-#define cpu_set_ccr_S(cpu, val) cpu_set_ccr_flag (cpu, M6811_S_BIT, val)
-#define cpu_set_ccr_N(cpu, val) cpu_set_ccr_flag (cpu, M6811_N_BIT, val)
-#define cpu_set_ccr_V(cpu, val) cpu_set_ccr_flag (cpu, M6811_V_BIT, val)
-#define cpu_set_ccr_C(cpu, val) cpu_set_ccr_flag (cpu, M6811_C_BIT, val)
-#define cpu_set_ccr_Z(cpu, val) cpu_set_ccr_flag (cpu, M6811_Z_BIT, val)
-#define cpu_set_ccr_I(cpu, val) cpu_set_ccr_flag (cpu, M6811_I_BIT, val)
-
-extern void cpu_memory_exception (sim_cpu *cpu,
- SIM_SIGNAL excep,
- uint16_t addr,
- const char *message);
-
-STATIC_INLINE UNUSED address_word
-phys_to_virt (sim_cpu *cpu, address_word addr)
-{
- struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
-
- if (addr >= m68hc11_cpu->bank_start && addr < m68hc11_cpu->bank_end)
- return ((address_word) (addr - m68hc11_cpu->bank_start)
- + (((address_word) m68hc11_cpu->cpu_regs.page) << m68hc11_cpu->bank_shift)
- + m68hc11_cpu->bank_virtual);
- else
- return (address_word) (addr);
-}
-
-STATIC_INLINE UNUSED uint8_t
-memory_read8 (sim_cpu *cpu, uint16_t addr)
-{
- uint8_t val;
-
- if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
- {
- cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
- "Read error");
- }
- return val;
-}
-
-STATIC_INLINE UNUSED void
-memory_write8 (sim_cpu *cpu, uint16_t addr, uint8_t val)
-{
- if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
- {
- cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
- "Write error");
- }
-}
-
-STATIC_INLINE UNUSED uint16_t
-memory_read16 (sim_cpu *cpu, uint16_t addr)
-{
- uint8_t b[2];
-
- if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
- {
- cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
- "Read error");
- }
- return (((uint16_t) (b[0])) << 8) | ((uint16_t) b[1]);
-}
-
-STATIC_INLINE UNUSED void
-memory_write16 (sim_cpu *cpu, uint16_t addr, uint16_t val)
-{
- uint8_t b[2];
-
- b[0] = val >> 8;
- b[1] = val;
- if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
- {
- cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
- "Write error");
- }
-}
-extern void
-cpu_ccr_update_tst8 (sim_cpu *cpu, uint8_t val);
-
-STATIC_INLINE UNUSED void
-cpu_ccr_update_tst16 (sim_cpu *cpu, uint16_t val)
-{
- cpu_set_ccr_V (cpu, 0);
- cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
- cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
-}
-
-STATIC_INLINE UNUSED void
-cpu_ccr_update_shift8 (sim_cpu *cpu, uint8_t val)
-{
- cpu_set_ccr_N (cpu, val & 0x80 ? 1 : 0);
- cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
- cpu_set_ccr_V (cpu, cpu_get_ccr_N (cpu) ^ cpu_get_ccr_C (cpu));
-}
-
-STATIC_INLINE UNUSED void
-cpu_ccr_update_shift16 (sim_cpu *cpu, uint16_t val)
-{
- cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
- cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
- cpu_set_ccr_V (cpu, cpu_get_ccr_N (cpu) ^ cpu_get_ccr_C (cpu));
-}
-
-STATIC_INLINE UNUSED void
-cpu_ccr_update_add8 (sim_cpu *cpu, uint8_t r, uint8_t a, uint8_t b)
-{
- cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
- cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
- cpu_set_ccr_Z (cpu, r == 0);
- cpu_set_ccr_N (cpu, r & 0x80 ? 1 : 0);
-}
-
-
-STATIC_INLINE UNUSED void
-cpu_ccr_update_sub8 (sim_cpu *cpu, uint8_t r, uint8_t a, uint8_t b)
-{
- cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
- cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
- cpu_set_ccr_Z (cpu, r == 0);
- cpu_set_ccr_N (cpu, r & 0x80 ? 1 : 0);
-}
-
-STATIC_INLINE UNUSED void
-cpu_ccr_update_add16 (sim_cpu *cpu, uint16_t r, uint16_t a, uint16_t b)
-{
- cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
- cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
- cpu_set_ccr_Z (cpu, r == 0);
- cpu_set_ccr_N (cpu, r & 0x8000 ? 1 : 0);
-}
-
-STATIC_INLINE UNUSED void
-cpu_ccr_update_sub16 (sim_cpu *cpu, uint16_t r, uint16_t a, uint16_t b)
-{
- cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
- cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
- cpu_set_ccr_Z (cpu, r == 0);
- cpu_set_ccr_N (cpu, r & 0x8000 ? 1 : 0);
-}
-
-/* Push and pop instructions for 68HC11 (next-available stack mode). */
-STATIC_INLINE UNUSED void
-cpu_m68hc11_push_uint8 (sim_cpu *cpu, uint8_t val)
-{
- struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
- uint16_t addr = m68hc11_cpu->cpu_regs.sp;
-
- memory_write8 (cpu, addr, val);
- m68hc11_cpu->cpu_regs.sp = addr - 1;
-}
-
-STATIC_INLINE UNUSED void
-cpu_m68hc11_push_uint16 (sim_cpu *cpu, uint16_t val)
-{
- struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
- uint16_t addr = m68hc11_cpu->cpu_regs.sp - 1;
-
- memory_write16 (cpu, addr, val);
- m68hc11_cpu->cpu_regs.sp = addr - 1;
-}
-
-STATIC_INLINE UNUSED uint8_t
-cpu_m68hc11_pop_uint8 (sim_cpu *cpu)
-{
- struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
- uint16_t addr = m68hc11_cpu->cpu_regs.sp;
- uint8_t val;
-
- val = memory_read8 (cpu, addr + 1);
- m68hc11_cpu->cpu_regs.sp = addr + 1;
- return val;
-}
-
-STATIC_INLINE UNUSED uint16_t
-cpu_m68hc11_pop_uint16 (sim_cpu *cpu)
-{
- struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
- uint16_t addr = m68hc11_cpu->cpu_regs.sp;
- uint16_t val;
-
- val = memory_read16 (cpu, addr + 1);
- m68hc11_cpu->cpu_regs.sp = addr + 2;
- return val;
-}
-
-/* Push and pop instructions for 68HC12 (last-used stack mode). */
-STATIC_INLINE UNUSED void
-cpu_m68hc12_push_uint8 (sim_cpu *cpu, uint8_t val)
-{
- struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
- uint16_t addr = m68hc11_cpu->cpu_regs.sp;
-
- addr --;
- memory_write8 (cpu, addr, val);
- m68hc11_cpu->cpu_regs.sp = addr;
-}
-
-STATIC_INLINE UNUSED void
-cpu_m68hc12_push_uint16 (sim_cpu *cpu, uint16_t val)
-{
- struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
- uint16_t addr = m68hc11_cpu->cpu_regs.sp;
-
- addr -= 2;
- memory_write16 (cpu, addr, val);
- m68hc11_cpu->cpu_regs.sp = addr;
-}
-
-STATIC_INLINE UNUSED uint8_t
-cpu_m68hc12_pop_uint8 (sim_cpu *cpu)
-{
- struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
- uint16_t addr = m68hc11_cpu->cpu_regs.sp;
- uint8_t val;
-
- val = memory_read8 (cpu, addr);
- m68hc11_cpu->cpu_regs.sp = addr + 1;
- return val;
-}
-
-STATIC_INLINE UNUSED uint16_t
-cpu_m68hc12_pop_uint16 (sim_cpu *cpu)
-{
- struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
- uint16_t addr = m68hc11_cpu->cpu_regs.sp;
- uint16_t val;
-
- val = memory_read16 (cpu, addr);
- m68hc11_cpu->cpu_regs.sp = addr + 2;
- return val;
-}
-
-/* Fetch a 8/16 bit value and update the PC. */
-STATIC_INLINE UNUSED uint8_t
-cpu_fetch8 (sim_cpu *cpu)
-{
- struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
- uint16_t addr = m68hc11_cpu->cpu_regs.pc;
- uint8_t val;
-
- val = memory_read8 (cpu, addr);
- m68hc11_cpu->cpu_regs.pc = addr + 1;
- return val;
-}
-
-STATIC_INLINE UNUSED uint16_t
-cpu_fetch16 (sim_cpu *cpu)
-{
- struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
- uint16_t addr = m68hc11_cpu->cpu_regs.pc;
- uint16_t val;
-
- val = memory_read16 (cpu, addr);
- m68hc11_cpu->cpu_regs.pc = addr + 2;
- return val;
-}
-
-extern void cpu_call (sim_cpu *cpu, uint16_t addr);
-extern void cpu_exg (sim_cpu *cpu, uint8_t code);
-extern void cpu_dbcc (sim_cpu *cpu);
-extern void cpu_special (sim_cpu *cpu, enum M6811_Special special);
-extern void cpu_move8 (sim_cpu *cpu, uint8_t op);
-extern void cpu_move16 (sim_cpu *cpu, uint8_t op);
-
-extern uint16_t cpu_fetch_relbranch (sim_cpu *cpu);
-extern uint16_t cpu_fetch_relbranch16 (sim_cpu *cpu);
-extern void cpu_push_all (sim_cpu *cpu);
-extern void cpu_single_step (sim_cpu *cpu);
-
-extern void cpu_info (SIM_DESC sd, sim_cpu *cpu);
-
-extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
-
-/* Returns the address of a 68HC12 indexed operand.
- Pre and post modifications are handled on the source register. */
-extern uint16_t cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);
-
-extern void cpu_return (sim_cpu *cpu);
-extern void cpu_set_sp (sim_cpu *cpu, uint16_t val);
-extern int cpu_reset (sim_cpu *cpu);
-extern int cpu_restart (sim_cpu *cpu);
-extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
- uint16_t addr, const char *message, ...)
- ATTRIBUTE_PRINTF (4, 5);
-extern void emul_os (int op, sim_cpu *cpu);
-extern void cpu_interp_m6811 (sim_cpu *cpu);
-extern void cpu_interp_m6812 (sim_cpu *cpu);
-
-extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
- double ton, double toff,
- int64_t repeat);
-extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
-extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
- unsigned addr, uint8_t val);
-
-extern void sim_board_reset (SIM_DESC sd);
-
-#define PRINT_TIME 0x01
-#define PRINT_CYCLE 0x02
-extern const char *cycle_to_string (sim_cpu *cpu, int64_t t, int flags);
-
-#endif
-
-
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 19/20] sim: bfin: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
` (17 preceding siblings ...)
2022-12-23 6:07 ` [PATCH 18/20] sim: m68hc11: " Mike Frysinger
@ 2022-12-23 6:07 ` Mike Frysinger
2022-12-23 6:07 ` [PATCH 20/20] sim: m32r: " Mike Frysinger
2022-12-24 1:55 ` [PATCH] sim: or1k: " Mike Frysinger
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:07 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so drop the bfin.h include and move the remaining
bfin-specific settings into it.
---
sim/bfin/bfin-sim.c | 2 ++
sim/bfin/bfin-sim.h | 29 +++++++++++++++++++++++++++++
sim/bfin/devices.h | 2 ++
sim/bfin/dv-bfin_pll.c | 1 -
sim/bfin/interp.c | 3 +++
sim/bfin/machs.c | 3 +++
sim/bfin/sim-main.h | 36 ------------------------------------
7 files changed, 39 insertions(+), 37 deletions(-)
diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c
index 37ac5ce5d6f0..75c6e7c9f1b2 100644
--- a/sim/bfin/bfin-sim.c
+++ b/sim/bfin/bfin-sim.c
@@ -29,6 +29,8 @@
#include "ansidecl.h"
#include "opcode/bfin.h"
#include "sim-main.h"
+#include "arch.h"
+#include "bfin-sim.h"
#include "dv-bfin_cec.h"
#include "dv-bfin_mmu.h"
diff --git a/sim/bfin/bfin-sim.h b/sim/bfin/bfin-sim.h
index 36b9e0235b64..b6573c946dac 100644
--- a/sim/bfin/bfin-sim.h
+++ b/sim/bfin/bfin-sim.h
@@ -35,6 +35,8 @@ typedef int32_t bs32;
typedef int64_t bs40;
typedef int64_t bs64;
+#include "machs.h"
+
/* For dealing with parallel instructions, we must avoid changing our register
file until all parallel insns have been simulated. This queue of stores
can be used to delay a modification.
@@ -359,4 +361,31 @@ extern bu32 hwloop_get_next_pc (SIM_CPU *, bu32, bu32);
#define BFIN_L1_CACHE_BYTES 32
+#define BFIN_CPU_STATE (*(struct bfin_cpu_state *) CPU_ARCH_DATA (cpu))
+#define STATE_BOARD_DATA(sd) ((struct bfin_board_data *) STATE_ARCH_DATA (sd))
+
+#include "dv-bfin_trace.h"
+
+#undef CLAMP
+#define CLAMP(a, b, c) min (max (a, b), c)
+
+/* TODO: Move all this trace logic to the common code. */
+#define BFIN_TRACE_CORE(cpu, addr, size, map, val) \
+ do { \
+ TRACE_CORE (cpu, "%cBUS %s %i bytes @ 0x%08x: 0x%0*x", \
+ map == exec_map ? 'I' : 'D', \
+ map == write_map ? "STORE" : "FETCH", \
+ size, addr, size * 2, val); \
+ PROFILE_COUNT_CORE (cpu, addr, size, map); \
+ } while (0)
+#define BFIN_TRACE_BRANCH(cpu, oldpc, newpc, hwloop, fmt, ...) \
+ do { \
+ TRACE_BRANCH (cpu, fmt " to %#x", ## __VA_ARGS__, newpc); \
+ if (STATE_ENVIRONMENT (CPU_STATE (cpu)) == OPERATING_ENVIRONMENT) \
+ bfin_trace_queue (cpu, oldpc, newpc, hwloop); \
+ } while (0)
+
+/* Default memory size. */
+#define BFIN_DEFAULT_MEM_SIZE (128 * 1024 * 1024)
+
#endif
diff --git a/sim/bfin/devices.h b/sim/bfin/devices.h
index b772aa2e2583..348df3ce148c 100644
--- a/sim/bfin/devices.h
+++ b/sim/bfin/devices.h
@@ -26,6 +26,8 @@
#include "hw-device.h"
#include "hw-tree.h"
+#include "bfin-sim.h"
+
/* We keep the same inital structure layout with DMA enabled devices. */
struct dv_bfin {
bu32 base;
diff --git a/sim/bfin/dv-bfin_pll.c b/sim/bfin/dv-bfin_pll.c
index 97b9dc1e259f..dc6627ae77ba 100644
--- a/sim/bfin/dv-bfin_pll.c
+++ b/sim/bfin/dv-bfin_pll.c
@@ -22,7 +22,6 @@
#include "defs.h"
#include "sim-main.h"
-#include "machs.h"
#include "devices.h"
#include "dv-bfin_pll.h"
diff --git a/sim/bfin/interp.c b/sim/bfin/interp.c
index 493c3b62ffb8..04c1773eaf42 100644
--- a/sim/bfin/interp.c
+++ b/sim/bfin/interp.c
@@ -34,9 +34,12 @@
#include "sim/callback.h"
#include "gdb/signals.h"
#include "sim-main.h"
+#include "sim-options.h"
#include "sim-syscall.h"
#include "sim-hw.h"
+#include "bfin-sim.h"
+
/* The numbers here do not matter. They just need to be unique. They also
need not be static across releases -- they're used internally only. The
mapping from the Linux ABI to the CB values is in linux-targ-map.h. */
diff --git a/sim/bfin/machs.c b/sim/bfin/machs.c
index adc0eb355319..acb2613b4e5e 100644
--- a/sim/bfin/machs.c
+++ b/sim/bfin/machs.c
@@ -28,7 +28,10 @@
#include "bfd.h"
#include "sim-hw.h"
+#include "sim-options.h"
+
#include "devices.h"
+#include "arch.h"
#include "dv-bfin_cec.h"
#include "dv-bfin_dmac.h"
diff --git a/sim/bfin/sim-main.h b/sim/bfin/sim-main.h
index a3855f3ded63..65ba92582c3f 100644
--- a/sim/bfin/sim-main.h
+++ b/sim/bfin/sim-main.h
@@ -22,42 +22,6 @@
#define _BFIN_MAIN_SIM_H_
#include "sim-basics.h"
-#include "arch.h"
#include "sim-base.h"
-#include "bfin-sim.h"
-
-#include "machs.h"
-
-#define BFIN_CPU_STATE (*(struct bfin_cpu_state *) CPU_ARCH_DATA (cpu))
-#define STATE_BOARD_DATA(sd) ((struct bfin_board_data *) STATE_ARCH_DATA (sd))
-
-#include "sim-config.h"
-#include "sim-types.h"
-#include "sim-engine.h"
-#include "sim-options.h"
-#include "dv-bfin_trace.h"
-
-#undef CLAMP
-#define CLAMP(a, b, c) min (max (a, b), c)
-
-/* TODO: Move all this trace logic to the common code. */
-#define BFIN_TRACE_CORE(cpu, addr, size, map, val) \
- do { \
- TRACE_CORE (cpu, "%cBUS %s %i bytes @ 0x%08x: 0x%0*x", \
- map == exec_map ? 'I' : 'D', \
- map == write_map ? "STORE" : "FETCH", \
- size, addr, size * 2, val); \
- PROFILE_COUNT_CORE (cpu, addr, size, map); \
- } while (0)
-#define BFIN_TRACE_BRANCH(cpu, oldpc, newpc, hwloop, fmt, ...) \
- do { \
- TRACE_BRANCH (cpu, fmt " to %#x", ## __VA_ARGS__, newpc); \
- if (STATE_ENVIRONMENT (CPU_STATE (cpu)) == OPERATING_ENVIRONMENT) \
- bfin_trace_queue (cpu, oldpc, newpc, hwloop); \
- } while (0)
-
-/* Default memory size. */
-#define BFIN_DEFAULT_MEM_SIZE (128 * 1024 * 1024)
-
#endif
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 20/20] sim: m32r: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
` (18 preceding siblings ...)
2022-12-23 6:07 ` [PATCH 19/20] sim: bfin: " Mike Frysinger
@ 2022-12-23 6:07 ` Mike Frysinger
2022-12-24 1:55 ` [PATCH] sim: or1k: " Mike Frysinger
20 siblings, 0 replies; 23+ messages in thread
From: Mike Frysinger @ 2022-12-23 6:07 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to the existing m32r-sim.h.
Unfortunately, we can't yet drop the m32r-sim.h include from sim-main.h
as many of the generated CGEN files refer only to sim-main.h. We'll
have to improve the CGEN interface before we can make more progress,
but this is at least a minor improvement.
---
sim/m32r/m32r-sim.h | 22 ++++++++++++++++++++++
sim/m32r/m32r.c | 2 ++
sim/m32r/m32r2.c | 2 ++
sim/m32r/m32rx.c | 2 ++
sim/m32r/sim-if.c | 1 +
sim/m32r/sim-main.h | 24 ++----------------------
sim/m32r/traps.c | 2 ++
7 files changed, 33 insertions(+), 22 deletions(-)
diff --git a/sim/m32r/m32r-sim.h b/sim/m32r/m32r-sim.h
index fc41c2146f75..3586f3297880 100644
--- a/sim/m32r/m32r-sim.h
+++ b/sim/m32r/m32r-sim.h
@@ -166,5 +166,27 @@ do { \
/* Handle the trap insn. */
USI m32r_trap (SIM_CPU *, PCADDR, int);
+\f
+struct m32r_sim_cpu {
+ M32R_MISC_PROFILE m32r_misc_profile;
+#define CPU_M32R_MISC_PROFILE(cpu) (& M32R_SIM_CPU (cpu)->m32r_misc_profile)
+
+ /* CPU specific parts go here.
+ Note that in files that don't need to access these pieces WANT_CPU_FOO
+ won't be defined and thus these parts won't appear. This is ok in the
+ sense that things work. It is a source of bugs though.
+ One has to of course be careful to not take the size of this
+ struct and no structure members accessed in non-cpu specific files can
+ go after here. Oh for a better language. */
+#if defined (WANT_CPU_M32RBF)
+ M32RBF_CPU_DATA cpu_data;
+#endif
+#if defined (WANT_CPU_M32RXF)
+ M32RXF_CPU_DATA cpu_data;
+#elif defined (WANT_CPU_M32R2F)
+ M32R2F_CPU_DATA cpu_data;
+#endif
+};
+#define M32R_SIM_CPU(cpu) ((struct m32r_sim_cpu *) CPU_ARCH_DATA (cpu))
#endif /* M32R_SIM_H */
diff --git a/sim/m32r/m32r.c b/sim/m32r/m32r.c
index 478a45c25869..014aa712c160 100644
--- a/sim/m32r/m32r.c
+++ b/sim/m32r/m32r.c
@@ -28,6 +28,8 @@
#include "cgen-ops.h"
#include <stdlib.h>
+#include "m32r-sim.h"
+
/* Return the size of REGNO in bytes. */
static int
diff --git a/sim/m32r/m32r2.c b/sim/m32r/m32r2.c
index 8881bc68081f..b95e509a41aa 100644
--- a/sim/m32r/m32r2.c
+++ b/sim/m32r/m32r2.c
@@ -27,6 +27,8 @@
#include "cgen-mem.h"
#include "cgen-ops.h"
+#include "m32r-sim.h"
+
/* The contents of BUF are in target byte order. */
int
diff --git a/sim/m32r/m32rx.c b/sim/m32r/m32rx.c
index e5724c5410d6..52073e1344a0 100644
--- a/sim/m32r/m32rx.c
+++ b/sim/m32r/m32rx.c
@@ -27,6 +27,8 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "cgen-mem.h"
#include "cgen-ops.h"
+#include "m32r-sim.h"
+
/* The contents of BUF are in target byte order. */
int
diff --git a/sim/m32r/sim-if.c b/sim/m32r/sim-if.c
index e11545461c5d..c8c04b38b68a 100644
--- a/sim/m32r/sim-if.c
+++ b/sim/m32r/sim-if.c
@@ -30,6 +30,7 @@
#include "libiberty.h"
#include "bfd.h"
+#include "m32r-sim.h"
#include "dv-m32r_uart.h"
#define M32R_DEFAULT_MEM_SIZE 0x2000000 /* 32M */
diff --git a/sim/m32r/sim-main.h b/sim/m32r/sim-main.h
index 70962320dfc7..9a52563f25a2 100644
--- a/sim/m32r/sim-main.h
+++ b/sim/m32r/sim-main.h
@@ -14,29 +14,9 @@
#include "arch.h"
#include "sim-base.h"
#include "cgen-sim.h"
-#include "m32r-sim.h"
-\f
-struct m32r_sim_cpu {
- M32R_MISC_PROFILE m32r_misc_profile;
-#define CPU_M32R_MISC_PROFILE(cpu) (& M32R_SIM_CPU (cpu)->m32r_misc_profile)
- /* CPU specific parts go here.
- Note that in files that don't need to access these pieces WANT_CPU_FOO
- won't be defined and thus these parts won't appear. This is ok in the
- sense that things work. It is a source of bugs though.
- One has to of course be careful to not take the size of this
- struct and no structure members accessed in non-cpu specific files can
- go after here. Oh for a better language. */
-#if defined (WANT_CPU_M32RBF)
- M32RBF_CPU_DATA cpu_data;
-#endif
-#if defined (WANT_CPU_M32RXF)
- M32RXF_CPU_DATA cpu_data;
-#elif defined (WANT_CPU_M32R2F)
- M32R2F_CPU_DATA cpu_data;
-#endif
-};
-#define M32R_SIM_CPU(cpu) ((struct m32r_sim_cpu *) CPU_ARCH_DATA (cpu))
+/* TODO: Move this to the CGEN generated files instead. */
+#include "m32r-sim.h"
\f
/* Misc. */
diff --git a/sim/m32r/traps.c b/sim/m32r/traps.c
index 12a87b4a6978..b82f974dc534 100644
--- a/sim/m32r/traps.c
+++ b/sim/m32r/traps.c
@@ -55,6 +55,8 @@
#include <linux/unistd.h>
#endif
+#include "m32r-sim.h"
+
#define TRAP_LINUX_SYSCALL 2
#define TRAP_FLUSH_CACHE 12
/* The semantic code invokes this for invalid (unrecognized) instructions. */
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH] sim: or1k: move arch-specific settings to internal header
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
` (19 preceding siblings ...)
2022-12-23 6:07 ` [PATCH 20/20] sim: m32r: " Mike Frysinger
@ 2022-12-24 1:55 ` Mike Frysinger
2022-12-24 10:18 ` Stafford Horne
20 siblings, 1 reply; 23+ messages in thread
From: Mike Frysinger @ 2022-12-24 1:55 UTC (permalink / raw)
To: gdb-patches
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to the existing or1k-sim.h.
Unfortunately, we can't yet drop the or1k-sim.h include from sim-main.h
as many of the generated CGEN files refer only to sim-main.h. We'll
have to improve the CGEN interface before we can make more progress,
but this is at least a minor improvement.
---
sim/or1k/or1k-sim.h | 27 +++++++++++++++++++++++++++
sim/or1k/sim-main.h | 32 ++------------------------------
sim/or1k/traps.c | 1 +
3 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/sim/or1k/or1k-sim.h b/sim/or1k/or1k-sim.h
index 417272033cd1..61d542fcf7c8 100644
--- a/sim/or1k/or1k-sim.h
+++ b/sim/or1k/or1k-sim.h
@@ -89,4 +89,31 @@ USI or1k32bf_make_load_store_addr (sim_cpu *current_cpu, USI base, SI offset,
USI or1k32bf_ff1 (sim_cpu *current_cpu, USI val);
USI or1k32bf_fl1 (sim_cpu *current_cpu, USI val);
+#define OR1K_DEFAULT_MEM_SIZE 0x800000 /* 8M */
+
+struct or1k_sim_cpu
+{
+ OR1K_MISC_PROFILE or1k_misc_profile;
+#define CPU_OR1K_MISC_PROFILE(cpu) (& OR1K_SIM_CPU (cpu)->or1k_misc_profile)
+
+ /* CPU specific parts go here.
+ Note that in files that don't need to access these pieces WANT_CPU_FOO
+ won't be defined and thus these parts won't appear. This is ok in the
+ sense that things work. It is a source of bugs though.
+ One has to of course be careful to not take the size of this
+ struct and no structure members accessed in non-cpu specific files can
+ go after here. Oh for a better language. */
+ UWI spr[NUM_SPR];
+
+ /* Next instruction will be in delay slot. */
+ BI next_delay_slot;
+ /* Currently in delay slot. */
+ BI delay_slot;
+
+#ifdef WANT_CPU_OR1K32BF
+ OR1K32BF_CPU_DATA cpu_data;
+#endif
+};
+#define OR1K_SIM_CPU(cpu) ((struct or1k_sim_cpu *) CPU_ARCH_DATA (cpu))
+
#endif /* OR1K_SIM_H */
diff --git a/sim/or1k/sim-main.h b/sim/or1k/sim-main.h
index 24c8ddb0e31a..7dd3e9a66550 100644
--- a/sim/or1k/sim-main.h
+++ b/sim/or1k/sim-main.h
@@ -21,42 +21,14 @@
#define WITH_SCACHE_PBB 1
-#include "ansidecl.h"
#include "or1k-desc.h"
#include "or1k-opc.h"
#include "sim-basics.h"
#include "arch.h"
#include "sim-base.h"
-#include "sim-fpu.h"
-
#include "cgen-sim.h"
-#include "or1k-sim.h"
-#define OR1K_DEFAULT_MEM_SIZE 0x800000 /* 8M */
-
-struct or1k_sim_cpu
-{
- OR1K_MISC_PROFILE or1k_misc_profile;
-#define CPU_OR1K_MISC_PROFILE(cpu) (& OR1K_SIM_CPU (cpu)->or1k_misc_profile)
-
- /* CPU specific parts go here.
- Note that in files that don't need to access these pieces WANT_CPU_FOO
- won't be defined and thus these parts won't appear. This is ok in the
- sense that things work. It is a source of bugs though.
- One has to of course be careful to not take the size of this
- struct and no structure members accessed in non-cpu specific files can
- go after here. Oh for a better language. */
- UWI spr[NUM_SPR];
-
- /* Next instruction will be in delay slot. */
- BI next_delay_slot;
- /* Currently in delay slot. */
- BI delay_slot;
-
-#ifdef WANT_CPU_OR1K32BF
- OR1K32BF_CPU_DATA cpu_data;
-#endif
-};
-#define OR1K_SIM_CPU(cpu) ((struct or1k_sim_cpu *) CPU_ARCH_DATA (cpu))
+/* TODO: Move this to the CGEN generated files instead. */
+#include "or1k-sim.h"
#endif /* SIM_MAIN_H */
diff --git a/sim/or1k/traps.c b/sim/or1k/traps.c
index 97e81f41e7da..6fe94d88abd6 100644
--- a/sim/or1k/traps.c
+++ b/sim/or1k/traps.c
@@ -23,6 +23,7 @@
#define WANT_CPU
#include "sim-main.h"
+#include "sim-fpu.h"
#include "sim-signal.h"
#include "cgen-ops.h"
--
2.39.0
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH] sim: or1k: move arch-specific settings to internal header
2022-12-24 1:55 ` [PATCH] sim: or1k: " Mike Frysinger
@ 2022-12-24 10:18 ` Stafford Horne
0 siblings, 0 replies; 23+ messages in thread
From: Stafford Horne @ 2022-12-24 10:18 UTC (permalink / raw)
To: Mike Frysinger; +Cc: gdb-patches
On Fri, Dec 23, 2022 at 08:55:39PM -0500, Mike Frysinger via Gdb-patches wrote:
> There's no need for these settings to be in sim-main.h which is shared
> with common/ sim code, so move it all out to the existing or1k-sim.h.
> Unfortunately, we can't yet drop the or1k-sim.h include from sim-main.h
> as many of the generated CGEN files refer only to sim-main.h. We'll
> have to improve the CGEN interface before we can make more progress,
> but this is at least a minor improvement.
> ---
> sim/or1k/or1k-sim.h | 27 +++++++++++++++++++++++++++
> sim/or1k/sim-main.h | 32 ++------------------------------
> sim/or1k/traps.c | 1 +
> 3 files changed, 30 insertions(+), 30 deletions(-)
>
> diff --git a/sim/or1k/or1k-sim.h b/sim/or1k/or1k-sim.h
> index 417272033cd1..61d542fcf7c8 100644
> --- a/sim/or1k/or1k-sim.h
> +++ b/sim/or1k/or1k-sim.h
> @@ -89,4 +89,31 @@ USI or1k32bf_make_load_store_addr (sim_cpu *current_cpu, USI base, SI offset,
> USI or1k32bf_ff1 (sim_cpu *current_cpu, USI val);
> USI or1k32bf_fl1 (sim_cpu *current_cpu, USI val);
>
> +#define OR1K_DEFAULT_MEM_SIZE 0x800000 /* 8M */
> +
> +struct or1k_sim_cpu
> +{
> + OR1K_MISC_PROFILE or1k_misc_profile;
> +#define CPU_OR1K_MISC_PROFILE(cpu) (& OR1K_SIM_CPU (cpu)->or1k_misc_profile)
> +
> + /* CPU specific parts go here.
> + Note that in files that don't need to access these pieces WANT_CPU_FOO
> + won't be defined and thus these parts won't appear. This is ok in the
> + sense that things work. It is a source of bugs though.
> + One has to of course be careful to not take the size of this
> + struct and no structure members accessed in non-cpu specific files can
> + go after here. Oh for a better language. */
> + UWI spr[NUM_SPR];
> +
> + /* Next instruction will be in delay slot. */
> + BI next_delay_slot;
> + /* Currently in delay slot. */
> + BI delay_slot;
> +
> +#ifdef WANT_CPU_OR1K32BF
> + OR1K32BF_CPU_DATA cpu_data;
> +#endif
> +};
> +#define OR1K_SIM_CPU(cpu) ((struct or1k_sim_cpu *) CPU_ARCH_DATA (cpu))
> +
> #endif /* OR1K_SIM_H */
> diff --git a/sim/or1k/sim-main.h b/sim/or1k/sim-main.h
> index 24c8ddb0e31a..7dd3e9a66550 100644
> --- a/sim/or1k/sim-main.h
> +++ b/sim/or1k/sim-main.h
> @@ -21,42 +21,14 @@
>
> #define WITH_SCACHE_PBB 1
>
> -#include "ansidecl.h"
> #include "or1k-desc.h"
> #include "or1k-opc.h"
> #include "sim-basics.h"
> #include "arch.h"
> #include "sim-base.h"
> -#include "sim-fpu.h"
> -
> #include "cgen-sim.h"
> -#include "or1k-sim.h"
>
> -#define OR1K_DEFAULT_MEM_SIZE 0x800000 /* 8M */
> -
> -struct or1k_sim_cpu
> -{
> - OR1K_MISC_PROFILE or1k_misc_profile;
> -#define CPU_OR1K_MISC_PROFILE(cpu) (& OR1K_SIM_CPU (cpu)->or1k_misc_profile)
> -
> - /* CPU specific parts go here.
> - Note that in files that don't need to access these pieces WANT_CPU_FOO
> - won't be defined and thus these parts won't appear. This is ok in the
> - sense that things work. It is a source of bugs though.
> - One has to of course be careful to not take the size of this
> - struct and no structure members accessed in non-cpu specific files can
> - go after here. Oh for a better language. */
> - UWI spr[NUM_SPR];
> -
> - /* Next instruction will be in delay slot. */
> - BI next_delay_slot;
> - /* Currently in delay slot. */
> - BI delay_slot;
> -
> -#ifdef WANT_CPU_OR1K32BF
> - OR1K32BF_CPU_DATA cpu_data;
> -#endif
> -};
> -#define OR1K_SIM_CPU(cpu) ((struct or1k_sim_cpu *) CPU_ARCH_DATA (cpu))
> +/* TODO: Move this to the CGEN generated files instead. */
> +#include "or1k-sim.h"
>
> #endif /* SIM_MAIN_H */
> diff --git a/sim/or1k/traps.c b/sim/or1k/traps.c
> index 97e81f41e7da..6fe94d88abd6 100644
> --- a/sim/or1k/traps.c
> +++ b/sim/or1k/traps.c
> @@ -23,6 +23,7 @@
> #define WANT_CPU
>
> #include "sim-main.h"
> +#include "sim-fpu.h"
> #include "sim-signal.h"
> #include "cgen-ops.h"
>
> --
> 2.39.0
This all looks good to me.
Please commit,
-Stafford
^ permalink raw reply [flat|nested] 23+ messages in thread