From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH 04/12] RISC-V: GAS: Add basic shared test utilities
Date: Sat, 5 Nov 2022 12:29:10 +0000 [thread overview]
Message-ID: <6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1667651354.git.research_trasio@irq.a4lg.com>
This commit adds basic shared test utilities intended for future
extension tests.
gas/ChangeLog:
* testsuite/gas/riscv/testutils.inc: New test utilities.
---
gas/testsuite/gas/riscv/testutils.inc | 113 ++++++++++++++++++++++++++
1 file changed, 113 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/testutils.inc
diff --git a/gas/testsuite/gas/riscv/testutils.inc b/gas/testsuite/gas/riscv/testutils.inc
new file mode 100644
index 00000000000..009484eefed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/testutils.inc
@@ -0,0 +1,113 @@
+# Set NOARCH symbols.
+.ifndef NOARCH
+.set NOARCH, 0
+.endif
+.ifndef NOARCH_ARCH
+.set NOARCH_ARCH, 0
+.endif
+.ifndef NOARCH_XLEN
+.set NOARCH_XLEN, 0
+.endif
+.if NOARCH
+.set NOARCH_ARCH, 1
+.set NOARCH_XLEN, 1
+.endif
+
+# Update XLEN constraint symbols.
+# For intentional error handling tests, .if SYM ... .endif block should be
+# used to test those varibales.
+.macro UPDATE_XLEN
+ .if NOARCH_XLEN
+ # When NOARCH_XLEN is set,
+ # set those variables to "invalid" 1 to generate errors.
+ .set XLEN_EQ_32, 1
+ .set XLEN_EQ_64, 1
+ .set XLEN_GE_64, 1
+ .else
+ # Set symbol values depending on the XLEN.
+ .ifdef XLEN
+ .ifeq XLEN-32
+ .set XLEN_EQ_32, 1
+ .else
+ .set XLEN_EQ_32, 0
+ .endif
+ .ifeq XLEN-64
+ .set XLEN_EQ_64, 1
+ .else
+ .set XLEN_EQ_64, 0
+ .endif
+ .ifge XLEN-64
+ .set XLEN_GE_64, 1
+ .else
+ .set XLEN_GE_64, 0
+ .endif
+ .else
+ .set XLEN_EQ_32, 0
+ .set XLEN_EQ_64, 0
+ .set XLEN_GE_64, 0
+ .endif
+ .endif
+.endm
+UPDATE_XLEN
+
+# Set the base architecture.
+.macro SET_BASE_FORCE xlen, basearch=i
+ .option arch, rv\xlen\basearch
+ .set XLEN, \xlen
+ UPDATE_XLEN
+.endm
+
+# Set the base architecture unless the symbol NOARCH_ARCH is set.
+.macro SET_BASE xlen, basearch=i
+ .if !NOARCH_ARCH
+ SET_BASE_FORCE \xlen, \basearch
+ .endif
+.endm
+
+# Begin base architecture block.
+.macro SET_BASE_START_FORCE xlen, basearch=i
+ .option push
+ SET_BASE_FORCE \xlen, \basearch
+.endm
+
+# Begin base architecture block.
+# Don't change the architecture if NOARCH_ARCH is set.
+.macro SET_BASE_START xlen, basearch=i
+ .option push
+ SET_BASE \xlen, \basearch
+.endm
+
+# End base architecture block.
+.macro SET_BASE_END
+ .option pop
+.endm
+
+# Set the architecture.
+.macro SET_ARCH_FORCE arch
+ .option arch, \arch
+.endm
+
+# Set the architecture unless the symbol NOARCH_ARCH is set.
+.macro SET_ARCH arch
+ .ifeq NOARCH_ARCH-0
+ SET_ARCH_FORCE \arch
+ .endif
+.endm
+
+# Begin architecture block.
+.macro SET_ARCH_START_FORCE arch
+ .option push
+ SET_ARCH_FORCE \arch
+.endm
+
+# Begin architecture block.
+# Don't change the architecture if NOARCH_ARCH is set.
+.macro SET_ARCH_START arch
+ .option push
+ SET_ARCH \arch
+.endm
+
+# End architecture block.
+.macro SET_ARCH_END
+ .option pop
+.endm
--
2.37.2
next prev parent reply other threads:[~2022-11-05 12:30 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
2022-11-05 12:29 ` [PATCH 01/12] RISC-V: Remove unnecessary empty matching file Tsukasa OI
2022-11-29 7:38 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 02/12] RISC-V: Tidy disassembler corner case tests Tsukasa OI
2022-11-29 7:48 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 03/12] RISC-V: Tidying related to 'Zfinx' disassembler test Tsukasa OI
2022-11-29 7:50 ` Nelson Chu
2022-11-05 12:29 ` Tsukasa OI [this message]
2022-11-29 7:53 ` [PATCH 04/12] RISC-V: GAS: Add basic shared test utilities Nelson Chu
2022-11-05 12:29 ` [PATCH 05/12] RISC-V: Redefine "nop" test Tsukasa OI
2022-11-29 7:58 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 06/12] RISC-V: Reorganize/enhance {sign,zero}-extension instructions Tsukasa OI
2022-11-29 8:10 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 07/12] RISC-V: Combine complex extension error handling tests Tsukasa OI
2022-11-29 8:16 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 08/12] RISC-V: Refine/enhance 'M'/'Zmmul' extension tests Tsukasa OI
2022-11-29 8:23 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 09/12] RISC-V: Combine/enhance 'Zicbo[mz]' " Tsukasa OI
2022-11-29 8:38 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 10/12] RISC-V: Enhance 'Zicbop' testcases Tsukasa OI
2022-11-29 8:51 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 11/12] RISC-V: Reorganize/enhance 'Zb*' extension tests Tsukasa OI
2022-11-29 8:57 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 12/12] RISC-V: Combine/enhance 'Zk*'/'Zbk*' " Tsukasa OI
2022-11-29 9:00 ` Nelson Chu
2022-11-20 2:28 ` [PING^1][PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
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