From: Nelson Chu <nelson@rivosinc.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
binutils@sourceware.org
Subject: Re: [PATCH 07/12] RISC-V: Combine complex extension error handling tests
Date: Tue, 29 Nov 2022 16:16:36 +0800 [thread overview]
Message-ID: <CAPpQWtBU6g2JGgkxjSvKqX4b4rmUwB7Sw9UH_4FXz_ROLQw=SQ@mail.gmail.com> (raw)
In-Reply-To: <ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com>
On Sat, Nov 5, 2022 at 8:30 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> Because mapping symbols with ISA string is now supported, we can now
> combine five complex "no required extensions" testcases related to
> the "fcvt.d.h" instruction into one.
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/zfhmin-d-noarch.s: Combined.
> * testsuite/gas/riscv/zfhmin-d-noarch.d: Likewise.
> Minimize extension requirements.
> * testsuite/gas/riscv/zfhmin-d-noarch.l: Likewise.
> Make matching pattern stricter.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail.s: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l: Removed.
> ---
> .../gas/riscv/zfhmin-d-insn-class-fail-1.d | 3 ---
> .../gas/riscv/zfhmin-d-insn-class-fail-1.l | 2 --
> .../gas/riscv/zfhmin-d-insn-class-fail-2.d | 3 ---
> .../gas/riscv/zfhmin-d-insn-class-fail-2.l | 2 --
> .../gas/riscv/zfhmin-d-insn-class-fail-3.d | 3 ---
> .../gas/riscv/zfhmin-d-insn-class-fail-3.l | 2 --
> .../gas/riscv/zfhmin-d-insn-class-fail-4.d | 3 ---
> .../gas/riscv/zfhmin-d-insn-class-fail-4.l | 2 --
> .../gas/riscv/zfhmin-d-insn-class-fail-5.d | 3 ---
> .../gas/riscv/zfhmin-d-insn-class-fail-5.l | 2 --
> .../gas/riscv/zfhmin-d-insn-class-fail.s | 4 ---
> gas/testsuite/gas/riscv/zfhmin-d-noarch.d | 2 ++
> gas/testsuite/gas/riscv/zfhmin-d-noarch.l | 6 +++++
> gas/testsuite/gas/riscv/zfhmin-d-noarch.s | 25 +++++++++++++++++++
> 14 files changed, 33 insertions(+), 29 deletions(-)
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s
> create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-noarch.s
>
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d
> deleted file mode 100644
> index 02a11943cf2..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv64i
> -#source: zfhmin-d-insn-class-fail.s
> -#error_output: zfhmin-d-insn-class-fail-1.l
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l
> deleted file mode 100644
> index 12f41a39ae0..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -.*: Assembler messages:
> -.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zfhmin' and `d', or `zhinxmin' and `zdinx' required
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d
> deleted file mode 100644
> index 27b5a12857e..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv64i_zhinxmin
> -#source: zfhmin-d-insn-class-fail.s
> -#error_output: zfhmin-d-insn-class-fail-2.l
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l
> deleted file mode 100644
> index 255f96cb5a1..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -.*: Assembler messages:
> -.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zdinx' required
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d
> deleted file mode 100644
> index 4f195bfa7c5..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv64i_zdinx
> -#source: zfhmin-d-insn-class-fail.s
> -#error_output: zfhmin-d-insn-class-fail-3.l
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l
> deleted file mode 100644
> index 7ff7b278fe3..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -.*: Assembler messages:
> -.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zhinxmin' required
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d
> deleted file mode 100644
> index 940d48c5dfd..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv64i_zfhmin
> -#source: zfhmin-d-insn-class-fail.s
> -#error_output: zfhmin-d-insn-class-fail-4.l
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l
> deleted file mode 100644
> index 2d58e4ce1ce..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -.*: Assembler messages:
> -.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `d' required
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d
> deleted file mode 100644
> index af26d5e9ea7..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv64id
> -#source: zfhmin-d-insn-class-fail.s
> -#error_output: zfhmin-d-insn-class-fail-5.l
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l
> deleted file mode 100644
> index 2fa6e8c754b..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -.*: Assembler messages:
> -.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zfhmin' required
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s
> deleted file mode 100644
> index 691d0a929dc..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -# This test checks error message corresponding required extension(s).
> -# Operands are invalid on Zhinxmin+Zdinx but they are not parsed since
> -# extension test fails.
> -fcvt.d.h fa0, fa1
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-noarch.d b/gas/testsuite/gas/riscv/zfhmin-d-noarch.d
> new file mode 100644
> index 00000000000..fded578caea
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zfhmin-d-noarch.d
> @@ -0,0 +1,2 @@
> +#as: -march=rv64i -I$srcdir/$subdir
> +#error_output: zfhmin-d-noarch.l
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-noarch.l b/gas/testsuite/gas/riscv/zfhmin-d-noarch.l
> new file mode 100644
> index 00000000000..8a55ccaac2b
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zfhmin-d-noarch.l
> @@ -0,0 +1,6 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `fcvt\.d\.h fa0,fa1', extension `zfhmin' and `d', or `zhinxmin' and `zdinx' required
> +.*: Error: unrecognized opcode `fcvt\.d\.h fa0,fa1', extension `d' required
> +.*: Error: unrecognized opcode `fcvt\.d\.h fa0,fa1', extension `zfhmin' required
> +.*: Error: unrecognized opcode `fcvt\.d\.h a0,a1', extension `zdinx' required
> +.*: Error: unrecognized opcode `fcvt\.d\.h a0,a1', extension `zhinxmin' required
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-noarch.s b/gas/testsuite/gas/riscv/zfhmin-d-noarch.s
> new file mode 100644
> index 00000000000..f247de1bd36
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zfhmin-d-noarch.s
> @@ -0,0 +1,25 @@
> +.include "testutils.inc"
> +
> +target:
> + # Case 1: No 'Zfhmin', 'D', 'Zhinxmin' or 'Zdinx'
> + fcvt.d.h fa0, fa1
> +
> + # Case 2: 'Zfhmin' but no 'D'
> + SET_ARCH_START +zfhmin
> + fcvt.d.h fa0, fa1
> + SET_ARCH_END
> +
> + # Case 3: 'D' but no 'Zfhmin'
> + SET_ARCH_START +d
> + fcvt.d.h fa0, fa1
> + SET_ARCH_END
> +
> + # Case 4: 'Zhinxmin' but no 'Zdinx'
> + SET_ARCH_START +zhinxmin
> + fcvt.d.h a0, a1
> + SET_ARCH_END
> +
> + # Case 5: 'Zdinx' but no 'Zhinxmin'
> + SET_ARCH_START +zdinx
> + fcvt.d.h a0, a1
> + SET_ARCH_END
This is pretty close to what I thought, but don't need to add those
complicated macros. Just using ".option arch" directly should be
enough.
Thanks
Nelson
> --
> 2.37.2
>
next prev parent reply other threads:[~2022-11-29 8:16 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
2022-11-05 12:29 ` [PATCH 01/12] RISC-V: Remove unnecessary empty matching file Tsukasa OI
2022-11-29 7:38 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 02/12] RISC-V: Tidy disassembler corner case tests Tsukasa OI
2022-11-29 7:48 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 03/12] RISC-V: Tidying related to 'Zfinx' disassembler test Tsukasa OI
2022-11-29 7:50 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 04/12] RISC-V: GAS: Add basic shared test utilities Tsukasa OI
2022-11-29 7:53 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 05/12] RISC-V: Redefine "nop" test Tsukasa OI
2022-11-29 7:58 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 06/12] RISC-V: Reorganize/enhance {sign,zero}-extension instructions Tsukasa OI
2022-11-29 8:10 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 07/12] RISC-V: Combine complex extension error handling tests Tsukasa OI
2022-11-29 8:16 ` Nelson Chu [this message]
2022-11-05 12:29 ` [PATCH 08/12] RISC-V: Refine/enhance 'M'/'Zmmul' extension tests Tsukasa OI
2022-11-29 8:23 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 09/12] RISC-V: Combine/enhance 'Zicbo[mz]' " Tsukasa OI
2022-11-29 8:38 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 10/12] RISC-V: Enhance 'Zicbop' testcases Tsukasa OI
2022-11-29 8:51 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 11/12] RISC-V: Reorganize/enhance 'Zb*' extension tests Tsukasa OI
2022-11-29 8:57 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 12/12] RISC-V: Combine/enhance 'Zk*'/'Zbk*' " Tsukasa OI
2022-11-29 9:00 ` Nelson Chu
2022-11-20 2:28 ` [PING^1][PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
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