From: Nelson Chu <nelson@rivosinc.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
binutils@sourceware.org
Subject: Re: [PATCH 09/12] RISC-V: Combine/enhance 'Zicbo[mz]' extension tests
Date: Tue, 29 Nov 2022 16:38:59 +0800 [thread overview]
Message-ID: <CAPpQWtAioEp2MtNsmXNGS2df9Qy6-kx5-RY5K2jU765V-Rqcwg@mail.gmail.com> (raw)
In-Reply-To: <82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com>
On Sat, Nov 5, 2022 at 8:30 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> This commit combines tests for 'Zicbom' and 'Zicboz' extensions and adds
> "no required extension" testcases based on new test utilities. It also
> contains minor tidying (such as minimizing base from RV64G to RV32I).
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/zicbo-mz-ext.s: Combine zicbo[mz].s.
> * testsuite/gas/riscv/zicbo-mz-ext.d: Likewise.
> Minimize extension requirements and remove source.
> * testsuite/gas/riscv/zicbo-mz-ext-noarch.d: New test for
> architecture failure.
> * testsuite/gas/riscv/zicbo-mz-ext-noarch.l: Likewise.
> * testsuite/gas/riscv/zicbo-mz-ext-fail.s: Combine
> zicbo[mz]-fail.s.
> * testsuite/gas/riscv/zicbo-mz-ext-fail.d: Likewise.
> Minimize extension requirements.
> * testsuite/gas/riscv/zicbo-mz-ext-fail.l: Likewise.
> Make matching pattern stricter.
> * testsuite/gas/riscv/zicbom.s: Removed.
> * testsuite/gas/riscv/zicbom.d: Removed.
> * testsuite/gas/riscv/zicbom-fail.s: Removed.
> * testsuite/gas/riscv/zicbom-fail.d: Removed.
> * testsuite/gas/riscv/zicbom-fail.l: Removed.
> * testsuite/gas/riscv/zicboz.s: Removed.
> * testsuite/gas/riscv/zicboz.d: Removed.
> * testsuite/gas/riscv/zicboz-fail.s: Removed.
> * testsuite/gas/riscv/zicboz-fail.d: Removed.
> * testsuite/gas/riscv/zicboz-fail.l: Removed.
> ---
> gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d | 2 ++
> gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l | 11 +++++++++++
> .../riscv/{zicbom-fail.s => zicbo-mz-ext-fail.s} | 4 ++++
> gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d | 3 +++
> gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l | 11 +++++++++++
> .../gas/riscv/{zicbom.d => zicbo-mz-ext.d} | 9 ++++++---
> gas/testsuite/gas/riscv/zicbo-mz-ext.s | 16 ++++++++++++++++
One testcase for zicbom-zicboz.s/d, and the other testcase for
zicbom-zicboz-fail.s/d. Use .option arch directly rather than those
new defined macros. Personally, I think we don't need the no-arch
test cases since it's trivial, but that's just my personal thought.
Thanks
Nelson
> gas/testsuite/gas/riscv/zicbom-fail.d | 3 ---
> gas/testsuite/gas/riscv/zicbom-fail.l | 7 -------
> gas/testsuite/gas/riscv/zicbom.s | 7 -------
> gas/testsuite/gas/riscv/zicboz-fail.d | 3 ---
> gas/testsuite/gas/riscv/zicboz-fail.l | 5 -----
> gas/testsuite/gas/riscv/zicboz-fail.s | 5 -----
> gas/testsuite/gas/riscv/zicboz.d | 13 -------------
> gas/testsuite/gas/riscv/zicboz.s | 5 -----
> 15 files changed, 53 insertions(+), 51 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d
> create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l
> rename gas/testsuite/gas/riscv/{zicbom-fail.s => zicbo-mz-ext-fail.s} (61%)
> create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l
> rename gas/testsuite/gas/riscv/{zicbom.d => zicbo-mz-ext.d} (60%)
> create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext.s
> delete mode 100644 gas/testsuite/gas/riscv/zicbom-fail.d
> delete mode 100644 gas/testsuite/gas/riscv/zicbom-fail.l
> delete mode 100644 gas/testsuite/gas/riscv/zicbom.s
> delete mode 100644 gas/testsuite/gas/riscv/zicboz-fail.d
> delete mode 100644 gas/testsuite/gas/riscv/zicboz-fail.l
> delete mode 100644 gas/testsuite/gas/riscv/zicboz-fail.s
> delete mode 100644 gas/testsuite/gas/riscv/zicboz.d
> delete mode 100644 gas/testsuite/gas/riscv/zicboz.s
>
> diff --git a/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d b/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d
> new file mode 100644
> index 00000000000..e84233b09a1
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d
> @@ -0,0 +1,2 @@
> +#as: -march=rv32i_zicbom_zicboz
> +#error_output: zicbo-mz-ext-fail.l
> diff --git a/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l b/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l
> new file mode 100644
> index 00000000000..a0bd7096f25
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l
> @@ -0,0 +1,11 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cbo\.clean 1\(x1\)'
> +.*: Error: illegal operands `cbo\.clean x30'
> +.*: Error: illegal operands `cbo\.flush \(0\+1\)\(x1\)'
> +.*: Error: illegal operands `cbo\.flush x30'
> +.*: Error: illegal operands `cbo\.inval 3\*2\+5\(x1\)'
> +.*: Error: illegal operands `cbo\.inval x30'
> +.*: Error: illegal operands `cbo\.zero x1'
> +.*: Error: illegal operands `cbo\.zero 1\(x30\)'
> +.*: Error: illegal operands `cbo\.zero 3\+5\(x1\)'
> +.*: Error: illegal operands `cbo\.zero \(2\*4\)\(x30\)'
> diff --git a/gas/testsuite/gas/riscv/zicbom-fail.s b/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.s
> similarity index 61%
> rename from gas/testsuite/gas/riscv/zicbom-fail.s
> rename to gas/testsuite/gas/riscv/zicbo-mz-ext-fail.s
> index 5fa22749b3a..447e9c37de7 100644
> --- a/gas/testsuite/gas/riscv/zicbom-fail.s
> +++ b/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.s
> @@ -5,3 +5,7 @@ target:
> cbo.flush x30
> cbo.inval 3*2+5(x1)
> cbo.inval x30
> + cbo.zero x1
> + cbo.zero 1(x30)
> + cbo.zero 3+5(x1)
> + cbo.zero (2*4)(x30)
> diff --git a/gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d b/gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d
> new file mode 100644
> index 00000000000..33db96dd471
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i -I$srcdir/$subdir -defsym NOARCH=1
> +#source: zicbo-mz-ext.s
> +#error_output: zicbo-mz-ext-noarch.l
> diff --git a/gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l b/gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l
> new file mode 100644
> index 00000000000..6cf1e4821a2
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l
> @@ -0,0 +1,11 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `cbo\.clean \(x1\)', extension `zicbom' required
> +.*: Error: unrecognized opcode `cbo\.clean 0\(x30\)', extension `zicbom' required
> +.*: Error: unrecognized opcode `cbo\.flush \(x1\)', extension `zicbom' required
> +.*: Error: unrecognized opcode `cbo\.flush \(2-2\)\(x30\)', extension `zicbom' required
> +.*: Error: unrecognized opcode `cbo\.inval \(x1\)', extension `zicbom' required
> +.*: Error: unrecognized opcode `cbo\.inval 3\*4-12\(x30\)', extension `zicbom' required
> +.*: Error: unrecognized opcode `cbo\.zero 0\(x1\)', extension `zicboz' required
> +.*: Error: unrecognized opcode `cbo\.zero \(x30\)', extension `zicboz' required
> +.*: Error: unrecognized opcode `cbo\.zero 2-2\(x1\)', extension `zicboz' required
> +.*: Error: unrecognized opcode `cbo\.zero \(3\*5-15\)\(x30\)', extension `zicboz' required
> diff --git a/gas/testsuite/gas/riscv/zicbom.d b/gas/testsuite/gas/riscv/zicbo-mz-ext.d
> similarity index 60%
> rename from gas/testsuite/gas/riscv/zicbom.d
> rename to gas/testsuite/gas/riscv/zicbo-mz-ext.d
> index edd8a7079f4..9daa1cc4a93 100644
> --- a/gas/testsuite/gas/riscv/zicbom.d
> +++ b/gas/testsuite/gas/riscv/zicbo-mz-ext.d
> @@ -1,6 +1,5 @@
> -#as: -march=rv64g_zicbom
> -#source: zicbom.s
> -#objdump: -dr
> +#as: -march=rv32i -I$srcdir/$subdir
> +#objdump: -d
>
> .*:[ ]+file format .*
>
> @@ -13,3 +12,7 @@ Disassembly of section .text:
> [ ]+[0-9a-f]+:[ ]+002f200f[ ]+cbo\.flush[ ]+\(t5\)
> [ ]+[0-9a-f]+:[ ]+0000a00f[ ]+cbo\.inval[ ]+\(ra\)
> [ ]+[0-9a-f]+:[ ]+000f200f[ ]+cbo\.inval[ ]+\(t5\)
> +[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+\(ra\)
> +[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+\(t5\)
> +[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+\(ra\)
> +[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+\(t5\)
> diff --git a/gas/testsuite/gas/riscv/zicbo-mz-ext.s b/gas/testsuite/gas/riscv/zicbo-mz-ext.s
> new file mode 100644
> index 00000000000..af997377903
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicbo-mz-ext.s
> @@ -0,0 +1,16 @@
> +.include "testutils.inc"
> +target:
> + SET_ARCH_START +zicbom
> + cbo.clean (x1)
> + cbo.clean 0(x30)
> + cbo.flush (x1)
> + cbo.flush (2-2)(x30)
> + cbo.inval (x1)
> + cbo.inval 3*4-12(x30)
> + SET_ARCH_END
> + SET_ARCH_START +zicboz
> + cbo.zero 0(x1)
> + cbo.zero (x30)
> + cbo.zero 2-2(x1)
> + cbo.zero (3*5-15)(x30)
> + SET_ARCH_END
> diff --git a/gas/testsuite/gas/riscv/zicbom-fail.d b/gas/testsuite/gas/riscv/zicbom-fail.d
> deleted file mode 100644
> index a6a61dfd37e..00000000000
> --- a/gas/testsuite/gas/riscv/zicbom-fail.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv64g_zicbom
> -#source: zicbom-fail.s
> -#error_output: zicbom-fail.l
> diff --git a/gas/testsuite/gas/riscv/zicbom-fail.l b/gas/testsuite/gas/riscv/zicbom-fail.l
> deleted file mode 100644
> index 2cf76356d2b..00000000000
> --- a/gas/testsuite/gas/riscv/zicbom-fail.l
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -.*: Assembler messages:
> -.*: Error: illegal operands `cbo.clean 1\(x1\)'
> -.*: Error: illegal operands `cbo.clean x30'
> -.*: Error: illegal operands `cbo.flush \(0\+1\)\(x1\)'
> -.*: Error: illegal operands `cbo.flush x30'
> -.*: Error: illegal operands `cbo.inval 3\*2\+5\(x1\)'
> -.*: Error: illegal operands `cbo.inval x30'
> diff --git a/gas/testsuite/gas/riscv/zicbom.s b/gas/testsuite/gas/riscv/zicbom.s
> deleted file mode 100644
> index 6a306b931ed..00000000000
> --- a/gas/testsuite/gas/riscv/zicbom.s
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -target:
> - cbo.clean (x1)
> - cbo.clean 0(x30)
> - cbo.flush (x1)
> - cbo.flush (2-2)(x30)
> - cbo.inval (x1)
> - cbo.inval 3*4-12(x30)
> diff --git a/gas/testsuite/gas/riscv/zicboz-fail.d b/gas/testsuite/gas/riscv/zicboz-fail.d
> deleted file mode 100644
> index 74cfd2fc911..00000000000
> --- a/gas/testsuite/gas/riscv/zicboz-fail.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv64g_zicboz
> -#source: zicboz-fail.s
> -#error_output: zicboz-fail.l
> diff --git a/gas/testsuite/gas/riscv/zicboz-fail.l b/gas/testsuite/gas/riscv/zicboz-fail.l
> deleted file mode 100644
> index ad8dcf54e00..00000000000
> --- a/gas/testsuite/gas/riscv/zicboz-fail.l
> +++ /dev/null
> @@ -1,5 +0,0 @@
> -.*: Assembler messages:
> -.*: Error: illegal operands `cbo.zero x1'
> -.*: Error: illegal operands `cbo.zero 1\(x30\)'
> -.*: Error: illegal operands `cbo.zero 3\+5\(x1\)'
> -.*: Error: illegal operands `cbo.zero \(2\*4\)\(x30\)'
> diff --git a/gas/testsuite/gas/riscv/zicboz-fail.s b/gas/testsuite/gas/riscv/zicboz-fail.s
> deleted file mode 100644
> index 0856ea85ab1..00000000000
> --- a/gas/testsuite/gas/riscv/zicboz-fail.s
> +++ /dev/null
> @@ -1,5 +0,0 @@
> -target:
> - cbo.zero x1
> - cbo.zero 1(x30)
> - cbo.zero 3+5(x1)
> - cbo.zero (2*4)(x30)
> diff --git a/gas/testsuite/gas/riscv/zicboz.d b/gas/testsuite/gas/riscv/zicboz.d
> deleted file mode 100644
> index e04ab3491db..00000000000
> --- a/gas/testsuite/gas/riscv/zicboz.d
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -#as: -march=rv64g_zicboz
> -#source: zicboz.s
> -#objdump: -dr
> -
> -.*:[ ]+file format .*
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+\(ra\)
> -[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+\(t5\)
> -[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+\(ra\)
> -[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+\(t5\)
> diff --git a/gas/testsuite/gas/riscv/zicboz.s b/gas/testsuite/gas/riscv/zicboz.s
> deleted file mode 100644
> index 3830362c376..00000000000
> --- a/gas/testsuite/gas/riscv/zicboz.s
> +++ /dev/null
> @@ -1,5 +0,0 @@
> -target:
> - cbo.zero 0(x1)
> - cbo.zero (x30)
> - cbo.zero 2-2(x1)
> - cbo.zero (3*5-15)(x30)
> --
> 2.37.2
>
next prev parent reply other threads:[~2022-11-29 8:39 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
2022-11-05 12:29 ` [PATCH 01/12] RISC-V: Remove unnecessary empty matching file Tsukasa OI
2022-11-29 7:38 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 02/12] RISC-V: Tidy disassembler corner case tests Tsukasa OI
2022-11-29 7:48 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 03/12] RISC-V: Tidying related to 'Zfinx' disassembler test Tsukasa OI
2022-11-29 7:50 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 04/12] RISC-V: GAS: Add basic shared test utilities Tsukasa OI
2022-11-29 7:53 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 05/12] RISC-V: Redefine "nop" test Tsukasa OI
2022-11-29 7:58 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 06/12] RISC-V: Reorganize/enhance {sign,zero}-extension instructions Tsukasa OI
2022-11-29 8:10 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 07/12] RISC-V: Combine complex extension error handling tests Tsukasa OI
2022-11-29 8:16 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 08/12] RISC-V: Refine/enhance 'M'/'Zmmul' extension tests Tsukasa OI
2022-11-29 8:23 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 09/12] RISC-V: Combine/enhance 'Zicbo[mz]' " Tsukasa OI
2022-11-29 8:38 ` Nelson Chu [this message]
2022-11-05 12:29 ` [PATCH 10/12] RISC-V: Enhance 'Zicbop' testcases Tsukasa OI
2022-11-29 8:51 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 11/12] RISC-V: Reorganize/enhance 'Zb*' extension tests Tsukasa OI
2022-11-29 8:57 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 12/12] RISC-V: Combine/enhance 'Zk*'/'Zbk*' " Tsukasa OI
2022-11-29 9:00 ` Nelson Chu
2022-11-20 2:28 ` [PING^1][PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
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