From: Nelson Chu <nelson@rivosinc.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
binutils@sourceware.org
Subject: Re: [PATCH 02/12] RISC-V: Tidy disassembler corner case tests
Date: Tue, 29 Nov 2022 15:48:14 +0800 [thread overview]
Message-ID: <CAPpQWtD-OcWn0rymUxDmd=5tmNejC6b6oCC5FcmL5R7Ha=VKzw@mail.gmail.com> (raw)
In-Reply-To: <4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com>
If the purpose of this patch is to prepare to support rv128 or larger
xlen, then I'm ok with it, although it seems useless until we have
already had any rv128 instructions. Btw, I cannot figure out the
purpose of this patch from the title "RISC-V: Tidy disassembler corner
case tests". It seems like it's not only for the tidy from the
contents.
Thanks
Nelson
On Sat, Nov 5, 2022 at 8:29 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> Because later commits use "XLEN" symbol rather than "rv64", it replaces
> occurrences of "rv64" with "XLEN" and makes other tidying changes for
> consistency with other testcases.
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/dis-addr-addiw-a.d: Tidying.
> * testsuite/gas/riscv/dis-addr-addiw-b.d: Likewise.
> * testsuite/gas/riscv/dis-addr-overflow.s: Tidying.
> * testsuite/gas/riscv/dis-addr-overflow-32.d: Use XLEN symbol.
> * testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise.
> * testsuite/gas/riscv/dis-addr-topaddr-gp.s: Tidying.
> * testsuite/gas/riscv/dis-addr-topaddr-gp-32.d: Use XLEN symbol.
> * testsuite/gas/riscv/dis-addr-topaddr-gp-64.d: Likewise.
> * testsuite/gas/riscv/dis-addr-topaddr.s: Moved to...
> * testsuite/gas/riscv/dis-addr-topaddr-zero.s: ...here
> with tidying.
> * testsuite/gas/riscv/dis-addr-topaddr-32.d: Moved to...
> * testsuite/gas/riscv/dis-addr-topaddr-zero-32.d: ...here.
> Use XLEN symbol. Minimize architecture requirements.
> * testsuite/gas/riscv/dis-addr-topaddr-64.d: Moved to...
> * testsuite/gas/riscv/dis-addr-topaddr-zero-64.d: ...here.
> Use XLEN symbol. Minimize architecture requirements.
> ---
> gas/testsuite/gas/riscv/dis-addr-addiw-a.d | 2 +-
> gas/testsuite/gas/riscv/dis-addr-addiw-b.d | 2 +-
> .../gas/riscv/dis-addr-overflow-32.d | 4 +-
> .../gas/riscv/dis-addr-overflow-64.d | 4 +-
> gas/testsuite/gas/riscv/dis-addr-overflow.s | 40 +++++++++----------
> .../gas/riscv/dis-addr-topaddr-gp-32.d | 4 +-
> .../gas/riscv/dis-addr-topaddr-gp-64.d | 4 +-
> gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s | 12 +++---
> ...opaddr-32.d => dis-addr-topaddr-zero-32.d} | 6 +--
> ...opaddr-64.d => dis-addr-topaddr-zero-64.d} | 6 +--
> .../gas/riscv/dis-addr-topaddr-zero.s | 11 +++++
> gas/testsuite/gas/riscv/dis-addr-topaddr.s | 10 -----
> 12 files changed, 53 insertions(+), 52 deletions(-)
> rename gas/testsuite/gas/riscv/{dis-addr-topaddr-32.d => dis-addr-topaddr-zero-32.d} (60%)
> rename gas/testsuite/gas/riscv/{dis-addr-topaddr-64.d => dis-addr-topaddr-zero-64.d} (58%)
> create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-zero.s
> delete mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr.s
>
> diff --git a/gas/testsuite/gas/riscv/dis-addr-addiw-a.d b/gas/testsuite/gas/riscv/dis-addr-addiw-a.d
> index c4e4cfe6df7..44837ff4f69 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-addiw-a.d
> +++ b/gas/testsuite/gas/riscv/dis-addr-addiw-a.d
> @@ -2,7 +2,7 @@
> #source: dis-addr-addiw.s
> #objdump: -d --adjust-vma=0xffffffe0
>
> -.*: file format elf64-(little|big)riscv
> +.*:[ ]+file format .*
>
>
> Disassembly of section .text:
> diff --git a/gas/testsuite/gas/riscv/dis-addr-addiw-b.d b/gas/testsuite/gas/riscv/dis-addr-addiw-b.d
> index d5f84db172e..bc1841f35f1 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-addiw-b.d
> +++ b/gas/testsuite/gas/riscv/dis-addr-addiw-b.d
> @@ -2,7 +2,7 @@
> #source: dis-addr-addiw.s
> #objdump: -d --adjust-vma=0x7fffffe0
>
> -.*: file format elf64-(little|big)riscv
> +.*:[ ]+file format .*
>
>
> Disassembly of section .text:
> diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow-32.d b/gas/testsuite/gas/riscv/dis-addr-overflow-32.d
> index 287c5ea022f..b246605e361 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-overflow-32.d
> +++ b/gas/testsuite/gas/riscv/dis-addr-overflow-32.d
> @@ -1,8 +1,8 @@
> -#as: -march=rv32ic
> +#as: -march=rv32ic -defsym XLEN=32
> #source: dis-addr-overflow.s
> #objdump: -d
>
> -.*: file format elf32-(little|big)riscv
> +.*:[ ]+file format .*
>
>
> Disassembly of section .text:
> diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow-64.d b/gas/testsuite/gas/riscv/dis-addr-overflow-64.d
> index 1966a5ed743..61885edbc75 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-overflow-64.d
> +++ b/gas/testsuite/gas/riscv/dis-addr-overflow-64.d
> @@ -1,8 +1,8 @@
> -#as: -march=rv64ic -defsym rv64=1
> +#as: -march=rv64ic -defsym XLEN=64
> #source: dis-addr-overflow.s
> #objdump: -d
>
> -.*: file format elf64-(little|big)riscv
> +.*:[ ]+file format .*
>
>
> Disassembly of section .text:
> diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow.s b/gas/testsuite/gas/riscv/dis-addr-overflow.s
> index 77ca39c07b6..47e5351c9fc 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-overflow.s
> +++ b/gas/testsuite/gas/riscv/dis-addr-overflow.s
> @@ -1,26 +1,26 @@
> -.set __global_pointer$, 0x00000200
> +.set __global_pointer$, 0x00000200
>
> -.ifdef rv64
> -topbase = 0xffffffff00000000
> +.ifge XLEN-64
> +.set topbase, 0xffffffff00000000
> .else
> -topbase = 0
> +.set topbase, 0
> .endif
>
> -.set addr_load, topbase + 0xffffeffc # -0x1000 -4
> -.set addr_store, topbase + 0xffffdff8 # -0x2000 -8
> -.set addr_jalr_1, topbase + 0xffffd000 # -0x3000
> -.set addr_jalr_2, topbase + 0xffffbff4 # -0x4000 -12
> -.set addr_jalr_3, topbase + 0xffffb000 # -0x5000
> -.set addr_loadaddr, topbase + 0xffff9ff0 # -0x6000 -16
> -.set addr_loadaddr_c, topbase + 0xffff8fec # -0x7000 -20
> -.set addr_loadaddr_w, topbase + 0xffff7fe8 # -0x8000 -24
> -.set addr_loadaddr_w_c, topbase + 0xffff6fe4 # -0x9000 -28
> -.set addr_rel_gp_pos, 0x00000600 # __global_pointer$ + 0x400
> -.set addr_rel_gp_neg, topbase + 0xfffffe00 # __global_pointer$ - 0x400
> -.set addr_rel_zero_pos, 0x00000100
> -.set addr_rel_zero_neg, topbase + 0xfffff800 # -0x800
> -.set addr_jalr_rel_zero_pos, 0x00000104
> -.set addr_jalr_rel_zero_neg, topbase + 0xfffff804 # -0x7fc
> +.set addr_load, topbase + 0xffffeffc # -0x1000 -4
> +.set addr_store, topbase + 0xffffdff8 # -0x2000 -8
> +.set addr_jalr_1, topbase + 0xffffd000 # -0x3000
> +.set addr_jalr_2, topbase + 0xffffbff4 # -0x4000 -12
> +.set addr_jalr_3, topbase + 0xffffb000 # -0x5000
> +.set addr_loadaddr, topbase + 0xffff9ff0 # -0x6000 -16
> +.set addr_loadaddr_c, topbase + 0xffff8fec # -0x7000 -20
> +.set addr_loadaddr_w, topbase + 0xffff7fe8 # -0x8000 -24
> +.set addr_loadaddr_w_c, topbase + 0xffff6fe4 # -0x9000 -28
> +.set addr_rel_gp_pos, 0x00000600 # __global_pointer$ + 0x400
> +.set addr_rel_gp_neg, topbase + 0xfffffe00 # __global_pointer$ - 0x400
> +.set addr_rel_zero_pos, 0x00000100
> +.set addr_rel_zero_neg, topbase + 0xfffff800 # -0x800
> +.set addr_jalr_rel_zero_pos, 0x00000104
> +.set addr_jalr_rel_zero_neg, topbase + 0xfffff804 # -0x7fc
>
> target:
> .option push
> @@ -48,7 +48,7 @@ target:
> lui t6, 0xffff9
> .option pop
> c.addi t6, -20
> -.ifdef rv64
> +.ifge XLEN-64
> .option push
> .option arch, -c
> # ADDIW (not compressed)
> diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
> index 875bfe73189..cdbbe3bf846 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
> +++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
> @@ -1,8 +1,8 @@
> -#as: -march=rv32i
> +#as: -march=rv32i -defsym XLEN=32
> #source: dis-addr-topaddr-gp.s
> #objdump: -d
>
> -.*: file format elf32-(little|big)riscv
> +.*:[ ]+file format .*
>
>
> Disassembly of section .text:
> diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
> index 5ac4b52b18d..54fc8631901 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
> +++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
> @@ -1,8 +1,8 @@
> -#as: -march=rv64i -defsym rv64=1
> +#as: -march=rv64i -defsym XLEN=64
> #source: dis-addr-topaddr-gp.s
> #objdump: -d
>
> -.*: file format elf64-(little|big)riscv
> +.*:[ ]+file format .*
>
>
> Disassembly of section .text:
> diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s
> index 6ba9fc7a39d..1689cdf89c1 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s
> +++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s
> @@ -1,12 +1,12 @@
> -.ifdef rv64
> -topbase = 0xffffffff00000000
> +.ifge XLEN-64
> +.set topbase, 0xffffffff00000000
> .else
> -topbase = 0
> +.set topbase, 0
> .endif
>
> -.set __global_pointer$, topbase + 0xffffffff # -1
> -.set addr_rel_gp_pos, 0x00000004 # +4
> -.set addr_rel_gp_neg, topbase + 0xfffffffc # -4
> +.set __global_pointer$, topbase + 0xffffffff # -1
> +.set addr_rel_gp_pos, 0x00000004 # +4
> +.set addr_rel_gp_neg, topbase + 0xfffffffc # -4
>
> target:
> # Use addresses relative to gp
> diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-32.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-zero-32.d
> similarity index 60%
> rename from gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
> rename to gas/testsuite/gas/riscv/dis-addr-topaddr-zero-32.d
> index 87854cd58e6..2934e2d5fec 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
> +++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-zero-32.d
> @@ -1,8 +1,8 @@
> -#as: -march=rv32ic
> -#source: dis-addr-topaddr.s
> +#as: -march=rv32i -defsym XLEN=32
> +#source: dis-addr-topaddr-zero.s
> #objdump: -d
>
> -.*: file format elf32-(little|big)riscv
> +.*:[ ]+file format .*
>
>
> Disassembly of section .text:
> diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-64.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-zero-64.d
> similarity index 58%
> rename from gas/testsuite/gas/riscv/dis-addr-topaddr-64.d
> rename to gas/testsuite/gas/riscv/dis-addr-topaddr-zero-64.d
> index 38f67efdcaf..9b2d170d3d6 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-topaddr-64.d
> +++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-zero-64.d
> @@ -1,8 +1,8 @@
> -#as: -march=rv64ic -defsym rv64=1
> -#source: dis-addr-topaddr.s
> +#as: -march=rv64i -defsym XLEN=64
> +#source: dis-addr-topaddr-zero.s
> #objdump: -d
>
> -.*: file format elf64-(little|big)riscv
> +.*:[ ]+file format .*
>
>
> Disassembly of section .text:
> diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-zero.s b/gas/testsuite/gas/riscv/dis-addr-topaddr-zero.s
> new file mode 100644
> index 00000000000..cdf44b5403b
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-zero.s
> @@ -0,0 +1,11 @@
> +.ifge XLEN-64
> +.set topbase, 0xffffffff00000000
> +.else
> +.set topbase, 0
> +.endif
> +
> +.set addr_top, topbase + 0xffffffff # -1
> +
> +target:
> + # Use address relative to zero
> + lb t0, -1(zero)
> diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr.s b/gas/testsuite/gas/riscv/dis-addr-topaddr.s
> deleted file mode 100644
> index b66587f448d..00000000000
> --- a/gas/testsuite/gas/riscv/dis-addr-topaddr.s
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -.ifdef rv64
> -topbase = 0xffffffff00000000
> -.else
> -topbase = 0
> -.endif
> -
> -.set addr_top, topbase + 0xffffffff # -1
> -
> -target:
> - lb t0, -1(zero)
> --
> 2.37.2
>
next prev parent reply other threads:[~2022-11-29 7:48 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
2022-11-05 12:29 ` [PATCH 01/12] RISC-V: Remove unnecessary empty matching file Tsukasa OI
2022-11-29 7:38 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 02/12] RISC-V: Tidy disassembler corner case tests Tsukasa OI
2022-11-29 7:48 ` Nelson Chu [this message]
2022-11-05 12:29 ` [PATCH 03/12] RISC-V: Tidying related to 'Zfinx' disassembler test Tsukasa OI
2022-11-29 7:50 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 04/12] RISC-V: GAS: Add basic shared test utilities Tsukasa OI
2022-11-29 7:53 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 05/12] RISC-V: Redefine "nop" test Tsukasa OI
2022-11-29 7:58 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 06/12] RISC-V: Reorganize/enhance {sign,zero}-extension instructions Tsukasa OI
2022-11-29 8:10 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 07/12] RISC-V: Combine complex extension error handling tests Tsukasa OI
2022-11-29 8:16 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 08/12] RISC-V: Refine/enhance 'M'/'Zmmul' extension tests Tsukasa OI
2022-11-29 8:23 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 09/12] RISC-V: Combine/enhance 'Zicbo[mz]' " Tsukasa OI
2022-11-29 8:38 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 10/12] RISC-V: Enhance 'Zicbop' testcases Tsukasa OI
2022-11-29 8:51 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 11/12] RISC-V: Reorganize/enhance 'Zb*' extension tests Tsukasa OI
2022-11-29 8:57 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 12/12] RISC-V: Combine/enhance 'Zk*'/'Zbk*' " Tsukasa OI
2022-11-29 9:00 ` Nelson Chu
2022-11-20 2:28 ` [PING^1][PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
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