From: Nelson Chu <nelson@rivosinc.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
binutils@sourceware.org
Subject: Re: [PATCH 10/12] RISC-V: Enhance 'Zicbop' testcases
Date: Tue, 29 Nov 2022 16:51:04 +0800 [thread overview]
Message-ID: <CAPpQWtAriWpK746Fth_ra2T_L=bRV4mpfLePfZFbLaZvRDKOow@mail.gmail.com> (raw)
In-Reply-To: <9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com>
On Sat, Nov 5, 2022 at 8:31 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> This commit makes some tidying and enhancements to 'Zicbop' testcases.
> It adds "no required extension" testcases based on new test utilities. It
> adds the hint of the failure reason to the file names.
I suggest moving the zicbop into zicbom-zicboz test case, and don't
care the no-arch test cases for now.
Nelson
> gas/ChangeLog:
>
> * testsuite/gas/riscv/zicbop.s: Enhanced to test offset zero.
> * testsuite/gas/riscv/zicbop.d: Likewise.
> Minimize extension requirements and objdump options.
> * testsuite/gas/riscv/zicbop-noarch.s: New test for
> architecture failure.
> * testsuite/gas/riscv/zicbop-noarch.d: Likewise.
> * testsuite/gas/riscv/zicbop-noarch.l: Likewise.
> * testsuite/gas/riscv/zicbop-fail-offset.s: Move from
> zicbop-fail.s.
> * testsuite/gas/riscv/zicbop-fail-offset.d: Likewise.
> Minimize extension requirements.
> * testsuite/gas/riscv/zicbop-fail-offset.l: Likewise.
> * testsuite/gas/riscv/zicbop-fail.s: Removed.
> * testsuite/gas/riscv/zicbop-fail.d: Removed.
> * testsuite/gas/riscv/zicbop-fail.l: Removed.
> ---
> gas/testsuite/gas/riscv/zicbop-fail-offset.d | 2 ++
> .../gas/riscv/{zicbop-fail.l => zicbop-fail-offset.l} | 0
> .../gas/riscv/{zicbop-fail.s => zicbop-fail-offset.s} | 0
> gas/testsuite/gas/riscv/zicbop-fail.d | 3 ---
> gas/testsuite/gas/riscv/zicbop-noarch.d | 4 ++++
> gas/testsuite/gas/riscv/zicbop-noarch.l | 7 +++++++
> gas/testsuite/gas/riscv/zicbop.d | 8 +++++---
> gas/testsuite/gas/riscv/zicbop.s | 7 +++++++
> 8 files changed, 25 insertions(+), 6 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/zicbop-fail-offset.d
> rename gas/testsuite/gas/riscv/{zicbop-fail.l => zicbop-fail-offset.l} (100%)
> rename gas/testsuite/gas/riscv/{zicbop-fail.s => zicbop-fail-offset.s} (100%)
> delete mode 100644 gas/testsuite/gas/riscv/zicbop-fail.d
> create mode 100644 gas/testsuite/gas/riscv/zicbop-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zicbop-noarch.l
>
> diff --git a/gas/testsuite/gas/riscv/zicbop-fail-offset.d b/gas/testsuite/gas/riscv/zicbop-fail-offset.d
> new file mode 100644
> index 00000000000..4680f6eef0d
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicbop-fail-offset.d
> @@ -0,0 +1,2 @@
> +#as: -march=rv32i_zicbop
> +#error_output: zicbop-fail-offset.l
> diff --git a/gas/testsuite/gas/riscv/zicbop-fail.l b/gas/testsuite/gas/riscv/zicbop-fail-offset.l
> similarity index 100%
> rename from gas/testsuite/gas/riscv/zicbop-fail.l
> rename to gas/testsuite/gas/riscv/zicbop-fail-offset.l
> diff --git a/gas/testsuite/gas/riscv/zicbop-fail.s b/gas/testsuite/gas/riscv/zicbop-fail-offset.s
> similarity index 100%
> rename from gas/testsuite/gas/riscv/zicbop-fail.s
> rename to gas/testsuite/gas/riscv/zicbop-fail-offset.s
> diff --git a/gas/testsuite/gas/riscv/zicbop-fail.d b/gas/testsuite/gas/riscv/zicbop-fail.d
> deleted file mode 100644
> index d734c7d4d15..00000000000
> --- a/gas/testsuite/gas/riscv/zicbop-fail.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv64g_zicbop
> -#source: zicbop-fail.s
> -#error_output: zicbop-fail.l
> diff --git a/gas/testsuite/gas/riscv/zicbop-noarch.d b/gas/testsuite/gas/riscv/zicbop-noarch.d
> new file mode 100644
> index 00000000000..2f51eb9b8d1
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicbop-noarch.d
> @@ -0,0 +1,4 @@
> +#as: -march=rv32i -I$srcdir/$subdir -defsym NOARCH=1
> +#source: zicbop.s
> +#objdump: -d
> +#error_output: zicbop-noarch.l
> diff --git a/gas/testsuite/gas/riscv/zicbop-noarch.l b/gas/testsuite/gas/riscv/zicbop-noarch.l
> new file mode 100644
> index 00000000000..742fedd9009
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicbop-noarch.l
> @@ -0,0 +1,7 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `prefetch\.i \(x1\)', extension `zicbop' required
> +.*: Error: unrecognized opcode `prefetch\.i 0x20\(x1\)', extension `zicbop' required
> +.*: Error: unrecognized opcode `prefetch\.r \(x16\)', extension `zicbop' required
> +.*: Error: unrecognized opcode `prefetch\.r -2048\(x16\)', extension `zicbop' required
> +.*: Error: unrecognized opcode `prefetch\.w \(x31\)', extension `zicbop' required
> +.*: Error: unrecognized opcode `prefetch\.w \+0x7e0\(x31\)', extension `zicbop' required
> diff --git a/gas/testsuite/gas/riscv/zicbop.d b/gas/testsuite/gas/riscv/zicbop.d
> index 056a8a501ff..b19ead39cd6 100644
> --- a/gas/testsuite/gas/riscv/zicbop.d
> +++ b/gas/testsuite/gas/riscv/zicbop.d
> @@ -1,12 +1,14 @@
> -#as: -march=rv64g_zicbop
> -#source: zicbop.s
> -#objdump: -dr
> +#as: -march=rv32i -I$srcdir/$subdir
> +#objdump: -d
>
> .*:[ ]+file format .*
>
> Disassembly of section .text:
>
> 0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+0000e013[ ]+prefetch\.i[ ]+0\(ra\)
> [ ]+[0-9a-f]+:[ ]+0200e013[ ]+prefetch\.i[ ]+32\(ra\)
> +[ ]+[0-9a-f]+:[ ]+00186013[ ]+prefetch\.r[ ]+0\(a6\)
> [ ]+[0-9a-f]+:[ ]+80186013[ ]+prefetch\.r[ ]+-2048\(a6\)
> +[ ]+[0-9a-f]+:[ ]+003fe013[ ]+prefetch\.w[ ]+0\(t6\)
> [ ]+[0-9a-f]+:[ ]+7e3fe013[ ]+prefetch\.w[ ]+2016\(t6\)
> diff --git a/gas/testsuite/gas/riscv/zicbop.s b/gas/testsuite/gas/riscv/zicbop.s
> index ffe2014be6f..698bb5d0d8e 100644
> --- a/gas/testsuite/gas/riscv/zicbop.s
> +++ b/gas/testsuite/gas/riscv/zicbop.s
> @@ -1,4 +1,11 @@
> +.include "testutils.inc"
> +
> target:
> + SET_ARCH_START +zicbop
> + prefetch.i (x1)
> prefetch.i 0x20(x1)
> + prefetch.r (x16)
> prefetch.r -2048(x16)
> + prefetch.w (x31)
> prefetch.w +0x7e0(x31)
> + SET_ARCH_END
This is only one extension needed to add, so don't need the mapping symbols.
> --
> 2.37.2
>
next prev parent reply other threads:[~2022-11-29 8:51 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
2022-11-05 12:29 ` [PATCH 01/12] RISC-V: Remove unnecessary empty matching file Tsukasa OI
2022-11-29 7:38 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 02/12] RISC-V: Tidy disassembler corner case tests Tsukasa OI
2022-11-29 7:48 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 03/12] RISC-V: Tidying related to 'Zfinx' disassembler test Tsukasa OI
2022-11-29 7:50 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 04/12] RISC-V: GAS: Add basic shared test utilities Tsukasa OI
2022-11-29 7:53 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 05/12] RISC-V: Redefine "nop" test Tsukasa OI
2022-11-29 7:58 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 06/12] RISC-V: Reorganize/enhance {sign,zero}-extension instructions Tsukasa OI
2022-11-29 8:10 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 07/12] RISC-V: Combine complex extension error handling tests Tsukasa OI
2022-11-29 8:16 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 08/12] RISC-V: Refine/enhance 'M'/'Zmmul' extension tests Tsukasa OI
2022-11-29 8:23 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 09/12] RISC-V: Combine/enhance 'Zicbo[mz]' " Tsukasa OI
2022-11-29 8:38 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 10/12] RISC-V: Enhance 'Zicbop' testcases Tsukasa OI
2022-11-29 8:51 ` Nelson Chu [this message]
2022-11-05 12:29 ` [PATCH 11/12] RISC-V: Reorganize/enhance 'Zb*' extension tests Tsukasa OI
2022-11-29 8:57 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 12/12] RISC-V: Combine/enhance 'Zk*'/'Zbk*' " Tsukasa OI
2022-11-29 9:00 ` Nelson Chu
2022-11-20 2:28 ` [PING^1][PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
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