From: Nelson Chu <nelson@rivosinc.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
binutils@sourceware.org
Subject: Re: [PATCH 06/12] RISC-V: Reorganize/enhance {sign,zero}-extension instructions
Date: Tue, 29 Nov 2022 16:10:11 +0800 [thread overview]
Message-ID: <CAPpQWtAz3+i1hVa79rfVxVz7PQs95wXHZZYdmnbW6OUBxTyzyA@mail.gmail.com> (raw)
In-Reply-To: <7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com>
This is not what I expected... What I expect is that we just have a
.s file for those instructions, and then just use ".option arch" to
generate the mapping symbols to let dis-assembler dumps the right
things. Although you may think that rv32 and rv64 in the same file
looks weird, but according to the purpose of the .option arch, this
should be allowed, so... From my side, you are not tidying the test
cases, defining lots of symbols by -defsym and macros by *.inc file
make things more complicated. What I worry is that except you, it's
too complicated for others to add test cases, so your new rules aren't
convenient, it not only increases the difficulty for everyone to
develop, but also increases the cost of maintenance... So again, I
disagree and suggest not to add these kinds of support.
Nelson
On Sat, Nov 5, 2022 at 8:30 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> This commit:
>
> - Clarifies the roles of {sign,zero}-extension instruction tests,
> - Shortens ".s" file using macro,
> - Enhances the tests with 'Zba' and 'Zbb' extensions and
> - Makes some tidying (e.g. making matching patterns stricter).
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/ext-insn.s: Reorganize based on ext.s.
> * testsuite/gas/riscv/ext-insn-32-noalias.d: Based on ext-32.d.
> Make matching pattern stricter.
> * testsuite/gas/riscv/ext-insn-64-noalias.d: Based on ext-64.d.
> Make matching pattern stricter.
> * testsuite/gas/riscv/ext-insn-32-noarch.d: New failure test.
> * testsuite/gas/riscv/ext-insn-32-noarch.l: Likewise.
> * testsuite/gas/riscv/ext-insn-64-noarch.d: New test to make sure
> that NOARCH=1 does not make errors since all opcodes are valid.
> * testsuite/gas/riscv/ext-insn-zba-32-noalias.d: Test with 'Zba'.
> * testsuite/gas/riscv/ext-insn-zba-64-noalias.d: Likewise.
> * testsuite/gas/riscv/ext-insn-zbb-32-noalias.d: Test with 'Zbb'.
> * testsuite/gas/riscv/ext-insn-zbb-64-noalias.d: Likewise.
> * testsuite/gas/riscv/ext.s: Removed.
> * testsuite/gas/riscv/ext-32.d: Removed.
> * testsuite/gas/riscv/ext-64.d: Removed.
> ---
> gas/testsuite/gas/riscv/ext-32.d | 39 --------------
> gas/testsuite/gas/riscv/ext-64.d | 51 -------------------
> gas/testsuite/gas/riscv/ext-insn-32-noalias.d | 39 ++++++++++++++
> gas/testsuite/gas/riscv/ext-insn-32-noarch.d | 3 ++
> gas/testsuite/gas/riscv/ext-insn-32-noarch.l | 9 ++++
> gas/testsuite/gas/riscv/ext-insn-64-noalias.d | 51 +++++++++++++++++++
> gas/testsuite/gas/riscv/ext-insn-64-noarch.d | 5 ++
> .../gas/riscv/ext-insn-zba-32-noalias.d | 39 ++++++++++++++
> .../gas/riscv/ext-insn-zba-64-noalias.d | 47 +++++++++++++++++
> .../gas/riscv/ext-insn-zbb-32-noalias.d | 27 ++++++++++
> .../gas/riscv/ext-insn-zbb-64-noalias.d | 39 ++++++++++++++
> gas/testsuite/gas/riscv/ext-insn.s | 23 +++++++++
> gas/testsuite/gas/riscv/ext.s | 38 --------------
> 13 files changed, 282 insertions(+), 128 deletions(-)
> delete mode 100644 gas/testsuite/gas/riscv/ext-32.d
> delete mode 100644 gas/testsuite/gas/riscv/ext-64.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-32-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-32-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-32-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-64-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-64-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-zba-32-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-zba-64-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-zbb-32-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-zbb-64-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn.s
> delete mode 100644 gas/testsuite/gas/riscv/ext.s
>
> diff --git a/gas/testsuite/gas/riscv/ext-32.d b/gas/testsuite/gas/riscv/ext-32.d
> deleted file mode 100644
> index 97daa31d0e9..00000000000
> --- a/gas/testsuite/gas/riscv/ext-32.d
> +++ /dev/null
> @@ -1,39 +0,0 @@
> -#as: -march=rv32i
> -#source: ext.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+0:[ ]+0ff57513[ ]+zext.b[ ]+a0,a0
> -[ ]+4:[ ]+01051513[ ]+sll[ ]+a0,a0,0x10
> -[ ]+8:[ ]+01055513[ ]+srl[ ]+a0,a0,0x10
> -[ ]+c:[ ]+01851513[ ]+sll[ ]+a0,a0,0x18
> -[ ]+10:[ ]+41855513[ ]+sra[ ]+a0,a0,0x18
> -[ ]+14:[ ]+01051513[ ]+sll[ ]+a0,a0,0x10
> -[ ]+18:[ ]+41055513[ ]+sra[ ]+a0,a0,0x10
> -[ ]+1c:[ ]+0ff67593[ ]+zext.b[ ]+a1,a2
> -[ ]+20:[ ]+01061593[ ]+sll[ ]+a1,a2,0x10
> -[ ]+24:[ ]+0105d593[ ]+srl[ ]+a1,a1,0x10
> -[ ]+28:[ ]+01861593[ ]+sll[ ]+a1,a2,0x18
> -[ ]+2c:[ ]+4185d593[ ]+sra[ ]+a1,a1,0x18
> -[ ]+30:[ ]+01061593[ ]+sll[ ]+a1,a2,0x10
> -[ ]+34:[ ]+4105d593[ ]+sra[ ]+a1,a1,0x10
> -[ ]+38:[ ]+0ff57513[ ]+zext.b[ ]+a0,a0
> -[ ]+3c:[ ]+0542[ ]+sll[ ]+a0,a0,0x10
> -[ ]+3e:[ ]+8141[ ]+srl[ ]+a0,a0,0x10
> -[ ]+40:[ ]+0562[ ]+sll[ ]+a0,a0,0x18
> -[ ]+42:[ ]+8561[ ]+sra[ ]+a0,a0,0x18
> -[ ]+44:[ ]+0542[ ]+sll[ ]+a0,a0,0x10
> -[ ]+46:[ ]+8541[ ]+sra[ ]+a0,a0,0x10
> -[ ]+48:[ ]+0ff67593[ ]+zext.b[ ]+a1,a2
> -[ ]+4c:[ ]+01061593[ ]+sll[ ]+a1,a2,0x10
> -[ ]+50:[ ]+81c1[ ]+srl[ ]+a1,a1,0x10
> -[ ]+52:[ ]+01861593[ ]+sll[ ]+a1,a2,0x18
> -[ ]+56:[ ]+85e1[ ]+sra[ ]+a1,a1,0x18
> -[ ]+58:[ ]+01061593[ ]+sll[ ]+a1,a2,0x10
> -[ ]+5c:[ ]+85c1[ ]+sra[ ]+a1,a1,0x10
> -#...
> diff --git a/gas/testsuite/gas/riscv/ext-64.d b/gas/testsuite/gas/riscv/ext-64.d
> deleted file mode 100644
> index 1fe339c4af4..00000000000
> --- a/gas/testsuite/gas/riscv/ext-64.d
> +++ /dev/null
> @@ -1,51 +0,0 @@
> -#as: -march=rv64i -defsym __64_bit__=1
> -#source: ext.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+0:[ ]+0ff57513[ ]+zext.b[ ]+a0,a0
> -[ ]+4:[ ]+03051513[ ]+sll[ ]+a0,a0,0x30
> -[ ]+8:[ ]+03055513[ ]+srl[ ]+a0,a0,0x30
> -[ ]+c:[ ]+03851513[ ]+sll[ ]+a0,a0,0x38
> -[ ]+10:[ ]+43855513[ ]+sra[ ]+a0,a0,0x38
> -[ ]+14:[ ]+03051513[ ]+sll[ ]+a0,a0,0x30
> -[ ]+18:[ ]+43055513[ ]+sra[ ]+a0,a0,0x30
> -[ ]+1c:[ ]+0ff67593[ ]+zext.b[ ]+a1,a2
> -[ ]+20:[ ]+03061593[ ]+sll[ ]+a1,a2,0x30
> -[ ]+24:[ ]+0305d593[ ]+srl[ ]+a1,a1,0x30
> -[ ]+28:[ ]+03861593[ ]+sll[ ]+a1,a2,0x38
> -[ ]+2c:[ ]+4385d593[ ]+sra[ ]+a1,a1,0x38
> -[ ]+30:[ ]+03061593[ ]+sll[ ]+a1,a2,0x30
> -[ ]+34:[ ]+4305d593[ ]+sra[ ]+a1,a1,0x30
> -[ ]+38:[ ]+02051513[ ]+sll[ ]+a0,a0,0x20
> -[ ]+3c:[ ]+02055513[ ]+srl[ ]+a0,a0,0x20
> -[ ]+40:[ ]+0005051b[ ]+sext.w[ ]+a0,a0
> -[ ]+44:[ ]+02061593[ ]+sll[ ]+a1,a2,0x20
> -[ ]+48:[ ]+0205d593[ ]+srl[ ]+a1,a1,0x20
> -[ ]+4c:[ ]+0006059b[ ]+sext.w[ ]+a1,a2
> -[ ]+50:[ ]+0ff57513[ ]+zext.b[ ]+a0,a0
> -[ ]+54:[ ]+1542[ ]+sll[ ]+a0,a0,0x30
> -[ ]+56:[ ]+9141[ ]+srl[ ]+a0,a0,0x30
> -[ ]+58:[ ]+1562[ ]+sll[ ]+a0,a0,0x38
> -[ ]+5a:[ ]+9561[ ]+sra[ ]+a0,a0,0x38
> -[ ]+5c:[ ]+1542[ ]+sll[ ]+a0,a0,0x30
> -[ ]+5e:[ ]+9541[ ]+sra[ ]+a0,a0,0x30
> -[ ]+60:[ ]+0ff67593[ ]+zext.b[ ]+a1,a2
> -[ ]+64:[ ]+03061593[ ]+sll[ ]+a1,a2,0x30
> -[ ]+68:[ ]+91c1[ ]+srl[ ]+a1,a1,0x30
> -[ ]+6a:[ ]+03861593[ ]+sll[ ]+a1,a2,0x38
> -[ ]+6e:[ ]+95e1[ ]+sra[ ]+a1,a1,0x38
> -[ ]+70:[ ]+03061593[ ]+sll[ ]+a1,a2,0x30
> -[ ]+74:[ ]+95c1[ ]+sra[ ]+a1,a1,0x30
> -[ ]+76:[ ]+1502[ ]+sll[ ]+a0,a0,0x20
> -[ ]+78:[ ]+9101[ ]+srl[ ]+a0,a0,0x20
> -[ ]+7a:[ ]+2501[ ]+sext.w[ ]+a0,a0
> -[ ]+7c:[ ]+02061593[ ]+sll[ ]+a1,a2,0x20
> -[ ]+80:[ ]+9181[ ]+srl[ ]+a1,a1,0x20
> -[ ]+82:[ ]+0006059b[ ]+sext.w[ ]+a1,a2
> -#...
> diff --git a/gas/testsuite/gas/riscv/ext-insn-32-noalias.d b/gas/testsuite/gas/riscv/ext-insn-32-noalias.d
> new file mode 100644
> index 00000000000..237fcf033d0
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn-32-noalias.d
> @@ -0,0 +1,39 @@
> +#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32
> +#source: ext-insn.s
> +#objdump: -d -M no-aliases
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+01051513[ ]+slli[ ]+a0,a0,0x10
> +[ ]+[0-9a-f]+:[ ]+01055513[ ]+srli[ ]+a0,a0,0x10
> +[ ]+[0-9a-f]+:[ ]+01851513[ ]+slli[ ]+a0,a0,0x18
> +[ ]+[0-9a-f]+:[ ]+41855513[ ]+srai[ ]+a0,a0,0x18
> +[ ]+[0-9a-f]+:[ ]+01051513[ ]+slli[ ]+a0,a0,0x10
> +[ ]+[0-9a-f]+:[ ]+41055513[ ]+srai[ ]+a0,a0,0x10
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
> +[ ]+[0-9a-f]+:[ ]+0105d593[ ]+srli[ ]+a1,a1,0x10
> +[ ]+[0-9a-f]+:[ ]+01861593[ ]+slli[ ]+a1,a2,0x18
> +[ ]+[0-9a-f]+:[ ]+4185d593[ ]+srai[ ]+a1,a1,0x18
> +[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
> +[ ]+[0-9a-f]+:[ ]+4105d593[ ]+srai[ ]+a1,a1,0x10
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+0542[ ]+c\.slli[ ]+a0,0x10
> +[ ]+[0-9a-f]+:[ ]+8141[ ]+c\.srli[ ]+a0,0x10
> +[ ]+[0-9a-f]+:[ ]+0562[ ]+c\.slli[ ]+a0,0x18
> +[ ]+[0-9a-f]+:[ ]+8561[ ]+c\.srai[ ]+a0,0x18
> +[ ]+[0-9a-f]+:[ ]+0542[ ]+c\.slli[ ]+a0,0x10
> +[ ]+[0-9a-f]+:[ ]+8541[ ]+c\.srai[ ]+a0,0x10
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
> +[ ]+[0-9a-f]+:[ ]+81c1[ ]+c\.srli[ ]+a1,0x10
> +[ ]+[0-9a-f]+:[ ]+01861593[ ]+slli[ ]+a1,a2,0x18
> +[ ]+[0-9a-f]+:[ ]+85e1[ ]+c\.srai[ ]+a1,0x18
> +[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
> +[ ]+[0-9a-f]+:[ ]+85c1[ ]+c\.srai[ ]+a1,0x10
> +#...
> diff --git a/gas/testsuite/gas/riscv/ext-insn-32-noarch.d b/gas/testsuite/gas/riscv/ext-insn-32-noarch.d
> new file mode 100644
> index 00000000000..7a2f4ddfec2
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn-32-noarch.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32 -defsym NOARCH=1
> +#source: ext-insn.s
> +#error_output: ext-insn-32-noarch.l
> diff --git a/gas/testsuite/gas/riscv/ext-insn-32-noarch.l b/gas/testsuite/gas/riscv/ext-insn-32-noarch.l
> new file mode 100644
> index 00000000000..f5954f207f0
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn-32-noarch.l
> @@ -0,0 +1,9 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `zext.w a0,a0'
> +.*: Error: unrecognized opcode `sext.w a0,a0'
> +.*: Error: unrecognized opcode `zext.w a1,a2'
> +.*: Error: unrecognized opcode `sext.w a1,a2'
> +.*: Error: unrecognized opcode `zext.w a0,a0'
> +.*: Error: unrecognized opcode `sext.w a0,a0'
> +.*: Error: unrecognized opcode `zext.w a1,a2'
> +.*: Error: unrecognized opcode `sext.w a1,a2'
> diff --git a/gas/testsuite/gas/riscv/ext-insn-64-noalias.d b/gas/testsuite/gas/riscv/ext-insn-64-noalias.d
> new file mode 100644
> index 00000000000..9a273eea0d7
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn-64-noalias.d
> @@ -0,0 +1,51 @@
> +#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64
> +#source: ext-insn.s
> +#objdump: -d -M no-aliases
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+03051513[ ]+slli[ ]+a0,a0,0x30
> +[ ]+[0-9a-f]+:[ ]+03055513[ ]+srli[ ]+a0,a0,0x30
> +[ ]+[0-9a-f]+:[ ]+03851513[ ]+slli[ ]+a0,a0,0x38
> +[ ]+[0-9a-f]+:[ ]+43855513[ ]+srai[ ]+a0,a0,0x38
> +[ ]+[0-9a-f]+:[ ]+03051513[ ]+slli[ ]+a0,a0,0x30
> +[ ]+[0-9a-f]+:[ ]+43055513[ ]+srai[ ]+a0,a0,0x30
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
> +[ ]+[0-9a-f]+:[ ]+0305d593[ ]+srli[ ]+a1,a1,0x30
> +[ ]+[0-9a-f]+:[ ]+03861593[ ]+slli[ ]+a1,a2,0x38
> +[ ]+[0-9a-f]+:[ ]+4385d593[ ]+srai[ ]+a1,a1,0x38
> +[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
> +[ ]+[0-9a-f]+:[ ]+4305d593[ ]+srai[ ]+a1,a1,0x30
> +[ ]+[0-9a-f]+:[ ]+02051513[ ]+slli[ ]+a0,a0,0x20
> +[ ]+[0-9a-f]+:[ ]+02055513[ ]+srli[ ]+a0,a0,0x20
> +[ ]+[0-9a-f]+:[ ]+0005051b[ ]+addiw[ ]+a0,a0,0
> +[ ]+[0-9a-f]+:[ ]+02061593[ ]+slli[ ]+a1,a2,0x20
> +[ ]+[0-9a-f]+:[ ]+0205d593[ ]+srli[ ]+a1,a1,0x20
> +[ ]+[0-9a-f]+:[ ]+0006059b[ ]+addiw[ ]+a1,a2,0
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+1542[ ]+c\.slli[ ]+a0,0x30
> +[ ]+[0-9a-f]+:[ ]+9141[ ]+c\.srli[ ]+a0,0x30
> +[ ]+[0-9a-f]+:[ ]+1562[ ]+c\.slli[ ]+a0,0x38
> +[ ]+[0-9a-f]+:[ ]+9561[ ]+c\.srai[ ]+a0,0x38
> +[ ]+[0-9a-f]+:[ ]+1542[ ]+c\.slli[ ]+a0,0x30
> +[ ]+[0-9a-f]+:[ ]+9541[ ]+c\.srai[ ]+a0,0x30
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
> +[ ]+[0-9a-f]+:[ ]+91c1[ ]+c\.srli[ ]+a1,0x30
> +[ ]+[0-9a-f]+:[ ]+03861593[ ]+slli[ ]+a1,a2,0x38
> +[ ]+[0-9a-f]+:[ ]+95e1[ ]+c\.srai[ ]+a1,0x38
> +[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
> +[ ]+[0-9a-f]+:[ ]+95c1[ ]+c\.srai[ ]+a1,0x30
> +[ ]+[0-9a-f]+:[ ]+1502[ ]+c\.slli[ ]+a0,0x20
> +[ ]+[0-9a-f]+:[ ]+9101[ ]+c\.srli[ ]+a0,0x20
> +[ ]+[0-9a-f]+:[ ]+2501[ ]+c\.addiw[ ]+a0,0
> +[ ]+[0-9a-f]+:[ ]+02061593[ ]+slli[ ]+a1,a2,0x20
> +[ ]+[0-9a-f]+:[ ]+9181[ ]+c\.srli[ ]+a1,0x20
> +[ ]+[0-9a-f]+:[ ]+0006059b[ ]+addiw[ ]+a1,a2,0
> +#...
> diff --git a/gas/testsuite/gas/riscv/ext-insn-64-noarch.d b/gas/testsuite/gas/riscv/ext-insn-64-noarch.d
> new file mode 100644
> index 00000000000..6061373bb71
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn-64-noarch.d
> @@ -0,0 +1,5 @@
> +#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64 -defsym NOARCH=1
> +#source: ext-insn.s
> +#objdump: -d -M no-aliases
> +
> +#...
> diff --git a/gas/testsuite/gas/riscv/ext-insn-zba-32-noalias.d b/gas/testsuite/gas/riscv/ext-insn-zba-32-noalias.d
> new file mode 100644
> index 00000000000..ccea949debc
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn-zba-32-noalias.d
> @@ -0,0 +1,39 @@
> +#as: -march=rv32i_zba -I$srcdir/$subdir -defsym XLEN=32
> +#source: ext-insn.s
> +#objdump: -d -M no-aliases
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+01051513[ ]+slli[ ]+a0,a0,0x10
> +[ ]+[0-9a-f]+:[ ]+01055513[ ]+srli[ ]+a0,a0,0x10
> +[ ]+[0-9a-f]+:[ ]+01851513[ ]+slli[ ]+a0,a0,0x18
> +[ ]+[0-9a-f]+:[ ]+41855513[ ]+srai[ ]+a0,a0,0x18
> +[ ]+[0-9a-f]+:[ ]+01051513[ ]+slli[ ]+a0,a0,0x10
> +[ ]+[0-9a-f]+:[ ]+41055513[ ]+srai[ ]+a0,a0,0x10
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
> +[ ]+[0-9a-f]+:[ ]+0105d593[ ]+srli[ ]+a1,a1,0x10
> +[ ]+[0-9a-f]+:[ ]+01861593[ ]+slli[ ]+a1,a2,0x18
> +[ ]+[0-9a-f]+:[ ]+4185d593[ ]+srai[ ]+a1,a1,0x18
> +[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
> +[ ]+[0-9a-f]+:[ ]+4105d593[ ]+srai[ ]+a1,a1,0x10
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+0542[ ]+c\.slli[ ]+a0,0x10
> +[ ]+[0-9a-f]+:[ ]+8141[ ]+c\.srli[ ]+a0,0x10
> +[ ]+[0-9a-f]+:[ ]+0562[ ]+c\.slli[ ]+a0,0x18
> +[ ]+[0-9a-f]+:[ ]+8561[ ]+c\.srai[ ]+a0,0x18
> +[ ]+[0-9a-f]+:[ ]+0542[ ]+c\.slli[ ]+a0,0x10
> +[ ]+[0-9a-f]+:[ ]+8541[ ]+c\.srai[ ]+a0,0x10
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
> +[ ]+[0-9a-f]+:[ ]+81c1[ ]+c\.srli[ ]+a1,0x10
> +[ ]+[0-9a-f]+:[ ]+01861593[ ]+slli[ ]+a1,a2,0x18
> +[ ]+[0-9a-f]+:[ ]+85e1[ ]+c\.srai[ ]+a1,0x18
> +[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
> +[ ]+[0-9a-f]+:[ ]+85c1[ ]+c\.srai[ ]+a1,0x10
> +#...
> diff --git a/gas/testsuite/gas/riscv/ext-insn-zba-64-noalias.d b/gas/testsuite/gas/riscv/ext-insn-zba-64-noalias.d
> new file mode 100644
> index 00000000000..a9e191a7449
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn-zba-64-noalias.d
> @@ -0,0 +1,47 @@
> +#as: -march=rv64i_zba -I$srcdir/$subdir -defsym XLEN=64
> +#source: ext-insn.s
> +#objdump: -d -M no-aliases
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+03051513[ ]+slli[ ]+a0,a0,0x30
> +[ ]+[0-9a-f]+:[ ]+03055513[ ]+srli[ ]+a0,a0,0x30
> +[ ]+[0-9a-f]+:[ ]+03851513[ ]+slli[ ]+a0,a0,0x38
> +[ ]+[0-9a-f]+:[ ]+43855513[ ]+srai[ ]+a0,a0,0x38
> +[ ]+[0-9a-f]+:[ ]+03051513[ ]+slli[ ]+a0,a0,0x30
> +[ ]+[0-9a-f]+:[ ]+43055513[ ]+srai[ ]+a0,a0,0x30
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
> +[ ]+[0-9a-f]+:[ ]+0305d593[ ]+srli[ ]+a1,a1,0x30
> +[ ]+[0-9a-f]+:[ ]+03861593[ ]+slli[ ]+a1,a2,0x38
> +[ ]+[0-9a-f]+:[ ]+4385d593[ ]+srai[ ]+a1,a1,0x38
> +[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
> +[ ]+[0-9a-f]+:[ ]+4305d593[ ]+srai[ ]+a1,a1,0x30
> +[ ]+[0-9a-f]+:[ ]+0805053b[ ]+add\.uw[ ]+a0,a0,zero
> +[ ]+[0-9a-f]+:[ ]+0005051b[ ]+addiw[ ]+a0,a0,0
> +[ ]+[0-9a-f]+:[ ]+080605bb[ ]+add\.uw[ ]+a1,a2,zero
> +[ ]+[0-9a-f]+:[ ]+0006059b[ ]+addiw[ ]+a1,a2,0
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+1542[ ]+c\.slli[ ]+a0,0x30
> +[ ]+[0-9a-f]+:[ ]+9141[ ]+c\.srli[ ]+a0,0x30
> +[ ]+[0-9a-f]+:[ ]+1562[ ]+c\.slli[ ]+a0,0x38
> +[ ]+[0-9a-f]+:[ ]+9561[ ]+c\.srai[ ]+a0,0x38
> +[ ]+[0-9a-f]+:[ ]+1542[ ]+c\.slli[ ]+a0,0x30
> +[ ]+[0-9a-f]+:[ ]+9541[ ]+c\.srai[ ]+a0,0x30
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
> +[ ]+[0-9a-f]+:[ ]+91c1[ ]+c\.srli[ ]+a1,0x30
> +[ ]+[0-9a-f]+:[ ]+03861593[ ]+slli[ ]+a1,a2,0x38
> +[ ]+[0-9a-f]+:[ ]+95e1[ ]+c\.srai[ ]+a1,0x38
> +[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
> +[ ]+[0-9a-f]+:[ ]+95c1[ ]+c\.srai[ ]+a1,0x30
> +[ ]+[0-9a-f]+:[ ]+0805053b[ ]+add\.uw[ ]+a0,a0,zero
> +[ ]+[0-9a-f]+:[ ]+2501[ ]+c\.addiw[ ]+a0,0
> +[ ]+[0-9a-f]+:[ ]+080605bb[ ]+add\.uw[ ]+a1,a2,zero
> +[ ]+[0-9a-f]+:[ ]+0006059b[ ]+addiw[ ]+a1,a2,0
> +#...
> diff --git a/gas/testsuite/gas/riscv/ext-insn-zbb-32-noalias.d b/gas/testsuite/gas/riscv/ext-insn-zbb-32-noalias.d
> new file mode 100644
> index 00000000000..edb2dcde2cf
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn-zbb-32-noalias.d
> @@ -0,0 +1,27 @@
> +#as: -march=rv32i_zbb -I$srcdir/$subdir -defsym XLEN=32
> +#source: ext-insn.s
> +#objdump: -d -M no-aliases
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+08054533[ ]+zext\.h[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+60451513[ ]+sext\.b[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+60551513[ ]+sext\.h[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+080645b3[ ]+zext\.h[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+60461593[ ]+sext\.b[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+60561593[ ]+sext\.h[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+08054533[ ]+zext\.h[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+60451513[ ]+sext\.b[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+60551513[ ]+sext\.h[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+080645b3[ ]+zext\.h[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+60461593[ ]+sext\.b[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+60561593[ ]+sext\.h[ ]+a1,a2
> +#...
> diff --git a/gas/testsuite/gas/riscv/ext-insn-zbb-64-noalias.d b/gas/testsuite/gas/riscv/ext-insn-zbb-64-noalias.d
> new file mode 100644
> index 00000000000..bc7b6145e59
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn-zbb-64-noalias.d
> @@ -0,0 +1,39 @@
> +#as: -march=rv64i_zbb -I$srcdir/$subdir -defsym XLEN=64
> +#source: ext-insn.s
> +#objdump: -d -M no-aliases
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+0805453b[ ]+zext\.h[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+60451513[ ]+sext\.b[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+60551513[ ]+sext\.h[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+080645bb[ ]+zext\.h[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+60461593[ ]+sext\.b[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+60561593[ ]+sext\.h[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+02051513[ ]+slli[ ]+a0,a0,0x20
> +[ ]+[0-9a-f]+:[ ]+02055513[ ]+srli[ ]+a0,a0,0x20
> +[ ]+[0-9a-f]+:[ ]+0005051b[ ]+addiw[ ]+a0,a0,0
> +[ ]+[0-9a-f]+:[ ]+02061593[ ]+slli[ ]+a1,a2,0x20
> +[ ]+[0-9a-f]+:[ ]+0205d593[ ]+srli[ ]+a1,a1,0x20
> +[ ]+[0-9a-f]+:[ ]+0006059b[ ]+addiw[ ]+a1,a2,0
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+0805453b[ ]+zext\.h[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+60451513[ ]+sext\.b[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+60551513[ ]+sext\.h[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+080645bb[ ]+zext\.h[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+60461593[ ]+sext\.b[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+60561593[ ]+sext\.h[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+1502[ ]+c\.slli[ ]+a0,0x20
> +[ ]+[0-9a-f]+:[ ]+9101[ ]+c\.srli[ ]+a0,0x20
> +[ ]+[0-9a-f]+:[ ]+2501[ ]+c\.addiw[ ]+a0,0
> +[ ]+[0-9a-f]+:[ ]+02061593[ ]+slli[ ]+a1,a2,0x20
> +[ ]+[0-9a-f]+:[ ]+9181[ ]+c\.srli[ ]+a1,0x20
> +[ ]+[0-9a-f]+:[ ]+0006059b[ ]+addiw[ ]+a1,a2,0
> +#...
> diff --git a/gas/testsuite/gas/riscv/ext-insn.s b/gas/testsuite/gas/riscv/ext-insn.s
> new file mode 100644
> index 00000000000..2e4dc1ed850
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn.s
> @@ -0,0 +1,23 @@
> +.include "testutils.inc"
> +
> +.macro INSN_SEQ
> + zext.b a0, a0 # andi (I)
> + zext.h a0, a0 # Zbb (RV32!=RV64) / shifts (I/C)
> + sext.b a0, a0 # Zbb / shifts (I/C)
> + sext.h a0, a0 # Zbb / shifts (I/C)
> + zext.b a1, a2 # andi (I)
> + zext.h a1, a2 # Zbb (RV32!=RV64) / shifts (I/C)
> + sext.b a1, a2 # Zbb / shifts (I/C)
> + sext.h a1, a2 # Zbb / shifts (I/C)
> +.if XLEN_GE_64
> + zext.w a0, a0 # add.uw (RV64_Zba) / shifts (I/C)
> + sext.w a0, a0 # addiw (I) / c.addiw (C)
> + zext.w a1, a2 # add.uw (RV64_Zba) / shifts (I/C)
> + sext.w a1, a2 # addiw (I/C)
> +.endif
> +.endm
> +
> +target:
> + INSN_SEQ
> + .option arch, +c
> + INSN_SEQ
> diff --git a/gas/testsuite/gas/riscv/ext.s b/gas/testsuite/gas/riscv/ext.s
> deleted file mode 100644
> index 0268dcafc1d..00000000000
> --- a/gas/testsuite/gas/riscv/ext.s
> +++ /dev/null
> @@ -1,38 +0,0 @@
> -target:
> - .option arch, -c
> - zext.b a0, a0
> - zext.h a0, a0
> - sext.b a0, a0
> - sext.h a0, a0
> -
> - zext.b a1, a2
> - zext.h a1, a2
> - sext.b a1, a2
> - sext.h a1, a2
> -
> -.ifdef __64_bit__
> - zext.w a0, a0
> - sext.w a0, a0
> -
> - zext.w a1, a2
> - sext.w a1, a2
> -.endif
> -
> - .option arch, +c
> - zext.b a0, a0
> - zext.h a0, a0
> - sext.b a0, a0
> - sext.h a0, a0
> -
> - zext.b a1, a2
> - zext.h a1, a2
> - sext.b a1, a2
> - sext.h a1, a2
> -
> -.ifdef __64_bit__
> - zext.w a0, a0
> - sext.w a0, a0
> -
> - zext.w a1, a2
> - sext.w a1, a2
> -.endif
> --
> 2.37.2
>
next prev parent reply other threads:[~2022-11-29 8:10 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
2022-11-05 12:29 ` [PATCH 01/12] RISC-V: Remove unnecessary empty matching file Tsukasa OI
2022-11-29 7:38 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 02/12] RISC-V: Tidy disassembler corner case tests Tsukasa OI
2022-11-29 7:48 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 03/12] RISC-V: Tidying related to 'Zfinx' disassembler test Tsukasa OI
2022-11-29 7:50 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 04/12] RISC-V: GAS: Add basic shared test utilities Tsukasa OI
2022-11-29 7:53 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 05/12] RISC-V: Redefine "nop" test Tsukasa OI
2022-11-29 7:58 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 06/12] RISC-V: Reorganize/enhance {sign,zero}-extension instructions Tsukasa OI
2022-11-29 8:10 ` Nelson Chu [this message]
2022-11-05 12:29 ` [PATCH 07/12] RISC-V: Combine complex extension error handling tests Tsukasa OI
2022-11-29 8:16 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 08/12] RISC-V: Refine/enhance 'M'/'Zmmul' extension tests Tsukasa OI
2022-11-29 8:23 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 09/12] RISC-V: Combine/enhance 'Zicbo[mz]' " Tsukasa OI
2022-11-29 8:38 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 10/12] RISC-V: Enhance 'Zicbop' testcases Tsukasa OI
2022-11-29 8:51 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 11/12] RISC-V: Reorganize/enhance 'Zb*' extension tests Tsukasa OI
2022-11-29 8:57 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 12/12] RISC-V: Combine/enhance 'Zk*'/'Zbk*' " Tsukasa OI
2022-11-29 9:00 ` Nelson Chu
2022-11-20 2:28 ` [PING^1][PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
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