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From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
	Nelson Chu <nelson@rivosinc.com>,
	Kito Cheng <kito.cheng@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH 08/12] RISC-V: Refine/enhance 'M'/'Zmmul' extension tests
Date: Sat,  5 Nov 2022 12:29:14 +0000	[thread overview]
Message-ID: <9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1667651354.git.research_trasio@irq.a4lg.com>

This commit refines tests for 'M' and 'Zmmul' extensions and adds "no
required extension" testcases based on new test utilities.

gas/ChangeLog:

	* testsuite/gas/riscv/m-ext.s: Refine using new testing utils.
	* testsuite/gas/riscv/m-ext-32.d: Refine.
	* testsuite/gas/riscv/m-ext-32-noarch.d: New test.
	* testsuite/gas/riscv/m-ext-32-noarch.l: Likewise.
	* testsuite/gas/riscv/m-ext-32-noarch-m.d: New test ased on
	m-ext-fail-zmmul-32.d but refine.
	* testsuite/gas/riscv/m-ext-32-noarch-m.l: New test ased on
	m-ext-fail-zmmul-32.l.
	* testsuite/gas/riscv/m-ext-64.d: Refine.
	* testsuite/gas/riscv/m-ext-64-noarch.d: New test ased on
	m-ext-fail-noarch-64.d but refine.
	* testsuite/gas/riscv/m-ext-64-noarch.l: New test ased on
	m-ext-fail-noarch-64.l.
	* testsuite/gas/riscv/m-ext-64-noarch-m.d: New test ased on
	m-ext-fail-zmmul-64.d but refine.
	* testsuite/gas/riscv/m-ext-64-noarch-m.l: New test ased on
	m-ext-fail-zmmul-64.l.
	* testsuite/gas/riscv/m-ext-fail-xlen-32.d: Removed.
	* testsuite/gas/riscv/m-ext-fail-xlen-32.l: Removed.
	* testsuite/gas/riscv/m-ext-fail-zmmul-32.d: Removed.
	* testsuite/gas/riscv/m-ext-fail-zmmul-64.d: Removed.
	* testsuite/gas/riscv/m-ext-fail-noarch-64.d: Removed.
	* testsuite/gas/riscv/zmmul-32.d: Removed as duplicate.
	* testsuite/gas/riscv/zmmul-64.d: Removed as duplicate.
---
 gas/testsuite/gas/riscv/m-ext-32-noarch-m.d     |  4 ++++
 ...-ext-fail-zmmul-32.l => m-ext-32-noarch-m.l} |  0
 gas/testsuite/gas/riscv/m-ext-32-noarch.d       |  4 ++++
 gas/testsuite/gas/riscv/m-ext-32-noarch.l       | 14 ++++++++++++++
 gas/testsuite/gas/riscv/m-ext-32.d              |  2 +-
 gas/testsuite/gas/riscv/m-ext-64-noarch-m.d     |  4 ++++
 ...-ext-fail-zmmul-64.l => m-ext-64-noarch-m.l} |  0
 gas/testsuite/gas/riscv/m-ext-64-noarch.d       |  4 ++++
 ...m-ext-fail-noarch-64.l => m-ext-64-noarch.l} |  0
 gas/testsuite/gas/riscv/m-ext-64.d              |  2 +-
 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d  |  4 ----
 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d    |  4 ----
 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l    |  6 ------
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d   |  4 ----
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d   |  4 ----
 gas/testsuite/gas/riscv/m-ext.s                 | 17 +++++++++++------
 gas/testsuite/gas/riscv/zmmul-32.d              | 14 --------------
 gas/testsuite/gas/riscv/zmmul-64.d              | 15 ---------------
 18 files changed, 43 insertions(+), 59 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/m-ext-32-noarch-m.d
 rename gas/testsuite/gas/riscv/{m-ext-fail-zmmul-32.l => m-ext-32-noarch-m.l} (100%)
 create mode 100644 gas/testsuite/gas/riscv/m-ext-32-noarch.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-32-noarch.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext-64-noarch-m.d
 rename gas/testsuite/gas/riscv/{m-ext-fail-zmmul-64.l => m-ext-64-noarch-m.l} (100%)
 create mode 100644 gas/testsuite/gas/riscv/m-ext-64-noarch.d
 rename gas/testsuite/gas/riscv/{m-ext-fail-noarch-64.l => m-ext-64-noarch.l} (100%)
 delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
 delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
 delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
 delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
 delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
 delete mode 100644 gas/testsuite/gas/riscv/zmmul-32.d
 delete mode 100644 gas/testsuite/gas/riscv/zmmul-64.d

diff --git a/gas/testsuite/gas/riscv/m-ext-32-noarch-m.d b/gas/testsuite/gas/riscv/m-ext-32-noarch-m.d
new file mode 100644
index 00000000000..1d05564125f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-32-noarch-m.d
@@ -0,0 +1,4 @@
+#as: -march=rv32i_zmmul -I$srcdir/$subdir -defsym XLEN=32 -defsym NOARCH_ARCH=1
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-32-noarch-m.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l b/gas/testsuite/gas/riscv/m-ext-32-noarch-m.l
similarity index 100%
rename from gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
rename to gas/testsuite/gas/riscv/m-ext-32-noarch-m.l
diff --git a/gas/testsuite/gas/riscv/m-ext-32-noarch.d b/gas/testsuite/gas/riscv/m-ext-32-noarch.d
new file mode 100644
index 00000000000..a708d429ac7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-32-noarch.d
@@ -0,0 +1,4 @@
+#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32 -defsym NOARCH=1
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-32-noarch.l
diff --git a/gas/testsuite/gas/riscv/m-ext-32-noarch.l b/gas/testsuite/gas/riscv/m-ext-32-noarch.l
new file mode 100644
index 00000000000..f9179f45bb4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-32-noarch.l
@@ -0,0 +1,14 @@
+.*Assembler messages:
+.*: Error: unrecognized opcode `mul a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `mulh a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `mulhsu a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `mulhu a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `div a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `rem a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `mulw a0,a1,a2'
+.*: Error: unrecognized opcode `divw a0,a1,a2'
+.*: Error: unrecognized opcode `divuw a0,a1,a2'
+.*: Error: unrecognized opcode `remw a0,a1,a2'
+.*: Error: unrecognized opcode `remuw a0,a1,a2'
diff --git a/gas/testsuite/gas/riscv/m-ext-32.d b/gas/testsuite/gas/riscv/m-ext-32.d
index fe2ef9af54b..02be2ef9569 100644
--- a/gas/testsuite/gas/riscv/m-ext-32.d
+++ b/gas/testsuite/gas/riscv/m-ext-32.d
@@ -1,4 +1,4 @@
-#as: -march=rv32im
+#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32
 #source: m-ext.s
 #objdump: -d
 
diff --git a/gas/testsuite/gas/riscv/m-ext-64-noarch-m.d b/gas/testsuite/gas/riscv/m-ext-64-noarch-m.d
new file mode 100644
index 00000000000..d74fbd0b682
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-64-noarch-m.d
@@ -0,0 +1,4 @@
+#as: -march=rv64i_zmmul -I$srcdir/$subdir -defsym XLEN=64 -defsym NOARCH_ARCH=1
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-64-noarch-m.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l b/gas/testsuite/gas/riscv/m-ext-64-noarch-m.l
similarity index 100%
rename from gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l
rename to gas/testsuite/gas/riscv/m-ext-64-noarch-m.l
diff --git a/gas/testsuite/gas/riscv/m-ext-64-noarch.d b/gas/testsuite/gas/riscv/m-ext-64-noarch.d
new file mode 100644
index 00000000000..2d7031e5a35
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-64-noarch.d
@@ -0,0 +1,4 @@
+#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64 -defsym NOARCH=1
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-64-noarch.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l b/gas/testsuite/gas/riscv/m-ext-64-noarch.l
similarity index 100%
rename from gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
rename to gas/testsuite/gas/riscv/m-ext-64-noarch.l
diff --git a/gas/testsuite/gas/riscv/m-ext-64.d b/gas/testsuite/gas/riscv/m-ext-64.d
index 05099b14e9e..ad086829ae5 100644
--- a/gas/testsuite/gas/riscv/m-ext-64.d
+++ b/gas/testsuite/gas/riscv/m-ext-64.d
@@ -1,4 +1,4 @@
-#as: -march=rv64im -defsym rv64=1
+#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64
 #source: m-ext.s
 #objdump: -d
 
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
deleted file mode 100644
index 3c4fc9a0a50..00000000000
--- a/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
+++ /dev/null
@@ -1,4 +0,0 @@
-#as: -march=rv64i -defsym rv64=1
-#source: m-ext.s
-#objdump: -d
-#error_output: m-ext-fail-noarch-64.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
deleted file mode 100644
index 54f8b8225dc..00000000000
--- a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
+++ /dev/null
@@ -1,4 +0,0 @@
-#as: -march=rv32im -defsym rv64=1
-#source: m-ext.s
-#objdump: -d
-#error_output: m-ext-fail-xlen-32.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
deleted file mode 100644
index d65ca4980e6..00000000000
--- a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
+++ /dev/null
@@ -1,6 +0,0 @@
-.*Assembler messages:
-.*: Error: unrecognized opcode `mulw a0,a1,a2'
-.*: Error: unrecognized opcode `divw a0,a1,a2'
-.*: Error: unrecognized opcode `divuw a0,a1,a2'
-.*: Error: unrecognized opcode `remw a0,a1,a2'
-.*: Error: unrecognized opcode `remuw a0,a1,a2'
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
deleted file mode 100644
index c164fa96f8f..00000000000
--- a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
+++ /dev/null
@@ -1,4 +0,0 @@
-#as: -march=rv32i_zmmul
-#source: m-ext.s
-#objdump: -d
-#error_output: m-ext-fail-zmmul-32.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
deleted file mode 100644
index f736d9c66c6..00000000000
--- a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
+++ /dev/null
@@ -1,4 +0,0 @@
-#as: -march=rv64i_zmmul -defsym rv64=1
-#source: m-ext.s
-#objdump: -d
-#error_output: m-ext-fail-zmmul-64.l
diff --git a/gas/testsuite/gas/riscv/m-ext.s b/gas/testsuite/gas/riscv/m-ext.s
index 68baf2ab9c0..8d599f20aef 100644
--- a/gas/testsuite/gas/riscv/m-ext.s
+++ b/gas/testsuite/gas/riscv/m-ext.s
@@ -1,21 +1,26 @@
+.include "testutils.inc"
+
 target:
+	SET_ARCH_START	+zmmul
 	mul	a0, a1, a2
 	mulh	a0, a1, a2
 	mulhsu	a0, a1, a2
 	mulhu	a0, a1, a2
-.ifndef zmmul
+	SET_ARCH_START	+m
 	div	a0, a1, a2
 	divu	a0, a1, a2
 	rem	a0, a1, a2
 	remu	a0, a1, a2
-.endif
-
-.ifdef rv64
+	SET_ARCH_END
+	SET_ARCH_END
+.if	XLEN_GE_64
+	SET_ARCH_START	+zmmul
 	mulw	a0, a1, a2
-.ifndef zmmul
+	SET_ARCH_START	+m
 	divw	a0, a1, a2
 	divuw	a0, a1, a2
 	remw	a0, a1, a2
 	remuw	a0, a1, a2
-.endif
+	SET_ARCH_END
+	SET_ARCH_END
 .endif
diff --git a/gas/testsuite/gas/riscv/zmmul-32.d b/gas/testsuite/gas/riscv/zmmul-32.d
deleted file mode 100644
index c9cf56ab33f..00000000000
--- a/gas/testsuite/gas/riscv/zmmul-32.d
+++ /dev/null
@@ -1,14 +0,0 @@
-#as: -march=rv32im -defsym zmmul=1
-#source: m-ext.s
-#objdump: -d
-
-.*:[ 	]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ 	]+[0-9a-f]+:[ 	]+02c58533[ 	]+mul[  	]+a0,a1,a2
-[ 	]+[0-9a-f]+:[ 	]+02c59533[ 	]+mulh[ 	]+a0,a1,a2
-[ 	]+[0-9a-f]+:[ 	]+02c5a533[ 	]+mulhsu[ 	]+a0,a1,a2
-[ 	]+[0-9a-f]+:[ 	]+02c5b533[ 	]+mulhu[ 	]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zmmul-64.d b/gas/testsuite/gas/riscv/zmmul-64.d
deleted file mode 100644
index 67ef3604755..00000000000
--- a/gas/testsuite/gas/riscv/zmmul-64.d
+++ /dev/null
@@ -1,15 +0,0 @@
-#as: -march=rv64im -defsym zmmul=1 -defsym rv64=1
-#source: m-ext.s
-#objdump: -d
-
-.*:[ 	]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ 	]+[0-9a-f]+:[ 	]+02c58533[ 	]+mul[  	]+a0,a1,a2
-[ 	]+[0-9a-f]+:[ 	]+02c59533[ 	]+mulh[ 	]+a0,a1,a2
-[ 	]+[0-9a-f]+:[ 	]+02c5a533[ 	]+mulhsu[ 	]+a0,a1,a2
-[ 	]+[0-9a-f]+:[ 	]+02c5b533[ 	]+mulhu[ 	]+a0,a1,a2
-[ 	]+[0-9a-f]+:[ 	]+02c5853b[ 	]+mulw[ 	]+a0,a1,a2
-- 
2.37.2


  parent reply	other threads:[~2022-11-05 12:30 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
2022-11-05 12:29 ` [PATCH 01/12] RISC-V: Remove unnecessary empty matching file Tsukasa OI
2022-11-29  7:38   ` Nelson Chu
2022-11-05 12:29 ` [PATCH 02/12] RISC-V: Tidy disassembler corner case tests Tsukasa OI
2022-11-29  7:48   ` Nelson Chu
2022-11-05 12:29 ` [PATCH 03/12] RISC-V: Tidying related to 'Zfinx' disassembler test Tsukasa OI
2022-11-29  7:50   ` Nelson Chu
2022-11-05 12:29 ` [PATCH 04/12] RISC-V: GAS: Add basic shared test utilities Tsukasa OI
2022-11-29  7:53   ` Nelson Chu
2022-11-05 12:29 ` [PATCH 05/12] RISC-V: Redefine "nop" test Tsukasa OI
2022-11-29  7:58   ` Nelson Chu
2022-11-05 12:29 ` [PATCH 06/12] RISC-V: Reorganize/enhance {sign,zero}-extension instructions Tsukasa OI
2022-11-29  8:10   ` Nelson Chu
2022-11-05 12:29 ` [PATCH 07/12] RISC-V: Combine complex extension error handling tests Tsukasa OI
2022-11-29  8:16   ` Nelson Chu
2022-11-05 12:29 ` Tsukasa OI [this message]
2022-11-29  8:23   ` [PATCH 08/12] RISC-V: Refine/enhance 'M'/'Zmmul' extension tests Nelson Chu
2022-11-05 12:29 ` [PATCH 09/12] RISC-V: Combine/enhance 'Zicbo[mz]' " Tsukasa OI
2022-11-29  8:38   ` Nelson Chu
2022-11-05 12:29 ` [PATCH 10/12] RISC-V: Enhance 'Zicbop' testcases Tsukasa OI
2022-11-29  8:51   ` Nelson Chu
2022-11-05 12:29 ` [PATCH 11/12] RISC-V: Reorganize/enhance 'Zb*' extension tests Tsukasa OI
2022-11-29  8:57   ` Nelson Chu
2022-11-05 12:29 ` [PATCH 12/12] RISC-V: Combine/enhance 'Zk*'/'Zbk*' " Tsukasa OI
2022-11-29  9:00   ` Nelson Chu
2022-11-20  2:28 ` [PING^1][PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI

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