* [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren)
@ 2022-02-09 2:29 Tsukasa OI
2022-02-09 2:29 ` [PATCH 1/5] RISC-V: Add mininal support for Zicbo[mpz] Tsukasa OI
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Tsukasa OI @ 2022-02-09 2:29 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This patchset is a modified version of:
<https://sourceware.org/pipermail/binutils/2021-December/118909.html>
GitHub:
<https://github.com/a4lg/binutils-gdb/tree/riscv-CMOs> (original; 2021-12-16, rebased)
<https://github.com/a4lg/binutils-gdb/tree/riscv-CMOs-with-paren> (new: 2022-02-09)
There seems a discussion to change operand of cbo.* instructions on:
<https://github.com/riscv/riscv-CMOs/issues/47>.
I have a little preference for old one but it's not bad to have both
options (as complete patchsets).
Note that however, the original patchset is *NOT OUTDATED* yet.
It implements Zicbom/Zicboz instruction like:
cbo.zero a0
This new patchset implements Zicbom/Zicboz instructions like:
cbo.zero (a0)
cbo.zero 0(a0) # only zero is allowed
Actually, my first attempt to implement cbo.* instructions used the same
format as *new* patchset (I modified before submitting the first
patchset for compliance to the specification document).
This version requires extra checking (0(a0) actually allows
EXPRESSION_RESULTS_IN_ZERO(a0)) so I added a few extra tests.
It will also reject operand format in older patchset.
Old patchset and new patchset are mutually exclusive and should follow
the conclusion of the discussion above.
Thanks,
Tsukasa
Tsukasa OI (5):
RISC-V: Add mininal support for Zicbo[mpz]
RISC-V: Cache management instructions
RISC-V: Cache management instruction testcases
RISC-V: Prefetch hint instructions and operand set
RISC-V: Prefetch hint instruction testcases
bfd/elfxx-riscv.c | 9 +++++++++
gas/config/tc-riscv.c | 18 ++++++++++++++++++
gas/testsuite/gas/riscv/zicbom-fail.d | 3 +++
gas/testsuite/gas/riscv/zicbom-fail.l | 7 +++++++
gas/testsuite/gas/riscv/zicbom-fail.s | 7 +++++++
gas/testsuite/gas/riscv/zicbom.d | 15 +++++++++++++++
gas/testsuite/gas/riscv/zicbom.s | 7 +++++++
gas/testsuite/gas/riscv/zicbop-fail.d | 3 +++
gas/testsuite/gas/riscv/zicbop-fail.l | 4 ++++
gas/testsuite/gas/riscv/zicbop-fail.s | 4 ++++
gas/testsuite/gas/riscv/zicbop.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zicbop.s | 4 ++++
gas/testsuite/gas/riscv/zicboz-fail.d | 3 +++
gas/testsuite/gas/riscv/zicboz-fail.l | 3 +++
gas/testsuite/gas/riscv/zicboz-fail.s | 3 +++
gas/testsuite/gas/riscv/zicboz.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zicboz.s | 4 ++++
include/opcode/riscv-opc.h | 16 ++++++++++++++++
include/opcode/riscv.h | 3 +++
opcodes/riscv-dis.c | 4 ++++
opcodes/riscv-opc.c | 9 +++++++++
21 files changed, 150 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zicbom-fail.d
create mode 100644 gas/testsuite/gas/riscv/zicbom-fail.l
create mode 100644 gas/testsuite/gas/riscv/zicbom-fail.s
create mode 100644 gas/testsuite/gas/riscv/zicbom.d
create mode 100644 gas/testsuite/gas/riscv/zicbom.s
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.d
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.l
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.s
create mode 100644 gas/testsuite/gas/riscv/zicbop.d
create mode 100644 gas/testsuite/gas/riscv/zicbop.s
create mode 100644 gas/testsuite/gas/riscv/zicboz-fail.d
create mode 100644 gas/testsuite/gas/riscv/zicboz-fail.l
create mode 100644 gas/testsuite/gas/riscv/zicboz-fail.s
create mode 100644 gas/testsuite/gas/riscv/zicboz.d
create mode 100644 gas/testsuite/gas/riscv/zicboz.s
base-commit: a37603c43f8da7983ed53b567ea30ce66066daa2
--
2.32.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/5] RISC-V: Add mininal support for Zicbo[mpz]
2022-02-09 2:29 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Tsukasa OI
@ 2022-02-09 2:29 ` Tsukasa OI
2022-02-09 2:29 ` [PATCH 2/5] RISC-V: Cache management instructions Tsukasa OI
` (4 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Tsukasa OI @ 2022-02-09 2:29 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
Minimal support for 'Zicbom', 'Zicboz' and 'Zicbop' extensions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_supported_std_z_ext): Add 'Zicbom',
'Zicbop' and 'Zicboz' standard 'Z' extensions.
---
bfd/elfxx-riscv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 9f52bb545ac..3761811d4fd 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1179,6 +1179,9 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{
+ {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
--
2.32.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/5] RISC-V: Cache management instructions
2022-02-09 2:29 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Tsukasa OI
2022-02-09 2:29 ` [PATCH 1/5] RISC-V: Add mininal support for Zicbo[mpz] Tsukasa OI
@ 2022-02-09 2:29 ` Tsukasa OI
2022-02-09 2:29 ` [PATCH 3/5] RISC-V: Cache management instruction testcases Tsukasa OI
` (3 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Tsukasa OI @ 2022-02-09 2:29 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds 'Zicbom' / 'Zicboz' instructions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
new instruction classes.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN,
MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL,
MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add cache-block management
instructions.
---
bfd/elfxx-riscv.c | 4 ++++
include/opcode/riscv-opc.h | 9 +++++++++
include/opcode/riscv.h | 2 ++
opcodes/riscv-opc.c | 6 ++++++
4 files changed, 21 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 3761811d4fd..a7cd9320655 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -2334,6 +2334,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
{
case INSN_CLASS_I:
return riscv_subset_supports (rps, "i");
+ case INSN_CLASS_ZICBOM:
+ return riscv_subset_supports (rps, "zicbom");
+ case INSN_CLASS_ZICBOZ:
+ return riscv_subset_supports (rps, "zicboz");
case INSN_CLASS_ZICSR:
return riscv_subset_supports (rps, "zicsr");
case INSN_CLASS_ZIFENCEI:
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 0b8cc6c7ddb..b24e8a47c87 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2029,6 +2029,15 @@
#define MASK_HSV_W 0xfe007fff
#define MATCH_HSV_D 0x6e004073
#define MASK_HSV_D 0xfe007fff
+/* Zicbom/Zicboz instructions. */
+#define MATCH_CBO_CLEAN 0x10200f
+#define MASK_CBO_CLEAN 0xfff07fff
+#define MATCH_CBO_FLUSH 0x20200f
+#define MASK_CBO_FLUSH 0xfff07fff
+#define MATCH_CBO_INVAL 0x200f
+#define MASK_CBO_INVAL 0xfff07fff
+#define MATCH_CBO_ZERO 0x40200f
+#define MASK_CBO_ZERO 0xfff07fff
/* Privileged CSR addresses. */
#define CSR_USTATUS 0x0
#define CSR_UIE 0x4
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 048ab0a5d68..1d74f0e521a 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -388,6 +388,8 @@ enum riscv_insn_class
INSN_CLASS_V,
INSN_CLASS_ZVEF,
INSN_CLASS_SVINVAL,
+ INSN_CLASS_ZICBOM,
+ INSN_CLASS_ZICBOZ,
};
/* This structure holds information for a particular instruction. */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 2da0f7cf0a4..f092e975bd8 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -849,6 +849,12 @@ const struct riscv_opcode riscv_opcodes[] =
{"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
+/* Zicbom and Zicboz instructions. */
+{"cbo.clean", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
+{"cbo.flush", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
+{"cbo.inval", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
+{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
+
/* Zbb or zbkb instructions. */
{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
--
2.32.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/5] RISC-V: Cache management instruction testcases
2022-02-09 2:29 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Tsukasa OI
2022-02-09 2:29 ` [PATCH 1/5] RISC-V: Add mininal support for Zicbo[mpz] Tsukasa OI
2022-02-09 2:29 ` [PATCH 2/5] RISC-V: Cache management instructions Tsukasa OI
@ 2022-02-09 2:29 ` Tsukasa OI
2022-02-09 2:29 ` [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set Tsukasa OI
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Tsukasa OI @ 2022-02-09 2:29 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds testcases for 'Zicbom' / 'Zicboz' instructions.
* testsuite/gas/riscv/zicbom.d: New cache-block management
instruction tests.
* testsuite/gas/riscv/zicbom.s: Likewise.
* testsuite/gas/riscv/zicbom-fail.d: New cache-block management
instruction failure tests.
* testsuite/gas/riscv/zicbom-fail.l: Likewise.
* testsuite/gas/riscv/zicbom-fail.s: Likewise.
* testsuite/gas/riscv/zicboz.d: New cache-block zero instruction
tests.
* testsuite/gas/riscv/zicboz.s: Likewise.
* testsuite/gas/riscv/zicboz-fail.d: New cache-block zero
instruction failure tests.
* testsuite/gas/riscv/zicboz-fail.l: Likewise.
* testsuite/gas/riscv/zicboz-fail.s: Likewise.
---
gas/testsuite/gas/riscv/zicbom-fail.d | 3 +++
gas/testsuite/gas/riscv/zicbom-fail.l | 7 +++++++
gas/testsuite/gas/riscv/zicbom-fail.s | 7 +++++++
gas/testsuite/gas/riscv/zicbom.d | 15 +++++++++++++++
gas/testsuite/gas/riscv/zicbom.s | 7 +++++++
gas/testsuite/gas/riscv/zicboz-fail.d | 3 +++
gas/testsuite/gas/riscv/zicboz-fail.l | 3 +++
gas/testsuite/gas/riscv/zicboz-fail.s | 3 +++
gas/testsuite/gas/riscv/zicboz.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zicboz.s | 4 ++++
10 files changed, 64 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zicbom-fail.d
create mode 100644 gas/testsuite/gas/riscv/zicbom-fail.l
create mode 100644 gas/testsuite/gas/riscv/zicbom-fail.s
create mode 100644 gas/testsuite/gas/riscv/zicbom.d
create mode 100644 gas/testsuite/gas/riscv/zicbom.s
create mode 100644 gas/testsuite/gas/riscv/zicboz-fail.d
create mode 100644 gas/testsuite/gas/riscv/zicboz-fail.l
create mode 100644 gas/testsuite/gas/riscv/zicboz-fail.s
create mode 100644 gas/testsuite/gas/riscv/zicboz.d
create mode 100644 gas/testsuite/gas/riscv/zicboz.s
diff --git a/gas/testsuite/gas/riscv/zicbom-fail.d b/gas/testsuite/gas/riscv/zicbom-fail.d
new file mode 100644
index 00000000000..a6a61dfd37e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64g_zicbom
+#source: zicbom-fail.s
+#error_output: zicbom-fail.l
diff --git a/gas/testsuite/gas/riscv/zicbom-fail.l b/gas/testsuite/gas/riscv/zicbom-fail.l
new file mode 100644
index 00000000000..8b8eab54301
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom-fail.l
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cbo.clean 1\(x1\)'
+.*: Error: illegal operands `cbo.clean x30'
+.*: Error: illegal operands `cbo.flush \(0\+1\)\(x1\)'
+.*: Error: illegal operands `cbo.flush x30'
+.*: Error: illegal operands `cbo.inval \(3\*2\)\(x1\)'
+.*: Error: illegal operands `cbo.inval x30'
diff --git a/gas/testsuite/gas/riscv/zicbom-fail.s b/gas/testsuite/gas/riscv/zicbom-fail.s
new file mode 100644
index 00000000000..11133ff75d4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom-fail.s
@@ -0,0 +1,7 @@
+target:
+ cbo.clean 1(x1)
+ cbo.clean x30
+ cbo.flush (0+1)(x1)
+ cbo.flush x30
+ cbo.inval (3*2)(x1)
+ cbo.inval x30
diff --git a/gas/testsuite/gas/riscv/zicbom.d b/gas/testsuite/gas/riscv/zicbom.d
new file mode 100644
index 00000000000..edd8a7079f4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom.d
@@ -0,0 +1,15 @@
+#as: -march=rv64g_zicbom
+#source: zicbom.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0010a00f[ ]+cbo\.clean[ ]+\(ra\)
+[ ]+[0-9a-f]+:[ ]+001f200f[ ]+cbo\.clean[ ]+\(t5\)
+[ ]+[0-9a-f]+:[ ]+0020a00f[ ]+cbo\.flush[ ]+\(ra\)
+[ ]+[0-9a-f]+:[ ]+002f200f[ ]+cbo\.flush[ ]+\(t5\)
+[ ]+[0-9a-f]+:[ ]+0000a00f[ ]+cbo\.inval[ ]+\(ra\)
+[ ]+[0-9a-f]+:[ ]+000f200f[ ]+cbo\.inval[ ]+\(t5\)
diff --git a/gas/testsuite/gas/riscv/zicbom.s b/gas/testsuite/gas/riscv/zicbom.s
new file mode 100644
index 00000000000..463a6b3ebb4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom.s
@@ -0,0 +1,7 @@
+target:
+ cbo.clean (x1)
+ cbo.clean 0(x30)
+ cbo.flush (x1)
+ cbo.flush (2-2)(x30)
+ cbo.inval (x1)
+ cbo.inval (3*4-12)(x30)
diff --git a/gas/testsuite/gas/riscv/zicboz-fail.d b/gas/testsuite/gas/riscv/zicboz-fail.d
new file mode 100644
index 00000000000..74cfd2fc911
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64g_zicboz
+#source: zicboz-fail.s
+#error_output: zicboz-fail.l
diff --git a/gas/testsuite/gas/riscv/zicboz-fail.l b/gas/testsuite/gas/riscv/zicboz-fail.l
new file mode 100644
index 00000000000..0a19d3323c4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cbo.zero x1'
+.*: Error: illegal operands `cbo.zero 1\(x30\)'
diff --git a/gas/testsuite/gas/riscv/zicboz-fail.s b/gas/testsuite/gas/riscv/zicboz-fail.s
new file mode 100644
index 00000000000..b524cb6e269
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz-fail.s
@@ -0,0 +1,3 @@
+target:
+ cbo.zero x1
+ cbo.zero 1(x30)
diff --git a/gas/testsuite/gas/riscv/zicboz.d b/gas/testsuite/gas/riscv/zicboz.d
new file mode 100644
index 00000000000..7e47ad72610
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz.d
@@ -0,0 +1,12 @@
+#as: -march=rv64g_zicboz
+#source: zicboz.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+\(ra\)
+[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+\(t5\)
+[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+\(ra\)
diff --git a/gas/testsuite/gas/riscv/zicboz.s b/gas/testsuite/gas/riscv/zicboz.s
new file mode 100644
index 00000000000..ca5efb5ce24
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz.s
@@ -0,0 +1,4 @@
+target:
+ cbo.zero 0(x1)
+ cbo.zero (x30)
+ cbo.zero (2-2)(x1)
--
2.32.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set
2022-02-09 2:29 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Tsukasa OI
` (2 preceding siblings ...)
2022-02-09 2:29 ` [PATCH 3/5] RISC-V: Cache management instruction testcases Tsukasa OI
@ 2022-02-09 2:29 ` Tsukasa OI
2022-02-25 2:50 ` Nelson Chu
2022-02-09 2:29 ` [PATCH 5/5] RISC-V: Prefetch hint instruction testcases Tsukasa OI
2022-04-01 3:33 ` [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Palmer Dabbelt
5 siblings, 1 reply; 12+ messages in thread
From: Tsukasa OI @ 2022-02-09 2:29 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds 'Zicbop' hint instructions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
new instruction class.
gas/ChangeLog:
* config/tc-riscv.c (riscv_ip): Add handling for new operand
type 'f' (32-byte aligned pseudo S-type immediate for prefetch
hints).
(validate_riscv_insn): Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I,
MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W,
MASK_PREFETCH_W): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
class INSN_CLASS_ZICBOP.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add handling for new operand
type.
* riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.
---
bfd/elfxx-riscv.c | 2 ++
gas/config/tc-riscv.c | 18 ++++++++++++++++++
include/opcode/riscv-opc.h | 7 +++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-dis.c | 4 ++++
opcodes/riscv-opc.c | 3 +++
6 files changed, 35 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index a7cd9320655..2bd45a0bf17 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -2336,6 +2336,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "i");
case INSN_CLASS_ZICBOM:
return riscv_subset_supports (rps, "zicbom");
+ case INSN_CLASS_ZICBOP:
+ return riscv_subset_supports (rps, "zicbop");
case INSN_CLASS_ZICBOZ:
return riscv_subset_supports (rps, "zicboz");
case INSN_CLASS_ZICSR:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 25908597436..ddddb0989b1 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1160,6 +1160,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break;
case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break;
case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
+ case 'f': used_bits |= ENCODE_STYPE_IMM (-1U); break;
case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
case 'z': break; /* Zero immediate. */
case '[': break; /* Unused operand. */
@@ -3163,6 +3164,23 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
imm_expr->X_op = O_absent;
continue;
+ case 'f': /* Prefetch offset, pseudo S-type but lower 5-bits zero. */
+ if (riscv_handle_implicit_zero_offset (imm_expr, asarg))
+ continue;
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, false);
+ if (((unsigned) (imm_expr->X_add_number) & 0x1fU)
+ || imm_expr->X_add_number >= (signed) RISCV_IMM_REACH / 2
+ || imm_expr->X_add_number < -(signed) RISCV_IMM_REACH / 2)
+ as_bad (_("improper prefetch offset (%ld)"),
+ (long) imm_expr->X_add_number);
+ ip->insn_opcode |=
+ ENCODE_STYPE_IMM ((unsigned) (imm_expr->X_add_number) &
+ ~ 0x1fU);
+ imm_expr->X_op = O_absent;
+ asarg = expr_end;
+ continue;
+
default:
unknown_riscv_ip_operand:
as_fatal (_("internal: unknown argument type `%s'"),
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index b24e8a47c87..203bcdb9212 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2038,6 +2038,13 @@
#define MASK_CBO_INVAL 0xfff07fff
#define MATCH_CBO_ZERO 0x40200f
#define MASK_CBO_ZERO 0xfff07fff
+/* Zicbop hint instructions. */
+#define MATCH_PREFETCH_I 0x6013
+#define MASK_PREFETCH_I 0x1f07fff
+#define MATCH_PREFETCH_R 0x106013
+#define MASK_PREFETCH_R 0x1f07fff
+#define MATCH_PREFETCH_W 0x306013
+#define MASK_PREFETCH_W 0x1f07fff
/* Privileged CSR addresses. */
#define CSR_USTATUS 0x0
#define CSR_UIE 0x4
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 1d74f0e521a..b769769b4ec 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -389,6 +389,7 @@ enum riscv_insn_class
INSN_CLASS_ZVEF,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
+ INSN_CLASS_ZICBOP,
INSN_CLASS_ZICBOZ,
};
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 34724d4aec5..57b798d8e14 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -424,6 +424,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
break;
+ case 'f':
+ print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
+ break;
+
case 'a':
info->target = EXTRACT_JTYPE_IMM (l) + pc;
(*info->print_address_func) (info->target, info);
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index f092e975bd8..23716b6b7c9 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -388,6 +388,9 @@ const struct riscv_opcode riscv_opcodes[] =
{"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE },
{"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_LW, match_never, INSN_MACRO },
{"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI|MASK_IMM, MASK_XORI|MASK_IMM, match_opcode, INSN_ALIAS },
+{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 },
+{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 },
+{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 },
{"ori", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 },
{"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
{"or", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
--
2.32.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 5/5] RISC-V: Prefetch hint instruction testcases
2022-02-09 2:29 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Tsukasa OI
` (3 preceding siblings ...)
2022-02-09 2:29 ` [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set Tsukasa OI
@ 2022-02-09 2:29 ` Tsukasa OI
2022-04-01 3:33 ` [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Palmer Dabbelt
5 siblings, 0 replies; 12+ messages in thread
From: Tsukasa OI @ 2022-02-09 2:29 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds testcases for 'Zicbop' hint instructions.
gas/ChangeLog:
* testsuite/gas/riscv/zicbop-fail.d: New testcase for invalid
prefetch hint instructions.
* testsuite/gas/riscv/zicbop-fail.l: Likewise.
* testsuite/gas/riscv/zicbop-fail.s: Likewise.
* testsuite/gas/riscv/zicbop.d: New testcase for prefetch hint
instructions.
* testsuite/gas/riscv/zicbop.s: Likewise.
---
gas/testsuite/gas/riscv/zicbop-fail.d | 3 +++
gas/testsuite/gas/riscv/zicbop-fail.l | 4 ++++
gas/testsuite/gas/riscv/zicbop-fail.s | 4 ++++
gas/testsuite/gas/riscv/zicbop.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zicbop.s | 4 ++++
5 files changed, 27 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.d
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.l
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.s
create mode 100644 gas/testsuite/gas/riscv/zicbop.d
create mode 100644 gas/testsuite/gas/riscv/zicbop.s
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.d b/gas/testsuite/gas/riscv/zicbop-fail.d
new file mode 100644
index 00000000000..d734c7d4d15
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64g_zicbop
+#source: zicbop-fail.s
+#error_output: zicbop-fail.l
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.l b/gas/testsuite/gas/riscv/zicbop-fail.l
new file mode 100644
index 00000000000..4b5d5fc84fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop-fail.l
@@ -0,0 +1,4 @@
+.*: Assembler messages:
+.*: Error: improper prefetch offset \(2048\)
+.*: Error: improper prefetch offset \(-2080\)
+.*: Error: improper prefetch offset \(255\)
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.s b/gas/testsuite/gas/riscv/zicbop-fail.s
new file mode 100644
index 00000000000..0353c5ff80a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop-fail.s
@@ -0,0 +1,4 @@
+target:
+ prefetch.i 2048(x1)
+ prefetch.r -0x820(x16)
+ prefetch.w +0xff(x31)
diff --git a/gas/testsuite/gas/riscv/zicbop.d b/gas/testsuite/gas/riscv/zicbop.d
new file mode 100644
index 00000000000..056a8a501ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop.d
@@ -0,0 +1,12 @@
+#as: -march=rv64g_zicbop
+#source: zicbop.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0200e013[ ]+prefetch\.i[ ]+32\(ra\)
+[ ]+[0-9a-f]+:[ ]+80186013[ ]+prefetch\.r[ ]+-2048\(a6\)
+[ ]+[0-9a-f]+:[ ]+7e3fe013[ ]+prefetch\.w[ ]+2016\(t6\)
diff --git a/gas/testsuite/gas/riscv/zicbop.s b/gas/testsuite/gas/riscv/zicbop.s
new file mode 100644
index 00000000000..ffe2014be6f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop.s
@@ -0,0 +1,4 @@
+target:
+ prefetch.i 0x20(x1)
+ prefetch.r -2048(x16)
+ prefetch.w +0x7e0(x31)
--
2.32.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set
2022-02-09 2:29 ` [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set Tsukasa OI
@ 2022-02-25 2:50 ` Nelson Chu
2022-02-25 7:07 ` Tsukasa OI
0 siblings, 1 reply; 12+ messages in thread
From: Nelson Chu @ 2022-02-25 2:50 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Binutils, Christoph Muellner
Hi Tsukasa,
On Wed, Feb 9, 2022 at 10:33 AM Tsukasa OI via Binutils
<binutils@sourceware.org> wrote:
>
> This commit adds 'Zicbop' hint instructions.
>
> bfd/ChangeLog:
>
> * elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
> new instruction class.
>
> gas/ChangeLog:
>
> * config/tc-riscv.c (riscv_ip): Add handling for new operand
> type 'f' (32-byte aligned pseudo S-type immediate for prefetch
> hints).
> (validate_riscv_insn): Likewise.
>
> include/ChangeLog:
>
> * opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I,
> MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W,
> MASK_PREFETCH_W): New macros.
> * opcode/riscv.h (enum riscv_insn_class): Add new instruction
> class INSN_CLASS_ZICBOP.
>
> opcodes/ChangeLog:
>
> * riscv-dis.c (print_insn_args): Add handling for new operand
> type.
> * riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.
> ---
> bfd/elfxx-riscv.c | 2 ++
> gas/config/tc-riscv.c | 18 ++++++++++++++++++
> include/opcode/riscv-opc.h | 7 +++++++
> include/opcode/riscv.h | 1 +
> opcodes/riscv-dis.c | 4 ++++
> opcodes/riscv-opc.c | 3 +++
> 6 files changed, 35 insertions(+)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index a7cd9320655..2bd45a0bf17 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -2336,6 +2336,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
> return riscv_subset_supports (rps, "i");
> case INSN_CLASS_ZICBOM:
> return riscv_subset_supports (rps, "zicbom");
> + case INSN_CLASS_ZICBOP:
> + return riscv_subset_supports (rps, "zicbop");
> case INSN_CLASS_ZICBOZ:
> return riscv_subset_supports (rps, "zicboz");
> case INSN_CLASS_ZICSR:
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 25908597436..ddddb0989b1 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -1160,6 +1160,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
> case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break;
> case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break;
> case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
> + case 'f': used_bits |= ENCODE_STYPE_IMM (-1U); break;
I prefer to reuse the q operand here.
> case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
> case 'z': break; /* Zero immediate. */
> case '[': break; /* Unused operand. */
> @@ -3163,6 +3164,23 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
> imm_expr->X_op = O_absent;
> continue;
>
> + case 'f': /* Prefetch offset, pseudo S-type but lower 5-bits zero. */
> + if (riscv_handle_implicit_zero_offset (imm_expr, asarg))
> + continue;
> + my_getExpression (imm_expr, asarg);
> + check_absolute_expr (ip, imm_expr, false);
> + if (((unsigned) (imm_expr->X_add_number) & 0x1fU)
> + || imm_expr->X_add_number >= (signed) RISCV_IMM_REACH / 2
> + || imm_expr->X_add_number < -(signed) RISCV_IMM_REACH / 2)
> + as_bad (_("improper prefetch offset (%ld)"),
> + (long) imm_expr->X_add_number);
> + ip->insn_opcode |=
> + ENCODE_STYPE_IMM ((unsigned) (imm_expr->X_add_number) &
> + ~ 0x1fU);
> + imm_expr->X_op = O_absent;
> + asarg = expr_end;
> + continue;
> +
Reusing the q operand should be enough. Though we may add relocation
when the offset is a symbol, I think this should be fine.
> default:
> unknown_riscv_ip_operand:
> as_fatal (_("internal: unknown argument type `%s'"),
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index b24e8a47c87..203bcdb9212 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2038,6 +2038,13 @@
> #define MASK_CBO_INVAL 0xfff07fff
> #define MATCH_CBO_ZERO 0x40200f
> #define MASK_CBO_ZERO 0xfff07fff
> +/* Zicbop hint instructions. */
> +#define MATCH_PREFETCH_I 0x6013
> +#define MASK_PREFETCH_I 0x1f07fff
> +#define MATCH_PREFETCH_R 0x106013
> +#define MASK_PREFETCH_R 0x1f07fff
> +#define MATCH_PREFETCH_W 0x306013
> +#define MASK_PREFETCH_W 0x1f07fff
> /* Privileged CSR addresses. */
> #define CSR_USTATUS 0x0
> #define CSR_UIE 0x4
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 1d74f0e521a..b769769b4ec 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -389,6 +389,7 @@ enum riscv_insn_class
> INSN_CLASS_ZVEF,
> INSN_CLASS_SVINVAL,
> INSN_CLASS_ZICBOM,
> + INSN_CLASS_ZICBOP,
> INSN_CLASS_ZICBOZ,
> };
>
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index 34724d4aec5..57b798d8e14 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -424,6 +424,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
> print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
> break;
>
> + case 'f':
> + print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
> + break;
> +
> case 'a':
> info->target = EXTRACT_JTYPE_IMM (l) + pc;
> (*info->print_address_func) (info->target, info);
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index f092e975bd8..23716b6b7c9 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -388,6 +388,9 @@ const struct riscv_opcode riscv_opcodes[] =
> {"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE },
> {"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_LW, match_never, INSN_MACRO },
> {"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI|MASK_IMM, MASK_XORI|MASK_IMM, match_opcode, INSN_ALIAS },
> +{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 },
> +{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 },
> +{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 },
> {"ori", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 },
> {"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
> {"or", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
> --
> 2.32.0
>
Consider Christoph patch,
https://sourceware.org/pipermail/binutils/2022-January/119262.html
His patch is closer to the implementation I will do, just consider the
compatibility of amo instructions should be perfect. However, you are
adding more testcases than us. It would be always good to add more
testcases, so except the f operand, your patches LGTM.
Thanks
Nelson
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set
2022-02-25 2:50 ` Nelson Chu
@ 2022-02-25 7:07 ` Tsukasa OI
2022-03-18 7:50 ` Nelson Chu
0 siblings, 1 reply; 12+ messages in thread
From: Tsukasa OI @ 2022-02-25 7:07 UTC (permalink / raw)
To: Nelson Chu; +Cc: Binutils
[-- Attachment #1: Type: text/plain, Size: 3326 bytes --]
Hi Nelson,
I attached new rebased version of my CMO patches (for reference and
NOT an actual submission) so that you can test an example below.
| (Submission) (Attachment)
| PATCH 1/5 -> PATCH 1-2/2 (splitted and squashed)
| PATCH 4-5/5 -> PATCH 1/2 (squashed and order changed) p
| PATCH 2-3/5 -> PATCH 2/2 (squashed and order changed) m/z
This reorganization is mainly caused by following open issue:
<https://github.com/riscv/riscv-CMOs/issues/47>
I hope this is resolved soon so that I can submit the next version
without extra footnotes.
On 2022/02/25 11:50, Nelson Chu wrote:
> Hi Tsukasa,
>
> Reusing the q operand should be enough. Though we may add relocation
> when the offset is a symbol, I think this should be fine.
>
> Consider Christoph patch,
> https://sourceware.org/pipermail/binutils/2022-January/119262.html
>
> His patch is closer to the implementation I will do, just consider the
> compatibility of amo instructions should be perfect. However, you are
> adding more testcases than us. It would be always good to add more
> testcases, so except the f operand, your patches LGTM.
>
> Thanks
> Nelson
Unfortunately, simply reusing 'q' doesn't work.
For overflow checking, 'q' is fine.
On 2022/02/25 11:50, Nelson Chu wrote:>> case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
>> + case 'f': used_bits |= ENCODE_STYPE_IMM (-1U); break;
>
> I prefer to reuse the q operand here.
We may use simple fall-through here.
However, 32-byte alignment constraint requires a new operand type.
Let's see... assume that we change to use "q(s)" instead of "f(s)" (you
can just patch the patches I attached).
# BTW, I use minimal playground to test my GNU Binutils patches
# <https://github.com/a4lg/riscv-baremetal-playground>
# so that this example can be built and linked.
.globl _start
.section .entry, "ax", %progbits
_start:
.option arch,+zicbop
prefetch.i 0(t0)
# Remove Zicbop extension from final ELF
# to disassemble above instruction as `ori', not `prefetch.i'.
.option arch,-zicbop
ret
If we assemble above example (test.bare.S) and disassemble the result,
it should look like this:
0000000080000028 <_start>:
80000028: 0002e013 ori zero,t0,0
8000002c: 8082 ret
Looks great. But if we change 0(t0) to 1(t0), we DON'T get an error and
the result will look like...
0000000080000028 <_start>:
80000028: 0002e093 ori ra,t0,0
8000002c: 8082 ret
Oh no, a side effect (assignment to ra[x1]) without "illegal operands".
It happens because `match_opcode' for prefetch instructions (to test
instruction validity in `riscv_ip') is called before instruction bits
are modified. For store addresses, actual value insertion happens in
`md_apply_fix' function after "successfully assembled" in `riscv_ip'.
So, we need to test validity of the immediate constant (32-byte aligned)
somewhere. Even if we test it on fixup, it (at least) requires new
BFD relocation type (preventing reuse of case 'q' code path).
Of course, if we consider using relocations on prefetch instructions,
we could move, for instance, address insertion.
Still, we absolutely need something new to handle special 32-byte
alignment or we will risk generating corrupted programs.
Thanks,
Tsukasa
[-- Attachment #2: 0001-RISC-V-Prefetch-hint-instructions-and-operand-set.patch --]
[-- Type: text/plain, Size: 9157 bytes --]
From 2cf451c653352e6f5d1769f36a2a48f1d5820ae1 Mon Sep 17 00:00:00 2001
Message-Id: <2cf451c653352e6f5d1769f36a2a48f1d5820ae1.1645771895.git.research_trasio@irq.a4lg.com>
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: Tue, 11 Jan 2022 19:14:02 +0900
Subject: [PATCH 1/2] RISC-V: Prefetch hint instructions and operand set
This commit adds 'Zicbop' hint instructions and testcases.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_supported_std_z_ext): Add 'Zicbop'
standard 'Z' extension. (riscv_multi_subset_supports): Add
handling for new instruction class.
gas/ChangeLog:
* config/tc-riscv.c (riscv_ip): Add handling for new operand
type 'f' (32-byte aligned pseudo S-type immediate for prefetch
hints).
(validate_riscv_insn): Likewise.
* testsuite/gas/riscv/zicbop-fail.d: New testcase for invalid
prefetch hint instructions.
* testsuite/gas/riscv/zicbop-fail.l: Likewise.
* testsuite/gas/riscv/zicbop-fail.s: Likewise.
* testsuite/gas/riscv/zicbop.d: New testcase for prefetch hint
instructions.
* testsuite/gas/riscv/zicbop.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I,
MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W,
MASK_PREFETCH_W): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
class INSN_CLASS_ZICBOP.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add handling for new operand
type.
* riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.
---
bfd/elfxx-riscv.c | 3 +++
gas/config/tc-riscv.c | 18 ++++++++++++++++++
gas/testsuite/gas/riscv/zicbop-fail.d | 3 +++
gas/testsuite/gas/riscv/zicbop-fail.l | 4 ++++
gas/testsuite/gas/riscv/zicbop-fail.s | 4 ++++
gas/testsuite/gas/riscv/zicbop.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zicbop.s | 4 ++++
include/opcode/riscv-opc.h | 7 +++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-dis.c | 4 ++++
opcodes/riscv-opc.c | 3 +++
11 files changed, 63 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.d
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.l
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.s
create mode 100644 gas/testsuite/gas/riscv/zicbop.d
create mode 100644 gas/testsuite/gas/riscv/zicbop.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index d74e7a584eb..83cd90d006a 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1172,6 +1172,7 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{
+ {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
@@ -2319,6 +2320,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
{
case INSN_CLASS_I:
return riscv_subset_supports (rps, "i");
+ case INSN_CLASS_ZICBOP:
+ return riscv_subset_supports (rps, "zicbop");
case INSN_CLASS_ZICSR:
return riscv_subset_supports (rps, "zicsr");
case INSN_CLASS_ZIFENCEI:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 322e0f070ba..966d08ced82 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1180,6 +1180,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break;
case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break;
case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
+ case 'f': used_bits |= ENCODE_STYPE_IMM (-1U); break;
case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
case 'z': break; /* Zero immediate. */
case '[': break; /* Unused operand. */
@@ -3191,6 +3192,23 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
imm_expr->X_op = O_absent;
continue;
+ case 'f': /* Prefetch offset, pseudo S-type but lower 5-bits zero. */
+ if (riscv_handle_implicit_zero_offset (imm_expr, asarg))
+ continue;
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, false);
+ if (((unsigned) (imm_expr->X_add_number) & 0x1fU)
+ || imm_expr->X_add_number >= (signed) RISCV_IMM_REACH / 2
+ || imm_expr->X_add_number < -(signed) RISCV_IMM_REACH / 2)
+ as_bad (_("improper prefetch offset (%ld)"),
+ (long) imm_expr->X_add_number);
+ ip->insn_opcode |=
+ ENCODE_STYPE_IMM ((unsigned) (imm_expr->X_add_number) &
+ ~ 0x1fU);
+ imm_expr->X_op = O_absent;
+ asarg = expr_end;
+ continue;
+
default:
unknown_riscv_ip_operand:
as_fatal (_("internal: unknown argument type `%s'"),
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.d b/gas/testsuite/gas/riscv/zicbop-fail.d
new file mode 100644
index 00000000000..d734c7d4d15
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64g_zicbop
+#source: zicbop-fail.s
+#error_output: zicbop-fail.l
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.l b/gas/testsuite/gas/riscv/zicbop-fail.l
new file mode 100644
index 00000000000..4b5d5fc84fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop-fail.l
@@ -0,0 +1,4 @@
+.*: Assembler messages:
+.*: Error: improper prefetch offset \(2048\)
+.*: Error: improper prefetch offset \(-2080\)
+.*: Error: improper prefetch offset \(255\)
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.s b/gas/testsuite/gas/riscv/zicbop-fail.s
new file mode 100644
index 00000000000..0353c5ff80a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop-fail.s
@@ -0,0 +1,4 @@
+target:
+ prefetch.i 2048(x1)
+ prefetch.r -0x820(x16)
+ prefetch.w +0xff(x31)
diff --git a/gas/testsuite/gas/riscv/zicbop.d b/gas/testsuite/gas/riscv/zicbop.d
new file mode 100644
index 00000000000..056a8a501ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop.d
@@ -0,0 +1,12 @@
+#as: -march=rv64g_zicbop
+#source: zicbop.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0200e013[ ]+prefetch\.i[ ]+32\(ra\)
+[ ]+[0-9a-f]+:[ ]+80186013[ ]+prefetch\.r[ ]+-2048\(a6\)
+[ ]+[0-9a-f]+:[ ]+7e3fe013[ ]+prefetch\.w[ ]+2016\(t6\)
diff --git a/gas/testsuite/gas/riscv/zicbop.s b/gas/testsuite/gas/riscv/zicbop.s
new file mode 100644
index 00000000000..ffe2014be6f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop.s
@@ -0,0 +1,4 @@
+target:
+ prefetch.i 0x20(x1)
+ prefetch.r -2048(x16)
+ prefetch.w +0x7e0(x31)
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 01cd3a4e9dd..1572c84f0be 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2029,6 +2029,13 @@
#define MASK_HSV_W 0xfe007fff
#define MATCH_HSV_D 0x6e004073
#define MASK_HSV_D 0xfe007fff
+/* Zicbop hint instructions. */
+#define MATCH_PREFETCH_I 0x6013
+#define MASK_PREFETCH_I 0x1f07fff
+#define MATCH_PREFETCH_R 0x106013
+#define MASK_PREFETCH_R 0x1f07fff
+#define MATCH_PREFETCH_W 0x306013
+#define MASK_PREFETCH_W 0x1f07fff
/* Unprivileged Counter/Timers CSR addresses. */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 048ab0a5d68..5462b5eceab 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -388,6 +388,7 @@ enum riscv_insn_class
INSN_CLASS_V,
INSN_CLASS_ZVEF,
INSN_CLASS_SVINVAL,
+ INSN_CLASS_ZICBOP,
};
/* This structure holds information for a particular instruction. */
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 34724d4aec5..57b798d8e14 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -424,6 +424,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
break;
+ case 'f':
+ print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
+ break;
+
case 'a':
info->target = EXTRACT_JTYPE_IMM (l) + pc;
(*info->print_address_func) (info->target, info);
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 2da0f7cf0a4..bd200d736e5 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -388,6 +388,9 @@ const struct riscv_opcode riscv_opcodes[] =
{"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE },
{"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_LW, match_never, INSN_MACRO },
{"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI|MASK_IMM, MASK_XORI|MASK_IMM, match_opcode, INSN_ALIAS },
+{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 },
+{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 },
+{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 },
{"ori", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 },
{"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
{"or", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
--
2.32.0
[-- Attachment #3: 0002-RISC-V-Cache-management-instructions.patch --]
[-- Type: text/plain, Size: 6954 bytes --]
From 596caba950482dd6a6dc0f564e9be9d56c81bb48 Mon Sep 17 00:00:00 2001
Message-Id: <596caba950482dd6a6dc0f564e9be9d56c81bb48.1645771895.git.research_trasio@irq.a4lg.com>
In-Reply-To: <2cf451c653352e6f5d1769f36a2a48f1d5820ae1.1645771895.git.research_trasio@irq.a4lg.com>
References: <2cf451c653352e6f5d1769f36a2a48f1d5820ae1.1645771895.git.research_trasio@irq.a4lg.com>
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: Tue, 11 Jan 2022 19:14:02 +0900
Subject: [PATCH 2/2] RISC-V: Cache management instructions
This commit adds 'Zicbom' / 'Zicboz' instructions and testcases.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_supported_std_z_ext): Add 'Zicbom' and
'Zicboz' standard 'Z' extensions. (riscv_multi_subset_supports):
Add handling for new instruction classes.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN,
MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL,
MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ.
gas/ChangeLog:
* testsuite/gas/riscv/zicbom.d: New cache-block management
instruction tests.
* testsuite/gas/riscv/zicbom.s: Likewise.
* testsuite/gas/riscv/zicboz.d: New cache-block zero instruction
tests.
* testsuite/gas/riscv/zicboz.s: Likewise.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add cache-block management
instructions.
---
bfd/elfxx-riscv.c | 6 ++++++
gas/testsuite/gas/riscv/zicbom.d | 15 +++++++++++++++
gas/testsuite/gas/riscv/zicbom.s | 7 +++++++
gas/testsuite/gas/riscv/zicboz.d | 11 +++++++++++
gas/testsuite/gas/riscv/zicboz.s | 3 +++
include/opcode/riscv-opc.h | 9 +++++++++
include/opcode/riscv.h | 2 ++
opcodes/riscv-opc.c | 6 ++++++
8 files changed, 59 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zicbom.d
create mode 100644 gas/testsuite/gas/riscv/zicbom.s
create mode 100644 gas/testsuite/gas/riscv/zicboz.d
create mode 100644 gas/testsuite/gas/riscv/zicboz.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 83cd90d006a..b761b590dd0 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1172,7 +1172,9 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{
+ {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
@@ -2320,8 +2322,12 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
{
case INSN_CLASS_I:
return riscv_subset_supports (rps, "i");
+ case INSN_CLASS_ZICBOM:
+ return riscv_subset_supports (rps, "zicbom");
case INSN_CLASS_ZICBOP:
return riscv_subset_supports (rps, "zicbop");
+ case INSN_CLASS_ZICBOZ:
+ return riscv_subset_supports (rps, "zicboz");
case INSN_CLASS_ZICSR:
return riscv_subset_supports (rps, "zicsr");
case INSN_CLASS_ZIFENCEI:
diff --git a/gas/testsuite/gas/riscv/zicbom.d b/gas/testsuite/gas/riscv/zicbom.d
new file mode 100644
index 00000000000..3a194cf6edf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom.d
@@ -0,0 +1,15 @@
+#as: -march=rv64g_zicbom
+#source: zicbom.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0010a00f[ ]+cbo\.clean[ ]+ra
+[ ]+[0-9a-f]+:[ ]+001f200f[ ]+cbo\.clean[ ]+t5
+[ ]+[0-9a-f]+:[ ]+0020a00f[ ]+cbo\.flush[ ]+ra
+[ ]+[0-9a-f]+:[ ]+002f200f[ ]+cbo\.flush[ ]+t5
+[ ]+[0-9a-f]+:[ ]+0000a00f[ ]+cbo\.inval[ ]+ra
+[ ]+[0-9a-f]+:[ ]+000f200f[ ]+cbo\.inval[ ]+t5
diff --git a/gas/testsuite/gas/riscv/zicbom.s b/gas/testsuite/gas/riscv/zicbom.s
new file mode 100644
index 00000000000..778a61e76f3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom.s
@@ -0,0 +1,7 @@
+target:
+ cbo.clean x1
+ cbo.clean x30
+ cbo.flush x1
+ cbo.flush x30
+ cbo.inval x1
+ cbo.inval x30
diff --git a/gas/testsuite/gas/riscv/zicboz.d b/gas/testsuite/gas/riscv/zicboz.d
new file mode 100644
index 00000000000..7686edbe677
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz.d
@@ -0,0 +1,11 @@
+#as: -march=rv64g_zicboz
+#source: zicboz.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+ra
+[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+t5
diff --git a/gas/testsuite/gas/riscv/zicboz.s b/gas/testsuite/gas/riscv/zicboz.s
new file mode 100644
index 00000000000..ba75b787b00
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz.s
@@ -0,0 +1,3 @@
+target:
+ cbo.zero x1
+ cbo.zero x30
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 1572c84f0be..3eea33a5dae 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2036,6 +2036,15 @@
#define MASK_PREFETCH_R 0x1f07fff
#define MATCH_PREFETCH_W 0x306013
#define MASK_PREFETCH_W 0x1f07fff
+/* Zicbom/Zicboz instructions. */
+#define MATCH_CBO_CLEAN 0x10200f
+#define MASK_CBO_CLEAN 0xfff07fff
+#define MATCH_CBO_FLUSH 0x20200f
+#define MASK_CBO_FLUSH 0xfff07fff
+#define MATCH_CBO_INVAL 0x200f
+#define MASK_CBO_INVAL 0xfff07fff
+#define MATCH_CBO_ZERO 0x40200f
+#define MASK_CBO_ZERO 0xfff07fff
/* Unprivileged Counter/Timers CSR addresses. */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 5462b5eceab..b769769b4ec 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -388,7 +388,9 @@ enum riscv_insn_class
INSN_CLASS_V,
INSN_CLASS_ZVEF,
INSN_CLASS_SVINVAL,
+ INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
+ INSN_CLASS_ZICBOZ,
};
/* This structure holds information for a particular instruction. */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index bd200d736e5..c472c6d3252 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -852,6 +852,12 @@ const struct riscv_opcode riscv_opcodes[] =
{"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
+/* Zicbom and Zicboz instructions. */
+{"cbo.clean", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
+{"cbo.flush", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
+{"cbo.inval", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
+{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "s", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
+
/* Zbb or zbkb instructions. */
{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
--
2.32.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set
2022-02-25 7:07 ` Tsukasa OI
@ 2022-03-18 7:50 ` Nelson Chu
0 siblings, 0 replies; 12+ messages in thread
From: Nelson Chu @ 2022-03-18 7:50 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Binutils
Hi Tsukasa,
Yeah you are right, we should define a new operand for the imm of
prefetch instructions, to check if the lower 5 bit is zero. Sorry
that I thought wrong before. The patches in the riscv-CMOs-with-paren
branch from your github LGTM, so sommited.
Thanks
Nelson
On Fri, Feb 25, 2022 at 3:07 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> Hi Nelson,
>
> I attached new rebased version of my CMO patches (for reference and
> NOT an actual submission) so that you can test an example below.
>
> | (Submission) (Attachment)
> | PATCH 1/5 -> PATCH 1-2/2 (splitted and squashed)
> | PATCH 4-5/5 -> PATCH 1/2 (squashed and order changed) p
> | PATCH 2-3/5 -> PATCH 2/2 (squashed and order changed) m/z
>
> This reorganization is mainly caused by following open issue:
> <https://github.com/riscv/riscv-CMOs/issues/47>
> I hope this is resolved soon so that I can submit the next version
> without extra footnotes.
>
>
> On 2022/02/25 11:50, Nelson Chu wrote:
> > Hi Tsukasa,
> >
> > Reusing the q operand should be enough. Though we may add relocation
> > when the offset is a symbol, I think this should be fine.
> >
> > Consider Christoph patch,
> > https://sourceware.org/pipermail/binutils/2022-January/119262.html
> >
> > His patch is closer to the implementation I will do, just consider the
> > compatibility of amo instructions should be perfect. However, you are
> > adding more testcases than us. It would be always good to add more
> > testcases, so except the f operand, your patches LGTM.
> >
> > Thanks
> > Nelson
>
>
> Unfortunately, simply reusing 'q' doesn't work.
>
> For overflow checking, 'q' is fine.
>
> On 2022/02/25 11:50, Nelson Chu wrote:>> case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
> >> + case 'f': used_bits |= ENCODE_STYPE_IMM (-1U); break;
> >
> > I prefer to reuse the q operand here.
>
> We may use simple fall-through here.
>
> However, 32-byte alignment constraint requires a new operand type.
>
>
> Let's see... assume that we change to use "q(s)" instead of "f(s)" (you
> can just patch the patches I attached).
>
> # BTW, I use minimal playground to test my GNU Binutils patches
> # <https://github.com/a4lg/riscv-baremetal-playground>
> # so that this example can be built and linked.
> .globl _start
> .section .entry, "ax", %progbits
> _start:
> .option arch,+zicbop
> prefetch.i 0(t0)
> # Remove Zicbop extension from final ELF
> # to disassemble above instruction as `ori', not `prefetch.i'.
> .option arch,-zicbop
> ret
>
> If we assemble above example (test.bare.S) and disassemble the result,
> it should look like this:
>
> 0000000080000028 <_start>:
> 80000028: 0002e013 ori zero,t0,0
> 8000002c: 8082 ret
>
> Looks great. But if we change 0(t0) to 1(t0), we DON'T get an error and
> the result will look like...
>
> 0000000080000028 <_start>:
> 80000028: 0002e093 ori ra,t0,0
> 8000002c: 8082 ret
>
> Oh no, a side effect (assignment to ra[x1]) without "illegal operands".
>
>
> It happens because `match_opcode' for prefetch instructions (to test
> instruction validity in `riscv_ip') is called before instruction bits
> are modified. For store addresses, actual value insertion happens in
> `md_apply_fix' function after "successfully assembled" in `riscv_ip'.
>
> So, we need to test validity of the immediate constant (32-byte aligned)
> somewhere. Even if we test it on fixup, it (at least) requires new
> BFD relocation type (preventing reuse of case 'q' code path).
>
>
> Of course, if we consider using relocations on prefetch instructions,
> we could move, for instance, address insertion.
> Still, we absolutely need something new to handle special 32-byte
> alignment or we will risk generating corrupted programs.
>
>
> Thanks,
> Tsukasa
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren)
2022-02-09 2:29 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Tsukasa OI
` (4 preceding siblings ...)
2022-02-09 2:29 ` [PATCH 5/5] RISC-V: Prefetch hint instruction testcases Tsukasa OI
@ 2022-04-01 3:33 ` Palmer Dabbelt
2022-04-01 4:04 ` Kito Cheng
5 siblings, 1 reply; 12+ messages in thread
From: Palmer Dabbelt @ 2022-04-01 3:33 UTC (permalink / raw)
To: binutils; +Cc: research_trasio, binutils
On Tue, 08 Feb 2022 18:29:27 PST (-0800), binutils@sourceware.org wrote:
> This patchset is a modified version of:
> <https://sourceware.org/pipermail/binutils/2021-December/118909.html>
>
> GitHub:
> <https://github.com/a4lg/binutils-gdb/tree/riscv-CMOs> (original; 2021-12-16, rebased)
> <https://github.com/a4lg/binutils-gdb/tree/riscv-CMOs-with-paren> (new: 2022-02-09)
>
>
> There seems a discussion to change operand of cbo.* instructions on:
> <https://github.com/riscv/riscv-CMOs/issues/47>.
Looks like that still hasn't been resolved? I don't really care either
way, just that whatever we do is in agreement with the spec as it'd be
silly to differ from LLVM here.
> I have a little preference for old one but it's not bad to have both
> options (as complete patchsets).
>
> Note that however, the original patchset is *NOT OUTDATED* yet.
> It implements Zicbom/Zicboz instruction like:
>
> cbo.zero a0
>
> This new patchset implements Zicbom/Zicboz instructions like:
>
> cbo.zero (a0)
> cbo.zero 0(a0) # only zero is allowed
There's some precedent for accepting both flavors of instructions like
that, so if there's already an assembler out there that does things one
way and the spec does the other I guess we could accept both? I'd still
prefer to just have everyone agree on the specification side, though.
> Actually, my first attempt to implement cbo.* instructions used the same
> format as *new* patchset (I modified before submitting the first
> patchset for compliance to the specification document).
>
> This version requires extra checking (0(a0) actually allows
> EXPRESSION_RESULTS_IN_ZERO(a0)) so I added a few extra tests.
> It will also reject operand format in older patchset.
>
> Old patchset and new patchset are mutually exclusive and should follow
> the conclusion of the discussion above.
>
> Thanks,
> Tsukasa
>
>
>
>
> Tsukasa OI (5):
> RISC-V: Add mininal support for Zicbo[mpz]
> RISC-V: Cache management instructions
> RISC-V: Cache management instruction testcases
> RISC-V: Prefetch hint instructions and operand set
> RISC-V: Prefetch hint instruction testcases
>
> bfd/elfxx-riscv.c | 9 +++++++++
> gas/config/tc-riscv.c | 18 ++++++++++++++++++
> gas/testsuite/gas/riscv/zicbom-fail.d | 3 +++
> gas/testsuite/gas/riscv/zicbom-fail.l | 7 +++++++
> gas/testsuite/gas/riscv/zicbom-fail.s | 7 +++++++
> gas/testsuite/gas/riscv/zicbom.d | 15 +++++++++++++++
> gas/testsuite/gas/riscv/zicbom.s | 7 +++++++
> gas/testsuite/gas/riscv/zicbop-fail.d | 3 +++
> gas/testsuite/gas/riscv/zicbop-fail.l | 4 ++++
> gas/testsuite/gas/riscv/zicbop-fail.s | 4 ++++
> gas/testsuite/gas/riscv/zicbop.d | 12 ++++++++++++
> gas/testsuite/gas/riscv/zicbop.s | 4 ++++
> gas/testsuite/gas/riscv/zicboz-fail.d | 3 +++
> gas/testsuite/gas/riscv/zicboz-fail.l | 3 +++
> gas/testsuite/gas/riscv/zicboz-fail.s | 3 +++
> gas/testsuite/gas/riscv/zicboz.d | 12 ++++++++++++
> gas/testsuite/gas/riscv/zicboz.s | 4 ++++
> include/opcode/riscv-opc.h | 16 ++++++++++++++++
> include/opcode/riscv.h | 3 +++
> opcodes/riscv-dis.c | 4 ++++
> opcodes/riscv-opc.c | 9 +++++++++
> 21 files changed, 150 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/zicbom-fail.d
> create mode 100644 gas/testsuite/gas/riscv/zicbom-fail.l
> create mode 100644 gas/testsuite/gas/riscv/zicbom-fail.s
> create mode 100644 gas/testsuite/gas/riscv/zicbom.d
> create mode 100644 gas/testsuite/gas/riscv/zicbom.s
> create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.d
> create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.l
> create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.s
> create mode 100644 gas/testsuite/gas/riscv/zicbop.d
> create mode 100644 gas/testsuite/gas/riscv/zicbop.s
> create mode 100644 gas/testsuite/gas/riscv/zicboz-fail.d
> create mode 100644 gas/testsuite/gas/riscv/zicboz-fail.l
> create mode 100644 gas/testsuite/gas/riscv/zicboz-fail.s
> create mode 100644 gas/testsuite/gas/riscv/zicboz.d
> create mode 100644 gas/testsuite/gas/riscv/zicboz.s
>
>
> base-commit: a37603c43f8da7983ed53b567ea30ce66066daa2
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren)
2022-04-01 3:33 ` [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Palmer Dabbelt
@ 2022-04-01 4:04 ` Kito Cheng
2022-04-01 4:15 ` Palmer Dabbelt
0 siblings, 1 reply; 12+ messages in thread
From: Kito Cheng @ 2022-04-01 4:04 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: Binutils
Nelson has merge this patch series:
https://github.com/bminor/binutils-gdb/commit/41d6ac5da655a2e78109848f2db47e53552fd61a
https://github.com/bminor/binutils-gdb/commit/3b374308d3006407b9571e573e4ccce4e904a4c4
On Fri, Apr 1, 2022 at 11:33 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Tue, 08 Feb 2022 18:29:27 PST (-0800), binutils@sourceware.org wrote:
> > This patchset is a modified version of:
> > <https://sourceware.org/pipermail/binutils/2021-December/118909.html>
> >
> > GitHub:
> > <https://github.com/a4lg/binutils-gdb/tree/riscv-CMOs> (original; 2021-12-16, rebased)
> > <https://github.com/a4lg/binutils-gdb/tree/riscv-CMOs-with-paren> (new: 2022-02-09)
> >
> >
> > There seems a discussion to change operand of cbo.* instructions on:
> > <https://github.com/riscv/riscv-CMOs/issues/47>.
>
> Looks like that still hasn't been resolved? I don't really care either
> way, just that whatever we do is in agreement with the spec as it'd be
> silly to differ from LLVM here.
>
> > I have a little preference for old one but it's not bad to have both
> > options (as complete patchsets).
> >
> > Note that however, the original patchset is *NOT OUTDATED* yet.
> > It implements Zicbom/Zicboz instruction like:
> >
> > cbo.zero a0
> >
> > This new patchset implements Zicbom/Zicboz instructions like:
> >
> > cbo.zero (a0)
> > cbo.zero 0(a0) # only zero is allowed
>
> There's some precedent for accepting both flavors of instructions like
> that, so if there's already an assembler out there that does things one
> way and the spec does the other I guess we could accept both? I'd still
> prefer to just have everyone agree on the specification side, though.
>
> > Actually, my first attempt to implement cbo.* instructions used the same
> > format as *new* patchset (I modified before submitting the first
> > patchset for compliance to the specification document).
> >
> > This version requires extra checking (0(a0) actually allows
> > EXPRESSION_RESULTS_IN_ZERO(a0)) so I added a few extra tests.
> > It will also reject operand format in older patchset.
> >
> > Old patchset and new patchset are mutually exclusive and should follow
> > the conclusion of the discussion above.
> >
> > Thanks,
> > Tsukasa
> >
> >
> >
> >
> > Tsukasa OI (5):
> > RISC-V: Add mininal support for Zicbo[mpz]
> > RISC-V: Cache management instructions
> > RISC-V: Cache management instruction testcases
> > RISC-V: Prefetch hint instructions and operand set
> > RISC-V: Prefetch hint instruction testcases
> >
> > bfd/elfxx-riscv.c | 9 +++++++++
> > gas/config/tc-riscv.c | 18 ++++++++++++++++++
> > gas/testsuite/gas/riscv/zicbom-fail.d | 3 +++
> > gas/testsuite/gas/riscv/zicbom-fail.l | 7 +++++++
> > gas/testsuite/gas/riscv/zicbom-fail.s | 7 +++++++
> > gas/testsuite/gas/riscv/zicbom.d | 15 +++++++++++++++
> > gas/testsuite/gas/riscv/zicbom.s | 7 +++++++
> > gas/testsuite/gas/riscv/zicbop-fail.d | 3 +++
> > gas/testsuite/gas/riscv/zicbop-fail.l | 4 ++++
> > gas/testsuite/gas/riscv/zicbop-fail.s | 4 ++++
> > gas/testsuite/gas/riscv/zicbop.d | 12 ++++++++++++
> > gas/testsuite/gas/riscv/zicbop.s | 4 ++++
> > gas/testsuite/gas/riscv/zicboz-fail.d | 3 +++
> > gas/testsuite/gas/riscv/zicboz-fail.l | 3 +++
> > gas/testsuite/gas/riscv/zicboz-fail.s | 3 +++
> > gas/testsuite/gas/riscv/zicboz.d | 12 ++++++++++++
> > gas/testsuite/gas/riscv/zicboz.s | 4 ++++
> > include/opcode/riscv-opc.h | 16 ++++++++++++++++
> > include/opcode/riscv.h | 3 +++
> > opcodes/riscv-dis.c | 4 ++++
> > opcodes/riscv-opc.c | 9 +++++++++
> > 21 files changed, 150 insertions(+)
> > create mode 100644 gas/testsuite/gas/riscv/zicbom-fail.d
> > create mode 100644 gas/testsuite/gas/riscv/zicbom-fail.l
> > create mode 100644 gas/testsuite/gas/riscv/zicbom-fail.s
> > create mode 100644 gas/testsuite/gas/riscv/zicbom.d
> > create mode 100644 gas/testsuite/gas/riscv/zicbom.s
> > create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.d
> > create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.l
> > create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.s
> > create mode 100644 gas/testsuite/gas/riscv/zicbop.d
> > create mode 100644 gas/testsuite/gas/riscv/zicbop.s
> > create mode 100644 gas/testsuite/gas/riscv/zicboz-fail.d
> > create mode 100644 gas/testsuite/gas/riscv/zicboz-fail.l
> > create mode 100644 gas/testsuite/gas/riscv/zicboz-fail.s
> > create mode 100644 gas/testsuite/gas/riscv/zicboz.d
> > create mode 100644 gas/testsuite/gas/riscv/zicboz.s
> >
> >
> > base-commit: a37603c43f8da7983ed53b567ea30ce66066daa2
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren)
2022-04-01 4:04 ` Kito Cheng
@ 2022-04-01 4:15 ` Palmer Dabbelt
0 siblings, 0 replies; 12+ messages in thread
From: Palmer Dabbelt @ 2022-04-01 4:15 UTC (permalink / raw)
To: Kito Cheng; +Cc: binutils
On Thu, 31 Mar 2022 21:04:12 PDT (-0700), Kito Cheng wrote:
> Nelson has merge this patch series:
>
> https://github.com/bminor/binutils-gdb/commit/41d6ac5da655a2e78109848f2db47e53552fd61a
> https://github.com/bminor/binutils-gdb/commit/3b374308d3006407b9571e573e4ccce4e904a4c4
Thanks, I'd just looked for a email. I poked the spec folks, just to
make sure we don't make a mess.
>
> On Fri, Apr 1, 2022 at 11:33 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>>
>> On Tue, 08 Feb 2022 18:29:27 PST (-0800), binutils@sourceware.org wrote:
>> > This patchset is a modified version of:
>> > <https://sourceware.org/pipermail/binutils/2021-December/118909.html>
>> >
>> > GitHub:
>> > <https://github.com/a4lg/binutils-gdb/tree/riscv-CMOs> (original; 2021-12-16, rebased)
>> > <https://github.com/a4lg/binutils-gdb/tree/riscv-CMOs-with-paren> (new: 2022-02-09)
>> >
>> >
>> > There seems a discussion to change operand of cbo.* instructions on:
>> > <https://github.com/riscv/riscv-CMOs/issues/47>.
>>
>> Looks like that still hasn't been resolved? I don't really care either
>> way, just that whatever we do is in agreement with the spec as it'd be
>> silly to differ from LLVM here.
>>
>> > I have a little preference for old one but it's not bad to have both
>> > options (as complete patchsets).
>> >
>> > Note that however, the original patchset is *NOT OUTDATED* yet.
>> > It implements Zicbom/Zicboz instruction like:
>> >
>> > cbo.zero a0
>> >
>> > This new patchset implements Zicbom/Zicboz instructions like:
>> >
>> > cbo.zero (a0)
>> > cbo.zero 0(a0) # only zero is allowed
>>
>> There's some precedent for accepting both flavors of instructions like
>> that, so if there's already an assembler out there that does things one
>> way and the spec does the other I guess we could accept both? I'd still
>> prefer to just have everyone agree on the specification side, though.
>>
>> > Actually, my first attempt to implement cbo.* instructions used the same
>> > format as *new* patchset (I modified before submitting the first
>> > patchset for compliance to the specification document).
>> >
>> > This version requires extra checking (0(a0) actually allows
>> > EXPRESSION_RESULTS_IN_ZERO(a0)) so I added a few extra tests.
>> > It will also reject operand format in older patchset.
>> >
>> > Old patchset and new patchset are mutually exclusive and should follow
>> > the conclusion of the discussion above.
>> >
>> > Thanks,
>> > Tsukasa
>> >
>> >
>> >
>> >
>> > Tsukasa OI (5):
>> > RISC-V: Add mininal support for Zicbo[mpz]
>> > RISC-V: Cache management instructions
>> > RISC-V: Cache management instruction testcases
>> > RISC-V: Prefetch hint instructions and operand set
>> > RISC-V: Prefetch hint instruction testcases
>> >
>> > bfd/elfxx-riscv.c | 9 +++++++++
>> > gas/config/tc-riscv.c | 18 ++++++++++++++++++
>> > gas/testsuite/gas/riscv/zicbom-fail.d | 3 +++
>> > gas/testsuite/gas/riscv/zicbom-fail.l | 7 +++++++
>> > gas/testsuite/gas/riscv/zicbom-fail.s | 7 +++++++
>> > gas/testsuite/gas/riscv/zicbom.d | 15 +++++++++++++++
>> > gas/testsuite/gas/riscv/zicbom.s | 7 +++++++
>> > gas/testsuite/gas/riscv/zicbop-fail.d | 3 +++
>> > gas/testsuite/gas/riscv/zicbop-fail.l | 4 ++++
>> > gas/testsuite/gas/riscv/zicbop-fail.s | 4 ++++
>> > gas/testsuite/gas/riscv/zicbop.d | 12 ++++++++++++
>> > gas/testsuite/gas/riscv/zicbop.s | 4 ++++
>> > gas/testsuite/gas/riscv/zicboz-fail.d | 3 +++
>> > gas/testsuite/gas/riscv/zicboz-fail.l | 3 +++
>> > gas/testsuite/gas/riscv/zicboz-fail.s | 3 +++
>> > gas/testsuite/gas/riscv/zicboz.d | 12 ++++++++++++
>> > gas/testsuite/gas/riscv/zicboz.s | 4 ++++
>> > include/opcode/riscv-opc.h | 16 ++++++++++++++++
>> > include/opcode/riscv.h | 3 +++
>> > opcodes/riscv-dis.c | 4 ++++
>> > opcodes/riscv-opc.c | 9 +++++++++
>> > 21 files changed, 150 insertions(+)
>> > create mode 100644 gas/testsuite/gas/riscv/zicbom-fail.d
>> > create mode 100644 gas/testsuite/gas/riscv/zicbom-fail.l
>> > create mode 100644 gas/testsuite/gas/riscv/zicbom-fail.s
>> > create mode 100644 gas/testsuite/gas/riscv/zicbom.d
>> > create mode 100644 gas/testsuite/gas/riscv/zicbom.s
>> > create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.d
>> > create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.l
>> > create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.s
>> > create mode 100644 gas/testsuite/gas/riscv/zicbop.d
>> > create mode 100644 gas/testsuite/gas/riscv/zicbop.s
>> > create mode 100644 gas/testsuite/gas/riscv/zicboz-fail.d
>> > create mode 100644 gas/testsuite/gas/riscv/zicboz-fail.l
>> > create mode 100644 gas/testsuite/gas/riscv/zicboz-fail.s
>> > create mode 100644 gas/testsuite/gas/riscv/zicboz.d
>> > create mode 100644 gas/testsuite/gas/riscv/zicboz.s
>> >
>> >
>> > base-commit: a37603c43f8da7983ed53b567ea30ce66066daa2
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-04-01 4:15 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-09 2:29 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Tsukasa OI
2022-02-09 2:29 ` [PATCH 1/5] RISC-V: Add mininal support for Zicbo[mpz] Tsukasa OI
2022-02-09 2:29 ` [PATCH 2/5] RISC-V: Cache management instructions Tsukasa OI
2022-02-09 2:29 ` [PATCH 3/5] RISC-V: Cache management instruction testcases Tsukasa OI
2022-02-09 2:29 ` [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set Tsukasa OI
2022-02-25 2:50 ` Nelson Chu
2022-02-25 7:07 ` Tsukasa OI
2022-03-18 7:50 ` Nelson Chu
2022-02-09 2:29 ` [PATCH 5/5] RISC-V: Prefetch hint instruction testcases Tsukasa OI
2022-04-01 3:33 ` [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Palmer Dabbelt
2022-04-01 4:04 ` Kito Cheng
2022-04-01 4:15 ` Palmer Dabbelt
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