[Bug target/112817] New: RISC-V: RVV: provide a preprocessor macro for VLS codegen

[Bug target/112817] New: RISC-V: RVV: provide a preprocessor macro for VLS codegen

[vineetg at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

            Bug ID: 112817
           Summary: RISC-V: RVV: provide a preprocessor macro for VLS
                    codegen
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: vineetg at gcc dot gnu.org
                CC: ewlu at rivosinc dot com, juzhe.zhong at rivai dot ai,
                    rdapp at gcc dot gnu.org
  Target Milestone: ---

LLVM toggle for setting up fixed vector length using -mrvv-vector-bits=zvl
(which in turn derives VL from -march=...-vl256) also generates a preprocessor
define __riscv_v_fixed_vlen.

gcc doesn't, which is a bit of pain for downstream projects such as xsimd.

Granted the C-API document [1] doesn't specify this, generation by llvm and
more importantly usage in downstream projects seems good enough of a
requirement to have it in gcc as well.

[1] https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Severity|normal                      |enhancement

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
>gcc doesn't, which is a bit of pain for downstream projects such as xsimd.

Does it even make sense to define this? Projects like xsimd seems to be good
for fixed length SIMD but it seems to have a broken idea for non-fixed length
SIMD like SVE and RVV. Would it better to have xsimd provide better interfaces
instead for non-fixed length vectors and not provide a fixed length API at all?

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Note the reality is xsimd was not thought out for SIMD but rather just fixed
length extensions. It seems more like a major shift that needs to happen to
these libraries and stop just thinking fixed length registers.

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

[vineetg at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

Vineet Gupta <vineetg at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |vineetg at gcc dot gnu.org

--- Comment #3 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
I agree, but what xsimd does is not under our control. Whoever wants to use
xsimd for whatever reasons, we can allow gcc to be used similarly to llvm and
certainly not for lack of a trivial define.

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

--- Comment #4 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Vineet Gupta from comment #3)
> I agree, but what xsimd does is not under our control. Whoever wants to use
> xsimd for whatever reasons, we can allow gcc to be used similarly to llvm
> and certainly not for lack of a trivial define.

What I am trying to say is almost all of these "SIMD" libraries were done to
wrap x86_64 SIMD and is almost done in a bad form in general. I noticed that
when working on AARCH64 (even before SVE). they push the idea of a low level
wrapper just because "it is easier" rather than higher level concepts. xsimd,
even the whole C++ SIMD library seems to push low level wrappers rather than
high level concepts that could be optimized.

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

--- Comment #5 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Support VLS codegen with -mrvv-vector-bits and attribute is reasonable to be
landed on GCC-14.

But currently we are busy with fixing bugs (me, Robin, Lixu@eswin, Li
Pan@intel).
You can see gcc-patch list...


Could you first implement -mrvv-vector-bits feature ?

I have support it in rvv-next, but I don't have time to migrate that into trunk
GCC.

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

[vineetg at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

--- Comment #6 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
(In reply to JuzheZhong from comment #5)

> Support VLS codegen with -mrvv-vector-bits and attribute is reasonable to be
> landed on GCC-14.

I don't think that is the reqmt for this issue. Just defining the preprocessor
flag with existing gcc toggle for VLS codegen should be enough - as long as it
generates same macro as llvm.

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

--- Comment #7 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
(In reply to Vineet Gupta from comment #6)
> (In reply to JuzheZhong from comment #5)
> 
> > Support VLS codegen with -mrvv-vector-bits and attribute is reasonable to be
> > landed on GCC-14.
> 
> I don't think that is the reqmt for this issue. Just defining the
> preprocessor flag with existing gcc toggle for VLS codegen should be enough
> - as long as it generates same macro as llvm.

So, what do you mean ? I don't understand.
If you doesn't need attribute, how to fix the issue.

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

[kito at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

Kito Cheng <kito at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |kito at gcc dot gnu.org

--- Comment #8 from Kito Cheng <kito at gcc dot gnu.org> ---
This topic has raised at last RISC-V GCC sync meeting, and one action item for
me is chat with JuzheZhong about -mrvv-vector-bits=zvl / __riscv_v_fixed_vlen /
riscv_rvv_vector_bits stuffs

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

[vineetg at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

--- Comment #9 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
(In reply to JuzheZhong from comment #5)
> Support VLS codegen with -mrvv-vector-bits and attribute is reasonable to be
> landed on GCC-14.
> 
> Could you first implement -mrvv-vector-bits feature ?
> 
> I have support it in rvv-next, but I don't have time to migrate that into
> trunk GCC.

I presume you are referring to https://github.com/riscv-collab/riscv-gcc.git
and #riscv-gcc-rvv-next

I don't see the attribute support. Is it called something else there ?

I was looking for a new entry in gcc/c-family/c-attribs.cc or would be
somewhere else.

[Bug target/112817] RISC-V: RVV: provide attribute riscv_rvv_vector_bits for VLS codegen

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

--- Comment #10 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Yes. I haven't support VLS attributes. I guess kito may have some ideas.

[Bug target/112817] RISC-V: RVV: provide attribute riscv_rvv_vector_bits for VLS codegen

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

--- Comment #11 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Vineet Gupta from comment #9)
> I was looking for a new entry in gcc/c-family/c-attribs.cc or would be
> somewhere else.

It would more likely be in config/riscv/riscv.cc defined in
riscv_attribute_table.

[Bug target/112817] RISC-V: RVV: provide attribute riscv_rvv_vector_bits for VLS codegen

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

--- Comment #12 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Hi, Vineet.

Are you going to support VLS compile option and attributes?

If not, I can ask other RISC-V folks to do that.

Thanks.

[Bug target/112817] RISC-V: RVV: provide attribute riscv_rvv_vector_bits for VLS codegen

[vineetg at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

--- Comment #13 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
Yeah Greg from Rivos started working on it. He'll update here as he makes
progress.

[Bug target/112817] RISC-V: RVV: provide attribute riscv_rvv_vector_bits for VLS codegen

[vineetg at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

Vineet Gupta <vineetg at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |ASSIGNED
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2024-03-06

--- Comment #14 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
To summarize this needs following 3 things

1. preprocessor macro __riscv_v_fixed_vlen if -march has explicit xxxvl
specified 
2. implement gcc toggle -mrvv-vector-bits=zvl which essentially copies the xxx
from -march string
3. Implement attribute riscv_rvv_vector_bits to specify vector length for user
types: cfr. https://godbolt.org/z/5Pc4PzPvs, https://godbolt.org/z/9hdMqh3jf,
https://godbolt.org/z/9WKM8s5rq

[Bug target/112817] RISC-V: RVV: provide attribute riscv_rvv_vector_bits for VLS codegen

[vineetg at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

--- Comment #15 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
(In reply to Vineet Gupta from comment #14)
> 2. implement gcc toggle -mrvv-vector-bits=zvl which essentially copies the
> xxx from -march string

Done:

commit 0a01d1232ff0a8b094270fbf45c9fd0ea46df19f
Author: Pan Li <pan2.li@intel.com>
Date:   Fri Feb 23 15:37:28 2024 +0800

    RISC-V: Introduce gcc option mrvv-vector-bits for RVV

    This patch would like to introduce one new gcc option for RVV. To
    appoint the bits size of one RVV vector register. Valid arguments to
    '-mrvv-vector-bits=' are:

    * scalable
    * zvl

    The scalable will pick up the zvl*b in the march as the minimal vlen.
    For example, the minimal vlen will be 512 when march=rv64gcv_zvl512b
    and mrvv-vector-bits=scalable.

    The zvl will pick up the zvl*b in the march as exactly vlen.
    For example, the vlen will be 1024 exactly when march=rv64gcv_zvl1024b
    and mrvv-vector-bits=zvl.

    The internal option --param=riscv-autovec-preference will be replaced
    by option -mrvv-vector-bits. Aka:

    * -mrvv-vector-bits=scalable indicates
--param=riscv-autovec-preference=scalable
    * -mrvv-vector-bits=zvl indicates
--param=riscv-autovec-preference=fixed-vlmax

    You can also take -fno-tree-vectorize for
--param=riscv-autovec-preference=none.
    The internal option --param=riscv-autovec-preference is unavailable after
this
    patch.