* [PATCH v5 01/10] RISC-V: autovec: Add new predicates and function prototypes
2023-04-26 21:45 [PATCH v5 00/10] RISC-V: autovec: Add autovec support Michael Collison
@ 2023-04-26 21:45 ` Michael Collison
2023-04-28 22:28 ` Jeff Law
2023-04-26 21:45 ` [PATCH v5 02/10] RISC-V: autovec: Export policy functions to global scope Michael Collison
` (8 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: Michael Collison @ 2023-04-26 21:45 UTC (permalink / raw)
To: gcc-patches
2023-04-24 Michael Collison <collison@rivosinc.com>
Juzhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-protos.h
(riscv_vector_preferred_simd_mode): New.
(riscv_vector_mask_mode_p): Ditto.
(riscv_vector_get_mask_mode): Ditto.
(emit_vlmax_vsetvl): Ditto.
(get_mask_policy_no_pred): Ditto.
(get_tail_policy_no_pred): Ditto.
(vlmul_field_enum): Ditto.
* config/riscv/riscv-v.cc (emit_vlmax_vsetvl):
Remove static scope.
* config/riscv/predicates.md (p_reg_or_const_csr_operand):
New predicate.
(vector_reg_or_const_dup_operand): Ditto.
* config/riscv/riscv-opts.h (riscv_vector_bits_enum): New enum.
(riscv_vector_lmul_enum): Ditto.
(vlmul_field_enum): Ditto.
---
gcc/config/riscv/predicates.md | 13 +++++++++++++
gcc/config/riscv/riscv-opts.h | 29 +++++++++++++++++++++++++++++
gcc/config/riscv/riscv-protos.h | 9 +++++++++
3 files changed, 51 insertions(+)
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 8654dbc5943..b3f2d622c7b 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -264,6 +264,14 @@
})
;; Predicates for the V extension.
+(define_special_predicate "p_reg_or_const_csr_operand"
+ (match_code "reg, subreg, const_int")
+{
+ if (CONST_INT_P (op))
+ return satisfies_constraint_K (op);
+ return GET_MODE (op) == Pmode;
+})
+
(define_special_predicate "vector_length_operand"
(ior (match_operand 0 "pmode_register_operand")
(match_operand 0 "const_csr_operand")))
@@ -291,6 +299,11 @@
(and (match_code "const_vector")
(match_test "rtx_equal_p (op, riscv_vector::gen_scalar_move_mask (GET_MODE (op)))")))
+(define_predicate "vector_reg_or_const_dup_operand"
+ (ior (match_operand 0 "register_operand")
+ (match_test "const_vec_duplicate_p (op)
+ && !CONST_POLY_INT_P (CONST_VECTOR_ELT (op, 0))")))
+
(define_predicate "vector_mask_operand"
(ior (match_operand 0 "register_operand")
(match_operand 0 "vector_all_trues_mask_operand")))
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index cf0cd669be4..af77df11430 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -67,6 +67,35 @@ enum stack_protector_guard {
SSP_GLOBAL /* global canary */
};
+/* RISC-V auto-vectorization preference. */
+enum riscv_autovec_preference_enum {
+ NO_AUTOVEC,
+ RVV_SCALABLE,
+ RVV_FIXED_VLMAX
+};
+
+/* vectorization factor. */
+enum riscv_vector_lmul_enum
+{
+ RVV_LMUL1 = 1,
+ RVV_LMUL2 = 2,
+ RVV_LMUL4 = 4,
+ RVV_LMUL8 = 8
+};
+
+enum vlmul_field_enum
+{
+ VLMUL_FIELD_000, /* LMUL = 1. */
+ VLMUL_FIELD_001, /* LMUL = 2. */
+ VLMUL_FIELD_010, /* LMUL = 4. */
+ VLMUL_FIELD_011, /* LMUL = 8. */
+ VLMUL_FIELD_100, /* RESERVED. */
+ VLMUL_FIELD_101, /* LMUL = 1/8. */
+ VLMUL_FIELD_110, /* LMUL = 1/4. */
+ VLMUL_FIELD_111, /* LMUL = 1/2. */
+ MAX_VLMUL_FIELD
+};
+
#define MASK_ZICSR (1 << 0)
#define MASK_ZIFENCEI (1 << 1)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 5244e8dcbf0..55056222e57 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -237,4 +237,13 @@ extern const char*
th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
#endif
+/* Routines implemented in riscv-v.cc. */
+
+namespace riscv_vector {
+extern machine_mode riscv_vector_preferred_simd_mode (scalar_mode mode);
+extern bool riscv_vector_mask_mode_p (machine_mode);
+extern opt_machine_mode riscv_vector_get_mask_mode (machine_mode mode);
+extern rtx get_mask_policy_no_pred ();
+extern rtx get_tail_policy_no_pred ();
+}
#endif /* ! GCC_RISCV_PROTOS_H */
--
2.34.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v5 01/10] RISC-V: autovec: Add new predicates and function prototypes
2023-04-26 21:45 ` [PATCH v5 01/10] RISC-V: autovec: Add new predicates and function prototypes Michael Collison
@ 2023-04-28 22:28 ` Jeff Law
0 siblings, 0 replies; 19+ messages in thread
From: Jeff Law @ 2023-04-28 22:28 UTC (permalink / raw)
To: Michael Collison, gcc-patches
On 4/26/23 15:45, Michael Collison wrote:
> 2023-04-24 Michael Collison <collison@rivosinc.com>
> Juzhe Zhong <juzhe.zhong@rivai.ai>
>
> * config/riscv/riscv-protos.h
> (riscv_vector_preferred_simd_mode): New.
> (riscv_vector_mask_mode_p): Ditto.
> (riscv_vector_get_mask_mode): Ditto.
> (emit_vlmax_vsetvl): Ditto.
> (get_mask_policy_no_pred): Ditto.
> (get_tail_policy_no_pred): Ditto.
> (vlmul_field_enum): Ditto.
> * config/riscv/riscv-v.cc (emit_vlmax_vsetvl):
> Remove static scope.
> * config/riscv/predicates.md (p_reg_or_const_csr_operand):
> New predicate.
> (vector_reg_or_const_dup_operand): Ditto.
> * config/riscv/riscv-opts.h (riscv_vector_bits_enum): New enum.
> (riscv_vector_lmul_enum): Ditto.
> (vlmul_field_enum): Ditto.
> ---
> gcc/config/riscv/predicates.md | 13 +++++++++++++
> gcc/config/riscv/riscv-opts.h | 29 +++++++++++++++++++++++++++++
> gcc/config/riscv/riscv-protos.h | 9 +++++++++
> 3 files changed, 51 insertions(+)
>
> diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
> index 8654dbc5943..b3f2d622c7b 100644
> --- a/gcc/config/riscv/predicates.md
> +++ b/gcc/config/riscv/predicates.md
> @@ -264,6 +264,14 @@
> })
>
> ;; Predicates for the V extension.
> +(define_special_predicate "p_reg_or_const_csr_operand"
> + (match_code "reg, subreg, const_int")
> +{
> + if (CONST_INT_P (op))
> + return satisfies_constraint_K (op);
> + return GET_MODE (op) == Pmode;
> +})
I don't see where this is used? Perhaps defer?
>
> +(define_predicate "vector_reg_or_const_dup_operand"
> + (ior (match_operand 0 "register_operand")
> + (match_test "const_vec_duplicate_p (op)
> + && !CONST_POLY_INT_P (CONST_VECTOR_ELT (op, 0))")))
> +
Similarly.
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index cf0cd669be4..af77df11430 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -67,6 +67,35 @@ enum stack_protector_guard {
> SSP_GLOBAL /* global canary */
> };
>
> +/* RISC-V auto-vectorization preference. */
> +enum riscv_autovec_preference_enum {
> + NO_AUTOVEC,
> + RVV_SCALABLE,
> + RVV_FIXED_VLMAX
> +};
I think these were included in one of Juzhe's patches. So you can
probably drop them.
> +enum vlmul_field_enum
> +{
> + VLMUL_FIELD_000, /* LMUL = 1. */
> + VLMUL_FIELD_001, /* LMUL = 2. */
> + VLMUL_FIELD_010, /* LMUL = 4. */
> + VLMUL_FIELD_011, /* LMUL = 8. */
> + VLMUL_FIELD_100, /* RESERVED. */
> + VLMUL_FIELD_101, /* LMUL = 1/8. */
> + VLMUL_FIELD_110, /* LMUL = 1/4. */
> + VLMUL_FIELD_111, /* LMUL = 1/2. */
> + MAX_VLMUL_FIELD
> +};
AFAICT these are unused. Perhaps defer this hunk?
So no real objections. There's one hunk that clearly shouldn't be
applied as it's in one of Juzhe's recently applied patches. There's a
few hunks that don't look like they're used -- if you have strong
reasons to believe they will be needed, go ahead and include them.
Otherwise drop them for now.
OK for the trunk after addressing the comments above.
jeff
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v5 02/10] RISC-V: autovec: Export policy functions to global scope
2023-04-26 21:45 [PATCH v5 00/10] RISC-V: autovec: Add autovec support Michael Collison
2023-04-26 21:45 ` [PATCH v5 01/10] RISC-V: autovec: Add new predicates and function prototypes Michael Collison
@ 2023-04-26 21:45 ` Michael Collison
2023-04-28 22:15 ` Jeff Law
2023-04-26 21:45 ` [PATCH v5 03/10] RISC-V:autovec: Add auto-vectorization support functions Michael Collison
` (7 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: Michael Collison @ 2023-04-26 21:45 UTC (permalink / raw)
To: gcc-patches
2023-03-02 Michael Collison <collison@rivosinc.com>
Juzhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred):
Remove static declaration to to make externally visible.
(get_mask_policy_for_pred): Ditto.
* config/riscv/riscv-vector-builtins.h (get_tail_policy_for_pred):
New external declaration.
(get_mask_policy_for_pred): Ditto.
---
gcc/config/riscv/riscv-vector-builtins.cc | 4 ++--
gcc/config/riscv/riscv-vector-builtins.h | 3 +++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 01cea23d3e6..1ed9e4acc40 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -2493,7 +2493,7 @@ use_real_merge_p (enum predication_type_index pred)
/* Get TAIL policy for predication. If predication indicates TU, return the TU.
Otherwise, return the prefer default configuration. */
-static rtx
+rtx
get_tail_policy_for_pred (enum predication_type_index pred)
{
if (pred == PRED_TYPE_tu || pred == PRED_TYPE_tum || pred == PRED_TYPE_tumu)
@@ -2503,7 +2503,7 @@ get_tail_policy_for_pred (enum predication_type_index pred)
/* Get MASK policy for predication. If predication indicates MU, return the MU.
Otherwise, return the prefer default configuration. */
-static rtx
+rtx
get_mask_policy_for_pred (enum predication_type_index pred)
{
if (pred == PRED_TYPE_tumu || pred == PRED_TYPE_mu)
diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h
index 8ffb9d33e33..de3fd6ca290 100644
--- a/gcc/config/riscv/riscv-vector-builtins.h
+++ b/gcc/config/riscv/riscv-vector-builtins.h
@@ -483,6 +483,9 @@ extern rvv_builtin_types_t builtin_types[NUM_VECTOR_TYPES + 1];
extern function_instance get_read_vl_instance (void);
extern tree get_read_vl_decl (void);
+extern rtx get_tail_policy_for_pred (enum predication_type_index pred);
+extern rtx get_mask_policy_for_pred (enum predication_type_index pred);
+
inline tree
rvv_arg_type_info::get_scalar_type (vector_type_index type_idx) const
{
--
2.34.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v5 03/10] RISC-V:autovec: Add auto-vectorization support functions
2023-04-26 21:45 [PATCH v5 00/10] RISC-V: autovec: Add autovec support Michael Collison
2023-04-26 21:45 ` [PATCH v5 01/10] RISC-V: autovec: Add new predicates and function prototypes Michael Collison
2023-04-26 21:45 ` [PATCH v5 02/10] RISC-V: autovec: Export policy functions to global scope Michael Collison
@ 2023-04-26 21:45 ` Michael Collison
2023-04-28 22:19 ` Jeff Law
2023-05-03 10:53 ` Kito Cheng
2023-04-26 21:45 ` [PATCH v5 04/10] RISC-V:autovec: Add target vectorization hooks Michael Collison
` (6 subsequent siblings)
9 siblings, 2 replies; 19+ messages in thread
From: Michael Collison @ 2023-04-26 21:45 UTC (permalink / raw)
To: gcc-patches
2023-04-24 Michael Collison <collison@rivosinc.com>
Juzhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-v.cc
(riscv_vector_preferred_simd_mode): New function.
(get_mask_policy_no_pred): Ditto.
(get_tail_policy_no_pred): Ditto.
(riscv_vector_mask_mode_p): Ditto.
(riscv_vector_get_mask_mode): Ditto.
---
gcc/config/riscv/riscv-v.cc | 79 +++++++++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 392f5d02e17..ecd98680d64 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -39,9 +39,11 @@
#include "emit-rtl.h"
#include "tm_p.h"
#include "target.h"
+#include "targhooks.h"
#include "expr.h"
#include "optabs.h"
#include "tm-constrs.h"
+#include "riscv-vector-builtins.h"
#include "rtx-vector-builder.h"
using namespace riscv_vector;
@@ -176,6 +178,46 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul)
return ratio;
}
+/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE for RVV. */
+
+machine_mode
+riscv_vector_preferred_simd_mode (scalar_mode mode)
+{
+ if (!TARGET_VECTOR)
+ return word_mode;
+
+ switch (mode)
+ {
+ case E_QImode:
+ return VNx8QImode;
+ break;
+ case E_HImode:
+ return VNx4HImode;
+ break;
+ case E_SImode:
+ return VNx2SImode;
+ break;
+ case E_DImode:
+ if (riscv_vector_elen_flags != MASK_VECTOR_ELEN_32
+ && riscv_vector_elen_flags != MASK_VECTOR_ELEN_FP_32)
+ return VNx1DImode;
+ break;
+ case E_SFmode:
+ if (TARGET_HARD_FLOAT && riscv_vector_elen_flags != MASK_VECTOR_ELEN_32
+ && riscv_vector_elen_flags != MASK_VECTOR_ELEN_64)
+ return VNx2SFmode;
+ break;
+ case E_DFmode:
+ if (TARGET_DOUBLE_FLOAT && TARGET_VECTOR_ELEN_FP_64)
+ return VNx1DFmode;
+ break;
+ default:
+ break;
+ }
+
+ return word_mode;
+}
+
/* Emit an RVV unmask && vl mov from SRC to DEST. */
static void
emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len,
@@ -421,6 +463,43 @@ get_avl_type_rtx (enum avl_type type)
return gen_int_mode (type, Pmode);
}
+rtx
+get_mask_policy_no_pred ()
+{
+ return get_mask_policy_for_pred (PRED_TYPE_none);
+}
+
+rtx
+get_tail_policy_no_pred ()
+{
+ return get_mask_policy_for_pred (PRED_TYPE_none);
+}
+
+/* Return true if it is a RVV mask mode. */
+bool
+riscv_vector_mask_mode_p (machine_mode mode)
+{
+ return (mode == VNx1BImode || mode == VNx2BImode || mode == VNx4BImode
+ || mode == VNx8BImode || mode == VNx16BImode || mode == VNx32BImode
+ || mode == VNx64BImode);
+}
+
+/* Implement TARGET_VECTORIZE_GET_MASK_MODE for RVV. */
+
+opt_machine_mode
+riscv_vector_get_mask_mode (machine_mode mode)
+{
+ machine_mode mask_mode;
+ int nf = 1;
+
+ FOR_EACH_MODE_IN_CLASS (mask_mode, MODE_VECTOR_BOOL)
+ if (GET_MODE_INNER (mask_mode) == BImode
+ && known_eq (GET_MODE_NUNITS (mask_mode) * nf, GET_MODE_NUNITS (mode))
+ && riscv_vector_mask_mode_p (mask_mode))
+ return mask_mode;
+ return default_get_mask_mode (mode);
+}
+
/* Return the RVV vector mode that has NUNITS elements of mode INNER_MODE.
This function is not only used by builtins, but also will be used by
auto-vectorization in the future. */
--
2.34.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v5 03/10] RISC-V:autovec: Add auto-vectorization support functions
2023-04-26 21:45 ` [PATCH v5 03/10] RISC-V:autovec: Add auto-vectorization support functions Michael Collison
@ 2023-04-28 22:19 ` Jeff Law
2023-05-03 10:53 ` Kito Cheng
1 sibling, 0 replies; 19+ messages in thread
From: Jeff Law @ 2023-04-28 22:19 UTC (permalink / raw)
To: Michael Collison, gcc-patches
On 4/26/23 15:45, Michael Collison wrote:
> 2023-04-24 Michael Collison <collison@rivosinc.com>
> Juzhe Zhong <juzhe.zhong@rivai.ai>
>
> * config/riscv/riscv-v.cc
> (riscv_vector_preferred_simd_mode): New function.
> (get_mask_policy_no_pred): Ditto.
> (get_tail_policy_no_pred): Ditto.
> (riscv_vector_mask_mode_p): Ditto.
> (riscv_vector_get_mask_mode): Ditto.
> ---
> @@ -176,6 +178,46 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul)
> return ratio;
> }
>
> +/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE for RVV. */
Doesn't really tell me much.
/* Return the preferred SIMD mode for MODE. */
> @@ -421,6 +463,43 @@ get_avl_type_rtx (enum avl_type type)
> return gen_int_mode (type, Pmode);
> }
>
> +rtx
> +get_mask_policy_no_pred ()
> +{
> + return get_mask_policy_for_pred (PRED_TYPE_none);
> +}
> +
> +rtx
> +get_tail_policy_no_pred ()
> +{
> + return get_mask_policy_for_pred (PRED_TYPE_none);
> +}
I'm guessing the call in get_tail_policy_no_pred should have been to
get_tail_policy_for_pred rather than get_mask_policy_for_pred.
^^^^ ^^^^
A short function comment for the two functions seems appropriate.
> +
> +/* Implement TARGET_VECTORIZE_GET_MASK_MODE for RVV. */
How about
/* Return the appropriate mask mode for MODE. */
OK with the trivial fixes noted above.
Jeff
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v5 03/10] RISC-V:autovec: Add auto-vectorization support functions
2023-04-26 21:45 ` [PATCH v5 03/10] RISC-V:autovec: Add auto-vectorization support functions Michael Collison
2023-04-28 22:19 ` Jeff Law
@ 2023-05-03 10:53 ` Kito Cheng
2023-05-03 17:31 ` Michael Collison
1 sibling, 1 reply; 19+ messages in thread
From: Kito Cheng @ 2023-05-03 10:53 UTC (permalink / raw)
To: Michael Collison; +Cc: gcc-patches
> @@ -176,6 +178,46 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul)
> return ratio;
> }
>
> +/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE for RVV. */
> +
> +machine_mode
> +riscv_vector_preferred_simd_mode (scalar_mode mode)
JuZhe's patch[1] has been implemented and his version handles
types/modes in the right way IMO,
so I would like to take his version for this hook.
[1] https://patchwork.sourceware.org/project/gcc/patch/20230419164214.1032017-3-juzhe.zhong@rivai.ai/
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v5 03/10] RISC-V:autovec: Add auto-vectorization support functions
2023-05-03 10:53 ` Kito Cheng
@ 2023-05-03 17:31 ` Michael Collison
2023-05-06 20:13 ` Jeff Law
0 siblings, 1 reply; 19+ messages in thread
From: Michael Collison @ 2023-05-03 17:31 UTC (permalink / raw)
To: Kito Cheng, juzhe.zhong; +Cc: gcc-patches
HI Kito,
I see there have been many comments on the
"riscv_vector_preferred_simd_mode" hook, is there an updated version?
On 5/3/23 06:53, Kito Cheng wrote:
>> @@ -176,6 +178,46 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul)
>> return ratio;
>> }
>>
>> +/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE for RVV. */
>> +
>> +machine_mode
>> +riscv_vector_preferred_simd_mode (scalar_mode mode)
> JuZhe's patch[1] has been implemented and his version handles
> types/modes in the right way IMO,
> so I would like to take his version for this hook.
>
> [1] https://patchwork.sourceware.org/project/gcc/patch/20230419164214.1032017-3-juzhe.zhong@rivai.ai/
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v5 03/10] RISC-V:autovec: Add auto-vectorization support functions
2023-05-03 17:31 ` Michael Collison
@ 2023-05-06 20:13 ` Jeff Law
0 siblings, 0 replies; 19+ messages in thread
From: Jeff Law @ 2023-05-06 20:13 UTC (permalink / raw)
To: Michael Collison, Kito Cheng, juzhe.zhong; +Cc: gcc-patches
On 5/3/23 11:31, Michael Collison wrote:
> HI Kito,
>
> I see there have been many comments on the
> "riscv_vector_preferred_simd_mode" hook, is there an updated version?
I think there's a version on the trunk now. So if there's updates to
do, let's do them relative to what's on the trunk.
Jeff
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v5 04/10] RISC-V:autovec: Add target vectorization hooks
2023-04-26 21:45 [PATCH v5 00/10] RISC-V: autovec: Add autovec support Michael Collison
` (2 preceding siblings ...)
2023-04-26 21:45 ` [PATCH v5 03/10] RISC-V:autovec: Add auto-vectorization support functions Michael Collison
@ 2023-04-26 21:45 ` Michael Collison
2023-05-03 10:59 ` Kito Cheng
2023-04-26 21:45 ` [PATCH v5 05/10] RISC-V:autovec: Add autovectorization patterns for binary integer & len_load/store Michael Collison
` (5 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: Michael Collison @ 2023-04-26 21:45 UTC (permalink / raw)
To: gcc-patches
2023-04-24 Michael Collison <collison@rivosinc.com>
Juzhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv.cc
(riscv_estimated_poly_value): Implement
TARGET_ESTIMATED_POLY_VALUE.
(riscv_preferred_simd_mode): Implement
TARGET_VECTORIZE_PREFERRED_SIMD_MODE.
(riscv_autovectorize_vector_modes): Implement
TARGET_AUTOVECTORIZE_VECTOR_MODES.
(riscv_get_mask_mode): Implement TARGET_VECTORIZE_GET_MASK_MODE.
(riscv_empty_mask_is_expensive): Implement
TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE.
(riscv_vectorize_create_costs): Implement
TARGET_VECTORIZE_CREATE_COSTS.
(TARGET_ESTIMATED_POLY_VALUE): Register target macro.
(TARGET_VECTORIZE_GET_MASK_MODE): Ditto.
(TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE): Ditto.
---
gcc/config/riscv/riscv.cc | 129 ++++++++++++++++++++++++++++++++++++++
1 file changed, 129 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index dc47434fac4..77209b161f6 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -60,6 +60,15 @@ along with GCC; see the file COPYING3. If not see
#include "opts.h"
#include "tm-constrs.h"
#include "rtl-iter.h"
+#include "gimple.h"
+#include "cfghooks.h"
+#include "cfgloop.h"
+#include "cfgrtl.h"
+#include "sel-sched.h"
+#include "fold-const.h"
+#include "gimple-iterator.h"
+#include "gimple-expr.h"
+#include "tree-vectorizer.h"
/* This file should be included last. */
#include "target-def.h"
@@ -275,6 +284,9 @@ poly_uint16 riscv_vector_chunks;
/* The number of bytes in a vector chunk. */
unsigned riscv_bytes_per_vector_chunk;
+/* Prefer vf for auto-vectorizer. */
+unsigned riscv_vectorization_factor;
+
/* Index R is the smallest register class that contains register R. */
const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = {
GR_REGS, GR_REGS, GR_REGS, GR_REGS,
@@ -6363,6 +6375,9 @@ riscv_option_override (void)
/* Convert -march to a chunks count. */
riscv_vector_chunks = riscv_convert_vector_bits ();
+
+ if (TARGET_VECTOR)
+ riscv_vectorization_factor = RVV_LMUL1;
}
/* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
@@ -7057,6 +7072,105 @@ riscv_dwarf_poly_indeterminate_value (unsigned int i, unsigned int *factor,
return RISCV_DWARF_VLENB;
}
+/* Implement TARGET_ESTIMATED_POLY_VALUE.
+ Look into the tuning structure for an estimate.
+ KIND specifies the type of requested estimate: min, max or likely.
+ For cores with a known RVV width all three estimates are the same.
+ For generic RVV tuning we want to distinguish the maximum estimate from
+ the minimum and likely ones.
+ The likely estimate is the same as the minimum in that case to give a
+ conservative behavior of auto-vectorizing with RVV when it is a win
+ even for 128-bit RVV.
+ When RVV width information is available VAL.coeffs[1] is multiplied by
+ the number of VQ chunks over the initial Advanced SIMD 128 bits. */
+
+static HOST_WIDE_INT
+riscv_estimated_poly_value (poly_int64 val,
+ poly_value_estimate_kind kind = POLY_VALUE_LIKELY)
+{
+ unsigned int width_source = BITS_PER_RISCV_VECTOR.is_constant ()
+ ? (unsigned int) BITS_PER_RISCV_VECTOR.to_constant ()
+ : (unsigned int) RVV_SCALABLE;
+
+ /* If there is no core-specific information then the minimum and likely
+ values are based on 128-bit vectors and the maximum is based on
+ the architectural maximum of 65536 bits. */
+ if (width_source == RVV_SCALABLE)
+ switch (kind)
+ {
+ case POLY_VALUE_MIN:
+ case POLY_VALUE_LIKELY:
+ return val.coeffs[0];
+
+ case POLY_VALUE_MAX:
+ return val.coeffs[0] + val.coeffs[1] * 15;
+ }
+
+ /* Allow BITS_PER_RISCV_VECTOR to be a bitmask of different VL, treating the
+ lowest as likely. This could be made more general if future -mtune
+ options need it to be. */
+ if (kind == POLY_VALUE_MAX)
+ width_source = 1 << floor_log2 (width_source);
+ else
+ width_source = least_bit_hwi (width_source);
+
+ /* If the core provides width information, use that. */
+ HOST_WIDE_INT over_128 = width_source - 128;
+ return val.coeffs[0] + val.coeffs[1] * over_128 / 128;
+}
+
+/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
+
+static machine_mode
+riscv_preferred_simd_mode (scalar_mode mode)
+{
+ if (TARGET_VECTOR)
+ return riscv_vector::riscv_vector_preferred_simd_mode (mode);
+
+ return word_mode;
+}
+
+/* Implement TARGET_AUTOVECTORIZE_VECTOR_MODES for RVV. */
+static unsigned int
+riscv_autovectorize_vector_modes (vector_modes *modes, bool)
+{
+ if (!TARGET_VECTOR)
+ return 0;
+
+ if (riscv_vectorization_factor == RVV_LMUL1)
+ {
+ modes->safe_push (VNx16QImode);
+ modes->safe_push (VNx8QImode);
+ modes->safe_push (VNx4QImode);
+ modes->safe_push (VNx2QImode);
+ }
+
+ return 0;
+}
+
+/* Implement TARGET_VECTORIZE_GET_MASK_MODE. */
+
+static opt_machine_mode
+riscv_get_mask_mode (machine_mode mode)
+{
+ machine_mode mask_mode = VOIDmode;
+ if (TARGET_VECTOR
+ && riscv_vector::riscv_vector_get_mask_mode (mode).exists (&mask_mode))
+ return mask_mode;
+
+ return default_get_mask_mode (mode);
+}
+
+/* Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. Assume for now that
+ it isn't worth branching around empty masked ops (including masked
+ stores). */
+
+static bool
+riscv_empty_mask_is_expensive (unsigned)
+{
+ return false;
+}
+
/* Return true if a shift-amount matches the trailing cleared bits on
a bitmask. */
@@ -7382,6 +7496,21 @@ riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
#undef TARGET_VERIFY_TYPE_CONTEXT
#define TARGET_VERIFY_TYPE_CONTEXT riscv_verify_type_context
+#undef TARGET_ESTIMATED_POLY_VALUE
+#define TARGET_ESTIMATED_POLY_VALUE riscv_estimated_poly_value
+
+#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
+#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE riscv_preferred_simd_mode
+
+#undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES
+#define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES riscv_autovectorize_vector_modes
+
+#undef TARGET_VECTORIZE_GET_MASK_MODE
+#define TARGET_VECTORIZE_GET_MASK_MODE riscv_get_mask_mode
+
+#undef TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE
+#define TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE riscv_empty_mask_is_expensive
+
#undef TARGET_VECTOR_ALIGNMENT
#define TARGET_VECTOR_ALIGNMENT riscv_vector_alignment
--
2.34.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v5 04/10] RISC-V:autovec: Add target vectorization hooks
2023-04-26 21:45 ` [PATCH v5 04/10] RISC-V:autovec: Add target vectorization hooks Michael Collison
@ 2023-05-03 10:59 ` Kito Cheng
0 siblings, 0 replies; 19+ messages in thread
From: Kito Cheng @ 2023-05-03 10:59 UTC (permalink / raw)
To: Michael Collison; +Cc: gcc-patches
> @@ -275,6 +284,9 @@ poly_uint16 riscv_vector_chunks;
> /* The number of bytes in a vector chunk. */
> unsigned riscv_bytes_per_vector_chunk;
>
> +/* Prefer vf for auto-vectorizer. */
> +unsigned riscv_vectorization_factor;
> +
Drop this, we have riscv_autovec_lmul
> /* Index R is the smallest register class that contains register R. */
> const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = {
> GR_REGS, GR_REGS, GR_REGS, GR_REGS,
> @@ -6363,6 +6375,9 @@ riscv_option_override (void)
>
> /* Convert -march to a chunks count. */
> riscv_vector_chunks = riscv_convert_vector_bits ();
> +
> + if (TARGET_VECTOR)
> + riscv_vectorization_factor = RVV_LMUL1;
Drop this, we have riscv_autovec_lmul
> +/* Implement TARGET_AUTOVECTORIZE_VECTOR_MODES for RVV. */
> +static unsigned int
> +riscv_autovectorize_vector_modes (vector_modes *modes, bool)
> +{
> + if (!TARGET_VECTOR)
> + return 0;
> +
> + if (riscv_vectorization_factor == RVV_LMUL1)
Drop this or check with riscv_autovec_lmul.
> + {
> + modes->safe_push (VNx16QImode);
> + modes->safe_push (VNx8QImode);
> + modes->safe_push (VNx4QImode);
> + modes->safe_push (VNx2QImode);
Modes are not consider different VLEN here,
you could ref this patch[1] to see how to get right mode via get_vector_mode
[1] https://patchwork.sourceware.org/project/gcc/patch/20230419164214.1032017-3-juzhe.zhong@rivai.ai/
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v5 05/10] RISC-V:autovec: Add autovectorization patterns for binary integer & len_load/store
2023-04-26 21:45 [PATCH v5 00/10] RISC-V: autovec: Add autovec support Michael Collison
` (3 preceding siblings ...)
2023-04-26 21:45 ` [PATCH v5 04/10] RISC-V:autovec: Add target vectorization hooks Michael Collison
@ 2023-04-26 21:45 ` Michael Collison
2023-04-26 21:45 ` [PATCH v5 06/10] RISC-V:autovec: Add autovectorization tests for add & sub Michael Collison
` (4 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: Michael Collison @ 2023-04-26 21:45 UTC (permalink / raw)
To: gcc-patches
2023-04-25 Michael Collison <collison@rivosinc.com>
Juzhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include
vector-iterators.md.
* config/riscv/vector-auto.md: New file containing
autovectorization patterns.
* config/riscv/vector.md: Remove include of vector-iterators.md
and include vector-auto.md.
---
gcc/config/riscv/riscv.md | 1 +
gcc/config/riscv/vector-auto.md | 74 +++++++++++++++++++++++++++++++++
gcc/config/riscv/vector.md | 4 +-
3 files changed, 77 insertions(+), 2 deletions(-)
create mode 100644 gcc/config/riscv/vector-auto.md
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index bc384d9aedf..7f8f3a6cb18 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -135,6 +135,7 @@
(include "predicates.md")
(include "constraints.md")
(include "iterators.md")
+(include "vector-iterators.md")
;; ....................
;;
diff --git a/gcc/config/riscv/vector-auto.md b/gcc/config/riscv/vector-auto.md
new file mode 100644
index 00000000000..83d2ab6957a
--- /dev/null
+++ b/gcc/config/riscv/vector-auto.md
@@ -0,0 +1,74 @@
+;; Machine description for RISC-V 'V' Extension for GNU compiler.
+;; Copyright (C) 2022-2023 Free Software Foundation, Inc.
+;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
+;; Contributed by Michael Collison (collison@rivosinc.com, Rivos Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; len_load/len_store is a sub-optimal pattern for RVV auto-vectorization support.
+;; We will replace them when len_maskload/len_maskstore is supported in loop vectorizer.
+(define_expand "len_load_<mode>"
+ [(match_operand:V 0 "register_operand")
+ (match_operand:V 1 "memory_operand")
+ (match_operand 2 "vector_length_operand")
+ (match_operand 3 "const_0_operand")]
+ "TARGET_VECTOR"
+{
+ riscv_vector::emit_nonvlmax_op (code_for_pred_mov (<MODE>mode), operands[0],
+ operands[1], operands[2], <VM>mode);
+ DONE;
+})
+
+(define_expand "len_store_<mode>"
+ [(match_operand:V 0 "memory_operand")
+ (match_operand:V 1 "register_operand")
+ (match_operand 2 "vector_length_operand")
+ (match_operand 3 "const_0_operand")]
+ "TARGET_VECTOR"
+{
+ riscv_vector::emit_nonvlmax_op (code_for_pred_mov (<MODE>mode), operands[0],
+ operands[1], operands[2], <VM>mode);
+ DONE;
+})
+
+;; -------------------------------------------------------------------------
+;; ---- [INT] Vector binary patterns
+;; -------------------------------------------------------------------------
+
+(define_expand "<optab><mode>3"
+ [(set (match_operand:VI 0 "register_operand")
+ (any_int_binop:VI (match_operand:VI 1 "<binop_rhs1_predicate>")
+ (match_operand:VI 2 "<binop_rhs2_predicate>")))]
+ "TARGET_VECTOR"
+{
+ using namespace riscv_vector;
+
+ rtx merge = RVV_VUNDEF (<MODE>mode);
+ rtx vl = gen_reg_rtx (Pmode);
+ emit_vlmax_vsetvl (<MODE>mode, vl);
+ rtx mask_policy = get_mask_policy_no_pred ();
+ rtx tail_policy = get_tail_policy_no_pred ();
+ rtx mask = CONSTM1_RTX(<VM>mode);
+ rtx vlmax_avl_p = get_avl_type_rtx (NONVLMAX);
+
+ emit_insn (gen_pred_<optab><mode> (operands[0], mask, merge, operands[1], operands[2],
+ vl, tail_policy, mask_policy, vlmax_avl_p));
+
+ DONE;
+})
+
+
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 0ecca98f20c..2ac5b744503 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -26,8 +26,6 @@
;; - Auto-vectorization (TBD)
;; - Combine optimization (TBD)
-(include "vector-iterators.md")
-
(define_constants [
(INVALID_ATTRIBUTE 255)
(X0_REGNUM 0)
@@ -351,6 +349,8 @@
(symbol_ref "INTVAL (operands[4])")]
(const_int INVALID_ATTRIBUTE)))
+(include "vector-auto.md")
+
;; -----------------------------------------------------------------
;; ---- Miscellaneous Operations
;; -----------------------------------------------------------------
--
2.34.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v5 06/10] RISC-V:autovec: Add autovectorization tests for add & sub
2023-04-26 21:45 [PATCH v5 00/10] RISC-V: autovec: Add autovec support Michael Collison
` (4 preceding siblings ...)
2023-04-26 21:45 ` [PATCH v5 05/10] RISC-V:autovec: Add autovectorization patterns for binary integer & len_load/store Michael Collison
@ 2023-04-26 21:45 ` Michael Collison
2023-04-26 21:45 ` [PATCH v5 07/10] vect: Verify that GET_MODE_NUNITS is a multiple of 2 Michael Collison
` (3 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: Michael Collison @ 2023-04-26 21:45 UTC (permalink / raw)
To: gcc-patches
2023-03-02 Michael Collison <collison@rivosinc.com>
Vineet Gupta <vineetg@rivosinc.com>
* gcc.target/riscv/rvv/autovec: New directory
for autovectorization tests.
* gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New
test to verify code generation of vector add on rv32.
* gcc.target/riscv/rvv/autovec/loop-add.c: New
test to verify code generation of vector add on rv64.
* gcc.target/riscv/rvv/autovec/loop-sub-rv32.c: New
test to verify code generation of vector subtract on rv32.
* gcc.target/riscv/rvv/autovec/loop-sub.c: New
test to verify code generation of vector subtract on rv64.
---
.../riscv/rvv/autovec/loop-add-rv32.c | 24 +++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-add.c | 24 +++++++++++++++++++
.../riscv/rvv/autovec/loop-sub-rv32.c | 24 +++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-sub.c | 24 +++++++++++++++++++
4 files changed, 96 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
new file mode 100644
index 00000000000..bdc3b6892e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] + b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
new file mode 100644
index 00000000000..d7f992c7d27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] + b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
new file mode 100644
index 00000000000..7d0a40ec539
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] - b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
new file mode 100644
index 00000000000..c8900884f83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] - b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v5 07/10] vect: Verify that GET_MODE_NUNITS is a multiple of 2.
2023-04-26 21:45 [PATCH v5 00/10] RISC-V: autovec: Add autovec support Michael Collison
` (5 preceding siblings ...)
2023-04-26 21:45 ` [PATCH v5 06/10] RISC-V:autovec: Add autovectorization tests for add & sub Michael Collison
@ 2023-04-26 21:45 ` Michael Collison
2023-05-02 10:11 ` Richard Sandiford
2023-04-26 21:45 ` [PATCH v5 08/10] RISC-V:autovec: Add autovectorization tests for binary integer Michael Collison
` (2 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: Michael Collison @ 2023-04-26 21:45 UTC (permalink / raw)
To: gcc-patches
While working on autovectorizing for the RISCV port I encountered an issue
where can_duplicate_and_interleave_p assumes that GET_MODE_NUNITS is a
evenly divisible by two. The RISC-V target has vector modes (e.g. VNx1DImode),
where GET_MODE_NUNITS is equal to one.
Tested on RISCV and x86_64-linux-gnu. Okay?
2023-03-09 Michael Collison <collison@rivosinc.com>
* tree-vect-slp.cc (can_duplicate_and_interleave_p):
Check that GET_MODE_NUNITS is a multiple of 2.
---
gcc/tree-vect-slp.cc | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index d73deaecce0..a64fe454e19 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -423,10 +423,13 @@ can_duplicate_and_interleave_p (vec_info *vinfo, unsigned int count,
(GET_MODE_BITSIZE (int_mode), 1);
tree vector_type
= get_vectype_for_scalar_type (vinfo, int_type, count);
+ poly_int64 half_nelts;
if (vector_type
&& VECTOR_MODE_P (TYPE_MODE (vector_type))
&& known_eq (GET_MODE_SIZE (TYPE_MODE (vector_type)),
- GET_MODE_SIZE (base_vector_mode)))
+ GET_MODE_SIZE (base_vector_mode))
+ && multiple_p (GET_MODE_NUNITS (TYPE_MODE (vector_type)),
+ 2, &half_nelts))
{
/* Try fusing consecutive sequences of COUNT / NVECTORS elements
together into elements of type INT_TYPE and using the result
@@ -434,7 +437,7 @@ can_duplicate_and_interleave_p (vec_info *vinfo, unsigned int count,
poly_uint64 nelts = GET_MODE_NUNITS (TYPE_MODE (vector_type));
vec_perm_builder sel1 (nelts, 2, 3);
vec_perm_builder sel2 (nelts, 2, 3);
- poly_int64 half_nelts = exact_div (nelts, 2);
+
for (unsigned int i = 0; i < 3; ++i)
{
sel1.quick_push (i);
--
2.34.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v5 07/10] vect: Verify that GET_MODE_NUNITS is a multiple of 2.
2023-04-26 21:45 ` [PATCH v5 07/10] vect: Verify that GET_MODE_NUNITS is a multiple of 2 Michael Collison
@ 2023-05-02 10:11 ` Richard Sandiford
0 siblings, 0 replies; 19+ messages in thread
From: Richard Sandiford @ 2023-05-02 10:11 UTC (permalink / raw)
To: Michael Collison; +Cc: gcc-patches
Michael Collison <collison@rivosinc.com> writes:
> While working on autovectorizing for the RISCV port I encountered an issue
> where can_duplicate_and_interleave_p assumes that GET_MODE_NUNITS is a
> evenly divisible by two. The RISC-V target has vector modes (e.g. VNx1DImode),
> where GET_MODE_NUNITS is equal to one.
>
> Tested on RISCV and x86_64-linux-gnu. Okay?
>
> 2023-03-09 Michael Collison <collison@rivosinc.com>
>
> * tree-vect-slp.cc (can_duplicate_and_interleave_p):
> Check that GET_MODE_NUNITS is a multiple of 2.
OK, thanks. Doesn't need to wait for any other of the other patches
in the series.
Richard
> ---
> gcc/tree-vect-slp.cc | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
> index d73deaecce0..a64fe454e19 100644
> --- a/gcc/tree-vect-slp.cc
> +++ b/gcc/tree-vect-slp.cc
> @@ -423,10 +423,13 @@ can_duplicate_and_interleave_p (vec_info *vinfo, unsigned int count,
> (GET_MODE_BITSIZE (int_mode), 1);
> tree vector_type
> = get_vectype_for_scalar_type (vinfo, int_type, count);
> + poly_int64 half_nelts;
> if (vector_type
> && VECTOR_MODE_P (TYPE_MODE (vector_type))
> && known_eq (GET_MODE_SIZE (TYPE_MODE (vector_type)),
> - GET_MODE_SIZE (base_vector_mode)))
> + GET_MODE_SIZE (base_vector_mode))
> + && multiple_p (GET_MODE_NUNITS (TYPE_MODE (vector_type)),
> + 2, &half_nelts))
> {
> /* Try fusing consecutive sequences of COUNT / NVECTORS elements
> together into elements of type INT_TYPE and using the result
> @@ -434,7 +437,7 @@ can_duplicate_and_interleave_p (vec_info *vinfo, unsigned int count,
> poly_uint64 nelts = GET_MODE_NUNITS (TYPE_MODE (vector_type));
> vec_perm_builder sel1 (nelts, 2, 3);
> vec_perm_builder sel2 (nelts, 2, 3);
> - poly_int64 half_nelts = exact_div (nelts, 2);
> +
> for (unsigned int i = 0; i < 3; ++i)
> {
> sel1.quick_push (i);
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v5 08/10] RISC-V:autovec: Add autovectorization tests for binary integer
2023-04-26 21:45 [PATCH v5 00/10] RISC-V: autovec: Add autovec support Michael Collison
` (6 preceding siblings ...)
2023-04-26 21:45 ` [PATCH v5 07/10] vect: Verify that GET_MODE_NUNITS is a multiple of 2 Michael Collison
@ 2023-04-26 21:45 ` Michael Collison
2023-04-26 21:45 ` [PATCH v5 09/10] RISC-V: autovec: This patch adds a guard for VNx1 vectors that are present in ports like riscv Michael Collison
2023-04-26 21:45 ` [PATCH v5 10/10] RISC-V: autovec: This patch supports 8 bit auto-vectorization in riscv Michael Collison
9 siblings, 0 replies; 19+ messages in thread
From: Michael Collison @ 2023-04-26 21:45 UTC (permalink / raw)
To: gcc-patches
2023-04-05 Michael Collison <collison@rivosinc.com>
* gcc.target/riscv/rvv/autovec/loop-and-rv32.c: New
test to verify code generation of vector "and" on rv32.
* gcc.target/riscv/rvv/autovec/loop-and.c: New
test to verify code generation of vector "and" on rv64.
* gcc.target/riscv/rvv/autovec/loop-div-rv32.c: New
test to verify code generation of vector divide on rv32.
* gcc.target/riscv/rvv/autovec/loop-div.c: New
test to verify code generation of vector divide on rv64.
* gcc.target/riscv/rvv/autovec/loop-max-rv32.c: New
test to verify code generation of vector maximum on rv32.
* gcc.target/riscv/rvv/autovec/loop-max.c: New
test to verify code generation of vector maximum on rv64.
* gcc.target/riscv/rvv/autovec/loop-min-rv32.c: New
test to verify code generation of vector minimum on rv32.
* gcc.target/riscv/rvv/autovec/loop-min.c: New
test to verify code generation of vector minimum on rv64.
* gcc.target/riscv/rvv/autovec/loop-mod-rv32.c: New
test to verify code generation of vector modulus on rv32.
* gcc.target/riscv/rvv/autovec/loop-mod.c: New
test to verify code generation of vector modulus on rv64.
* gcc.target/riscv/rvv/autovec/loop-mul-rv32.c: New
test to verify code generation of vector multiply on rv32.
* gcc.target/riscv/rvv/autovec/loop-mul.c: New
test to verify code generation of vector multiply on rv64.
* gcc.target/riscv/rvv/autovec/loop-or-rv32.c: New
test to verify code generation of vector "or" on rv32.
* gcc.target/riscv/rvv/autovec/loop-or.c: New
test to verify code generation of vector "or" on rv64.
* gcc.target/riscv/rvv/autovec/loop-xor-rv32.c: New
test to verify code generation of vector xor on rv32.
* gcc.target/riscv/rvv/autovec/loop-xor.c: New
test to verify code generation of vector xor on rv64.
---
.../riscv/rvv/autovec/loop-and-rv32.c | 24 ++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-and.c | 24 ++++++++++++++++++
.../riscv/rvv/autovec/loop-div-rv32.c | 25 +++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-div.c | 25 +++++++++++++++++++
.../riscv/rvv/autovec/loop-max-rv32.c | 25 +++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-max.c | 25 +++++++++++++++++++
.../riscv/rvv/autovec/loop-min-rv32.c | 25 +++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-min.c | 25 +++++++++++++++++++
.../riscv/rvv/autovec/loop-mod-rv32.c | 25 +++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-mod.c | 25 +++++++++++++++++++
.../riscv/rvv/autovec/loop-mul-rv32.c | 24 ++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-mul.c | 24 ++++++++++++++++++
.../riscv/rvv/autovec/loop-or-rv32.c | 24 ++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-or.c | 24 ++++++++++++++++++
.../riscv/rvv/autovec/loop-xor-rv32.c | 24 ++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-xor.c | 24 ++++++++++++++++++
gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 3 +++
17 files changed, 395 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
new file mode 100644
index 00000000000..eb1ac5b44fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vand_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] & b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
new file mode 100644
index 00000000000..ff0cc2a5df7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vand_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] & b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
new file mode 100644
index 00000000000..21960f265b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vdiv_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] / b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
new file mode 100644
index 00000000000..bd675b4f6f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vdiv_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] / b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
new file mode 100644
index 00000000000..751ee9ecaa3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vmax_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] >= b[i] ? a[i] : b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
new file mode 100644
index 00000000000..f4dbf3f04fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vmax_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] >= b[i] ? a[i] : b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
new file mode 100644
index 00000000000..e51cf590577
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vmin_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] <= b[i] ? a[i] : b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
new file mode 100644
index 00000000000..304f939f6f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vmin_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] <= b[i] ? a[i] : b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
new file mode 100644
index 00000000000..7c497f6e4cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vmod_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] % b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
new file mode 100644
index 00000000000..7508f4a50d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vmod_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] % b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
new file mode 100644
index 00000000000..fd6dcbf9c53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] * b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
new file mode 100644
index 00000000000..9fce40890ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] * b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
new file mode 100644
index 00000000000..305d106abd9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] | b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
new file mode 100644
index 00000000000..501017bc790
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] | b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
new file mode 100644
index 00000000000..6a9ffdb11d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vxor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] ^ b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
new file mode 100644
index 00000000000..c9d7d7f8a75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vxor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] ^ b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index 7a9a2b6ac48..081fa9363de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -40,10 +40,13 @@ dg-init
# Main loop.
set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -O3"
+set AUTOVECFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -O2 -fno-vect-cost-model -std=c99"
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \
"" $CFLAGS
gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
"" $CFLAGS
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \
+ "" $AUTOVECFLAGS
# All done.
dg-finish
--
2.34.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v5 09/10] RISC-V: autovec: This patch adds a guard for VNx1 vectors that are present in ports like riscv.
2023-04-26 21:45 [PATCH v5 00/10] RISC-V: autovec: Add autovec support Michael Collison
` (7 preceding siblings ...)
2023-04-26 21:45 ` [PATCH v5 08/10] RISC-V:autovec: Add autovectorization tests for binary integer Michael Collison
@ 2023-04-26 21:45 ` Michael Collison
2023-04-26 21:45 ` [PATCH v5 10/10] RISC-V: autovec: This patch supports 8 bit auto-vectorization in riscv Michael Collison
9 siblings, 0 replies; 19+ messages in thread
From: Michael Collison @ 2023-04-26 21:45 UTC (permalink / raw)
To: gcc-patches
From: Kevin Lee <kevinl@rivosinc.com>
Kevin Lee <kevinl@rivosinc.com>
gcc/ChangeLog:
* tree-vect-data-refs.cc (vect_grouped_store_supported): Add new
condition
---
gcc/tree-vect-data-refs.cc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/tree-vect-data-refs.cc b/gcc/tree-vect-data-refs.cc
index 8daf7bd7dd3..df393ba723d 100644
--- a/gcc/tree-vect-data-refs.cc
+++ b/gcc/tree-vect-data-refs.cc
@@ -5399,6 +5399,8 @@ vect_grouped_store_supported (tree vectype, unsigned HOST_WIDE_INT count)
poly_uint64 nelt = GET_MODE_NUNITS (mode);
/* The encoding has 2 interleaved stepped patterns. */
+ if(!multiple_p (nelt, 2))
+ return false;
vec_perm_builder sel (nelt, 2, 3);
sel.quick_grow (6);
for (i = 0; i < 3; i++)
--
2.34.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v5 10/10] RISC-V: autovec: This patch supports 8 bit auto-vectorization in riscv.
2023-04-26 21:45 [PATCH v5 00/10] RISC-V: autovec: Add autovec support Michael Collison
` (8 preceding siblings ...)
2023-04-26 21:45 ` [PATCH v5 09/10] RISC-V: autovec: This patch adds a guard for VNx1 vectors that are present in ports like riscv Michael Collison
@ 2023-04-26 21:45 ` Michael Collison
9 siblings, 0 replies; 19+ messages in thread
From: Michael Collison @ 2023-04-26 21:45 UTC (permalink / raw)
To: gcc-patches
From: Kevin Lee <kevinl@rivosinc.com>
2023-04-14 Kevin Lee <kevinl@rivosinc.com>
gcc/testsuite/ChangeLog:
* config/riscv/riscv.cc (riscv_autovectorize_vector_modes): Add
new vector mode
* gcc.target/riscv/rvv/autovec/loop-add-rv32.c: Support 8bit
type
* gcc.target/riscv/rvv/autovec/loop-add.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-and-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-and.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-div-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-div.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-max-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-max.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-min-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-min.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-mod-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-mod.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-mul-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-mul.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-or-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-or.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-sub-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-sub.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-xor-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-xor.c: Ditto
---
gcc/config/riscv/riscv.cc | 1 +
.../gcc.target/riscv/rvv/autovec/loop-add-rv32.c | 5 +++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c | 5 +++--
.../gcc.target/riscv/rvv/autovec/loop-and-rv32.c | 5 +++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c | 5 +++--
.../gcc.target/riscv/rvv/autovec/loop-div-rv32.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c | 8 +++++---
.../gcc.target/riscv/rvv/autovec/loop-max-rv32.c | 7 ++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c | 7 ++++---
.../gcc.target/riscv/rvv/autovec/loop-min-rv32.c | 7 ++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c | 7 ++++---
.../gcc.target/riscv/rvv/autovec/loop-mod-rv32.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c | 8 +++++---
.../gcc.target/riscv/rvv/autovec/loop-mul-rv32.c | 5 +++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c | 5 +++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c | 5 +++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c | 5 +++--
.../gcc.target/riscv/rvv/autovec/loop-sub-rv32.c | 5 +++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c | 5 +++--
.../gcc.target/riscv/rvv/autovec/loop-xor-rv32.c | 5 +++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c | 5 +++--
21 files changed, 73 insertions(+), 48 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 77209b161f6..f293414acd1 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7143,6 +7143,7 @@ riscv_autovectorize_vector_modes (vector_modes *modes, bool)
modes->safe_push (VNx8QImode);
modes->safe_push (VNx4QImode);
modes->safe_push (VNx2QImode);
+ modes->safe_push (VNx1QImode);
}
return 0;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
index bdc3b6892e9..76f5a3a3ff5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] + b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
index d7f992c7d27..3d1e10bf4e1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
@@ -10,8 +10,9 @@
dst[i] = a[i] + b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
index eb1ac5b44fd..a4c7abfb0ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] & b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
index ff0cc2a5df7..a795e0968a9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
@@ -10,8 +10,9 @@
dst[i] = a[i] & b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
index 21960f265b7..c734bb9c5f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] / b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,6 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */
+/* int8_t and int16_t not autovec currently */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
index bd675b4f6f0..9f57cd91054 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
@@ -10,8 +10,9 @@
dst[i] = a[i] / b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,6 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */
+/* int8_t and int16_t not autovec currently */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
index 751ee9ecaa3..bd825c3dfaa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] >= b[i] ? a[i] : b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,5 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
index f4dbf3f04fc..729fbe0bc76 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
@@ -10,8 +10,9 @@
dst[i] = a[i] >= b[i] ? a[i] : b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,5 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
index e51cf590577..808c2879d86 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] <= b[i] ? a[i] : b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,5 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
index 304f939f6f9..c81ba64223f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
@@ -10,8 +10,9 @@
dst[i] = a[i] <= b[i] ? a[i] : b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,5 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
index 7c497f6e4cc..9ce4f82b3a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] % b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,6 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */
+/* int8_t and int16_t not autovec currently */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
index 7508f4a50d1..46fbff22266 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
@@ -10,8 +10,9 @@
dst[i] = a[i] % b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,6 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */
+/* int8_t and int16_t not autovec currently */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
index fd6dcbf9c53..336af62359e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] * b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
index 9fce40890ef..12a17d0da00 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
@@ -10,8 +10,9 @@
dst[i] = a[i] * b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
index 305d106abd9..b272d893114 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] | b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
index 501017bc790..52243be3712 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
@@ -10,8 +10,9 @@
dst[i] = a[i] | b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
index 7d0a40ec539..6fdce0f7881 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] - b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
index c8900884f83..73369745afc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
@@ -10,8 +10,9 @@
dst[i] = a[i] - b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
index 6a9ffdb11d5..bd43e60cceb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] ^ b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
index c9d7d7f8a75..cb3adde80c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
@@ -10,8 +10,9 @@
dst[i] = a[i] ^ b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 8 } } */
--
2.34.1
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