Re: Indirect memory addresses vs. lra

[Segher Boessenkool <segher@kernel.crashing.org>]

Hi John,

On Mon, Aug 12, 2019 at 08:47:43AM +0200, John Darrington wrote:
> On Sat, Aug 10, 2019 at 11:12:18AM -0500, Segher Boessenkool wrote:
>      On Sat, Aug 10, 2019 at 08:05:53AM +0200, John Darrington wrote:
>      > 	 Choosing alt 5 in insn 14:  (0) m  (1) m {*movsi}
>      >    14: [r40:PSI+0x20]=[r41:PSI]
>      >     Inserting insn reload before:
>      >    48: r40:PSI=r34:PSI
>      >    49: r41:PSI=[y:PSI+0x2f]
>      
>      insn 14 is a mem-to-mem move (another feature not many more modern /
>      more RISCy CPUs have).  That requires both of your address registers.
>      So far, so good.  The reloads (insn 48 and 49) require address
>      registers themselves; that isn't necessarily a problem either.
> 
> So far as I can see, insn 48 is completely redundant.  It's copying a
> pseudo reg (74) into another pseudo reg (40).
> This is pointless and a waste, since insn 14 does not modify 74.
> I don't understand why lra feels the need to do it.

LRA always does this, I think...  it reloads all inputs to all insns
that may need reloading.  It later optimises most of that away again,
but this gives it a lot of freedom to move things around.

Or that is what it always looked like to me.  I haven't looked at the
code to see if that is the real reason, blush.

> If lra knew about (mem (mem ...)) style addressing, then insn 49 would
> also be redundant (which is why I raised the topic).

Yes.  But it probably should be able to deal with things like this, too,
or some other testcases will die a horrible death.

> In summary, what we have is:
> 
> (insn 48 84 49 2 (set (reg/f:PSI 40 [34])
>         (reg/f:PSI 74 [34]))
>      (nil))
> (insn 49 48 14 2 (set (reg:PSI 41)
>         (mem/f/c:PSI (plus:PSI (reg/f:PSI 9 y)
>                 (const_int 47 [0x2f])) [3 p+0 S4 A8]))
>      (nil))
> (insn 14 49 15 2 (set (mem:SI (plus:PSI (reg/f:PSI 40 [34])
>                 (const_int 32 [0x20])) [2  S4 A64])
>         (mem:SI (reg:PSI 41) [2 *p_5(D)+0 S4 A8])) 
> 
> where, like you say, insns 48 and 49 are reloads.  But these two reloads 
> are unnecessary and cause the machine to run out of PSImode registers.

Anyway, please have patience, and see what Vladimir comes up with.  These
things take time.


Segher