Re: Indirect memory addresses vs. lra

[Vladimir Makarov <vmakarov@redhat.com>]

On 8/15/19 12:38 PM, Richard Biener wrote:
> On August 15, 2019 6:29:13 PM GMT+02:00, Vladimir Makarov <vmakarov@redhat.com> wrote:
>> On 8/10/19 2:05 AM, John Darrington wrote:
>>> On Fri, Aug 09, 2019 at 01:34:36PM -0400, Vladimir Makarov wrote:
>>>        
>>>        If you provide LRA dump for such test (it is better to use
>>>        -fira-verbose=15 to output full RA info into stderr), I
>> probably could
>>>        say more.
>>>
>>> I've attached such a dump (generated from
>> gcc/testsuite/gcc.c-torture/compile/pr53410-2.c).
>>>        
>>>        The less regs the architecture has, thoke easier to run into
>> such error
>>>        message if something described wrong in the back-end.?? I see
>> your
>>>        architecture is 16-bit micro-controller with only 8 regs, some
>> of them is
>>>        specialized.?? So your architecture is really register
>> constrained.
>>> That's not quite correct.  It is a 24-bit micro-controller (the
>> address
>>> space is 24 bits wide).  There are 2 address registers (plus stack
>>> pointer and program counter) and there are 8 general purpose data
>>> registers (of differing sizes).
>>>        
>>>
>>> J'
>>>
>> Thank you for providing the sources.  It helped me to understand what
>> is
>> going on.  So the test crashes on
>>
>> /home/jmd/Source/GCC2/gcc/testsuite/gcc.c-torture/compile/pr53410-2.c:
>> In function ‘f1’:
>> /home/jmd/Source/GCC2/gcc/testsuite/gcc.c-torture/compile/pr53410-2.c:10:1:
>> error: unable to find a register to spill
>> /home/jmd/Source/GCC2/gcc/testsuite/gcc.c-torture/compile/pr53410-2.c:10:1:
>> error: this is the insn:
>> (insn 14 49 15 2 (set (mem:SI (plus:PSI (reg/f:PSI 40 [34])
>>                  (const_int 32 [0x20])) [2  S4 A64])
>> (mem:SI (reg:PSI 41) [2 *p_5(D)+0 S4 A8]))
>> "/home/jmd/Source/GCC2/gcc/testsuite/gcc.c-torture/compile/pr53410-2.c":9:9
>> 95 {*movsi}
>>       (expr_list:REG_DEAD (reg:PSI 41)
>>          (expr_list:REG_DEAD (reg/f:PSI 40 [34])
>>              (nil))))
>>
>> Your target has only 2 non-fixed addr registers (r8, r9).  One (r9) is
>> defined as a hard reg pointer pointer. Honestly, I never saw a target
>> with such register constraints.
>>
>> -O0 assumes -fno-omit-frame-pointer.  So in -O0 mode we have only *one*
>> free addr reg for insn which requires *2* of them.  That is why the GCC
>> port crashes on this test.  If you add -fomit-frame-pointer, the test
>> succeeds.
>>
>> But even if use -fomit-frame-pointer,  it is not guaranteed that hard
>> reg pointer will be substituted by stack pointer.  There are many cases
>> where it is not possible (e.g. in case of alloca usage).
>>
>> So what can be done, imho.  The simplest solution would be preventing
>> insns with more one memory operand.  The more difficult solution would
>> be permitting two memory one with address pseudo and another one with
>> stack pointer.
> Couldn't we spill the frame pointer? Basically we should be able to compute the first address into a reg, spill that, do the second (both could require the frame pointer), spill the frame pointer, reload the first computed address from the stack, execute the insn and then reload the frame pointer.
>
> Maybe the frame pointer can also be implemented 'virually' in an index register that you keep updated so that sp + reg
> Is the FP. Or frame accesses can use a
> Stack slot as FP and the indirect memory
> Addressing... (is there an indirect lea?)
>
Yes, it could be a solution.  It just needs some target maintainer 
creativity.  There are a lot of things (tricks) can be done in 
machine-dependent code which would not require RA changes.