From: Segher Boessenkool <segher@kernel.crashing.org>
To: John Darrington <john@darrington.wattle.id.au>
Cc: Vladimir Makarov <vmakarov@redhat.com>, Jeff Law <law@redhat.com>,
Paul Koning <paulkoning@comcast.net>,
gcc@gcc.gnu.org
Subject: Re: Indirect memory addresses vs. lra
Date: Sat, 10 Aug 2019 16:12:00 -0000 [thread overview]
Message-ID: <20190810161218.GQ31406@gate.crashing.org> (raw)
In-Reply-To: <20190810060553.m6e42sovw7s4xqoa@jocasta.intra>
Hi!
On Sat, Aug 10, 2019 at 08:05:53AM +0200, John Darrington wrote:
> Choosing alt 5 in insn 14: (0) m (1) m {*movsi}
> 14: [r40:PSI+0x20]=[r41:PSI]
> Inserting insn reload before:
> 48: r40:PSI=r34:PSI
> 49: r41:PSI=[y:PSI+0x2f]
insn 14 is a mem-to-mem move (another feature not many more modern /
more RISCy CPUs have). That requires both of your address registers.
So far, so good. The reloads (insn 48 and 49) require address
registers themselves; that isn't necessarily a problem either. But
this requires careful juggling. Maybe you will need some backend code
for this, or to optimise this (although right now you just want it to
*work* :-) )
For some reason LRA didn't manage. Register inheritance seems to be
implicated (but that might be a red herring). Vladimir will probably
find out more, and/or correct me :-)
Segher
next prev parent reply other threads:[~2019-08-10 16:12 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-04 19:18 John Darrington
2019-08-08 16:25 ` Vladimir Makarov
2019-08-08 16:44 ` Paul Koning
2019-08-08 17:21 ` Segher Boessenkool
2019-08-08 17:25 ` Paul Koning
2019-08-08 19:09 ` Segher Boessenkool
2019-08-08 17:30 ` Paul Koning
2019-08-08 19:19 ` Segher Boessenkool
2019-08-08 19:57 ` Jeff Law
2019-08-09 8:14 ` John Darrington
2019-08-09 14:17 ` Segher Boessenkool
2019-08-09 14:23 ` Paul Koning
2019-08-10 6:10 ` John Darrington
2019-08-10 16:15 ` Segher Boessenkool
2019-08-09 16:07 ` Jeff Law
2019-08-09 17:34 ` Vladimir Makarov
2019-08-10 6:06 ` John Darrington
2019-08-10 16:12 ` Segher Boessenkool [this message]
2019-08-12 6:47 ` John Darrington
2019-08-12 8:40 ` Segher Boessenkool
2019-08-12 13:35 ` Vladimir Makarov
2019-08-15 16:29 ` Vladimir Makarov
2019-08-15 16:38 ` Richard Biener
2019-08-15 17:41 ` John Darrington
2019-08-15 18:30 ` Vladimir Makarov
2019-08-15 21:22 ` Segher Boessenkool
2019-08-15 17:36 ` John Darrington
2019-08-15 18:23 ` Vladimir Makarov
2019-08-16 11:24 ` Special Memory Constraint [was Re: Indirect memory addresses vs. lra] John Darrington
2019-08-16 14:50 ` Vladimir Makarov
2019-08-19 7:36 ` John Darrington
2019-08-19 13:14 ` Vladimir Makarov
2019-08-19 15:07 ` Segher Boessenkool
2019-08-19 18:06 ` John Darrington
2019-08-20 6:56 ` Richard Biener
2019-08-20 7:07 ` John Darrington
2019-08-20 7:30 ` Richard Biener
2019-08-08 18:46 ` Indirect memory addresses vs. lra Vladimir Makarov
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