Re: Indirect memory addresses vs. lra

[John Darrington <john@darrington.wattle.id.au>]

On Thu, Aug 15, 2019 at 12:29:13PM -0400, Vladimir Makarov wrote:


     Thank you for providing the sources.?? It helped me to understand what is
     going on.?? So the test crashes on
     
     /home/jmd/Source/GCC2/gcc/testsuite/gcc.c-torture/compile/pr53410-2.c: In function ???f1???:
     /home/jmd/Source/GCC2/gcc/testsuite/gcc.c-torture/compile/pr53410-2.c:10:1: error: unable to find a register to spill
     /home/jmd/Source/GCC2/gcc/testsuite/gcc.c-torture/compile/pr53410-2.c:10:1: error: this is the insn:
     (insn 14 49 15 2 (set (mem:SI (plus:PSI (reg/f:PSI 40 [34])
                     (const_int 32 [0x20])) [2  S4 A64])
             (mem:SI (reg:PSI 41) [2 *p_5(D)+0 S4 A8])) "/home/jmd/Source/GCC2/gcc/testsuite/gcc.c-torture/compile/pr53410-2.c":9:9 95 {*movsi}
          (expr_list:REG_DEAD (reg:PSI 41)
             (expr_list:REG_DEAD (reg/f:PSI 40 [34])
                 (nil))))

Thanks for taking a look.
     
     Your target has only 2 non-fixed addr registers (r8, r9).  One (r9) is defined as a hard reg pointer pointer.

That is correct.

     Honestly, I never saw a target with such register constraints.

My recollection is that MC68HC11 was the same.
     
     So what can be done, imho.  The simplest solution would be preventing insns with more one memory operand.

I tried this solution earlier.  But unfortunately it makes things worse.  What happens is it libgcc cannot
even be built -- ICEs occur on a memory from  address reg insn such as:
     
(insn 117 2981 3697 5 (set (mem/f:PSI (plus:PSI (reg:PSI 1309)
                (const_int 102 [0x66])) [3 fs_129(D)->pc+0 S4 A8])
		        (reg:PSI 1310)) "/home/jmd/Source/GCC2/libgcc/unwind-dw2.c":977:9 96 {movpsi}


J'
     

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