From: Richard Biener <richard.guenther@gmail.com>
To: John Darrington <john@darrington.wattle.id.au>
Cc: Segher Boessenkool <segher@kernel.crashing.org>,
Vladimir Makarov <vmakarov@redhat.com>,
GCC Development <gcc@gcc.gnu.org>
Subject: Re: Special Memory Constraint [was Re: Indirect memory addresses vs. lra]
Date: Tue, 20 Aug 2019 07:30:00 -0000 [thread overview]
Message-ID: <CAFiYyc1fsCtDNP0WXCz8d8aEBeBL8NMqj8TpT=XoLGrBEjuRHA@mail.gmail.com> (raw)
In-Reply-To: <20190820070729.efox77kw3jhovswh@jocasta.intra>
On Tue, Aug 20, 2019 at 9:07 AM John Darrington
<john@darrington.wattle.id.au> wrote:
>
> On Tue, Aug 20, 2019 at 08:56:39AM +0200, Richard Biener wrote:
>
> > Most of these suggestions involve adding some sort of virtual registers
> > So I hacked the machine description to add two new registers Z1 and Z2
> > with the same mode as X and Y.
> >
> > Obviously the assembler balks at this. However the compiler still
> > ICEs at the same place as before.
> >
> > So this suggests that our original diagnosis, viz: there are not enough
> > address registers was not accurate, and in fact there is some other
> > problem?
>
> That sounds likely. Given you have indirect addressing you could
> simulate N virtual regs by placing them in a virtual reg table in memory
> and accessed via a fixed address register (assuming all instructions
> that would need an address reg also can take that indirect from memory).
>
> That was my plan. Accordingly, extending the md to provide N additional
> regs (N currently = 2) was the first step. Having doubled the number
> of available address registers, I had expected this would fix most of the
> ICEs (but cause a lot of assembler errors).
>
> However it hasn't eliminated any ICEs. lra is still complaining
> "unable to find a register to spill" So the plan seems to have fallen
> over at the first hurdle. Why can it still not spill registers despite
> having a lot more of them?
You really have to sit down and trace the LRA code with a debugger
to tell... unfortunately the dumps aren't verbose enough to tell.
Usually after spilling the insn constraints can still not be satisfied,
the main question is usually why.
Richard.
> J'
next prev parent reply other threads:[~2019-08-20 7:30 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-04 19:18 Indirect memory addresses vs. lra John Darrington
2019-08-08 16:25 ` Vladimir Makarov
2019-08-08 16:44 ` Paul Koning
2019-08-08 17:21 ` Segher Boessenkool
2019-08-08 17:25 ` Paul Koning
2019-08-08 19:09 ` Segher Boessenkool
2019-08-08 17:30 ` Paul Koning
2019-08-08 19:19 ` Segher Boessenkool
2019-08-08 19:57 ` Jeff Law
2019-08-09 8:14 ` John Darrington
2019-08-09 14:17 ` Segher Boessenkool
2019-08-09 14:23 ` Paul Koning
2019-08-10 6:10 ` John Darrington
2019-08-10 16:15 ` Segher Boessenkool
2019-08-09 16:07 ` Jeff Law
2019-08-09 17:34 ` Vladimir Makarov
2019-08-10 6:06 ` John Darrington
2019-08-10 16:12 ` Segher Boessenkool
2019-08-12 6:47 ` John Darrington
2019-08-12 8:40 ` Segher Boessenkool
2019-08-12 13:35 ` Vladimir Makarov
2019-08-15 16:29 ` Vladimir Makarov
2019-08-15 16:38 ` Richard Biener
2019-08-15 17:41 ` John Darrington
2019-08-15 18:30 ` Vladimir Makarov
2019-08-15 21:22 ` Segher Boessenkool
2019-08-15 17:36 ` John Darrington
2019-08-15 18:23 ` Vladimir Makarov
2019-08-16 11:24 ` Special Memory Constraint [was Re: Indirect memory addresses vs. lra] John Darrington
2019-08-16 14:50 ` Vladimir Makarov
2019-08-19 7:36 ` John Darrington
2019-08-19 13:14 ` Vladimir Makarov
2019-08-19 15:07 ` Segher Boessenkool
2019-08-19 18:06 ` John Darrington
2019-08-20 6:56 ` Richard Biener
2019-08-20 7:07 ` John Darrington
2019-08-20 7:30 ` Richard Biener [this message]
2019-08-08 18:46 ` Indirect memory addresses vs. lra Vladimir Makarov
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