* [PATCH] Support Intel USER_MSR @ 2023-10-10 7:24 Hu, Lin1 2023-10-16 12:11 ` Jan Beulich 0 siblings, 1 reply; 33+ messages in thread From: Hu, Lin1 @ 2023-10-10 7:24 UTC (permalink / raw) To: binutils; +Cc: JBeulich, hongjiu.lu This patch aims to support Intel USER_MSR. gas/ChangeLog: * NEWS: Support Intel USER_MSR. * config/tc-i386.c: Add user_msr and add VEXMAP7 in opc_spc and build_vex_prefix. (build_modrm_byte): Swap Operands for USER_MSR. * doc/c-i386.texi: Document .user_msr. * testsuite/gas/i386/i386.exp: Run USER_MSR tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/user_msr-inval.l: New test. * testsuite/gas/i386/user_msr-inval.s: Ditto. * testsuite/gas/i386/x86-64-user_msr-intel.d: Ditto. * testsuite/gas/i386/x86-64-user_msr.d: Ditto. * testsuite/gas/i386/x86-64-user_msr.s: Ditto. opcodes/ChangeLog: * i386-dis.c (get32_operand0): Add a new function to get operand0 that is IMM32. (Gq): New. (Id0): Ditto. (get_valid_dis386): Add VEX_MAP7 in VEX prefix. (OP_I): Handle d_0_mode. (d_0_mode): New. (REG_VEX_MAP7_F8_L_0_W_0_M_1): New. (MOD_VEX_MAP7_F8_L_0_W_0): Ditto. (PREFIX_VEX_MAP7_F8_L_0_W_0_M_1_R_0_X86_64): Ditto. (X86_64_VEX_MAP7_F8_L_0_W_0_M_1_R_0): Ditto. (VEX_MAP7): Ditto. (VEX_LEN_MAP7_F8): Ditto. (VEX_W_MAP7_F8_L_0): Ditto. (MOD_0F38F8): Ditto. (PREFIX_0F38F8_M_0): Ditto. (PREFIX_0F38F8_M_1_X86_64): Ditto. (X86_64_0F38F8_M_1): Ditto. (PREFIX_0F38F8): Remove. (prefix_table): Add PREFIX_0F38F8_M_1_X86_64. Remove PREFIX_0F38F8. (reg_table): Add REG_VEX_MAP7_F8_L_0_W_0_M_1, PREFIX_VEX_MAP7_F8_L_0_W_0_M_1_R_0_X86_64. (x86_64_table): Add X86_64_0F38F8_PREFIX_3_M_1, X86_64_VEX_MAP7_F8_L_0_W_0_M_1_R_0 and X86_64_0F38F8_M_1. (vex_table): Add VEX_MAP7. (vex_len_table): Add VEX_LEN_MAP7_F8, VEX_W_MAP7_F8_L_0. (mod_table): New entry for USER_MSR and add MOD_VEX_MAP7_F8_L_0_W_0 and MOD_0F38F8. * i386-gen.c (cpu_flag_init): Add CPU_USER_MSR_FLAGS and CPU_ANY_USER_MSR_FLAGS. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (SPACE_VEXMAP7): New. (SWAP_SOURCE_DEST): Ditto. (CPU_USER_MSR_FLAGS): Ditoo. (CPU_ANY_USER_MSR_FLAGS): Ditto. (i386_cpu_flags): Add cpuuser_msr. * i386-opc.tbl: Add USER_MSR instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 2 + gas/config/tc-i386.c | 15 + gas/doc/c-i386.texi | 3 +- gas/testsuite/gas/i386/i386.exp | 1 + gas/testsuite/gas/i386/user_msr-inval.l | 3 + gas/testsuite/gas/i386/user_msr-inval.s | 7 + .../gas/i386/x86-64-user_msr-intel.d | 18 + gas/testsuite/gas/i386/x86-64-user_msr.d | 18 + gas/testsuite/gas/i386/x86-64-user_msr.s | 15 + gas/testsuite/gas/i386/x86-64.exp | 2 + opcodes/i386-dis.c | 387 ++++- opcodes/i386-gen.c | 2 + opcodes/i386-init.h | 816 +++++------ opcodes/i386-mnem.h | 1278 +++++++++-------- opcodes/i386-opc.h | 10 + opcodes/i386-opc.tbl | 12 + opcodes/i386-tbl.h | 272 ++-- 17 files changed, 1698 insertions(+), 1163 deletions(-) create mode 100644 gas/testsuite/gas/i386/user_msr-inval.l create mode 100644 gas/testsuite/gas/i386/user_msr-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr.d create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr.s diff --git a/gas/NEWS b/gas/NEWS index 71a1269b893..ab0e7813f27 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel USER_MSR instructions. + * Add support for Intel AVX10.1. * Add support for Intel PBNDKB instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 714354d5116..2a7b1329858 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1164,6 +1164,7 @@ static const arch_entry cpu_arch[] = VECARCH (sm4, SM4, ANY_SM4, reset), SUBARCH (pbndkb, PBNDKB, PBNDKB, false), VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set), + SUBARCH (user_msr, USER_MSR, USER_MSR, false), }; #undef SUBARCH @@ -3863,6 +3864,8 @@ build_vex_prefix (const insn_template *t) case SPACE_0F: case SPACE_0F38: case SPACE_0F3A: + case SPACE_EVEXMAP5: + case SPACE_VEXMAP7: i.vex.bytes[0] = 0xc4; break; case SPACE_XOP08: @@ -8752,6 +8755,18 @@ build_modrm_byte (void) source = v; v = tmp; } + if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCE_DEST) + { + if (dest == (unsigned int) ~0) + source = source ^ 1; + else + { + unsigned int tmp = source; + + source = dest; + dest = tmp; + } + } if (v < MAX_OPERANDS) { diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index b04e1b00b4b..03ee980bef7 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -216,6 +216,7 @@ accept various extension mnemonics. For example, @code{avx10.1/512}, @code{avx10.1/256}, @code{avx10.1/128}, +@code{user_msr}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1650,7 +1651,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} @item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs} @item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4} -@item @samp{.pbndkb} +@item @samp{.pbndkb} @tab @samp{.user_msr} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index ee74bcd4615..81ce1e38b10 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -509,6 +509,7 @@ if [gas_32_check] then { run_dump_test "sm4" run_dump_test "sm4-intel" run_list_test "pbndkb-inval" + run_list_test "user_msr-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" diff --git a/gas/testsuite/gas/i386/user_msr-inval.l b/gas/testsuite/gas/i386/user_msr-inval.l new file mode 100644 index 00000000000..9618645bea8 --- /dev/null +++ b/gas/testsuite/gas/i386/user_msr-inval.l @@ -0,0 +1,3 @@ +.* Assembler messages: +.*:6: Error: `urdmsr' is only supported in 64-bit mode +.*:7: Error: `uwrmsr' is only supported in 64-bit mode diff --git a/gas/testsuite/gas/i386/user_msr-inval.s b/gas/testsuite/gas/i386/user_msr-inval.s new file mode 100644 index 00000000000..dba67ddfd5d --- /dev/null +++ b/gas/testsuite/gas/i386/user_msr-inval.s @@ -0,0 +1,7 @@ +# Check Illegal 32bit USER_MSR instructions + + .allow_index_reg + .text +_start: + urdmsr %r12, %r14 #USER_MSR + uwrmsr %r12, %r14 #USER_MSR diff --git a/gas/testsuite/gas/i386/x86-64-user_msr-intel.d b/gas/testsuite/gas/i386/x86-64-user_msr-intel.d new file mode 100644 index 00000000000..fe8418b2ce0 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr-intel.d @@ -0,0 +1,18 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 USER_MSR insns (Intel disassembly) +#source: x86-64-user_msr.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 4d 0f 38 f8 f4\s+urdmsr r12,r14 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr r12,0x3120f0f +\s*[a-f0-9]+:\s*f3 4d 0f 38 f8 f4\s+uwrmsr r14,r12 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr 0x3120f0f,r12 +\s*[a-f0-9]+:\s*f2 4d 0f 38 f8 f4\s+urdmsr r12,r14 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr r12,0x3120f0f +\s*[a-f0-9]+:\s*f3 4d 0f 38 f8 f4\s+uwrmsr r14,r12 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr 0x3120f0f,r12 diff --git a/gas/testsuite/gas/i386/x86-64-user_msr.d b/gas/testsuite/gas/i386/x86-64-user_msr.d new file mode 100644 index 00000000000..295f80c0318 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr.d @@ -0,0 +1,18 @@ +#as: +#objdump: -dw +#name: x86_64 USER_MSR insns +#source: x86-64-user_msr.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 4d 0f 38 f8 f4\s+urdmsr %r14,%r12 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr \$0x3120f0f,%r12 +\s*[a-f0-9]+:\s*f3 4d 0f 38 f8 f4\s+uwrmsr %r12,%r14 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr %r12,\$0x3120f0f +\s*[a-f0-9]+:\s*f2 4d 0f 38 f8 f4\s+urdmsr %r14,%r12 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr \$0x3120f0f,%r12 +\s*[a-f0-9]+:\s*f3 4d 0f 38 f8 f4\s+uwrmsr %r12,%r14 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr %r12,\$0x3120f0f diff --git a/gas/testsuite/gas/i386/x86-64-user_msr.s b/gas/testsuite/gas/i386/x86-64-user_msr.s new file mode 100644 index 00000000000..c62c5e785bd --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s @@ -0,0 +1,15 @@ +# Check 64bit USER_MSR instructions + + .allow_index_reg + .text +_start: + urdmsr %r14, %r12 #USER_MSR + urdmsr $51515151, %r12 #USER_MSR + uwrmsr %r12, %r14 #USER_MSR + uwrmsr %r12, $51515151 #USER_MSR + +.intel_syntax noprefix + urdmsr r12, r14 #USER_MSR + urdmsr r12, 51515151 #USER_MSR + uwrmsr r14, r12 #USER_MSR + uwrmsr 51515151, r12 #USER_MSR diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 52711cdcf6f..5765d473e31 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -450,6 +450,8 @@ run_dump_test "x86-64-sm4" run_dump_test "x86-64-sm4-intel" run_dump_test "x86-64-pbndkb" run_dump_test "x86-64-pbndkb-intel" +run_dump_test "x86-64-user_msr" +run_dump_test "x86-64-user_msr-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 87ecf0f5e23..810cd76669f 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -418,6 +418,7 @@ fetch_error (const instr_info *ins) #define Gv { OP_G, v_mode } #define Gd { OP_G, d_mode } #define Gdq { OP_G, dq_mode } +#define Gq { OP_G, q_mode } #define Gm { OP_G, m_mode } #define Gva { OP_G, va_mode } #define Gw { OP_G, w_mode } @@ -430,6 +431,7 @@ fetch_error (const instr_info *ins) #define Id { OP_I, d_mode } #define Iw { OP_I, w_mode } #define I1 { OP_I, const_1_mode } +#define Id0 { OP_I, d_0_mode } #define Jb { OP_J, b_mode } #define Jv { OP_J, v_mode } #define Jdqw { OP_J, dqw_mode } @@ -618,6 +620,8 @@ enum w_mode, /* double word operand */ d_mode, + /* double word operand 0 */ + d_0_mode, /* word operand with operand swapped */ w_swap_mode, /* double word operand with operand swapped */ @@ -845,6 +849,7 @@ enum REG_VEX_0FAE, REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0, REG_VEX_0F38F3_L_0, + REG_VEX_MAP7_F8_L_0_W_0_M_1, REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, @@ -893,8 +898,10 @@ enum MOD_0FC7_REG_6, MOD_0FC7_REG_7, MOD_0F38DC_PREFIX_1, + MOD_0F38F8, MOD_VEX_0F3849_X86_64_L_0_W_0, + MOD_VEX_MAP7_F8_L_0_W_0, }; enum @@ -1010,7 +1017,8 @@ enum PREFIX_0F38F0, PREFIX_0F38F1, PREFIX_0F38F6, - PREFIX_0F38F8, + PREFIX_0F38F8_M_0, + PREFIX_0F38F8_M_1_X86_64, PREFIX_0F38FA, PREFIX_0F38FB, PREFIX_0F38FC, @@ -1073,6 +1081,7 @@ enum PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0, PREFIX_VEX_0F3AF0_L_0, + PREFIX_VEX_MAP7_F8_L_0_W_0_M_1_R_0_X86_64, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F6F, @@ -1217,6 +1226,7 @@ enum X86_64_0F18_REG_7_MOD_0, X86_64_0F24, X86_64_0F26, + X86_64_0F38F8_M_1, X86_64_0FC7_REG_6_MOD_3_PREFIX_1, X86_64_VEX_0F3849, @@ -1240,6 +1250,7 @@ enum X86_64_VEX_0F38ED, X86_64_VEX_0F38EE, X86_64_VEX_0F38EF, + X86_64_VEX_MAP7_F8_L_0_W_0_M_1_R_0, }; enum @@ -1259,7 +1270,8 @@ enum { VEX_0F = 0, VEX_0F38, - VEX_0F3A + VEX_0F3A, + VEX_MAP7 }; enum @@ -1350,6 +1362,7 @@ enum VEX_LEN_0F3ADE_W_0, VEX_LEN_0F3ADF, VEX_LEN_0F3AF0, + VEX_LEN_MAP7_F8, VEX_LEN_XOP_08_85, VEX_LEN_XOP_08_86, VEX_LEN_XOP_08_87, @@ -1510,6 +1523,7 @@ enum VEX_W_0F3ACE, VEX_W_0F3ACF, VEX_W_0F3ADE, + VEX_W_MAP7_F8_L_0, VEX_W_XOP_08_85_L_0, VEX_W_XOP_08_86_L_0, @@ -2849,6 +2863,10 @@ static const struct dis386 reg_table[][8] = { { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE }, { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE }, }, + /* REG_VEX_MAP7_F8_L_0_W_0_M_1 */ + { + { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_M_1_R_0) }, + }, /* REG_XOP_09_01_L_0 */ { { Bad_Opcode }, @@ -3555,13 +3573,22 @@ static const struct dis386 prefix_table[][4] = { { Bad_Opcode }, }, - /* PREFIX_0F38F8 */ + /* PREFIX_0F38F8_M_0 */ { { Bad_Opcode }, { "enqcmds", { Gva, M }, 0 }, { "movdir64b", { Gva, M }, 0 }, { "enqcmd", { Gva, M }, 0 }, }, + + /* PREFIX_0F38F8_M_1_X86_64 */ + { + { Bad_Opcode }, + { "uwrmsr", { Gdq, Eq }, 0 }, + { Bad_Opcode }, + { "urdmsr", { Rdq, Gq }, 0 }, + }, + /* PREFIX_0F38FA */ { { Bad_Opcode }, @@ -4014,6 +4041,14 @@ static const struct dis386 prefix_table[][4] = { { "rorxS", { Gdq, Edq, Ib }, 0 }, }, + /* PREFIX_VEX_MAP7_F8_L_0_W_0_M_1_R_0_X86_64 */ + { + { Bad_Opcode }, + { "uwrmsr", { Id0, Eq }, 0 }, + { Bad_Opcode }, + { "urdmsr", { Eq, Id }, 0 }, + }, + #include "i386-dis-evex-prefix.h" }; @@ -4322,6 +4357,12 @@ static const struct dis386 x86_64_table[][2] = { { "movZ", { Td, Em }, 0 }, }, + { + /* X86_64_0F38F8_M_1 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) }, + }, + /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */ { { Bad_Opcode }, @@ -4453,6 +4494,13 @@ static const struct dis386 x86_64_table[][2] = { { Bad_Opcode }, { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, }, + + /* X86_64_VEX_MAP7_F8_L_0_W_0_M_1_R_0 */ + { + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_M_1_R_0_X86_64) }, + }, + }; static const struct dis386 three_byte_table[][256] = { @@ -4739,7 +4787,7 @@ static const struct dis386 three_byte_table[][256] = { { PREFIX_TABLE (PREFIX_0F38F6) }, { Bad_Opcode }, /* f8 */ - { PREFIX_TABLE (PREFIX_0F38F8) }, + { MOD_TABLE (MOD_0F38F8) }, { "movdiri", { Mdq, Gdq }, PREFIX_OPCODE }, { PREFIX_TABLE (PREFIX_0F38FA) }, { PREFIX_TABLE (PREFIX_0F38FB) }, @@ -6791,6 +6839,297 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, }, + /* VEX_MAP7 */ + { + /* 00 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 08 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 10 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 18 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 20 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 28 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 30 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 38 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 40 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 48 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 50 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 58 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 60 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 68 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 70 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 78 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 80 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 88 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 90 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 98 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* e0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* e8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f8 */ + { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + }, }; #include "i386-dis-evex.h" @@ -7205,6 +7544,11 @@ static const struct dis386 vex_len_table[][2] = { { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) }, }, + /* VEX_LEN_MAP7_F8 */ + { + { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) }, + }, + /* VEX_LEN_XOP_08_85 */ { { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) }, @@ -7811,6 +8155,10 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3ADE */ { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) }, }, + { + /* VEX_W_MAP7_F8_L_0 */ + { MOD_TABLE (MOD_VEX_MAP7_F8_L_0_W_0) }, + }, /* VEX_W_XOP_08_85_L_0 */ { { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 }, @@ -8153,11 +8501,21 @@ static const struct dis386 mod_table[][2] = { { "aesenc128kl", { XM, M }, 0 }, { "loadiwkey", { XM, EXx }, 0 }, }, + /* MOD_0F38F8 */ + { + { PREFIX_TABLE (PREFIX_0F38F8_M_0) }, + { X86_64_TABLE (X86_64_0F38F8_M_1) }, + }, { /* MOD_VEX_0F3849_X86_64_L_0_W_0 */ { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) }, { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) }, }, + { + /* MOD_VEX_MAP7_F8_L_0_W_0 */ + { Bad_Opcode }, + { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0_M_1) }, + }, #include "i386-dis-evex-mod.h" }; @@ -8769,6 +9127,9 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) case 0x3: vex_table_index = VEX_0F3A; break; + case 0x7: + vex_table_index = VEX_MAP7; + break; } ins->codep++; ins->vex.w = *ins->codep & 0x80; @@ -11248,6 +11609,20 @@ get32s (instr_info *ins, bfd_vma *res) return true; } +/* The function is used to get imm32, when imm32 is operand 0, and ins only has 2 operands. */ +static bool +get32_operand0 (instr_info *ins, bfd_vma *res) +{ + + if (!fetch_code (ins->info, ins->codep + 5)) + return false; + *res = *(ins->codep++ + 1) & (bfd_vma) 0xff; + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 8; + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 16; + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 24; + return true; +} + static bool get64 (instr_info *ins, uint64_t *res) { @@ -12008,6 +12383,10 @@ OP_I (instr_info *ins, int bytemode, int sizeflag) } } break; + case d_0_mode: + if (!get32_operand0 (ins, &op)) + return false; + break; case const_1_mode: if (ins->intel_syntax) oappend (ins, "1"); diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index cfc5a7a6172..bb58afcbc06 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -380,6 +380,7 @@ static bitfield cpu_flags[] = BITFIELD (RAO_INT), BITFIELD (FRED), BITFIELD (LKGS), + BITFIELD (USER_MSR), BITFIELD (MWAITX), BITFIELD (CLZERO), BITFIELD (OSPKE), @@ -1023,6 +1024,7 @@ process_i386_opcode_modifier (FILE *table, char *mod, unsigned int space, SPACE(0F3A), SPACE(EVEXMAP5), SPACE(EVEXMAP6), + SPACE(VEXMAP7), SPACE(XOP08), SPACE(XOP09), SPACE(XOP0A), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 149ae0e950c..a6f0d149d8c 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -223,6 +223,8 @@ enum i386_cpu CpuFRED, /* lkgs instruction required */ CpuLKGS, + /* Intel USER_MSR Instruction support required. */ + CpuUSER_MSR, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -471,6 +473,7 @@ typedef union i386_cpu_flags unsigned int cpurao_int:1; unsigned int cpufred:1; unsigned int cpulkgs:1; + unsigned int cpuuser_msr:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; @@ -573,6 +576,11 @@ enum /* Instrucion requires that destination must be distinct from source registers. */ #define DISTINCT_DEST 9 + /* Swap source and dest. + 1. instructions only has 2 register operands and operand1 in MODRM.REG + and operand0 in MODRM.R/M. + 2. instructions only has 2 operands and operand1 is IMM. */ +#define SWAP_SOURCE_DEST 10 OperandConstraint, /* instruction ignores operand size prefix and in Intel mode ignores mnemonic size suffix check. */ @@ -966,6 +974,7 @@ typedef struct insn_template 3: 0F3A opcode prefix / space. 5: EVEXMAP5 opcode prefix / space. 6: EVEXMAP6 opcode prefix / space. + 7: VEXMAP7 opcode prefix / space. 8: XOP 08 opcode space. 9: XOP 09 opcode space. A: XOP 0A opcode space. @@ -976,6 +985,7 @@ typedef struct insn_template #define SPACE_0F3A 3 #define SPACE_EVEXMAP5 5 #define SPACE_EVEXMAP6 6 +#define SPACE_VEXMAP7 7 #define SPACE_XOP08 8 #define SPACE_XOP09 9 #define SPACE_XOP0A 0xA diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index e60184ba154..75f3df6af2d 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -85,6 +85,7 @@ #define RegKludge OperandConstraint=REG_KLUDGE #define SwapSources OperandConstraint=SWAP_SOURCES #define Ugh OperandConstraint=UGH +#define SwapSourceDest OperandConstraint=SWAP_SOURCE_DEST #define IgnoreSize MnemonicSize=IGNORESIZE #define DefaultSize MnemonicSize=DEFAULTSIZE @@ -112,6 +113,8 @@ #define EVexMap5 OpcodeSpace=SPACE_EVEXMAP5 #define EVexMap6 OpcodeSpace=SPACE_EVEXMAP6 +#define VexMap7 OpcodeSpace=SPACE_VEXMAP7 + #define VexW0 VexW=VEXW0 #define VexW1 VexW=VEXW1 #define VexWIG VexW=VEXWIG @@ -3346,3 +3349,12 @@ erets, 0xf20f01ca, FRED|x64, NoSuf, {} eretu, 0xf30f01ca, FRED|x64, NoSuf, {} // FRED instructions end. + +// USER_MSR instructions. + +urdmsr, 0xf20f38f8, USER_MSR|x64, Modrm|IgnoreSize|SwapSourceDest|NoSuf, { Reg64, Reg64 } +urdmsr, 0xf2f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|IgnoreSize|NoSuf, { Imm32S, Reg64 } +uwrmsr, 0xf30f38f8, USER_MSR|x64, Modrm|IgnoreSize|NoSuf, { Reg64, Reg64 } +uwrmsr, 0xf3f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|IgnoreSize|SwapSourceDest|NoSuf, { Reg64, Imm32S } + +// USER_MSR instructions end. -- 2.31.1 ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH] Support Intel USER_MSR 2023-10-10 7:24 [PATCH] Support Intel USER_MSR Hu, Lin1 @ 2023-10-16 12:11 ` Jan Beulich 2023-10-18 7:51 ` Hu, Lin1 0 siblings, 1 reply; 33+ messages in thread From: Jan Beulich @ 2023-10-16 12:11 UTC (permalink / raw) To: Hu, Lin1; +Cc: hongjiu.lu, binutils On 10.10.2023 09:24, Hu, Lin1 wrote: > @@ -3863,6 +3864,8 @@ build_vex_prefix (const insn_template *t) > case SPACE_0F: > case SPACE_0F38: > case SPACE_0F3A: > + case SPACE_EVEXMAP5: > + case SPACE_VEXMAP7: > i.vex.bytes[0] = 0xc4; > break; I can see the need for the latter line you add, but why the former? (If it is needed for some reason, this is a strong hint at the description being overly brief.) > @@ -8752,6 +8755,18 @@ build_modrm_byte (void) > source = v; > v = tmp; > } > + if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCE_DEST) > + { > + if (dest == (unsigned int) ~0) > + source = source ^ 1; > + else > + { > + unsigned int tmp = source; > + > + source = dest; > + dest = tmp; > + } > + } Why is this needed? There's only a single register operand in both affected insn forms (see comment below on the 2-register form). Furthermore I think it would be easier if you "canonicalized" the early immediate to be the 1st operand, such that for all other purposes immediates remain first. As a cosmetic nit: Please have a blank line ahead of the if() block (if it needs to stay). > --- /dev/null > +++ b/gas/testsuite/gas/i386/user_msr-inval.s > @@ -0,0 +1,7 @@ > +# Check Illegal 32bit USER_MSR instructions > + > + .allow_index_reg > + .text > +_start: > + urdmsr %r12, %r14 #USER_MSR > + uwrmsr %r12, %r14 #USER_MSR As per comments on earlier series: What use are the comments here? (Applicable also again below.) > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s > @@ -0,0 +1,15 @@ > +# Check 64bit USER_MSR instructions > + > + .allow_index_reg > + .text > +_start: > + urdmsr %r14, %r12 #USER_MSR > + urdmsr $51515151, %r12 #USER_MSR > + uwrmsr %r12, %r14 #USER_MSR > + uwrmsr %r12, $51515151 #USER_MSR > + > +.intel_syntax noprefix Nit: Please indent directives. > + urdmsr r12, r14 #USER_MSR > + urdmsr r12, 51515151 #USER_MSR > + uwrmsr r14, r12 #USER_MSR > + uwrmsr 51515151, r12 #USER_MSR I think varying registers slightly more (such that each two-register form has one low-8 and one high-8 operand, totaling to two forms each to prove that the REX.[RB] bits are also correctly dealt with) would be better. Btw, what's the interaction here with APX? The legacy forms are going to use REX2, but the VEX forms would need EVEX variants then. > @@ -618,6 +620,8 @@ enum > w_mode, > /* double word operand */ > d_mode, > + /* double word operand 0 */ > + d_0_mode, Why is this needed? IOW why does d_mode not do? Or alternatively why isn't this a name indicating that it's an unsigned 32-bit value (as opposed to other 32-bit immediates in 64-bit mode)? > @@ -845,6 +849,7 @@ enum > REG_VEX_0FAE, > REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0, > REG_VEX_0F38F3_L_0, > + REG_VEX_MAP7_F8_L_0_W_0_M_1, > > REG_XOP_09_01_L_0, > REG_XOP_09_02_L_0, > @@ -893,8 +898,10 @@ enum > MOD_0FC7_REG_6, > MOD_0FC7_REG_7, > MOD_0F38DC_PREFIX_1, > + MOD_0F38F8, > > MOD_VEX_0F3849_X86_64_L_0_W_0, > + MOD_VEX_MAP7_F8_L_0_W_0, > }; As before - no new mod_table[] entries please which don't have both branches populated. > @@ -6791,6 +6839,297 @@ static const struct dis386 vex_table[][256] = { > { Bad_Opcode }, > { Bad_Opcode }, > }, > + /* VEX_MAP7 */ > + { > + /* 00 */ > + { Bad_Opcode }, I wonder whether adding a full new table (rather than some special case code) is really a god use of space. Of course if you know that more of it will be populated in the not too distant future ... > @@ -11248,6 +11609,20 @@ get32s (instr_info *ins, bfd_vma *res) > return true; > } > > +/* The function is used to get imm32, when imm32 is operand 0, and ins only has 2 operands. */ > +static bool > +get32_operand0 (instr_info *ins, bfd_vma *res) > +{ > + > + if (!fetch_code (ins->info, ins->codep + 5)) > + return false; > + *res = *(ins->codep++ + 1) & (bfd_vma) 0xff; > + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 8; > + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 16; > + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 24; > + return true; > +} Instead of this (which assumes ModRM.mod == 3) I think you want to arrange for dealing with ModRM first. We already have OP_Skip_MODRM() for such needs, which you could use in a first "hidden" operand. > @@ -3346,3 +3349,12 @@ erets, 0xf20f01ca, FRED|x64, NoSuf, {} > eretu, 0xf30f01ca, FRED|x64, NoSuf, {} > > // FRED instructions end. > + > +// USER_MSR instructions. > + > +urdmsr, 0xf20f38f8, USER_MSR|x64, Modrm|IgnoreSize|SwapSourceDest|NoSuf, { Reg64, Reg64 } Iirc RegMem is the attribute to use here, not any new one. > +urdmsr, 0xf2f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|IgnoreSize|NoSuf, { Imm32S, Reg64 } This and ... > +uwrmsr, 0xf30f38f8, USER_MSR|x64, Modrm|IgnoreSize|NoSuf, { Reg64, Reg64 } > +uwrmsr, 0xf3f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|IgnoreSize|SwapSourceDest|NoSuf, { Reg64, Imm32S } ... this needs to use Imm32, not Imm32S. I understand this is going to cause complications elsewhere, but we can't afford getting this wrong. Also in all forms I think you don't mean IgnoreSize, but NoRex64. Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH] Support Intel USER_MSR 2023-10-16 12:11 ` Jan Beulich @ 2023-10-18 7:51 ` Hu, Lin1 2023-10-19 8:36 ` Jan Beulich 0 siblings, 1 reply; 33+ messages in thread From: Hu, Lin1 @ 2023-10-18 7:51 UTC (permalink / raw) To: Beulich, Jan; +Cc: Lu, Hongjiu, binutils [-- Attachment #1: Type: text/plain, Size: 6975 bytes --] Thanks for your review. I responded individually under each comment. Attached is the modified version. BRs, Lin -----Original Message----- From: Jan Beulich <jbeulich@suse.com> Sent: Monday, October 16, 2023 8:11 PM To: Hu, Lin1 <lin1.hu@intel.com> Cc: Lu, Hongjiu <hongjiu.lu@intel.com>; binutils@sourceware.org Subject: Re: [PATCH] Support Intel USER_MSR On 10.10.2023 09:24, Hu, Lin1 wrote: > @@ -3863,6 +3864,8 @@ build_vex_prefix (const insn_template *t) > case SPACE_0F: > case SPACE_0F38: > case SPACE_0F3A: > + case SPACE_EVEXMAP5: > + case SPACE_VEXMAP7: > i.vex.bytes[0] = 0xc4; > break; > I can see the need for the latter line you add, but why the former? > (If it is needed for some reason, this is a strong hint at the description being overly brief.) I think it's a wrong that is made by reordering patches. I have removed it. > @@ -8752,6 +8755,18 @@ build_modrm_byte (void) > source = v; > v = tmp; > } > + if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCE_DEST) > + { > + if (dest == (unsigned int) ~0) > + source = source ^ 1; > + else > + { > + unsigned int tmp = source; > + > + source = dest; > + dest = tmp; > + } > + } > Why is this needed? There's only a single register operand in both affected insn forms (see comment below on the 2-register form). Furthermore I think it would be easier if you "canonicalized" the early immediate to be the 1st operand, such that for all other purposes immediates remain first. > As a cosmetic nit: Please have a blank line ahead of the if() block (if it needs to stay). Indeed, I've only kept the part that deals with a single register. Do you mean to complain to the person who designed the insn. Unfortunately, that's impossible. > --- /dev/null > +++ b/gas/testsuite/gas/i386/user_msr-inval.s > @@ -0,0 +1,7 @@ > +# Check Illegal 32bit USER_MSR instructions > + > + .allow_index_reg > + .text > +_start: > + urdmsr %r12, %r14 #USER_MSR > + uwrmsr %r12, %r14 #USER_MSR > As per comments on earlier series: What use are the comments here? > (Applicable also again below.) I have removed it. > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s > @@ -0,0 +1,15 @@ > +# Check 64bit USER_MSR instructions > + > + .allow_index_reg > + .text > +_start: > + urdmsr %r14, %r12 #USER_MSR > + urdmsr $51515151, %r12 #USER_MSR > + uwrmsr %r12, %r14 #USER_MSR > + uwrmsr %r12, $51515151 #USER_MSR > + > +.intel_syntax noprefix > Nit: Please indent directives. Have removed these comments. > + urdmsr r12, r14 #USER_MSR > + urdmsr r12, 51515151 #USER_MSR > + uwrmsr r14, r12 #USER_MSR > + uwrmsr 51515151, r12 #USER_MSR > I think varying registers slightly more (such that each two-register form has one low-8 and one high-8 operand, totaling to two forms each to prove that the REX.[RB] bits are also correctly dealt with) would be better. I have added some other tests here. > Btw, what's the interaction here with APX? The legacy forms are going to use REX2, but the VEX forms would need EVEX variants then. Not at the moment. If it gets added to the documentation later, I'll add its. > @@ -618,6 +620,8 @@ enum > w_mode, > /* double word operand */ > d_mode, > + /* double word operand 0 */ > + d_0_mode, > Why is this needed? IOW why does d_mode not do? Or alternatively why isn't this a name indicating that it's an unsigned 32-bit value (as opposed to other 32-bit immediates in 64-bit mode)? I want to output imm32 first, but modrm byte is behind imm32, so I need to skip modrm for the moment. If I use { "uwrmsr", { Id, Eq }, 0} Id will read modrm byte. The mode is for a imm32 not an unsigned 32-bit value, so its name doesn't indicate that it's an unsigned integer. > @@ -845,6 +849,7 @@ enum > REG_VEX_0FAE, > REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0, > REG_VEX_0F38F3_L_0, > + REG_VEX_MAP7_F8_L_0_W_0_M_1, > > REG_XOP_09_01_L_0, > REG_XOP_09_02_L_0, > @@ -893,8 +898,10 @@ enum > MOD_0FC7_REG_6, > MOD_0FC7_REG_7, > MOD_0F38DC_PREFIX_1, > + MOD_0F38F8, > > MOD_VEX_0F3849_X86_64_L_0_W_0, > + MOD_VEX_MAP7_F8_L_0_W_0, > }; > As before - no new mod_table[] entries please which don't have both branches populated. Have removed it. + { + /* MOD_VEX_MAP7_F8_L_0_W_0 */ + { Bad_Opcode }, + { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0_M_1) }, + }, > @@ -6791,6 +6839,297 @@ static const struct dis386 vex_table[][256] = { > { Bad_Opcode }, > { Bad_Opcode }, > }, > + /* VEX_MAP7 */ > + { > + /* 00 */ > + { Bad_Opcode }, > I wonder whether adding a full new table (rather than some special case > code) is really a god use of space. Of course if you know that more of it will be populated in the not too distant future ... I don't know, I'm just treating the new opcode_space MAP7 like other opcode_space. > @@ -11248,6 +11609,20 @@ get32s (instr_info *ins, bfd_vma *res) > return true; > } > > +/* The function is used to get imm32, when imm32 is operand 0, and > +ins only has 2 operands. */ static bool > +get32_operand0 (instr_info *ins, bfd_vma *res) { > + > + if (!fetch_code (ins->info, ins->codep + 5)) > + return false; > + *res = *(ins->codep++ + 1) & (bfd_vma) 0xff; > + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 8; > + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 16; > + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 24; > + return true; > +} > Instead of this (which assumes ModRM.mod == 3) I think you want to arrange for dealing with ModRM first. We already have OP_Skip_MODRM() for such needs, which you could use in a first "hidden" operand. I want to output imm32 first, but modrm byte is behind imm32, so I need to skip modrm for the moment. but I can't use OP_Skip_MODRM to deal with my problem, If I use it, I should add ins->codep-- at the end of get32_operand0. > @@ -3346,3 +3349,12 @@ erets, 0xf20f01ca, FRED|x64, NoSuf, {} eretu, > 0xf30f01ca, FRED|x64, NoSuf, {} > > // FRED instructions end. > + > +// USER_MSR instructions. > + > +urdmsr, 0xf20f38f8, USER_MSR|x64, > +Modrm|IgnoreSize|SwapSourceDest|NoSuf, { Reg64, Reg64 } > Iirc RegMem is the attribute to use here, not any new one. Indeed. > +urdmsr, 0xf2f8/0, USER_MSR|x64, > +Modrm|Vex128|VexMap7|VexW0|IgnoreSize|NoSuf, { Imm32S, Reg64 } > This and ... > +uwrmsr, 0xf30f38f8, USER_MSR|x64, Modrm|IgnoreSize|NoSuf, { Reg64, > +Reg64 } uwrmsr, 0xf3f8/0, USER_MSR|x64, > +Modrm|Vex128|VexMap7|VexW0|IgnoreSize|SwapSourceDest|NoSuf, { Reg64, > +Imm32S } > ... this needs to use Imm32, not Imm32S. I understand this is going to cause complications elsewhere, but we can't afford getting this wrong. > Also in all forms I think you don't mean IgnoreSize, but NoRex64. Have modified them. Jan [-- Attachment #2: 0001-Support-Intel-USER_MSR.patch --] [-- Type: application/octet-stream, Size: 240971 bytes --] From 8cb02e1cc961d3c605f84213f1e6e23a61f8e067 Mon Sep 17 00:00:00 2001 From: "Hu, Lin1" <lin1.hu@intel.com> Date: Fri, 25 Nov 2022 16:30:07 +0800 Subject: [PATCH] Support Intel USER_MSR gas/ChangeLog: * NEWS: Support Intel USER_MSR. * config/tc-i386.c: Add user_msr and add VEXMAP7 in opc_spc and build_vex_prefix. (build_modrm_byte): Swap Operands for USER_MSR. * doc/c-i386.texi: Document .user_msr. * testsuite/gas/i386/i386.exp: Run USER_MSR tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/user_msr-inval.l: New test. * testsuite/gas/i386/user_msr-inval.s: Ditto. * testsuite/gas/i386/x86-64-user_msr-intel.d: Ditto. * testsuite/gas/i386/x86-64-user_msr.d: Ditto. * testsuite/gas/i386/x86-64-user_msr.s: Ditto. opcodes/ChangeLog: * i386-dis.c (get32_operand0): Add a new function to get operand0 that is IMM32. (Gq): New. (Id0): Ditto. (get_valid_dis386): Add VEX_MAP7 in VEX prefix. (OP_I): Handle d_0_mode. (d_0_mode): New. (REG_VEX_MAP7_F8_L_0_W_0): New. (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64): Ditto. (X86_64_VEX_MAP7_F8_L_0_W_0_R_0): Ditto. (VEX_MAP7): Ditto. (VEX_LEN_MAP7_F8): Ditto. (VEX_W_MAP7_F8_L_0): Ditto. (MOD_0F38F8): Ditto. (PREFIX_0F38F8_M_0): Ditto. (PREFIX_0F38F8_M_1_X86_64): Ditto. (X86_64_0F38F8_M_1): Ditto. (PREFIX_0F38F8): Remove. (prefix_table): Add PREFIX_0F38F8_M_1_X86_64. Remove PREFIX_0F38F8. (reg_table): Add REG_VEX_MAP7_F8_L_0_W_0, PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64. (x86_64_table): Add X86_64_0F38F8_PREFIX_3_M_1, X86_64_VEX_MAP7_F8_L_0_W_0_R_0 and X86_64_0F38F8_M_1. (vex_table): Add VEX_MAP7. (vex_len_table): Add VEX_LEN_MAP7_F8, VEX_W_MAP7_F8_L_0. (mod_table): New entry for USER_MSR and add MOD_0F38F8. * i386-gen.c (cpu_flag_init): Add CPU_USER_MSR_FLAGS and CPU_ANY_USER_MSR_FLAGS. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (SPACE_VEXMAP7): New. (SWAP_SOURCE_DEST): Ditto. (CPU_USER_MSR_FLAGS): Ditoo. (CPU_ANY_USER_MSR_FLAGS): Ditto. (i386_cpu_flags): Add cpuuser_msr. * i386-opc.tbl: Add USER_MSR instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 2 + gas/config/tc-i386.c | 14 + gas/doc/c-i386.texi | 3 +- gas/testsuite/gas/i386/i386.exp | 1 + gas/testsuite/gas/i386/user_msr-inval.l | 3 + gas/testsuite/gas/i386/user_msr-inval.s | 7 + .../gas/i386/x86-64-user_msr-intel.d | 34 + gas/testsuite/gas/i386/x86-64-user_msr.d | 34 + gas/testsuite/gas/i386/x86-64-user_msr.s | 31 + gas/testsuite/gas/i386/x86-64.exp | 2 + opcodes/i386-dis.c | 381 ++++- opcodes/i386-gen.c | 2 + opcodes/i386-init.h | 816 +++++------ opcodes/i386-mnem.h | 1278 +++++++++-------- opcodes/i386-opc.h | 10 + opcodes/i386-opc.tbl | 12 + opcodes/i386-tbl.h | 272 ++-- 17 files changed, 1739 insertions(+), 1163 deletions(-) create mode 100644 gas/testsuite/gas/i386/user_msr-inval.l create mode 100644 gas/testsuite/gas/i386/user_msr-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr.d create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr.s diff --git a/gas/NEWS b/gas/NEWS index 71a1269b893..ab0e7813f27 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel USER_MSR instructions. + * Add support for Intel AVX10.1. * Add support for Intel PBNDKB instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 714354d5116..86727f3d963 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1164,6 +1164,7 @@ static const arch_entry cpu_arch[] = VECARCH (sm4, SM4, ANY_SM4, reset), SUBARCH (pbndkb, PBNDKB, PBNDKB, false), VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set), + SUBARCH (user_msr, USER_MSR, USER_MSR, false), }; #undef SUBARCH @@ -3863,6 +3864,7 @@ build_vex_prefix (const insn_template *t) case SPACE_0F: case SPACE_0F38: case SPACE_0F3A: + case SPACE_VEXMAP7: i.vex.bytes[0] = 0xc4; break; case SPACE_XOP08: @@ -7188,6 +7190,14 @@ match_template (char mnem_suffix) else check_register = 0; + if (t->mnem_off == MN_urdmsr + && (i.types[0].bitfield.imm32s || i.types[0].bitfield.imm64)) + i.types[0].bitfield.imm32 = 1; + + if (t->mnem_off == MN_uwrmsr + && (i.types[1].bitfield.imm32s || i.types[1].bitfield.imm64)) + i.types[1].bitfield.imm32 = 1; + overlap0 = operand_type_and (i.types[0], operand_types[0]); switch (t->operands) { @@ -8753,6 +8763,10 @@ build_modrm_byte (void) v = tmp; } + if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCE_DEST + && dest == (unsigned int) ~0) + source = source ^ 1; + if (v < MAX_OPERANDS) { gas_assert (i.tm.opcode_modifier.vexvvvv); diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index b04e1b00b4b..03ee980bef7 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -216,6 +216,7 @@ accept various extension mnemonics. For example, @code{avx10.1/512}, @code{avx10.1/256}, @code{avx10.1/128}, +@code{user_msr}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1650,7 +1651,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} @item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs} @item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4} -@item @samp{.pbndkb} +@item @samp{.pbndkb} @tab @samp{.user_msr} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index ee74bcd4615..81ce1e38b10 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -509,6 +509,7 @@ if [gas_32_check] then { run_dump_test "sm4" run_dump_test "sm4-intel" run_list_test "pbndkb-inval" + run_list_test "user_msr-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" diff --git a/gas/testsuite/gas/i386/user_msr-inval.l b/gas/testsuite/gas/i386/user_msr-inval.l new file mode 100644 index 00000000000..9618645bea8 --- /dev/null +++ b/gas/testsuite/gas/i386/user_msr-inval.l @@ -0,0 +1,3 @@ +.* Assembler messages: +.*:6: Error: `urdmsr' is only supported in 64-bit mode +.*:7: Error: `uwrmsr' is only supported in 64-bit mode diff --git a/gas/testsuite/gas/i386/user_msr-inval.s b/gas/testsuite/gas/i386/user_msr-inval.s new file mode 100644 index 00000000000..3762e2bd7b9 --- /dev/null +++ b/gas/testsuite/gas/i386/user_msr-inval.s @@ -0,0 +1,7 @@ +# Check Illegal 32bit USER_MSR instructions + + .allow_index_reg + .text +_start: + urdmsr %r12, %r14 + uwrmsr %r12, %r14 diff --git a/gas/testsuite/gas/i386/x86-64-user_msr-intel.d b/gas/testsuite/gas/i386/x86-64-user_msr-intel.d new file mode 100644 index 00000000000..94d969c68e9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr-intel.d @@ -0,0 +1,34 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 USER_MSR insns (Intel disassembly) +#source: x86-64-user_msr.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr r12,r14 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr rax,r14 +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr r12,rdx +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr rax,rdx +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr r12,0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr rax,0x3120f0f +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr r14,r12 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr r14,rax +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr rdx,r12 +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr rdx,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr 0x3120f0f,r12 +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr 0x3120f0f,rax +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr r12,r14 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr rax,r14 +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr r12,rdx +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr rax,rdx +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr r12,0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr rax,0x3120f0f +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr r14,r12 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr r14,rax +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr rdx,r12 +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr rdx,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr 0x3120f0f,r12 +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr 0x3120f0f,rax diff --git a/gas/testsuite/gas/i386/x86-64-user_msr.d b/gas/testsuite/gas/i386/x86-64-user_msr.d new file mode 100644 index 00000000000..d3e4543bc33 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr.d @@ -0,0 +1,34 @@ +#as: +#objdump: -dw +#name: x86_64 USER_MSR insns +#source: x86-64-user_msr.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr %r14,%r12 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr %r14,%rax +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr %rdx,%r12 +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr %rdx,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr \$0x3120f0f,%r12 +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr \$0x3120f0f,%rax +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr %r12,%r14 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr %rax,%r14 +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr %r12,%rdx +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr %rax,%rdx +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr %r12,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr %rax,\$0x3120f0f +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr %r14,%r12 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr %r14,%rax +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr %rdx,%r12 +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr %rdx,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr \$0x3120f0f,%r12 +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr \$0x3120f0f,%rax +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr %r12,%r14 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr %rax,%r14 +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr %r12,%rdx +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr %rax,%rdx +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr %r12,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr %rax,\$0x3120f0f diff --git a/gas/testsuite/gas/i386/x86-64-user_msr.s b/gas/testsuite/gas/i386/x86-64-user_msr.s new file mode 100644 index 00000000000..89d07245868 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s @@ -0,0 +1,31 @@ +# Check 64bit USER_MSR instructions + + .allow_index_reg + .text +_start: + urdmsr %r14, %r12 + urdmsr %r14, %rax + urdmsr %rdx, %r12 + urdmsr %rdx, %rax + urdmsr $51515151, %r12 + urdmsr $51515151, %rax + uwrmsr %r12, %r14 + uwrmsr %rax, %r14 + uwrmsr %r12, %rdx + uwrmsr %rax, %rdx + uwrmsr %r12, $51515151 + uwrmsr %rax, $51515151 + +.intel_syntax noprefix + urdmsr r12, r14 + urdmsr rax, r14 + urdmsr r12, rdx + urdmsr rax, rdx + urdmsr r12, 51515151 + urdmsr rax, 51515151 + uwrmsr r14, r12 + uwrmsr r14, rax + uwrmsr rdx, r12 + uwrmsr rdx, rax + uwrmsr 51515151, r12 + uwrmsr 51515151, rax diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 52711cdcf6f..5765d473e31 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -450,6 +450,8 @@ run_dump_test "x86-64-sm4" run_dump_test "x86-64-sm4-intel" run_dump_test "x86-64-pbndkb" run_dump_test "x86-64-pbndkb-intel" +run_dump_test "x86-64-user_msr" +run_dump_test "x86-64-user_msr-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 87ecf0f5e23..af53381096a 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -418,6 +418,7 @@ fetch_error (const instr_info *ins) #define Gv { OP_G, v_mode } #define Gd { OP_G, d_mode } #define Gdq { OP_G, dq_mode } +#define Gq { OP_G, q_mode } #define Gm { OP_G, m_mode } #define Gva { OP_G, va_mode } #define Gw { OP_G, w_mode } @@ -430,6 +431,7 @@ fetch_error (const instr_info *ins) #define Id { OP_I, d_mode } #define Iw { OP_I, w_mode } #define I1 { OP_I, const_1_mode } +#define Id0 { OP_I, d_0_mode } #define Jb { OP_J, b_mode } #define Jv { OP_J, v_mode } #define Jdqw { OP_J, dqw_mode } @@ -618,6 +620,8 @@ enum w_mode, /* double word operand */ d_mode, + /* double word operand 0 */ + d_0_mode, /* word operand with operand swapped */ w_swap_mode, /* double word operand with operand swapped */ @@ -845,6 +849,7 @@ enum REG_VEX_0FAE, REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0, REG_VEX_0F38F3_L_0, + REG_VEX_MAP7_F8_L_0_W_0, REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, @@ -893,6 +898,7 @@ enum MOD_0FC7_REG_6, MOD_0FC7_REG_7, MOD_0F38DC_PREFIX_1, + MOD_0F38F8, MOD_VEX_0F3849_X86_64_L_0_W_0, }; @@ -1010,7 +1016,8 @@ enum PREFIX_0F38F0, PREFIX_0F38F1, PREFIX_0F38F6, - PREFIX_0F38F8, + PREFIX_0F38F8_M_0, + PREFIX_0F38F8_M_1_X86_64, PREFIX_0F38FA, PREFIX_0F38FB, PREFIX_0F38FC, @@ -1073,6 +1080,7 @@ enum PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0, PREFIX_VEX_0F3AF0_L_0, + PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F6F, @@ -1217,6 +1225,7 @@ enum X86_64_0F18_REG_7_MOD_0, X86_64_0F24, X86_64_0F26, + X86_64_0F38F8_M_1, X86_64_0FC7_REG_6_MOD_3_PREFIX_1, X86_64_VEX_0F3849, @@ -1240,6 +1249,7 @@ enum X86_64_VEX_0F38ED, X86_64_VEX_0F38EE, X86_64_VEX_0F38EF, + X86_64_VEX_MAP7_F8_L_0_W_0_R_0, }; enum @@ -1259,7 +1269,8 @@ enum { VEX_0F = 0, VEX_0F38, - VEX_0F3A + VEX_0F3A, + VEX_MAP7 }; enum @@ -1350,6 +1361,7 @@ enum VEX_LEN_0F3ADE_W_0, VEX_LEN_0F3ADF, VEX_LEN_0F3AF0, + VEX_LEN_MAP7_F8, VEX_LEN_XOP_08_85, VEX_LEN_XOP_08_86, VEX_LEN_XOP_08_87, @@ -1510,6 +1522,7 @@ enum VEX_W_0F3ACE, VEX_W_0F3ACF, VEX_W_0F3ADE, + VEX_W_MAP7_F8_L_0, VEX_W_XOP_08_85_L_0, VEX_W_XOP_08_86_L_0, @@ -2849,6 +2862,10 @@ static const struct dis386 reg_table[][8] = { { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE }, { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE }, }, + /* REG_VEX_MAP7_F8_L_0_W_0 */ + { + { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) }, + }, /* REG_XOP_09_01_L_0 */ { { Bad_Opcode }, @@ -3555,13 +3572,22 @@ static const struct dis386 prefix_table[][4] = { { Bad_Opcode }, }, - /* PREFIX_0F38F8 */ + /* PREFIX_0F38F8_M_0 */ { { Bad_Opcode }, { "enqcmds", { Gva, M }, 0 }, { "movdir64b", { Gva, M }, 0 }, { "enqcmd", { Gva, M }, 0 }, }, + + /* PREFIX_0F38F8_M_1_X86_64 */ + { + { Bad_Opcode }, + { "uwrmsr", { Gq, Eq }, 0 }, + { Bad_Opcode }, + { "urdmsr", { Eq, Gq }, 0 }, + }, + /* PREFIX_0F38FA */ { { Bad_Opcode }, @@ -4014,6 +4040,14 @@ static const struct dis386 prefix_table[][4] = { { "rorxS", { Gdq, Edq, Ib }, 0 }, }, + /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */ + { + { Bad_Opcode }, + { "uwrmsr", { Id0, Eq }, 0 }, + { Bad_Opcode }, + { "urdmsr", { Eq, Id }, 0 }, + }, + #include "i386-dis-evex-prefix.h" }; @@ -4322,6 +4356,12 @@ static const struct dis386 x86_64_table[][2] = { { "movZ", { Td, Em }, 0 }, }, + { + /* X86_64_0F38F8_M_1 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) }, + }, + /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */ { { Bad_Opcode }, @@ -4453,6 +4493,13 @@ static const struct dis386 x86_64_table[][2] = { { Bad_Opcode }, { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, }, + + /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */ + { + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) }, + }, + }; static const struct dis386 three_byte_table[][256] = { @@ -4739,7 +4786,7 @@ static const struct dis386 three_byte_table[][256] = { { PREFIX_TABLE (PREFIX_0F38F6) }, { Bad_Opcode }, /* f8 */ - { PREFIX_TABLE (PREFIX_0F38F8) }, + { MOD_TABLE (MOD_0F38F8) }, { "movdiri", { Mdq, Gdq }, PREFIX_OPCODE }, { PREFIX_TABLE (PREFIX_0F38FA) }, { PREFIX_TABLE (PREFIX_0F38FB) }, @@ -6791,6 +6838,297 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, }, + /* VEX_MAP7 */ + { + /* 00 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 08 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 10 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 18 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 20 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 28 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 30 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 38 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 40 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 48 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 50 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 58 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 60 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 68 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 70 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 78 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 80 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 88 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 90 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 98 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* e0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* e8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f8 */ + { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + }, }; #include "i386-dis-evex.h" @@ -7205,6 +7543,11 @@ static const struct dis386 vex_len_table[][2] = { { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) }, }, + /* VEX_LEN_MAP7_F8 */ + { + { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) }, + }, + /* VEX_LEN_XOP_08_85 */ { { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) }, @@ -7811,6 +8154,10 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3ADE */ { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) }, }, + { + /* VEX_W_MAP7_F8_L_0 */ + { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) }, + }, /* VEX_W_XOP_08_85_L_0 */ { { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 }, @@ -8153,6 +8500,11 @@ static const struct dis386 mod_table[][2] = { { "aesenc128kl", { XM, M }, 0 }, { "loadiwkey", { XM, EXx }, 0 }, }, + /* MOD_0F38F8 */ + { + { PREFIX_TABLE (PREFIX_0F38F8_M_0) }, + { X86_64_TABLE (X86_64_0F38F8_M_1) }, + }, { /* MOD_VEX_0F3849_X86_64_L_0_W_0 */ { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) }, @@ -8769,6 +9121,9 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) case 0x3: vex_table_index = VEX_0F3A; break; + case 0x7: + vex_table_index = VEX_MAP7; + break; } ins->codep++; ins->vex.w = *ins->codep & 0x80; @@ -11248,6 +11603,20 @@ get32s (instr_info *ins, bfd_vma *res) return true; } +/* The function is used to get imm32, when imm32 is operand 0, and ins only has 2 operands. */ +static bool +get32_operand0 (instr_info *ins, bfd_vma *res) +{ + + if (!fetch_code (ins->info, ins->codep + 5)) + return false; + *res = *(ins->codep++ + 1) & (bfd_vma) 0xff; + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 8; + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 16; + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 24; + return true; +} + static bool get64 (instr_info *ins, uint64_t *res) { @@ -12008,6 +12377,10 @@ OP_I (instr_info *ins, int bytemode, int sizeflag) } } break; + case d_0_mode: + if (!get32_operand0 (ins, &op)) + return false; + break; case const_1_mode: if (ins->intel_syntax) oappend (ins, "1"); diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index cfc5a7a6172..bb58afcbc06 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -380,6 +380,7 @@ static bitfield cpu_flags[] = BITFIELD (RAO_INT), BITFIELD (FRED), BITFIELD (LKGS), + BITFIELD (USER_MSR), BITFIELD (MWAITX), BITFIELD (CLZERO), BITFIELD (OSPKE), @@ -1023,6 +1024,7 @@ process_i386_opcode_modifier (FILE *table, char *mod, unsigned int space, SPACE(0F3A), SPACE(EVEXMAP5), SPACE(EVEXMAP6), + SPACE(VEXMAP7), SPACE(XOP08), SPACE(XOP09), SPACE(XOP0A), diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h index 446a2d8a8cc..d27c8b4658e 100644 --- a/opcodes/i386-init.h +++ b/opcodes/i386-init.h @@ -26,7 +26,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_286_FLAGS \ { { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -36,7 +36,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_386_FLAGS \ { { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -46,7 +46,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_486_FLAGS \ { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -56,7 +56,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_586_FLAGS \ { { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -65,8 +65,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_686_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ @@ -75,8 +75,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_CMOV_FLAGS \ { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -86,7 +86,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_FXSR_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -96,7 +96,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_CLFLUSH_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -106,7 +106,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_NOP_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -116,7 +116,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_SYSCALL_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -126,7 +126,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_8087_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -136,7 +136,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_687_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ @@ -145,8 +145,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_FISTTP_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ @@ -155,8 +155,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_MMX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ @@ -166,7 +166,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_SSE_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ @@ -176,7 +176,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_SSE2_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ @@ -186,7 +186,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_SSE3_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -196,7 +196,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_PADLOCK_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ @@ -206,7 +206,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_SVME_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ @@ -216,7 +216,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_VMX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -226,7 +226,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_SMX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -236,7 +236,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_SSSE3_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -246,7 +246,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_SSE4A_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -256,7 +256,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_LZCNT_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -266,7 +266,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_POPCNT_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -276,7 +276,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_MONITOR_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -286,7 +286,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_SSE4_1_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -296,7 +296,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_SSE4_2_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -306,7 +306,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_AVX2_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -315,8 +315,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_AVX512CD_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -325,8 +325,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 0, 0, 0 } } #define CPU_AVX512ER_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -335,8 +335,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 0, 0, 0 } } #define CPU_AVX512PF_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -345,8 +345,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 0, 0, 0 } } #define CPU_AVX512DQ_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -355,8 +355,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 0, 0, 0 } } #define CPU_AVX512BW_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -365,8 +365,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 0, 0, 0 } } #define CPU_IAMCU_FLAGS \ { { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -376,7 +376,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_XSAVE_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -386,7 +386,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_XSAVEOPT_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -396,7 +396,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_AES_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ @@ -406,7 +406,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_PCLMULQDQ_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ @@ -416,7 +416,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_FMA_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -425,8 +425,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_FMA4_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -435,8 +435,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_XOP_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -445,8 +445,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_LWP_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -456,7 +456,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_BMI_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -466,7 +466,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_TBM_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -476,7 +476,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_MOVBE_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -486,7 +486,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_CX16_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -496,7 +496,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_LAHF_SAHF_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -506,7 +506,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_EPT_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -516,7 +516,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_RDTSCP_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -526,7 +526,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_FSGSBASE_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -536,7 +536,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_RDRND_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -546,7 +546,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_F16C_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -555,8 +555,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_BMI2_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -566,7 +566,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_RTM_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -576,7 +576,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_INVPCID_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -586,7 +586,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_VMFUNC_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -596,7 +596,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_MPX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -606,7 +606,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_RDSEED_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -616,7 +616,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ADX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -626,7 +626,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_PRFCHW_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -636,7 +636,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_SMAP_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -646,7 +646,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_SHA_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ @@ -656,7 +656,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_SHA512_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -665,8 +665,8 @@ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_SM3_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -675,8 +675,8 @@ 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_SM4_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -685,8 +685,8 @@ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_CLFLUSHOPT_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -696,7 +696,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_XSAVES_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -706,7 +706,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_XSAVEC_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -716,7 +716,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_PREFETCHWT1_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -726,7 +726,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_SE1_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -736,7 +736,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_CLWB_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -746,7 +746,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_AVX512IFMA_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -755,8 +755,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 0, 0, 0 } } #define CPU_AVX512VBMI_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -765,8 +765,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 0, 0, 0 } } #define CPU_AVX512_4FMAPS_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -775,8 +775,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 0, 0, 0 } } #define CPU_AVX512_4VNNIW_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -785,8 +785,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 0, 0, 0 } } #define CPU_AVX512_VPOPCNTDQ_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -795,8 +795,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 0, 0, 0 } } #define CPU_AVX512_VBMI2_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -805,8 +805,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 0, 0, 0 } } #define CPU_AVX512_VNNI_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -815,8 +815,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 0, 0, 0 } } #define CPU_AVX512_BITALG_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -825,8 +825,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 0, 0, 0 } } #define CPU_AVX512_BF16_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -835,8 +835,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 0, 0, 0 } } #define CPU_AVX512_VP2INTERSECT_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -845,8 +845,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 0, 0, 0 } } #define CPU_TDX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -856,7 +856,7 @@ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_AVX_VNNI_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -865,8 +865,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_AVX512_FP16_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -875,8 +875,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 0, 0, 0 } } #define CPU_PREFETCHI_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -886,7 +886,7 @@ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_AVX_IFMA_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -895,8 +895,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_AVX_VNNI_INT8_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -905,8 +905,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_AVX_VNNI_INT16_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -915,8 +915,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_CMPCCXADD_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -926,7 +926,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_WRMSRNS_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -936,7 +936,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_MSRLIST_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -946,7 +946,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_AVX_NE_CONVERT_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -955,8 +955,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_RAO_INT_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -966,7 +966,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_FRED_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -976,7 +976,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_LKGS_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -986,9 +986,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } -#define CPU_MWAITX_FLAGS \ +#define CPU_USER_MSR_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -996,9 +996,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } -#define CPU_CLZERO_FLAGS \ +#define CPU_MWAITX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1006,17 +1006,27 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } + +#define CPU_CLZERO_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_OSPKE_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_RDPID_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1024,9 +1034,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_PTWRITE_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1034,9 +1044,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_IBT_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1044,9 +1054,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_SHSTK_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1054,9 +1064,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_AMX_INT8_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1064,9 +1074,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_AMX_BF16_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1074,9 +1084,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_AMX_FP16_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1084,9 +1094,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_AMX_COMPLEX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1094,9 +1104,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_AMX_TILE_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1104,9 +1114,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_GFNI_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ @@ -1114,9 +1124,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_VAES_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -1124,9 +1134,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_VPCLMULQDQ_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -1134,9 +1144,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_WBNOINVD_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1144,9 +1154,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_PCONFIG_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1154,9 +1164,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_PBNDKB_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1164,9 +1174,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_WAITPKG_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1174,9 +1184,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_UINTR_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1184,9 +1194,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_CLDEMOTE_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1194,9 +1204,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_MOVDIRI_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1204,9 +1214,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_MOVDIR64B_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1214,9 +1224,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ENQCMD_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1225,8 +1235,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_SERIALIZE_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1235,8 +1245,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_RDPRU_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1245,8 +1255,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_MCOMMIT_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1255,8 +1265,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_SEV_ES_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ @@ -1265,8 +1275,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_TSXLDTRK_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1275,8 +1285,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_KL_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ @@ -1285,8 +1295,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_WIDEKL_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ @@ -1295,8 +1305,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_HRESET_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1305,8 +1315,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_INVLPGB_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1315,8 +1325,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_TLBSYNC_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1325,8 +1335,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_SNP_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ @@ -1335,8 +1345,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_RMPQUERY_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ @@ -1345,8 +1355,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_287_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1355,8 +1365,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_387_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1365,8 +1375,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_3DNOW_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ @@ -1375,8 +1385,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_3DNOWA_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ @@ -1385,8 +1395,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_64_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1395,8 +1405,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_AVX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -1405,8 +1415,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_HLE_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1415,8 +1425,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 0, 0, 0, 0 } } #define CPU_AVX512F_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -1425,8 +1435,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 0, 0, 0 } } #define CPU_AVX512VL_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -1435,8 +1445,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 1, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 1, 0, 0 } } #define CPU_UNKNOWN_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ @@ -1446,7 +1456,7 @@ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ - 1, 1, 0, 0 } } + 1, 1, 1, 0, 0 } } #define CPU_GENERIC32_FLAGS \ { { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1456,7 +1466,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_GENERIC64_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 0, 0, 0, \ @@ -1465,8 +1475,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_NONE_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1476,7 +1486,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_PENTIUMPRO_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ @@ -1485,8 +1495,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_P2_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, \ @@ -1495,8 +1505,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_P3_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, \ @@ -1505,8 +1515,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_P4_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, \ @@ -1515,8 +1525,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_NOCONA_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \ @@ -1525,8 +1535,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_CORE_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \ @@ -1535,8 +1545,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_CORE2_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \ @@ -1545,8 +1555,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_COREI7_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \ @@ -1555,8 +1565,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_K6_FLAGS \ { { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ @@ -1565,8 +1575,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_K6_2_FLAGS \ { { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ @@ -1575,8 +1585,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ATHLON_FLAGS \ { { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, \ @@ -1585,8 +1595,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_K8_FLAGS \ { { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 1, 1, 0, 0, 0, \ @@ -1595,8 +1605,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_AMDFAM10_FLAGS \ { { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \ @@ -1605,8 +1615,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_BDVER1_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ @@ -1615,8 +1625,8 @@ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_BDVER2_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ @@ -1625,8 +1635,8 @@ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_BDVER3_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ @@ -1635,58 +1645,58 @@ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_BDVER4_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_ZNVER1_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \ 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, \ 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_ZNVER2_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \ 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, \ 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \ - 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \ + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_ZNVER3_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \ 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, \ 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ - 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \ + 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_ZNVER4_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, \ 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, \ 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, \ - 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ - 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, \ - 1, 1, 0, 0 } } + 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \ + 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, \ + 0, 1, 1, 0, 0 } } #define CPU_BTVER1_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ @@ -1695,8 +1705,8 @@ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_BTVER2_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ @@ -1705,8 +1715,8 @@ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, \ + 0, 0, 0, 0, 0 } } #define CPU_ABM_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1716,7 +1726,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_AVX10_1_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -1725,8 +1735,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 1, \ 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 1, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 1, 0, 0 } } #define CPU_TSX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1735,8 +1745,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 0, 0, 0, 0 } } #define CPU_ANY_FXSR_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -1744,9 +1754,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ANY_8087_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, \ @@ -1755,8 +1765,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ANY_687_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ @@ -1766,7 +1776,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_FISTTP_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ @@ -1776,7 +1786,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_MMX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ @@ -1785,8 +1795,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ANY_SSE_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \ @@ -1794,9 +1804,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ANY_SSE2_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ @@ -1804,9 +1814,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ANY_SSE3_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ @@ -1816,7 +1826,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_SVME_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ @@ -1825,8 +1835,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ANY_VMX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1836,7 +1846,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_SSSE3_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1846,7 +1856,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_SSE4A_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1856,7 +1866,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_SSE4_1_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1866,7 +1876,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_SSE4_2_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1876,7 +1886,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX2_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1884,9 +1894,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 1, 1, 0, 0 } } + 0, 1, 1, 0, 0 } } #define CPU_ANY_AVX512CD_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1896,7 +1906,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX512ER_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1906,7 +1916,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX512PF_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1916,7 +1926,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX512DQ_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1926,7 +1936,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX512BW_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1936,7 +1946,7 @@ 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_IAMCU_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1946,17 +1956,17 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_XSAVE_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, \ 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, \ 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, \ - 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, \ - 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 1, 0, 0 } } + 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ + 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 1, 0, 0 } } #define CPU_ANY_XSAVEOPT_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1966,7 +1976,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AES_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1974,9 +1984,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_PCLMULQDQ_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1984,9 +1994,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_FMA_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1996,7 +2006,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_FMA4_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2006,7 +2016,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_XOP_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2016,7 +2026,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_LWP_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2026,7 +2036,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_EPT_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2036,7 +2046,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_F16C_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2046,7 +2056,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_RTM_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2055,8 +2065,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ANY_VMFUNC_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2066,7 +2076,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_MPX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2076,7 +2086,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_SHA_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2086,7 +2096,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_SHA512_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2096,7 +2106,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_SM3_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2106,7 +2116,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_SM4_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2116,7 +2126,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_XSAVES_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2126,7 +2136,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_XSAVEC_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2136,7 +2146,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX512IFMA_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2146,7 +2156,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX512VBMI_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2156,7 +2166,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX512_4FMAPS_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2166,7 +2176,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX512_4VNNIW_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2176,7 +2186,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX512_VPOPCNTDQ_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2186,7 +2196,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX512_VBMI2_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2196,7 +2206,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX512_VNNI_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2206,7 +2216,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX512_BITALG_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2216,7 +2226,7 @@ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX512_BF16_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2226,7 +2236,7 @@ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX512_VP2INTERSECT_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2236,7 +2246,7 @@ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX_VNNI_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2246,7 +2256,7 @@ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX512_FP16_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2256,7 +2266,7 @@ 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX_IFMA_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2266,7 +2276,7 @@ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX_VNNI_INT8_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2276,7 +2286,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX_VNNI_INT16_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2286,7 +2296,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX_NE_CONVERT_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2296,7 +2306,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_FRED_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2306,7 +2316,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_LKGS_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2316,17 +2326,17 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_OSPKE_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AMX_INT8_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2334,9 +2344,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AMX_BF16_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2344,9 +2354,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AMX_FP16_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2354,9 +2364,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AMX_COMPLEX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2364,9 +2374,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_AMX_TILE_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2374,9 +2384,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_GFNI_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2384,9 +2394,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_VAES_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2394,9 +2404,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_VPCLMULQDQ_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2404,9 +2414,9 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0 } } #define CPU_ANY_SEV_ES_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2415,8 +2425,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ANY_TSXLDTRK_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2425,8 +2435,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ANY_KL_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2435,8 +2445,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ANY_WIDEKL_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2445,8 +2455,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ANY_SNP_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2455,8 +2465,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ANY_RMPQUERY_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2465,8 +2475,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ANY_287_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ @@ -2475,8 +2485,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ANY_387_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ @@ -2485,8 +2495,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ANY_3DNOW_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2495,8 +2505,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ANY_3DNOWA_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2505,8 +2515,8 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ - 0, 0, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ + 0, 0, 0, 0, 0 } } #define CPU_ANY_AVX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2514,9 +2524,9 @@ 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 1, 1, 0, 0 } } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 1, 1, 0, 0 } } #define CPU_ANY_AVX512F_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2526,7 +2536,7 @@ 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 1, 1, 0, 0 } } + 0, 1, 1, 0, 0 } } #define CPU_ANY_AVX512VL_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -2536,5 +2546,5 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 1, 0, 0 } } + 0, 0, 1, 0, 0 } } diff --git a/opcodes/i386-mnem.h b/opcodes/i386-mnem.h index 5d0b4d10469..3823e8ead4f 100644 --- a/opcodes/i386-mnem.h +++ b/opcodes/i386-mnem.h @@ -1587,776 +1587,778 @@ extern const char i386_mnemonics[]; #define MN_stmxcsr (MN_vstmxcsr + 1) #define MN_vstmxcsr 0x3092 #define MN_blsr 0x309b -#define MN_rdmsr 0x30a0 -#define MN_wrmsr 0x30a6 -#define MN_btr 0x30ac -#define MN_xcrypt_ctr 0x30b0 -#define MN_xcryptctr 0x30bb -#define MN_ltr 0x30c5 -#define MN_str 0x30c9 -#define MN_bextr 0x30cd -#define MN_fdivr 0x30d3 -#define MN_fidivr 0x30d9 -#define MN_rex_wr 0x30e0 -#define MN_aas 0x30e7 -#define MN_scas 0x30eb -#define MN_das 0x30f0 -#define MN_fabs 0x30f4 -#define MN_movabs 0x30f9 +#define MN_rdmsr (MN_urdmsr + 1) +#define MN_urdmsr 0x30a0 +#define MN_wrmsr (MN_uwrmsr + 1) +#define MN_uwrmsr 0x30a7 +#define MN_btr 0x30ae +#define MN_xcrypt_ctr 0x30b2 +#define MN_xcryptctr 0x30bd +#define MN_ltr 0x30c7 +#define MN_str 0x30cb +#define MN_bextr 0x30cf +#define MN_fdivr 0x30d5 +#define MN_fidivr 0x30db +#define MN_rex_wr 0x30e2 +#define MN_aas 0x30e9 +#define MN_scas 0x30ed +#define MN_das 0x30f2 +#define MN_fabs 0x30f6 +#define MN_movabs 0x30fb #define MN_cs (MN_blcs + 2) -#define MN_blcs 0x3100 +#define MN_blcs 0x3102 #define MN_ds (MN_lds + 1) -#define MN_lds 0x3105 -#define MN_enqcmds 0x3109 -#define MN_lods 0x3111 -#define MN_vpdpbssds 0x3116 -#define MN_vp4dpwssds 0x3120 -#define MN_vpdpwssds 0x312b -#define MN_vpdpbusds 0x3135 -#define MN_vpdpwusds 0x313f -#define MN_vpdpbsuds 0x3149 -#define MN_vpdpwsuds 0x3153 -#define MN_vpdpbuuds 0x315d -#define MN_vpdpwuuds 0x3167 +#define MN_lds 0x3107 +#define MN_enqcmds 0x310b +#define MN_lods 0x3113 +#define MN_vpdpbssds 0x3118 +#define MN_vp4dpwssds 0x3122 +#define MN_vpdpwssds 0x312d +#define MN_vpdpbusds 0x3137 +#define MN_vpdpwusds 0x3141 +#define MN_vpdpbsuds 0x314b +#define MN_vpdpwsuds 0x3155 +#define MN_vpdpbuuds 0x315f +#define MN_vpdpwuuds 0x3169 #define MN_es (MN_les + 1) -#define MN_les 0x3171 -#define MN_xsaves 0x3175 +#define MN_les 0x3173 +#define MN_xsaves 0x3177 #define MN_fs (MN_lfs + 1) -#define MN_lfs 0x317c +#define MN_lfs 0x317e #define MN_gs (MN_lkgs + 2) -#define MN_lkgs 0x3180 -#define MN_lgs 0x3185 -#define MN_swapgs 0x3189 -#define MN_fchs 0x3190 -#define MN_js 0x3195 -#define MN_encls 0x3198 +#define MN_lkgs 0x3182 +#define MN_lgs 0x3187 +#define MN_swapgs 0x318b +#define MN_fchs 0x3192 +#define MN_js 0x3197 +#define MN_encls 0x319a #define MN_emms (MN_femms + 1) -#define MN_femms 0x319e +#define MN_femms 0x31a0 #define MN_ins (MN_lwpins + 3) -#define MN_lwpins 0x31a4 -#define MN_jns 0x31ab -#define MN_wrmsrns 0x31af -#define MN_setns 0x31b7 -#define MN_cmovns 0x31bd -#define MN_fcos 0x31c4 -#define MN_fsincos 0x31c9 -#define MN_stos 0x31d1 -#define MN_vfmaddsub231ps 0x31d6 -#define MN_vfmsub231ps 0x31e5 -#define MN_vfnmsub231ps 0x31f1 -#define MN_vfmsubadd231ps 0x31fe -#define MN_vfmadd231ps 0x320d -#define MN_vfnmadd231ps 0x3219 -#define MN_vfmaddsub132ps 0x3226 -#define MN_vfmsub132ps 0x3235 -#define MN_vfnmsub132ps 0x3241 -#define MN_vfmsubadd132ps 0x324e -#define MN_vfmadd132ps 0x325d -#define MN_vfnmadd132ps 0x3269 -#define MN_vcvtneebf162ps 0x3276 -#define MN_vbcstnebf162ps 0x3285 -#define MN_vcvtneobf162ps 0x3294 +#define MN_lwpins 0x31a6 +#define MN_jns 0x31ad +#define MN_wrmsrns 0x31b1 +#define MN_setns 0x31b9 +#define MN_cmovns 0x31bf +#define MN_fcos 0x31c6 +#define MN_fsincos 0x31cb +#define MN_stos 0x31d3 +#define MN_vfmaddsub231ps 0x31d8 +#define MN_vfmsub231ps 0x31e7 +#define MN_vfnmsub231ps 0x31f3 +#define MN_vfmsubadd231ps 0x3200 +#define MN_vfmadd231ps 0x320f +#define MN_vfnmadd231ps 0x321b +#define MN_vfmaddsub132ps 0x3228 +#define MN_vfmsub132ps 0x3237 +#define MN_vfnmsub132ps 0x3243 +#define MN_vfmsubadd132ps 0x3250 +#define MN_vfmadd132ps 0x325f +#define MN_vfnmadd132ps 0x326b +#define MN_vcvtneebf162ps 0x3278 +#define MN_vbcstnebf162ps 0x3287 +#define MN_vcvtneobf162ps 0x3296 #define MN_cvtpd2ps (MN_vcvtpd2ps + 1) -#define MN_vcvtpd2ps 0x32a3 -#define MN_vcvtneeph2ps 0x32ad -#define MN_vcvtneoph2ps 0x32ba -#define MN_vcvtph2ps 0x32c7 -#define MN_vbcstnesh2ps 0x32d1 -#define MN_vpermi2ps 0x32de -#define MN_cvtpi2ps 0x32e8 -#define MN_vpermil2ps 0x32f1 -#define MN_vexp2ps 0x32fc +#define MN_vcvtpd2ps 0x32a5 +#define MN_vcvtneeph2ps 0x32af +#define MN_vcvtneoph2ps 0x32bc +#define MN_vcvtph2ps 0x32c9 +#define MN_vbcstnesh2ps 0x32d3 +#define MN_vpermi2ps 0x32e0 +#define MN_cvtpi2ps 0x32ea +#define MN_vpermil2ps 0x32f3 +#define MN_vexp2ps 0x32fe #define MN_cvtdq2ps (MN_vcvtdq2ps + 1) -#define MN_vcvtdq2ps 0x3304 -#define MN_vcvtudq2ps 0x330e -#define MN_vcvtqq2ps 0x3319 -#define MN_vcvtuqq2ps 0x3323 -#define MN_vpermt2ps 0x332e -#define MN_vfmaddsub213ps 0x3338 -#define MN_vfmsub213ps 0x3347 -#define MN_vfnmsub213ps 0x3353 -#define MN_vfmsubadd213ps 0x3360 -#define MN_vfmadd213ps 0x336f -#define MN_vfnmadd213ps 0x337b -#define MN_vrcp14ps 0x3388 -#define MN_vrsqrt14ps 0x3391 -#define MN_tdpbf16ps 0x339c -#define MN_vdpbf16ps 0x33a6 -#define MN_tcmmrlfp16ps 0x33b0 -#define MN_tcmmimfp16ps 0x33bd -#define MN_tdpfp16ps 0x33ca -#define MN_vrcp28ps 0x33d4 -#define MN_vrsqrt28ps 0x33dd +#define MN_vcvtdq2ps 0x3306 +#define MN_vcvtudq2ps 0x3310 +#define MN_vcvtqq2ps 0x331b +#define MN_vcvtuqq2ps 0x3325 +#define MN_vpermt2ps 0x3330 +#define MN_vfmaddsub213ps 0x333a +#define MN_vfmsub213ps 0x3349 +#define MN_vfnmsub213ps 0x3355 +#define MN_vfmsubadd213ps 0x3362 +#define MN_vfmadd213ps 0x3371 +#define MN_vfnmadd213ps 0x337d +#define MN_vrcp14ps 0x338a +#define MN_vrsqrt14ps 0x3393 +#define MN_tdpbf16ps 0x339e +#define MN_vdpbf16ps 0x33a8 +#define MN_tcmmrlfp16ps 0x33b2 +#define MN_tcmmimfp16ps 0x33bf +#define MN_tdpfp16ps 0x33cc +#define MN_vrcp28ps 0x33d6 +#define MN_vrsqrt28ps 0x33df #define MN_movaps (MN_vmovaps + 1) -#define MN_vmovaps 0x33e8 +#define MN_vmovaps 0x33ea #define MN_subps (MN_addsubps + 3) #define MN_addsubps (MN_vfmaddsubps + 3) -#define MN_vfmaddsubps 0x33f0 -#define MN_vaddsubps 0x33fc +#define MN_vfmaddsubps 0x33f2 +#define MN_vaddsubps 0x33fe #define MN_hsubps (MN_vhsubps + 1) -#define MN_vhsubps 0x3406 -#define MN_vfmsubps 0x340e -#define MN_vfnmsubps 0x3417 -#define MN_vsubps 0x3421 -#define MN_vgatherpf0dps 0x3428 -#define MN_vscatterpf0dps 0x3436 -#define MN_vgatherpf1dps 0x3445 -#define MN_vscatterpf1dps 0x3453 +#define MN_vhsubps 0x3408 +#define MN_vfmsubps 0x3410 +#define MN_vfnmsubps 0x3419 +#define MN_vsubps 0x3423 +#define MN_vgatherpf0dps 0x342a +#define MN_vscatterpf0dps 0x3438 +#define MN_vgatherpf1dps 0x3447 +#define MN_vscatterpf1dps 0x3455 #define MN_addps (MN_vfmsubaddps + 6) -#define MN_vfmsubaddps 0x3462 +#define MN_vfmsubaddps 0x3464 #define MN_haddps (MN_vhaddps + 1) -#define MN_vhaddps 0x346e -#define MN_v4fmaddps 0x3476 -#define MN_vfmaddps 0x3480 -#define MN_v4fnmaddps 0x3489 -#define MN_vfnmaddps 0x3494 -#define MN_vaddps 0x349e +#define MN_vhaddps 0x3470 +#define MN_v4fmaddps 0x3478 +#define MN_vfmaddps 0x3482 +#define MN_v4fnmaddps 0x348b +#define MN_vfnmaddps 0x3496 +#define MN_vaddps 0x34a0 #define MN_andps (MN_vexpandps + 4) -#define MN_vexpandps 0x34a5 -#define MN_vandps 0x34af +#define MN_vexpandps 0x34a7 +#define MN_vandps 0x34b1 #define MN_blendps (MN_vblendps + 1) -#define MN_vblendps 0x34b6 +#define MN_vblendps 0x34b8 #define MN_roundps (MN_vroundps + 1) -#define MN_vroundps 0x34bf -#define MN_vgatherdps 0x34c8 -#define MN_vscatterdps 0x34d3 +#define MN_vroundps 0x34c1 +#define MN_vgatherdps 0x34ca +#define MN_vscatterdps 0x34d5 #define MN_cmpunordps (MN_vcmpunordps + 1) -#define MN_vcmpunordps 0x34df +#define MN_vcmpunordps 0x34e1 #define MN_cmpordps (MN_vcmpordps + 1) -#define MN_vcmpordps 0x34eb -#define MN_vreduceps 0x34f5 -#define MN_vrangeps 0x34ff -#define MN_vcmpngeps 0x3508 -#define MN_vcmpgeps 0x3512 -#define MN_vrndscaleps 0x351b +#define MN_vcmpordps 0x34ed +#define MN_vreduceps 0x34f7 +#define MN_vrangeps 0x3501 +#define MN_vcmpngeps 0x350a +#define MN_vcmpgeps 0x3514 +#define MN_vrndscaleps 0x351d #define MN_cmpnleps (MN_vcmpnleps + 1) -#define MN_vcmpnleps 0x3527 +#define MN_vcmpnleps 0x3529 #define MN_cmpleps (MN_vcmpleps + 1) -#define MN_vcmpleps 0x3531 -#define MN_vcmpfalseps 0x353a -#define MN_vcmptrueps 0x3546 -#define MN_vscalefps 0x3551 +#define MN_vcmpleps 0x3533 +#define MN_vcmpfalseps 0x353c +#define MN_vcmptrueps 0x3548 +#define MN_vscalefps 0x3553 #define MN_shufps (MN_vshufps + 1) -#define MN_vshufps 0x355b +#define MN_vshufps 0x355d #define MN_unpckhps (MN_vunpckhps + 1) -#define MN_vunpckhps 0x3563 +#define MN_vunpckhps 0x3565 #define MN_movlhps (MN_vmovlhps + 1) -#define MN_vmovlhps 0x356d +#define MN_vmovlhps 0x356f #define MN_movhps (MN_vmovhps + 1) -#define MN_vmovhps 0x3576 +#define MN_vmovhps 0x3578 #define MN_movmskps (MN_vmovmskps + 1) -#define MN_vmovmskps 0x357e +#define MN_vmovmskps 0x3580 #define MN_movhlps (MN_vmovhlps + 1) -#define MN_vmovhlps 0x3588 -#define MN_vpermilps 0x3591 +#define MN_vmovhlps 0x358a +#define MN_vpermilps 0x3593 #define MN_unpcklps (MN_vunpcklps + 1) -#define MN_vunpcklps 0x359b +#define MN_vunpcklps 0x359d #define MN_mulps (MN_vmulps + 1) -#define MN_vmulps 0x35a5 +#define MN_vmulps 0x35a7 #define MN_movlps (MN_vmovlps + 1) -#define MN_vmovlps 0x35ac -#define MN_cmps 0x35b4 -#define MN_vblendmps 0x35b9 -#define MN_vfixupimmps 0x35c3 -#define MN_vpermps 0x35cf +#define MN_vmovlps 0x35ae +#define MN_cmps 0x35b6 +#define MN_vblendmps 0x35bb +#define MN_vfixupimmps 0x35c5 +#define MN_vpermps 0x35d1 #define MN_andnps (MN_vandnps + 1) -#define MN_vandnps 0x35d7 +#define MN_vandnps 0x35d9 #define MN_minps (MN_vminps + 1) -#define MN_vminps 0x35df -#define MN_seamops 0x35e6 +#define MN_vminps 0x35e1 +#define MN_seamops 0x35e8 #define MN_rcpps (MN_vrcpps + 1) -#define MN_vrcpps 0x35ee +#define MN_vrcpps 0x35f0 #define MN_dpps (MN_vdpps + 1) -#define MN_vdpps 0x35f5 +#define MN_vdpps 0x35f7 #define MN_cmpps (MN_vcmpps + 1) -#define MN_vcmpps 0x35fb -#define MN_vgetexpps 0x3602 -#define MN_vgatherpf0qps 0x360c -#define MN_vscatterpf0qps 0x361a -#define MN_vgatherpf1qps 0x3629 -#define MN_vscatterpf1qps 0x3637 -#define MN_vcmpunord_qps 0x3646 -#define MN_vcmpord_qps 0x3654 +#define MN_vcmpps 0x35fd +#define MN_vgetexpps 0x3604 +#define MN_vgatherpf0qps 0x360e +#define MN_vscatterpf0qps 0x361c +#define MN_vgatherpf1qps 0x362b +#define MN_vscatterpf1qps 0x3639 +#define MN_vcmpunord_qps 0x3648 +#define MN_vcmpord_qps 0x3656 #define MN_cmpneqps (MN_vcmpneqps + 1) -#define MN_vcmpneqps 0x3660 +#define MN_vcmpneqps 0x3662 #define MN_cmpeqps (MN_vcmpeqps + 1) -#define MN_vcmpeqps 0x366a -#define MN_vcmpge_oqps 0x3673 -#define MN_vcmple_oqps 0x367f -#define MN_vcmpfalse_oqps 0x368b -#define MN_vcmpneq_oqps 0x369a -#define MN_vcmpeq_oqps 0x36a7 -#define MN_vcmpgt_oqps 0x36b3 -#define MN_vcmplt_oqps 0x36bf -#define MN_vgatherqps 0x36cb -#define MN_vscatterqps 0x36d6 -#define MN_vcmpnge_uqps 0x36e2 -#define MN_vcmpnle_uqps 0x36ef -#define MN_vcmptrue_uqps 0x36fc -#define MN_vcmpneq_uqps 0x370a -#define MN_vcmpeq_uqps 0x3717 -#define MN_vcmpngt_uqps 0x3723 -#define MN_vcmpnlt_uqps 0x3730 +#define MN_vcmpeqps 0x366c +#define MN_vcmpge_oqps 0x3675 +#define MN_vcmple_oqps 0x3681 +#define MN_vcmpfalse_oqps 0x368d +#define MN_vcmpneq_oqps 0x369c +#define MN_vcmpeq_oqps 0x36a9 +#define MN_vcmpgt_oqps 0x36b5 +#define MN_vcmplt_oqps 0x36c1 +#define MN_vgatherqps 0x36cd +#define MN_vscatterqps 0x36d8 +#define MN_vcmpnge_uqps 0x36e4 +#define MN_vcmpnle_uqps 0x36f1 +#define MN_vcmptrue_uqps 0x36fe +#define MN_vcmpneq_uqps 0x370c +#define MN_vcmpeq_uqps 0x3719 +#define MN_vcmpngt_uqps 0x3725 +#define MN_vcmpnlt_uqps 0x3732 #define MN_orps (MN_vorps + 1) -#define MN_vorps 0x373d +#define MN_vorps 0x373f #define MN_xorps (MN_vxorps + 1) -#define MN_vxorps 0x3743 -#define MN_vcmpunord_sps 0x374a -#define MN_vcmpord_sps 0x3758 -#define MN_vcmpge_osps 0x3764 -#define MN_vcmple_osps 0x3770 -#define MN_vcmpfalse_osps 0x377c -#define MN_vcmpneq_osps 0x378b -#define MN_vcmpeq_osps 0x3798 -#define MN_vcmpgt_osps 0x37a4 -#define MN_vcmplt_osps 0x37b0 -#define MN_vfpclassps 0x37bc -#define MN_vcompressps 0x37c7 -#define MN_vcmpnge_usps 0x37d3 -#define MN_vcmpnle_usps 0x37e0 -#define MN_vcmptrue_usps 0x37ed -#define MN_vcmpneq_usps 0x37fb -#define MN_vcmpeq_usps 0x3808 -#define MN_vcmpngt_usps 0x3814 -#define MN_vcmpnlt_usps 0x3821 +#define MN_vxorps 0x3745 +#define MN_vcmpunord_sps 0x374c +#define MN_vcmpord_sps 0x375a +#define MN_vcmpge_osps 0x3766 +#define MN_vcmple_osps 0x3772 +#define MN_vcmpfalse_osps 0x377e +#define MN_vcmpneq_osps 0x378d +#define MN_vcmpeq_osps 0x379a +#define MN_vcmpgt_osps 0x37a6 +#define MN_vcmplt_osps 0x37b2 +#define MN_vfpclassps 0x37be +#define MN_vcompressps 0x37c9 +#define MN_vcmpnge_usps 0x37d5 +#define MN_vcmpnle_usps 0x37e2 +#define MN_vcmptrue_usps 0x37ef +#define MN_vcmpneq_usps 0x37fd +#define MN_vcmpeq_usps 0x380a +#define MN_vcmpngt_usps 0x3816 +#define MN_vcmpnlt_usps 0x3823 #define MN_extractps (MN_vextractps + 1) -#define MN_vextractps 0x382e -#define MN_vcmpngtps 0x3839 -#define MN_vcmpgtps 0x3843 +#define MN_vextractps 0x3830 +#define MN_vcmpngtps 0x383b +#define MN_vcmpgtps 0x3845 #define MN_cmpnltps (MN_vcmpnltps + 1) -#define MN_vcmpnltps 0x384c +#define MN_vcmpnltps 0x384e #define MN_cmpltps (MN_vcmpltps + 1) -#define MN_vcmpltps 0x3856 -#define MN_vgetmantps 0x385f +#define MN_vcmpltps 0x3858 +#define MN_vgetmantps 0x3861 #define MN_movntps (MN_vmovntps + 1) -#define MN_vmovntps 0x386a +#define MN_vmovntps 0x386c #define MN_insertps (MN_vinsertps + 1) -#define MN_vinsertps 0x3873 +#define MN_vinsertps 0x3875 #define MN_sqrtps (MN_rsqrtps + 1) #define MN_rsqrtps (MN_vrsqrtps + 1) -#define MN_vrsqrtps 0x387d -#define MN_vsqrtps 0x3886 -#define MN_vtestps 0x388e +#define MN_vrsqrtps 0x387f +#define MN_vsqrtps 0x3888 +#define MN_vtestps 0x3890 #define MN_movups (MN_vmovups + 1) -#define MN_vmovups 0x3896 +#define MN_vmovups 0x3898 #define MN_blendvps (MN_vblendvps + 1) -#define MN_vblendvps 0x389e +#define MN_vblendvps 0x38a0 #define MN_divps (MN_vdivps + 1) -#define MN_vdivps 0x38a8 -#define MN_vmaskmovps 0x38af +#define MN_vdivps 0x38aa +#define MN_vmaskmovps 0x38b1 #define MN_maxps (MN_vmaxps + 1) -#define MN_vmaxps 0x38ba -#define MN_vfrczps 0x38c1 -#define MN_xrstors 0x38c9 +#define MN_vmaxps 0x38bc +#define MN_vfrczps 0x38c3 +#define MN_xrstors 0x38cb #define MN_ss (MN_vfmsub231ss + 9) -#define MN_vfmsub231ss 0x38d1 -#define MN_vfnmsub231ss 0x38dd -#define MN_vfmadd231ss 0x38ea -#define MN_vfnmadd231ss 0x38f6 -#define MN_vfmsub132ss 0x3903 -#define MN_vfnmsub132ss 0x390f -#define MN_vfmadd132ss 0x391c -#define MN_vfnmadd132ss 0x3928 +#define MN_vfmsub231ss 0x38d3 +#define MN_vfnmsub231ss 0x38df +#define MN_vfmadd231ss 0x38ec +#define MN_vfnmadd231ss 0x38f8 +#define MN_vfmsub132ss 0x3905 +#define MN_vfnmsub132ss 0x3911 +#define MN_vfmadd132ss 0x391e +#define MN_vfnmadd132ss 0x392a #define MN_cvtsd2ss (MN_vcvtsd2ss + 1) -#define MN_vcvtsd2ss 0x3935 -#define MN_vcvtsh2ss 0x393f +#define MN_vcvtsd2ss 0x3937 +#define MN_vcvtsh2ss 0x3941 #define MN_cvtsi2ss (MN_vcvtsi2ss + 1) -#define MN_vcvtsi2ss 0x3949 -#define MN_vcvtusi2ss 0x3953 -#define MN_vfmsub213ss 0x395e -#define MN_vfnmsub213ss 0x396a -#define MN_vfmadd213ss 0x3977 -#define MN_vfnmadd213ss 0x3983 -#define MN_vrcp14ss 0x3990 -#define MN_vrsqrt14ss 0x3999 -#define MN_vrcp28ss 0x39a4 -#define MN_vrsqrt28ss 0x39ad +#define MN_vcvtsi2ss 0x394b +#define MN_vcvtusi2ss 0x3955 +#define MN_vfmsub213ss 0x3960 +#define MN_vfnmsub213ss 0x396c +#define MN_vfmadd213ss 0x3979 +#define MN_vfnmadd213ss 0x3985 +#define MN_vrcp14ss 0x3992 +#define MN_vrsqrt14ss 0x399b +#define MN_vrcp28ss 0x39a6 +#define MN_vrsqrt28ss 0x39af #define MN_subss (MN_vfmsubss + 3) -#define MN_vfmsubss 0x39b8 -#define MN_vfnmsubss 0x39c1 -#define MN_vsubss 0x39cb +#define MN_vfmsubss 0x39ba +#define MN_vfnmsubss 0x39c3 +#define MN_vsubss 0x39cd #define MN_addss (MN_v4fmaddss + 4) -#define MN_v4fmaddss 0x39d2 -#define MN_vfmaddss 0x39dc -#define MN_v4fnmaddss 0x39e5 -#define MN_vfnmaddss 0x39f0 -#define MN_vaddss 0x39fa +#define MN_v4fmaddss 0x39d4 +#define MN_vfmaddss 0x39de +#define MN_v4fnmaddss 0x39e7 +#define MN_vfnmaddss 0x39f2 +#define MN_vaddss 0x39fc #define MN_roundss (MN_vroundss + 1) -#define MN_vroundss 0x3a01 +#define MN_vroundss 0x3a03 #define MN_cmpunordss (MN_vcmpunordss + 1) -#define MN_vcmpunordss 0x3a0a +#define MN_vcmpunordss 0x3a0c #define MN_cmpordss (MN_vcmpordss + 1) -#define MN_vcmpordss 0x3a16 -#define MN_vreducess 0x3a20 -#define MN_vrangess 0x3a2a -#define MN_vcmpngess 0x3a33 -#define MN_vcmpgess 0x3a3d -#define MN_vrndscaless 0x3a46 +#define MN_vcmpordss 0x3a18 +#define MN_vreducess 0x3a22 +#define MN_vrangess 0x3a2c +#define MN_vcmpngess 0x3a35 +#define MN_vcmpgess 0x3a3f +#define MN_vrndscaless 0x3a48 #define MN_cmpnless (MN_vcmpnless + 1) -#define MN_vcmpnless 0x3a52 +#define MN_vcmpnless 0x3a54 #define MN_cmpless (MN_vcmpless + 1) -#define MN_vcmpless 0x3a5c -#define MN_vcmpfalsess 0x3a65 -#define MN_vcmptruess 0x3a71 -#define MN_vscalefss 0x3a7c +#define MN_vcmpless 0x3a5e +#define MN_vcmpfalsess 0x3a67 +#define MN_vcmptruess 0x3a73 +#define MN_vscalefss 0x3a7e #define MN_comiss (MN_ucomiss + 1) #define MN_ucomiss (MN_vucomiss + 1) -#define MN_vucomiss 0x3a86 -#define MN_vcomiss 0x3a8f +#define MN_vucomiss 0x3a88 +#define MN_vcomiss 0x3a91 #define MN_lss (MN_mulss + 2) #define MN_mulss (MN_vmulss + 1) -#define MN_vmulss 0x3a97 -#define MN_vfixupimmss 0x3a9e +#define MN_vmulss 0x3a99 +#define MN_vfixupimmss 0x3aa0 #define MN_minss (MN_vminss + 1) -#define MN_vminss 0x3aaa +#define MN_vminss 0x3aac #define MN_rcpss (MN_vrcpss + 1) -#define MN_vrcpss 0x3ab1 +#define MN_vrcpss 0x3ab3 #define MN_cmpss (MN_vcmpss + 1) -#define MN_vcmpss 0x3ab8 -#define MN_vgetexpss 0x3abf -#define MN_vcmpunord_qss 0x3ac9 -#define MN_vcmpord_qss 0x3ad7 +#define MN_vcmpss 0x3aba +#define MN_vgetexpss 0x3ac1 +#define MN_vcmpunord_qss 0x3acb +#define MN_vcmpord_qss 0x3ad9 #define MN_cmpneqss (MN_vcmpneqss + 1) -#define MN_vcmpneqss 0x3ae3 +#define MN_vcmpneqss 0x3ae5 #define MN_cmpeqss (MN_vcmpeqss + 1) -#define MN_vcmpeqss 0x3aed -#define MN_vcmpge_oqss 0x3af6 -#define MN_vcmple_oqss 0x3b02 -#define MN_vcmpfalse_oqss 0x3b0e -#define MN_vcmpneq_oqss 0x3b1d -#define MN_vcmpeq_oqss 0x3b2a -#define MN_vcmpgt_oqss 0x3b36 -#define MN_vcmplt_oqss 0x3b42 -#define MN_vcmpnge_uqss 0x3b4e -#define MN_vcmpnle_uqss 0x3b5b -#define MN_vcmptrue_uqss 0x3b68 -#define MN_vcmpneq_uqss 0x3b76 -#define MN_vcmpeq_uqss 0x3b83 -#define MN_vcmpngt_uqss 0x3b8f -#define MN_vcmpnlt_uqss 0x3b9c -#define MN_vcmpunord_sss 0x3ba9 -#define MN_vcmpord_sss 0x3bb7 -#define MN_vcmpge_osss 0x3bc3 -#define MN_vcmple_osss 0x3bcf -#define MN_vcmpfalse_osss 0x3bdb -#define MN_vcmpneq_osss 0x3bea -#define MN_vcmpeq_osss 0x3bf7 -#define MN_vcmpgt_osss 0x3c03 -#define MN_vcmplt_osss 0x3c0f -#define MN_vfpclassss 0x3c1b -#define MN_vcmpnge_usss 0x3c26 -#define MN_vcmpnle_usss 0x3c33 -#define MN_vcmptrue_usss 0x3c40 -#define MN_vcmpneq_usss 0x3c4e -#define MN_vcmpeq_usss 0x3c5b -#define MN_vcmpngt_usss 0x3c67 -#define MN_vcmpnlt_usss 0x3c74 -#define MN_vcmpngtss 0x3c81 -#define MN_vcmpgtss 0x3c8b +#define MN_vcmpeqss 0x3aef +#define MN_vcmpge_oqss 0x3af8 +#define MN_vcmple_oqss 0x3b04 +#define MN_vcmpfalse_oqss 0x3b10 +#define MN_vcmpneq_oqss 0x3b1f +#define MN_vcmpeq_oqss 0x3b2c +#define MN_vcmpgt_oqss 0x3b38 +#define MN_vcmplt_oqss 0x3b44 +#define MN_vcmpnge_uqss 0x3b50 +#define MN_vcmpnle_uqss 0x3b5d +#define MN_vcmptrue_uqss 0x3b6a +#define MN_vcmpneq_uqss 0x3b78 +#define MN_vcmpeq_uqss 0x3b85 +#define MN_vcmpngt_uqss 0x3b91 +#define MN_vcmpnlt_uqss 0x3b9e +#define MN_vcmpunord_sss 0x3bab +#define MN_vcmpord_sss 0x3bb9 +#define MN_vcmpge_osss 0x3bc5 +#define MN_vcmple_osss 0x3bd1 +#define MN_vcmpfalse_osss 0x3bdd +#define MN_vcmpneq_osss 0x3bec +#define MN_vcmpeq_osss 0x3bf9 +#define MN_vcmpgt_osss 0x3c05 +#define MN_vcmplt_osss 0x3c11 +#define MN_vfpclassss 0x3c1d +#define MN_vcmpnge_usss 0x3c28 +#define MN_vcmpnle_usss 0x3c35 +#define MN_vcmptrue_usss 0x3c42 +#define MN_vcmpneq_usss 0x3c50 +#define MN_vcmpeq_usss 0x3c5d +#define MN_vcmpngt_usss 0x3c69 +#define MN_vcmpnlt_usss 0x3c76 +#define MN_vcmpngtss 0x3c83 +#define MN_vcmpgtss 0x3c8d #define MN_cmpnltss (MN_vcmpnltss + 1) -#define MN_vcmpnltss 0x3c94 +#define MN_vcmpnltss 0x3c96 #define MN_cmpltss (MN_vcmpltss + 1) -#define MN_vcmpltss 0x3c9e -#define MN_vgetmantss 0x3ca7 -#define MN_movntss 0x3cb2 +#define MN_vcmpltss 0x3ca0 +#define MN_vgetmantss 0x3ca9 +#define MN_movntss 0x3cb4 #define MN_sqrtss (MN_rsqrtss + 1) #define MN_rsqrtss (MN_vrsqrtss + 1) -#define MN_vrsqrtss 0x3cba -#define MN_vsqrtss 0x3cc3 -#define MN_vbroadcastss 0x3ccb +#define MN_vrsqrtss 0x3cbc +#define MN_vsqrtss 0x3cc5 +#define MN_vbroadcastss 0x3ccd #define MN_divss (MN_vdivss + 1) -#define MN_vdivss 0x3cd8 +#define MN_vdivss 0x3cda #define MN_movss (MN_vmovss + 1) -#define MN_vmovss 0x3cdf +#define MN_vmovss 0x3ce1 #define MN_maxss (MN_vmaxss + 1) -#define MN_vmaxss 0x3ce6 -#define MN_vfrczss 0x3ced -#define MN_bts 0x3cf5 -#define MN_erets 0x3cf9 -#define MN_sets 0x3cff -#define MN_clts 0x3d04 -#define MN_outs 0x3d09 +#define MN_vmaxss 0x3ce8 +#define MN_vfrczss 0x3cef +#define MN_bts 0x3cf7 +#define MN_erets 0x3cfb +#define MN_sets 0x3d01 +#define MN_clts 0x3d06 +#define MN_outs 0x3d0b #define MN_movs (MN_cmovs + 1) -#define MN_cmovs 0x3d0e -#define MN_fldl2t 0x3d14 -#define MN_xlat 0x3d1b -#define MN_bt 0x3d20 -#define MN_fxtract 0x3d23 -#define MN_lgdt 0x3d2b -#define MN_sgdt 0x3d30 -#define MN_lidt 0x3d35 -#define MN_sidt 0x3d3a -#define MN_fldt 0x3d3f -#define MN_lldt 0x3d44 -#define MN_sldt 0x3d49 +#define MN_cmovs 0x3d10 +#define MN_fldl2t 0x3d16 +#define MN_xlat 0x3d1d +#define MN_bt 0x3d22 +#define MN_fxtract 0x3d25 +#define MN_lgdt 0x3d2d +#define MN_sgdt 0x3d32 +#define MN_lidt 0x3d37 +#define MN_sidt 0x3d3c +#define MN_fldt 0x3d41 +#define MN_lldt 0x3d46 +#define MN_sldt 0x3d4b #define MN_ret (MN_iret + 1) #define MN_iret (MN_uiret + 1) -#define MN_uiret 0x3d4e -#define MN_lret 0x3d54 -#define MN_seamret 0x3d59 -#define MN_sysret 0x3d61 -#define MN_hreset 0x3d68 -#define MN_pfcmpgt 0x3d6f -#define MN_ht 0x3d77 +#define MN_uiret 0x3d50 +#define MN_lret 0x3d56 +#define MN_seamret 0x3d5b +#define MN_sysret 0x3d63 +#define MN_hreset 0x3d6a +#define MN_pfcmpgt 0x3d71 +#define MN_ht 0x3d79 #define MN_wait (MN_fwait + 1) -#define MN_fwait 0x3d7a +#define MN_fwait 0x3d7c #define MN_mwait (MN_umwait + 1) -#define MN_umwait 0x3d80 -#define MN_mcommit 0x3d87 -#define MN_finit 0x3d8f -#define MN_skinit 0x3d95 -#define MN_fninit 0x3d9c -#define MN_vmgexit 0x3da3 -#define MN_sysexit 0x3dab -#define MN_hlt 0x3db3 -#define MN_popcnt 0x3db7 -#define MN_lzcnt 0x3dbe -#define MN_tzcnt 0x3dc4 -#define MN_hnt 0x3dca +#define MN_umwait 0x3d82 +#define MN_mcommit 0x3d89 +#define MN_finit 0x3d91 +#define MN_skinit 0x3d97 +#define MN_fninit 0x3d9e +#define MN_vmgexit 0x3da5 +#define MN_sysexit 0x3dad +#define MN_hlt 0x3db5 +#define MN_popcnt 0x3db9 +#define MN_lzcnt 0x3dc0 +#define MN_tzcnt 0x3dc6 +#define MN_hnt 0x3dcc #define MN_int (MN_frndint + 4) -#define MN_frndint 0x3dce -#define MN_not 0x3dd6 -#define MN_invept 0x3dda -#define MN_xsaveopt 0x3de1 -#define MN_clflushopt 0x3dea -#define MN_fstpt 0x3df5 -#define MN_xabort 0x3dfb -#define MN_fsqrt 0x3e02 -#define MN_pfrsqrt 0x3e08 +#define MN_frndint 0x3dd0 +#define MN_not 0x3dd8 +#define MN_invept 0x3ddc +#define MN_xsaveopt 0x3de3 +#define MN_clflushopt 0x3dec +#define MN_fstpt 0x3df7 +#define MN_xabort 0x3dfd +#define MN_fsqrt 0x3e04 +#define MN_pfrsqrt 0x3e0a #define MN_aesdeclast (MN_vaesdeclast + 1) -#define MN_vaesdeclast 0x3e10 +#define MN_vaesdeclast 0x3e12 #define MN_aesenclast (MN_vaesenclast + 1) -#define MN_vaesenclast 0x3e1c +#define MN_vaesenclast 0x3e1e #define MN_test (MN_ptest + 1) #define MN_ptest (MN_vptest + 1) -#define MN_vptest 0x3e28 -#define MN_xtest 0x3e2f -#define MN_fst 0x3e35 -#define MN_fist 0x3e39 -#define MN_rdmsrlist 0x3e3e -#define MN_wrmsrlist 0x3e48 +#define MN_vptest 0x3e2a +#define MN_xtest 0x3e31 +#define MN_fst 0x3e37 +#define MN_fist 0x3e3b +#define MN_rdmsrlist 0x3e40 +#define MN_wrmsrlist 0x3e4a #define MN_aeskeygenassist (MN_vaeskeygenassist + 1) -#define MN_vaeskeygenassist 0x3e52 -#define MN_vmptrst 0x3e63 -#define MN_ftst 0x3e6b -#define MN_rmpadjust 0x3e70 -#define MN_out 0x3e7a -#define MN_pext 0x3e7e -#define MN_bndcu 0x3e83 -#define MN_enclu 0x3e89 -#define MN_fcmovnu 0x3e8f +#define MN_vaeskeygenassist 0x3e54 +#define MN_vmptrst 0x3e65 +#define MN_ftst 0x3e6d +#define MN_rmpadjust 0x3e72 +#define MN_out 0x3e7c +#define MN_pext 0x3e80 +#define MN_bndcu 0x3e85 +#define MN_enclu 0x3e8b +#define MN_fcmovnu 0x3e91 #define MN_lddqu (MN_vlddqu + 1) -#define MN_vlddqu 0x3e97 +#define MN_vlddqu 0x3e99 #define MN_movdqu (MN_maskmovdqu + 4) #define MN_maskmovdqu (MN_vmaskmovdqu + 1) -#define MN_vmaskmovdqu 0x3e9e -#define MN_vmovdqu 0x3eaa -#define MN_rdpkru 0x3eb2 -#define MN_wrpkru 0x3eb9 -#define MN_rdpru 0x3ec0 -#define MN_eretu 0x3ec6 -#define MN_fcmovu 0x3ecc -#define MN_xgetbv 0x3ed3 -#define MN_xsetbv 0x3eda +#define MN_vmaskmovdqu 0x3ea0 +#define MN_vmovdqu 0x3eac +#define MN_rdpkru 0x3eb4 +#define MN_wrpkru 0x3ebb +#define MN_rdpru 0x3ec2 +#define MN_eretu 0x3ec8 +#define MN_fcmovu 0x3ece +#define MN_xgetbv 0x3ed5 +#define MN_xsetbv 0x3edc #define MN_div (MN_fdiv + 1) -#define MN_fdiv 0x3ee1 +#define MN_fdiv 0x3ee3 #define MN_idiv (MN_fidiv + 1) -#define MN_fidiv 0x3ee6 -#define MN_enclv 0x3eec -#define MN_fldenv 0x3ef2 -#define MN_fstenv 0x3ef9 -#define MN_fnstenv 0x3f00 +#define MN_fidiv 0x3ee8 +#define MN_enclv 0x3eee +#define MN_fldenv 0x3ef4 +#define MN_fstenv 0x3efb +#define MN_fnstenv 0x3f02 #define MN_mov (MN_vpcmov + 3) -#define MN_vpcmov 0x3f08 -#define MN_bndmov 0x3f0f -#define MN_smov 0x3f16 -#define MN_rex_w 0x3f1b -#define MN_vcvttph2w 0x3f21 -#define MN_vcvtph2w 0x3f2b -#define MN_vpermi2w 0x3f34 -#define MN_vpmovm2w 0x3f3d -#define MN_vpermt2w 0x3f46 -#define MN_vpshaw 0x3f4f +#define MN_vpcmov 0x3f0a +#define MN_bndmov 0x3f11 +#define MN_smov 0x3f18 +#define MN_rex_w 0x3f1d +#define MN_vcvttph2w 0x3f23 +#define MN_vcvtph2w 0x3f2d +#define MN_vpermi2w 0x3f36 +#define MN_vpmovm2w 0x3f3f +#define MN_vpermt2w 0x3f48 +#define MN_vpshaw 0x3f51 #define MN_psraw (MN_vpsraw + 1) -#define MN_vpsraw 0x3f56 -#define MN_vphsubbw 0x3f5d -#define MN_cbw 0x3f66 +#define MN_vpsraw 0x3f58 +#define MN_vphsubbw 0x3f5f +#define MN_cbw 0x3f68 #define MN_psadbw (MN_vdbpsadbw + 3) -#define MN_vdbpsadbw 0x3f6a +#define MN_vdbpsadbw 0x3f6c #define MN_mpsadbw (MN_vmpsadbw + 1) -#define MN_vmpsadbw 0x3f74 -#define MN_vpsadbw 0x3f7d -#define MN_vphaddbw 0x3f85 +#define MN_vmpsadbw 0x3f76 +#define MN_vpsadbw 0x3f7f +#define MN_vphaddbw 0x3f87 #define MN_punpckhbw (MN_vpunpckhbw + 1) -#define MN_vpunpckhbw 0x3f8e -#define MN_kunpckbw 0x3f99 +#define MN_vpunpckhbw 0x3f90 +#define MN_kunpckbw 0x3f9b #define MN_punpcklbw (MN_vpunpcklbw + 1) -#define MN_vpunpcklbw 0x3fa2 -#define MN_vphaddubw 0x3fad +#define MN_vpunpcklbw 0x3fa4 +#define MN_vphaddubw 0x3faf #define MN_phsubw (MN_vphsubw + 1) -#define MN_vphsubw 0x3fb7 +#define MN_vphsubw 0x3fb9 #define MN_psubw (MN_vpsubw + 1) -#define MN_vpsubw 0x3fbf +#define MN_vpsubw 0x3fc1 #define MN_pmovsxbw (MN_vpmovsxbw + 1) -#define MN_vpmovsxbw 0x3fc6 +#define MN_vpmovsxbw 0x3fc8 #define MN_pmovzxbw (MN_vpmovzxbw + 1) -#define MN_vpmovzxbw 0x3fd0 -#define MN_fldcw 0x3fda -#define MN_fstcw 0x3fe0 -#define MN_fnstcw 0x3fe6 +#define MN_vpmovzxbw 0x3fd2 +#define MN_fldcw 0x3fdc +#define MN_fstcw 0x3fe2 +#define MN_fnstcw 0x3fe8 #define MN_phaddw (MN_vphaddw + 1) -#define MN_vphaddw 0x3fed -#define MN_kaddw 0x3ff5 +#define MN_vphaddw 0x3fef +#define MN_kaddw 0x3ff7 #define MN_paddw (MN_vpaddw + 1) -#define MN_vpaddw 0x3ffb -#define MN_vpshldw 0x4002 -#define MN_kandw 0x400a -#define MN_vpexpandw 0x4010 +#define MN_vpaddw 0x3ffd +#define MN_vpshldw 0x4004 +#define MN_kandw 0x400c +#define MN_vpexpandw 0x4012 #define MN_pblendw (MN_vpblendw + 1) -#define MN_vpblendw 0x401a -#define MN_vpshrdw 0x4023 +#define MN_vpblendw 0x401c +#define MN_vpshrdw 0x4025 #define MN_packssdw (MN_vpackssdw + 1) -#define MN_vpackssdw 0x402b +#define MN_vpackssdw 0x402d #define MN_packusdw (MN_vpackusdw + 1) -#define MN_vpackusdw 0x4035 -#define MN_vpmovusdw 0x403f -#define MN_vpmovsdw 0x4049 -#define MN_vpmovdw 0x4052 -#define MN_vpcomgew 0x405a -#define MN_vpcomlew 0x4063 -#define MN_vpcmpnlew 0x406c -#define MN_vpcmplew 0x4076 -#define MN_vpcomfalsew 0x407f -#define MN_vpcomtruew 0x408b -#define MN_pi2fw 0x4096 -#define MN_pshufw 0x409c +#define MN_vpackusdw 0x4037 +#define MN_vpmovusdw 0x4041 +#define MN_vpmovsdw 0x404b +#define MN_vpmovdw 0x4054 +#define MN_vpcomgew 0x405c +#define MN_vpcomlew 0x4065 +#define MN_vpcmpnlew 0x406e +#define MN_vpcmplew 0x4078 +#define MN_vpcomfalsew 0x4081 +#define MN_vpcomtruew 0x408d +#define MN_pi2fw 0x4098 +#define MN_pshufw 0x409e #define MN_pavgw (MN_vpavgw + 1) -#define MN_vpavgw 0x40a3 -#define MN_prefetchw 0x40aa +#define MN_vpavgw 0x40a5 +#define MN_prefetchw 0x40ac #define MN_pshufhw (MN_vpshufhw + 1) -#define MN_vpshufhw 0x40b4 +#define MN_vpshufhw 0x40b6 #define MN_pmulhw (MN_vpmulhw + 1) -#define MN_vpmulhw 0x40bd -#define MN_pf2iw 0x40c5 +#define MN_vpmulhw 0x40bf +#define MN_pf2iw 0x40c7 #define MN_pshuflw (MN_vpshuflw + 1) -#define MN_vpshuflw 0x40cb -#define MN_vpshlw 0x40d4 +#define MN_vpshuflw 0x40cd +#define MN_vpshlw 0x40d6 #define MN_psllw (MN_vpsllw + 1) -#define MN_vpsllw 0x40db +#define MN_vpsllw 0x40dd #define MN_pmullw (MN_vpmullw + 1) -#define MN_vpmullw 0x40e2 +#define MN_vpmullw 0x40e4 #define MN_psrlw (MN_vpsrlw + 1) -#define MN_vpsrlw 0x40ea -#define MN_kshiftlw 0x40f1 -#define MN_vpblendmw 0x40fa -#define MN_vptestnmw 0x4104 -#define MN_vpcomw 0x410e -#define MN_vpermw 0x4115 -#define MN_vptestmw 0x411c -#define MN_kandnw 0x4125 +#define MN_vpsrlw 0x40ec +#define MN_kshiftlw 0x40f3 +#define MN_vpblendmw 0x40fc +#define MN_vptestnmw 0x4106 +#define MN_vpcomw 0x4110 +#define MN_vpermw 0x4117 +#define MN_vptestmw 0x411e +#define MN_kandnw 0x4127 #define MN_psignw (MN_vpsignw + 1) -#define MN_vpsignw 0x412c -#define MN_vpcmpw 0x4134 -#define MN_vpcomeqw 0x413b -#define MN_vpcomneqw 0x4144 -#define MN_vpcmpneqw 0x414e +#define MN_vpsignw 0x412e +#define MN_vpcmpw 0x4136 +#define MN_vpcomeqw 0x413d +#define MN_vpcomneqw 0x4146 +#define MN_vpcmpneqw 0x4150 #define MN_pcmpeqw (MN_vpcmpeqw + 1) -#define MN_vpcmpeqw 0x4158 -#define MN_vpmovusqw 0x4161 -#define MN_vpmovsqw 0x416b -#define MN_vpmovqw 0x4174 -#define MN_verw 0x417c -#define MN_pmulhrw 0x4181 -#define MN_korw 0x4189 -#define MN_kxnorw 0x418e -#define MN_kxorw 0x4195 +#define MN_vpcmpeqw 0x415a +#define MN_vpmovusqw 0x4163 +#define MN_vpmovsqw 0x416d +#define MN_vpmovqw 0x4176 +#define MN_verw 0x417e +#define MN_pmulhrw 0x4183 +#define MN_korw 0x418b +#define MN_kxnorw 0x4190 +#define MN_kxorw 0x4197 #define MN_pinsrw (MN_vpinsrw + 1) -#define MN_vpinsrw 0x419b -#define MN_kshiftrw 0x41a3 +#define MN_vpinsrw 0x419d +#define MN_kshiftrw 0x41a5 #define MN_pextrw (MN_vpextrw + 1) -#define MN_vpextrw 0x41ac +#define MN_vpextrw 0x41ae #define MN_pabsw (MN_vpabsw + 1) -#define MN_vpabsw 0x41b4 +#define MN_vpabsw 0x41b6 #define MN_pmaddubsw (MN_vpmaddubsw + 1) -#define MN_vpmaddubsw 0x41bb +#define MN_vpmaddubsw 0x41bd #define MN_phsubsw (MN_vphsubsw + 1) -#define MN_vphsubsw 0x41c6 +#define MN_vphsubsw 0x41c8 #define MN_psubsw (MN_vpsubsw + 1) -#define MN_vpsubsw 0x41cf +#define MN_vpsubsw 0x41d1 #define MN_phaddsw (MN_vphaddsw + 1) -#define MN_vphaddsw 0x41d7 +#define MN_vphaddsw 0x41d9 #define MN_paddsw (MN_vpaddsw + 1) -#define MN_vpaddsw 0x41e0 -#define MN_lmsw 0x41e8 -#define MN_smsw 0x41ed +#define MN_vpaddsw 0x41e2 +#define MN_lmsw 0x41ea +#define MN_smsw 0x41ef #define MN_pminsw (MN_vpminsw + 1) -#define MN_vpminsw 0x41f2 +#define MN_vpminsw 0x41f4 #define MN_pmulhrsw (MN_vpmulhrsw + 1) -#define MN_vpmulhrsw 0x41fa -#define MN_vpcompressw 0x4204 -#define MN_fstsw 0x4210 -#define MN_fnstsw 0x4216 +#define MN_vpmulhrsw 0x41fc +#define MN_vpcompressw 0x4206 +#define MN_fstsw 0x4212 +#define MN_fnstsw 0x4218 #define MN_psubusw (MN_vpsubusw + 1) -#define MN_vpsubusw 0x421d +#define MN_vpsubusw 0x421f #define MN_paddusw (MN_vpaddusw + 1) -#define MN_vpaddusw 0x4226 -#define MN_movsw 0x422f +#define MN_vpaddusw 0x4228 +#define MN_movsw 0x4231 #define MN_pmaxsw (MN_vpmaxsw + 1) -#define MN_vpmaxsw 0x4235 -#define MN_cbtw 0x423d -#define MN_vpcomgtw 0x4242 +#define MN_vpmaxsw 0x4237 +#define MN_cbtw 0x423f +#define MN_vpcomgtw 0x4244 #define MN_pcmpgtw (MN_vpcmpgtw + 1) -#define MN_vpcmpgtw 0x424b -#define MN_vpcomltw 0x4254 -#define MN_vpcmpnltw 0x425d -#define MN_vpcmpltw 0x4267 -#define MN_vpopcntw 0x4270 -#define MN_knotw 0x4279 -#define MN_vprotw 0x427f -#define MN_vpbroadcastw 0x4286 -#define MN_ktestw 0x4293 -#define MN_kortestw 0x429a -#define MN_vcvttph2uw 0x42a3 -#define MN_vcvtph2uw 0x42ae -#define MN_vpcomgeuw 0x42b8 -#define MN_vpcomleuw 0x42c2 -#define MN_vpcmpnleuw 0x42cc -#define MN_vpcmpleuw 0x42d7 -#define MN_vpcomfalseuw 0x42e1 -#define MN_vpcomtrueuw 0x42ee +#define MN_vpcmpgtw 0x424d +#define MN_vpcomltw 0x4256 +#define MN_vpcmpnltw 0x425f +#define MN_vpcmpltw 0x4269 +#define MN_vpopcntw 0x4272 +#define MN_knotw 0x427b +#define MN_vprotw 0x4281 +#define MN_vpbroadcastw 0x4288 +#define MN_ktestw 0x4295 +#define MN_kortestw 0x429c +#define MN_vcvttph2uw 0x42a5 +#define MN_vcvtph2uw 0x42b0 +#define MN_vpcomgeuw 0x42ba +#define MN_vpcomleuw 0x42c4 +#define MN_vpcmpnleuw 0x42ce +#define MN_vpcmpleuw 0x42d9 +#define MN_vpcomfalseuw 0x42e3 +#define MN_vpcomtrueuw 0x42f0 #define MN_pmulhuw (MN_vpmulhuw + 1) -#define MN_vpmulhuw 0x42fa -#define MN_vpcomuw 0x4303 +#define MN_vpmulhuw 0x42fc +#define MN_vpcomuw 0x4305 #define MN_pminuw (MN_vpminuw + 1) -#define MN_vpminuw 0x430b -#define MN_vpcmpuw 0x4313 -#define MN_vpcomequw 0x431b -#define MN_vpcomnequw 0x4325 -#define MN_vpcmpnequw 0x4330 -#define MN_vpcmpequw 0x433b +#define MN_vpminuw 0x430d +#define MN_vpcmpuw 0x4315 +#define MN_vpcomequw 0x431d +#define MN_vpcomnequw 0x4327 +#define MN_vpcmpnequw 0x4332 +#define MN_vpcmpequw 0x433d #define MN_phminposuw (MN_vphminposuw + 1) -#define MN_vphminposuw 0x4345 -#define MN_vpcomgtuw 0x4351 -#define MN_vpcomltuw 0x435b -#define MN_vpcmpnltuw 0x4365 -#define MN_vpcmpltuw 0x4370 +#define MN_vphminposuw 0x4347 +#define MN_vpcomgtuw 0x4353 +#define MN_vpcomltuw 0x435d +#define MN_vpcmpnltuw 0x4367 +#define MN_vpcmpltuw 0x4372 #define MN_pmaxuw (MN_vpmaxuw + 1) -#define MN_vpmaxuw 0x437a -#define MN_vpsravw 0x4382 -#define MN_vpshldvw 0x438a -#define MN_vpshrdvw 0x4393 -#define MN_vpsllvw 0x439c -#define MN_vpsrlvw 0x43a4 -#define MN_kmovw 0x43ac -#define MN_vmovw 0x43b2 -#define MN_vpmacsww 0x43b8 -#define MN_vpmacssww 0x43c1 -#define MN_movzw 0x43cb -#define MN_rex_x 0x43d1 -#define MN_fyl2x 0x43d7 -#define MN_rex64x 0x43dd -#define MN_vcvtneps2bf16x 0x43e4 -#define MN_pfmax 0x43f3 -#define MN_adcx 0x43f9 -#define MN_bndldx 0x43fe -#define MN_vfpclasspdx 0x4405 -#define MN_fclex 0x4411 -#define MN_fnclex 0x4417 -#define MN_rex 0x441e -#define MN_vcvtpd2phx 0x4422 -#define MN_vcvtdq2phx 0x442d -#define MN_vcvtudq2phx 0x4438 -#define MN_vcvtqq2phx 0x4444 -#define MN_vcvtuqq2phx 0x444f -#define MN_vcvtps2phx 0x445b -#define MN_vfpclassphx 0x4466 -#define MN_shlx 0x4472 -#define MN_mulx 0x4477 -#define MN_adox 0x447c -#define MN_vcvttpd2dqx 0x4481 -#define MN_vcvtpd2dqx 0x448d -#define MN_vcvttpd2udqx 0x4498 -#define MN_vcvtpd2udqx 0x44a5 -#define MN_rex_rx 0x44b1 -#define MN_sarx 0x44b8 -#define MN_shrx 0x44bd -#define MN_rorx 0x44c2 -#define MN_monitorx 0x44c7 -#define MN_rex_wrx 0x44d0 -#define MN_vcvtpd2psx 0x44d8 -#define MN_vcvtph2psx 0x44e3 -#define MN_vcvtqq2psx 0x44ee -#define MN_vcvtuqq2psx 0x44f9 -#define MN_vfpclasspsx 0x4505 -#define MN_movsx 0x4511 -#define MN_mwaitx 0x4517 -#define MN_bndstx 0x451e -#define MN_rex_wx 0x4525 -#define MN_rexx 0x452c -#define MN_vcvtps2phxx 0x4531 -#define MN_movzx 0x453d -#define MN_rex64y 0x4543 -#define MN_vcvtneps2bf16y 0x454a -#define MN_vfpclasspdy 0x4559 -#define MN_loadiwkey 0x4565 -#define MN_vcvtpd2phy 0x456f -#define MN_vcvtdq2phy 0x457a -#define MN_vcvtudq2phy 0x4585 -#define MN_vcvtqq2phy 0x4591 -#define MN_vcvtuqq2phy 0x459c -#define MN_vfpclassphy 0x45a8 -#define MN_vcvttpd2dqy 0x45b4 -#define MN_vcvtpd2dqy 0x45c0 -#define MN_vcvttpd2udqy 0x45cb -#define MN_vcvtpd2udqy 0x45d8 -#define MN_rmpquery 0x45e4 -#define MN_clrssbsy 0x45ed -#define MN_setssbsy 0x45f6 -#define MN_vcvtpd2psy 0x45ff -#define MN_vcvtqq2psy 0x460a -#define MN_vcvtuqq2psy 0x4615 -#define MN_vfpclasspsy 0x4621 -#define MN_rex64xy 0x462d -#define MN_rexy 0x4635 -#define MN_vcvtps2phxy 0x463a -#define MN_rexxy 0x4646 -#define MN_rex64z 0x464c -#define MN_fldz 0x4653 -#define MN_vfpclasspdz 0x4658 -#define MN_vcvtpd2phz 0x4664 -#define MN_vcvtqq2phz 0x466f -#define MN_vcvtuqq2phz 0x467a -#define MN_vfpclassphz 0x4686 -#define MN_jz 0x4692 -#define MN_jnz 0x4695 -#define MN_repnz 0x4699 -#define MN_loopnz 0x469f -#define MN_setnz 0x46a6 -#define MN_cmovnz 0x46ac -#define MN_repz 0x46b3 -#define MN_loopz 0x46b8 -#define MN_vfpclasspsz 0x46be -#define MN_setz 0x46ca -#define MN_cmovz 0x46cf -#define MN_rex64xz 0x46d5 -#define MN_jecxz 0x46dd -#define MN_jcxz 0x46e3 -#define MN_jrcxz 0x46e8 -#define MN_rexz 0x46ee -#define MN_rexxz 0x46f3 -#define MN_rex64yz 0x46f9 -#define MN_rex64xyz 0x4701 -#define MN_rexyz 0x470a -#define MN_rexxyz 0x4710 -#define MN__disp32_ 0x4717 -#define MN__vex2_ 0x4720 -#define MN__vex3_ 0x4727 -#define MN__disp16_ 0x472e -#define MN__disp8_ 0x4737 -#define MN__load_ 0x473f -#define MN__store_ 0x4746 -#define MN__nooptimize_ 0x474e -#define MN__rex_ 0x475b -#define MN__evex_ 0x4761 -#define MN__vex_ 0x4768 -#define MN__insn 0x476e +#define MN_vpmaxuw 0x437c +#define MN_vpsravw 0x4384 +#define MN_vpshldvw 0x438c +#define MN_vpshrdvw 0x4395 +#define MN_vpsllvw 0x439e +#define MN_vpsrlvw 0x43a6 +#define MN_kmovw 0x43ae +#define MN_vmovw 0x43b4 +#define MN_vpmacsww 0x43ba +#define MN_vpmacssww 0x43c3 +#define MN_movzw 0x43cd +#define MN_rex_x 0x43d3 +#define MN_fyl2x 0x43d9 +#define MN_rex64x 0x43df +#define MN_vcvtneps2bf16x 0x43e6 +#define MN_pfmax 0x43f5 +#define MN_adcx 0x43fb +#define MN_bndldx 0x4400 +#define MN_vfpclasspdx 0x4407 +#define MN_fclex 0x4413 +#define MN_fnclex 0x4419 +#define MN_rex 0x4420 +#define MN_vcvtpd2phx 0x4424 +#define MN_vcvtdq2phx 0x442f +#define MN_vcvtudq2phx 0x443a +#define MN_vcvtqq2phx 0x4446 +#define MN_vcvtuqq2phx 0x4451 +#define MN_vcvtps2phx 0x445d +#define MN_vfpclassphx 0x4468 +#define MN_shlx 0x4474 +#define MN_mulx 0x4479 +#define MN_adox 0x447e +#define MN_vcvttpd2dqx 0x4483 +#define MN_vcvtpd2dqx 0x448f +#define MN_vcvttpd2udqx 0x449a +#define MN_vcvtpd2udqx 0x44a7 +#define MN_rex_rx 0x44b3 +#define MN_sarx 0x44ba +#define MN_shrx 0x44bf +#define MN_rorx 0x44c4 +#define MN_monitorx 0x44c9 +#define MN_rex_wrx 0x44d2 +#define MN_vcvtpd2psx 0x44da +#define MN_vcvtph2psx 0x44e5 +#define MN_vcvtqq2psx 0x44f0 +#define MN_vcvtuqq2psx 0x44fb +#define MN_vfpclasspsx 0x4507 +#define MN_movsx 0x4513 +#define MN_mwaitx 0x4519 +#define MN_bndstx 0x4520 +#define MN_rex_wx 0x4527 +#define MN_rexx 0x452e +#define MN_vcvtps2phxx 0x4533 +#define MN_movzx 0x453f +#define MN_rex64y 0x4545 +#define MN_vcvtneps2bf16y 0x454c +#define MN_vfpclasspdy 0x455b +#define MN_loadiwkey 0x4567 +#define MN_vcvtpd2phy 0x4571 +#define MN_vcvtdq2phy 0x457c +#define MN_vcvtudq2phy 0x4587 +#define MN_vcvtqq2phy 0x4593 +#define MN_vcvtuqq2phy 0x459e +#define MN_vfpclassphy 0x45aa +#define MN_vcvttpd2dqy 0x45b6 +#define MN_vcvtpd2dqy 0x45c2 +#define MN_vcvttpd2udqy 0x45cd +#define MN_vcvtpd2udqy 0x45da +#define MN_rmpquery 0x45e6 +#define MN_clrssbsy 0x45ef +#define MN_setssbsy 0x45f8 +#define MN_vcvtpd2psy 0x4601 +#define MN_vcvtqq2psy 0x460c +#define MN_vcvtuqq2psy 0x4617 +#define MN_vfpclasspsy 0x4623 +#define MN_rex64xy 0x462f +#define MN_rexy 0x4637 +#define MN_vcvtps2phxy 0x463c +#define MN_rexxy 0x4648 +#define MN_rex64z 0x464e +#define MN_fldz 0x4655 +#define MN_vfpclasspdz 0x465a +#define MN_vcvtpd2phz 0x4666 +#define MN_vcvtqq2phz 0x4671 +#define MN_vcvtuqq2phz 0x467c +#define MN_vfpclassphz 0x4688 +#define MN_jz 0x4694 +#define MN_jnz 0x4697 +#define MN_repnz 0x469b +#define MN_loopnz 0x46a1 +#define MN_setnz 0x46a8 +#define MN_cmovnz 0x46ae +#define MN_repz 0x46b5 +#define MN_loopz 0x46ba +#define MN_vfpclasspsz 0x46c0 +#define MN_setz 0x46cc +#define MN_cmovz 0x46d1 +#define MN_rex64xz 0x46d7 +#define MN_jecxz 0x46df +#define MN_jcxz 0x46e5 +#define MN_jrcxz 0x46ea +#define MN_rexz 0x46f0 +#define MN_rexxz 0x46f5 +#define MN_rex64yz 0x46fb +#define MN_rex64xyz 0x4703 +#define MN_rexyz 0x470c +#define MN_rexxyz 0x4712 +#define MN__disp32_ 0x4719 +#define MN__vex2_ 0x4722 +#define MN__vex3_ 0x4729 +#define MN__disp16_ 0x4730 +#define MN__disp8_ 0x4739 +#define MN__load_ 0x4741 +#define MN__store_ 0x4748 +#define MN__nooptimize_ 0x4750 +#define MN__rex_ 0x475d +#define MN__evex_ 0x4763 +#define MN__vex_ 0x476a +#define MN__insn 0x4770 diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 149ae0e950c..a6f0d149d8c 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -223,6 +223,8 @@ enum i386_cpu CpuFRED, /* lkgs instruction required */ CpuLKGS, + /* Intel USER_MSR Instruction support required. */ + CpuUSER_MSR, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -471,6 +473,7 @@ typedef union i386_cpu_flags unsigned int cpurao_int:1; unsigned int cpufred:1; unsigned int cpulkgs:1; + unsigned int cpuuser_msr:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; @@ -573,6 +576,11 @@ enum /* Instrucion requires that destination must be distinct from source registers. */ #define DISTINCT_DEST 9 + /* Swap source and dest. + 1. instructions only has 2 register operands and operand1 in MODRM.REG + and operand0 in MODRM.R/M. + 2. instructions only has 2 operands and operand1 is IMM. */ +#define SWAP_SOURCE_DEST 10 OperandConstraint, /* instruction ignores operand size prefix and in Intel mode ignores mnemonic size suffix check. */ @@ -966,6 +974,7 @@ typedef struct insn_template 3: 0F3A opcode prefix / space. 5: EVEXMAP5 opcode prefix / space. 6: EVEXMAP6 opcode prefix / space. + 7: VEXMAP7 opcode prefix / space. 8: XOP 08 opcode space. 9: XOP 09 opcode space. A: XOP 0A opcode space. @@ -976,6 +985,7 @@ typedef struct insn_template #define SPACE_0F3A 3 #define SPACE_EVEXMAP5 5 #define SPACE_EVEXMAP6 6 +#define SPACE_VEXMAP7 7 #define SPACE_XOP08 8 #define SPACE_XOP09 9 #define SPACE_XOP0A 0xA diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index e60184ba154..7f674586a7d 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -85,6 +85,7 @@ #define RegKludge OperandConstraint=REG_KLUDGE #define SwapSources OperandConstraint=SWAP_SOURCES #define Ugh OperandConstraint=UGH +#define SwapSourceDest OperandConstraint=SWAP_SOURCE_DEST #define IgnoreSize MnemonicSize=IGNORESIZE #define DefaultSize MnemonicSize=DEFAULTSIZE @@ -112,6 +113,8 @@ #define EVexMap5 OpcodeSpace=SPACE_EVEXMAP5 #define EVexMap6 OpcodeSpace=SPACE_EVEXMAP6 +#define VexMap7 OpcodeSpace=SPACE_VEXMAP7 + #define VexW0 VexW=VEXW0 #define VexW1 VexW=VEXW1 #define VexWIG VexW=VEXWIG @@ -3346,3 +3349,12 @@ erets, 0xf20f01ca, FRED|x64, NoSuf, {} eretu, 0xf30f01ca, FRED|x64, NoSuf, {} // FRED instructions end. + +// USER_MSR instructions. + +urdmsr, 0xf20f38f8, USER_MSR|x64, RegMem|NoSuf|NoRex64, { Reg64, Reg64 } +urdmsr, 0xf2f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|NoSuf|NoRex64, { Imm32, Reg64 } +uwrmsr, 0xf30f38f8, USER_MSR|x64, Modrm|NoSuf|NoRex64, { Reg64, Reg64 } +uwrmsr, 0xf3f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|SwapSourceDest|NoSuf|NoRex64, { Reg64, Imm32 } + +// USER_MSR instructions end. diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 4c677d1f485..1232153126d 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -12392,7 +12392,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 110, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }, + { { 111, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, @@ -12403,7 +12403,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 110, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 111, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, @@ -12414,7 +12414,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 110, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }, + { { 111, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, @@ -12425,7 +12425,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 110, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 111, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, @@ -12436,7 +12436,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 110, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }, + { { 111, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -12445,7 +12445,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 110, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 111, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -22954,7 +22954,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 3, 1, 0, 0, 5, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0 }, - { { 111, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, + { { 112, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -22976,7 +22976,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 3, 1, 0, 0, 5, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0 }, - { { 111, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, + { { 112, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -22998,7 +22998,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 3, 1, 0, 0, 5, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0 }, - { { 111, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, + { { 112, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -23020,7 +23020,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 3, 1, 0, 0, 5, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0 }, - { { 111, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, + { { 112, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -23064,7 +23064,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 3, 1, 0, 0, 5, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0 }, - { { 112, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, + { { 113, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { { 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, @@ -23088,7 +23088,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 3, 1, 0, 0, 5, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0 }, - { { 112, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, + { { 113, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -23110,7 +23110,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 3, 1, 0, 0, 5, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0 }, - { { 112, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, + { { 113, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -23132,7 +23132,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 3, 1, 0, 0, 5, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0 }, - { { 112, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, + { { 113, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -23154,7 +23154,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 3, 1, 0, 0, 5, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0 }, - { { 112, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, + { { 113, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -23165,7 +23165,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 110, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }, + { { 111, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, @@ -23178,7 +23178,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 1, 0, 0, 0, 1, 4, 0, 0, 7, 0, 0, 0, 0, 0, 0 }, - { { 110, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, + { { 111, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, @@ -23191,7 +23191,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 110, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }, + { { 111, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, @@ -23204,7 +23204,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 1, 0, 0, 0, 1, 4, 0, 0, 7, 0, 0, 0, 0, 0, 0 }, - { { 110, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, + { { 111, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, @@ -23217,7 +23217,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 5, 1, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0 }, - { { 110, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, + { { 111, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -26635,7 +26635,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 125, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 126, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_vmload, 0x01da, 0, SPACE_0F, None, @@ -32554,14 +32554,14 @@ static const insn_template i386_optab[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 130, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 131, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_invlpgb, 0x01fe, 3, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 130, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 131, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, @@ -32572,35 +32572,35 @@ static const insn_template i386_optab[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 131, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 132, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_clzero, 0x01fc, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_clzero, 0x01fc, 1, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_monitorx, 0x01fa, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_monitorx, 0x01fa, 3, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, @@ -32611,7 +32611,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 98, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 99, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, @@ -32622,14 +32622,14 @@ static const insn_template i386_optab[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_mwaitx, 0x01fb, 3, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, @@ -32640,91 +32640,91 @@ static const insn_template i386_optab[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 101, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_wrpkru, 0x01ef, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 101, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_rdpid, 0xc7, 1, SPACE_0F, 7, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 101, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, + { { 102, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_rdpid, 0xc7, 1, SPACE_0F, 7, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 101, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 102, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_ptwrite, 0xae, 1, SPACE_0F, 4, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 102, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, + { { 103, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0 } } } }, { MN_ptwrite, 0xae, 1, SPACE_0F, 4, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 102, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 103, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0 } } } }, { MN_incsspd, 0xae, 1, SPACE_0F, 5, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 104, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 105, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_incsspq, 0xae, 1, SPACE_0F, 5, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 104, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 105, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_rdsspd, 0x1e, 1, SPACE_0F, 1, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 104, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 105, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_rdsspq, 0x1e, 1, SPACE_0F, 1, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 104, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 105, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_saveprevssp, 0x01ea, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 104, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 105, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_rstorssp, 0x01, 1, SPACE_0F, 5, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 104, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 105, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0 } } } }, { MN_wrssd, 0xf6, 2, SPACE_0F38, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 104, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 105, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, @@ -32733,7 +32733,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 3, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 104, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 105, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, @@ -32742,7 +32742,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 104, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 105, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, @@ -32751,7 +32751,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 104, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 105, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, @@ -32760,77 +32760,77 @@ static const insn_template i386_optab[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 104, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 105, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_clrssbsy, 0xae, 1, SPACE_0F, 6, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 104, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 105, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0 } } } }, { MN_endbr64, 0x1efa, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 103, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 104, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_endbr32, 0x1efb, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 103, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 104, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_notrack, 0x3e, 0, SPACE_BASE, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 103, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 104, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_wbnoinvd, 0x09, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 113, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 114, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_pconfig, 0x01c5, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 114, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 115, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_pbndkb, 0x01c7, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 115, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 116, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_umonitor, 0xae, 1, SPACE_0F, 6, { 0, 0, 0, 1, 0, 0, 0, 0, 8, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 116, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 117, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_tpause, 0xae, 1, SPACE_0F, 6, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 116, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 117, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_tpause, 0xae, 3, SPACE_0F, 6, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 116, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 117, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, @@ -32841,14 +32841,14 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 116, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 117, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_umwait, 0xae, 3, SPACE_0F, 6, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 116, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 117, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, @@ -32859,14 +32859,14 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 118, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 119, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_movdiri, 0xf9, 2, SPACE_0F38, None, { 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 119, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 120, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, @@ -32875,7 +32875,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 8, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 120, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 121, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, @@ -33041,7 +33041,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 8, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 121, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 122, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, @@ -33050,7 +33050,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 8, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 121, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 122, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, @@ -33081,35 +33081,35 @@ static const insn_template i386_optab[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 124, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 125, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_psmash, 0x01ff, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 132, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 133, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_psmash, 0x01ff, 1, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 132, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 133, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_pvalidate, 0x01ff, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 132, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 133, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_pvalidate, 0x01ff, 3, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 132, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 133, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, @@ -33120,21 +33120,21 @@ static const insn_template i386_optab[] = { 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 132, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 133, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_rmpupdate, 0x01fe, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 132, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 133, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_rmpupdate, 0x01fe, 2, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 132, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 133, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, @@ -33143,21 +33143,21 @@ static const insn_template i386_optab[] = { 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 132, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 133, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_rmpadjust, 0x01fe, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 132, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 133, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_rmpadjust, 0x01fe, 3, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 132, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 133, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, @@ -33168,21 +33168,21 @@ static const insn_template i386_optab[] = { 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 132, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 133, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_rmpquery, 0x01fd, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 133, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 134, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_rmpquery, 0x01fd, 3, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 133, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 134, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, @@ -33193,49 +33193,49 @@ static const insn_template i386_optab[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 123, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 124, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_serialize, 0x01e8, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 122, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 123, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_xsusldtrk, 0x01e8, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 126, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_xresldtrk, 0x01e9, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 126, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_ldtilecfg, 0x49, 1, SPACE_0F38, 0, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 109, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 110, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } } } }, { MN_sttilecfg, 0x49, 1, SPACE_0F38, 0, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 109, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 110, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } } } }, { MN_tcmmimfp16ps, 0x6c, 3, SPACE_0F38, None, { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 108, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 109, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -33246,7 +33246,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 108, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 109, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -33257,7 +33257,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 106, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 107, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -33268,7 +33268,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 107, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 108, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -33279,7 +33279,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 105, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 106, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -33290,7 +33290,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 105, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 106, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -33301,7 +33301,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 105, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 106, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -33312,7 +33312,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 105, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 106, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -33323,7 +33323,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 3, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 109, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 110, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -33332,7 +33332,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 109, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 110, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -33341,7 +33341,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 2, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 109, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 110, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, @@ -33350,21 +33350,21 @@ static const insn_template i386_optab[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 109, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 110, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_tilezero, 0x49, 1, SPACE_0F38, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 109, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 110, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } } } }, { MN_loadiwkey, 0xdc, 2, SPACE_0F38, None, { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -33373,7 +33373,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, @@ -33382,7 +33382,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, @@ -33391,7 +33391,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -33400,7 +33400,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -33409,7 +33409,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -33418,7 +33418,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -33427,28 +33427,28 @@ static const insn_template i386_optab[] = { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } } } }, { MN_aesdecwide128kl, 0xd8, 1, SPACE_0F38, 1, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } } } }, { MN_aesencwide256kl, 0xd8, 1, SPACE_0F38, 2, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } } } }, { MN_aesdecwide256kl, 0xd8, 1, SPACE_0F38, 3, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } } } }, { MN_tdcall, 0x01cc, 0, SPACE_0F, None, @@ -33483,42 +33483,42 @@ static const insn_template i386_optab[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 117, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 118, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_clui, 0x01ee, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 117, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 118, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_stui, 0x01ef, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 117, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 118, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_testui, 0x01ed, 0, SPACE_0F, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 117, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 118, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_senduipi, 0xc7, 1, SPACE_0F, 6, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 117, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { 118, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_hreset, 0xf0c0, 1, SPACE_0F3A, None, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 130, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { MN_vfcmaddcph, 0x56, 3, SPACE_EVEXMAP6, None, @@ -35889,6 +35889,42 @@ static const insn_template i386_optab[] = { { 96, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, + { MN_urdmsr, 0xf8, 2, SPACE_0F38, None, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, + 0, 0, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0 }, + { { 98, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { MN_urdmsr, 0xf8, 2, SPACE_VEXMAP7, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, + 0, 0, 1, 1, 0, 1, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0 }, + { { 98, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { MN_uwrmsr, 0xf8, 2, SPACE_0F38, None, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, + 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0 }, + { { 98, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { MN_uwrmsr, 0xf8, 2, SPACE_VEXMAP7, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 10, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, + 0, 0, 1, 1, 0, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0 }, + { { 98, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, }; /* i386 opcode sets table. */ @@ -38235,6 +38271,8 @@ static const insn_template *const i386_op_sets[] = i386_optab + 3741, i386_optab + 3742, i386_optab + 3743, + i386_optab + 3745, + i386_optab + 3747, }; /* i386 mnemonics table. */ @@ -39591,8 +39629,8 @@ const char i386_mnemonics[] = "\0""vldmxcsr" "\0""vstmxcsr" "\0""blsr" - "\0""rdmsr" - "\0""wrmsr" + "\0""urdmsr" + "\0""uwrmsr" "\0""btr" "\0""xcrypt-ctr" "\0""xcryptctr" -- 2.31.1 ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH] Support Intel USER_MSR 2023-10-18 7:51 ` Hu, Lin1 @ 2023-10-19 8:36 ` Jan Beulich 2023-10-24 8:38 ` Hu, Lin1 0 siblings, 1 reply; 33+ messages in thread From: Jan Beulich @ 2023-10-19 8:36 UTC (permalink / raw) To: Hu, Lin1; +Cc: Lu, Hongjiu, binutils On 18.10.2023 09:51, Hu, Lin1 wrote: > Thanks for your review. I responded individually under each comment. > Attached is the modified version. Please can you send proper new versions, to allow easy commenting? > -----Original Message----- > From: Jan Beulich <jbeulich@suse.com> > Sent: Monday, October 16, 2023 8:11 PM > > On 10.10.2023 09:24, Hu, Lin1 wrote: >> @@ -8752,6 +8755,18 @@ build_modrm_byte (void) >> source = v; >> v = tmp; >> } >> + if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCE_DEST) >> + { >> + if (dest == (unsigned int) ~0) >> + source = source ^ 1; >> + else >> + { >> + unsigned int tmp = source; >> + >> + source = dest; >> + dest = tmp; >> + } >> + } > >> Why is this needed? There's only a single register operand in both affected insn forms (see comment below on the 2-register form). > Furthermore I think it would be easier if you "canonicalized" the early immediate to be the 1st operand, such that for all other purposes immediates remain first. > >> As a cosmetic nit: Please have a blank line ahead of the if() block (if it needs to stay). > > Indeed, I've only kept the part that deals with a single register. Do you mean to complain to the person who designed the insn. Unfortunately, that's impossible. I'm having trouble connecting your reply to what I wrote. No, I do not mean to complain; I can certainly see why the immediate is wanted as first (Intel) / last (AT&T) operand. I'm also not happy about the new change to build_modrm_byte(). When asking to "canonicalize" operands, I meant to gave this generalized, with SWAP_SOURCE_DEST dropped completely. (This will then also save me from complaining about a missing blank in SwapSourceDest's #define.) >> --- /dev/null >> +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s >> @@ -0,0 +1,15 @@ >> +# Check 64bit USER_MSR instructions >> + >> + .allow_index_reg >> + .text >> +_start: >> + urdmsr %r14, %r12 #USER_MSR >> + urdmsr $51515151, %r12 #USER_MSR >> + uwrmsr %r12, %r14 #USER_MSR >> + uwrmsr %r12, $51515151 #USER_MSR >> + >> +.intel_syntax noprefix > >> Nit: Please indent directives. > Have removed these comments. Neither does your reply fit here, nor did you what I've asked for here (in addition to the earlier, wider request of dropping meaningless comments). >> + urdmsr r12, r14 #USER_MSR >> + urdmsr r12, 51515151 #USER_MSR >> + uwrmsr r14, r12 #USER_MSR >> + uwrmsr 51515151, r12 #USER_MSR > >> I think varying registers slightly more (such that each two-register form has one low-8 and one high-8 operand, totaling to two forms each to prove that the REX.[RB] bits are also correctly dealt with) would be better. > > I have added some other tests here. Thanks. >> @@ -618,6 +620,8 @@ enum >> w_mode, >> /* double word operand */ >> d_mode, >> + /* double word operand 0 */ >> + d_0_mode, > >> Why is this needed? IOW why does d_mode not do? Or alternatively why isn't this a name indicating that it's an unsigned 32-bit value (as opposed to other 32-bit immediates in 64-bit mode)? > > I want to output imm32 first, but modrm byte is behind imm32, so I need to skip modrm for the moment. If I use { "uwrmsr", { Id, Eq }, 0} Id will read modrm byte. The mode is for a imm32 not an unsigned 32-bit value, so its name doesn't indicate that it's an unsigned integer. But the immediate is an unsigned 32-bit one. Signed ones would be sign- extended, which isn't the case here (or else the range 0x80000000 ... 0xffffffff wouldn't form valid MSR numbers). >> @@ -845,6 +849,7 @@ enum >> REG_VEX_0FAE, >> REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0, >> REG_VEX_0F38F3_L_0, >> + REG_VEX_MAP7_F8_L_0_W_0_M_1, >> >> REG_XOP_09_01_L_0, >> REG_XOP_09_02_L_0, >> @@ -893,8 +898,10 @@ enum >> MOD_0FC7_REG_6, >> MOD_0FC7_REG_7, >> MOD_0F38DC_PREFIX_1, >> + MOD_0F38F8, >> >> MOD_VEX_0F3849_X86_64_L_0_W_0, >> + MOD_VEX_MAP7_F8_L_0_W_0, >> }; > >> As before - no new mod_table[] entries please which don't have both branches populated. > > Have removed it. But you're using Eq there, i.e. permitting memory operands as well. What (I think) you want is Rq. For consistency this may then also want using in the new PREFIX_0F38F8_M_1_X86_64 entry. But of course you need to be careful about the collision with Nq. >> @@ -6791,6 +6839,297 @@ static const struct dis386 vex_table[][256] = { >> { Bad_Opcode }, >> { Bad_Opcode }, >> }, >> + /* VEX_MAP7 */ >> + { >> + /* 00 */ >> + { Bad_Opcode }, > >> I wonder whether adding a full new table (rather than some special case >> code) is really a god use of space. Of course if you know that more of it will be populated in the not too distant future ... > > I don't know, I'm just treating the new opcode_space MAP7 like other opcode_space. I'm afraid that "I don't know" is not an answer here. You can basically take two positions: Mine (waste of space) or you justify why the extra space used (and the extra runtime relocations added) aren't of concern. >> @@ -11248,6 +11609,20 @@ get32s (instr_info *ins, bfd_vma *res) >> return true; >> } >> >> +/* The function is used to get imm32, when imm32 is operand 0, and >> +ins only has 2 operands. */ static bool >> +get32_operand0 (instr_info *ins, bfd_vma *res) { >> + >> + if (!fetch_code (ins->info, ins->codep + 5)) >> + return false; >> + *res = *(ins->codep++ + 1) & (bfd_vma) 0xff; >> + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 8; >> + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 16; >> + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 24; >> + return true; >> +} > >> Instead of this (which assumes ModRM.mod == 3) I think you want to arrange for dealing with ModRM first. We already have OP_Skip_MODRM() for such needs, which you could use in a first "hidden" operand. > > I want to output imm32 first, but modrm byte is behind imm32, so I need to skip modrm for the moment. but I can't use OP_Skip_MODRM to deal with my problem, If I use it, I should add ins->codep-- at the end of get32_operand0. get32_operand0() should go away imo; at the very least I don't agree with special casing it being operand 0 (which, as you realize, is true only in the textual representation, and only in Intel syntax, but in particular not in the encoding). It may be necessary to special case it being an unsigned immediate, but get32() already fits that purpose. >> @@ -3346,3 +3349,12 @@ erets, 0xf20f01ca, FRED|x64, NoSuf, {} eretu, >> 0xf30f01ca, FRED|x64, NoSuf, {} >> >> // FRED instructions end. >> + >> +// USER_MSR instructions. >> + >> +urdmsr, 0xf20f38f8, USER_MSR|x64, >> +Modrm|IgnoreSize|SwapSourceDest|NoSuf, { Reg64, Reg64 } > >> Iirc RegMem is the attribute to use here, not any new one. > > Indeed. > >> +urdmsr, 0xf2f8/0, USER_MSR|x64, >> +Modrm|Vex128|VexMap7|VexW0|IgnoreSize|NoSuf, { Imm32S, Reg64 } > >> This and ... > >> +uwrmsr, 0xf30f38f8, USER_MSR|x64, Modrm|IgnoreSize|NoSuf, { Reg64, >> +Reg64 } uwrmsr, 0xf3f8/0, USER_MSR|x64, >> +Modrm|Vex128|VexMap7|VexW0|IgnoreSize|SwapSourceDest|NoSuf, { Reg64, >> +Imm32S } > >> ... this needs to use Imm32, not Imm32S. I understand this is going to cause complications elsewhere, but we can't afford getting this wrong. I see you've corrected this, but it doesn't look to me as if the match_template() change is actually going to do the job. You can't change i.types[] without looking at the actual values. I think this needs dealing with in optimize_imm() and/or finalize_imm() (irrespective of it's name more likely the former, but knock-on adjustments to the latter may then turn out to be needed). >> Also in all forms I think you don't mean IgnoreSize, but NoRex64. > > Have modified them. Hmm, I may have mislead you: NoRex64 is meaningless on VEX encodings. There only the IgnoreSize needed dropping. I'm sorry. Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH] Support Intel USER_MSR 2023-10-19 8:36 ` Jan Beulich @ 2023-10-24 8:38 ` Hu, Lin1 2023-10-24 8:55 ` Jan Beulich 0 siblings, 1 reply; 33+ messages in thread From: Hu, Lin1 @ 2023-10-24 8:38 UTC (permalink / raw) To: Beulich, Jan; +Cc: Lu, Hongjiu, binutils Thanks for your advice. I've tentatively made some changes based on your comments, but it's not completely finalized yet, I'd like to consult with you for your opinion, and I'll send out a new patch after it's basically confirmed. BRs, Lin > -----Original Message----- > From: Jan Beulich <jbeulich@suse.com> > Sent: Thursday, October 19, 2023 4:36 PM > To: Hu, Lin1 <lin1.hu@intel.com> > Cc: Lu, Hongjiu <hongjiu.lu@intel.com>; binutils@sourceware.org > Subject: Re: [PATCH] Support Intel USER_MSR > > On 18.10.2023 09:51, Hu, Lin1 wrote: > > Thanks for your review. I responded individually under each comment. > > Attached is the modified version. > > Please can you send proper new versions, to allow easy commenting? > > > -----Original Message----- > > From: Jan Beulich <jbeulich@suse.com> > > Sent: Monday, October 16, 2023 8:11 PM > > > > On 10.10.2023 09:24, Hu, Lin1 wrote: > >> @@ -8752,6 +8755,18 @@ build_modrm_byte (void) > >> source = v; > >> v = tmp; > >> } > >> + if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCE_DEST) > >> + { > >> + if (dest == (unsigned int) ~0) > >> + source = source ^ 1; > >> + else > >> + { > >> + unsigned int tmp = source; > >> + > >> + source = dest; > >> + dest = tmp; > >> + } > >> + } > > > >> Why is this needed? There's only a single register operand in both affected > insn forms (see comment below on the 2-register form). > > Furthermore I think it would be easier if you "canonicalized" the early > immediate to be the 1st operand, such that for all other purposes immediates > remain first. > > > >> As a cosmetic nit: Please have a blank line ahead of the if() block (if it needs > to stay). > > > > Indeed, I've only kept the part that deals with a single register. Do you mean to > complain to the person who designed the insn. Unfortunately, that's impossible. > > I'm having trouble connecting your reply to what I wrote. No, I do not mean to > complain; I can certainly see why the immediate is wanted as first (Intel) / last > (AT&T) operand. > > I'm also not happy about the new change to build_modrm_byte(). When asking > to "canonicalize" operands, I meant to gave this generalized, with > SWAP_SOURCE_DEST dropped completely. (This will then also save me from > complaining about a missing blank in SwapSourceDest's > #define.) > OK, I implemented a basic logic to handle the current situation, and included remarks. Like: /* If the last operand is an immediate number (ATT), we need to modify the source operand accordingly. If any instructions use other immediate (imm8, imm16, etc.) as the last operand, we must update the constraint. */ if (i.types[source].bitfield.imm32 == 1) source--; What's your opinion on this version? > >> --- /dev/null > >> +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s > >> @@ -0,0 +1,15 @@ > >> +# Check 64bit USER_MSR instructions > >> + > >> + .allow_index_reg > >> + .text > >> +_start: > >> + urdmsr %r14, %r12 #USER_MSR > >> + urdmsr $51515151, %r12 #USER_MSR > >> + uwrmsr %r12, %r14 #USER_MSR > >> + uwrmsr %r12, $51515151 #USER_MSR > >> + > >> +.intel_syntax noprefix > > > >> Nit: Please indent directives. > > Have removed these comments. > > Neither does your reply fit here, nor did you what I've asked for here (in addition > to the earlier, wider request of dropping meaningless comments). > Perhaps there's an issue with my interface, but it seems to me that the instruction now begins with a \t instead of two spaces for the updated patch. > >> + urdmsr r12, r14 #USER_MSR > >> + urdmsr r12, 51515151 #USER_MSR > >> + uwrmsr r14, r12 #USER_MSR > >> + uwrmsr 51515151, r12 #USER_MSR > > > >> I think varying registers slightly more (such that each two-register form has > one low-8 and one high-8 operand, totaling to two forms each to prove that the > REX.[RB] bits are also correctly dealt with) would be better. > > > > I have added some other tests here. > > Thanks. > > >> @@ -618,6 +620,8 @@ enum > >> w_mode, > >> /* double word operand */ > >> d_mode, > >> + /* double word operand 0 */ > >> + d_0_mode, > > > >> Why is this needed? IOW why does d_mode not do? Or alternatively why isn't > this a name indicating that it's an unsigned 32-bit value (as opposed to other 32- > bit immediates in 64-bit mode)? > > > > I want to output imm32 first, but modrm byte is behind imm32, so I need to > skip modrm for the moment. If I use { "uwrmsr", { Id, Eq }, 0} Id will read modrm > byte. The mode is for a imm32 not an unsigned 32-bit value, so its name doesn't > indicate that it's an unsigned integer. > > But the immediate is an unsigned 32-bit one. Signed ones would be sign- > extended, which isn't the case here (or else the range 0x80000000 ... > 0xffffffff wouldn't form valid MSR numbers). OK, you are right. > > >> @@ -845,6 +849,7 @@ enum > >> REG_VEX_0FAE, > >> REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0, > >> REG_VEX_0F38F3_L_0, > >> + REG_VEX_MAP7_F8_L_0_W_0_M_1, > >> > >> REG_XOP_09_01_L_0, > >> REG_XOP_09_02_L_0, > >> @@ -893,8 +898,10 @@ enum > >> MOD_0FC7_REG_6, > >> MOD_0FC7_REG_7, > >> MOD_0F38DC_PREFIX_1, > >> + MOD_0F38F8, > >> > >> MOD_VEX_0F3849_X86_64_L_0_W_0, > >> + MOD_VEX_MAP7_F8_L_0_W_0, > >> }; > > > >> As before - no new mod_table[] entries please which don't have both > branches populated. > > > > Have removed it. > > But you're using Eq there, i.e. permitting memory operands as well. > What (I think) you want is Rq. For consistency this may then also want using in > the new PREFIX_0F38F8_M_1_X86_64 entry. But of course you need to be > careful about the collision with Nq. I change the Nq's mode from q_mode to q_mm_mode and create Rq ( OP_R, q_mode ) for used. > > >> @@ -6791,6 +6839,297 @@ static const struct dis386 vex_table[][256] = { > >> { Bad_Opcode }, > >> { Bad_Opcode }, > >> }, > >> + /* VEX_MAP7 */ > >> + { > >> + /* 00 */ > >> + { Bad_Opcode }, > > > >> I wonder whether adding a full new table (rather than some special > >> case > >> code) is really a god use of space. Of course if you know that more of it will > be populated in the not too distant future ... > > > > I don't know, I'm just treating the new opcode_space MAP7 like other > opcode_space. > > I'm afraid that "I don't know" is not an answer here. You can basically take two > positions: Mine (waste of space) or you justify why the extra space used (and the > extra runtime relocations added) aren't of concern. > OK, I will skip MAP7 table. If vex_table_index = VEX_MAP7 and index == f8 dp will be VEX_LEN_MAP7_F8. So I don't need to add a full new table untill other MAP7 instructions raise. > >> @@ -11248,6 +11609,20 @@ get32s (instr_info *ins, bfd_vma *res) > >> return true; > >> } > >> > >> +/* The function is used to get imm32, when imm32 is operand 0, and > >> +ins only has 2 operands. */ static bool > >> +get32_operand0 (instr_info *ins, bfd_vma *res) { > >> + > >> + if (!fetch_code (ins->info, ins->codep + 5)) > >> + return false; > >> + *res = *(ins->codep++ + 1) & (bfd_vma) 0xff; > >> + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 8; > >> + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 16; > >> + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 24; > >> + return true; > >> +} > > > >> Instead of this (which assumes ModRM.mod == 3) I think you want to arrange > for dealing with ModRM first. We already have OP_Skip_MODRM() for such > needs, which you could use in a first "hidden" operand. > > > > I want to output imm32 first, but modrm byte is behind imm32, so I need to > skip modrm for the moment. but I can't use OP_Skip_MODRM to deal with my > problem, If I use it, I should add ins->codep-- at the end of get32_operand0. > > get32_operand0() should go away imo; at the very least I don't agree with > special casing it being operand 0 (which, as you realize, is true only in the textual > representation, and only in Intel syntax, but in particular not in the encoding). It > may be necessary to special case it being an unsigned immediate, but get32() > already fits that purpose. I've thought of it so far is I can use a Fixup function like static bool uwrmsr_Fixup (instr_info *ins, int bytemode, int sizeflag) { if (bytemode == d_mode) { if (OP_Skip_MODRM (ins, 0, sizeflag)) { if (OP_I (ins, bytemode, sizeflag)) { ins->codep--; } return true; } } return false; } Then the uwrmsr's unit will be { "uwrmsr", { { uwrmsr_Fixup, d_mode }, Rq }, 0 }. What‘s your opinion? > > >> @@ -3346,3 +3349,12 @@ erets, 0xf20f01ca, FRED|x64, NoSuf, {} eretu, > >> 0xf30f01ca, FRED|x64, NoSuf, {} > >> > >> // FRED instructions end. > >> + > >> +// USER_MSR instructions. > >> + > >> +urdmsr, 0xf20f38f8, USER_MSR|x64, > >> +Modrm|IgnoreSize|SwapSourceDest|NoSuf, { Reg64, Reg64 } > > > >> Iirc RegMem is the attribute to use here, not any new one. > > > > Indeed. > > > >> +urdmsr, 0xf2f8/0, USER_MSR|x64, > >> +Modrm|Vex128|VexMap7|VexW0|IgnoreSize|NoSuf, { Imm32S, Reg64 } > > > >> This and ... > > > >> +uwrmsr, 0xf30f38f8, USER_MSR|x64, Modrm|IgnoreSize|NoSuf, { Reg64, > >> +Reg64 } uwrmsr, 0xf3f8/0, USER_MSR|x64, > >> +Modrm|Vex128|VexMap7|VexW0|IgnoreSize|SwapSourceDest|NoSuf, > { Reg64, > >> +Imm32S } > > > >> ... this needs to use Imm32, not Imm32S. I understand this is going to cause > complications elsewhere, but we can't afford getting this wrong. > > I see you've corrected this, but it doesn't look to me as if the > match_template() change is actually going to do the job. You can't change > i.types[] without looking at the actual values. I think this needs dealing with in > optimize_imm() and/or finalize_imm() (irrespective of it's name more likely the > former, but knock-on adjustments to the latter may then turn out to be needed). > OK. > >> Also in all forms I think you don't mean IgnoreSize, but NoRex64. > > > > Have modified them. > > Hmm, I may have mislead you: NoRex64 is meaningless on VEX encodings. > There only the IgnoreSize needed dropping. I'm sorry. > > Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH] Support Intel USER_MSR 2023-10-24 8:38 ` Hu, Lin1 @ 2023-10-24 8:55 ` Jan Beulich 2023-10-24 10:01 ` Hu, Lin1 0 siblings, 1 reply; 33+ messages in thread From: Jan Beulich @ 2023-10-24 8:55 UTC (permalink / raw) To: Hu, Lin1, Lu, Hongjiu; +Cc: binutils On 24.10.2023 10:38, Hu, Lin1 wrote: >> -----Original Message----- >> From: Jan Beulich <jbeulich@suse.com> >> Sent: Thursday, October 19, 2023 4:36 PM >> >> On 18.10.2023 09:51, Hu, Lin1 wrote: >>> -----Original Message----- >>> From: Jan Beulich <jbeulich@suse.com> >>> Sent: Monday, October 16, 2023 8:11 PM >>> >>> On 10.10.2023 09:24, Hu, Lin1 wrote: >>>> @@ -8752,6 +8755,18 @@ build_modrm_byte (void) >>>> source = v; >>>> v = tmp; >>>> } >>>> + if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCE_DEST) >>>> + { >>>> + if (dest == (unsigned int) ~0) >>>> + source = source ^ 1; >>>> + else >>>> + { >>>> + unsigned int tmp = source; >>>> + >>>> + source = dest; >>>> + dest = tmp; >>>> + } >>>> + } >>> >>>> Why is this needed? There's only a single register operand in both affected >> insn forms (see comment below on the 2-register form). >>> Furthermore I think it would be easier if you "canonicalized" the early >> immediate to be the 1st operand, such that for all other purposes immediates >> remain first. >>> >>>> As a cosmetic nit: Please have a blank line ahead of the if() block (if it needs >> to stay). >>> >>> Indeed, I've only kept the part that deals with a single register. Do you mean to >> complain to the person who designed the insn. Unfortunately, that's impossible. >> >> I'm having trouble connecting your reply to what I wrote. No, I do not mean to >> complain; I can certainly see why the immediate is wanted as first (Intel) / last >> (AT&T) operand. >> >> I'm also not happy about the new change to build_modrm_byte(). When asking >> to "canonicalize" operands, I meant to gave this generalized, with >> SWAP_SOURCE_DEST dropped completely. (This will then also save me from >> complaining about a missing blank in SwapSourceDest's >> #define.) >> > > OK, I implemented a basic logic to handle the current situation, and included remarks. > Like: > > /* If the last operand is an immediate number (ATT), we need to modify > the source operand accordingly. If any instructions use other immediate > (imm8, imm16, etc.) as the last operand, we must update the constraint. */ > if (i.types[source].bitfield.imm32 == 1) > source--; > > What's your opinion on this version? As before - build_modrm_byte() is the wrong place to make the intended (generalized) adjustment. You want to move the unusually placed imm operand to its usual place as soon as you're done with matching input against the respective template. >>>> --- /dev/null >>>> +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s >>>> @@ -0,0 +1,15 @@ >>>> +# Check 64bit USER_MSR instructions >>>> + >>>> + .allow_index_reg >>>> + .text >>>> +_start: >>>> + urdmsr %r14, %r12 #USER_MSR >>>> + urdmsr $51515151, %r12 #USER_MSR >>>> + uwrmsr %r12, %r14 #USER_MSR >>>> + uwrmsr %r12, $51515151 #USER_MSR >>>> + >>>> +.intel_syntax noprefix >>> >>>> Nit: Please indent directives. >>> Have removed these comments. >> >> Neither does your reply fit here, nor did you what I've asked for here (in addition >> to the earlier, wider request of dropping meaningless comments). >> > > Perhaps there's an issue with my interface, but it seems to me that the > instruction now begins with a \t instead of two spaces for the updated patch. Not that you say "instruction" when I said "directive". My comment wasn't about any instruction, but about the ".intel_syntax noprefix" line. >>>> @@ -6791,6 +6839,297 @@ static const struct dis386 vex_table[][256] = { >>>> { Bad_Opcode }, >>>> { Bad_Opcode }, >>>> }, >>>> + /* VEX_MAP7 */ >>>> + { >>>> + /* 00 */ >>>> + { Bad_Opcode }, >>> >>>> I wonder whether adding a full new table (rather than some special >>>> case >>>> code) is really a god use of space. Of course if you know that more of it will >> be populated in the not too distant future ... >>> >>> I don't know, I'm just treating the new opcode_space MAP7 like other >> opcode_space. >> >> I'm afraid that "I don't know" is not an answer here. You can basically take two >> positions: Mine (waste of space) or you justify why the extra space used (and the >> extra runtime relocations added) aren't of concern. >> > > OK, I will skip MAP7 table. If vex_table_index = VEX_MAP7 and index == f8 > dp will be VEX_LEN_MAP7_F8. So I don't need to add a full new table untill other MAP7 > instructions raise. H.J., before we go this route, what's your view here? >>>> @@ -11248,6 +11609,20 @@ get32s (instr_info *ins, bfd_vma *res) >>>> return true; >>>> } >>>> >>>> +/* The function is used to get imm32, when imm32 is operand 0, and >>>> +ins only has 2 operands. */ static bool >>>> +get32_operand0 (instr_info *ins, bfd_vma *res) { >>>> + >>>> + if (!fetch_code (ins->info, ins->codep + 5)) >>>> + return false; >>>> + *res = *(ins->codep++ + 1) & (bfd_vma) 0xff; >>>> + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 8; >>>> + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 16; >>>> + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 24; >>>> + return true; >>>> +} >>> >>>> Instead of this (which assumes ModRM.mod == 3) I think you want to arrange >> for dealing with ModRM first. We already have OP_Skip_MODRM() for such >> needs, which you could use in a first "hidden" operand. >>> >>> I want to output imm32 first, but modrm byte is behind imm32, so I need to >> skip modrm for the moment. but I can't use OP_Skip_MODRM to deal with my >> problem, If I use it, I should add ins->codep-- at the end of get32_operand0. >> >> get32_operand0() should go away imo; at the very least I don't agree with >> special casing it being operand 0 (which, as you realize, is true only in the textual >> representation, and only in Intel syntax, but in particular not in the encoding). It >> may be necessary to special case it being an unsigned immediate, but get32() >> already fits that purpose. > > I've thought of it so far is I can use a Fixup function like > > static bool > uwrmsr_Fixup (instr_info *ins, int bytemode, int sizeflag) > { > if (bytemode == d_mode) > { > if (OP_Skip_MODRM (ins, 0, sizeflag)) > { > if (OP_I (ins, bytemode, sizeflag)) > { > ins->codep--; > } > return true; > } > } > return false; > } > > Then the uwrmsr's unit will be { "uwrmsr", { { uwrmsr_Fixup, d_mode }, Rq }, 0 }. > What‘s your opinion? Hmm, not very nice, but I can't exclude it simply won't get any better. My desire was for there to not be any new fixup function, and for OP_Skip_MODRM to be used directly in the table entry. (In any event, if you really need to keep this new function, please combine the three if()-s into a single one, helping readability quite a bit. Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH] Support Intel USER_MSR 2023-10-24 8:55 ` Jan Beulich @ 2023-10-24 10:01 ` Hu, Lin1 2023-10-24 12:02 ` Jan Beulich 0 siblings, 1 reply; 33+ messages in thread From: Hu, Lin1 @ 2023-10-24 10:01 UTC (permalink / raw) To: Beulich, Jan, Lu, Hongjiu; +Cc: binutils > -----Original Message----- > From: Jan Beulich <jbeulich@suse.com> > Sent: Tuesday, October 24, 2023 4:56 PM > To: Hu, Lin1 <lin1.hu@intel.com>; Lu, Hongjiu <hongjiu.lu@intel.com> > Cc: binutils@sourceware.org > Subject: Re: [PATCH] Support Intel USER_MSR > > On 24.10.2023 10:38, Hu, Lin1 wrote: > >> -----Original Message----- > >> From: Jan Beulich <jbeulich@suse.com> > >> Sent: Thursday, October 19, 2023 4:36 PM > >> > >> On 18.10.2023 09:51, Hu, Lin1 wrote: > >>> -----Original Message----- > >>> From: Jan Beulich <jbeulich@suse.com> > >>> Sent: Monday, October 16, 2023 8:11 PM > >>> > >>> On 10.10.2023 09:24, Hu, Lin1 wrote: > >>>> @@ -8752,6 +8755,18 @@ build_modrm_byte (void) > >>>> source = v; > >>>> v = tmp; > >>>> } > >>>> + if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCE_DEST) > >>>> + { > >>>> + if (dest == (unsigned int) ~0) > >>>> + source = source ^ 1; > >>>> + else > >>>> + { > >>>> + unsigned int tmp = source; > >>>> + > >>>> + source = dest; > >>>> + dest = tmp; > >>>> + } > >>>> + } > >>> > >>>> Why is this needed? There's only a single register operand in both > >>>> affected > >> insn forms (see comment below on the 2-register form). > >>> Furthermore I think it would be easier if you "canonicalized" the > >>> early > >> immediate to be the 1st operand, such that for all other purposes > >> immediates remain first. > >>> > >>>> As a cosmetic nit: Please have a blank line ahead of the if() block > >>>> (if it needs > >> to stay). > >>> > >>> Indeed, I've only kept the part that deals with a single register. > >>> Do you mean to > >> complain to the person who designed the insn. Unfortunately, that's > impossible. > >> > >> I'm having trouble connecting your reply to what I wrote. No, I do > >> not mean to complain; I can certainly see why the immediate is wanted > >> as first (Intel) / last > >> (AT&T) operand. > >> > >> I'm also not happy about the new change to build_modrm_byte(). When > >> asking to "canonicalize" operands, I meant to gave this generalized, > >> with SWAP_SOURCE_DEST dropped completely. (This will then also save > >> me from complaining about a missing blank in SwapSourceDest's > >> #define.) > >> > > > > OK, I implemented a basic logic to handle the current situation, and included > remarks. > > Like: > > > > /* If the last operand is an immediate number (ATT), we need to modify > > the source operand accordingly. If any instructions use other immediate > > (imm8, imm16, etc.) as the last operand, we must update the constraint. > */ > > if (i.types[source].bitfield.imm32 == 1) > > source--; > > > > What's your opinion on this version? > > As before - build_modrm_byte() is the wrong place to make the intended > (generalized) adjustment. You want to move the unusually placed imm operand > to its usual place as soon as you're done with matching input against the > respective template. Oh, I get you. > > >>>> --- /dev/null > >>>> +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s > >>>> @@ -0,0 +1,15 @@ > >>>> +# Check 64bit USER_MSR instructions > >>>> + > >>>> + .allow_index_reg > >>>> + .text > >>>> +_start: > >>>> + urdmsr %r14, %r12 #USER_MSR > >>>> + urdmsr $51515151, %r12 #USER_MSR > >>>> + uwrmsr %r12, %r14 #USER_MSR > >>>> + uwrmsr %r12, $51515151 #USER_MSR > >>>> + > >>>> +.intel_syntax noprefix > >>> > >>>> Nit: Please indent directives. > >>> Have removed these comments. > >> > >> Neither does your reply fit here, nor did you what I've asked for > >> here (in addition to the earlier, wider request of dropping meaningless > comments). > >> > > > > Perhaps there's an issue with my interface, but it seems to me that > > the instruction now begins with a \t instead of two spaces for the updated > patch. > > Not that you say "instruction" when I said "directive". My comment wasn't > about any instruction, but about the ".intel_syntax noprefix" > line. > Okay, thanks for the explanation. > >>>> @@ -6791,6 +6839,297 @@ static const struct dis386 vex_table[][256] = { > >>>> { Bad_Opcode }, > >>>> { Bad_Opcode }, > >>>> }, > >>>> + /* VEX_MAP7 */ > >>>> + { > >>>> + /* 00 */ > >>>> + { Bad_Opcode }, > >>> > >>>> I wonder whether adding a full new table (rather than some special > >>>> case > >>>> code) is really a god use of space. Of course if you know that more > >>>> of it will > >> be populated in the not too distant future ... > >>> > >>> I don't know, I'm just treating the new opcode_space MAP7 like other > >> opcode_space. > >> > >> I'm afraid that "I don't know" is not an answer here. You can > >> basically take two > >> positions: Mine (waste of space) or you justify why the extra space > >> used (and the extra runtime relocations added) aren't of concern. > >> > > > > OK, I will skip MAP7 table. If vex_table_index = VEX_MAP7 and index == > > f8 dp will be VEX_LEN_MAP7_F8. So I don't need to add a full new table > > untill other MAP7 instructions raise. > > H.J., before we go this route, what's your view here? > Just mention: H.J. has a sabbatical until Nov 30 2023. I'm not sure if you got his e-mail. > >>>> @@ -11248,6 +11609,20 @@ get32s (instr_info *ins, bfd_vma *res) > >>>> return true; > >>>> } > >>>> > >>>> +/* The function is used to get imm32, when imm32 is operand 0, and > >>>> +ins only has 2 operands. */ static bool > >>>> +get32_operand0 (instr_info *ins, bfd_vma *res) { > >>>> + > >>>> + if (!fetch_code (ins->info, ins->codep + 5)) > >>>> + return false; > >>>> + *res = *(ins->codep++ + 1) & (bfd_vma) 0xff; > >>>> + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 8; > >>>> + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 16; > >>>> + *res |= (*(ins->codep++ + 1) & (bfd_vma) 0xff) << 24; > >>>> + return true; > >>>> +} > >>> > >>>> Instead of this (which assumes ModRM.mod == 3) I think you want to > >>>> arrange > >> for dealing with ModRM first. We already have OP_Skip_MODRM() for > >> such needs, which you could use in a first "hidden" operand. > >>> > >>> I want to output imm32 first, but modrm byte is behind imm32, so I > >>> need to > >> skip modrm for the moment. but I can't use OP_Skip_MODRM to deal with > >> my problem, If I use it, I should add ins->codep-- at the end of > get32_operand0. > >> > >> get32_operand0() should go away imo; at the very least I don't agree > >> with special casing it being operand 0 (which, as you realize, is > >> true only in the textual representation, and only in Intel syntax, > >> but in particular not in the encoding). It may be necessary to > >> special case it being an unsigned immediate, but get32() already fits that > purpose. > > > > I've thought of it so far is I can use a Fixup function like > > > > static bool > > uwrmsr_Fixup (instr_info *ins, int bytemode, int sizeflag) { > > if (bytemode == d_mode) > > { > > if (OP_Skip_MODRM (ins, 0, sizeflag)) > > { > > if (OP_I (ins, bytemode, sizeflag)) > > { > > ins->codep--; > > } > > return true; > > } > > } > > return false; > > } > > > > Then the uwrmsr's unit will be { "uwrmsr", { { uwrmsr_Fixup, d_mode }, > Rq }, 0 }. > > What‘s your opinion? > > Hmm, not very nice, but I can't exclude it simply won't get any better. > My desire was for there to not be any new fixup function, and for > OP_Skip_MODRM to be used directly in the table entry. (In any event, if you > really need to keep this new function, please combine the three if()-s into a > single one, helping readability quite a bit. > I have another idea, can I have a new function like OP_back_codep(...) { Ins->codep--; Return true; } So the uwrmsr's unit will be { "uwrmsr", { Skip_MODRM, Id, Back_Codep, Rq }, 0 }. OK, thanks for your advices. > Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH] Support Intel USER_MSR 2023-10-24 10:01 ` Hu, Lin1 @ 2023-10-24 12:02 ` Jan Beulich 2023-10-25 2:01 ` Hu, Lin1 0 siblings, 1 reply; 33+ messages in thread From: Jan Beulich @ 2023-10-24 12:02 UTC (permalink / raw) To: Hu, Lin1; +Cc: binutils, Lu, Hongjiu On 24.10.2023 12:01, Hu, Lin1 wrote: >> -----Original Message----- >> From: Jan Beulich <jbeulich@suse.com> >> Sent: Tuesday, October 24, 2023 4:56 PM >> >> On 24.10.2023 10:38, Hu, Lin1 wrote: >>> I've thought of it so far is I can use a Fixup function like >>> >>> static bool >>> uwrmsr_Fixup (instr_info *ins, int bytemode, int sizeflag) { >>> if (bytemode == d_mode) >>> { >>> if (OP_Skip_MODRM (ins, 0, sizeflag)) >>> { >>> if (OP_I (ins, bytemode, sizeflag)) >>> { >>> ins->codep--; >>> } >>> return true; >>> } >>> } >>> return false; >>> } >>> >>> Then the uwrmsr's unit will be { "uwrmsr", { { uwrmsr_Fixup, d_mode }, >> Rq }, 0 }. >>> What‘s your opinion? >> >> Hmm, not very nice, but I can't exclude it simply won't get any better. >> My desire was for there to not be any new fixup function, and for >> OP_Skip_MODRM to be used directly in the table entry. (In any event, if you >> really need to keep this new function, please combine the three if()-s into a >> single one, helping readability quite a bit. >> > > I have another idea, can I have a new function like > > OP_back_codep(...) > { > Ins->codep--; > Return true; > } > > So the uwrmsr's unit will be { "uwrmsr", { Skip_MODRM, Id, Back_Codep, Rq }, 0 }. Well, the main thing I dislike is the decrementing of codep, no matter where it's put. In case you don't think you can get away without, I guess I'll try afterwards, aiming at an incremental change then. Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH] Support Intel USER_MSR 2023-10-24 12:02 ` Jan Beulich @ 2023-10-25 2:01 ` Hu, Lin1 2023-10-25 8:48 ` Jan Beulich 0 siblings, 1 reply; 33+ messages in thread From: Hu, Lin1 @ 2023-10-25 2:01 UTC (permalink / raw) To: Beulich, Jan; +Cc: binutils, Lu, Hongjiu > -----Original Message----- > From: Jan Beulich <jbeulich@suse.com> > Sent: Tuesday, October 24, 2023 8:02 PM > To: Hu, Lin1 <lin1.hu@intel.com> > Cc: binutils@sourceware.org; Lu, Hongjiu <hongjiu.lu@intel.com> > Subject: Re: [PATCH] Support Intel USER_MSR > > On 24.10.2023 12:01, Hu, Lin1 wrote: > >> -----Original Message----- > >> From: Jan Beulich <jbeulich@suse.com> > >> Sent: Tuesday, October 24, 2023 4:56 PM > >> > >> On 24.10.2023 10:38, Hu, Lin1 wrote: > >>> I've thought of it so far is I can use a Fixup function like > >>> > >>> static bool > >>> uwrmsr_Fixup (instr_info *ins, int bytemode, int sizeflag) { > >>> if (bytemode == d_mode) > >>> { > >>> if (OP_Skip_MODRM (ins, 0, sizeflag)) > >>> { > >>> if (OP_I (ins, bytemode, sizeflag)) > >>> { > >>> ins->codep--; > >>> } > >>> return true; > >>> } > >>> } > >>> return false; > >>> } > >>> > >>> Then the uwrmsr's unit will be { "uwrmsr", { { uwrmsr_Fixup, > d_mode }, > >> Rq }, 0 }. > >>> What‘s your opinion? > >> > >> Hmm, not very nice, but I can't exclude it simply won't get any better. > >> My desire was for there to not be any new fixup function, and for > >> OP_Skip_MODRM to be used directly in the table entry. (In any event, > >> if you really need to keep this new function, please combine the > >> three if()-s into a single one, helping readability quite a bit. > >> > > > > I have another idea, can I have a new function like > > > > OP_back_codep(...) > > { > > Ins->codep--; > > Return true; > > } > > > > So the uwrmsr's unit will be { "uwrmsr", { Skip_MODRM, Id, Back_Codep, Rq }, > 0 }. > > Well, the main thing I dislike is the decrementing of codep, no matter where it's > put. In case you don't think you can get away without, I guess I'll try afterwards, > aiming at an incremental change then. > I have another one in mind at the moment. Can I have a bool variable in instr_info, @@ -221,6 +221,9 @@ struct instr_info /* Record whether EVEX masking is used incorrectly. */ bool illegal_masking; + /* Record whether the modrm byte has been skipped. */ + bool has_skipped_modrm. + unsigned char op_ad; And the Skip mod/rm byte pattern will be @@ -11668,7 +11658,11 @@ OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, /* Skip mod/rm byte. */ MODRM_CHECK; - ins->codep++; + if (!ins->has_skipped_modrm) + { + ins->codep++; + ins->has_skipped_modrm = true; + } return true; } . This change will be applied to all other similar sections (include OP_E). So the uwrmsr's unit will be { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 }, because the codep won't increasing in Rq, I don't need the decrementing of codep. > Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH] Support Intel USER_MSR 2023-10-25 2:01 ` Hu, Lin1 @ 2023-10-25 8:48 ` Jan Beulich 2023-10-25 9:11 ` [PATCH][v3] " Hu, Lin1 0 siblings, 1 reply; 33+ messages in thread From: Jan Beulich @ 2023-10-25 8:48 UTC (permalink / raw) To: Hu, Lin1; +Cc: binutils, Lu, Hongjiu On 25.10.2023 04:01, Hu, Lin1 wrote: >> -----Original Message----- >> From: Jan Beulich <jbeulich@suse.com> >> Sent: Tuesday, October 24, 2023 8:02 PM >> To: Hu, Lin1 <lin1.hu@intel.com> >> Cc: binutils@sourceware.org; Lu, Hongjiu <hongjiu.lu@intel.com> >> Subject: Re: [PATCH] Support Intel USER_MSR >> >> On 24.10.2023 12:01, Hu, Lin1 wrote: >>>> -----Original Message----- >>>> From: Jan Beulich <jbeulich@suse.com> >>>> Sent: Tuesday, October 24, 2023 4:56 PM >>>> >>>> On 24.10.2023 10:38, Hu, Lin1 wrote: >>>>> I've thought of it so far is I can use a Fixup function like >>>>> >>>>> static bool >>>>> uwrmsr_Fixup (instr_info *ins, int bytemode, int sizeflag) { >>>>> if (bytemode == d_mode) >>>>> { >>>>> if (OP_Skip_MODRM (ins, 0, sizeflag)) >>>>> { >>>>> if (OP_I (ins, bytemode, sizeflag)) >>>>> { >>>>> ins->codep--; >>>>> } >>>>> return true; >>>>> } >>>>> } >>>>> return false; >>>>> } >>>>> >>>>> Then the uwrmsr's unit will be { "uwrmsr", { { uwrmsr_Fixup, >> d_mode }, >>>> Rq }, 0 }. >>>>> What‘s your opinion? >>>> >>>> Hmm, not very nice, but I can't exclude it simply won't get any better. >>>> My desire was for there to not be any new fixup function, and for >>>> OP_Skip_MODRM to be used directly in the table entry. (In any event, >>>> if you really need to keep this new function, please combine the >>>> three if()-s into a single one, helping readability quite a bit. >>>> >>> >>> I have another idea, can I have a new function like >>> >>> OP_back_codep(...) >>> { >>> Ins->codep--; >>> Return true; >>> } >>> >>> So the uwrmsr's unit will be { "uwrmsr", { Skip_MODRM, Id, Back_Codep, Rq }, >> 0 }. >> >> Well, the main thing I dislike is the decrementing of codep, no matter where it's >> put. In case you don't think you can get away without, I guess I'll try afterwards, >> aiming at an incremental change then. >> > > I have another one in mind at the moment. Can I have a bool variable in instr_info, > > @@ -221,6 +221,9 @@ struct instr_info > /* Record whether EVEX masking is used incorrectly. */ > bool illegal_masking; > > + /* Record whether the modrm byte has been skipped. */ > + bool has_skipped_modrm. > + > unsigned char op_ad; > > And the Skip mod/rm byte pattern will be > > @@ -11668,7 +11658,11 @@ OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, > > /* Skip mod/rm byte. */ > MODRM_CHECK; > - ins->codep++; > + if (!ins->has_skipped_modrm) > + { > + ins->codep++; > + ins->has_skipped_modrm = true; > + } > return true; > } > . > This change will be applied to all other similar sections (include OP_E). Yes, that's along the lines of what I had in mind. Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH][v3] Support Intel USER_MSR 2023-10-25 8:48 ` Jan Beulich @ 2023-10-25 9:11 ` Hu, Lin1 2023-10-25 11:43 ` Jan Beulich 0 siblings, 1 reply; 33+ messages in thread From: Hu, Lin1 @ 2023-10-25 9:11 UTC (permalink / raw) To: binutils; +Cc: JBeulich, hongjiu.lu This patch is the 3rd version of USER_MSR. For some problems about MAP7 and Imm32, I feel like the way it's currently handled isn't graceful enough, but I don't have a better idea at the moment, so I wanted to see what you thought. gas/ChangeLog: * NEWS: Support Intel USER_MSR. * config/tc-i386.c: Add user_msr and add VEXMAP7 in opc_spc and build_vex_prefix. (build_modrm_byte): Swap Operands for USER_MSR. * doc/c-i386.texi: Document .user_msr. * testsuite/gas/i386/i386.exp: Run USER_MSR tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/user_msr-inval.l: New test. * testsuite/gas/i386/user_msr-inval.s: Ditto. * testsuite/gas/i386/x86-64-user_msr-intel.d: Ditto. * testsuite/gas/i386/x86-64-user_msr.d: Ditto. * testsuite/gas/i386/x86-64-user_msr.s: Ditto. opcodes/ChangeLog: * i386-dis.c (get32_operand0): Add a new function to get operand0 that is IMM32. (Gq): New. (Id0): Ditto. (get_valid_dis386): Add VEX_MAP7 in VEX prefix. (OP_I): Handle d_0_mode. (d_0_mode): New. (REG_VEX_MAP7_F8_L_0_W_0): New. (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64): Ditto. (X86_64_VEX_MAP7_F8_L_0_W_0_R_0): Ditto. (VEX_MAP7): Ditto. (VEX_LEN_MAP7_F8): Ditto. (VEX_W_MAP7_F8_L_0): Ditto. (MOD_0F38F8): Ditto. (PREFIX_0F38F8_M_0): Ditto. (PREFIX_0F38F8_M_1_X86_64): Ditto. (X86_64_0F38F8_M_1): Ditto. (PREFIX_0F38F8): Remove. (prefix_table): Add PREFIX_0F38F8_M_1_X86_64. Remove PREFIX_0F38F8. (reg_table): Add REG_VEX_MAP7_F8_L_0_W_0, PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64. (x86_64_table): Add X86_64_0F38F8_PREFIX_3_M_1, X86_64_VEX_MAP7_F8_L_0_W_0_R_0 and X86_64_0F38F8_M_1. (vex_table): Add VEX_MAP7. (vex_len_table): Add VEX_LEN_MAP7_F8, VEX_W_MAP7_F8_L_0. (mod_table): New entry for USER_MSR and add MOD_0F38F8. * i386-gen.c (cpu_flag_init): Add CPU_USER_MSR_FLAGS and CPU_ANY_USER_MSR_FLAGS. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (SPACE_VEXMAP7): New. (SWAP_SOURCE_DEST): Ditto. (CPU_USER_MSR_FLAGS): Ditoo. (CPU_ANY_USER_MSR_FLAGS): Ditto. (i386_cpu_flags): Add cpuuser_msr. * i386-opc.tbl: Add USER_MSR instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 2 + gas/config/tc-i386.c | 25 + gas/doc/c-i386.texi | 3 +- gas/testsuite/gas/i386/i386.exp | 1 + gas/testsuite/gas/i386/user_msr-inval.l | 3 + gas/testsuite/gas/i386/user_msr-inval.s | 7 + .../gas/i386/x86-64-user_msr-intel.d | 34 + gas/testsuite/gas/i386/x86-64-user_msr.d | 34 + gas/testsuite/gas/i386/x86-64-user_msr.s | 31 + gas/testsuite/gas/i386/x86-64.exp | 2 + opcodes/i386-dis.c | 144 +- opcodes/i386-gen.c | 2 + opcodes/i386-opc.h | 5 + opcodes/i386-opc.tbl | 11 + 17 files changed, 1495 insertions(+), 1175 deletions(-) create mode 100644 gas/testsuite/gas/i386/user_msr-inval.l create mode 100644 gas/testsuite/gas/i386/user_msr-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr.d create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr.s diff --git a/gas/NEWS b/gas/NEWS index 71a1269b893..ab0e7813f27 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel USER_MSR instructions. + * Add support for Intel AVX10.1. * Add support for Intel PBNDKB instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 714354d5116..d89aad52eff 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1164,6 +1164,7 @@ static const arch_entry cpu_arch[] = VECARCH (sm4, SM4, ANY_SM4, reset), SUBARCH (pbndkb, PBNDKB, PBNDKB, false), VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set), + SUBARCH (user_msr, USER_MSR, USER_MSR, false), }; #undef SUBARCH @@ -3863,6 +3864,7 @@ build_vex_prefix (const insn_template *t) case SPACE_0F: case SPACE_0F38: case SPACE_0F3A: + case SPACE_VEXMAP7: i.vex.bytes[0] = 0xc4; break; case SPACE_XOP08: @@ -5235,6 +5237,17 @@ md_assemble (char *line) if (i.imm_operands) optimize_imm (); + /* user_msr instructions can match Imm32 templates when + guess_suffix == QWORD_MNEM_SUFFIX. */ + if (t->mnem_off == MN_urdmsr) + i.types[0] + = operand_type_or (i.types[0], + smallest_imm_type (i.op[0].imms->X_add_number)); + if (t->mnem_off == MN_uwrmsr) + i.types[1] + = operand_type_or (i.types[1], + smallest_imm_type (i.op[1].imms->X_add_number)); + if (i.disp_operands && !optimize_disp (t)) return; @@ -7566,6 +7579,18 @@ match_template (char mnem_suffix) break; } + /* This pattern aims to put the unusually placed imm operand to a usual + place. The constraints are currently only adapted to uwrmsr, and may + need further tweaking when new similar instructions become available. */ + if (i.operands > 0 + && i.tm.operand_types[0].bitfield.class == Reg + && operand_type_check (i.tm.operand_types[i.operands - 1], imm)) + { + i.tm.operand_types[0] = operand_types[i.operands - 1]; + i.tm.operand_types[i.operands - 1] = operand_types[0]; + swap_2_operands(0, i.operands - 1); + } + return t; } diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index b04e1b00b4b..03ee980bef7 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -216,6 +216,7 @@ accept various extension mnemonics. For example, @code{avx10.1/512}, @code{avx10.1/256}, @code{avx10.1/128}, +@code{user_msr}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1650,7 +1651,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} @item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs} @item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4} -@item @samp{.pbndkb} +@item @samp{.pbndkb} @tab @samp{.user_msr} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index ee74bcd4615..81ce1e38b10 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -509,6 +509,7 @@ if [gas_32_check] then { run_dump_test "sm4" run_dump_test "sm4-intel" run_list_test "pbndkb-inval" + run_list_test "user_msr-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" diff --git a/gas/testsuite/gas/i386/user_msr-inval.l b/gas/testsuite/gas/i386/user_msr-inval.l new file mode 100644 index 00000000000..9618645bea8 --- /dev/null +++ b/gas/testsuite/gas/i386/user_msr-inval.l @@ -0,0 +1,3 @@ +.* Assembler messages: +.*:6: Error: `urdmsr' is only supported in 64-bit mode +.*:7: Error: `uwrmsr' is only supported in 64-bit mode diff --git a/gas/testsuite/gas/i386/user_msr-inval.s b/gas/testsuite/gas/i386/user_msr-inval.s new file mode 100644 index 00000000000..3762e2bd7b9 --- /dev/null +++ b/gas/testsuite/gas/i386/user_msr-inval.s @@ -0,0 +1,7 @@ +# Check Illegal 32bit USER_MSR instructions + + .allow_index_reg + .text +_start: + urdmsr %r12, %r14 + uwrmsr %r12, %r14 diff --git a/gas/testsuite/gas/i386/x86-64-user_msr-intel.d b/gas/testsuite/gas/i386/x86-64-user_msr-intel.d new file mode 100644 index 00000000000..94d969c68e9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr-intel.d @@ -0,0 +1,34 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 USER_MSR insns (Intel disassembly) +#source: x86-64-user_msr.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr r12,r14 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr rax,r14 +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr r12,rdx +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr rax,rdx +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr r12,0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr rax,0x3120f0f +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr r14,r12 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr r14,rax +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr rdx,r12 +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr rdx,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr 0x3120f0f,r12 +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr 0x3120f0f,rax +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr r12,r14 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr rax,r14 +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr r12,rdx +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr rax,rdx +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr r12,0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr rax,0x3120f0f +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr r14,r12 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr r14,rax +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr rdx,r12 +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr rdx,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr 0x3120f0f,r12 +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr 0x3120f0f,rax diff --git a/gas/testsuite/gas/i386/x86-64-user_msr.d b/gas/testsuite/gas/i386/x86-64-user_msr.d new file mode 100644 index 00000000000..d3e4543bc33 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr.d @@ -0,0 +1,34 @@ +#as: +#objdump: -dw +#name: x86_64 USER_MSR insns +#source: x86-64-user_msr.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr %r14,%r12 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr %r14,%rax +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr %rdx,%r12 +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr %rdx,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr \$0x3120f0f,%r12 +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr \$0x3120f0f,%rax +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr %r12,%r14 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr %rax,%r14 +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr %r12,%rdx +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr %rax,%rdx +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr %r12,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr %rax,\$0x3120f0f +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr %r14,%r12 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr %r14,%rax +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr %rdx,%r12 +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr %rdx,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr \$0x3120f0f,%r12 +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr \$0x3120f0f,%rax +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr %r12,%r14 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr %rax,%r14 +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr %r12,%rdx +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr %rax,%rdx +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr %r12,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr %rax,\$0x3120f0f diff --git a/gas/testsuite/gas/i386/x86-64-user_msr.s b/gas/testsuite/gas/i386/x86-64-user_msr.s new file mode 100644 index 00000000000..3801044d254 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s @@ -0,0 +1,31 @@ +# Check 64bit USER_MSR instructions + + .allow_index_reg + .text +_start: + urdmsr %r14, %r12 + urdmsr %r14, %rax + urdmsr %rdx, %r12 + urdmsr %rdx, %rax + urdmsr $51515151, %r12 + urdmsr $51515151, %rax + uwrmsr %r12, %r14 + uwrmsr %rax, %r14 + uwrmsr %r12, %rdx + uwrmsr %rax, %rdx + uwrmsr %r12, $51515151 + uwrmsr %rax, $51515151 + + .intel_syntax noprefix + urdmsr r12, r14 + urdmsr rax, r14 + urdmsr r12, rdx + urdmsr rax, rdx + urdmsr r12, 51515151 + urdmsr rax, 51515151 + uwrmsr r14, r12 + uwrmsr r14, rax + uwrmsr rdx, r12 + uwrmsr rdx, rax + uwrmsr 51515151, r12 + uwrmsr 51515151, rax diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 52711cdcf6f..5765d473e31 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -450,6 +450,8 @@ run_dump_test "x86-64-sm4" run_dump_test "x86-64-sm4-intel" run_dump_test "x86-64-pbndkb" run_dump_test "x86-64-pbndkb-intel" +run_dump_test "x86-64-user_msr" +run_dump_test "x86-64-user_msr-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 87ecf0f5e23..1b7fa648e8e 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -221,6 +221,9 @@ struct instr_info /* Record whether EVEX masking is used incorrectly. */ bool illegal_masking; + /* Record whether the modrm byte has been skipped. */ + bool has_skipped_modrm; + unsigned char op_ad; signed char op_index[MAX_OPERANDS]; bool op_riprel[MAX_OPERANDS]; @@ -418,6 +421,7 @@ fetch_error (const instr_info *ins) #define Gv { OP_G, v_mode } #define Gd { OP_G, d_mode } #define Gdq { OP_G, dq_mode } +#define Gq { OP_G, q_mode } #define Gm { OP_G, m_mode } #define Gva { OP_G, va_mode } #define Gw { OP_G, w_mode } @@ -527,7 +531,8 @@ fetch_error (const instr_info *ins) #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } #define Rd { OP_R, d_mode } #define Rdq { OP_R, dq_mode } -#define Nq { OP_R, q_mode } +#define Rq { OP_R, q_mode } +#define Nq { OP_R, q_mm_mode } #define Ux { OP_R, x_mode } #define Uxmm { OP_R, xmm_mode } #define Rxmmq { OP_R, xmmq_mode } @@ -624,6 +629,8 @@ enum d_swap_mode, /* quad word operand */ q_mode, + /* 64-byte MM operand */ + q_mm_mode, /* quad word operand with operand swapped */ q_swap_mode, /* ten-byte operand */ @@ -845,6 +852,7 @@ enum REG_VEX_0FAE, REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0, REG_VEX_0F38F3_L_0, + REG_VEX_MAP7_F8_L_0_W_0, REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, @@ -893,6 +901,7 @@ enum MOD_0FC7_REG_6, MOD_0FC7_REG_7, MOD_0F38DC_PREFIX_1, + MOD_0F38F8, MOD_VEX_0F3849_X86_64_L_0_W_0, }; @@ -1010,7 +1019,8 @@ enum PREFIX_0F38F0, PREFIX_0F38F1, PREFIX_0F38F6, - PREFIX_0F38F8, + PREFIX_0F38F8_M_0, + PREFIX_0F38F8_M_1_X86_64, PREFIX_0F38FA, PREFIX_0F38FB, PREFIX_0F38FC, @@ -1073,6 +1083,7 @@ enum PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0, PREFIX_VEX_0F3AF0_L_0, + PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F6F, @@ -1217,6 +1228,7 @@ enum X86_64_0F18_REG_7_MOD_0, X86_64_0F24, X86_64_0F26, + X86_64_0F38F8_M_1, X86_64_0FC7_REG_6_MOD_3_PREFIX_1, X86_64_VEX_0F3849, @@ -1240,6 +1252,7 @@ enum X86_64_VEX_0F38ED, X86_64_VEX_0F38EE, X86_64_VEX_0F38EF, + X86_64_VEX_MAP7_F8_L_0_W_0_R_0, }; enum @@ -1259,7 +1272,8 @@ enum { VEX_0F = 0, VEX_0F38, - VEX_0F3A + VEX_0F3A, + VEX_MAP7 }; enum @@ -1350,6 +1364,7 @@ enum VEX_LEN_0F3ADE_W_0, VEX_LEN_0F3ADF, VEX_LEN_0F3AF0, + VEX_LEN_MAP7_F8, VEX_LEN_XOP_08_85, VEX_LEN_XOP_08_86, VEX_LEN_XOP_08_87, @@ -1510,6 +1525,7 @@ enum VEX_W_0F3ACE, VEX_W_0F3ACF, VEX_W_0F3ADE, + VEX_W_MAP7_F8_L_0, VEX_W_XOP_08_85_L_0, VEX_W_XOP_08_86_L_0, @@ -2849,6 +2865,10 @@ static const struct dis386 reg_table[][8] = { { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE }, { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE }, }, + /* REG_VEX_MAP7_F8_L_0_W_0 */ + { + { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) }, + }, /* REG_XOP_09_01_L_0 */ { { Bad_Opcode }, @@ -3555,13 +3575,22 @@ static const struct dis386 prefix_table[][4] = { { Bad_Opcode }, }, - /* PREFIX_0F38F8 */ + /* PREFIX_0F38F8_M_0 */ { { Bad_Opcode }, { "enqcmds", { Gva, M }, 0 }, { "movdir64b", { Gva, M }, 0 }, { "enqcmd", { Gva, M }, 0 }, }, + + /* PREFIX_0F38F8_M_1_X86_64 */ + { + { Bad_Opcode }, + { "uwrmsr", { Gq, Rq }, 0 }, + { Bad_Opcode }, + { "urdmsr", { Rq, Gq }, 0 }, + }, + /* PREFIX_0F38FA */ { { Bad_Opcode }, @@ -4014,6 +4043,14 @@ static const struct dis386 prefix_table[][4] = { { "rorxS", { Gdq, Edq, Ib }, 0 }, }, + /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */ + { + { Bad_Opcode }, + { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 }, + { Bad_Opcode }, + { "urdmsr", { Rq, Id }, 0 }, + }, + #include "i386-dis-evex-prefix.h" }; @@ -4322,6 +4359,12 @@ static const struct dis386 x86_64_table[][2] = { { "movZ", { Td, Em }, 0 }, }, + { + /* X86_64_0F38F8_M_1 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) }, + }, + /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */ { { Bad_Opcode }, @@ -4453,6 +4496,13 @@ static const struct dis386 x86_64_table[][2] = { { Bad_Opcode }, { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, }, + + /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */ + { + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) }, + }, + }; static const struct dis386 three_byte_table[][256] = { @@ -4739,7 +4789,7 @@ static const struct dis386 three_byte_table[][256] = { { PREFIX_TABLE (PREFIX_0F38F6) }, { Bad_Opcode }, /* f8 */ - { PREFIX_TABLE (PREFIX_0F38F8) }, + { MOD_TABLE (MOD_0F38F8) }, { "movdiri", { Mdq, Gdq }, PREFIX_OPCODE }, { PREFIX_TABLE (PREFIX_0F38FA) }, { PREFIX_TABLE (PREFIX_0F38FB) }, @@ -7205,6 +7255,11 @@ static const struct dis386 vex_len_table[][2] = { { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) }, }, + /* VEX_LEN_MAP7_F8 */ + { + { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) }, + }, + /* VEX_LEN_XOP_08_85 */ { { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) }, @@ -7811,6 +7866,10 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3ADE */ { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) }, }, + { + /* VEX_W_MAP7_F8_L_0 */ + { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) }, + }, /* VEX_W_XOP_08_85_L_0 */ { { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 }, @@ -8153,6 +8212,11 @@ static const struct dis386 mod_table[][2] = { { "aesenc128kl", { XM, M }, 0 }, { "loadiwkey", { XM, EXx }, 0 }, }, + /* MOD_0F38F8 */ + { + { PREFIX_TABLE (PREFIX_0F38F8_M_0) }, + { X86_64_TABLE (X86_64_0F38F8_M_1) }, + }, { /* MOD_VEX_0F3849_X86_64_L_0_W_0 */ { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) }, @@ -8527,6 +8591,8 @@ static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; /* Fetch error indicator. */ static const struct dis386 err_opcode = { NULL, { XX }, 0 }; +static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) }; + /* Get a pointer to struct dis386 with a valid name. */ static const struct dis386 * @@ -8769,6 +8835,9 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) case 0x3: vex_table_index = VEX_0F3A; break; + case 0x7: + vex_table_index = VEX_MAP7; + break; } ins->codep++; ins->vex.w = *ins->codep & 0x80; @@ -8803,7 +8872,12 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) ins->need_vex = 3; ins->codep++; vindex = *ins->codep++; - dp = &vex_table[vex_table_index][vindex]; + if (vex_table_index == VEX_MAP7 && vindex == 0xf8) + { + dp = &map7_f8_opcode; + } + else + dp = &vex_table[vex_table_index][vindex]; ins->end_codep = ins->codep; /* There is no MODRM byte for VEX0F 77. */ if ((vex_table_index != VEX_0F || vindex != 0x77) @@ -9130,6 +9204,7 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) .last_rex_prefix = -1, .last_seg_prefix = -1, .fwait_prefix = -1, + .has_skipped_modrm = 0, }; char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE]; @@ -10017,7 +10092,11 @@ dofloat (instr_info *ins, int sizeflag) } /* Skip mod/rm byte. */ MODRM_CHECK; - ins->codep++; + if (!ins->has_skipped_modrm) + { + ins->codep++; + ins->has_skipped_modrm = true; + } dp = &float_reg[floatop - 0xd8][ins->modrm.reg]; if (dp->name == NULL) @@ -11299,7 +11378,11 @@ OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, /* Skip mod/rm byte. */ MODRM_CHECK; - ins->codep++; + if (!ins->has_skipped_modrm) + { + ins->codep++; + ins->has_skipped_modrm = true; + } return true; } @@ -11818,7 +11901,11 @@ OP_E (instr_info *ins, int bytemode, int sizeflag) { /* Skip mod/rm byte. */ MODRM_CHECK; - ins->codep++; + if (!ins->has_skipped_modrm) + { + ins->codep++; + ins->has_skipped_modrm = true; + } if (ins->modrm.mod == 3) { @@ -12522,7 +12609,11 @@ OP_EM (instr_info *ins, int bytemode, int sizeflag) /* Skip mod/rm byte. */ MODRM_CHECK; - ins->codep++; + if (!ins->has_skipped_modrm) + { + ins->codep++; + ins->has_skipped_modrm = true; + } ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); reg = ins->modrm.rm; if (ins->prefixes & PREFIX_DATA) @@ -12558,7 +12649,11 @@ OP_EMC (instr_info *ins, int bytemode, int sizeflag) /* Skip mod/rm byte. */ MODRM_CHECK; - ins->codep++; + if (!ins->has_skipped_modrm) + { + ins->codep++; + ins->has_skipped_modrm = true; + } ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); oappend_register (ins, att_names_mm[ins->modrm.rm]); return true; @@ -12580,7 +12675,11 @@ OP_EX (instr_info *ins, int bytemode, int sizeflag) /* Skip mod/rm byte. */ MODRM_CHECK; - ins->codep++; + if (!ins->has_skipped_modrm) + { + ins->codep++; + ins->has_skipped_modrm = true; + } if (bytemode == dq_mode) bytemode = ins->vex.w ? q_mode : d_mode; @@ -12623,9 +12722,10 @@ OP_R (instr_info *ins, int bytemode, int sizeflag) { case d_mode: case dq_mode: + case q_mode: case mask_mode: return OP_E (ins, bytemode, sizeflag); - case q_mode: + case q_mm_mode: return OP_EM (ins, x_mode, sizeflag); case xmm_mode: if (ins->vex.length <= 128) @@ -12641,7 +12741,11 @@ OP_M (instr_info *ins, int bytemode, int sizeflag) { /* Skip mod/rm byte. */ MODRM_CHECK; - ins->codep++; + if (!ins->has_skipped_modrm) + { + ins->codep++; + ins->has_skipped_modrm = true; + } if (ins->modrm.mod == 3) /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ @@ -12866,7 +12970,11 @@ OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) } /* Skip mod/rm byte. */ MODRM_CHECK; - ins->codep++; + if (!ins->has_skipped_modrm) + { + ins->codep++; + ins->has_skipped_modrm = true; + } return true; } @@ -12897,7 +13005,11 @@ OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, } /* Skip mod/rm byte. */ MODRM_CHECK; - ins->codep++; + if (!ins->has_skipped_modrm) + { + ins->codep++; + ins->has_skipped_modrm = true; + } return true; } diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index cfc5a7a6172..bb58afcbc06 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -380,6 +380,7 @@ static bitfield cpu_flags[] = BITFIELD (RAO_INT), BITFIELD (FRED), BITFIELD (LKGS), + BITFIELD (USER_MSR), BITFIELD (MWAITX), BITFIELD (CLZERO), BITFIELD (OSPKE), @@ -1023,6 +1024,7 @@ process_i386_opcode_modifier (FILE *table, char *mod, unsigned int space, SPACE(0F3A), SPACE(EVEXMAP5), SPACE(EVEXMAP6), + SPACE(VEXMAP7), SPACE(XOP08), SPACE(XOP09), SPACE(XOP0A), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 149ae0e950c..529eb7c41c8 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -223,6 +223,8 @@ enum i386_cpu CpuFRED, /* lkgs instruction required */ CpuLKGS, + /* Intel USER_MSR Instruction support required. */ + CpuUSER_MSR, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -471,6 +473,7 @@ typedef union i386_cpu_flags unsigned int cpurao_int:1; unsigned int cpufred:1; unsigned int cpulkgs:1; + unsigned int cpuuser_msr:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; @@ -966,6 +969,7 @@ typedef struct insn_template 3: 0F3A opcode prefix / space. 5: EVEXMAP5 opcode prefix / space. 6: EVEXMAP6 opcode prefix / space. + 7: VEXMAP7 opcode prefix / space. 8: XOP 08 opcode space. 9: XOP 09 opcode space. A: XOP 0A opcode space. @@ -976,6 +980,7 @@ typedef struct insn_template #define SPACE_0F3A 3 #define SPACE_EVEXMAP5 5 #define SPACE_EVEXMAP6 6 +#define SPACE_VEXMAP7 7 #define SPACE_XOP08 8 #define SPACE_XOP09 9 #define SPACE_XOP0A 0xA diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index e60184ba154..a3426298340 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -112,6 +112,8 @@ #define EVexMap5 OpcodeSpace=SPACE_EVEXMAP5 #define EVexMap6 OpcodeSpace=SPACE_EVEXMAP6 +#define VexMap7 OpcodeSpace=SPACE_VEXMAP7 + #define VexW0 VexW=VEXW0 #define VexW1 VexW=VEXW1 #define VexWIG VexW=VEXWIG @@ -3346,3 +3348,12 @@ erets, 0xf20f01ca, FRED|x64, NoSuf, {} eretu, 0xf30f01ca, FRED|x64, NoSuf, {} // FRED instructions end. + +// USER_MSR instructions. + +urdmsr, 0xf20f38f8, USER_MSR|x64, RegMem|NoSuf|NoRex64, { Reg64, Reg64 } +urdmsr, 0xf2f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 } +uwrmsr, 0xf30f38f8, USER_MSR|x64, Modrm|NoSuf|NoRex64, { Reg64, Reg64 } +uwrmsr, 0xf3f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Reg64, Imm32 } + +// USER_MSR instructions end. -- 2.31.1 ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH][v3] Support Intel USER_MSR 2023-10-25 9:11 ` [PATCH][v3] " Hu, Lin1 @ 2023-10-25 11:43 ` Jan Beulich 2023-10-26 6:14 ` Hu, Lin1 2023-10-26 6:21 ` [PATCH][v4] " Hu, Lin1 0 siblings, 2 replies; 33+ messages in thread From: Jan Beulich @ 2023-10-25 11:43 UTC (permalink / raw) To: Hu, Lin1; +Cc: hongjiu.lu, binutils On 25.10.2023 11:11, Hu, Lin1 wrote: > @@ -5235,6 +5237,17 @@ md_assemble (char *line) > if (i.imm_operands) This if() ... > optimize_imm (); > > + /* user_msr instructions can match Imm32 templates when > + guess_suffix == QWORD_MNEM_SUFFIX. */ > + if (t->mnem_off == MN_urdmsr) > + i.types[0] > + = operand_type_or (i.types[0], > + smallest_imm_type (i.op[0].imms->X_add_number)); > + if (t->mnem_off == MN_uwrmsr) > + i.types[1] > + = operand_type_or (i.types[1], > + smallest_imm_type (i.op[1].imms->X_add_number)); ... should now enclose all of these additions as well. Both for performance reasons (insns without immediates can skip the extra conditionals) and to avoid latent issues (i.op[].imms is not valid to de-reference without first checking [or knowing by implication] that the respective operand actually is an immediate; considering we're ahead of template matching, that'll need some further adjustment here anyway). But then the question is - do you actually need to go through optimize_imm() for these two insns? Or, worse, is it perhaps even wrong to do so? It looks at least latently risky to me. > @@ -7566,6 +7579,18 @@ match_template (char mnem_suffix) > break; > } > > + /* This pattern aims to put the unusually placed imm operand to a usual > + place. The constraints are currently only adapted to uwrmsr, and may > + need further tweaking when new similar instructions become available. */ > + if (i.operands > 0 > + && i.tm.operand_types[0].bitfield.class == Reg This part is needlessly strict. Altogether I'd suggest that you check that you have more than one operand, the last is an immediate (as you ... > + && operand_type_check (i.tm.operand_types[i.operands - 1], imm)) ... do already), and the first is not. Generated code wise the checks would likely be cheaper when done against the local variable operand_types[]. > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s > @@ -0,0 +1,31 @@ > +# Check 64bit USER_MSR instructions > + > + .allow_index_reg This doesn't look to have any meaning here. > + .text > +_start: > + urdmsr %r14, %r12 > + urdmsr %r14, %rax > + urdmsr %rdx, %r12 > + urdmsr %rdx, %rax > + urdmsr $51515151, %r12 > + urdmsr $51515151, %rax > + uwrmsr %r12, %r14 > + uwrmsr %rax, %r14 > + uwrmsr %r12, %rdx > + uwrmsr %rax, %rdx > + uwrmsr %r12, $51515151 > + uwrmsr %rax, $51515151 Considering the special handling of immediates, may I ask that you check further values. E.g. 0x7f, 0x7fff, and 0x80000000? It may further be worthwhile to have another testcase checking that out of range values (negative or too large) are properly rejected. > @@ -624,6 +629,8 @@ enum > d_swap_mode, > /* quad word operand */ > q_mode, > + /* 64-byte MM operand */ > + q_mm_mode, Byte or rather bit? > @@ -1240,6 +1252,7 @@ enum > X86_64_VEX_0F38ED, > X86_64_VEX_0F38EE, > X86_64_VEX_0F38EF, > + X86_64_VEX_MAP7_F8_L_0_W_0_R_0, > }; As you can observe from e.g. the change you're making here, ... > @@ -1259,7 +1272,8 @@ enum > { > VEX_0F = 0, > VEX_0F38, > - VEX_0F3A > + VEX_0F3A, > + VEX_MAP7 > }; ... it is beneficial to have a trailing comma in enumeration which may further be extended. > @@ -8803,7 +8872,12 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) > ins->need_vex = 3; > ins->codep++; > vindex = *ins->codep++; > - dp = &vex_table[vex_table_index][vindex]; > + if (vex_table_index == VEX_MAP7 && vindex == 0xf8) > + { > + dp = &map7_f8_opcode; > + } > + else > + dp = &vex_table[vex_table_index][vindex]; In the VEX_MAP7 case this is an out of bounds access now, isn't it? > @@ -9130,6 +9204,7 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) > .last_rex_prefix = -1, > .last_seg_prefix = -1, > .fwait_prefix = -1, > + .has_skipped_modrm = 0, > }; No need to add explicit initializers when the value is zero. Omitting the line also would save me from demanding that you use "false", not "0". > @@ -10017,7 +10092,11 @@ dofloat (instr_info *ins, int sizeflag) > } > /* Skip mod/rm byte. */ > MODRM_CHECK; > - ins->codep++; > + if (!ins->has_skipped_modrm) > + { > + ins->codep++; > + ins->has_skipped_modrm = true; > + } > > dp = &float_reg[floatop - 0xd8][ins->modrm.reg]; > if (dp->name == NULL) > @@ -11299,7 +11378,11 @@ OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, > > /* Skip mod/rm byte. */ > MODRM_CHECK; > - ins->codep++; > + if (!ins->has_skipped_modrm) > + { > + ins->codep++; > + ins->has_skipped_modrm = true; > + } > return true; > } > > @@ -11818,7 +11901,11 @@ OP_E (instr_info *ins, int bytemode, int sizeflag) > { > /* Skip mod/rm byte. */ > MODRM_CHECK; > - ins->codep++; > + if (!ins->has_skipped_modrm) > + { > + ins->codep++; > + ins->has_skipped_modrm = true; > + } > > if (ins->modrm.mod == 3) > { > @@ -12522,7 +12609,11 @@ OP_EM (instr_info *ins, int bytemode, int sizeflag) > > /* Skip mod/rm byte. */ > MODRM_CHECK; > - ins->codep++; > + if (!ins->has_skipped_modrm) > + { > + ins->codep++; > + ins->has_skipped_modrm = true; > + } > ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); > reg = ins->modrm.rm; > if (ins->prefixes & PREFIX_DATA) > @@ -12558,7 +12649,11 @@ OP_EMC (instr_info *ins, int bytemode, int sizeflag) > > /* Skip mod/rm byte. */ > MODRM_CHECK; > - ins->codep++; > + if (!ins->has_skipped_modrm) > + { > + ins->codep++; > + ins->has_skipped_modrm = true; > + } > ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); > oappend_register (ins, att_names_mm[ins->modrm.rm]); > return true; > @@ -12580,7 +12675,11 @@ OP_EX (instr_info *ins, int bytemode, int sizeflag) > > /* Skip mod/rm byte. */ > MODRM_CHECK; > - ins->codep++; > + if (!ins->has_skipped_modrm) > + { > + ins->codep++; > + ins->has_skipped_modrm = true; > + } > > if (bytemode == dq_mode) > bytemode = ins->vex.w ? q_mode : d_mode; Do you really need all of these adjustments? The only place I can see it's needed is ... > @@ -12623,9 +12722,10 @@ OP_R (instr_info *ins, int bytemode, int sizeflag) > { > case d_mode: > case dq_mode: > + case q_mode: > case mask_mode: > return OP_E (ins, bytemode, sizeflag); ... OP_E() for now. Otherwise, if you really want to do it uniformly, I think you'd want to fold this into MODRM_CHECK, such that the same code doesn't need repeating a whopping 9 times. Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH][v3] Support Intel USER_MSR 2023-10-25 11:43 ` Jan Beulich @ 2023-10-26 6:14 ` Hu, Lin1 2023-10-26 6:21 ` [PATCH][v4] " Hu, Lin1 1 sibling, 0 replies; 33+ messages in thread From: Hu, Lin1 @ 2023-10-26 6:14 UTC (permalink / raw) To: Beulich, Jan; +Cc: Lu, Hongjiu, binutils > -----Original Message----- > From: Jan Beulich <jbeulich@suse.com> > Sent: Wednesday, October 25, 2023 7:43 PM > To: Hu, Lin1 <lin1.hu@intel.com> > Cc: Lu, Hongjiu <hongjiu.lu@intel.com>; binutils@sourceware.org > Subject: Re: [PATCH][v3] Support Intel USER_MSR > > On 25.10.2023 11:11, Hu, Lin1 wrote: > > @@ -5235,6 +5237,17 @@ md_assemble (char *line) > > if (i.imm_operands) > > This if() ... > > > optimize_imm (); > > > > + /* user_msr instructions can match Imm32 templates when > > + guess_suffix == QWORD_MNEM_SUFFIX. */ > > + if (t->mnem_off == MN_urdmsr) > > + i.types[0] > > + = operand_type_or (i.types[0], > > + smallest_imm_type (i.op[0].imms->X_add_number)); > > + if (t->mnem_off == MN_uwrmsr) > > + i.types[1] > > + = operand_type_or (i.types[1], > > + smallest_imm_type (i.op[1].imms->X_add_number)); > > ... should now enclose all of these additions as well. Both for performance > reasons (insns without immediates can skip the extra > conditionals) and to avoid latent issues (i.op[].imms is not valid to de-reference > without first checking [or knowing by implication] that the respective operand > actually is an immediate; considering we're ahead of template matching, that'll > need some further adjustment here anyway). > > But then the question is - do you actually need to go through > optimize_imm() for these two insns? Or, worse, is it perhaps even wrong to do > so? It looks at least latently risky to me. > I am sorry for I didn't notice that current_template was a global variable, that part of the change has been removed by me, and the solution is now @@ -6371,8 +6371,11 @@ optimize_imm (void) smallest_imm_type (i.op[op].imms->X_add_number)); /* We must avoid matching of Imm32 templates when 64bit - only immediate is available. */ - if (guess_suffix == QWORD_MNEM_SUFFIX) + only immediate is available. user_msr instructions can + match Imm32 templates when guess_suffix == QWORD_MNEM_SUFFIX. + */ + if (guess_suffix == QWORD_MNEM_SUFFIX + && !is_cpu(current_templates->start, CpuUSER_MSR)) i.types[op].bitfield.imm32 = 0; break; Or you want USER_MSR not to go through optimize_imm(), I can extract the code that the USER_MSR should perform out of optimize_imm(). > > @@ -7566,6 +7579,18 @@ match_template (char mnem_suffix) > > break; > > } > > > > + /* This pattern aims to put the unusually placed imm operand to a usual > > + place. The constraints are currently only adapted to uwrmsr, and may > > + need further tweaking when new similar instructions become > > + available. */ if (i.operands > 0 > > + && i.tm.operand_types[0].bitfield.class == Reg > > This part is needlessly strict. Altogether I'd suggest that you check that you have > more than one operand, the last is an immediate (as you ... > > > + && operand_type_check (i.tm.operand_types[i.operands - 1], > > + imm)) > > ... do already), and the first is not. > > Generated code wise the checks would likely be cheaper when done against the > local variable operand_types[]. > OK, I have modified them. > > > --- /dev/null > > +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s > > @@ -0,0 +1,31 @@ > > +# Check 64bit USER_MSR instructions > > + > > + .allow_index_reg > > This doesn't look to have any meaning here. > > > + .text > > +_start: > > + urdmsr %r14, %r12 > > + urdmsr %r14, %rax > > + urdmsr %rdx, %r12 > > + urdmsr %rdx, %rax > > + urdmsr $51515151, %r12 > > + urdmsr $51515151, %rax > > + uwrmsr %r12, %r14 > > + uwrmsr %rax, %r14 > > + uwrmsr %r12, %rdx > > + uwrmsr %rax, %rdx > > + uwrmsr %r12, $51515151 > > + uwrmsr %rax, $51515151 > > Considering the special handling of immediates, may I ask that you check further > values. E.g. 0x7f, 0x7fff, and 0x80000000? It may further be worthwhile to have > another testcase checking that out of range values (negative or too large) are > properly rejected. > Ok, I have added some tests. > > > @@ -624,6 +629,8 @@ enum > > d_swap_mode, > > /* quad word operand */ > > q_mode, > > + /* 64-byte MM operand */ > > + q_mm_mode, > > Byte or rather bit? Oh, It's a mistake. > > > @@ -1240,6 +1252,7 @@ enum > > X86_64_VEX_0F38ED, > > X86_64_VEX_0F38EE, > > X86_64_VEX_0F38EF, > > + X86_64_VEX_MAP7_F8_L_0_W_0_R_0, > > }; > > As you can observe from e.g. the change you're making here, ... > > > @@ -1259,7 +1272,8 @@ enum > > { > > VEX_0F = 0, > > VEX_0F38, > > - VEX_0F3A > > + VEX_0F3A, > > + VEX_MAP7 > > }; > > ... it is beneficial to have a trailing comma in enumeration which may further be > extended. > OK. > > > @@ -8803,7 +8872,12 @@ get_valid_dis386 (const struct dis386 *dp, > instr_info *ins) > > ins->need_vex = 3; > > ins->codep++; > > vindex = *ins->codep++; > > - dp = &vex_table[vex_table_index][vindex]; > > + if (vex_table_index == VEX_MAP7 && vindex == 0xf8) > > + { > > + dp = &map7_f8_opcode; > > + } > > + else > > + dp = &vex_table[vex_table_index][vindex]; > > In the VEX_MAP7 case this is an out of bounds access now, isn't it? > Yes, you are right. > > > @@ -9130,6 +9204,7 @@ print_insn (bfd_vma pc, disassemble_info *info, int > intel_syntax) > > .last_rex_prefix = -1, > > .last_seg_prefix = -1, > > .fwait_prefix = -1, > > + .has_skipped_modrm = 0, > > }; > > No need to add explicit initializers when the value is zero. Omitting the line also > would save me from demanding that you use "false", not "0". > OK, I have removed the line. > > > @@ -10017,7 +10092,11 @@ dofloat (instr_info *ins, int sizeflag) > > } > > /* Skip mod/rm byte. */ > > MODRM_CHECK; > > - ins->codep++; > > + if (!ins->has_skipped_modrm) > > + { > > + ins->codep++; > > + ins->has_skipped_modrm = true; > > + } > > > > dp = &float_reg[floatop - 0xd8][ins->modrm.reg]; > > if (dp->name == NULL) > > @@ -11299,7 +11378,11 @@ OP_Skip_MODRM (instr_info *ins, int bytemode > > ATTRIBUTE_UNUSED, > > > > /* Skip mod/rm byte. */ > > MODRM_CHECK; > > - ins->codep++; > > + if (!ins->has_skipped_modrm) > > + { > > + ins->codep++; > > + ins->has_skipped_modrm = true; > > + } > > return true; > > } > > > > @@ -11818,7 +11901,11 @@ OP_E (instr_info *ins, int bytemode, int > > sizeflag) { > > /* Skip mod/rm byte. */ > > MODRM_CHECK; > > - ins->codep++; > > + if (!ins->has_skipped_modrm) > > + { > > + ins->codep++; > > + ins->has_skipped_modrm = true; > > + } > > > > if (ins->modrm.mod == 3) > > { > > @@ -12522,7 +12609,11 @@ OP_EM (instr_info *ins, int bytemode, int > > sizeflag) > > > > /* Skip mod/rm byte. */ > > MODRM_CHECK; > > - ins->codep++; > > + if (!ins->has_skipped_modrm) > > + { > > + ins->codep++; > > + ins->has_skipped_modrm = true; > > + } > > ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); > > reg = ins->modrm.rm; > > if (ins->prefixes & PREFIX_DATA) > > @@ -12558,7 +12649,11 @@ OP_EMC (instr_info *ins, int bytemode, int > > sizeflag) > > > > /* Skip mod/rm byte. */ > > MODRM_CHECK; > > - ins->codep++; > > + if (!ins->has_skipped_modrm) > > + { > > + ins->codep++; > > + ins->has_skipped_modrm = true; > > + } > > ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); > > oappend_register (ins, att_names_mm[ins->modrm.rm]); > > return true; > > @@ -12580,7 +12675,11 @@ OP_EX (instr_info *ins, int bytemode, int > > sizeflag) > > > > /* Skip mod/rm byte. */ > > MODRM_CHECK; > > - ins->codep++; > > + if (!ins->has_skipped_modrm) > > + { > > + ins->codep++; > > + ins->has_skipped_modrm = true; > > + } > > > > if (bytemode == dq_mode) > > bytemode = ins->vex.w ? q_mode : d_mode; > > Do you really need all of these adjustments? The only place I can see it's needed > is ... > > > @@ -12623,9 +12722,10 @@ OP_R (instr_info *ins, int bytemode, int sizeflag) > > { > > case d_mode: > > case dq_mode: > > + case q_mode: > > case mask_mode: > > return OP_E (ins, bytemode, sizeflag); > > ... OP_E() for now. Otherwise, if you really want to do it uniformly, I think you'd > want to fold this into MODRM_CHECK, such that the same code doesn't need > repeating a whopping 9 times. > Ok, I'm fine with both, in terms of saving time and lines of code, it's better to just add what's needed for now. > > Jan BRs, Lin ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH][v4] Support Intel USER_MSR 2023-10-25 11:43 ` Jan Beulich 2023-10-26 6:14 ` Hu, Lin1 @ 2023-10-26 6:21 ` Hu, Lin1 2023-10-26 8:31 ` Jan Beulich 1 sibling, 1 reply; 33+ messages in thread From: Hu, Lin1 @ 2023-10-26 6:21 UTC (permalink / raw) To: binutils; +Cc: JBeulich, hongjiu.lu gas/ChangeLog: * NEWS: Support Intel USER_MSR. * config/tc-i386.c: Add user_msr and add VEXMAP7 in opc_spc and build_vex_prefix. (build_modrm_byte): Swap Operands for USER_MSR. * doc/c-i386.texi: Document .user_msr. * testsuite/gas/i386/i386.exp: Run USER_MSR tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/user_msr-inval.l: New test. * testsuite/gas/i386/user_msr-inval.s: Ditto. * testsuite/gas/i386/x86-64-user_msr-intel.d: Ditto. * testsuite/gas/i386/x86-64-user_msr.d: Ditto. * testsuite/gas/i386/x86-64-user_msr.s: Ditto. opcodes/ChangeLog: * i386-dis.c (get32_operand0): Add a new function to get operand0 that is IMM32. (Gq): New. (Id0): Ditto. (get_valid_dis386): Add VEX_MAP7 in VEX prefix. (OP_I): Handle d_0_mode. (d_0_mode): New. (REG_VEX_MAP7_F8_L_0_W_0): New. (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64): Ditto. (X86_64_VEX_MAP7_F8_L_0_W_0_R_0): Ditto. (VEX_MAP7): Ditto. (VEX_LEN_MAP7_F8): Ditto. (VEX_W_MAP7_F8_L_0): Ditto. (MOD_0F38F8): Ditto. (PREFIX_0F38F8_M_0): Ditto. (PREFIX_0F38F8_M_1_X86_64): Ditto. (X86_64_0F38F8_M_1): Ditto. (PREFIX_0F38F8): Remove. (prefix_table): Add PREFIX_0F38F8_M_1_X86_64. Remove PREFIX_0F38F8. (reg_table): Add REG_VEX_MAP7_F8_L_0_W_0, PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64. (x86_64_table): Add X86_64_0F38F8_PREFIX_3_M_1, X86_64_VEX_MAP7_F8_L_0_W_0_R_0 and X86_64_0F38F8_M_1. (vex_table): Add VEX_MAP7. (vex_len_table): Add VEX_LEN_MAP7_F8, VEX_W_MAP7_F8_L_0. (mod_table): New entry for USER_MSR and add MOD_0F38F8. * i386-gen.c (cpu_flag_init): Add CPU_USER_MSR_FLAGS and CPU_ANY_USER_MSR_FLAGS. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (SPACE_VEXMAP7): New. (SWAP_SOURCE_DEST): Ditto. (CPU_USER_MSR_FLAGS): Ditoo. (CPU_ANY_USER_MSR_FLAGS): Ditto. (i386_cpu_flags): Add cpuuser_msr. * i386-opc.tbl: Add USER_MSR instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 2 + gas/config/tc-i386.c | 41 +- gas/doc/c-i386.texi | 3 +- gas/testsuite/gas/i386/i386.exp | 1 + gas/testsuite/gas/i386/user_msr-inval.l | 3 + gas/testsuite/gas/i386/user_msr-inval.s | 7 + .../gas/i386/x86-64-user_msr-intel.d | 46 + .../gas/i386/x86-64-user_msr-inval.l | 7 + .../gas/i386/x86-64-user_msr-inval.s | 11 + gas/testsuite/gas/i386/x86-64-user_msr.d | 46 + gas/testsuite/gas/i386/x86-64-user_msr.s | 43 + gas/testsuite/gas/i386/x86-64.exp | 3 + opcodes/i386-dis.c | 150 +- opcodes/i386-gen.c | 2 + opcodes/i386-opc.h | 5 + opcodes/i386-opc.tbl | 11 + 19 files changed, 1551 insertions(+), 1196 deletions(-) create mode 100644 gas/testsuite/gas/i386/user_msr-inval.l create mode 100644 gas/testsuite/gas/i386/user_msr-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr.d create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr.s diff --git a/gas/NEWS b/gas/NEWS index 71a1269b893..ab0e7813f27 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel USER_MSR instructions. + * Add support for Intel AVX10.1. * Add support for Intel PBNDKB instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 714354d5116..f1be117c4df 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1164,6 +1164,7 @@ static const arch_entry cpu_arch[] = VECARCH (sm4, SM4, ANY_SM4, reset), SUBARCH (pbndkb, PBNDKB, PBNDKB, false), VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set), + SUBARCH (user_msr, USER_MSR, USER_MSR, false), }; #undef SUBARCH @@ -2504,7 +2505,8 @@ smallest_imm_type (offsetT num) t.bitfield.imm8 = 1; t.bitfield.imm8s = 1; t.bitfield.imm16 = 1; - t.bitfield.imm32 = 1; + if (fits_in_unsigned_long (num)) + t.bitfield.imm32 = 1; t.bitfield.imm32s = 1; } else if (fits_in_unsigned_byte (num)) @@ -2517,12 +2519,14 @@ smallest_imm_type (offsetT num) else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) { t.bitfield.imm16 = 1; - t.bitfield.imm32 = 1; + if (fits_in_unsigned_long (num)) + t.bitfield.imm32 = 1; t.bitfield.imm32s = 1; } else if (fits_in_signed_long (num)) { - t.bitfield.imm32 = 1; + if (fits_in_unsigned_long (num)) + t.bitfield.imm32 = 1; t.bitfield.imm32s = 1; } else if (fits_in_unsigned_long (num)) @@ -3863,6 +3867,7 @@ build_vex_prefix (const insn_template *t) case SPACE_0F: case SPACE_0F38: case SPACE_0F3A: + case SPACE_VEXMAP7: i.vex.bytes[0] = 0xc4; break; case SPACE_XOP08: @@ -5235,6 +5240,17 @@ md_assemble (char *line) if (i.imm_operands) optimize_imm (); + /* user_msr instructions can match Imm32 templates when + guess_suffix == QWORD_MNEM_SUFFIX. */ + if (t->mnem_off == MN_urdmsr) + i.types[0] + = operand_type_or (i.types[0], + smallest_imm_type (i.op[0].imms->X_add_number)); + if (t->mnem_off == MN_uwrmsr) + i.types[1] + = operand_type_or (i.types[1], + smallest_imm_type (i.op[1].imms->X_add_number)); + if (i.disp_operands && !optimize_disp (t)) return; @@ -6358,8 +6374,11 @@ optimize_imm (void) smallest_imm_type (i.op[op].imms->X_add_number)); /* We must avoid matching of Imm32 templates when 64bit - only immediate is available. */ - if (guess_suffix == QWORD_MNEM_SUFFIX) + only immediate is available. user_msr instructions can + match Imm32 templates when guess_suffix == QWORD_MNEM_SUFFIX. + */ + if (guess_suffix == QWORD_MNEM_SUFFIX + && !is_cpu(current_templates->start, CpuUSER_MSR)) i.types[op].bitfield.imm32 = 0; break; @@ -7566,6 +7585,18 @@ match_template (char mnem_suffix) break; } + /* This pattern aims to put the unusually placed imm operand to a usual + place. The constraints are currently only adapted to uwrmsr, and may + need further tweaking when new similar instructions become available. */ + if (i.operands > 0 + && !operand_type_check (operand_types[0], imm) + && operand_type_check (operand_types[i.operands - 1], imm)) + { + i.tm.operand_types[0] = operand_types[i.operands - 1]; + i.tm.operand_types[i.operands - 1] = operand_types[0]; + swap_2_operands(0, i.operands - 1); + } + return t; } diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index b04e1b00b4b..03ee980bef7 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -216,6 +216,7 @@ accept various extension mnemonics. For example, @code{avx10.1/512}, @code{avx10.1/256}, @code{avx10.1/128}, +@code{user_msr}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1650,7 +1651,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} @item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs} @item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4} -@item @samp{.pbndkb} +@item @samp{.pbndkb} @tab @samp{.user_msr} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index ee74bcd4615..81ce1e38b10 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -509,6 +509,7 @@ if [gas_32_check] then { run_dump_test "sm4" run_dump_test "sm4-intel" run_list_test "pbndkb-inval" + run_list_test "user_msr-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" diff --git a/gas/testsuite/gas/i386/user_msr-inval.l b/gas/testsuite/gas/i386/user_msr-inval.l new file mode 100644 index 00000000000..9618645bea8 --- /dev/null +++ b/gas/testsuite/gas/i386/user_msr-inval.l @@ -0,0 +1,3 @@ +.* Assembler messages: +.*:6: Error: `urdmsr' is only supported in 64-bit mode +.*:7: Error: `uwrmsr' is only supported in 64-bit mode diff --git a/gas/testsuite/gas/i386/user_msr-inval.s b/gas/testsuite/gas/i386/user_msr-inval.s new file mode 100644 index 00000000000..3762e2bd7b9 --- /dev/null +++ b/gas/testsuite/gas/i386/user_msr-inval.s @@ -0,0 +1,7 @@ +# Check Illegal 32bit USER_MSR instructions + + .allow_index_reg + .text +_start: + urdmsr %r12, %r14 + uwrmsr %r12, %r14 diff --git a/gas/testsuite/gas/i386/x86-64-user_msr-intel.d b/gas/testsuite/gas/i386/x86-64-user_msr-intel.d new file mode 100644 index 00000000000..e68b5eacfa9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr-intel.d @@ -0,0 +1,46 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 USER_MSR insns (Intel disassembly) +#source: x86-64-user_msr.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr r12,r14 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr rax,r14 +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr r12,rdx +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr rax,rdx +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr r12,0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr rax,0x3120f0f +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 7f 00 00 00\s+urdmsr r12,0x7f +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 ff 7f 00 00\s+urdmsr r12,0x7fff +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 00 00 00 80\s+urdmsr r12,0x80000000 +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr r14,r12 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr r14,rax +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr rdx,r12 +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr rdx,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr 0x3120f0f,r12 +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr 0x3120f0f,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 7f 00 00 00\s+uwrmsr 0x7f,r12 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 ff 7f 00 00\s+uwrmsr 0x7fff,r12 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 00 00 00 80\s+uwrmsr 0x80000000,r12 +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr r12,r14 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr rax,r14 +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr r12,rdx +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr rax,rdx +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr r12,0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr rax,0x3120f0f +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 7f 00 00 00\s+urdmsr r12,0x7f +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 ff 7f 00 00\s+urdmsr r12,0x7fff +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 00 00 00 80\s+urdmsr r12,0x80000000 +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr r14,r12 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr r14,rax +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr rdx,r12 +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr rdx,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr 0x3120f0f,r12 +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr 0x3120f0f,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 7f 00 00 00\s+uwrmsr 0x7f,r12 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 ff 7f 00 00\s+uwrmsr 0x7fff,r12 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 00 00 00 80\s+uwrmsr 0x80000000,r12 diff --git a/gas/testsuite/gas/i386/x86-64-user_msr-inval.l b/gas/testsuite/gas/i386/x86-64-user_msr-inval.l new file mode 100644 index 00000000000..52e55e7f0c7 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr-inval.l @@ -0,0 +1,7 @@ +.* Assembler messages: +.*:6: Error: operand type mismatch for `urdmsr'. +.*:7: Error: operand type mismatch for `urdmsr'. +.*:8: Error: operand type mismatch for `urdmsr'. +.*:9: Error: operand type mismatch for `urdmsr'. +.*:10: Error: operand type mismatch for `uwrmsr'. +.*:11: Error: operand type mismatch for `uwrmsr'. diff --git a/gas/testsuite/gas/i386/x86-64-user_msr-inval.s b/gas/testsuite/gas/i386/x86-64-user_msr-inval.s new file mode 100644 index 00000000000..6aff469485b --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr-inval.s @@ -0,0 +1,11 @@ +# Check Illegal 64bit USER_MSR instructions + + .allow_index_reg + .text +_start: + urdmsr $-1, %r14 + urdmsr $-32767, %r14 + urdmsr $-2147483648, %r14 + urdmsr $0x7fffffffffffffff, %r14 + uwrmsr %r12, $-1 + uwrmsr %r12, $0x7fffffffffffffff diff --git a/gas/testsuite/gas/i386/x86-64-user_msr.d b/gas/testsuite/gas/i386/x86-64-user_msr.d new file mode 100644 index 00000000000..41f29718ab0 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr.d @@ -0,0 +1,46 @@ +#as: +#objdump: -dw +#name: x86_64 USER_MSR insns +#source: x86-64-user_msr.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr %r14,%r12 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr %r14,%rax +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr %rdx,%r12 +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr %rdx,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr \$0x3120f0f,%r12 +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr \$0x3120f0f,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 7f 00 00 00\s+urdmsr \$0x7f,%r12 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 ff 7f 00 00\s+urdmsr \$0x7fff,%r12 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 00 00 00 80\s+urdmsr \$0x80000000,%r12 +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr %r12,%r14 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr %rax,%r14 +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr %r12,%rdx +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr %rax,%rdx +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr %r12,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr %rax,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 7f 00 00 00\s+uwrmsr %r12,\$0x7f +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 ff 7f 00 00\s+uwrmsr %r12,\$0x7fff +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 00 00 00 80\s+uwrmsr %r12,\$0x80000000 +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr %r14,%r12 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr %r14,%rax +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr %rdx,%r12 +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr %rdx,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr \$0x3120f0f,%r12 +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr \$0x3120f0f,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 7f 00 00 00\s+urdmsr \$0x7f,%r12 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 ff 7f 00 00\s+urdmsr \$0x7fff,%r12 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 00 00 00 80\s+urdmsr \$0x80000000,%r12 +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr %r12,%r14 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr %rax,%r14 +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr %r12,%rdx +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr %rax,%rdx +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr %r12,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr %rax,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 7f 00 00 00\s+uwrmsr %r12,\$0x7f +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 ff 7f 00 00\s+uwrmsr %r12,\$0x7fff +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 00 00 00 80\s+uwrmsr %r12,\$0x80000000 diff --git a/gas/testsuite/gas/i386/x86-64-user_msr.s b/gas/testsuite/gas/i386/x86-64-user_msr.s new file mode 100644 index 00000000000..f06fd7187c9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s @@ -0,0 +1,43 @@ +# Check 64bit USER_MSR instructions + + .allow_index_reg + .text +_start: + urdmsr %r14, %r12 + urdmsr %r14, %rax + urdmsr %rdx, %r12 + urdmsr %rdx, %rax + urdmsr $51515151, %r12 + urdmsr $51515151, %rax + urdmsr $0x7f, %r12 + urdmsr $0x7fff, %r12 + urdmsr $0x80000000, %r12 + uwrmsr %r12, %r14 + uwrmsr %rax, %r14 + uwrmsr %r12, %rdx + uwrmsr %rax, %rdx + uwrmsr %r12, $51515151 + uwrmsr %rax, $51515151 + uwrmsr %r12, $0x7f + uwrmsr %r12, $0x7fff + uwrmsr %r12, $0x80000000 + + .intel_syntax noprefix + urdmsr r12, r14 + urdmsr rax, r14 + urdmsr r12, rdx + urdmsr rax, rdx + urdmsr r12, 51515151 + urdmsr rax, 51515151 + urdmsr r12, 0x7f + urdmsr r12, 0x7fff + urdmsr r12, 0x80000000 + uwrmsr r14, r12 + uwrmsr r14, rax + uwrmsr rdx, r12 + uwrmsr rdx, rax + uwrmsr 51515151, r12 + uwrmsr 51515151, rax + uwrmsr 0x7f, r12 + uwrmsr 0x7fff, r12 + uwrmsr 0x80000000, r12 diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 52711cdcf6f..22fdb0d9bcd 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -450,6 +450,9 @@ run_dump_test "x86-64-sm4" run_dump_test "x86-64-sm4-intel" run_dump_test "x86-64-pbndkb" run_dump_test "x86-64-pbndkb-intel" +run_dump_test "x86-64-user_msr" +run_dump_test "x86-64-user_msr-intel" +run_list_test "x86-64-user_msr-inval" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 87ecf0f5e23..e4daa454b07 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -221,6 +221,9 @@ struct instr_info /* Record whether EVEX masking is used incorrectly. */ bool illegal_masking; + /* Record whether the modrm byte has been skipped. */ + bool has_skipped_modrm; + unsigned char op_ad; signed char op_index[MAX_OPERANDS]; bool op_riprel[MAX_OPERANDS]; @@ -418,6 +421,7 @@ fetch_error (const instr_info *ins) #define Gv { OP_G, v_mode } #define Gd { OP_G, d_mode } #define Gdq { OP_G, dq_mode } +#define Gq { OP_G, q_mode } #define Gm { OP_G, m_mode } #define Gva { OP_G, va_mode } #define Gw { OP_G, w_mode } @@ -527,7 +531,8 @@ fetch_error (const instr_info *ins) #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } #define Rd { OP_R, d_mode } #define Rdq { OP_R, dq_mode } -#define Nq { OP_R, q_mode } +#define Rq { OP_R, q_mode } +#define Nq { OP_R, q_mm_mode } #define Ux { OP_R, x_mode } #define Uxmm { OP_R, xmm_mode } #define Rxmmq { OP_R, xmmq_mode } @@ -624,6 +629,8 @@ enum d_swap_mode, /* quad word operand */ q_mode, + /* 8-byte MM operand */ + q_mm_mode, /* quad word operand with operand swapped */ q_swap_mode, /* ten-byte operand */ @@ -845,6 +852,7 @@ enum REG_VEX_0FAE, REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0, REG_VEX_0F38F3_L_0, + REG_VEX_MAP7_F8_L_0_W_0, REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, @@ -893,6 +901,7 @@ enum MOD_0FC7_REG_6, MOD_0FC7_REG_7, MOD_0F38DC_PREFIX_1, + MOD_0F38F8, MOD_VEX_0F3849_X86_64_L_0_W_0, }; @@ -1010,7 +1019,8 @@ enum PREFIX_0F38F0, PREFIX_0F38F1, PREFIX_0F38F6, - PREFIX_0F38F8, + PREFIX_0F38F8_M_0, + PREFIX_0F38F8_M_1_X86_64, PREFIX_0F38FA, PREFIX_0F38FB, PREFIX_0F38FC, @@ -1073,6 +1083,7 @@ enum PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0, PREFIX_VEX_0F3AF0_L_0, + PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F6F, @@ -1217,6 +1228,7 @@ enum X86_64_0F18_REG_7_MOD_0, X86_64_0F24, X86_64_0F26, + X86_64_0F38F8_M_1, X86_64_0FC7_REG_6_MOD_3_PREFIX_1, X86_64_VEX_0F3849, @@ -1240,6 +1252,7 @@ enum X86_64_VEX_0F38ED, X86_64_VEX_0F38EE, X86_64_VEX_0F38EF, + X86_64_VEX_MAP7_F8_L_0_W_0_R_0, }; enum @@ -1259,7 +1272,8 @@ enum { VEX_0F = 0, VEX_0F38, - VEX_0F3A + VEX_0F3A, + VEX_MAP7, }; enum @@ -1350,6 +1364,7 @@ enum VEX_LEN_0F3ADE_W_0, VEX_LEN_0F3ADF, VEX_LEN_0F3AF0, + VEX_LEN_MAP7_F8, VEX_LEN_XOP_08_85, VEX_LEN_XOP_08_86, VEX_LEN_XOP_08_87, @@ -1510,6 +1525,7 @@ enum VEX_W_0F3ACE, VEX_W_0F3ACF, VEX_W_0F3ADE, + VEX_W_MAP7_F8_L_0, VEX_W_XOP_08_85_L_0, VEX_W_XOP_08_86_L_0, @@ -2849,6 +2865,10 @@ static const struct dis386 reg_table[][8] = { { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE }, { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE }, }, + /* REG_VEX_MAP7_F8_L_0_W_0 */ + { + { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) }, + }, /* REG_XOP_09_01_L_0 */ { { Bad_Opcode }, @@ -3555,13 +3575,22 @@ static const struct dis386 prefix_table[][4] = { { Bad_Opcode }, }, - /* PREFIX_0F38F8 */ + /* PREFIX_0F38F8_M_0 */ { { Bad_Opcode }, { "enqcmds", { Gva, M }, 0 }, { "movdir64b", { Gva, M }, 0 }, { "enqcmd", { Gva, M }, 0 }, }, + + /* PREFIX_0F38F8_M_1_X86_64 */ + { + { Bad_Opcode }, + { "uwrmsr", { Gq, Rq }, 0 }, + { Bad_Opcode }, + { "urdmsr", { Rq, Gq }, 0 }, + }, + /* PREFIX_0F38FA */ { { Bad_Opcode }, @@ -4014,6 +4043,14 @@ static const struct dis386 prefix_table[][4] = { { "rorxS", { Gdq, Edq, Ib }, 0 }, }, + /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */ + { + { Bad_Opcode }, + { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 }, + { Bad_Opcode }, + { "urdmsr", { Rq, Id }, 0 }, + }, + #include "i386-dis-evex-prefix.h" }; @@ -4322,6 +4359,12 @@ static const struct dis386 x86_64_table[][2] = { { "movZ", { Td, Em }, 0 }, }, + { + /* X86_64_0F38F8_M_1 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) }, + }, + /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */ { { Bad_Opcode }, @@ -4453,6 +4496,13 @@ static const struct dis386 x86_64_table[][2] = { { Bad_Opcode }, { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, }, + + /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */ + { + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) }, + }, + }; static const struct dis386 three_byte_table[][256] = { @@ -4739,7 +4789,7 @@ static const struct dis386 three_byte_table[][256] = { { PREFIX_TABLE (PREFIX_0F38F6) }, { Bad_Opcode }, /* f8 */ - { PREFIX_TABLE (PREFIX_0F38F8) }, + { MOD_TABLE (MOD_0F38F8) }, { "movdiri", { Mdq, Gdq }, PREFIX_OPCODE }, { PREFIX_TABLE (PREFIX_0F38FA) }, { PREFIX_TABLE (PREFIX_0F38FB) }, @@ -7205,6 +7255,11 @@ static const struct dis386 vex_len_table[][2] = { { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) }, }, + /* VEX_LEN_MAP7_F8 */ + { + { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) }, + }, + /* VEX_LEN_XOP_08_85 */ { { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) }, @@ -7811,6 +7866,10 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3ADE */ { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) }, }, + { + /* VEX_W_MAP7_F8_L_0 */ + { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) }, + }, /* VEX_W_XOP_08_85_L_0 */ { { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 }, @@ -8153,6 +8212,11 @@ static const struct dis386 mod_table[][2] = { { "aesenc128kl", { XM, M }, 0 }, { "loadiwkey", { XM, EXx }, 0 }, }, + /* MOD_0F38F8 */ + { + { PREFIX_TABLE (PREFIX_0F38F8_M_0) }, + { X86_64_TABLE (X86_64_0F38F8_M_1) }, + }, { /* MOD_VEX_0F3849_X86_64_L_0_W_0 */ { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) }, @@ -8527,6 +8591,8 @@ static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; /* Fetch error indicator. */ static const struct dis386 err_opcode = { NULL, { XX }, 0 }; +static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) }; + /* Get a pointer to struct dis386 with a valid name. */ static const struct dis386 * @@ -8769,6 +8835,9 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) case 0x3: vex_table_index = VEX_0F3A; break; + case 0x7: + vex_table_index = VEX_MAP7; + break; } ins->codep++; ins->vex.w = *ins->codep & 0x80; @@ -8803,7 +8872,15 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) ins->need_vex = 3; ins->codep++; vindex = *ins->codep++; - dp = &vex_table[vex_table_index][vindex]; + if (vex_table_index == VEX_MAP7) + { + if (vindex == 0xf8) + dp = &map7_f8_opcode; + else + dp = &bad_opcode; + } + else + dp = &vex_table[vex_table_index][vindex]; ins->end_codep = ins->codep; /* There is no MODRM byte for VEX0F 77. */ if ((vex_table_index != VEX_0F || vindex != 0x77) @@ -11299,7 +11376,11 @@ OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, /* Skip mod/rm byte. */ MODRM_CHECK; - ins->codep++; + if (!ins->has_skipped_modrm) + { + ins->codep++; + ins->has_skipped_modrm = true; + } return true; } @@ -11818,7 +11899,11 @@ OP_E (instr_info *ins, int bytemode, int sizeflag) { /* Skip mod/rm byte. */ MODRM_CHECK; - ins->codep++; + if (!ins->has_skipped_modrm) + { + ins->codep++; + ins->has_skipped_modrm = true; + } if (ins->modrm.mod == 3) { @@ -12623,9 +12708,10 @@ OP_R (instr_info *ins, int bytemode, int sizeflag) { case d_mode: case dq_mode: + case q_mode: case mask_mode: return OP_E (ins, bytemode, sizeflag); - case q_mode: + case q_mm_mode: return OP_EM (ins, x_mode, sizeflag); case xmm_mode: if (ins->vex.length <= 128) diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index cfc5a7a6172..bb58afcbc06 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -380,6 +380,7 @@ static bitfield cpu_flags[] = BITFIELD (RAO_INT), BITFIELD (FRED), BITFIELD (LKGS), + BITFIELD (USER_MSR), BITFIELD (MWAITX), BITFIELD (CLZERO), BITFIELD (OSPKE), @@ -1023,6 +1024,7 @@ process_i386_opcode_modifier (FILE *table, char *mod, unsigned int space, SPACE(0F3A), SPACE(EVEXMAP5), SPACE(EVEXMAP6), + SPACE(VEXMAP7), SPACE(XOP08), SPACE(XOP09), SPACE(XOP0A), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 149ae0e950c..529eb7c41c8 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -223,6 +223,8 @@ enum i386_cpu CpuFRED, /* lkgs instruction required */ CpuLKGS, + /* Intel USER_MSR Instruction support required. */ + CpuUSER_MSR, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -471,6 +473,7 @@ typedef union i386_cpu_flags unsigned int cpurao_int:1; unsigned int cpufred:1; unsigned int cpulkgs:1; + unsigned int cpuuser_msr:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; @@ -966,6 +969,7 @@ typedef struct insn_template 3: 0F3A opcode prefix / space. 5: EVEXMAP5 opcode prefix / space. 6: EVEXMAP6 opcode prefix / space. + 7: VEXMAP7 opcode prefix / space. 8: XOP 08 opcode space. 9: XOP 09 opcode space. A: XOP 0A opcode space. @@ -976,6 +980,7 @@ typedef struct insn_template #define SPACE_0F3A 3 #define SPACE_EVEXMAP5 5 #define SPACE_EVEXMAP6 6 +#define SPACE_VEXMAP7 7 #define SPACE_XOP08 8 #define SPACE_XOP09 9 #define SPACE_XOP0A 0xA diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index e60184ba154..a3426298340 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -112,6 +112,8 @@ #define EVexMap5 OpcodeSpace=SPACE_EVEXMAP5 #define EVexMap6 OpcodeSpace=SPACE_EVEXMAP6 +#define VexMap7 OpcodeSpace=SPACE_VEXMAP7 + #define VexW0 VexW=VEXW0 #define VexW1 VexW=VEXW1 #define VexWIG VexW=VEXWIG @@ -3346,3 +3348,12 @@ erets, 0xf20f01ca, FRED|x64, NoSuf, {} eretu, 0xf30f01ca, FRED|x64, NoSuf, {} // FRED instructions end. + +// USER_MSR instructions. + +urdmsr, 0xf20f38f8, USER_MSR|x64, RegMem|NoSuf|NoRex64, { Reg64, Reg64 } +urdmsr, 0xf2f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 } +uwrmsr, 0xf30f38f8, USER_MSR|x64, Modrm|NoSuf|NoRex64, { Reg64, Reg64 } +uwrmsr, 0xf3f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Reg64, Imm32 } + +// USER_MSR instructions end. -- 2.31.1 ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH][v4] Support Intel USER_MSR 2023-10-26 6:21 ` [PATCH][v4] " Hu, Lin1 @ 2023-10-26 8:31 ` Jan Beulich 2023-10-26 9:08 ` Hu, Lin1 0 siblings, 1 reply; 33+ messages in thread From: Jan Beulich @ 2023-10-26 8:31 UTC (permalink / raw) To: Hu, Lin1; +Cc: hongjiu.lu, binutils On 26.10.2023 08:21, Hu, Lin1 wrote: > @@ -2504,7 +2505,8 @@ smallest_imm_type (offsetT num) > t.bitfield.imm8 = 1; > t.bitfield.imm8s = 1; > t.bitfield.imm16 = 1; > - t.bitfield.imm32 = 1; > + if (fits_in_unsigned_long (num)) > + t.bitfield.imm32 = 1; > t.bitfield.imm32s = 1; > } I fear this isn't correct for 32-bit code, where all immediates are deemed fitting in both 32-bit signed and unsigned. Otoh you surely ran the testsuite, and I would have expected mistakes here to be covered by at least one testcase. > @@ -2517,12 +2519,14 @@ smallest_imm_type (offsetT num) > else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) > { > t.bitfield.imm16 = 1; > - t.bitfield.imm32 = 1; > + if (fits_in_unsigned_long (num)) > + t.bitfield.imm32 = 1; > t.bitfield.imm32s = 1; > } > else if (fits_in_signed_long (num)) > { > - t.bitfield.imm32 = 1; > + if (fits_in_unsigned_long (num)) > + t.bitfield.imm32 = 1; > t.bitfield.imm32s = 1; > } Same issue here then, if any. > @@ -5235,6 +5240,17 @@ md_assemble (char *line) > if (i.imm_operands) > optimize_imm (); > > + /* user_msr instructions can match Imm32 templates when > + guess_suffix == QWORD_MNEM_SUFFIX. */ > + if (t->mnem_off == MN_urdmsr) > + i.types[0] > + = operand_type_or (i.types[0], > + smallest_imm_type (i.op[0].imms->X_add_number)); > + if (t->mnem_off == MN_uwrmsr) > + i.types[1] > + = operand_type_or (i.types[1], > + smallest_imm_type (i.op[1].imms->X_add_number)); My respective comment on v3 was left entirely unaddressed? > @@ -6358,8 +6374,11 @@ optimize_imm (void) > smallest_imm_type (i.op[op].imms->X_add_number)); > > /* We must avoid matching of Imm32 templates when 64bit > - only immediate is available. */ > - if (guess_suffix == QWORD_MNEM_SUFFIX) > + only immediate is available. user_msr instructions can > + match Imm32 templates when guess_suffix == QWORD_MNEM_SUFFIX. > + */ > + if (guess_suffix == QWORD_MNEM_SUFFIX > + && !is_cpu(current_templates->start, CpuUSER_MSR)) > i.types[op].bitfield.imm32 = 0; > break; Taking together the changes you make to smallest_imm_type() and the change you make here, I guess - to come back to an earlier comment of yours - it would be less risky if these changes were omitted and the new insns instead bypassed optimize_imm(), as suggested before as an alternative. > @@ -7566,6 +7585,18 @@ match_template (char mnem_suffix) > break; > } > > + /* This pattern aims to put the unusually placed imm operand to a usual > + place. The constraints are currently only adapted to uwrmsr, and may > + need further tweaking when new similar instructions become available. */ > + if (i.operands > 0 As said in reply to v3, can this please be "> 1"? There's no need to ... > + && !operand_type_check (operand_types[0], imm) > + && operand_type_check (operand_types[i.operands - 1], imm)) ... rely on the combination of these two conditions to never be true when i.operands == 1. Thinking about it, since operand_type_check() may - depending on what exact code the compiler generates - be comparibly expensive, how about if (i.imm_operands > 0 && i.imm_operands < i.operands && operand_type_check (operand_types[i.operands - 1], imm)) instead? > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-user_msr-inval.l > @@ -0,0 +1,7 @@ > +.* Assembler messages: > +.*:6: Error: operand type mismatch for `urdmsr'. > +.*:7: Error: operand type mismatch for `urdmsr'. > +.*:8: Error: operand type mismatch for `urdmsr'. > +.*:9: Error: operand type mismatch for `urdmsr'. > +.*:10: Error: operand type mismatch for `uwrmsr'. > +.*:11: Error: operand type mismatch for `uwrmsr'. > diff --git a/gas/testsuite/gas/i386/x86-64-user_msr-inval.s b/gas/testsuite/gas/i386/x86-64-user_msr-inval.s > new file mode 100644 > index 00000000000..6aff469485b > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-user_msr-inval.s > @@ -0,0 +1,11 @@ > +# Check Illegal 64bit USER_MSR instructions > + > + .allow_index_reg Yet another instance of this when it's not needed? > --- /dev/null > +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s > @@ -0,0 +1,43 @@ > +# Check 64bit USER_MSR instructions > + > + .allow_index_reg Iirc I did ask to remove this, for being meaningless here. Please uniformly remove this from all the new tests introduced here. > @@ -8803,7 +8872,15 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) > ins->need_vex = 3; > ins->codep++; > vindex = *ins->codep++; > - dp = &vex_table[vex_table_index][vindex]; > + if (vex_table_index == VEX_MAP7) > + { > + if (vindex == 0xf8) > + dp = &map7_f8_opcode; > + else > + dp = &bad_opcode; > + } > + else > + dp = &vex_table[vex_table_index][vindex]; How about if (vex_table_index != VEX_MAP7) dp = &vex_table[vex_table_index][vindex]; else if (vindex == 0xf8) dp = &map7_f8_opcode; else dp = &bad_opcode; (i.e. common case first and overall less indentation)? > @@ -11299,7 +11376,11 @@ OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, > > /* Skip mod/rm byte. */ > MODRM_CHECK; > - ins->codep++; > + if (!ins->has_skipped_modrm) > + { > + ins->codep++; > + ins->has_skipped_modrm = true; > + } > return true; > } I understand you need to set has_skipped_modrm here, but does this need to be conditional? Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH][v4] Support Intel USER_MSR 2023-10-26 8:31 ` Jan Beulich @ 2023-10-26 9:08 ` Hu, Lin1 2023-10-26 9:25 ` Jan Beulich 0 siblings, 1 reply; 33+ messages in thread From: Hu, Lin1 @ 2023-10-26 9:08 UTC (permalink / raw) To: Beulich, Jan; +Cc: Lu, Hongjiu, binutils > -----Original Message----- > From: Jan Beulich <jbeulich@suse.com> > Sent: Thursday, October 26, 2023 4:31 PM > To: Hu, Lin1 <lin1.hu@intel.com> > Cc: Lu, Hongjiu <hongjiu.lu@intel.com>; binutils@sourceware.org > Subject: Re: [PATCH][v4] Support Intel USER_MSR > > On 26.10.2023 08:21, Hu, Lin1 wrote: > > @@ -2504,7 +2505,8 @@ smallest_imm_type (offsetT num) > > t.bitfield.imm8 = 1; > > t.bitfield.imm8s = 1; > > t.bitfield.imm16 = 1; > > - t.bitfield.imm32 = 1; > > + if (fits_in_unsigned_long (num)) > > + t.bitfield.imm32 = 1; > > t.bitfield.imm32s = 1; > > } > > I fear this isn't correct for 32-bit code, where all immediates are deemed fitting > in both 32-bit signed and unsigned. Otoh you surely ran the testsuite, and I > would have expected mistakes here to be covered by at least one testcase. > OK, so we might need special handling in places for cases where the operand of a USER_MSR instruction is negative, do you have a suggestion for where this should be handled, after match_template()? PS. This part of change is for raise error when user input urdmsr $-1, %r14. > > > @@ -2517,12 +2519,14 @@ smallest_imm_type (offsetT num) > > else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) > > { > > t.bitfield.imm16 = 1; > > - t.bitfield.imm32 = 1; > > + if (fits_in_unsigned_long (num)) > > + t.bitfield.imm32 = 1; > > t.bitfield.imm32s = 1; > > } > > else if (fits_in_signed_long (num)) > > { > > - t.bitfield.imm32 = 1; > > + if (fits_in_unsigned_long (num)) > > + t.bitfield.imm32 = 1; > > t.bitfield.imm32s = 1; > > } > > Same issue here then, if any. > > > @@ -5235,6 +5240,17 @@ md_assemble (char *line) > > if (i.imm_operands) > > optimize_imm (); > > > > + /* user_msr instructions can match Imm32 templates when > > + guess_suffix == QWORD_MNEM_SUFFIX. */ > > + if (t->mnem_off == MN_urdmsr) > > + i.types[0] > > + = operand_type_or (i.types[0], > > + smallest_imm_type (i.op[0].imms->X_add_number)); > > + if (t->mnem_off == MN_uwrmsr) > > + i.types[1] > > + = operand_type_or (i.types[1], > > + smallest_imm_type (i.op[1].imms->X_add_number)); > > My respective comment on v3 was left entirely unaddressed? > It's a mistake, I forget to remove the part of the code. > > > @@ -6358,8 +6374,11 @@ optimize_imm (void) > > smallest_imm_type (i.op[op].imms- > >X_add_number)); > > > > /* We must avoid matching of Imm32 templates when 64bit > > - only immediate is available. */ > > - if (guess_suffix == QWORD_MNEM_SUFFIX) > > + only immediate is available. user_msr instructions can > > + match Imm32 templates when guess_suffix == > QWORD_MNEM_SUFFIX. > > + */ > > + if (guess_suffix == QWORD_MNEM_SUFFIX > > + && !is_cpu(current_templates->start, CpuUSER_MSR)) > > i.types[op].bitfield.imm32 = 0; > > break; > > Taking together the changes you make to smallest_imm_type() and the change > you make here, I guess - to come back to an earlier comment of yours - it would > be less risky if these changes were omitted and the new insns instead bypassed > optimize_imm(), as suggested before as an alternative. For solve the problem of Imm32, I just need theses change without smallest_imm_type(). I want to make sure I'm not misunderstanding. For solving the Imm32 problem, do you mean you prefer if (i.imm_operands) { if (is_cpu(current_templates->start, CpuUSER_MSR)) { for (op == i.operands; --op >= 0;) { if (operand_type_check (i.types[op], imm)) { i.types[op] = operand_type_or (i.types[op], smallest_imm_type (i.op[op].imms->X_add_number)); } } } else optimize_imm(); } This part of the code is currently just a prototype. > > > > @@ -7566,6 +7585,18 @@ match_template (char mnem_suffix) > > break; > > } > > > > + /* This pattern aims to put the unusually placed imm operand to a usual > > + place. The constraints are currently only adapted to uwrmsr, and may > > + need further tweaking when new similar instructions become > > + available. */ if (i.operands > 0 > > As said in reply to v3, can this please be "> 1"? There's no need to ... > > > + && !operand_type_check (operand_types[0], imm) > > + && operand_type_check (operand_types[i.operands - 1], imm)) > > ... rely on the combination of these two conditions to never be true when > i.operands == 1. > > Thinking about it, since operand_type_check() may - depending on what exact > code the compiler generates - be comparibly expensive, how about > > if (i.imm_operands > 0 && i.imm_operands < i.operands > && operand_type_check (operand_types[i.operands - 1], imm)) > > instead? > OK, thanks for your suggestion. > > > --- /dev/null > > +++ b/gas/testsuite/gas/i386/x86-64-user_msr-inval.l > > @@ -0,0 +1,7 @@ > > +.* Assembler messages: > > +.*:6: Error: operand type mismatch for `urdmsr'. > > +.*:7: Error: operand type mismatch for `urdmsr'. > > +.*:8: Error: operand type mismatch for `urdmsr'. > > +.*:9: Error: operand type mismatch for `urdmsr'. > > +.*:10: Error: operand type mismatch for `uwrmsr'. > > +.*:11: Error: operand type mismatch for `uwrmsr'. > > diff --git a/gas/testsuite/gas/i386/x86-64-user_msr-inval.s > > b/gas/testsuite/gas/i386/x86-64-user_msr-inval.s > > new file mode 100644 > > index 00000000000..6aff469485b > > --- /dev/null > > +++ b/gas/testsuite/gas/i386/x86-64-user_msr-inval.s > > @@ -0,0 +1,11 @@ > > +# Check Illegal 64bit USER_MSR instructions > > + > > + .allow_index_reg > > Yet another instance of this when it's not needed? > Since it looked to me like they were denied for the same reason, I'll add them。 > > > --- /dev/null > > +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s > > @@ -0,0 +1,43 @@ > > +# Check 64bit USER_MSR instructions > > + > > + .allow_index_reg > > Iirc I did ask to remove this, for being meaningless here. Please uniformly > remove this from all the new tests introduced here. > OK, I have removed them. > > @@ -8803,7 +8872,15 @@ get_valid_dis386 (const struct dis386 *dp, > instr_info *ins) > > ins->need_vex = 3; > > ins->codep++; > > vindex = *ins->codep++; > > - dp = &vex_table[vex_table_index][vindex]; > > + if (vex_table_index == VEX_MAP7) > > + { > > + if (vindex == 0xf8) > > + dp = &map7_f8_opcode; > > + else > > + dp = &bad_opcode; > > + } > > + else > > + dp = &vex_table[vex_table_index][vindex]; > > How about > > if (vex_table_index != VEX_MAP7) > dp = &vex_table[vex_table_index][vindex]; > else if (vindex == 0xf8) > dp = &map7_f8_opcode; > else > dp = &bad_opcode; > > (i.e. common case first and overall less indentation)? > Yes, it looks great. > > > @@ -11299,7 +11376,11 @@ OP_Skip_MODRM (instr_info *ins, int bytemode > > ATTRIBUTE_UNUSED, > > > > /* Skip mod/rm byte. */ > > MODRM_CHECK; > > - ins->codep++; > > + if (!ins->has_skipped_modrm) > > + { > > + ins->codep++; > > + ins->has_skipped_modrm = true; > > + } > > return true; > > } > > I understand you need to set has_skipped_modrm here, but does this need to be > conditional? > I just tend to keep them in line. I have remove the condition. BRs, Lin ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH][v4] Support Intel USER_MSR 2023-10-26 9:08 ` Hu, Lin1 @ 2023-10-26 9:25 ` Jan Beulich 2023-10-26 10:26 ` Hu, Lin1 2023-10-27 9:00 ` [PATCH][v5] " Hu, Lin1 0 siblings, 2 replies; 33+ messages in thread From: Jan Beulich @ 2023-10-26 9:25 UTC (permalink / raw) To: Hu, Lin1; +Cc: Lu, Hongjiu, binutils On 26.10.2023 11:08, Hu, Lin1 wrote: >> -----Original Message----- >> From: Jan Beulich <jbeulich@suse.com> >> Sent: Thursday, October 26, 2023 4:31 PM >> >> On 26.10.2023 08:21, Hu, Lin1 wrote: >>> @@ -2504,7 +2505,8 @@ smallest_imm_type (offsetT num) >>> t.bitfield.imm8 = 1; >>> t.bitfield.imm8s = 1; >>> t.bitfield.imm16 = 1; >>> - t.bitfield.imm32 = 1; >>> + if (fits_in_unsigned_long (num)) >>> + t.bitfield.imm32 = 1; >>> t.bitfield.imm32s = 1; >>> } >> >> I fear this isn't correct for 32-bit code, where all immediates are deemed fitting >> in both 32-bit signed and unsigned. Otoh you surely ran the testsuite, and I >> would have expected mistakes here to be covered by at least one testcase. >> > > OK, so we might need special handling in places for cases where the operand of a USER_MSR instruction is negative, do you have a suggestion for where this should be handled, after match_template()? > > PS. This part of change is for raise error when user input urdmsr $-1, %r14. Hmm, I realize even when avoiding optimize_imm() you still need to have smallest_imm_type() capable of dealing with the case. That's fine, the logic shouldn't be put elsewhere (which would only make things yet less manageable). But outside of 64-bit code I think you want to set .imm32 without consulting fits_in_unsigned_long(). >>> @@ -6358,8 +6374,11 @@ optimize_imm (void) >>> smallest_imm_type (i.op[op].imms- >>> X_add_number)); >>> >>> /* We must avoid matching of Imm32 templates when 64bit >>> - only immediate is available. */ >>> - if (guess_suffix == QWORD_MNEM_SUFFIX) >>> + only immediate is available. user_msr instructions can >>> + match Imm32 templates when guess_suffix == >> QWORD_MNEM_SUFFIX. >>> + */ >>> + if (guess_suffix == QWORD_MNEM_SUFFIX >>> + && !is_cpu(current_templates->start, CpuUSER_MSR)) >>> i.types[op].bitfield.imm32 = 0; >>> break; >> >> Taking together the changes you make to smallest_imm_type() and the change >> you make here, I guess - to come back to an earlier comment of yours - it would >> be less risky if these changes were omitted and the new insns instead bypassed >> optimize_imm(), as suggested before as an alternative. > > For solve the problem of Imm32, I just need theses change without smallest_imm_type(). > > I want to make sure I'm not misunderstanding. For solving the Imm32 problem, do you mean you prefer > > if (i.imm_operands) > { > if (is_cpu(current_templates->start, CpuUSER_MSR)) > { > for (op == i.operands; --op >= 0;) > { > if (operand_type_check (i.types[op], imm)) > { > i.types[op] = operand_type_or (i.types[op], > smallest_imm_type (i.op[op].imms->X_add_number)); > } > } > } > else > optimize_imm(); > } > > This part of the code is currently just a prototype. Along these lines (and with a suitable comment), yes. I'm not sure, btw, whether you really need operand_type_or(); I seems to me that you could assign the return value directly to i.types[op]. But I may be overlooking some particular case ... >>> --- /dev/null >>> +++ b/gas/testsuite/gas/i386/x86-64-user_msr-inval.s >>> @@ -0,0 +1,11 @@ >>> +# Check Illegal 64bit USER_MSR instructions >>> + >>> + .allow_index_reg >> >> Yet another instance of this when it's not needed? >> > > Since it looked to me like they were denied for the same reason, I'll add them。 Why do you say "add" here, ... >>> --- /dev/null >>> +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s >>> @@ -0,0 +1,43 @@ >>> +# Check 64bit USER_MSR instructions >>> + >>> + .allow_index_reg >> >> Iirc I did ask to remove this, for being meaningless here. Please uniformly >> remove this from all the new tests introduced here. >> > > OK, I have removed them. ... when here you say you removed them? Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH][v4] Support Intel USER_MSR 2023-10-26 9:25 ` Jan Beulich @ 2023-10-26 10:26 ` Hu, Lin1 2023-10-27 9:00 ` [PATCH][v5] " Hu, Lin1 1 sibling, 0 replies; 33+ messages in thread From: Hu, Lin1 @ 2023-10-26 10:26 UTC (permalink / raw) To: Beulich, Jan; +Cc: Lu, Hongjiu, binutils > On 26.10.2023 11:08, Hu, Lin1 wrote: > >> -----Original Message----- > >> From: Jan Beulich <jbeulich@suse.com> > >> Sent: Thursday, October 26, 2023 4:31 PM > >>> @@ -6358,8 +6374,11 @@ optimize_imm (void) > >>> smallest_imm_type (i.op[op].imms- > X_add_number)); > >>> > >>> /* We must avoid matching of Imm32 templates when 64bit > >>> - only immediate is available. */ > >>> - if (guess_suffix == QWORD_MNEM_SUFFIX) > >>> + only immediate is available. user_msr instructions can > >>> + match Imm32 templates when guess_suffix == > >> QWORD_MNEM_SUFFIX. > >>> + */ > >>> + if (guess_suffix == QWORD_MNEM_SUFFIX > >>> + && !is_cpu(current_templates->start, CpuUSER_MSR)) > >>> i.types[op].bitfield.imm32 = 0; > >>> break; > >> > >> Taking together the changes you make to smallest_imm_type() and the > >> change you make here, I guess - to come back to an earlier comment of > >> yours - it would be less risky if these changes were omitted and the > >> new insns instead bypassed optimize_imm(), as suggested before as an > alternative. > > > > For solve the problem of Imm32, I just need theses change without > smallest_imm_type(). > > > > I want to make sure I'm not misunderstanding. For solving the Imm32 > > problem, do you mean you prefer > > > > if (i.imm_operands) > > { > > if (is_cpu(current_templates->start, CpuUSER_MSR)) > > { > > for (op == i.operands; --op >= 0;) > > { > > if (operand_type_check (i.types[op], imm)) > > { > > i.types[op] = operand_type_or (i.types[op], > > smallest_imm_type (i.op[op].imms- > >X_add_number)); > > } > > } > > } > > else > > optimize_imm(); > > } > > > > This part of the code is currently just a prototype. > > Along these lines (and with a suitable comment), yes. I'm not sure, btw, whether > you really need operand_type_or(); I seems to me that you could assign the > return value directly to i.types[op]. But I may be overlooking some particular > case ... > I will try. I simply mimicked that part. > > >>> --- /dev/null > >>> +++ b/gas/testsuite/gas/i386/x86-64-user_msr-inval.s > >>> @@ -0,0 +1,11 @@ > >>> +# Check Illegal 64bit USER_MSR instructions > >>> + > >>> + .allow_index_reg > >> > >> Yet another instance of this when it's not needed? > >> > > > > Since it looked to me like they were denied for the same reason, I'll > > add them。 > > Why do you say "add" here, ... > > >>> --- /dev/null > >>> +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s > >>> @@ -0,0 +1,43 @@ > >>> +# Check 64bit USER_MSR instructions > >>> + > >>> + .allow_index_reg > >> > >> Iirc I did ask to remove this, for being meaningless here. Please > >> uniformly remove this from all the new tests introduced here. > >> > > > > OK, I have removed them. > > ... when here you say you removed them? > I misunderstood, I thought you were saying I was missing the test for uwrmsr %r14, $-1 and so on. I added some test about uwrmsr %r12, $-1, uwrmsr %r12, $-32767. And removed all .allow_index_reg. At least it turned out right in the end. > > Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH][v5] Support Intel USER_MSR 2023-10-26 9:25 ` Jan Beulich 2023-10-26 10:26 ` Hu, Lin1 @ 2023-10-27 9:00 ` Hu, Lin1 2023-10-27 13:36 ` Jan Beulich 1 sibling, 1 reply; 33+ messages in thread From: Hu, Lin1 @ 2023-10-27 9:00 UTC (permalink / raw) To: binutils; +Cc: JBeulich, hongjiu.lu In the previous email, I entered a wrong message ID, so just resend the patch to make sure they are in the same thread. gas/ChangeLog: * NEWS: Support Intel USER_MSR. * config/tc-i386.c: Add user_msr and add VEXMAP7 in opc_spc and build_vex_prefix. (build_modrm_byte): Swap Operands for USER_MSR. * doc/c-i386.texi: Document .user_msr. * testsuite/gas/i386/i386.exp: Run USER_MSR tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/user_msr-inval.l: New test. * testsuite/gas/i386/user_msr-inval.s: Ditto. * testsuite/gas/i386/x86-64-user_msr-intel.d: Ditto. * testsuite/gas/i386/x86-64-user_msr.d: Ditto. * testsuite/gas/i386/x86-64-user_msr.s: Ditto. opcodes/ChangeLog: * i386-dis.c (get32_operand0): Add a new function to get operand0 that is IMM32. (Gq): New. (Id0): Ditto. (get_valid_dis386): Add VEX_MAP7 in VEX prefix. (OP_I): Handle d_0_mode. (d_0_mode): New. (REG_VEX_MAP7_F8_L_0_W_0): New. (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64): Ditto. (X86_64_VEX_MAP7_F8_L_0_W_0_R_0): Ditto. (VEX_MAP7): Ditto. (VEX_LEN_MAP7_F8): Ditto. (VEX_W_MAP7_F8_L_0): Ditto. (MOD_0F38F8): Ditto. (PREFIX_0F38F8_M_0): Ditto. (PREFIX_0F38F8_M_1_X86_64): Ditto. (X86_64_0F38F8_M_1): Ditto. (PREFIX_0F38F8): Remove. (prefix_table): Add PREFIX_0F38F8_M_1_X86_64. Remove PREFIX_0F38F8. (reg_table): Add REG_VEX_MAP7_F8_L_0_W_0, PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64. (x86_64_table): Add X86_64_0F38F8_PREFIX_3_M_1, X86_64_VEX_MAP7_F8_L_0_W_0_R_0 and X86_64_0F38F8_M_1. (vex_table): Add VEX_MAP7. (vex_len_table): Add VEX_LEN_MAP7_F8, VEX_W_MAP7_F8_L_0. (mod_table): New entry for USER_MSR and add MOD_0F38F8. * i386-gen.c (cpu_flag_init): Add CPU_USER_MSR_FLAGS and CPU_ANY_USER_MSR_FLAGS. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (SPACE_VEXMAP7): New. (SWAP_SOURCE_DEST): Ditto. (CPU_USER_MSR_FLAGS): Ditoo. (CPU_ANY_USER_MSR_FLAGS): Ditto. (i386_cpu_flags): Add cpuuser_msr. * i386-opc.tbl: Add USER_MSR instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 2 + gas/config/tc-i386.c | 46 +- gas/doc/c-i386.texi | 3 +- gas/testsuite/gas/i386/i386.exp | 1 + gas/testsuite/gas/i386/user_msr-inval.l | 3 + gas/testsuite/gas/i386/user_msr-inval.s | 6 + .../gas/i386/x86-64-user_msr-intel.d | 46 + .../gas/i386/x86-64-user_msr-inval.l | 9 + .../gas/i386/x86-64-user_msr-inval.s | 12 + gas/testsuite/gas/i386/x86-64-user_msr.d | 46 + gas/testsuite/gas/i386/x86-64-user_msr.s | 42 + gas/testsuite/gas/i386/x86-64.exp | 3 + opcodes/i386-dis.c | 96 +- opcodes/i386-gen.c | 2 + opcodes/i386-init.h | 816 +++++------ opcodes/i386-mnem.h | 1278 +++++++++-------- opcodes/i386-opc.h | 5 + opcodes/i386-opc.tbl | 11 + opcodes/i386-tbl.h | 272 ++-- 19 files changed, 1528 insertions(+), 1171 deletions(-) create mode 100644 gas/testsuite/gas/i386/user_msr-inval.l create mode 100644 gas/testsuite/gas/i386/user_msr-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr.d create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr.s diff --git a/gas/NEWS b/gas/NEWS index 71a1269b893..ab0e7813f27 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel USER_MSR instructions. + * Add support for Intel AVX10.1. * Add support for Intel PBNDKB instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 714354d5116..2cf0ffc3608 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1164,6 +1164,7 @@ static const arch_entry cpu_arch[] = VECARCH (sm4, SM4, ANY_SM4, reset), SUBARCH (pbndkb, PBNDKB, PBNDKB, false), VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set), + SUBARCH (user_msr, USER_MSR, USER_MSR, false), }; #undef SUBARCH @@ -2504,7 +2505,10 @@ smallest_imm_type (offsetT num) t.bitfield.imm8 = 1; t.bitfield.imm8s = 1; t.bitfield.imm16 = 1; - t.bitfield.imm32 = 1; + if (flag_code != CODE_64BIT) + t.bitfield.imm32 = 1; + else if (fits_in_unsigned_long (num)) + t.bitfield.imm32 = 1; t.bitfield.imm32s = 1; } else if (fits_in_unsigned_byte (num)) @@ -2517,12 +2521,18 @@ smallest_imm_type (offsetT num) else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) { t.bitfield.imm16 = 1; - t.bitfield.imm32 = 1; + if (flag_code != CODE_64BIT) + t.bitfield.imm32 = 1; + else if (fits_in_unsigned_long (num)) + t.bitfield.imm32 = 1; t.bitfield.imm32s = 1; } else if (fits_in_signed_long (num)) { - t.bitfield.imm32 = 1; + if (flag_code != CODE_64BIT) + t.bitfield.imm32 = 1; + else if (fits_in_unsigned_long (num)) + t.bitfield.imm32 = 1; t.bitfield.imm32s = 1; } else if (fits_in_unsigned_long (num)) @@ -3863,6 +3873,7 @@ build_vex_prefix (const insn_template *t) case SPACE_0F: case SPACE_0F38: case SPACE_0F3A: + case SPACE_VEXMAP7: i.vex.bytes[0] = 0xc4; break; case SPACE_XOP08: @@ -5158,6 +5169,7 @@ md_assemble (char *line) const char *end, *pass1_mnem = NULL; enum i386_error pass1_err = 0; const insn_template *t; + int op; /* Initialize globals. */ current_templates = NULL; @@ -5232,8 +5244,23 @@ md_assemble (char *line) && (t->mnem_off == MN_extrq || t->mnem_off == MN_insertq)) swap_2_operands (0, 1); + /* For USER_MSR instructions, imm32 stands for the name of an model specific + register (MSR). So we need to avoid set i.types[op].bitfield.imm32 = 0, + when guess_suffix == QWORD_MNEM_SUFFIX. For time-saving reasons, + we specialize the USER_MSR and make only the necessary judgments. */ if (i.imm_operands) - optimize_imm (); + { + if (!is_cpu(current_templates->start, CpuUSER_MSR)) + optimize_imm (); + else + { + for (op = i.operands; --op >= 0;) + { + if (operand_type_check(i.types[op], imm)) + i.types[op] = smallest_imm_type (i.op[op].imms->X_add_number); + } + } + } if (i.disp_operands && !optimize_disp (t)) return; @@ -7566,6 +7593,17 @@ match_template (char mnem_suffix) break; } + /* This pattern aims to put the unusually placed imm operand to a usual + place. The constraints are currently only adapted to uwrmsr, and may + need further tweaking when new similar instructions become available. */ + if (i.imm_operands && i.imm_operands < i.operands + && operand_type_check (operand_types[i.operands - 1], imm)) + { + i.tm.operand_types[0] = operand_types[i.operands - 1]; + i.tm.operand_types[i.operands - 1] = operand_types[0]; + swap_2_operands(0, i.operands - 1); + } + return t; } diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index b04e1b00b4b..03ee980bef7 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -216,6 +216,7 @@ accept various extension mnemonics. For example, @code{avx10.1/512}, @code{avx10.1/256}, @code{avx10.1/128}, +@code{user_msr}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1650,7 +1651,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} @item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs} @item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4} -@item @samp{.pbndkb} +@item @samp{.pbndkb} @tab @samp{.user_msr} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index ee74bcd4615..81ce1e38b10 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -509,6 +509,7 @@ if [gas_32_check] then { run_dump_test "sm4" run_dump_test "sm4-intel" run_list_test "pbndkb-inval" + run_list_test "user_msr-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" diff --git a/gas/testsuite/gas/i386/user_msr-inval.l b/gas/testsuite/gas/i386/user_msr-inval.l new file mode 100644 index 00000000000..54c48f1953b --- /dev/null +++ b/gas/testsuite/gas/i386/user_msr-inval.l @@ -0,0 +1,3 @@ +.* Assembler messages: +.*:5: Error: `urdmsr' is only supported in 64-bit mode +.*:6: Error: `uwrmsr' is only supported in 64-bit mode diff --git a/gas/testsuite/gas/i386/user_msr-inval.s b/gas/testsuite/gas/i386/user_msr-inval.s new file mode 100644 index 00000000000..1682a1e8d79 --- /dev/null +++ b/gas/testsuite/gas/i386/user_msr-inval.s @@ -0,0 +1,6 @@ +# Check Illegal 32bit USER_MSR instructions + + .text +_start: + urdmsr %r12, %r14 + uwrmsr %r12, %r14 diff --git a/gas/testsuite/gas/i386/x86-64-user_msr-intel.d b/gas/testsuite/gas/i386/x86-64-user_msr-intel.d new file mode 100644 index 00000000000..e68b5eacfa9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr-intel.d @@ -0,0 +1,46 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 USER_MSR insns (Intel disassembly) +#source: x86-64-user_msr.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr r12,r14 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr rax,r14 +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr r12,rdx +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr rax,rdx +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr r12,0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr rax,0x3120f0f +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 7f 00 00 00\s+urdmsr r12,0x7f +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 ff 7f 00 00\s+urdmsr r12,0x7fff +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 00 00 00 80\s+urdmsr r12,0x80000000 +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr r14,r12 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr r14,rax +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr rdx,r12 +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr rdx,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr 0x3120f0f,r12 +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr 0x3120f0f,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 7f 00 00 00\s+uwrmsr 0x7f,r12 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 ff 7f 00 00\s+uwrmsr 0x7fff,r12 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 00 00 00 80\s+uwrmsr 0x80000000,r12 +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr r12,r14 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr rax,r14 +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr r12,rdx +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr rax,rdx +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr r12,0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr rax,0x3120f0f +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 7f 00 00 00\s+urdmsr r12,0x7f +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 ff 7f 00 00\s+urdmsr r12,0x7fff +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 00 00 00 80\s+urdmsr r12,0x80000000 +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr r14,r12 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr r14,rax +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr rdx,r12 +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr rdx,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr 0x3120f0f,r12 +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr 0x3120f0f,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 7f 00 00 00\s+uwrmsr 0x7f,r12 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 ff 7f 00 00\s+uwrmsr 0x7fff,r12 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 00 00 00 80\s+uwrmsr 0x80000000,r12 diff --git a/gas/testsuite/gas/i386/x86-64-user_msr-inval.l b/gas/testsuite/gas/i386/x86-64-user_msr-inval.l new file mode 100644 index 00000000000..9eb3044e16e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr-inval.l @@ -0,0 +1,9 @@ +.* Assembler messages: +.*:5: Error: operand type mismatch for `urdmsr' +.*:6: Error: operand type mismatch for `urdmsr' +.*:7: Error: operand type mismatch for `urdmsr' +.*:8: Error: operand type mismatch for `urdmsr' +.*:9: Error: operand type mismatch for `uwrmsr' +.*:10: Error: operand type mismatch for `uwrmsr' +.*:11: Error: operand type mismatch for `uwrmsr' +.*:12: Error: operand type mismatch for `uwrmsr' diff --git a/gas/testsuite/gas/i386/x86-64-user_msr-inval.s b/gas/testsuite/gas/i386/x86-64-user_msr-inval.s new file mode 100644 index 00000000000..e7b6d6eea83 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr-inval.s @@ -0,0 +1,12 @@ +# Check Illegal 64bit USER_MSR instructions + + .text +_start: + urdmsr $-1, %r14 + urdmsr $-32767, %r14 + urdmsr $-2147483648, %r14 + urdmsr $0x7fffffffffffffff, %r14 + uwrmsr %r12, $-1 + uwrmsr %r12, $-32767 + uwrmsr %r12, $-2147483648 + uwrmsr %r12, $0x7fffffffffffffff diff --git a/gas/testsuite/gas/i386/x86-64-user_msr.d b/gas/testsuite/gas/i386/x86-64-user_msr.d new file mode 100644 index 00000000000..41f29718ab0 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr.d @@ -0,0 +1,46 @@ +#as: +#objdump: -dw +#name: x86_64 USER_MSR insns +#source: x86-64-user_msr.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr %r14,%r12 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr %r14,%rax +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr %rdx,%r12 +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr %rdx,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr \$0x3120f0f,%r12 +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr \$0x3120f0f,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 7f 00 00 00\s+urdmsr \$0x7f,%r12 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 ff 7f 00 00\s+urdmsr \$0x7fff,%r12 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 00 00 00 80\s+urdmsr \$0x80000000,%r12 +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr %r12,%r14 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr %rax,%r14 +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr %r12,%rdx +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr %rax,%rdx +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr %r12,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr %rax,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 7f 00 00 00\s+uwrmsr %r12,\$0x7f +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 ff 7f 00 00\s+uwrmsr %r12,\$0x7fff +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 00 00 00 80\s+uwrmsr %r12,\$0x80000000 +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr %r14,%r12 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr %r14,%rax +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr %rdx,%r12 +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr %rdx,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr \$0x3120f0f,%r12 +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr \$0x3120f0f,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 7f 00 00 00\s+urdmsr \$0x7f,%r12 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 ff 7f 00 00\s+urdmsr \$0x7fff,%r12 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 00 00 00 80\s+urdmsr \$0x80000000,%r12 +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr %r12,%r14 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr %rax,%r14 +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr %r12,%rdx +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr %rax,%rdx +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr %r12,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr %rax,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 7f 00 00 00\s+uwrmsr %r12,\$0x7f +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 ff 7f 00 00\s+uwrmsr %r12,\$0x7fff +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 00 00 00 80\s+uwrmsr %r12,\$0x80000000 diff --git a/gas/testsuite/gas/i386/x86-64-user_msr.s b/gas/testsuite/gas/i386/x86-64-user_msr.s new file mode 100644 index 00000000000..63bc6c1352c --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s @@ -0,0 +1,42 @@ +# Check 64bit USER_MSR instructions + + .text +_start: + urdmsr %r14, %r12 + urdmsr %r14, %rax + urdmsr %rdx, %r12 + urdmsr %rdx, %rax + urdmsr $51515151, %r12 + urdmsr $51515151, %rax + urdmsr $0x7f, %r12 + urdmsr $0x7fff, %r12 + urdmsr $0x80000000, %r12 + uwrmsr %r12, %r14 + uwrmsr %rax, %r14 + uwrmsr %r12, %rdx + uwrmsr %rax, %rdx + uwrmsr %r12, $51515151 + uwrmsr %rax, $51515151 + uwrmsr %r12, $0x7f + uwrmsr %r12, $0x7fff + uwrmsr %r12, $0x80000000 + + .intel_syntax noprefix + urdmsr r12, r14 + urdmsr rax, r14 + urdmsr r12, rdx + urdmsr rax, rdx + urdmsr r12, 51515151 + urdmsr rax, 51515151 + urdmsr r12, 0x7f + urdmsr r12, 0x7fff + urdmsr r12, 0x80000000 + uwrmsr r14, r12 + uwrmsr r14, rax + uwrmsr rdx, r12 + uwrmsr rdx, rax + uwrmsr 51515151, r12 + uwrmsr 51515151, rax + uwrmsr 0x7f, r12 + uwrmsr 0x7fff, r12 + uwrmsr 0x80000000, r12 diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 52711cdcf6f..22fdb0d9bcd 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -450,6 +450,9 @@ run_dump_test "x86-64-sm4" run_dump_test "x86-64-sm4-intel" run_dump_test "x86-64-pbndkb" run_dump_test "x86-64-pbndkb-intel" +run_dump_test "x86-64-user_msr" +run_dump_test "x86-64-user_msr-intel" +run_list_test "x86-64-user_msr-inval" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 87ecf0f5e23..2e2043d467b 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -221,6 +221,9 @@ struct instr_info /* Record whether EVEX masking is used incorrectly. */ bool illegal_masking; + /* Record whether the modrm byte has been skipped. */ + bool has_skipped_modrm; + unsigned char op_ad; signed char op_index[MAX_OPERANDS]; bool op_riprel[MAX_OPERANDS]; @@ -418,6 +421,7 @@ fetch_error (const instr_info *ins) #define Gv { OP_G, v_mode } #define Gd { OP_G, d_mode } #define Gdq { OP_G, dq_mode } +#define Gq { OP_G, q_mode } #define Gm { OP_G, m_mode } #define Gva { OP_G, va_mode } #define Gw { OP_G, w_mode } @@ -527,7 +531,8 @@ fetch_error (const instr_info *ins) #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } #define Rd { OP_R, d_mode } #define Rdq { OP_R, dq_mode } -#define Nq { OP_R, q_mode } +#define Rq { OP_R, q_mode } +#define Nq { OP_R, q_mm_mode } #define Ux { OP_R, x_mode } #define Uxmm { OP_R, xmm_mode } #define Rxmmq { OP_R, xmmq_mode } @@ -624,6 +629,8 @@ enum d_swap_mode, /* quad word operand */ q_mode, + /* 8-byte MM operand */ + q_mm_mode, /* quad word operand with operand swapped */ q_swap_mode, /* ten-byte operand */ @@ -845,6 +852,7 @@ enum REG_VEX_0FAE, REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0, REG_VEX_0F38F3_L_0, + REG_VEX_MAP7_F8_L_0_W_0, REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, @@ -893,6 +901,7 @@ enum MOD_0FC7_REG_6, MOD_0FC7_REG_7, MOD_0F38DC_PREFIX_1, + MOD_0F38F8, MOD_VEX_0F3849_X86_64_L_0_W_0, }; @@ -1010,7 +1019,8 @@ enum PREFIX_0F38F0, PREFIX_0F38F1, PREFIX_0F38F6, - PREFIX_0F38F8, + PREFIX_0F38F8_M_0, + PREFIX_0F38F8_M_1_X86_64, PREFIX_0F38FA, PREFIX_0F38FB, PREFIX_0F38FC, @@ -1073,6 +1083,7 @@ enum PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0, PREFIX_VEX_0F3AF0_L_0, + PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F6F, @@ -1217,6 +1228,7 @@ enum X86_64_0F18_REG_7_MOD_0, X86_64_0F24, X86_64_0F26, + X86_64_0F38F8_M_1, X86_64_0FC7_REG_6_MOD_3_PREFIX_1, X86_64_VEX_0F3849, @@ -1240,6 +1252,7 @@ enum X86_64_VEX_0F38ED, X86_64_VEX_0F38EE, X86_64_VEX_0F38EF, + X86_64_VEX_MAP7_F8_L_0_W_0_R_0, }; enum @@ -1259,7 +1272,8 @@ enum { VEX_0F = 0, VEX_0F38, - VEX_0F3A + VEX_0F3A, + VEX_MAP7, }; enum @@ -1350,6 +1364,7 @@ enum VEX_LEN_0F3ADE_W_0, VEX_LEN_0F3ADF, VEX_LEN_0F3AF0, + VEX_LEN_MAP7_F8, VEX_LEN_XOP_08_85, VEX_LEN_XOP_08_86, VEX_LEN_XOP_08_87, @@ -1510,6 +1525,7 @@ enum VEX_W_0F3ACE, VEX_W_0F3ACF, VEX_W_0F3ADE, + VEX_W_MAP7_F8_L_0, VEX_W_XOP_08_85_L_0, VEX_W_XOP_08_86_L_0, @@ -2849,6 +2865,10 @@ static const struct dis386 reg_table[][8] = { { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE }, { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE }, }, + /* REG_VEX_MAP7_F8_L_0_W_0 */ + { + { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) }, + }, /* REG_XOP_09_01_L_0 */ { { Bad_Opcode }, @@ -3555,13 +3575,22 @@ static const struct dis386 prefix_table[][4] = { { Bad_Opcode }, }, - /* PREFIX_0F38F8 */ + /* PREFIX_0F38F8_M_0 */ { { Bad_Opcode }, { "enqcmds", { Gva, M }, 0 }, { "movdir64b", { Gva, M }, 0 }, { "enqcmd", { Gva, M }, 0 }, }, + + /* PREFIX_0F38F8_M_1_X86_64 */ + { + { Bad_Opcode }, + { "uwrmsr", { Gq, Rq }, 0 }, + { Bad_Opcode }, + { "urdmsr", { Rq, Gq }, 0 }, + }, + /* PREFIX_0F38FA */ { { Bad_Opcode }, @@ -4014,6 +4043,14 @@ static const struct dis386 prefix_table[][4] = { { "rorxS", { Gdq, Edq, Ib }, 0 }, }, + /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */ + { + { Bad_Opcode }, + { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 }, + { Bad_Opcode }, + { "urdmsr", { Rq, Id }, 0 }, + }, + #include "i386-dis-evex-prefix.h" }; @@ -4322,6 +4359,12 @@ static const struct dis386 x86_64_table[][2] = { { "movZ", { Td, Em }, 0 }, }, + { + /* X86_64_0F38F8_M_1 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) }, + }, + /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */ { { Bad_Opcode }, @@ -4453,6 +4496,13 @@ static const struct dis386 x86_64_table[][2] = { { Bad_Opcode }, { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, }, + + /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */ + { + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) }, + }, + }; static const struct dis386 three_byte_table[][256] = { @@ -4739,7 +4789,7 @@ static const struct dis386 three_byte_table[][256] = { { PREFIX_TABLE (PREFIX_0F38F6) }, { Bad_Opcode }, /* f8 */ - { PREFIX_TABLE (PREFIX_0F38F8) }, + { MOD_TABLE (MOD_0F38F8) }, { "movdiri", { Mdq, Gdq }, PREFIX_OPCODE }, { PREFIX_TABLE (PREFIX_0F38FA) }, { PREFIX_TABLE (PREFIX_0F38FB) }, @@ -7205,6 +7255,11 @@ static const struct dis386 vex_len_table[][2] = { { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) }, }, + /* VEX_LEN_MAP7_F8 */ + { + { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) }, + }, + /* VEX_LEN_XOP_08_85 */ { { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) }, @@ -7811,6 +7866,10 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3ADE */ { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) }, }, + { + /* VEX_W_MAP7_F8_L_0 */ + { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) }, + }, /* VEX_W_XOP_08_85_L_0 */ { { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 }, @@ -8153,6 +8212,11 @@ static const struct dis386 mod_table[][2] = { { "aesenc128kl", { XM, M }, 0 }, { "loadiwkey", { XM, EXx }, 0 }, }, + /* MOD_0F38F8 */ + { + { PREFIX_TABLE (PREFIX_0F38F8_M_0) }, + { X86_64_TABLE (X86_64_0F38F8_M_1) }, + }, { /* MOD_VEX_0F3849_X86_64_L_0_W_0 */ { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) }, @@ -8527,6 +8591,8 @@ static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; /* Fetch error indicator. */ static const struct dis386 err_opcode = { NULL, { XX }, 0 }; +static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) }; + /* Get a pointer to struct dis386 with a valid name. */ static const struct dis386 * @@ -8769,6 +8835,9 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) case 0x3: vex_table_index = VEX_0F3A; break; + case 0x7: + vex_table_index = VEX_MAP7; + break; } ins->codep++; ins->vex.w = *ins->codep & 0x80; @@ -8803,7 +8872,12 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) ins->need_vex = 3; ins->codep++; vindex = *ins->codep++; - dp = &vex_table[vex_table_index][vindex]; + if (vex_table_index != VEX_MAP7) + dp = &vex_table[vex_table_index][vindex]; + else if (vindex == 0xf8) + dp = &map7_f8_opcode; + else + dp = &bad_opcode; ins->end_codep = ins->codep; /* There is no MODRM byte for VEX0F 77. */ if ((vex_table_index != VEX_0F || vindex != 0x77) @@ -11300,6 +11374,7 @@ OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, /* Skip mod/rm byte. */ MODRM_CHECK; ins->codep++; + ins->has_skipped_modrm = true; return true; } @@ -11818,7 +11893,11 @@ OP_E (instr_info *ins, int bytemode, int sizeflag) { /* Skip mod/rm byte. */ MODRM_CHECK; - ins->codep++; + if (!ins->has_skipped_modrm) + { + ins->codep++; + ins->has_skipped_modrm = true; + } if (ins->modrm.mod == 3) { @@ -12623,9 +12702,10 @@ OP_R (instr_info *ins, int bytemode, int sizeflag) { case d_mode: case dq_mode: + case q_mode: case mask_mode: return OP_E (ins, bytemode, sizeflag); - case q_mode: + case q_mm_mode: return OP_EM (ins, x_mode, sizeflag); case xmm_mode: if (ins->vex.length <= 128) diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index cfc5a7a6172..bb58afcbc06 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -380,6 +380,7 @@ static bitfield cpu_flags[] = BITFIELD (RAO_INT), BITFIELD (FRED), BITFIELD (LKGS), + BITFIELD (USER_MSR), BITFIELD (MWAITX), BITFIELD (CLZERO), BITFIELD (OSPKE), @@ -1023,6 +1024,7 @@ process_i386_opcode_modifier (FILE *table, char *mod, unsigned int space, SPACE(0F3A), SPACE(EVEXMAP5), SPACE(EVEXMAP6), + SPACE(VEXMAP7), SPACE(XOP08), SPACE(XOP09), SPACE(XOP0A), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 149ae0e950c..529eb7c41c8 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -223,6 +223,8 @@ enum i386_cpu CpuFRED, /* lkgs instruction required */ CpuLKGS, + /* Intel USER_MSR Instruction support required. */ + CpuUSER_MSR, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -471,6 +473,7 @@ typedef union i386_cpu_flags unsigned int cpurao_int:1; unsigned int cpufred:1; unsigned int cpulkgs:1; + unsigned int cpuuser_msr:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; @@ -966,6 +969,7 @@ typedef struct insn_template 3: 0F3A opcode prefix / space. 5: EVEXMAP5 opcode prefix / space. 6: EVEXMAP6 opcode prefix / space. + 7: VEXMAP7 opcode prefix / space. 8: XOP 08 opcode space. 9: XOP 09 opcode space. A: XOP 0A opcode space. @@ -976,6 +980,7 @@ typedef struct insn_template #define SPACE_0F3A 3 #define SPACE_EVEXMAP5 5 #define SPACE_EVEXMAP6 6 +#define SPACE_VEXMAP7 7 #define SPACE_XOP08 8 #define SPACE_XOP09 9 #define SPACE_XOP0A 0xA diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index e60184ba154..a3426298340 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -112,6 +112,8 @@ #define EVexMap5 OpcodeSpace=SPACE_EVEXMAP5 #define EVexMap6 OpcodeSpace=SPACE_EVEXMAP6 +#define VexMap7 OpcodeSpace=SPACE_VEXMAP7 + #define VexW0 VexW=VEXW0 #define VexW1 VexW=VEXW1 #define VexWIG VexW=VEXWIG @@ -3346,3 +3348,12 @@ erets, 0xf20f01ca, FRED|x64, NoSuf, {} eretu, 0xf30f01ca, FRED|x64, NoSuf, {} // FRED instructions end. + +// USER_MSR instructions. + +urdmsr, 0xf20f38f8, USER_MSR|x64, RegMem|NoSuf|NoRex64, { Reg64, Reg64 } +urdmsr, 0xf2f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 } +uwrmsr, 0xf30f38f8, USER_MSR|x64, Modrm|NoSuf|NoRex64, { Reg64, Reg64 } +uwrmsr, 0xf3f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Reg64, Imm32 } + +// USER_MSR instructions end. -- 2.31.1 ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH][v5] Support Intel USER_MSR 2023-10-27 9:00 ` [PATCH][v5] " Hu, Lin1 @ 2023-10-27 13:36 ` Jan Beulich 2023-10-30 5:50 ` Hu, Lin1 0 siblings, 1 reply; 33+ messages in thread From: Jan Beulich @ 2023-10-27 13:36 UTC (permalink / raw) To: Hu, Lin1; +Cc: hongjiu.lu, binutils On 27.10.2023 11:00, Hu, Lin1 wrote: > @@ -2504,7 +2505,10 @@ smallest_imm_type (offsetT num) > t.bitfield.imm8 = 1; > t.bitfield.imm8s = 1; > t.bitfield.imm16 = 1; > - t.bitfield.imm32 = 1; > + if (flag_code != CODE_64BIT) > + t.bitfield.imm32 = 1; > + else if (fits_in_unsigned_long (num)) > + t.bitfield.imm32 = 1; > t.bitfield.imm32s = 1; > } if (flag_code != CODE_64BIT || fits_in_unsigned_long (num)) t.bitfield.imm32 = 1; would be more clear imo (same further down then). > @@ -5158,6 +5169,7 @@ md_assemble (char *line) > const char *end, *pass1_mnem = NULL; > enum i386_error pass1_err = 0; > const insn_template *t; > + int op; I know there are lots of example like this, but this new variable would benefit from being "unsigned int" and from being declared in the narrow- most scope possible. Then again, why don't you re-use j below? > @@ -5232,8 +5244,23 @@ md_assemble (char *line) > && (t->mnem_off == MN_extrq || t->mnem_off == MN_insertq)) > swap_2_operands (0, 1); Did you, btw, consider extending this to cater for UWRMSR as well, in place of the new construct at the bottom of match_template()? (I'm not saying it needs to be that way; if you decide to leave things as is, I may later see about folding both.) > + /* For USER_MSR instructions, imm32 stands for the name of an model specific > + register (MSR). So we need to avoid set i.types[op].bitfield.imm32 = 0, > + when guess_suffix == QWORD_MNEM_SUFFIX. For time-saving reasons, > + we specialize the USER_MSR and make only the necessary judgments. */ This comment wants to move ... > if (i.imm_operands) > - optimize_imm (); > + { > + if (!is_cpu(current_templates->start, CpuUSER_MSR)) ... right above this if(). I'd also like to suggest rewording, as emphasis ought to be on 32-bit immediates normally being imm32s for 64-bit operand- size insns. Mentioning guess_suffix == QWORD_MNEM_SUFFIX would make sense only when also saying what function this is talking about. Overall maybe: "For USER_MSR instructions, imm32 stands for the name of an model specific register (MSR). That's an unsigned quantity, whereas all other insns with 32-bit immediate and 64-bit operand size use sign-extended immediates (imm32s). Therefore these insns are special-cased, bypassing the normal handling of immediates here." > + optimize_imm (); > + else > + { > + for (op = i.operands; --op >= 0;) To accommodate the request further up this will need adjustment. It's not quite clear anyway why the loop here works downwards. Unless you think any of the remaining adjustment requests are unclear or undesirable, okay with those adjustments. Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH][v5] Support Intel USER_MSR 2023-10-27 13:36 ` Jan Beulich @ 2023-10-30 5:50 ` Hu, Lin1 2023-10-30 8:31 ` Jan Beulich 0 siblings, 1 reply; 33+ messages in thread From: Hu, Lin1 @ 2023-10-30 5:50 UTC (permalink / raw) To: Beulich, Jan; +Cc: Lu, Hongjiu, binutils > > @@ -5232,8 +5244,23 @@ md_assemble (char *line) > > && (t->mnem_off == MN_extrq || t->mnem_off == MN_insertq)) > > swap_2_operands (0, 1); > > Did you, btw, consider extending this to cater for UWRMSR as well, in place of > the new construct at the bottom of match_template()? (I'm not saying it needs > to be that way; if you decide to leave things as is, I may later see about folding > both.) > For this part, my current changes are @@ -5400,6 +5388,38 @@ md_assemble (char *line) return; } + /* The order of the immediates should be reversed + for 2 immediates extrq and insertq instructions. + And This pattern aims to put the unusually placed imm operand to a usual + place. The constraints are currently only adapted to uwrmsr, and may + need further tweaking when new similar instructions become available. */ + if (i.imm_operands && i.imm_operands < i.operands + && ((t->mnem_off == MN_extrq || t->mnem_off == MN_insertq) + || operand_type_check (i.tm.operand_types[1], imm))) + { + i386_operand_type tmp_operand_type = i.tm.operand_types[0]; + i.tm.operand_types[0] = i.tm.operand_types[1]; + i.tm.operand_types[1] = tmp_operand_type; + swap_2_operands(0, 1); + } after match_template. Some generalization has been reduced to save on code size. What's your opinion? For the other comments, I've made changes as mentioned. BRs, Lin ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH][v5] Support Intel USER_MSR 2023-10-30 5:50 ` Hu, Lin1 @ 2023-10-30 8:31 ` Jan Beulich 2023-10-31 1:43 ` Hu, Lin1 2023-10-31 2:14 ` [PATCH][v6] " Hu, Lin1 0 siblings, 2 replies; 33+ messages in thread From: Jan Beulich @ 2023-10-30 8:31 UTC (permalink / raw) To: Hu, Lin1; +Cc: Lu, Hongjiu, binutils On 30.10.2023 06:50, Hu, Lin1 wrote: >>> @@ -5232,8 +5244,23 @@ md_assemble (char *line) >>> && (t->mnem_off == MN_extrq || t->mnem_off == MN_insertq)) >>> swap_2_operands (0, 1); >> >> Did you, btw, consider extending this to cater for UWRMSR as well, in place of >> the new construct at the bottom of match_template()? (I'm not saying it needs >> to be that way; if you decide to leave things as is, I may later see about folding >> both.) >> > > For this part, my current changes are > > @@ -5400,6 +5388,38 @@ md_assemble (char *line) > return; > } > > + /* The order of the immediates should be reversed > + for 2 immediates extrq and insertq instructions. > + And This pattern aims to put the unusually placed imm operand to a usual > + place. The constraints are currently only adapted to uwrmsr, and may > + need further tweaking when new similar instructions become available. */ > + if (i.imm_operands && i.imm_operands < i.operands > + && ((t->mnem_off == MN_extrq || t->mnem_off == MN_insertq) > + || operand_type_check (i.tm.operand_types[1], imm))) > + { > + i386_operand_type tmp_operand_type = i.tm.operand_types[0]; > + i.tm.operand_types[0] = i.tm.operand_types[1]; > + i.tm.operand_types[1] = tmp_operand_type; > + swap_2_operands(0, 1); > + } > > after match_template. Some generalization has been reduced to save on code size. > What's your opinion? Hmm, why this way, rather than indeed merely extending (without moving) what's there? (Anyway, as said, I'm not going to insist on this folding; if you don't want to deal with that right here, I'll see to make a follow-on change later.) Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH][v5] Support Intel USER_MSR 2023-10-30 8:31 ` Jan Beulich @ 2023-10-31 1:43 ` Hu, Lin1 2023-10-31 2:14 ` [PATCH][v6] " Hu, Lin1 1 sibling, 0 replies; 33+ messages in thread From: Hu, Lin1 @ 2023-10-31 1:43 UTC (permalink / raw) To: Beulich, Jan; +Cc: Lu, Hongjiu, binutils > On 30.10.2023 06:50, Hu, Lin1 wrote: > >>> @@ -5232,8 +5244,23 @@ md_assemble (char *line) > >>> && (t->mnem_off == MN_extrq || t->mnem_off == MN_insertq)) > >>> swap_2_operands (0, 1); > >> > >> Did you, btw, consider extending this to cater for UWRMSR as well, in > >> place of the new construct at the bottom of match_template()? (I'm > >> not saying it needs to be that way; if you decide to leave things as > >> is, I may later see about folding > >> both.) > >> > > > > For this part, my current changes are > > > > @@ -5400,6 +5388,38 @@ md_assemble (char *line) > > return; > > } > > > > + /* The order of the immediates should be reversed > > + for 2 immediates extrq and insertq instructions. > > + And This pattern aims to put the unusually placed imm operand to a usual > > + place. The constraints are currently only adapted to uwrmsr, and may > > + need further tweaking when new similar instructions become > > + available. */ if (i.imm_operands && i.imm_operands < i.operands > > + && ((t->mnem_off == MN_extrq || t->mnem_off == MN_insertq) > > + || operand_type_check (i.tm.operand_types[1], imm))) > > + { > > + i386_operand_type tmp_operand_type = i.tm.operand_types[0]; > > + i.tm.operand_types[0] = i.tm.operand_types[1]; > > + i.tm.operand_types[1] = tmp_operand_type; > > + swap_2_operands(0, 1); > > + } > > > > after match_template. Some generalization has been reduced to save on code > size. > > What's your opinion? > > Hmm, why this way, rather than indeed merely extending (without moving) > what's there? (Anyway, as said, I'm not going to insist on this folding; if you > don't want to deal with that right here, I'll see to make a follow-on change later.) > I think I can't just extend it. If I swap the unusual immediate operand before match_template, I need a new opcode_modifier whose function is like D to match the correct template. And the instruction "out" will be affected by this change (of course the problem can be solved by adding a constraint). ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH][v6] Support Intel USER_MSR 2023-10-30 8:31 ` Jan Beulich 2023-10-31 1:43 ` Hu, Lin1 @ 2023-10-31 2:14 ` Hu, Lin1 2023-10-31 8:03 ` Jan Beulich 2023-11-14 7:14 ` Jan Beulich 1 sibling, 2 replies; 33+ messages in thread From: Hu, Lin1 @ 2023-10-31 2:14 UTC (permalink / raw) To: binutils; +Cc: JBeulich, hongjiu.lu This is the current version. BRs, Lin gas/ChangeLog: * NEWS: Support Intel USER_MSR. * config/tc-i386.c (smallest_imm_type): Reject imm32 in 64bit mode. (build_vex_prefix): Add VEXMAP7. (md_assemble): Handling the imm32 of USER_MSR. (match_template): Handling the unusual immediate. * doc/c-i386.texi: Document .user_msr. * testsuite/gas/i386/i386.exp: Run USER_MSR tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/user_msr-inval.l: New test. * testsuite/gas/i386/user_msr-inval.s: Ditto. * testsuite/gas/i386/x86-64-user_msr-intel.d: Ditto. * testsuite/gas/i386/x86-64-user_msr-inval.l: New test. * testsuite/gas/i386/x86-64-user_msr-inval.s: New test. * testsuite/gas/i386/x86-64-user_msr.d: Ditto. * testsuite/gas/i386/x86-64-user_msr.s: Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add a new attribute has_skipped_modrm. (Gq): New. (Rq): Ditto. (q_mm_mode): Ditto. (Nq): Change mode from q_mode to q_mm_mode. (VEX_LEN_TABLE): (get_valid_dis386): Add VEX_MAP7 in VEX prefix. and handle the map7_f8 for save space. (OP_Skip_MODRM): Set has_skipped_modrm. (OP_E): Skip codep++ when has skipped modrm byte. (OP_R): Support q_mode and q_mm_mode. (REG_VEX_MAP7_F8_L_0_W_0): New. (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64): Ditto. (X86_64_VEX_MAP7_F8_L_0_W_0_R_0): Ditto. (VEX_LEN_MAP7_F8): Ditto. (VEX_W_MAP7_F8_L_0): Ditto. (MOD_0F38F8): Ditto. (PREFIX_0F38F8_M_0): Ditto. (PREFIX_0F38F8_M_1_X86_64): Ditto. (X86_64_0F38F8_M_1): Ditto. (PREFIX_0F38F8): Remove. (prefix_table): Add PREFIX_0F38F8_M_1_X86_64. Remove PREFIX_0F38F8. (reg_table): Add REG_VEX_MAP7_F8_L_0_W_0, PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64. (x86_64_table): Add X86_64_0F38F8_PREFIX_3_M_1, X86_64_VEX_MAP7_F8_L_0_W_0_R_0 and X86_64_0F38F8_M_1. (vex_table): Add VEX_MAP7. (vex_len_table): Add VEX_LEN_MAP7_F8, VEX_W_MAP7_F8_L_0. (mod_table): New entry for USER_MSR and add MOD_0F38F8. * i386-gen.c (cpu_flag_init): Add CPU_USER_MSR_FLAGS and CPU_ANY_USER_MSR_FLAGS. Add add VEXMAP7. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (SPACE_VEXMAP7): New. (CPU_USER_MSR_FLAGS): Ditoo. (CPU_ANY_USER_MSR_FLAGS): Ditto. (i386_cpu_flags): Add cpuuser_msr. * i386-opc.tbl: Add USER_MSR instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 2 + gas/config/tc-i386.c | 40 +- gas/doc/c-i386.texi | 3 +- gas/testsuite/gas/i386/i386.exp | 1 + gas/testsuite/gas/i386/user_msr-inval.l | 3 + gas/testsuite/gas/i386/user_msr-inval.s | 6 + .../gas/i386/x86-64-user_msr-intel.d | 46 + .../gas/i386/x86-64-user_msr-inval.l | 9 + .../gas/i386/x86-64-user_msr-inval.s | 12 + gas/testsuite/gas/i386/x86-64-user_msr.d | 46 + gas/testsuite/gas/i386/x86-64-user_msr.s | 42 + gas/testsuite/gas/i386/x86-64.exp | 3 + opcodes/i386-dis.c | 96 +- opcodes/i386-gen.c | 2 + opcodes/i386-init.h | 816 +++++------ opcodes/i386-mnem.h | 1278 +++++++++-------- opcodes/i386-opc.h | 5 + opcodes/i386-opc.tbl | 11 + opcodes/i386-tbl.h | 272 ++-- 19 files changed, 1522 insertions(+), 1171 deletions(-) create mode 100644 gas/testsuite/gas/i386/user_msr-inval.l create mode 100644 gas/testsuite/gas/i386/user_msr-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr.d create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr.s diff --git a/gas/NEWS b/gas/NEWS index 71a1269b893..ab0e7813f27 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel USER_MSR instructions. + * Add support for Intel AVX10.1. * Add support for Intel PBNDKB instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 714354d5116..8a47e8715dc 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1164,6 +1164,7 @@ static const arch_entry cpu_arch[] = VECARCH (sm4, SM4, ANY_SM4, reset), SUBARCH (pbndkb, PBNDKB, PBNDKB, false), VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set), + SUBARCH (user_msr, USER_MSR, USER_MSR, false), }; #undef SUBARCH @@ -2504,7 +2505,8 @@ smallest_imm_type (offsetT num) t.bitfield.imm8 = 1; t.bitfield.imm8s = 1; t.bitfield.imm16 = 1; - t.bitfield.imm32 = 1; + if (flag_code != CODE_64BIT || fits_in_unsigned_long (num)) + t.bitfield.imm32 = 1; t.bitfield.imm32s = 1; } else if (fits_in_unsigned_byte (num)) @@ -2517,12 +2519,14 @@ smallest_imm_type (offsetT num) else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) { t.bitfield.imm16 = 1; - t.bitfield.imm32 = 1; + if (flag_code != CODE_64BIT || fits_in_unsigned_long (num)) + t.bitfield.imm32 = 1; t.bitfield.imm32s = 1; } else if (fits_in_signed_long (num)) { - t.bitfield.imm32 = 1; + if (flag_code != CODE_64BIT || fits_in_unsigned_long (num)) + t.bitfield.imm32 = 1; t.bitfield.imm32s = 1; } else if (fits_in_unsigned_long (num)) @@ -3863,6 +3867,7 @@ build_vex_prefix (const insn_template *t) case SPACE_0F: case SPACE_0F38: case SPACE_0F3A: + case SPACE_VEXMAP7: i.vex.bytes[0] = 0xc4; break; case SPACE_XOP08: @@ -5233,7 +5238,23 @@ md_assemble (char *line) swap_2_operands (0, 1); if (i.imm_operands) - optimize_imm (); + { + /* For USER_MSR instructions, imm32 stands for the name of an model specific + register (MSR). That's an unsigned quantity, whereas all other insns with + 32-bit immediate and 64-bit operand size use sign-extended + immediates (imm32s). Therefore these insns are special-cased, bypassing + the normal handling of immediates here. */ + if (is_cpu(current_templates->start, CpuUSER_MSR)) + { + for (j = 0; j < i.operands; j++) + { + if (operand_type_check(i.types[j], imm)) + i.types[j] = smallest_imm_type (i.op[j].imms->X_add_number); + } + } + else + optimize_imm (); + } if (i.disp_operands && !optimize_disp (t)) return; @@ -7566,6 +7587,17 @@ match_template (char mnem_suffix) break; } + /* This pattern aims to put the unusually placed imm operand to a usual + place. The constraints are currently only adapted to uwrmsr, and may + need further tweaking when new similar instructions become available. */ + if (i.imm_operands && i.imm_operands < i.operands + && operand_type_check (operand_types[i.operands - 1], imm)) + { + i.tm.operand_types[0] = operand_types[i.operands - 1]; + i.tm.operand_types[i.operands - 1] = operand_types[0]; + swap_2_operands(0, i.operands - 1); + } + return t; } diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index b04e1b00b4b..03ee980bef7 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -216,6 +216,7 @@ accept various extension mnemonics. For example, @code{avx10.1/512}, @code{avx10.1/256}, @code{avx10.1/128}, +@code{user_msr}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1650,7 +1651,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} @item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs} @item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4} -@item @samp{.pbndkb} +@item @samp{.pbndkb} @tab @samp{.user_msr} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index ee74bcd4615..81ce1e38b10 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -509,6 +509,7 @@ if [gas_32_check] then { run_dump_test "sm4" run_dump_test "sm4-intel" run_list_test "pbndkb-inval" + run_list_test "user_msr-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" diff --git a/gas/testsuite/gas/i386/user_msr-inval.l b/gas/testsuite/gas/i386/user_msr-inval.l new file mode 100644 index 00000000000..54c48f1953b --- /dev/null +++ b/gas/testsuite/gas/i386/user_msr-inval.l @@ -0,0 +1,3 @@ +.* Assembler messages: +.*:5: Error: `urdmsr' is only supported in 64-bit mode +.*:6: Error: `uwrmsr' is only supported in 64-bit mode diff --git a/gas/testsuite/gas/i386/user_msr-inval.s b/gas/testsuite/gas/i386/user_msr-inval.s new file mode 100644 index 00000000000..1682a1e8d79 --- /dev/null +++ b/gas/testsuite/gas/i386/user_msr-inval.s @@ -0,0 +1,6 @@ +# Check Illegal 32bit USER_MSR instructions + + .text +_start: + urdmsr %r12, %r14 + uwrmsr %r12, %r14 diff --git a/gas/testsuite/gas/i386/x86-64-user_msr-intel.d b/gas/testsuite/gas/i386/x86-64-user_msr-intel.d new file mode 100644 index 00000000000..e68b5eacfa9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr-intel.d @@ -0,0 +1,46 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 USER_MSR insns (Intel disassembly) +#source: x86-64-user_msr.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr r12,r14 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr rax,r14 +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr r12,rdx +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr rax,rdx +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr r12,0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr rax,0x3120f0f +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 7f 00 00 00\s+urdmsr r12,0x7f +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 ff 7f 00 00\s+urdmsr r12,0x7fff +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 00 00 00 80\s+urdmsr r12,0x80000000 +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr r14,r12 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr r14,rax +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr rdx,r12 +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr rdx,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr 0x3120f0f,r12 +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr 0x3120f0f,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 7f 00 00 00\s+uwrmsr 0x7f,r12 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 ff 7f 00 00\s+uwrmsr 0x7fff,r12 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 00 00 00 80\s+uwrmsr 0x80000000,r12 +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr r12,r14 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr rax,r14 +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr r12,rdx +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr rax,rdx +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr r12,0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr rax,0x3120f0f +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 7f 00 00 00\s+urdmsr r12,0x7f +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 ff 7f 00 00\s+urdmsr r12,0x7fff +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 00 00 00 80\s+urdmsr r12,0x80000000 +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr r14,r12 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr r14,rax +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr rdx,r12 +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr rdx,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr 0x3120f0f,r12 +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr 0x3120f0f,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 7f 00 00 00\s+uwrmsr 0x7f,r12 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 ff 7f 00 00\s+uwrmsr 0x7fff,r12 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 00 00 00 80\s+uwrmsr 0x80000000,r12 diff --git a/gas/testsuite/gas/i386/x86-64-user_msr-inval.l b/gas/testsuite/gas/i386/x86-64-user_msr-inval.l new file mode 100644 index 00000000000..9eb3044e16e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr-inval.l @@ -0,0 +1,9 @@ +.* Assembler messages: +.*:5: Error: operand type mismatch for `urdmsr' +.*:6: Error: operand type mismatch for `urdmsr' +.*:7: Error: operand type mismatch for `urdmsr' +.*:8: Error: operand type mismatch for `urdmsr' +.*:9: Error: operand type mismatch for `uwrmsr' +.*:10: Error: operand type mismatch for `uwrmsr' +.*:11: Error: operand type mismatch for `uwrmsr' +.*:12: Error: operand type mismatch for `uwrmsr' diff --git a/gas/testsuite/gas/i386/x86-64-user_msr-inval.s b/gas/testsuite/gas/i386/x86-64-user_msr-inval.s new file mode 100644 index 00000000000..e7b6d6eea83 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr-inval.s @@ -0,0 +1,12 @@ +# Check Illegal 64bit USER_MSR instructions + + .text +_start: + urdmsr $-1, %r14 + urdmsr $-32767, %r14 + urdmsr $-2147483648, %r14 + urdmsr $0x7fffffffffffffff, %r14 + uwrmsr %r12, $-1 + uwrmsr %r12, $-32767 + uwrmsr %r12, $-2147483648 + uwrmsr %r12, $0x7fffffffffffffff diff --git a/gas/testsuite/gas/i386/x86-64-user_msr.d b/gas/testsuite/gas/i386/x86-64-user_msr.d new file mode 100644 index 00000000000..41f29718ab0 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr.d @@ -0,0 +1,46 @@ +#as: +#objdump: -dw +#name: x86_64 USER_MSR insns +#source: x86-64-user_msr.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr %r14,%r12 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr %r14,%rax +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr %rdx,%r12 +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr %rdx,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr \$0x3120f0f,%r12 +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr \$0x3120f0f,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 7f 00 00 00\s+urdmsr \$0x7f,%r12 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 ff 7f 00 00\s+urdmsr \$0x7fff,%r12 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 00 00 00 80\s+urdmsr \$0x80000000,%r12 +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr %r12,%r14 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr %rax,%r14 +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr %r12,%rdx +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr %rax,%rdx +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr %r12,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr %rax,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 7f 00 00 00\s+uwrmsr %r12,\$0x7f +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 ff 7f 00 00\s+uwrmsr %r12,\$0x7fff +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 00 00 00 80\s+uwrmsr %r12,\$0x80000000 +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr %r14,%r12 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr %r14,%rax +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr %rdx,%r12 +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr %rdx,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr \$0x3120f0f,%r12 +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr \$0x3120f0f,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 7f 00 00 00\s+urdmsr \$0x7f,%r12 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 ff 7f 00 00\s+urdmsr \$0x7fff,%r12 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 00 00 00 80\s+urdmsr \$0x80000000,%r12 +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr %r12,%r14 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr %rax,%r14 +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr %r12,%rdx +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr %rax,%rdx +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr %r12,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr %rax,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 7f 00 00 00\s+uwrmsr %r12,\$0x7f +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 ff 7f 00 00\s+uwrmsr %r12,\$0x7fff +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 00 00 00 80\s+uwrmsr %r12,\$0x80000000 diff --git a/gas/testsuite/gas/i386/x86-64-user_msr.s b/gas/testsuite/gas/i386/x86-64-user_msr.s new file mode 100644 index 00000000000..63bc6c1352c --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s @@ -0,0 +1,42 @@ +# Check 64bit USER_MSR instructions + + .text +_start: + urdmsr %r14, %r12 + urdmsr %r14, %rax + urdmsr %rdx, %r12 + urdmsr %rdx, %rax + urdmsr $51515151, %r12 + urdmsr $51515151, %rax + urdmsr $0x7f, %r12 + urdmsr $0x7fff, %r12 + urdmsr $0x80000000, %r12 + uwrmsr %r12, %r14 + uwrmsr %rax, %r14 + uwrmsr %r12, %rdx + uwrmsr %rax, %rdx + uwrmsr %r12, $51515151 + uwrmsr %rax, $51515151 + uwrmsr %r12, $0x7f + uwrmsr %r12, $0x7fff + uwrmsr %r12, $0x80000000 + + .intel_syntax noprefix + urdmsr r12, r14 + urdmsr rax, r14 + urdmsr r12, rdx + urdmsr rax, rdx + urdmsr r12, 51515151 + urdmsr rax, 51515151 + urdmsr r12, 0x7f + urdmsr r12, 0x7fff + urdmsr r12, 0x80000000 + uwrmsr r14, r12 + uwrmsr r14, rax + uwrmsr rdx, r12 + uwrmsr rdx, rax + uwrmsr 51515151, r12 + uwrmsr 51515151, rax + uwrmsr 0x7f, r12 + uwrmsr 0x7fff, r12 + uwrmsr 0x80000000, r12 diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 52711cdcf6f..22fdb0d9bcd 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -450,6 +450,9 @@ run_dump_test "x86-64-sm4" run_dump_test "x86-64-sm4-intel" run_dump_test "x86-64-pbndkb" run_dump_test "x86-64-pbndkb-intel" +run_dump_test "x86-64-user_msr" +run_dump_test "x86-64-user_msr-intel" +run_list_test "x86-64-user_msr-inval" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 87ecf0f5e23..2e2043d467b 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -221,6 +221,9 @@ struct instr_info /* Record whether EVEX masking is used incorrectly. */ bool illegal_masking; + /* Record whether the modrm byte has been skipped. */ + bool has_skipped_modrm; + unsigned char op_ad; signed char op_index[MAX_OPERANDS]; bool op_riprel[MAX_OPERANDS]; @@ -418,6 +421,7 @@ fetch_error (const instr_info *ins) #define Gv { OP_G, v_mode } #define Gd { OP_G, d_mode } #define Gdq { OP_G, dq_mode } +#define Gq { OP_G, q_mode } #define Gm { OP_G, m_mode } #define Gva { OP_G, va_mode } #define Gw { OP_G, w_mode } @@ -527,7 +531,8 @@ fetch_error (const instr_info *ins) #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } #define Rd { OP_R, d_mode } #define Rdq { OP_R, dq_mode } -#define Nq { OP_R, q_mode } +#define Rq { OP_R, q_mode } +#define Nq { OP_R, q_mm_mode } #define Ux { OP_R, x_mode } #define Uxmm { OP_R, xmm_mode } #define Rxmmq { OP_R, xmmq_mode } @@ -624,6 +629,8 @@ enum d_swap_mode, /* quad word operand */ q_mode, + /* 8-byte MM operand */ + q_mm_mode, /* quad word operand with operand swapped */ q_swap_mode, /* ten-byte operand */ @@ -845,6 +852,7 @@ enum REG_VEX_0FAE, REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0, REG_VEX_0F38F3_L_0, + REG_VEX_MAP7_F8_L_0_W_0, REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, @@ -893,6 +901,7 @@ enum MOD_0FC7_REG_6, MOD_0FC7_REG_7, MOD_0F38DC_PREFIX_1, + MOD_0F38F8, MOD_VEX_0F3849_X86_64_L_0_W_0, }; @@ -1010,7 +1019,8 @@ enum PREFIX_0F38F0, PREFIX_0F38F1, PREFIX_0F38F6, - PREFIX_0F38F8, + PREFIX_0F38F8_M_0, + PREFIX_0F38F8_M_1_X86_64, PREFIX_0F38FA, PREFIX_0F38FB, PREFIX_0F38FC, @@ -1073,6 +1083,7 @@ enum PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0, PREFIX_VEX_0F3AF0_L_0, + PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F6F, @@ -1217,6 +1228,7 @@ enum X86_64_0F18_REG_7_MOD_0, X86_64_0F24, X86_64_0F26, + X86_64_0F38F8_M_1, X86_64_0FC7_REG_6_MOD_3_PREFIX_1, X86_64_VEX_0F3849, @@ -1240,6 +1252,7 @@ enum X86_64_VEX_0F38ED, X86_64_VEX_0F38EE, X86_64_VEX_0F38EF, + X86_64_VEX_MAP7_F8_L_0_W_0_R_0, }; enum @@ -1259,7 +1272,8 @@ enum { VEX_0F = 0, VEX_0F38, - VEX_0F3A + VEX_0F3A, + VEX_MAP7, }; enum @@ -1350,6 +1364,7 @@ enum VEX_LEN_0F3ADE_W_0, VEX_LEN_0F3ADF, VEX_LEN_0F3AF0, + VEX_LEN_MAP7_F8, VEX_LEN_XOP_08_85, VEX_LEN_XOP_08_86, VEX_LEN_XOP_08_87, @@ -1510,6 +1525,7 @@ enum VEX_W_0F3ACE, VEX_W_0F3ACF, VEX_W_0F3ADE, + VEX_W_MAP7_F8_L_0, VEX_W_XOP_08_85_L_0, VEX_W_XOP_08_86_L_0, @@ -2849,6 +2865,10 @@ static const struct dis386 reg_table[][8] = { { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE }, { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE }, }, + /* REG_VEX_MAP7_F8_L_0_W_0 */ + { + { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) }, + }, /* REG_XOP_09_01_L_0 */ { { Bad_Opcode }, @@ -3555,13 +3575,22 @@ static const struct dis386 prefix_table[][4] = { { Bad_Opcode }, }, - /* PREFIX_0F38F8 */ + /* PREFIX_0F38F8_M_0 */ { { Bad_Opcode }, { "enqcmds", { Gva, M }, 0 }, { "movdir64b", { Gva, M }, 0 }, { "enqcmd", { Gva, M }, 0 }, }, + + /* PREFIX_0F38F8_M_1_X86_64 */ + { + { Bad_Opcode }, + { "uwrmsr", { Gq, Rq }, 0 }, + { Bad_Opcode }, + { "urdmsr", { Rq, Gq }, 0 }, + }, + /* PREFIX_0F38FA */ { { Bad_Opcode }, @@ -4014,6 +4043,14 @@ static const struct dis386 prefix_table[][4] = { { "rorxS", { Gdq, Edq, Ib }, 0 }, }, + /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */ + { + { Bad_Opcode }, + { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 }, + { Bad_Opcode }, + { "urdmsr", { Rq, Id }, 0 }, + }, + #include "i386-dis-evex-prefix.h" }; @@ -4322,6 +4359,12 @@ static const struct dis386 x86_64_table[][2] = { { "movZ", { Td, Em }, 0 }, }, + { + /* X86_64_0F38F8_M_1 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) }, + }, + /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */ { { Bad_Opcode }, @@ -4453,6 +4496,13 @@ static const struct dis386 x86_64_table[][2] = { { Bad_Opcode }, { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, }, + + /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */ + { + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) }, + }, + }; static const struct dis386 three_byte_table[][256] = { @@ -4739,7 +4789,7 @@ static const struct dis386 three_byte_table[][256] = { { PREFIX_TABLE (PREFIX_0F38F6) }, { Bad_Opcode }, /* f8 */ - { PREFIX_TABLE (PREFIX_0F38F8) }, + { MOD_TABLE (MOD_0F38F8) }, { "movdiri", { Mdq, Gdq }, PREFIX_OPCODE }, { PREFIX_TABLE (PREFIX_0F38FA) }, { PREFIX_TABLE (PREFIX_0F38FB) }, @@ -7205,6 +7255,11 @@ static const struct dis386 vex_len_table[][2] = { { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) }, }, + /* VEX_LEN_MAP7_F8 */ + { + { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) }, + }, + /* VEX_LEN_XOP_08_85 */ { { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) }, @@ -7811,6 +7866,10 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3ADE */ { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) }, }, + { + /* VEX_W_MAP7_F8_L_0 */ + { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) }, + }, /* VEX_W_XOP_08_85_L_0 */ { { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 }, @@ -8153,6 +8212,11 @@ static const struct dis386 mod_table[][2] = { { "aesenc128kl", { XM, M }, 0 }, { "loadiwkey", { XM, EXx }, 0 }, }, + /* MOD_0F38F8 */ + { + { PREFIX_TABLE (PREFIX_0F38F8_M_0) }, + { X86_64_TABLE (X86_64_0F38F8_M_1) }, + }, { /* MOD_VEX_0F3849_X86_64_L_0_W_0 */ { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) }, @@ -8527,6 +8591,8 @@ static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; /* Fetch error indicator. */ static const struct dis386 err_opcode = { NULL, { XX }, 0 }; +static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) }; + /* Get a pointer to struct dis386 with a valid name. */ static const struct dis386 * @@ -8769,6 +8835,9 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) case 0x3: vex_table_index = VEX_0F3A; break; + case 0x7: + vex_table_index = VEX_MAP7; + break; } ins->codep++; ins->vex.w = *ins->codep & 0x80; @@ -8803,7 +8872,12 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) ins->need_vex = 3; ins->codep++; vindex = *ins->codep++; - dp = &vex_table[vex_table_index][vindex]; + if (vex_table_index != VEX_MAP7) + dp = &vex_table[vex_table_index][vindex]; + else if (vindex == 0xf8) + dp = &map7_f8_opcode; + else + dp = &bad_opcode; ins->end_codep = ins->codep; /* There is no MODRM byte for VEX0F 77. */ if ((vex_table_index != VEX_0F || vindex != 0x77) @@ -11300,6 +11374,7 @@ OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, /* Skip mod/rm byte. */ MODRM_CHECK; ins->codep++; + ins->has_skipped_modrm = true; return true; } @@ -11818,7 +11893,11 @@ OP_E (instr_info *ins, int bytemode, int sizeflag) { /* Skip mod/rm byte. */ MODRM_CHECK; - ins->codep++; + if (!ins->has_skipped_modrm) + { + ins->codep++; + ins->has_skipped_modrm = true; + } if (ins->modrm.mod == 3) { @@ -12623,9 +12702,10 @@ OP_R (instr_info *ins, int bytemode, int sizeflag) { case d_mode: case dq_mode: + case q_mode: case mask_mode: return OP_E (ins, bytemode, sizeflag); - case q_mode: + case q_mm_mode: return OP_EM (ins, x_mode, sizeflag); case xmm_mode: if (ins->vex.length <= 128) diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index cfc5a7a6172..bb58afcbc06 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -380,6 +380,7 @@ static bitfield cpu_flags[] = BITFIELD (RAO_INT), BITFIELD (FRED), BITFIELD (LKGS), + BITFIELD (USER_MSR), BITFIELD (MWAITX), BITFIELD (CLZERO), BITFIELD (OSPKE), @@ -1023,6 +1024,7 @@ process_i386_opcode_modifier (FILE *table, char *mod, unsigned int space, SPACE(0F3A), SPACE(EVEXMAP5), SPACE(EVEXMAP6), + SPACE(VEXMAP7), SPACE(XOP08), SPACE(XOP09), SPACE(XOP0A), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 149ae0e950c..529eb7c41c8 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -223,6 +223,8 @@ enum i386_cpu CpuFRED, /* lkgs instruction required */ CpuLKGS, + /* Intel USER_MSR Instruction support required. */ + CpuUSER_MSR, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -471,6 +473,7 @@ typedef union i386_cpu_flags unsigned int cpurao_int:1; unsigned int cpufred:1; unsigned int cpulkgs:1; + unsigned int cpuuser_msr:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; @@ -966,6 +969,7 @@ typedef struct insn_template 3: 0F3A opcode prefix / space. 5: EVEXMAP5 opcode prefix / space. 6: EVEXMAP6 opcode prefix / space. + 7: VEXMAP7 opcode prefix / space. 8: XOP 08 opcode space. 9: XOP 09 opcode space. A: XOP 0A opcode space. @@ -976,6 +980,7 @@ typedef struct insn_template #define SPACE_0F3A 3 #define SPACE_EVEXMAP5 5 #define SPACE_EVEXMAP6 6 +#define SPACE_VEXMAP7 7 #define SPACE_XOP08 8 #define SPACE_XOP09 9 #define SPACE_XOP0A 0xA diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index e60184ba154..a3426298340 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -112,6 +112,8 @@ #define EVexMap5 OpcodeSpace=SPACE_EVEXMAP5 #define EVexMap6 OpcodeSpace=SPACE_EVEXMAP6 +#define VexMap7 OpcodeSpace=SPACE_VEXMAP7 + #define VexW0 VexW=VEXW0 #define VexW1 VexW=VEXW1 #define VexWIG VexW=VEXWIG @@ -3346,3 +3348,12 @@ erets, 0xf20f01ca, FRED|x64, NoSuf, {} eretu, 0xf30f01ca, FRED|x64, NoSuf, {} // FRED instructions end. + +// USER_MSR instructions. + +urdmsr, 0xf20f38f8, USER_MSR|x64, RegMem|NoSuf|NoRex64, { Reg64, Reg64 } +urdmsr, 0xf2f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 } +uwrmsr, 0xf30f38f8, USER_MSR|x64, Modrm|NoSuf|NoRex64, { Reg64, Reg64 } +uwrmsr, 0xf3f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Reg64, Imm32 } + +// USER_MSR instructions end. -- 2.31.1 ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH][v6] Support Intel USER_MSR 2023-10-31 2:14 ` [PATCH][v6] " Hu, Lin1 @ 2023-10-31 8:03 ` Jan Beulich 2023-10-31 8:35 ` Hu, Lin1 2023-11-14 7:14 ` Jan Beulich 1 sibling, 1 reply; 33+ messages in thread From: Jan Beulich @ 2023-10-31 8:03 UTC (permalink / raw) To: Hu, Lin1; +Cc: hongjiu.lu, binutils On 31.10.2023 03:14, Hu, Lin1 wrote: > This is the current version. > > BRs, > Lin > > gas/ChangeLog: > > * NEWS: Support Intel USER_MSR. > * config/tc-i386.c (smallest_imm_type): Reject imm32 in 64bit > mode. > (build_vex_prefix): Add VEXMAP7. > (md_assemble): Handling the imm32 of USER_MSR. > (match_template): Handling the unusual immediate. > * doc/c-i386.texi: Document .user_msr. > * testsuite/gas/i386/i386.exp: Run USER_MSR tests. > * testsuite/gas/i386/x86-64.exp: Ditto. > * testsuite/gas/i386/user_msr-inval.l: New test. > * testsuite/gas/i386/user_msr-inval.s: Ditto. > * testsuite/gas/i386/x86-64-user_msr-intel.d: Ditto. > * testsuite/gas/i386/x86-64-user_msr-inval.l: New test. > * testsuite/gas/i386/x86-64-user_msr-inval.s: New test. > * testsuite/gas/i386/x86-64-user_msr.d: Ditto. > * testsuite/gas/i386/x86-64-user_msr.s: Ditto. > > opcodes/ChangeLog: > * i386-dis.c (struct instr_info): Add a new attribute > has_skipped_modrm. > (Gq): New. > (Rq): Ditto. > (q_mm_mode): Ditto. > (Nq): Change mode from q_mode to q_mm_mode. > (VEX_LEN_TABLE): > (get_valid_dis386): Add VEX_MAP7 in VEX prefix. > and handle the map7_f8 for save space. > (OP_Skip_MODRM): Set has_skipped_modrm. > (OP_E): Skip codep++ when has skipped modrm byte. > (OP_R): Support q_mode and q_mm_mode. > (REG_VEX_MAP7_F8_L_0_W_0): New. > (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64): Ditto. > (X86_64_VEX_MAP7_F8_L_0_W_0_R_0): Ditto. > (VEX_LEN_MAP7_F8): Ditto. > (VEX_W_MAP7_F8_L_0): Ditto. > (MOD_0F38F8): Ditto. > (PREFIX_0F38F8_M_0): Ditto. > (PREFIX_0F38F8_M_1_X86_64): Ditto. > (X86_64_0F38F8_M_1): Ditto. > (PREFIX_0F38F8): Remove. > (prefix_table): Add PREFIX_0F38F8_M_1_X86_64. > Remove PREFIX_0F38F8. > (reg_table): Add REG_VEX_MAP7_F8_L_0_W_0, > PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64. > (x86_64_table): Add X86_64_0F38F8_PREFIX_3_M_1, > X86_64_VEX_MAP7_F8_L_0_W_0_R_0 and X86_64_0F38F8_M_1. > (vex_table): Add VEX_MAP7. > (vex_len_table): Add VEX_LEN_MAP7_F8, > VEX_W_MAP7_F8_L_0. > (mod_table): New entry for USER_MSR and > add MOD_0F38F8. > * i386-gen.c (cpu_flag_init): Add CPU_USER_MSR_FLAGS and > CPU_ANY_USER_MSR_FLAGS. Add add VEXMAP7. > * i386-init.h: Regenerated. > * i386-mnem.h: Ditto. > * i386-opc.h (SPACE_VEXMAP7): New. > (CPU_USER_MSR_FLAGS): Ditoo. > (CPU_ANY_USER_MSR_FLAGS): Ditto. > (i386_cpu_flags): Add cpuuser_msr. > * i386-opc.tbl: Add USER_MSR instructions. > * i386-tbl.h: Regenerated. Okay. Going forward though please make sure that patches have a useful description (beyond the ChangeLog entries). Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH][v6] Support Intel USER_MSR 2023-10-31 8:03 ` Jan Beulich @ 2023-10-31 8:35 ` Hu, Lin1 0 siblings, 0 replies; 33+ messages in thread From: Hu, Lin1 @ 2023-10-31 8:35 UTC (permalink / raw) To: Beulich, Jan; +Cc: Lu, Hongjiu, binutils > On 31.10.2023 03:14, Hu, Lin1 wrote: > > This is the current version. > > > > BRs, > > Lin > > > > gas/ChangeLog: > > > > * NEWS: Support Intel USER_MSR. > > * config/tc-i386.c (smallest_imm_type): Reject imm32 in 64bit > > mode. > > (build_vex_prefix): Add VEXMAP7. > > (md_assemble): Handling the imm32 of USER_MSR. > > (match_template): Handling the unusual immediate. > > * doc/c-i386.texi: Document .user_msr. > > * testsuite/gas/i386/i386.exp: Run USER_MSR tests. > > * testsuite/gas/i386/x86-64.exp: Ditto. > > * testsuite/gas/i386/user_msr-inval.l: New test. > > * testsuite/gas/i386/user_msr-inval.s: Ditto. > > * testsuite/gas/i386/x86-64-user_msr-intel.d: Ditto. > > * testsuite/gas/i386/x86-64-user_msr-inval.l: New test. > > * testsuite/gas/i386/x86-64-user_msr-inval.s: New test. > > * testsuite/gas/i386/x86-64-user_msr.d: Ditto. > > * testsuite/gas/i386/x86-64-user_msr.s: Ditto. > > > > opcodes/ChangeLog: > > * i386-dis.c (struct instr_info): Add a new attribute > > has_skipped_modrm. > > (Gq): New. > > (Rq): Ditto. > > (q_mm_mode): Ditto. > > (Nq): Change mode from q_mode to q_mm_mode. > > (VEX_LEN_TABLE): > > (get_valid_dis386): Add VEX_MAP7 in VEX prefix. > > and handle the map7_f8 for save space. > > (OP_Skip_MODRM): Set has_skipped_modrm. > > (OP_E): Skip codep++ when has skipped modrm byte. > > (OP_R): Support q_mode and q_mm_mode. > > (REG_VEX_MAP7_F8_L_0_W_0): New. > > (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64): Ditto. > > (X86_64_VEX_MAP7_F8_L_0_W_0_R_0): Ditto. > > (VEX_LEN_MAP7_F8): Ditto. > > (VEX_W_MAP7_F8_L_0): Ditto. > > (MOD_0F38F8): Ditto. > > (PREFIX_0F38F8_M_0): Ditto. > > (PREFIX_0F38F8_M_1_X86_64): Ditto. > > (X86_64_0F38F8_M_1): Ditto. > > (PREFIX_0F38F8): Remove. > > (prefix_table): Add PREFIX_0F38F8_M_1_X86_64. > > Remove PREFIX_0F38F8. > > (reg_table): Add REG_VEX_MAP7_F8_L_0_W_0, > > PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64. > > (x86_64_table): Add X86_64_0F38F8_PREFIX_3_M_1, > > X86_64_VEX_MAP7_F8_L_0_W_0_R_0 and X86_64_0F38F8_M_1. > > (vex_table): Add VEX_MAP7. > > (vex_len_table): Add VEX_LEN_MAP7_F8, > > VEX_W_MAP7_F8_L_0. > > (mod_table): New entry for USER_MSR and > > add MOD_0F38F8. > > * i386-gen.c (cpu_flag_init): Add CPU_USER_MSR_FLAGS and > > CPU_ANY_USER_MSR_FLAGS. Add add VEXMAP7. > > * i386-init.h: Regenerated. > > * i386-mnem.h: Ditto. > > * i386-opc.h (SPACE_VEXMAP7): New. > > (CPU_USER_MSR_FLAGS): Ditoo. > > (CPU_ANY_USER_MSR_FLAGS): Ditto. > > (i386_cpu_flags): Add cpuuser_msr. > > * i386-opc.tbl: Add USER_MSR instructions. > > * i386-tbl.h: Regenerated. > > Okay. Going forward though please make sure that patches have a useful > description (beyond the ChangeLog entries). Thanks, have changed descriptions and upstreamed to the master branch. BRs, Lin ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH][v6] Support Intel USER_MSR 2023-10-31 2:14 ` [PATCH][v6] " Hu, Lin1 2023-10-31 8:03 ` Jan Beulich @ 2023-11-14 7:14 ` Jan Beulich 2023-11-15 3:09 ` Hu, Lin1 1 sibling, 1 reply; 33+ messages in thread From: Jan Beulich @ 2023-11-14 7:14 UTC (permalink / raw) To: Hu, Lin1, Lili Cui; +Cc: hongjiu.lu, binutils On 31.10.2023 03:14, Hu, Lin1 wrote: > @@ -3346,3 +3348,12 @@ erets, 0xf20f01ca, FRED|x64, NoSuf, {} > eretu, 0xf30f01ca, FRED|x64, NoSuf, {} > > // FRED instructions end. > + > +// USER_MSR instructions. > + > +urdmsr, 0xf20f38f8, USER_MSR|x64, RegMem|NoSuf|NoRex64, { Reg64, Reg64 } > +urdmsr, 0xf2f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 } > +uwrmsr, 0xf30f38f8, USER_MSR|x64, Modrm|NoSuf|NoRex64, { Reg64, Reg64 } > +uwrmsr, 0xf3f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Reg64, Imm32 } Actually I think the choice of Reg64 here for the operand specifying the MSR index is misleading, even if in line with what the doc presently says in the Opcode / Instruction column. For both insns the description says that only the low 32 bits are used (and the Exceptions section confirms this). Such operands, however, are expressed as Reg32 everywhere else. I'd like to suggest that the spec be adjusted, and I'm heavily inclined to change binutils regardless. Thoughts? Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH][v6] Support Intel USER_MSR 2023-11-14 7:14 ` Jan Beulich @ 2023-11-15 3:09 ` Hu, Lin1 2023-11-15 3:34 ` Jiang, Haochen 2023-11-15 7:48 ` Jan Beulich 0 siblings, 2 replies; 33+ messages in thread From: Hu, Lin1 @ 2023-11-15 3:09 UTC (permalink / raw) To: Beulich, Jan, Cui, Lili; +Cc: Lu, Hongjiu, binutils > -----Original Message----- > From: Jan Beulich <jbeulich@suse.com> > Sent: Tuesday, November 14, 2023 3:15 PM > To: Hu, Lin1 <lin1.hu@intel.com>; Cui, Lili <lili.cui@intel.com> > Cc: Lu, Hongjiu <hongjiu.lu@intel.com>; binutils@sourceware.org > Subject: Re: [PATCH][v6] Support Intel USER_MSR > > On 31.10.2023 03:14, Hu, Lin1 wrote: > > @@ -3346,3 +3348,12 @@ erets, 0xf20f01ca, FRED|x64, NoSuf, {} eretu, > > 0xf30f01ca, FRED|x64, NoSuf, {} > > > > // FRED instructions end. > > + > > +// USER_MSR instructions. > > + > > +urdmsr, 0xf20f38f8, USER_MSR|x64, RegMem|NoSuf|NoRex64, { Reg64, > > +Reg64 } urdmsr, 0xf2f8/0, USER_MSR|x64, > > +Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 } uwrmsr, > > +0xf30f38f8, USER_MSR|x64, Modrm|NoSuf|NoRex64, { Reg64, Reg64 } > > +uwrmsr, 0xf3f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|NoSuf, > { > > +Reg64, Imm32 } > > Actually I think the choice of Reg64 here for the operand specifying the MSR > index is misleading, even if in line with what the doc presently says in the > Opcode / Instruction column. For both insns the description says that only the > low 32 bits are used (and the Exceptions section confirms this). Such operands, > however, are expressed as Reg32 everywhere else. I'd like to suggest that the > spec be adjusted, and I'm heavily inclined to change binutils regardless. Thoughts? Can you give some examples about such operands are expressed as Reg32. I can go ahead and discuss it internally. May need to wait for HJ for final confirmation. BRs, Lin ^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH][v6] Support Intel USER_MSR 2023-11-15 3:09 ` Hu, Lin1 @ 2023-11-15 3:34 ` Jiang, Haochen 2023-11-15 7:36 ` Jan Beulich 2023-11-15 7:48 ` Jan Beulich 1 sibling, 1 reply; 33+ messages in thread From: Jiang, Haochen @ 2023-11-15 3:34 UTC (permalink / raw) To: Hu, Lin1, Beulich, Jan, Cui, Lili; +Cc: Lu, Hongjiu, binutils > > > + > > > +// USER_MSR instructions. > > > + > > > +urdmsr, 0xf20f38f8, USER_MSR|x64, RegMem|NoSuf|NoRex64, > { Reg64, > > > +Reg64 } urdmsr, 0xf2f8/0, USER_MSR|x64, > > > +Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 } uwrmsr, > > > +0xf30f38f8, USER_MSR|x64, Modrm|NoSuf|NoRex64, { Reg64, Reg64 } > > > +uwrmsr, 0xf3f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|NoSuf, > > { > > > +Reg64, Imm32 } > > > > Actually I think the choice of Reg64 here for the operand specifying the MSR > > index is misleading, even if in line with what the doc presently says in the > > Opcode / Instruction column. For both insns the description says that only the > > low 32 bits are used (and the Exceptions section confirms this). Such operands, > > however, are expressed as Reg32 everywhere else. I'd like to suggest that the > > spec be adjusted, and I'm heavily inclined to change binutils regardless. Thoughts? I suppose the reason why it is using Reg64 is because when the other operand is register, it is rare not to align the register size. I checked SDE and ISE and only got one case. And this reg size is inherited from that. However, it might be a point and as Lin said a sync with HW team is needed. Thx, Haochen > > Can you give some examples about such operands are expressed as Reg32. I > can go ahead and discuss it internally. May need to wait for HJ for final > confirmation. > > BRs, > Lin ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH][v6] Support Intel USER_MSR 2023-11-15 3:34 ` Jiang, Haochen @ 2023-11-15 7:36 ` Jan Beulich 2023-11-15 7:41 ` Jiang, Haochen 0 siblings, 1 reply; 33+ messages in thread From: Jan Beulich @ 2023-11-15 7:36 UTC (permalink / raw) To: Jiang, Haochen; +Cc: Lu, Hongjiu, binutils, Hu, Lin1, Cui, Lili On 15.11.2023 04:34, Jiang, Haochen wrote: >>>> + >>>> +// USER_MSR instructions. >>>> + >>>> +urdmsr, 0xf20f38f8, USER_MSR|x64, RegMem|NoSuf|NoRex64, >> { Reg64, >>>> +Reg64 } urdmsr, 0xf2f8/0, USER_MSR|x64, >>>> +Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 } uwrmsr, >>>> +0xf30f38f8, USER_MSR|x64, Modrm|NoSuf|NoRex64, { Reg64, Reg64 } >>>> +uwrmsr, 0xf3f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|NoSuf, >>> { >>>> +Reg64, Imm32 } >>> >>> Actually I think the choice of Reg64 here for the operand specifying the MSR >>> index is misleading, even if in line with what the doc presently says in the >>> Opcode / Instruction column. For both insns the description says that only the >>> low 32 bits are used (and the Exceptions section confirms this). Such operands, >>> however, are expressed as Reg32 everywhere else. I'd like to suggest that the >>> spec be adjusted, and I'm heavily inclined to change binutils regardless. Thoughts? > > I suppose the reason why it is using Reg64 is because when the other operand is > register, it is rare not to align the register size. I checked SDE and ISE and only > got one case. And this reg size is inherited from that. Only one? I know of two (MOVSX and MOVZX) without even needing to go look. Both registers matching in size is sensible only if both also express the same kind of entity. (Moves between GPRs and MM/XMM registers are other examples, just that there it's also register "kind" that's different.) Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH][v6] Support Intel USER_MSR 2023-11-15 7:36 ` Jan Beulich @ 2023-11-15 7:41 ` Jiang, Haochen 0 siblings, 0 replies; 33+ messages in thread From: Jiang, Haochen @ 2023-11-15 7:41 UTC (permalink / raw) To: Beulich, Jan; +Cc: Lu, Hongjiu, binutils, Hu, Lin1, Cui, Lili > On 15.11.2023 04:34, Jiang, Haochen wrote: > >>>> + > >>>> +// USER_MSR instructions. > >>>> + > >>>> +urdmsr, 0xf20f38f8, USER_MSR|x64, RegMem|NoSuf|NoRex64, > >> { Reg64, > >>>> +Reg64 } urdmsr, 0xf2f8/0, USER_MSR|x64, > >>>> +Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 } uwrmsr, > >>>> +0xf30f38f8, USER_MSR|x64, Modrm|NoSuf|NoRex64, { Reg64, > Reg64 } > >>>> +uwrmsr, 0xf3f8/0, USER_MSR|x64, > Modrm|Vex128|VexMap7|VexW0|NoSuf, > >>> { > >>>> +Reg64, Imm32 } > >>> > >>> Actually I think the choice of Reg64 here for the operand specifying the > MSR > >>> index is misleading, even if in line with what the doc presently says in the > >>> Opcode / Instruction column. For both insns the description says that only > the > >>> low 32 bits are used (and the Exceptions section confirms this). Such > operands, > >>> however, are expressed as Reg32 everywhere else. I'd like to suggest that > the > >>> spec be adjusted, and I'm heavily inclined to change binutils regardless. > Thoughts? > > > > I suppose the reason why it is using Reg64 is because when the other > operand is > > register, it is rare not to align the register size. I checked SDE and ISE and only > > got one case. And this reg size is inherited from that. > > Only one? I know of two (MOVSX and MOVZX) without even needing to go > look. Oops, missing that due to the search string. There could be more. > Both registers matching in size is sensible only if both also express the > same kind of entity. (Moves between GPRs and MM/XMM registers are other > examples, just that there it's also register "kind" that's different.) That is the point we need to sync with our internal team. Thx, Haochen > > Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH][v6] Support Intel USER_MSR 2023-11-15 3:09 ` Hu, Lin1 2023-11-15 3:34 ` Jiang, Haochen @ 2023-11-15 7:48 ` Jan Beulich 1 sibling, 0 replies; 33+ messages in thread From: Jan Beulich @ 2023-11-15 7:48 UTC (permalink / raw) To: Hu, Lin1; +Cc: Lu, Hongjiu, binutils, Cui, Lili On 15.11.2023 04:09, Hu, Lin1 wrote: >> -----Original Message----- >> From: Jan Beulich <jbeulich@suse.com> >> Sent: Tuesday, November 14, 2023 3:15 PM >> To: Hu, Lin1 <lin1.hu@intel.com>; Cui, Lili <lili.cui@intel.com> >> Cc: Lu, Hongjiu <hongjiu.lu@intel.com>; binutils@sourceware.org >> Subject: Re: [PATCH][v6] Support Intel USER_MSR >> >> On 31.10.2023 03:14, Hu, Lin1 wrote: >>> @@ -3346,3 +3348,12 @@ erets, 0xf20f01ca, FRED|x64, NoSuf, {} eretu, >>> 0xf30f01ca, FRED|x64, NoSuf, {} >>> >>> // FRED instructions end. >>> + >>> +// USER_MSR instructions. >>> + >>> +urdmsr, 0xf20f38f8, USER_MSR|x64, RegMem|NoSuf|NoRex64, { Reg64, >>> +Reg64 } urdmsr, 0xf2f8/0, USER_MSR|x64, >>> +Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 } uwrmsr, >>> +0xf30f38f8, USER_MSR|x64, Modrm|NoSuf|NoRex64, { Reg64, Reg64 } >>> +uwrmsr, 0xf3f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|NoSuf, >> { >>> +Reg64, Imm32 } >> >> Actually I think the choice of Reg64 here for the operand specifying the MSR >> index is misleading, even if in line with what the doc presently says in the >> Opcode / Instruction column. For both insns the description says that only the >> low 32 bits are used (and the Exceptions section confirms this). Such operands, >> however, are expressed as Reg32 everywhere else. I'd like to suggest that the >> spec be adjusted, and I'm heavily inclined to change binutils regardless. Thoughts? > > Can you give some examples about such operands are expressed as Reg32. Strictly speaking even basic insns like MOV demonstrate that, especially in AT&T syntax (which of course the SDM doesn't use), where in principle it would be possible to have movl %rcx, %rdx Yet even beyond that a basic example is still MOV, but in its to-selector- register form (just that there we're talking of Reg16, not Reg32): mov ds, ax The SDM also lists mov ds, rax but for the case of a (pointless) REX.W prefix (and wrongly mentioning m64 there, when only 16 bits will be accessed, i.e. no different from the store form). I could go further and mention examples like PEXTR{D,Q} or PINSR{D,Q}. The pattern of used register size being expressed properly in insn operands is pretty uniform; exceptions (sadly) exist, but imo it would be better to avoid introducing more. > I can go ahead and discuss it internally. Thanks for doing so. Jan ^ permalink raw reply [flat|nested] 33+ messages in thread
[parent not found: <2b4a78d3-a4e1-9fc3-c143-63bef46b276d@suse.co>]
* [PATCH][v5] Support Intel USER_MSR [not found] <2b4a78d3-a4e1-9fc3-c143-63bef46b276d@suse.co> @ 2023-10-26 11:24 ` Hu, Lin1 0 siblings, 0 replies; 33+ messages in thread From: Hu, Lin1 @ 2023-10-26 11:24 UTC (permalink / raw) To: binutils; +Cc: JBeulich, hongjiu.lu gas/ChangeLog: * NEWS: Support Intel USER_MSR. * config/tc-i386.c: Add user_msr and add VEXMAP7 in opc_spc and build_vex_prefix. (build_modrm_byte): Swap Operands for USER_MSR. * doc/c-i386.texi: Document .user_msr. * testsuite/gas/i386/i386.exp: Run USER_MSR tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/user_msr-inval.l: New test. * testsuite/gas/i386/user_msr-inval.s: Ditto. * testsuite/gas/i386/x86-64-user_msr-intel.d: Ditto. * testsuite/gas/i386/x86-64-user_msr.d: Ditto. * testsuite/gas/i386/x86-64-user_msr.s: Ditto. opcodes/ChangeLog: * i386-dis.c (get32_operand0): Add a new function to get operand0 that is IMM32. (Gq): New. (Id0): Ditto. (get_valid_dis386): Add VEX_MAP7 in VEX prefix. (OP_I): Handle d_0_mode. (d_0_mode): New. (REG_VEX_MAP7_F8_L_0_W_0): New. (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64): Ditto. (X86_64_VEX_MAP7_F8_L_0_W_0_R_0): Ditto. (VEX_MAP7): Ditto. (VEX_LEN_MAP7_F8): Ditto. (VEX_W_MAP7_F8_L_0): Ditto. (MOD_0F38F8): Ditto. (PREFIX_0F38F8_M_0): Ditto. (PREFIX_0F38F8_M_1_X86_64): Ditto. (X86_64_0F38F8_M_1): Ditto. (PREFIX_0F38F8): Remove. (prefix_table): Add PREFIX_0F38F8_M_1_X86_64. Remove PREFIX_0F38F8. (reg_table): Add REG_VEX_MAP7_F8_L_0_W_0, PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64. (x86_64_table): Add X86_64_0F38F8_PREFIX_3_M_1, X86_64_VEX_MAP7_F8_L_0_W_0_R_0 and X86_64_0F38F8_M_1. (vex_table): Add VEX_MAP7. (vex_len_table): Add VEX_LEN_MAP7_F8, VEX_W_MAP7_F8_L_0. (mod_table): New entry for USER_MSR and add MOD_0F38F8. * i386-gen.c (cpu_flag_init): Add CPU_USER_MSR_FLAGS and CPU_ANY_USER_MSR_FLAGS. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (SPACE_VEXMAP7): New. (SWAP_SOURCE_DEST): Ditto. (CPU_USER_MSR_FLAGS): Ditoo. (CPU_ANY_USER_MSR_FLAGS): Ditto. (i386_cpu_flags): Add cpuuser_msr. * i386-opc.tbl: Add USER_MSR instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 2 + gas/config/tc-i386.c | 46 +- gas/doc/c-i386.texi | 3 +- gas/testsuite/gas/i386/i386.exp | 1 + gas/testsuite/gas/i386/user_msr-inval.l | 3 + gas/testsuite/gas/i386/user_msr-inval.s | 6 + .../gas/i386/x86-64-user_msr-intel.d | 46 + .../gas/i386/x86-64-user_msr-inval.l | 9 + .../gas/i386/x86-64-user_msr-inval.s | 12 + gas/testsuite/gas/i386/x86-64-user_msr.d | 46 + gas/testsuite/gas/i386/x86-64-user_msr.s | 42 + gas/testsuite/gas/i386/x86-64.exp | 3 + opcodes/i386-dis.c | 96 +- opcodes/i386-gen.c | 2 + opcodes/i386-init.h | 816 +++++------ opcodes/i386-mnem.h | 1278 +++++++++-------- opcodes/i386-opc.h | 5 + opcodes/i386-opc.tbl | 11 + opcodes/i386-tbl.h | 272 ++-- 19 files changed, 1528 insertions(+), 1171 deletions(-) create mode 100644 gas/testsuite/gas/i386/user_msr-inval.l create mode 100644 gas/testsuite/gas/i386/user_msr-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr.d create mode 100644 gas/testsuite/gas/i386/x86-64-user_msr.s diff --git a/gas/NEWS b/gas/NEWS index 71a1269b893..ab0e7813f27 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel USER_MSR instructions. + * Add support for Intel AVX10.1. * Add support for Intel PBNDKB instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 714354d5116..2cf0ffc3608 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1164,6 +1164,7 @@ static const arch_entry cpu_arch[] = VECARCH (sm4, SM4, ANY_SM4, reset), SUBARCH (pbndkb, PBNDKB, PBNDKB, false), VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set), + SUBARCH (user_msr, USER_MSR, USER_MSR, false), }; #undef SUBARCH @@ -2504,7 +2505,10 @@ smallest_imm_type (offsetT num) t.bitfield.imm8 = 1; t.bitfield.imm8s = 1; t.bitfield.imm16 = 1; - t.bitfield.imm32 = 1; + if (flag_code != CODE_64BIT) + t.bitfield.imm32 = 1; + else if (fits_in_unsigned_long (num)) + t.bitfield.imm32 = 1; t.bitfield.imm32s = 1; } else if (fits_in_unsigned_byte (num)) @@ -2517,12 +2521,18 @@ smallest_imm_type (offsetT num) else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) { t.bitfield.imm16 = 1; - t.bitfield.imm32 = 1; + if (flag_code != CODE_64BIT) + t.bitfield.imm32 = 1; + else if (fits_in_unsigned_long (num)) + t.bitfield.imm32 = 1; t.bitfield.imm32s = 1; } else if (fits_in_signed_long (num)) { - t.bitfield.imm32 = 1; + if (flag_code != CODE_64BIT) + t.bitfield.imm32 = 1; + else if (fits_in_unsigned_long (num)) + t.bitfield.imm32 = 1; t.bitfield.imm32s = 1; } else if (fits_in_unsigned_long (num)) @@ -3863,6 +3873,7 @@ build_vex_prefix (const insn_template *t) case SPACE_0F: case SPACE_0F38: case SPACE_0F3A: + case SPACE_VEXMAP7: i.vex.bytes[0] = 0xc4; break; case SPACE_XOP08: @@ -5158,6 +5169,7 @@ md_assemble (char *line) const char *end, *pass1_mnem = NULL; enum i386_error pass1_err = 0; const insn_template *t; + int op; /* Initialize globals. */ current_templates = NULL; @@ -5232,8 +5244,23 @@ md_assemble (char *line) && (t->mnem_off == MN_extrq || t->mnem_off == MN_insertq)) swap_2_operands (0, 1); + /* For USER_MSR instructions, imm32 stands for the name of an model specific + register (MSR). So we need to avoid set i.types[op].bitfield.imm32 = 0, + when guess_suffix == QWORD_MNEM_SUFFIX. For time-saving reasons, + we specialize the USER_MSR and make only the necessary judgments. */ if (i.imm_operands) - optimize_imm (); + { + if (!is_cpu(current_templates->start, CpuUSER_MSR)) + optimize_imm (); + else + { + for (op = i.operands; --op >= 0;) + { + if (operand_type_check(i.types[op], imm)) + i.types[op] = smallest_imm_type (i.op[op].imms->X_add_number); + } + } + } if (i.disp_operands && !optimize_disp (t)) return; @@ -7566,6 +7593,17 @@ match_template (char mnem_suffix) break; } + /* This pattern aims to put the unusually placed imm operand to a usual + place. The constraints are currently only adapted to uwrmsr, and may + need further tweaking when new similar instructions become available. */ + if (i.imm_operands && i.imm_operands < i.operands + && operand_type_check (operand_types[i.operands - 1], imm)) + { + i.tm.operand_types[0] = operand_types[i.operands - 1]; + i.tm.operand_types[i.operands - 1] = operand_types[0]; + swap_2_operands(0, i.operands - 1); + } + return t; } diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index b04e1b00b4b..03ee980bef7 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -216,6 +216,7 @@ accept various extension mnemonics. For example, @code{avx10.1/512}, @code{avx10.1/256}, @code{avx10.1/128}, +@code{user_msr}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1650,7 +1651,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} @item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs} @item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4} -@item @samp{.pbndkb} +@item @samp{.pbndkb} @tab @samp{.user_msr} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index ee74bcd4615..81ce1e38b10 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -509,6 +509,7 @@ if [gas_32_check] then { run_dump_test "sm4" run_dump_test "sm4-intel" run_list_test "pbndkb-inval" + run_list_test "user_msr-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" diff --git a/gas/testsuite/gas/i386/user_msr-inval.l b/gas/testsuite/gas/i386/user_msr-inval.l new file mode 100644 index 00000000000..54c48f1953b --- /dev/null +++ b/gas/testsuite/gas/i386/user_msr-inval.l @@ -0,0 +1,3 @@ +.* Assembler messages: +.*:5: Error: `urdmsr' is only supported in 64-bit mode +.*:6: Error: `uwrmsr' is only supported in 64-bit mode diff --git a/gas/testsuite/gas/i386/user_msr-inval.s b/gas/testsuite/gas/i386/user_msr-inval.s new file mode 100644 index 00000000000..1682a1e8d79 --- /dev/null +++ b/gas/testsuite/gas/i386/user_msr-inval.s @@ -0,0 +1,6 @@ +# Check Illegal 32bit USER_MSR instructions + + .text +_start: + urdmsr %r12, %r14 + uwrmsr %r12, %r14 diff --git a/gas/testsuite/gas/i386/x86-64-user_msr-intel.d b/gas/testsuite/gas/i386/x86-64-user_msr-intel.d new file mode 100644 index 00000000000..e68b5eacfa9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr-intel.d @@ -0,0 +1,46 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 USER_MSR insns (Intel disassembly) +#source: x86-64-user_msr.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr r12,r14 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr rax,r14 +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr r12,rdx +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr rax,rdx +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr r12,0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr rax,0x3120f0f +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 7f 00 00 00\s+urdmsr r12,0x7f +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 ff 7f 00 00\s+urdmsr r12,0x7fff +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 00 00 00 80\s+urdmsr r12,0x80000000 +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr r14,r12 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr r14,rax +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr rdx,r12 +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr rdx,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr 0x3120f0f,r12 +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr 0x3120f0f,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 7f 00 00 00\s+uwrmsr 0x7f,r12 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 ff 7f 00 00\s+uwrmsr 0x7fff,r12 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 00 00 00 80\s+uwrmsr 0x80000000,r12 +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr r12,r14 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr rax,r14 +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr r12,rdx +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr rax,rdx +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr r12,0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr rax,0x3120f0f +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 7f 00 00 00\s+urdmsr r12,0x7f +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 ff 7f 00 00\s+urdmsr r12,0x7fff +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 00 00 00 80\s+urdmsr r12,0x80000000 +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr r14,r12 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr r14,rax +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr rdx,r12 +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr rdx,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr 0x3120f0f,r12 +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr 0x3120f0f,rax +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 7f 00 00 00\s+uwrmsr 0x7f,r12 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 ff 7f 00 00\s+uwrmsr 0x7fff,r12 +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 00 00 00 80\s+uwrmsr 0x80000000,r12 diff --git a/gas/testsuite/gas/i386/x86-64-user_msr-inval.l b/gas/testsuite/gas/i386/x86-64-user_msr-inval.l new file mode 100644 index 00000000000..9eb3044e16e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr-inval.l @@ -0,0 +1,9 @@ +.* Assembler messages: +.*:5: Error: operand type mismatch for `urdmsr' +.*:6: Error: operand type mismatch for `urdmsr' +.*:7: Error: operand type mismatch for `urdmsr' +.*:8: Error: operand type mismatch for `urdmsr' +.*:9: Error: operand type mismatch for `uwrmsr' +.*:10: Error: operand type mismatch for `uwrmsr' +.*:11: Error: operand type mismatch for `uwrmsr' +.*:12: Error: operand type mismatch for `uwrmsr' diff --git a/gas/testsuite/gas/i386/x86-64-user_msr-inval.s b/gas/testsuite/gas/i386/x86-64-user_msr-inval.s new file mode 100644 index 00000000000..e7b6d6eea83 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr-inval.s @@ -0,0 +1,12 @@ +# Check Illegal 64bit USER_MSR instructions + + .text +_start: + urdmsr $-1, %r14 + urdmsr $-32767, %r14 + urdmsr $-2147483648, %r14 + urdmsr $0x7fffffffffffffff, %r14 + uwrmsr %r12, $-1 + uwrmsr %r12, $-32767 + uwrmsr %r12, $-2147483648 + uwrmsr %r12, $0x7fffffffffffffff diff --git a/gas/testsuite/gas/i386/x86-64-user_msr.d b/gas/testsuite/gas/i386/x86-64-user_msr.d new file mode 100644 index 00000000000..41f29718ab0 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr.d @@ -0,0 +1,46 @@ +#as: +#objdump: -dw +#name: x86_64 USER_MSR insns +#source: x86-64-user_msr.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr %r14,%r12 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr %r14,%rax +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr %rdx,%r12 +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr %rdx,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr \$0x3120f0f,%r12 +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr \$0x3120f0f,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 7f 00 00 00\s+urdmsr \$0x7f,%r12 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 ff 7f 00 00\s+urdmsr \$0x7fff,%r12 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 00 00 00 80\s+urdmsr \$0x80000000,%r12 +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr %r12,%r14 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr %rax,%r14 +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr %r12,%rdx +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr %rax,%rdx +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr %r12,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr %rax,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 7f 00 00 00\s+uwrmsr %r12,\$0x7f +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 ff 7f 00 00\s+uwrmsr %r12,\$0x7fff +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 00 00 00 80\s+uwrmsr %r12,\$0x80000000 +\s*[a-f0-9]+:\s*f2 45 0f 38 f8 f4\s+urdmsr %r14,%r12 +\s*[a-f0-9]+:\s*f2 44 0f 38 f8 f0\s+urdmsr %r14,%rax +\s*[a-f0-9]+:\s*f2 41 0f 38 f8 d4\s+urdmsr %rdx,%r12 +\s*[a-f0-9]+:\s*f2 0f 38 f8 d0\s+urdmsr %rdx,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 0f 0f 12 03\s+urdmsr \$0x3120f0f,%r12 +\s*[a-f0-9]+:\s*c4 e7 7b f8 c0 0f 0f 12 03\s+urdmsr \$0x3120f0f,%rax +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 7f 00 00 00\s+urdmsr \$0x7f,%r12 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 ff 7f 00 00\s+urdmsr \$0x7fff,%r12 +\s*[a-f0-9]+:\s*c4 c7 7b f8 c4 00 00 00 80\s+urdmsr \$0x80000000,%r12 +\s*[a-f0-9]+:\s*f3 45 0f 38 f8 f4\s+uwrmsr %r12,%r14 +\s*[a-f0-9]+:\s*f3 44 0f 38 f8 f0\s+uwrmsr %rax,%r14 +\s*[a-f0-9]+:\s*f3 41 0f 38 f8 d4\s+uwrmsr %r12,%rdx +\s*[a-f0-9]+:\s*f3 0f 38 f8 d0\s+uwrmsr %rax,%rdx +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 0f 0f 12 03\s+uwrmsr %r12,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 e7 7a f8 c0 0f 0f 12 03\s+uwrmsr %rax,\$0x3120f0f +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 7f 00 00 00\s+uwrmsr %r12,\$0x7f +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 ff 7f 00 00\s+uwrmsr %r12,\$0x7fff +\s*[a-f0-9]+:\s*c4 c7 7a f8 c4 00 00 00 80\s+uwrmsr %r12,\$0x80000000 diff --git a/gas/testsuite/gas/i386/x86-64-user_msr.s b/gas/testsuite/gas/i386/x86-64-user_msr.s new file mode 100644 index 00000000000..63bc6c1352c --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s @@ -0,0 +1,42 @@ +# Check 64bit USER_MSR instructions + + .text +_start: + urdmsr %r14, %r12 + urdmsr %r14, %rax + urdmsr %rdx, %r12 + urdmsr %rdx, %rax + urdmsr $51515151, %r12 + urdmsr $51515151, %rax + urdmsr $0x7f, %r12 + urdmsr $0x7fff, %r12 + urdmsr $0x80000000, %r12 + uwrmsr %r12, %r14 + uwrmsr %rax, %r14 + uwrmsr %r12, %rdx + uwrmsr %rax, %rdx + uwrmsr %r12, $51515151 + uwrmsr %rax, $51515151 + uwrmsr %r12, $0x7f + uwrmsr %r12, $0x7fff + uwrmsr %r12, $0x80000000 + + .intel_syntax noprefix + urdmsr r12, r14 + urdmsr rax, r14 + urdmsr r12, rdx + urdmsr rax, rdx + urdmsr r12, 51515151 + urdmsr rax, 51515151 + urdmsr r12, 0x7f + urdmsr r12, 0x7fff + urdmsr r12, 0x80000000 + uwrmsr r14, r12 + uwrmsr r14, rax + uwrmsr rdx, r12 + uwrmsr rdx, rax + uwrmsr 51515151, r12 + uwrmsr 51515151, rax + uwrmsr 0x7f, r12 + uwrmsr 0x7fff, r12 + uwrmsr 0x80000000, r12 diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 52711cdcf6f..22fdb0d9bcd 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -450,6 +450,9 @@ run_dump_test "x86-64-sm4" run_dump_test "x86-64-sm4-intel" run_dump_test "x86-64-pbndkb" run_dump_test "x86-64-pbndkb-intel" +run_dump_test "x86-64-user_msr" +run_dump_test "x86-64-user_msr-intel" +run_list_test "x86-64-user_msr-inval" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 87ecf0f5e23..2e2043d467b 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -221,6 +221,9 @@ struct instr_info /* Record whether EVEX masking is used incorrectly. */ bool illegal_masking; + /* Record whether the modrm byte has been skipped. */ + bool has_skipped_modrm; + unsigned char op_ad; signed char op_index[MAX_OPERANDS]; bool op_riprel[MAX_OPERANDS]; @@ -418,6 +421,7 @@ fetch_error (const instr_info *ins) #define Gv { OP_G, v_mode } #define Gd { OP_G, d_mode } #define Gdq { OP_G, dq_mode } +#define Gq { OP_G, q_mode } #define Gm { OP_G, m_mode } #define Gva { OP_G, va_mode } #define Gw { OP_G, w_mode } @@ -527,7 +531,8 @@ fetch_error (const instr_info *ins) #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } #define Rd { OP_R, d_mode } #define Rdq { OP_R, dq_mode } -#define Nq { OP_R, q_mode } +#define Rq { OP_R, q_mode } +#define Nq { OP_R, q_mm_mode } #define Ux { OP_R, x_mode } #define Uxmm { OP_R, xmm_mode } #define Rxmmq { OP_R, xmmq_mode } @@ -624,6 +629,8 @@ enum d_swap_mode, /* quad word operand */ q_mode, + /* 8-byte MM operand */ + q_mm_mode, /* quad word operand with operand swapped */ q_swap_mode, /* ten-byte operand */ @@ -845,6 +852,7 @@ enum REG_VEX_0FAE, REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0, REG_VEX_0F38F3_L_0, + REG_VEX_MAP7_F8_L_0_W_0, REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, @@ -893,6 +901,7 @@ enum MOD_0FC7_REG_6, MOD_0FC7_REG_7, MOD_0F38DC_PREFIX_1, + MOD_0F38F8, MOD_VEX_0F3849_X86_64_L_0_W_0, }; @@ -1010,7 +1019,8 @@ enum PREFIX_0F38F0, PREFIX_0F38F1, PREFIX_0F38F6, - PREFIX_0F38F8, + PREFIX_0F38F8_M_0, + PREFIX_0F38F8_M_1_X86_64, PREFIX_0F38FA, PREFIX_0F38FB, PREFIX_0F38FC, @@ -1073,6 +1083,7 @@ enum PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0, PREFIX_VEX_0F3AF0_L_0, + PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F6F, @@ -1217,6 +1228,7 @@ enum X86_64_0F18_REG_7_MOD_0, X86_64_0F24, X86_64_0F26, + X86_64_0F38F8_M_1, X86_64_0FC7_REG_6_MOD_3_PREFIX_1, X86_64_VEX_0F3849, @@ -1240,6 +1252,7 @@ enum X86_64_VEX_0F38ED, X86_64_VEX_0F38EE, X86_64_VEX_0F38EF, + X86_64_VEX_MAP7_F8_L_0_W_0_R_0, }; enum @@ -1259,7 +1272,8 @@ enum { VEX_0F = 0, VEX_0F38, - VEX_0F3A + VEX_0F3A, + VEX_MAP7, }; enum @@ -1350,6 +1364,7 @@ enum VEX_LEN_0F3ADE_W_0, VEX_LEN_0F3ADF, VEX_LEN_0F3AF0, + VEX_LEN_MAP7_F8, VEX_LEN_XOP_08_85, VEX_LEN_XOP_08_86, VEX_LEN_XOP_08_87, @@ -1510,6 +1525,7 @@ enum VEX_W_0F3ACE, VEX_W_0F3ACF, VEX_W_0F3ADE, + VEX_W_MAP7_F8_L_0, VEX_W_XOP_08_85_L_0, VEX_W_XOP_08_86_L_0, @@ -2849,6 +2865,10 @@ static const struct dis386 reg_table[][8] = { { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE }, { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE }, }, + /* REG_VEX_MAP7_F8_L_0_W_0 */ + { + { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) }, + }, /* REG_XOP_09_01_L_0 */ { { Bad_Opcode }, @@ -3555,13 +3575,22 @@ static const struct dis386 prefix_table[][4] = { { Bad_Opcode }, }, - /* PREFIX_0F38F8 */ + /* PREFIX_0F38F8_M_0 */ { { Bad_Opcode }, { "enqcmds", { Gva, M }, 0 }, { "movdir64b", { Gva, M }, 0 }, { "enqcmd", { Gva, M }, 0 }, }, + + /* PREFIX_0F38F8_M_1_X86_64 */ + { + { Bad_Opcode }, + { "uwrmsr", { Gq, Rq }, 0 }, + { Bad_Opcode }, + { "urdmsr", { Rq, Gq }, 0 }, + }, + /* PREFIX_0F38FA */ { { Bad_Opcode }, @@ -4014,6 +4043,14 @@ static const struct dis386 prefix_table[][4] = { { "rorxS", { Gdq, Edq, Ib }, 0 }, }, + /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */ + { + { Bad_Opcode }, + { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 }, + { Bad_Opcode }, + { "urdmsr", { Rq, Id }, 0 }, + }, + #include "i386-dis-evex-prefix.h" }; @@ -4322,6 +4359,12 @@ static const struct dis386 x86_64_table[][2] = { { "movZ", { Td, Em }, 0 }, }, + { + /* X86_64_0F38F8_M_1 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) }, + }, + /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */ { { Bad_Opcode }, @@ -4453,6 +4496,13 @@ static const struct dis386 x86_64_table[][2] = { { Bad_Opcode }, { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, }, + + /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */ + { + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) }, + }, + }; static const struct dis386 three_byte_table[][256] = { @@ -4739,7 +4789,7 @@ static const struct dis386 three_byte_table[][256] = { { PREFIX_TABLE (PREFIX_0F38F6) }, { Bad_Opcode }, /* f8 */ - { PREFIX_TABLE (PREFIX_0F38F8) }, + { MOD_TABLE (MOD_0F38F8) }, { "movdiri", { Mdq, Gdq }, PREFIX_OPCODE }, { PREFIX_TABLE (PREFIX_0F38FA) }, { PREFIX_TABLE (PREFIX_0F38FB) }, @@ -7205,6 +7255,11 @@ static const struct dis386 vex_len_table[][2] = { { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) }, }, + /* VEX_LEN_MAP7_F8 */ + { + { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) }, + }, + /* VEX_LEN_XOP_08_85 */ { { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) }, @@ -7811,6 +7866,10 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3ADE */ { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) }, }, + { + /* VEX_W_MAP7_F8_L_0 */ + { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) }, + }, /* VEX_W_XOP_08_85_L_0 */ { { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 }, @@ -8153,6 +8212,11 @@ static const struct dis386 mod_table[][2] = { { "aesenc128kl", { XM, M }, 0 }, { "loadiwkey", { XM, EXx }, 0 }, }, + /* MOD_0F38F8 */ + { + { PREFIX_TABLE (PREFIX_0F38F8_M_0) }, + { X86_64_TABLE (X86_64_0F38F8_M_1) }, + }, { /* MOD_VEX_0F3849_X86_64_L_0_W_0 */ { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) }, @@ -8527,6 +8591,8 @@ static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; /* Fetch error indicator. */ static const struct dis386 err_opcode = { NULL, { XX }, 0 }; +static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) }; + /* Get a pointer to struct dis386 with a valid name. */ static const struct dis386 * @@ -8769,6 +8835,9 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) case 0x3: vex_table_index = VEX_0F3A; break; + case 0x7: + vex_table_index = VEX_MAP7; + break; } ins->codep++; ins->vex.w = *ins->codep & 0x80; @@ -8803,7 +8872,12 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) ins->need_vex = 3; ins->codep++; vindex = *ins->codep++; - dp = &vex_table[vex_table_index][vindex]; + if (vex_table_index != VEX_MAP7) + dp = &vex_table[vex_table_index][vindex]; + else if (vindex == 0xf8) + dp = &map7_f8_opcode; + else + dp = &bad_opcode; ins->end_codep = ins->codep; /* There is no MODRM byte for VEX0F 77. */ if ((vex_table_index != VEX_0F || vindex != 0x77) @@ -11300,6 +11374,7 @@ OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, /* Skip mod/rm byte. */ MODRM_CHECK; ins->codep++; + ins->has_skipped_modrm = true; return true; } @@ -11818,7 +11893,11 @@ OP_E (instr_info *ins, int bytemode, int sizeflag) { /* Skip mod/rm byte. */ MODRM_CHECK; - ins->codep++; + if (!ins->has_skipped_modrm) + { + ins->codep++; + ins->has_skipped_modrm = true; + } if (ins->modrm.mod == 3) { @@ -12623,9 +12702,10 @@ OP_R (instr_info *ins, int bytemode, int sizeflag) { case d_mode: case dq_mode: + case q_mode: case mask_mode: return OP_E (ins, bytemode, sizeflag); - case q_mode: + case q_mm_mode: return OP_EM (ins, x_mode, sizeflag); case xmm_mode: if (ins->vex.length <= 128) diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index cfc5a7a6172..bb58afcbc06 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -380,6 +380,7 @@ static bitfield cpu_flags[] = BITFIELD (RAO_INT), BITFIELD (FRED), BITFIELD (LKGS), + BITFIELD (USER_MSR), BITFIELD (MWAITX), BITFIELD (CLZERO), BITFIELD (OSPKE), @@ -1023,6 +1024,7 @@ process_i386_opcode_modifier (FILE *table, char *mod, unsigned int space, SPACE(0F3A), SPACE(EVEXMAP5), SPACE(EVEXMAP6), + SPACE(VEXMAP7), SPACE(XOP08), SPACE(XOP09), SPACE(XOP0A), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 149ae0e950c..529eb7c41c8 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -223,6 +223,8 @@ enum i386_cpu CpuFRED, /* lkgs instruction required */ CpuLKGS, + /* Intel USER_MSR Instruction support required. */ + CpuUSER_MSR, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -471,6 +473,7 @@ typedef union i386_cpu_flags unsigned int cpurao_int:1; unsigned int cpufred:1; unsigned int cpulkgs:1; + unsigned int cpuuser_msr:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; @@ -966,6 +969,7 @@ typedef struct insn_template 3: 0F3A opcode prefix / space. 5: EVEXMAP5 opcode prefix / space. 6: EVEXMAP6 opcode prefix / space. + 7: VEXMAP7 opcode prefix / space. 8: XOP 08 opcode space. 9: XOP 09 opcode space. A: XOP 0A opcode space. @@ -976,6 +980,7 @@ typedef struct insn_template #define SPACE_0F3A 3 #define SPACE_EVEXMAP5 5 #define SPACE_EVEXMAP6 6 +#define SPACE_VEXMAP7 7 #define SPACE_XOP08 8 #define SPACE_XOP09 9 #define SPACE_XOP0A 0xA diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index e60184ba154..a3426298340 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -112,6 +112,8 @@ #define EVexMap5 OpcodeSpace=SPACE_EVEXMAP5 #define EVexMap6 OpcodeSpace=SPACE_EVEXMAP6 +#define VexMap7 OpcodeSpace=SPACE_VEXMAP7 + #define VexW0 VexW=VEXW0 #define VexW1 VexW=VEXW1 #define VexWIG VexW=VEXWIG @@ -3346,3 +3348,12 @@ erets, 0xf20f01ca, FRED|x64, NoSuf, {} eretu, 0xf30f01ca, FRED|x64, NoSuf, {} // FRED instructions end. + +// USER_MSR instructions. + +urdmsr, 0xf20f38f8, USER_MSR|x64, RegMem|NoSuf|NoRex64, { Reg64, Reg64 } +urdmsr, 0xf2f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 } +uwrmsr, 0xf30f38f8, USER_MSR|x64, Modrm|NoSuf|NoRex64, { Reg64, Reg64 } +uwrmsr, 0xf3f8/0, USER_MSR|x64, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Reg64, Imm32 } + +// USER_MSR instructions end. -- 2.31.1 ^ permalink raw reply [flat|nested] 33+ messages in thread
end of thread, other threads:[~2023-11-15 7:48 UTC | newest]
Thread overview: 33+ messages (download: mbox.gz / follow: Atom feed)
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2023-10-10 7:24 [PATCH] Support Intel USER_MSR Hu, Lin1
2023-10-16 12:11 ` Jan Beulich
2023-10-18 7:51 ` Hu, Lin1
2023-10-19 8:36 ` Jan Beulich
2023-10-24 8:38 ` Hu, Lin1
2023-10-24 8:55 ` Jan Beulich
2023-10-24 10:01 ` Hu, Lin1
2023-10-24 12:02 ` Jan Beulich
2023-10-25 2:01 ` Hu, Lin1
2023-10-25 8:48 ` Jan Beulich
2023-10-25 9:11 ` [PATCH][v3] " Hu, Lin1
2023-10-25 11:43 ` Jan Beulich
2023-10-26 6:14 ` Hu, Lin1
2023-10-26 6:21 ` [PATCH][v4] " Hu, Lin1
2023-10-26 8:31 ` Jan Beulich
2023-10-26 9:08 ` Hu, Lin1
2023-10-26 9:25 ` Jan Beulich
2023-10-26 10:26 ` Hu, Lin1
2023-10-27 9:00 ` [PATCH][v5] " Hu, Lin1
2023-10-27 13:36 ` Jan Beulich
2023-10-30 5:50 ` Hu, Lin1
2023-10-30 8:31 ` Jan Beulich
2023-10-31 1:43 ` Hu, Lin1
2023-10-31 2:14 ` [PATCH][v6] " Hu, Lin1
2023-10-31 8:03 ` Jan Beulich
2023-10-31 8:35 ` Hu, Lin1
2023-11-14 7:14 ` Jan Beulich
2023-11-15 3:09 ` Hu, Lin1
2023-11-15 3:34 ` Jiang, Haochen
2023-11-15 7:36 ` Jan Beulich
2023-11-15 7:41 ` Jiang, Haochen
2023-11-15 7:48 ` Jan Beulich
[not found] <2b4a78d3-a4e1-9fc3-c143-63bef46b276d@suse.co>
2023-10-26 11:24 ` [PATCH][v5] " Hu, Lin1
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