* [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions
@ 2022-01-11 10:47 Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 1/5] RISC-V: Add 'Zfh' and 'Zfhmin' extensions Tsukasa OI
` (6 more replies)
0 siblings, 7 replies; 15+ messages in thread
From: Tsukasa OI @ 2022-01-11 10:47 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This patchset adds support for two recently ratified RISC-V extensions:
- Zfhmin (Half-precision floating point: conversion only)
- Zfh (Half-precision floating point: full arithmetic)
This patchset was intended to be a part of Binutils 2.38 but I was
getting too impatient. I tested this patchset with Spike simulator and
tested that a few programs with fp16 was working nicely. However, this
patchset lacks full testsuite.
The only reason I didn't make one was simple: all of floating point
extensions ('F', 'D' and 'Q') didn't have full testsuite. Thanks to the
fact that this patchset is too late for Binutils 2.38, we have time to
add full testsuite for all floating point extensions.
Also, this patchset lacks pseudoinstructions (intentionally). Possible
pseudoinstructions to implement later would be:
- fmv.h
- fneg.h
- fabs.h
Besides that, we can begin testing 'Zfh' and 'Zfhmin' extensions with
this patchset.
Tsukasa OI (5):
RISC-V: Add 'Zfh' and 'Zfhmin' extensions
RISC-V: Add insn classes for Zfh/Zfhmin extensions
RISC-V: Add 'Zfh' and 'Zfhmin' instructions
RISC-V: Add 'flh' and 'fsh' macro instructions
RISC-V: Add 'Zfh'/'Zfhmin' conflict message
bfd/elfxx-riscv.c | 16 +++++-
gas/config/tc-riscv.c | 10 ++++
include/opcode/riscv-opc.h | 108 +++++++++++++++++++++++++++++++++++++
include/opcode/riscv.h | 6 +++
opcodes/riscv-opc.c | 62 +++++++++++++++++++++
5 files changed, 201 insertions(+), 1 deletion(-)
base-commit: 9ed5be5650ba7c315cd7cfacccc9208de2f555df
--
2.32.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [RFC PATCH 1/5] RISC-V: Add 'Zfh' and 'Zfhmin' extensions
2022-01-11 10:47 [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions Tsukasa OI
@ 2022-01-11 10:48 ` Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 2/5] RISC-V: Add insn classes for Zfh/Zfhmin extensions Tsukasa OI
` (5 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Tsukasa OI @ 2022-01-11 10:48 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds 'Zfh' and 'Zfhmin' extensions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Add implicit subsets.
(riscv_supported_std_z_ext): Add 'Zfh' and 'Zfhmin' extensions.
---
bfd/elfxx-riscv.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 9f52bb545ac..dbe3611304b 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1100,6 +1100,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zvl64b", "zvl32b", check_implicit_always},
{"d", "f", check_implicit_always},
{"f", "zicsr", check_implicit_always},
+ {"zfh", "zfhmin", check_implicit_always},
+ {"zfhmin", "f", check_implicit_always},
{"zqinx", "zdinx", check_implicit_always},
{"zdinx", "zfinx", check_implicit_always},
{"zk", "zkn", check_implicit_always},
@@ -1184,6 +1186,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zdinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zqinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
--
2.32.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [RFC PATCH 2/5] RISC-V: Add insn classes for Zfh/Zfhmin extensions
2022-01-11 10:47 [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 1/5] RISC-V: Add 'Zfh' and 'Zfhmin' extensions Tsukasa OI
@ 2022-01-11 10:48 ` Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 3/5] RISC-V: Add 'Zfh' and 'Zfhmin' instructions Tsukasa OI
` (4 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Tsukasa OI @ 2022-01-11 10:48 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds several instruction classes corresponding 'Zfh',
'Zfhmin' and 'Zfhmin'+'D|Q' extensions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
new instruction classes.
include/ChangeLog:
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
classes INSN_CLASS_ZFH, INSN_CLASS_ZFHMIN,
INSN_CLASS_ZFHMIN_AND_D and INSN_CLASS_ZFHMIN_AND_Q.
---
bfd/elfxx-riscv.c | 10 ++++++++++
include/opcode/riscv.h | 4 ++++
2 files changed, 14 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index dbe3611304b..4f3705ad396 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -2368,6 +2368,16 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
case INSN_CLASS_Q_OR_ZQINX:
return (riscv_subset_supports (rps, "q")
|| riscv_subset_supports (rps, "zqinx"));
+ case INSN_CLASS_ZFH:
+ return riscv_subset_supports (rps, "zfh");
+ case INSN_CLASS_ZFHMIN:
+ return riscv_subset_supports (rps, "zfhmin");
+ case INSN_CLASS_ZFHMIN_AND_D:
+ return (riscv_subset_supports (rps, "zfhmin")
+ && riscv_subset_supports (rps, "d"));
+ case INSN_CLASS_ZFHMIN_AND_Q:
+ return (riscv_subset_supports (rps, "zfhmin")
+ && riscv_subset_supports (rps, "q"));
case INSN_CLASS_ZBA:
return riscv_subset_supports (rps, "zba");
case INSN_CLASS_ZBB:
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 048ab0a5d68..a5da8d0c4e0 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -370,6 +370,10 @@ enum riscv_insn_class
INSN_CLASS_F_OR_ZFINX,
INSN_CLASS_D_OR_ZDINX,
INSN_CLASS_Q_OR_ZQINX,
+ INSN_CLASS_ZFH,
+ INSN_CLASS_ZFHMIN,
+ INSN_CLASS_ZFHMIN_AND_D,
+ INSN_CLASS_ZFHMIN_AND_Q,
INSN_CLASS_ZBA,
INSN_CLASS_ZBB,
INSN_CLASS_ZBC,
--
2.32.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [RFC PATCH 3/5] RISC-V: Add 'Zfh' and 'Zfhmin' instructions
2022-01-11 10:47 [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 1/5] RISC-V: Add 'Zfh' and 'Zfhmin' extensions Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 2/5] RISC-V: Add insn classes for Zfh/Zfhmin extensions Tsukasa OI
@ 2022-01-11 10:48 ` Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 4/5] RISC-V: Add 'flh' and 'fsh' macro instructions Tsukasa OI
` (3 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Tsukasa OI @ 2022-01-11 10:48 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds most of 'Zfh' and 'Zfhmin' instructions including a few
pseudoinstructions.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_FADD_H, MASK_FADD_H, MATCH_FSUB_H,
MASK_FSUB_H, MATCH_FMUL_H, MASK_FMUL_H, MATCH_FDIV_H,
MASK_FDIV_H, MATCH_FSGNJ_H, MASK_FSGNJ_H, MATCH_FSGNJN_H,
MASK_FSGNJN_H, MATCH_FSGNJX_H, MASK_FSGNJX_H, MATCH_FMIN_H,
MASK_FMIN_H, MATCH_FMAX_H, MASK_FMAX_H, MATCH_FCVT_H_S,
MASK_FCVT_H_S, MATCH_FCVT_S_H, MASK_FCVT_S_H, MATCH_FCVT_H_D,
MASK_FCVT_H_D, MATCH_FCVT_D_H, MASK_FCVT_D_H, MATCH_FCVT_H_Q,
MASK_FCVT_H_Q, MATCH_FCVT_Q_H, MASK_FCVT_Q_H, MATCH_FSQRT_H,
MASK_FSQRT_H, MATCH_FLE_H, MASK_FLE_H, MATCH_FLT_H, MASK_FLT_H,
MATCH_FEQ_H, MASK_FEQ_H, MATCH_FCVT_W_H, MASK_FCVT_W_H,
MATCH_FCVT_WU_H, MASK_FCVT_WU_H, MATCH_FCVT_L_H, MASK_FCVT_L_H,
MATCH_FCVT_LU_H, MASK_FCVT_LU_H, MATCH_FMV_X_H, MASK_FMV_X_H,
MATCH_FCLASS_H, MASK_FCLASS_H, MATCH_FCVT_H_W, MASK_FCVT_H_W,
MATCH_FCVT_H_WU, MASK_FCVT_H_WU, MATCH_FCVT_H_L, MASK_FCVT_H_L,
MATCH_FCVT_H_LU, MASK_FCVT_H_LU, MATCH_FMV_H_X, MASK_FMV_H_X,
MATCH_FLH, MASK_FLH, MATCH_FSH, MASK_FSH, MATCH_FMADD_H,
MASK_FMADD_H, MATCH_FMSUB_H, MASK_FMSUB_H, MATCH_FNMSUB_H,
MASK_FNMSUB_H, MATCH_FNMADD_H, MASK_FNMADD_H): New instruction
macros.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add 'Zfh' and 'Zfhmin'
instructions including a few pseudoinstructions.
---
include/opcode/riscv-opc.h | 108 +++++++++++++++++++++++++++++++++++++
opcodes/riscv-opc.c | 60 +++++++++++++++++++++
2 files changed, 168 insertions(+)
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 0b8cc6c7ddb..b6d304cdfdd 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -267,6 +267,38 @@
#define MASK_CSRRSI 0x707f
#define MATCH_CSRRCI 0x7073
#define MASK_CSRRCI 0x707f
+#define MATCH_FADD_H 0x4000053
+#define MASK_FADD_H 0xfe00007f
+#define MATCH_FSUB_H 0xc000053
+#define MASK_FSUB_H 0xfe00007f
+#define MATCH_FMUL_H 0x14000053
+#define MASK_FMUL_H 0xfe00007f
+#define MATCH_FDIV_H 0x1c000053
+#define MASK_FDIV_H 0xfe00007f
+#define MATCH_FSGNJ_H 0x24000053
+#define MASK_FSGNJ_H 0xfe00707f
+#define MATCH_FSGNJN_H 0x24001053
+#define MASK_FSGNJN_H 0xfe00707f
+#define MATCH_FSGNJX_H 0x24002053
+#define MASK_FSGNJX_H 0xfe00707f
+#define MATCH_FMIN_H 0x2c000053
+#define MASK_FMIN_H 0xfe00707f
+#define MATCH_FMAX_H 0x2c001053
+#define MASK_FMAX_H 0xfe00707f
+#define MATCH_FCVT_H_S 0x44000053
+#define MASK_FCVT_H_S 0xfff0007f
+#define MATCH_FCVT_S_H 0x40200053
+#define MASK_FCVT_S_H 0xfff0007f
+#define MATCH_FCVT_H_D 0x44100053
+#define MASK_FCVT_H_D 0xfff0007f
+#define MATCH_FCVT_D_H 0x42200053
+#define MASK_FCVT_D_H 0xfff0007f
+#define MATCH_FCVT_H_Q 0x44300053
+#define MASK_FCVT_H_Q 0xfff0007f
+#define MATCH_FCVT_Q_H 0x46200053
+#define MASK_FCVT_Q_H 0xfff0007f
+#define MATCH_FSQRT_H 0x5c000053
+#define MASK_FSQRT_H 0xfff0007f
#define MATCH_FADD_S 0x53
#define MASK_FADD_S 0xfe00007f
#define MATCH_FSUB_S 0x8000053
@@ -339,6 +371,12 @@
#define MASK_FCVT_Q_D 0xfff0007f
#define MATCH_FSQRT_Q 0x5e000053
#define MASK_FSQRT_Q 0xfff0007f
+#define MATCH_FLE_H 0xa4000053
+#define MASK_FLE_H 0xfe00707f
+#define MATCH_FLT_H 0xa4001053
+#define MASK_FLT_H 0xfe00707f
+#define MATCH_FEQ_H 0xa4002053
+#define MASK_FEQ_H 0xfe00707f
#define MATCH_FLE_S 0xa0000053
#define MASK_FLE_S 0xfe00707f
#define MATCH_FLT_S 0xa0001053
@@ -357,6 +395,18 @@
#define MASK_FLT_Q 0xfe00707f
#define MATCH_FEQ_Q 0xa6002053
#define MASK_FEQ_Q 0xfe00707f
+#define MATCH_FCVT_W_H 0xc4000053
+#define MASK_FCVT_W_H 0xfff0007f
+#define MATCH_FCVT_WU_H 0xc4100053
+#define MASK_FCVT_WU_H 0xfff0007f
+#define MATCH_FCVT_L_H 0xc4200053
+#define MASK_FCVT_L_H 0xfff0007f
+#define MATCH_FCVT_LU_H 0xc4300053
+#define MASK_FCVT_LU_H 0xfff0007f
+#define MATCH_FMV_X_H 0xe4000053
+#define MASK_FMV_X_H 0xfff0707f
+#define MATCH_FCLASS_H 0xe4001053
+#define MASK_FCLASS_H 0xfff0707f
#define MATCH_FCVT_W_S 0xc0000053
#define MASK_FCVT_W_S 0xfff0007f
#define MATCH_FCVT_WU_S 0xc0100053
@@ -393,6 +443,16 @@
#define MASK_FMV_X_Q 0xfff0707f
#define MATCH_FCLASS_Q 0xe6001053
#define MASK_FCLASS_Q 0xfff0707f
+#define MATCH_FCVT_H_W 0xd4000053
+#define MASK_FCVT_H_W 0xfff0007f
+#define MATCH_FCVT_H_WU 0xd4100053
+#define MASK_FCVT_H_WU 0xfff0007f
+#define MATCH_FCVT_H_L 0xd4200053
+#define MASK_FCVT_H_L 0xfff0007f
+#define MATCH_FCVT_H_LU 0xd4300053
+#define MASK_FCVT_H_LU 0xfff0007f
+#define MATCH_FMV_H_X 0xf4000053
+#define MASK_FMV_H_X 0xfff0707f
#define MATCH_FCVT_S_W 0xd0000053
#define MASK_FCVT_S_W 0xfff0007f
#define MATCH_FCVT_S_WU 0xd0100053
@@ -521,6 +581,10 @@
#define MASK_BINV 0xfe00707f
#define MATCH_BEXT 0x48005033
#define MASK_BEXT 0xfe00707f
+#define MATCH_FLH 0x1007
+#define MASK_FLH 0x707f
+#define MATCH_FSH 0x1027
+#define MASK_FSH 0x707f
#define MATCH_FLW 0x2007
#define MASK_FLW 0x707f
#define MATCH_FLD 0x3007
@@ -533,6 +597,14 @@
#define MASK_FSD 0x707f
#define MATCH_FSQ 0x4027
#define MASK_FSQ 0x707f
+#define MATCH_FMADD_H 0x4000043
+#define MASK_FMADD_H 0x600007f
+#define MATCH_FMSUB_H 0x4000047
+#define MASK_FMSUB_H 0x600007f
+#define MATCH_FNMSUB_H 0x400004b
+#define MASK_FNMSUB_H 0x600007f
+#define MATCH_FNMADD_H 0x400004f
+#define MASK_FNMADD_H 0x600007f
#define MATCH_FMADD_S 0x43
#define MASK_FMADD_S 0x600007f
#define MATCH_FMSUB_S 0x47
@@ -2425,6 +2497,22 @@ DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
+DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H)
+DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H)
+DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H)
+DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H)
+DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H)
+DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H)
+DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H)
+DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H)
+DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S)
+DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H)
+DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D)
+DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
+DECLARE_INSN(fcvt_h_q, MATCH_FCVT_H_Q, MASK_FCVT_H_Q)
+DECLARE_INSN(fcvt_q_h, MATCH_FCVT_Q_H, MASK_FCVT_Q_H)
+DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H)
DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
@@ -2461,6 +2549,9 @@ DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S)
DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q)
DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D)
DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q)
+DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
+DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
+DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H)
DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
@@ -2470,6 +2561,12 @@ DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)
DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)
DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q)
+DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H)
+DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
+DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
+DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
+DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
+DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H)
DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
@@ -2488,6 +2585,11 @@ DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)
+DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W)
+DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU)
+DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
+DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
+DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X)
DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
@@ -2548,12 +2650,18 @@ DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
+DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
+DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)
+DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
+DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
+DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
+DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 2da0f7cf0a4..660ba0a8fe8 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -647,6 +647,66 @@ const struct riscv_opcode riscv_opcodes[] =
{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
+/* Half-precision floating-point instruction subset. */
+{"flh", 0, INSN_CLASS_ZFHMIN, "D,o(s)", MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"fsh", 0, INSN_CLASS_ZFHMIN, "T,q(s)", MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"fmv.x.h", 0, INSN_CLASS_ZFHMIN, "d,S", MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 },
+{"fmv.h.x", 0, INSN_CLASS_ZFHMIN, "D,s", MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 },
+{"fsgnj.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 },
+{"fsgnjn.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 },
+{"fsgnjx.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 },
+{"fadd.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FADD_H|MASK_RM, MASK_FADD_H|MASK_RM, match_opcode, 0 },
+{"fadd.h", 0, INSN_CLASS_ZFH, "D,S,T,m", MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 },
+{"fsub.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FSUB_H|MASK_RM, MASK_FSUB_H|MASK_RM, match_opcode, 0 },
+{"fsub.h", 0, INSN_CLASS_ZFH, "D,S,T,m", MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 },
+{"fmul.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FMUL_H|MASK_RM, MASK_FMUL_H|MASK_RM, match_opcode, 0 },
+{"fmul.h", 0, INSN_CLASS_ZFH, "D,S,T,m", MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 },
+{"fdiv.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FDIV_H|MASK_RM, MASK_FDIV_H|MASK_RM, match_opcode, 0 },
+{"fdiv.h", 0, INSN_CLASS_ZFH, "D,S,T,m", MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 },
+{"fsqrt.h", 0, INSN_CLASS_ZFH, "D,S", MATCH_FSQRT_H|MASK_RM, MASK_FSQRT_H|MASK_RM, match_opcode, 0 },
+{"fsqrt.h", 0, INSN_CLASS_ZFH, "D,S,m", MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 },
+{"fmin.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 },
+{"fmax.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 },
+{"fmadd.h", 0, INSN_CLASS_ZFH, "D,S,T,R", MATCH_FMADD_H|MASK_RM, MASK_FMADD_H|MASK_RM, match_opcode, 0 },
+{"fmadd.h", 0, INSN_CLASS_ZFH, "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 },
+{"fnmadd.h", 0, INSN_CLASS_ZFH, "D,S,T,R", MATCH_FNMADD_H|MASK_RM, MASK_FNMADD_H|MASK_RM, match_opcode, 0 },
+{"fnmadd.h", 0, INSN_CLASS_ZFH, "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 },
+{"fmsub.h", 0, INSN_CLASS_ZFH, "D,S,T,R", MATCH_FMSUB_H|MASK_RM, MASK_FMSUB_H|MASK_RM, match_opcode, 0 },
+{"fmsub.h", 0, INSN_CLASS_ZFH, "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 },
+{"fnmsub.h", 0, INSN_CLASS_ZFH, "D,S,T,R", MATCH_FNMSUB_H|MASK_RM, MASK_FNMSUB_H|MASK_RM, match_opcode, 0 },
+{"fnmsub.h", 0, INSN_CLASS_ZFH, "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 },
+{"fcvt.w.h", 0, INSN_CLASS_ZFH, "d,S", MATCH_FCVT_W_H|MASK_RM, MASK_FCVT_W_H|MASK_RM, match_opcode, 0 },
+{"fcvt.w.h", 0, INSN_CLASS_ZFH, "d,S,m", MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 },
+{"fcvt.wu.h", 0, INSN_CLASS_ZFH, "d,S", MATCH_FCVT_WU_H|MASK_RM, MASK_FCVT_WU_H|MASK_RM, match_opcode, 0 },
+{"fcvt.wu.h", 0, INSN_CLASS_ZFH, "d,S,m", MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 },
+{"fcvt.h.w", 0, INSN_CLASS_ZFH, "D,s", MATCH_FCVT_H_W|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 },
+{"fcvt.h.w", 0, INSN_CLASS_ZFH, "D,s,m", MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
+{"fcvt.h.wu", 0, INSN_CLASS_ZFH, "D,s", MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 },
+{"fcvt.h.wu", 0, INSN_CLASS_ZFH, "D,s,m", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
+{"fcvt.s.h", 0, INSN_CLASS_ZFHMIN, "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
+{"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 },
+{"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 },
+{"fcvt.h.s", 0, INSN_CLASS_ZFHMIN, "D,S", MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 },
+{"fcvt.h.s", 0, INSN_CLASS_ZFHMIN, "D,S,m", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
+{"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D, "D,S", MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 },
+{"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D, "D,S,m", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 },
+{"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q, "D,S", MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, 0 },
+{"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q, "D,S,m", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
+{"fclass.h", 0, INSN_CLASS_ZFH, "d,S", MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
+{"feq.h", 0, INSN_CLASS_ZFH, "d,S,T", MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
+{"flt.h", 0, INSN_CLASS_ZFH, "d,S,T", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
+{"fle.h", 0, INSN_CLASS_ZFH, "d,S,T", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
+{"fgt.h", 0, INSN_CLASS_ZFH, "d,T,S", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
+{"fge.h", 0, INSN_CLASS_ZFH, "d,T,S", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
+{"fcvt.l.h", 64, INSN_CLASS_ZFH, "d,S", MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 },
+{"fcvt.l.h", 64, INSN_CLASS_ZFH, "d,S,m", MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 },
+{"fcvt.lu.h", 64, INSN_CLASS_ZFH, "d,S", MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 },
+{"fcvt.lu.h", 64, INSN_CLASS_ZFH, "d,S,m", MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 },
+{"fcvt.h.l", 64, INSN_CLASS_ZFH, "D,s", MATCH_FCVT_H_L|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
+{"fcvt.h.l", 64, INSN_CLASS_ZFH, "D,s,m", MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 },
+{"fcvt.h.lu", 64, INSN_CLASS_ZFH, "D,s", MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_LU|MASK_RM, match_opcode, 0 },
+{"fcvt.h.lu", 64, INSN_CLASS_ZFH, "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
+
/* Double-precision floating-point instruction subset. */
{"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
--
2.32.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [RFC PATCH 4/5] RISC-V: Add 'flh' and 'fsh' macro instructions
2022-01-11 10:47 [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions Tsukasa OI
` (2 preceding siblings ...)
2022-01-11 10:48 ` [RFC PATCH 3/5] RISC-V: Add 'Zfh' and 'Zfhmin' instructions Tsukasa OI
@ 2022-01-11 10:48 ` Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 5/5] RISC-V: Add 'Zfh'/'Zfhmin' conflict message Tsukasa OI
` (2 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Tsukasa OI @ 2022-01-11 10:48 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds two new macro instructions 'flh' and 'fsh'.
gas/ChangeLog:
* config/tc-riscv.c (macro): Add macro instruction handling for
M_FLH and M_FSH.
include/ChangeLog:
* opcode/riscv.h (M_FLH, M_FSH): New macro instructions.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add new macro instructions.
---
gas/config/tc-riscv.c | 10 ++++++++++
include/opcode/riscv.h | 2 ++
opcodes/riscv-opc.c | 2 ++
3 files changed, 14 insertions(+)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 390aaf1710b..973230d827b 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1822,6 +1822,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
break;
+ case M_FLH:
+ pcrel_load (rd, rs1, imm_expr, "flh",
+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
+ break;
+
case M_FLW:
pcrel_load (rd, rs1, imm_expr, "flw",
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
@@ -1852,6 +1857,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
break;
+ case M_FSH:
+ pcrel_store (rs2, rs1, imm_expr, "fsh",
+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
+ break;
+
case M_FSW:
pcrel_store (rs2, rs1, imm_expr, "fsw",
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index a5da8d0c4e0..4d2acf807c2 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -484,9 +484,11 @@ enum
M_SH,
M_SW,
M_SD,
+ M_FLH,
M_FLW,
M_FLD,
M_FLQ,
+ M_FSH,
M_FSW,
M_FSD,
M_FSQ,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 660ba0a8fe8..a538d95e331 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -649,7 +649,9 @@ const struct riscv_opcode riscv_opcodes[] =
/* Half-precision floating-point instruction subset. */
{"flh", 0, INSN_CLASS_ZFHMIN, "D,o(s)", MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"flh", 0, INSN_CLASS_ZFHMIN, "D,A,s", 0, (int) M_FLH, match_never, INSN_MACRO },
{"fsh", 0, INSN_CLASS_ZFHMIN, "T,q(s)", MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"fsh", 0, INSN_CLASS_ZFHMIN, "T,A,s", 0, (int) M_FSH, match_never, INSN_MACRO },
{"fmv.x.h", 0, INSN_CLASS_ZFHMIN, "d,S", MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 },
{"fmv.h.x", 0, INSN_CLASS_ZFHMIN, "D,s", MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 },
{"fsgnj.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 },
--
2.32.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [RFC PATCH 5/5] RISC-V: Add 'Zfh'/'Zfhmin' conflict message
2022-01-11 10:47 [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions Tsukasa OI
` (3 preceding siblings ...)
2022-01-11 10:48 ` [RFC PATCH 4/5] RISC-V: Add 'flh' and 'fsh' macro instructions Tsukasa OI
@ 2022-01-11 10:48 ` Tsukasa OI
2022-05-18 1:43 ` [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions Kito Cheng
2022-05-22 5:15 ` [PATCH v2 0/4] RISC-V: Float16 extensions enhancements Tsukasa OI
6 siblings, 0 replies; 15+ messages in thread
From: Tsukasa OI @ 2022-01-11 10:48 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit changes error message while checking extension conflicts
to include 'Zfh' and 'Zfhmin' extensions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_check_conflicts): Change error
message to include 'Zfh' and 'Zfhmin' extensions.
---
bfd/elfxx-riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 4f3705ad396..fef6e220f95 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1913,7 +1913,7 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
&& riscv_lookup_subset (rps->subset_list, "f", &subset))
{
rps->error_handler
- (_("`zfinx' is conflict with the `f/d/q' extension"));
+ (_("`zfinx' is conflict with the `f/d/q/zfh/zfhmin' extension"));
no_conflict = false;
}
--
2.32.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions
2022-01-11 10:47 [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions Tsukasa OI
` (4 preceding siblings ...)
2022-01-11 10:48 ` [RFC PATCH 5/5] RISC-V: Add 'Zfh'/'Zfhmin' conflict message Tsukasa OI
@ 2022-05-18 1:43 ` Kito Cheng
2022-05-18 9:31 ` Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 0/4] RISC-V: Float16 extensions enhancements Tsukasa OI
6 siblings, 1 reply; 15+ messages in thread
From: Kito Cheng @ 2022-05-18 1:43 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu; +Cc: Binutils
HI Tsukasa:
Nelson has ported his zfh implementation from integration branch to
trunk, did you mind base that on to adding zfhmin?
On Tue, Jan 11, 2022 at 6:48 PM Tsukasa OI via Binutils
<binutils@sourceware.org> wrote:
>
> This patchset adds support for two recently ratified RISC-V extensions:
>
> - Zfhmin (Half-precision floating point: conversion only)
> - Zfh (Half-precision floating point: full arithmetic)
>
> This patchset was intended to be a part of Binutils 2.38 but I was
> getting too impatient. I tested this patchset with Spike simulator and
> tested that a few programs with fp16 was working nicely. However, this
> patchset lacks full testsuite.
>
> The only reason I didn't make one was simple: all of floating point
> extensions ('F', 'D' and 'Q') didn't have full testsuite. Thanks to the
> fact that this patchset is too late for Binutils 2.38, we have time to
> add full testsuite for all floating point extensions.
>
> Also, this patchset lacks pseudoinstructions (intentionally). Possible
> pseudoinstructions to implement later would be:
>
> - fmv.h
> - fneg.h
> - fabs.h
>
> Besides that, we can begin testing 'Zfh' and 'Zfhmin' extensions with
> this patchset.
>
>
>
>
> Tsukasa OI (5):
> RISC-V: Add 'Zfh' and 'Zfhmin' extensions
> RISC-V: Add insn classes for Zfh/Zfhmin extensions
> RISC-V: Add 'Zfh' and 'Zfhmin' instructions
> RISC-V: Add 'flh' and 'fsh' macro instructions
> RISC-V: Add 'Zfh'/'Zfhmin' conflict message
>
> bfd/elfxx-riscv.c | 16 +++++-
> gas/config/tc-riscv.c | 10 ++++
> include/opcode/riscv-opc.h | 108 +++++++++++++++++++++++++++++++++++++
> include/opcode/riscv.h | 6 +++
> opcodes/riscv-opc.c | 62 +++++++++++++++++++++
> 5 files changed, 201 insertions(+), 1 deletion(-)
>
>
> base-commit: 9ed5be5650ba7c315cd7cfacccc9208de2f555df
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions
2022-05-18 1:43 ` [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions Kito Cheng
@ 2022-05-18 9:31 ` Tsukasa OI
0 siblings, 0 replies; 15+ messages in thread
From: Tsukasa OI @ 2022-05-18 9:31 UTC (permalink / raw)
To: Kito Cheng, Nelson Chu; +Cc: Binutils
Hi Kito,
Thanks for letting me know. I think I can rebase or port my work to
Nelson's implementation.
Hi Nelson,
It's good to know that you implemented Zfh. I think I can port my
Zfhmin patch and testcases based on your work.
My original submission did not contain floating point data pseudo-op in
the assembler (like F, D and Q) and I didn't know .float, .single and
.double are already available on GAS (non arch-specific). Since
.float16 is currently RISC-V+GNU-specific, it would be nicer if we have
discussion on ... for instance, riscv-asm-manual.
Best Regards,
Tsukasa
On 2022/05/18 10:43, Kito Cheng wrote:
> HI Tsukasa:
>
> Nelson has ported his zfh implementation from integration branch to
> trunk, did you mind base that on to adding zfhmin?
>
> On Tue, Jan 11, 2022 at 6:48 PM Tsukasa OI via Binutils
> <binutils@sourceware.org> wrote:
>>
>> This patchset adds support for two recently ratified RISC-V extensions:
>>
>> - Zfhmin (Half-precision floating point: conversion only)
>> - Zfh (Half-precision floating point: full arithmetic)
>>
>> This patchset was intended to be a part of Binutils 2.38 but I was
>> getting too impatient. I tested this patchset with Spike simulator and
>> tested that a few programs with fp16 was working nicely. However, this
>> patchset lacks full testsuite.
>>
>> The only reason I didn't make one was simple: all of floating point
>> extensions ('F', 'D' and 'Q') didn't have full testsuite. Thanks to the
>> fact that this patchset is too late for Binutils 2.38, we have time to
>> add full testsuite for all floating point extensions.
>>
>> Also, this patchset lacks pseudoinstructions (intentionally). Possible
>> pseudoinstructions to implement later would be:
>>
>> - fmv.h
>> - fneg.h
>> - fabs.h
>>
>> Besides that, we can begin testing 'Zfh' and 'Zfhmin' extensions with
>> this patchset.
>>
>>
>>
>>
>> Tsukasa OI (5):
>> RISC-V: Add 'Zfh' and 'Zfhmin' extensions
>> RISC-V: Add insn classes for Zfh/Zfhmin extensions
>> RISC-V: Add 'Zfh' and 'Zfhmin' instructions
>> RISC-V: Add 'flh' and 'fsh' macro instructions
>> RISC-V: Add 'Zfh'/'Zfhmin' conflict message
>>
>> bfd/elfxx-riscv.c | 16 +++++-
>> gas/config/tc-riscv.c | 10 ++++
>> include/opcode/riscv-opc.h | 108 +++++++++++++++++++++++++++++++++++++
>> include/opcode/riscv.h | 6 +++
>> opcodes/riscv-opc.c | 62 +++++++++++++++++++++
>> 5 files changed, 201 insertions(+), 1 deletion(-)
>>
>>
>> base-commit: 9ed5be5650ba7c315cd7cfacccc9208de2f555df
>> --
>> 2.32.0
>>
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 0/4] RISC-V: Float16 extensions enhancements
2022-01-11 10:47 [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions Tsukasa OI
` (5 preceding siblings ...)
2022-05-18 1:43 ` [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions Kito Cheng
@ 2022-05-22 5:15 ` Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 1/4] RISC-V: Refactor 'Zfh'-related macros Tsukasa OI
` (4 more replies)
6 siblings, 5 replies; 15+ messages in thread
From: Tsukasa OI @ 2022-05-22 5:15 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
RFC PATCH v1:
<https://sourceware.org/pipermail/binutils/2022-January/119276.html>
<https://github.com/a4lg/binutils-gdb/tree/a4lg/snapshots/2022-01-11/riscv-zfh-RFC-v1>
This patchset will:
- Add `Zfhmin' extension support
- Refine (refactors) `Zfh' extension support (by Nelson Chu)
- Prepare for `Zhinx' extension
[CHANGES BETWEEN RFC PATCH v1 between PATCH v2]
- Added pseudoinstructions
- Large rebase (based on Nelson Chu's implementation)
- Preparation for `Zhinx' implementation
[Added pseudoinstructions]
I checked into LLVM (llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td) and found
my RFC PATCH v1 ONLY lacked following pseudoinstructions:
- fmv.h
- fneg.h
- fabs.h
In this version, it implements all `Zfh' or `Zfhmin' instructions
implemented in LLVM-CURRENT.
[Preparation for Zhinx implementation]
I mean, `Zhinx' implementation except actual feature support.
Instruction category is refined as follows:
Before:
- INSN_CLASS_ZFH
`Zfh'
- INSN_CLASS_D_AND_ZFH
`Zfh' and `D'
- INSN_CLASS_Q_AND_ZFH
`Zfh' and `Q'
After:
- INSN_CLASS_ZFH_OR_ZHINX
Either `Zfh' or `Zhinx'
Renamed from INSN_CLASS_ZFH.
- INSN_CLASS_ZFHMIN
`Zfhmin'
Part of former INSN_CLASS_ZFH.
- INSN_CLASS_ZFHMIN_OR_ZHINXMIN
Either `Zfhmin' or `Zhinxmin'
Part of former INSN_CLASS_ZFH.
- INSN_CLASS_ZFHMIN_AND_D
(`Zfhmin' and `D') or (`Zhinxmin' and `Zdinx')
Renamed from INSN_CLASS_D_AND_ZFH.
- INSN_CLASS_ZFHMIN_AND_Q
(`Zfhmin' and `Q') or (`Zhinxmin' and `Zqinx')
Renamed from INSN_CLASS_Q_AND_ZFH.
INFN_CLASS_ZFHMIN_AND_? do not represent actual required extensions.
This is because it'll be too long if we make this symbol faithful.
Tsukasa OI (4):
RISC-V: Refactor 'Zfh'-related macros
RISC-V: Add instruction declaration for 'Zfh'
RISC-V: Add 'Zfhmin' (and refactor 'Zfh')
RISC-V: Add 'Zfh' / 'Zfhmin' conflict message
bfd/elfxx-riscv.c | 33 ++++---
gas/config/tc-riscv.c | 19 ++--
include/opcode/riscv-opc.h | 180 ++++++++++++++++++++++---------------
include/opcode/riscv.h | 12 +--
opcodes/riscv-opc.c | 126 +++++++++++++-------------
5 files changed, 210 insertions(+), 160 deletions(-)
base-commit: cb3a7614feb82ffdc25161bf60529116c6112ab3
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 1/4] RISC-V: Refactor 'Zfh'-related macros
2022-05-22 5:15 ` [PATCH v2 0/4] RISC-V: Float16 extensions enhancements Tsukasa OI
@ 2022-05-22 5:15 ` Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 2/4] RISC-V: Add instruction declaration for 'Zfh' Tsukasa OI
` (3 subsequent siblings)
4 siblings, 0 replies; 15+ messages in thread
From: Tsukasa OI @ 2022-05-22 5:15 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit just moves 'Zfh'-related macros for better integration with
other instructions and macros. Since M_FLH/M_FSH values are internal,
there's no point adding them to the tail.
gas/ChangeLog:
* config/tc-riscv.c (macro): Move M_FLH and M_FSH handlings.
include/ChangeLog:
* opcode/riscv.h (M_FLH, M_FSH): Move around.
* opcode/riscv-opc.h (MATCH_FADD_H, MASK_FADD_H, MATCH_FSUB_H,
MASK_FSUB_H, MATCH_FMUL_H, MASK_FMUL_H, MATCH_FDIV_H,
MASK_FDIV_H, MATCH_FSGNJ_H, MASK_FSGNJ_H, MATCH_FSGNJN_H,
MASK_FSGNJN_H, MATCH_FSGNJX_H, MASK_FSGNJX_H, MATCH_FMIN_H,
MASK_FMIN_H, MATCH_FMAX_H, MASK_FMAX_H, MATCH_FCVT_H_S,
MASK_FCVT_H_S, MATCH_FCVT_S_H, MASK_FCVT_S_H, MATCH_FCVT_H_D,
MASK_FCVT_H_D, MATCH_FCVT_D_H, MASK_FCVT_D_H, MATCH_FCVT_H_Q,
MASK_FCVT_H_Q, MATCH_FCVT_Q_H, MASK_FCVT_Q_H, MATCH_FSQRT_H,
MASK_FSQRT_H, MATCH_FLE_H, MASK_FLE_H, MATCH_FLT_H, MASK_FLT_H,
MATCH_FEQ_H, MASK_FEQ_H, MATCH_FCVT_W_H, MASK_FCVT_W_H,
MATCH_FCVT_WU_H, MASK_FCVT_WU_H, MATCH_FCVT_L_H, MASK_FCVT_L_H,
MATCH_FCVT_LU_H, MASK_FCVT_LU_H, MATCH_FMV_X_H, MASK_FMV_X_H,
MATCH_FCLASS_H, MASK_FCLASS_H, MATCH_FCVT_H_W, MASK_FCVT_H_W,
MATCH_FCVT_H_WU, MASK_FCVT_H_WU, MATCH_FCVT_H_L, MASK_FCVT_H_L,
MATCH_FCVT_H_LU, MASK_FCVT_H_LU, MATCH_FMV_H_X, MASK_FMV_H_X,
MATCH_FLH, MASK_FLH, MATCH_FSH, MASK_FSH, MATCH_FMADD_H,
MASK_FMADD_H, MATCH_FMSUB_H, MASK_FMSUB_H, MATCH_FNMSUB_H,
MASK_FNMSUB_H, MATCH_FNMADD_H, MASK_FNMADD_H): Move around for
better integration with other instructions.
---
gas/config/tc-riscv.c | 19 ++---
include/opcode/riscv-opc.h | 144 ++++++++++++++++++-------------------
include/opcode/riscv.h | 4 +-
3 files changed, 84 insertions(+), 83 deletions(-)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 1b730b4be36..61cf383a9fb 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1843,6 +1843,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
break;
+ case M_FLH:
+ pcrel_load (rd, rs1, imm_expr, "flh",
+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
+ break;
+
case M_FLW:
pcrel_load (rd, rs1, imm_expr, "flw",
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
@@ -1873,6 +1878,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
break;
+ case M_FSH:
+ pcrel_store (rs2, rs1, imm_expr, "fsh",
+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
+ break;
+
case M_FSW:
pcrel_store (rs2, rs1, imm_expr, "fsw",
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
@@ -1908,15 +1918,6 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
vector_macro (ip);
break;
- case M_FLH:
- pcrel_load (rd, rs1, imm_expr, "flh",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
- case M_FSH:
- pcrel_store (rs2, rs1, imm_expr, "fsh",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
- break;
-
default:
as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name);
break;
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 2e867965e12..80e0b44a096 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -267,6 +267,38 @@
#define MASK_CSRRSI 0x707f
#define MATCH_CSRRCI 0x7073
#define MASK_CSRRCI 0x707f
+#define MATCH_FADD_H 0x4000053
+#define MASK_FADD_H 0xfe00007f
+#define MATCH_FSUB_H 0xc000053
+#define MASK_FSUB_H 0xfe00007f
+#define MATCH_FMUL_H 0x14000053
+#define MASK_FMUL_H 0xfe00007f
+#define MATCH_FDIV_H 0x1c000053
+#define MASK_FDIV_H 0xfe00007f
+#define MATCH_FSGNJ_H 0x24000053
+#define MASK_FSGNJ_H 0xfe00707f
+#define MATCH_FSGNJN_H 0x24001053
+#define MASK_FSGNJN_H 0xfe00707f
+#define MATCH_FSGNJX_H 0x24002053
+#define MASK_FSGNJX_H 0xfe00707f
+#define MATCH_FMIN_H 0x2c000053
+#define MASK_FMIN_H 0xfe00707f
+#define MATCH_FMAX_H 0x2c001053
+#define MASK_FMAX_H 0xfe00707f
+#define MATCH_FCVT_H_S 0x44000053
+#define MASK_FCVT_H_S 0xfff0007f
+#define MATCH_FCVT_S_H 0x40200053
+#define MASK_FCVT_S_H 0xfff0007f
+#define MATCH_FCVT_H_D 0x44100053
+#define MASK_FCVT_H_D 0xfff0007f
+#define MATCH_FCVT_D_H 0x42200053
+#define MASK_FCVT_D_H 0xfff0007f
+#define MATCH_FCVT_H_Q 0x44300053
+#define MASK_FCVT_H_Q 0xfff0007f
+#define MATCH_FCVT_Q_H 0x46200053
+#define MASK_FCVT_Q_H 0xfff0007f
+#define MATCH_FSQRT_H 0x5c000053
+#define MASK_FSQRT_H 0xfff0007f
#define MATCH_FADD_S 0x53
#define MASK_FADD_S 0xfe00007f
#define MATCH_FSUB_S 0x8000053
@@ -339,6 +371,12 @@
#define MASK_FCVT_Q_D 0xfff0007f
#define MATCH_FSQRT_Q 0x5e000053
#define MASK_FSQRT_Q 0xfff0007f
+#define MATCH_FLE_H 0xa4000053
+#define MASK_FLE_H 0xfe00707f
+#define MATCH_FLT_H 0xa4001053
+#define MASK_FLT_H 0xfe00707f
+#define MATCH_FEQ_H 0xa4002053
+#define MASK_FEQ_H 0xfe00707f
#define MATCH_FLE_S 0xa0000053
#define MASK_FLE_S 0xfe00707f
#define MATCH_FLT_S 0xa0001053
@@ -357,6 +395,18 @@
#define MASK_FLT_Q 0xfe00707f
#define MATCH_FEQ_Q 0xa6002053
#define MASK_FEQ_Q 0xfe00707f
+#define MATCH_FCVT_W_H 0xc4000053
+#define MASK_FCVT_W_H 0xfff0007f
+#define MATCH_FCVT_WU_H 0xc4100053
+#define MASK_FCVT_WU_H 0xfff0007f
+#define MATCH_FCVT_L_H 0xc4200053
+#define MASK_FCVT_L_H 0xfff0007f
+#define MATCH_FCVT_LU_H 0xc4300053
+#define MASK_FCVT_LU_H 0xfff0007f
+#define MATCH_FMV_X_H 0xe4000053
+#define MASK_FMV_X_H 0xfff0707f
+#define MATCH_FCLASS_H 0xe4001053
+#define MASK_FCLASS_H 0xfff0707f
#define MATCH_FCVT_W_S 0xc0000053
#define MASK_FCVT_W_S 0xfff0007f
#define MATCH_FCVT_WU_S 0xc0100053
@@ -391,6 +441,16 @@
#define MASK_FCVT_LU_Q 0xfff0007f
#define MATCH_FCLASS_Q 0xe6001053
#define MASK_FCLASS_Q 0xfff0707f
+#define MATCH_FCVT_H_W 0xd4000053
+#define MASK_FCVT_H_W 0xfff0007f
+#define MATCH_FCVT_H_WU 0xd4100053
+#define MASK_FCVT_H_WU 0xfff0007f
+#define MATCH_FCVT_H_L 0xd4200053
+#define MASK_FCVT_H_L 0xfff0007f
+#define MATCH_FCVT_H_LU 0xd4300053
+#define MASK_FCVT_H_LU 0xfff0007f
+#define MATCH_FMV_H_X 0xf4000053
+#define MASK_FMV_H_X 0xfff0707f
#define MATCH_FCVT_S_W 0xd0000053
#define MASK_FCVT_S_W 0xfff0007f
#define MATCH_FCVT_S_WU 0xd0100053
@@ -517,18 +577,30 @@
#define MASK_BINV 0xfe00707f
#define MATCH_BEXT 0x48005033
#define MASK_BEXT 0xfe00707f
+#define MATCH_FLH 0x1007
+#define MASK_FLH 0x707f
#define MATCH_FLW 0x2007
#define MASK_FLW 0x707f
#define MATCH_FLD 0x3007
#define MASK_FLD 0x707f
#define MATCH_FLQ 0x4007
#define MASK_FLQ 0x707f
+#define MATCH_FSH 0x1027
+#define MASK_FSH 0x707f
#define MATCH_FSW 0x2027
#define MASK_FSW 0x707f
#define MATCH_FSD 0x3027
#define MASK_FSD 0x707f
#define MATCH_FSQ 0x4027
#define MASK_FSQ 0x707f
+#define MATCH_FMADD_H 0x4000043
+#define MASK_FMADD_H 0x600007f
+#define MATCH_FMSUB_H 0x4000047
+#define MASK_FMSUB_H 0x600007f
+#define MATCH_FNMSUB_H 0x400004b
+#define MASK_FNMSUB_H 0x600007f
+#define MATCH_FNMADD_H 0x400004f
+#define MASK_FNMADD_H 0x600007f
#define MATCH_FMADD_S 0x43
#define MASK_FMADD_S 0x600007f
#define MATCH_FMSUB_S 0x47
@@ -701,78 +773,6 @@
#define MASK_AES64DSM 0xfe00707f
#define MATCH_AES64DS 0x3a000033
#define MASK_AES64DS 0xfe00707f
-#define MATCH_FADD_H 0x4000053
-#define MASK_FADD_H 0xfe00007f
-#define MATCH_FSUB_H 0xc000053
-#define MASK_FSUB_H 0xfe00007f
-#define MATCH_FMUL_H 0x14000053
-#define MASK_FMUL_H 0xfe00007f
-#define MATCH_FDIV_H 0x1c000053
-#define MASK_FDIV_H 0xfe00007f
-#define MATCH_FSGNJ_H 0x24000053
-#define MASK_FSGNJ_H 0xfe00707f
-#define MATCH_FSGNJN_H 0x24001053
-#define MASK_FSGNJN_H 0xfe00707f
-#define MATCH_FSGNJX_H 0x24002053
-#define MASK_FSGNJX_H 0xfe00707f
-#define MATCH_FMIN_H 0x2c000053
-#define MASK_FMIN_H 0xfe00707f
-#define MATCH_FMAX_H 0x2c001053
-#define MASK_FMAX_H 0xfe00707f
-#define MATCH_FCVT_H_S 0x44000053
-#define MASK_FCVT_H_S 0xfff0007f
-#define MATCH_FCVT_S_H 0x40200053
-#define MASK_FCVT_S_H 0xfff0007f
-#define MATCH_FSQRT_H 0x5c000053
-#define MASK_FSQRT_H 0xfff0007f
-#define MATCH_FLE_H 0xa4000053
-#define MASK_FLE_H 0xfe00707f
-#define MATCH_FLT_H 0xa4001053
-#define MASK_FLT_H 0xfe00707f
-#define MATCH_FEQ_H 0xa4002053
-#define MASK_FEQ_H 0xfe00707f
-#define MATCH_FCVT_W_H 0xc4000053
-#define MASK_FCVT_W_H 0xfff0007f
-#define MATCH_FCVT_WU_H 0xc4100053
-#define MASK_FCVT_WU_H 0xfff0007f
-#define MATCH_FMV_X_H 0xe4000053
-#define MASK_FMV_X_H 0xfff0707f
-#define MATCH_FCLASS_H 0xe4001053
-#define MASK_FCLASS_H 0xfff0707f
-#define MATCH_FCVT_H_W 0xd4000053
-#define MASK_FCVT_H_W 0xfff0007f
-#define MATCH_FCVT_H_WU 0xd4100053
-#define MASK_FCVT_H_WU 0xfff0007f
-#define MATCH_FMV_H_X 0xf4000053
-#define MASK_FMV_H_X 0xfff0707f
-#define MATCH_FLH 0x1007
-#define MASK_FLH 0x707f
-#define MATCH_FSH 0x1027
-#define MASK_FSH 0x707f
-#define MATCH_FMADD_H 0x4000043
-#define MASK_FMADD_H 0x600007f
-#define MATCH_FMSUB_H 0x4000047
-#define MASK_FMSUB_H 0x600007f
-#define MATCH_FNMSUB_H 0x400004b
-#define MASK_FNMSUB_H 0x600007f
-#define MATCH_FNMADD_H 0x400004f
-#define MASK_FNMADD_H 0x600007f
-#define MATCH_FCVT_H_D 0x44100053
-#define MASK_FCVT_H_D 0xfff0007f
-#define MATCH_FCVT_D_H 0x42200053
-#define MASK_FCVT_D_H 0xfff0007f
-#define MATCH_FCVT_H_Q 0x44300053
-#define MASK_FCVT_H_Q 0xfff0007f
-#define MATCH_FCVT_Q_H 0x46200053
-#define MASK_FCVT_Q_H 0xfff0007f
-#define MATCH_FCVT_L_H 0xc4200053
-#define MASK_FCVT_L_H 0xfff0007f
-#define MATCH_FCVT_LU_H 0xc4300053
-#define MASK_FCVT_LU_H 0xfff0007f
-#define MATCH_FCVT_H_L 0xd4200053
-#define MASK_FCVT_H_L 0xfff0007f
-#define MATCH_FCVT_H_LU 0xd4300053
-#define MASK_FCVT_H_LU 0xfff0007f
#define MATCH_VSETVL 0x80007057
#define MASK_VSETVL 0xfe00707f
#define MATCH_VSETIVLI 0xc0007057
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 0d1fbcf8fc5..7b1fcc4346f 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -486,9 +486,11 @@ enum
M_SH,
M_SW,
M_SD,
+ M_FLH,
M_FLW,
M_FLD,
M_FLQ,
+ M_FSH,
M_FSW,
M_FSD,
M_FSQ,
@@ -501,8 +503,6 @@ enum
M_SEXTH,
M_VMSGE,
M_VMSGEU,
- M_FLH,
- M_FSH,
M_NUM_MACROS
};
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 2/4] RISC-V: Add instruction declaration for 'Zfh'
2022-05-22 5:15 ` [PATCH v2 0/4] RISC-V: Float16 extensions enhancements Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 1/4] RISC-V: Refactor 'Zfh'-related macros Tsukasa OI
@ 2022-05-22 5:15 ` Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 3/4] RISC-V: Add 'Zfhmin' (and refactor 'Zfh') Tsukasa OI
` (2 subsequent siblings)
4 siblings, 0 replies; 15+ messages in thread
From: Tsukasa OI @ 2022-05-22 5:15 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds `DECLARE_INSN' instruction declaration statements for
'Zfh' half-precision floating point instructions.
include/ChangeLog:
* opcode/riscv-opc.h: Add DECLARE_INSN macros for 'Zfh'
instructions.
---
include/opcode/riscv-opc.h | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 80e0b44a096..d51b53cc40b 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2585,6 +2585,22 @@ DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
+DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H)
+DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H)
+DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H)
+DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H)
+DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H)
+DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H)
+DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H)
+DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H)
+DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S)
+DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H)
+DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D)
+DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
+DECLARE_INSN(fcvt_h_q, MATCH_FCVT_H_Q, MASK_FCVT_H_Q)
+DECLARE_INSN(fcvt_q_h, MATCH_FCVT_Q_H, MASK_FCVT_Q_H)
+DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H)
DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
@@ -2621,6 +2637,9 @@ DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S)
DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q)
DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D)
DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q)
+DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
+DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
+DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H)
DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
@@ -2630,6 +2649,12 @@ DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)
DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)
DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q)
+DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H)
+DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
+DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
+DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
+DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
+DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H)
DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
@@ -2647,6 +2672,11 @@ DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)
+DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W)
+DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU)
+DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
+DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
+DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X)
DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
@@ -2706,12 +2736,18 @@ DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
+DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
+DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)
+DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
+DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
+DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
+DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 3/4] RISC-V: Add 'Zfhmin' (and refactor 'Zfh')
2022-05-22 5:15 ` [PATCH v2 0/4] RISC-V: Float16 extensions enhancements Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 1/4] RISC-V: Refactor 'Zfh'-related macros Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 2/4] RISC-V: Add instruction declaration for 'Zfh' Tsukasa OI
@ 2022-05-22 5:15 ` Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 4/4] RISC-V: Add 'Zfh' / 'Zfhmin' conflict message Tsukasa OI
2022-05-22 9:11 ` [PATCH 0/1] RISC-V: Zfh extension diagnostic addition Tsukasa OI
4 siblings, 0 replies; 15+ messages in thread
From: Tsukasa OI @ 2022-05-22 5:15 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds 'Zfhmin' extension (a subset of 'Zfh' extension,
conversion only half-precision floating point support). In the process
supporting 'Zfhmin' extension, this commit also changes how instructions
are categorized considering 'Zfhmin' extension and upcoming 'Zhinx' and
'Zhinxmin' extensions (half-precision floating point support but will
use generic-purpose registers instead of dedicated registers).
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Change implicit
subsets (Zfh->Zicsr is not needed and Zfh->F are replaced with
Zfh->Zfhmin and Zfhmin->F).
(riscv_supported_std_z_ext): Add 'Zfhmin' extension.
(riscv_multi_subset_supports): Rewrite handling for new
instruction classes.
include/ChangeLog:
* opcode/riscv.h (enum riscv_insn_class): Renew instruction
classes INSN_CLASS_ZFH_OR_ZHINX, INSN_CLASS_ZFHMIN,
INSN_CLASS_ZFHMIN_OR_ZHINXMIN, INSN_CLASS_ZFHMIN_AND_D and
INSN_CLASS_ZFHMIN_AND_Q.
Remove INSN_CLASS_ZFH, INSN_CLASS_D_AND_ZFH and
INSN_CLASS_Q_AND_ZFH.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Change instruction classes for
'Zfh' and 'Zfhmin' instructions. Fix `fcvt.h.lu' instruction
(two operand variant) mask.
---
bfd/elfxx-riscv.c | 31 ++++++----
include/opcode/riscv.h | 8 ++-
opcodes/riscv-opc.c | 126 ++++++++++++++++++++---------------------
3 files changed, 89 insertions(+), 76 deletions(-)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index b2806185fa8..2dfbb08ca7c 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1099,9 +1099,9 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zvl128b", "zvl64b", check_implicit_always},
{"zvl64b", "zvl32b", check_implicit_always},
{"d", "f", check_implicit_always},
+ {"zfh", "zfhmin", check_implicit_always},
+ {"zfhmin", "f", check_implicit_always},
{"f", "zicsr", check_implicit_always},
- {"zfh", "f", check_implicit_always},
- {"zfh", "zicsr", check_implicit_always},
{"zqinx", "zdinx", check_implicit_always},
{"zdinx", "zfinx", check_implicit_always},
{"zfinx", "zicsr", check_implicit_always},
@@ -1184,6 +1184,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zdinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zqinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2362,14 +2363,24 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
case INSN_CLASS_Q_OR_ZQINX:
return (riscv_subset_supports (rps, "q")
|| riscv_subset_supports (rps, "zqinx"));
- case INSN_CLASS_ZFH:
- return riscv_subset_supports (rps, "zfh");
- case INSN_CLASS_D_AND_ZFH:
- return (riscv_subset_supports (rps, "d")
- && riscv_subset_supports (rps, "zfh") );
- case INSN_CLASS_Q_AND_ZFH:
- return (riscv_subset_supports (rps, "q")
- && riscv_subset_supports (rps, "zfh"));
+ case INSN_CLASS_ZFH_OR_ZHINX:
+ return (riscv_subset_supports (rps, "zfh")
+ || riscv_subset_supports (rps, "zhinx"));
+ case INSN_CLASS_ZFHMIN:
+ return riscv_subset_supports (rps, "zfhmin");
+ case INSN_CLASS_ZFHMIN_OR_ZHINXMIN:
+ return (riscv_subset_supports (rps, "zfhmin")
+ || riscv_subset_supports (rps, "zhinxmin"));
+ case INSN_CLASS_ZFHMIN_AND_D:
+ return (riscv_subset_supports (rps, "zfhmin")
+ && riscv_subset_supports (rps, "d"))
+ || (riscv_subset_supports (rps, "zhinxmin")
+ && riscv_subset_supports (rps, "zdinx"));
+ case INSN_CLASS_ZFHMIN_AND_Q:
+ return (riscv_subset_supports (rps, "zfhmin")
+ && riscv_subset_supports (rps, "q"))
+ || (riscv_subset_supports (rps, "zhinxmin")
+ && riscv_subset_supports (rps, "zqinx"));
case INSN_CLASS_ZBA:
return riscv_subset_supports (rps, "zba");
case INSN_CLASS_ZBB:
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 7b1fcc4346f..7bdb28192be 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -370,9 +370,11 @@ enum riscv_insn_class
INSN_CLASS_F_OR_ZFINX,
INSN_CLASS_D_OR_ZDINX,
INSN_CLASS_Q_OR_ZQINX,
- INSN_CLASS_ZFH,
- INSN_CLASS_D_AND_ZFH,
- INSN_CLASS_Q_AND_ZFH,
+ INSN_CLASS_ZFH_OR_ZHINX,
+ INSN_CLASS_ZFHMIN,
+ INSN_CLASS_ZFHMIN_OR_ZHINXMIN,
+ INSN_CLASS_ZFHMIN_AND_D,
+ INSN_CLASS_ZFHMIN_AND_Q,
INSN_CLASS_ZBA,
INSN_CLASS_ZBB,
INSN_CLASS_ZBC,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index bbd4a3718f6..e52365aab95 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -573,69 +573,69 @@ const struct riscv_opcode riscv_opcodes[] =
{"remuw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
/* Half-precision floating-point instruction subset. */
-{"flh", 0, INSN_CLASS_ZFH, "D,o(s)", MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"flh", 0, INSN_CLASS_ZFH, "D,A,s", 0, (int) M_FLH, match_never, INSN_MACRO },
-{"fsh", 0, INSN_CLASS_ZFH, "T,q(s)", MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"fsh", 0, INSN_CLASS_ZFH, "T,A,s", 0, (int) M_FSH, match_never, INSN_MACRO },
-{"fmv.h", 0, INSN_CLASS_ZFH, "D,U", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS },
-{"fneg.h", 0, INSN_CLASS_ZFH, "D,U", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_rs1_eq_rs2, INSN_ALIAS },
-{"fabs.h", 0, INSN_CLASS_ZFH, "D,U", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_rs1_eq_rs2, INSN_ALIAS },
-{"fsgnj.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 },
-{"fsgnjn.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 },
-{"fsgnjx.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 },
-{"fadd.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FADD_H|MASK_RM, MASK_FADD_H|MASK_RM, match_opcode, 0 },
-{"fadd.h", 0, INSN_CLASS_ZFH, "D,S,T,m", MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 },
-{"fsub.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FSUB_H|MASK_RM, MASK_FSUB_H|MASK_RM, match_opcode, 0 },
-{"fsub.h", 0, INSN_CLASS_ZFH, "D,S,T,m", MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 },
-{"fmul.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FMUL_H|MASK_RM, MASK_FMUL_H|MASK_RM, match_opcode, 0 },
-{"fmul.h", 0, INSN_CLASS_ZFH, "D,S,T,m", MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 },
-{"fdiv.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FDIV_H|MASK_RM, MASK_FDIV_H|MASK_RM, match_opcode, 0 },
-{"fdiv.h", 0, INSN_CLASS_ZFH, "D,S,T,m", MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 },
-{"fsqrt.h", 0, INSN_CLASS_ZFH, "D,S", MATCH_FSQRT_H|MASK_RM, MASK_FSQRT_H|MASK_RM, match_opcode, 0 },
-{"fsqrt.h", 0, INSN_CLASS_ZFH, "D,S,m", MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 },
-{"fmin.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 },
-{"fmax.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 },
-{"fmadd.h", 0, INSN_CLASS_ZFH, "D,S,T,R", MATCH_FMADD_H|MASK_RM, MASK_FMADD_H|MASK_RM, match_opcode, 0 },
-{"fmadd.h", 0, INSN_CLASS_ZFH, "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 },
-{"fnmadd.h", 0, INSN_CLASS_ZFH, "D,S,T,R", MATCH_FNMADD_H|MASK_RM, MASK_FNMADD_H|MASK_RM, match_opcode, 0 },
-{"fnmadd.h", 0, INSN_CLASS_ZFH, "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 },
-{"fmsub.h", 0, INSN_CLASS_ZFH, "D,S,T,R", MATCH_FMSUB_H|MASK_RM, MASK_FMSUB_H|MASK_RM, match_opcode, 0 },
-{"fmsub.h", 0, INSN_CLASS_ZFH, "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 },
-{"fnmsub.h", 0, INSN_CLASS_ZFH, "D,S,T,R", MATCH_FNMSUB_H|MASK_RM, MASK_FNMSUB_H|MASK_RM, match_opcode, 0 },
-{"fnmsub.h", 0, INSN_CLASS_ZFH, "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 },
-{"fcvt.w.h", 0, INSN_CLASS_ZFH, "d,S", MATCH_FCVT_W_H|MASK_RM, MASK_FCVT_W_H|MASK_RM, match_opcode, 0 },
-{"fcvt.w.h", 0, INSN_CLASS_ZFH, "d,S,m", MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 },
-{"fcvt.wu.h", 0, INSN_CLASS_ZFH, "d,S", MATCH_FCVT_WU_H|MASK_RM, MASK_FCVT_WU_H|MASK_RM, match_opcode, 0 },
-{"fcvt.wu.h", 0, INSN_CLASS_ZFH, "d,S,m", MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 },
-{"fcvt.h.w", 0, INSN_CLASS_ZFH, "D,s", MATCH_FCVT_H_W|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 },
-{"fcvt.h.w", 0, INSN_CLASS_ZFH, "D,s,m", MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
-{"fcvt.h.wu", 0, INSN_CLASS_ZFH, "D,s", MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 },
-{"fcvt.h.wu", 0, INSN_CLASS_ZFH, "D,s,m", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
-{"fcvt.s.h", 0, INSN_CLASS_ZFH, "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
-{"fcvt.d.h", 0, INSN_CLASS_D_AND_ZFH, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 },
-{"fcvt.q.h", 0, INSN_CLASS_Q_AND_ZFH, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 },
-{"fcvt.h.s", 0, INSN_CLASS_ZFH, "D,S", MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 },
-{"fcvt.h.s", 0, INSN_CLASS_ZFH, "D,S,m", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
-{"fcvt.h.d", 0, INSN_CLASS_D_AND_ZFH, "D,S", MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 },
-{"fcvt.h.d", 0, INSN_CLASS_D_AND_ZFH, "D,S,m", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 },
-{"fcvt.h.q", 0, INSN_CLASS_Q_AND_ZFH, "D,S", MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.h.q", 0, INSN_CLASS_Q_AND_ZFH, "D,S,m", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
-{"fclass.h", 0, INSN_CLASS_ZFH, "d,S", MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
-{"feq.h", 0, INSN_CLASS_ZFH, "d,S,T", MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
-{"flt.h", 0, INSN_CLASS_ZFH, "d,S,T", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
-{"fle.h", 0, INSN_CLASS_ZFH, "d,S,T", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
-{"fgt.h", 0, INSN_CLASS_ZFH, "d,T,S", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
-{"fge.h", 0, INSN_CLASS_ZFH, "d,T,S", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
-{"fmv.x.h", 0, INSN_CLASS_ZFH, "d,S", MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 },
-{"fmv.h.x", 0, INSN_CLASS_ZFH, "D,s", MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 },
-{"fcvt.l.h", 64, INSN_CLASS_ZFH, "d,S", MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 },
-{"fcvt.l.h", 64, INSN_CLASS_ZFH, "d,S,m", MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 },
-{"fcvt.lu.h", 64, INSN_CLASS_ZFH, "d,S", MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 },
-{"fcvt.lu.h", 64, INSN_CLASS_ZFH, "d,S,m", MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 },
-{"fcvt.h.l", 64, INSN_CLASS_ZFH, "D,s", MATCH_FCVT_H_L|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
-{"fcvt.h.l", 64, INSN_CLASS_ZFH, "D,s,m", MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 },
-{"fcvt.h.lu", 64, INSN_CLASS_ZFH, "D,s", MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
-{"fcvt.h.lu", 64, INSN_CLASS_ZFH, "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
+{"flh", 0, INSN_CLASS_ZFHMIN, "D,o(s)", MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"flh", 0, INSN_CLASS_ZFHMIN, "D,A,s", 0, (int) M_FLH, match_never, INSN_MACRO },
+{"fsh", 0, INSN_CLASS_ZFHMIN, "T,q(s)", MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"fsh", 0, INSN_CLASS_ZFHMIN, "T,A,s", 0, (int) M_FSH, match_never, INSN_MACRO },
+{"fmv.x.h", 0, INSN_CLASS_ZFHMIN, "d,S", MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 },
+{"fmv.h.x", 0, INSN_CLASS_ZFHMIN, "D,s", MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 },
+{"fmv.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,U", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS },
+{"fneg.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,U", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,U", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_rs1_eq_rs2, INSN_ALIAS },
+{"fsgnj.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 },
+{"fsgnjn.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 },
+{"fsgnjx.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 },
+{"fadd.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FADD_H|MASK_RM, MASK_FADD_H|MASK_RM, match_opcode, 0 },
+{"fadd.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,m", MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 },
+{"fsub.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FSUB_H|MASK_RM, MASK_FSUB_H|MASK_RM, match_opcode, 0 },
+{"fsub.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,m", MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 },
+{"fmul.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FMUL_H|MASK_RM, MASK_FMUL_H|MASK_RM, match_opcode, 0 },
+{"fmul.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,m", MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 },
+{"fdiv.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FDIV_H|MASK_RM, MASK_FDIV_H|MASK_RM, match_opcode, 0 },
+{"fdiv.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,m", MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 },
+{"fsqrt.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S", MATCH_FSQRT_H|MASK_RM, MASK_FSQRT_H|MASK_RM, match_opcode, 0 },
+{"fsqrt.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,m", MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 },
+{"fmin.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 },
+{"fmax.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T", MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 },
+{"fmadd.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R", MATCH_FMADD_H|MASK_RM, MASK_FMADD_H|MASK_RM, match_opcode, 0 },
+{"fmadd.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 },
+{"fnmadd.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R", MATCH_FNMADD_H|MASK_RM, MASK_FNMADD_H|MASK_RM, match_opcode, 0 },
+{"fnmadd.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 },
+{"fmsub.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R", MATCH_FMSUB_H|MASK_RM, MASK_FMSUB_H|MASK_RM, match_opcode, 0 },
+{"fmsub.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 },
+{"fnmsub.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R", MATCH_FNMSUB_H|MASK_RM, MASK_FNMSUB_H|MASK_RM, match_opcode, 0 },
+{"fnmsub.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 },
+{"fcvt.w.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S", MATCH_FCVT_W_H|MASK_RM, MASK_FCVT_W_H|MASK_RM, match_opcode, 0 },
+{"fcvt.w.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S,m", MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 },
+{"fcvt.wu.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S", MATCH_FCVT_WU_H|MASK_RM, MASK_FCVT_WU_H|MASK_RM, match_opcode, 0 },
+{"fcvt.wu.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S,m", MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 },
+{"fcvt.h.w", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,s", MATCH_FCVT_H_W|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 },
+{"fcvt.h.w", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,s,m", MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
+{"fcvt.h.wu", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,s", MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 },
+{"fcvt.h.wu", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,s,m", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
+{"fcvt.s.h", 0, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
+{"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 },
+{"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 },
+{"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, "D,S", MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 },
+{"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, "D,S,m", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
+{"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D, "D,S", MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 },
+{"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D, "D,S,m", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 },
+{"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q, "D,S", MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, 0 },
+{"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q, "D,S,m", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
+{"fclass.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S", MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
+{"feq.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S,T", MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
+{"flt.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S,T", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
+{"fle.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,S,T", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
+{"fgt.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,T,S", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
+{"fge.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "d,T,S", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
+{"fcvt.l.h", 64, INSN_CLASS_ZFH_OR_ZHINX, "d,S", MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 },
+{"fcvt.l.h", 64, INSN_CLASS_ZFH_OR_ZHINX, "d,S,m", MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 },
+{"fcvt.lu.h", 64, INSN_CLASS_ZFH_OR_ZHINX, "d,S", MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 },
+{"fcvt.lu.h", 64, INSN_CLASS_ZFH_OR_ZHINX, "d,S,m", MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 },
+{"fcvt.h.l", 64, INSN_CLASS_ZFH_OR_ZHINX, "D,s", MATCH_FCVT_H_L|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
+{"fcvt.h.l", 64, INSN_CLASS_ZFH_OR_ZHINX, "D,s,m", MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 },
+{"fcvt.h.lu", 64, INSN_CLASS_ZFH_OR_ZHINX, "D,s", MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_LU|MASK_RM, match_opcode, 0 },
+{"fcvt.h.lu", 64, INSN_CLASS_ZFH_OR_ZHINX, "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
/* Single-precision floating-point instruction subset. */
{"frcsr", 0, INSN_CLASS_F_OR_ZFINX, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 4/4] RISC-V: Add 'Zfh' / 'Zfhmin' conflict message
2022-05-22 5:15 ` [PATCH v2 0/4] RISC-V: Float16 extensions enhancements Tsukasa OI
` (2 preceding siblings ...)
2022-05-22 5:15 ` [PATCH v2 3/4] RISC-V: Add 'Zfhmin' (and refactor 'Zfh') Tsukasa OI
@ 2022-05-22 5:15 ` Tsukasa OI
2022-05-22 9:11 ` [PATCH 0/1] RISC-V: Zfh extension diagnostic addition Tsukasa OI
4 siblings, 0 replies; 15+ messages in thread
From: Tsukasa OI @ 2022-05-22 5:15 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit changes error message while checking extension conflicts
to include 'Zfh' and 'Zfhmin' extensions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_check_conflicts): Change error
message to include 'Zfh' and 'Zfhmin' extensions.
---
bfd/elfxx-riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 2dfbb08ca7c..5123e4a6fc4 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1905,7 +1905,7 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
&& riscv_lookup_subset (rps->subset_list, "f", &subset))
{
rps->error_handler
- (_("`zfinx' is conflict with the `f/d/q' extension"));
+ (_("`zfinx' is conflict with the `f/d/q/zfh/zfhmin' extension"));
no_conflict = false;
}
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 0/1] RISC-V: Zfh extension diagnostic addition
2022-05-22 5:15 ` [PATCH v2 0/4] RISC-V: Float16 extensions enhancements Tsukasa OI
` (3 preceding siblings ...)
2022-05-22 5:15 ` [PATCH v2 4/4] RISC-V: Add 'Zfh' / 'Zfhmin' conflict message Tsukasa OI
@ 2022-05-22 9:11 ` Tsukasa OI
2022-05-22 9:11 ` [PATCH 1/1] RISC-V: Add extension diagnostics to Zfh Tsukasa OI
4 siblings, 1 reply; 15+ messages in thread
From: Tsukasa OI @ 2022-05-22 9:11 UTC (permalink / raw)
To: Tsukasa OI, Palmer Dabbelt, Nelson Chu, Kito Cheng; +Cc: binutils
Hello,
This is an addition to:
<https://sourceware.org/pipermail/binutils/2022-May/120935.html>
I and Nelson forgot to add extension diagnostics to
`riscv_multi_subset_supports_ext' function (bfd/elfxx-riscv.c).
This patch adds related diagnostics for instruction classes I added in
my Zfh+Zfhmin PATCHSET v2.
Note that, even if instruction class name suggests Zhinx and Zhinxmin,
this is not represented in `riscv_multi_subset_supports_ext' since they
are not officially supported yet.
I note that consensus to place 'H' after 'V' is made:
<https://github.com/riscv/riscv-isa-manual/issues/837>
So, it's going to be canonical to order Zh* extensions after all Zv*.
Considering compatibility and that consensus, we could change
`riscv_ext_canonical_order'...
from "eigmafdqlcbkjtpvn"
to "eigmafdqlcbkjtpvnh" (add H to the tail)
and then we can add Zhinx and Zhinxmin extensions to supported extension
list: `riscv_supported_std_z_ext'. (I'm not sure **when** to do that;
after new ISA manual is ratified? or now?)
Tsukasa OI (1):
RISC-V: Add extension diagnostics to Zfh
bfd/elfxx-riscv.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
base-commit: 7d599d2e1a4fe39de46da8510c4e24bf6b698805
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/1] RISC-V: Add extension diagnostics to Zfh
2022-05-22 9:11 ` [PATCH 0/1] RISC-V: Zfh extension diagnostic addition Tsukasa OI
@ 2022-05-22 9:11 ` Tsukasa OI
0 siblings, 0 replies; 15+ messages in thread
From: Tsukasa OI @ 2022-05-22 9:11 UTC (permalink / raw)
To: Tsukasa OI, Palmer Dabbelt, Nelson Chu, Kito Cheng; +Cc: binutils
This commit adds extension diagnostics for five Zfh-related instruction
classes.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports_ext): Add
diagnostics for five Zfh-related instruction classes.
---
bfd/elfxx-riscv.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 5123e4a6fc4..ee996ddfce8 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -2483,6 +2483,28 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "d' or `zdinx";
case INSN_CLASS_Q_OR_ZQINX:
return "q' or `zqinx";
+ case INSN_CLASS_ZFH_OR_ZHINX:
+ return "zfh";
+ case INSN_CLASS_ZFHMIN:
+ return "zfhmin";
+ case INSN_CLASS_ZFHMIN_OR_ZHINXMIN:
+ return "zfhmin";
+ case INSN_CLASS_ZFHMIN_AND_D:
+ if (!riscv_subset_supports (rps, "zfhmin")
+ && !riscv_subset_supports (rps, "d"))
+ return "zfhmin' and `d";
+ else if (!riscv_subset_supports (rps, "zfhmin"))
+ return "zfhmin";
+ else
+ return "d";
+ case INSN_CLASS_ZFHMIN_AND_Q:
+ if (!riscv_subset_supports (rps, "zfhmin")
+ && !riscv_subset_supports (rps, "q"))
+ return "zfhmin' and `q";
+ else if (!riscv_subset_supports (rps, "zfhmin"))
+ return "zfhmin";
+ else
+ return "q";
case INSN_CLASS_ZBA:
return "zba";
case INSN_CLASS_ZBB:
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2022-05-22 9:11 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-11 10:47 [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 1/5] RISC-V: Add 'Zfh' and 'Zfhmin' extensions Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 2/5] RISC-V: Add insn classes for Zfh/Zfhmin extensions Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 3/5] RISC-V: Add 'Zfh' and 'Zfhmin' instructions Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 4/5] RISC-V: Add 'flh' and 'fsh' macro instructions Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 5/5] RISC-V: Add 'Zfh'/'Zfhmin' conflict message Tsukasa OI
2022-05-18 1:43 ` [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions Kito Cheng
2022-05-18 9:31 ` Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 0/4] RISC-V: Float16 extensions enhancements Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 1/4] RISC-V: Refactor 'Zfh'-related macros Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 2/4] RISC-V: Add instruction declaration for 'Zfh' Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 3/4] RISC-V: Add 'Zfhmin' (and refactor 'Zfh') Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 4/4] RISC-V: Add 'Zfh' / 'Zfhmin' conflict message Tsukasa OI
2022-05-22 9:11 ` [PATCH 0/1] RISC-V: Zfh extension diagnostic addition Tsukasa OI
2022-05-22 9:11 ` [PATCH 1/1] RISC-V: Add extension diagnostics to Zfh Tsukasa OI
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