* [RFC PATCH 1/6] RISC-V: Add Zvkb ISA extension support
2022-12-21 17:07 [RFC PATCH 0/6] RISC-V: Add support for vector crypto extensions Christoph Muellner
@ 2022-12-21 17:07 ` Christoph Muellner
2022-12-21 20:50 ` Jeff Law
2023-01-20 19:04 ` Philipp Tomsich
2022-12-21 17:07 ` [RFC PATCH 2/6] RISC-V: Add Zvkg " Christoph Muellner
` (5 subsequent siblings)
6 siblings, 2 replies; 19+ messages in thread
From: Christoph Muellner @ 2022-12-21 17:07 UTC (permalink / raw)
To: binutils, Nelson Chu, Andrew Waterman, Palmer Dabbelt,
Jim Wilson, Philipp Tomsich, Aaron Durbin, Andrew de los Reyes,
Eric Gouriou, Barna Ibrahim
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
This commit adds the Zvkb ISA extension instructions, which are part
of the vector crypto extensions.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 5 ++++
gas/config/tc-riscv.c | 13 ++++++++++
gas/testsuite/gas/riscv/zvkb.d | 36 ++++++++++++++++++++++++++++
gas/testsuite/gas/riscv/zvkb.s | 28 ++++++++++++++++++++++
include/opcode/riscv-opc.h | 44 ++++++++++++++++++++++++++++++++++
include/opcode/riscv.h | 5 ++++
opcodes/riscv-dis.c | 4 ++++
opcodes/riscv-opc.c | 16 +++++++++++++
8 files changed, 151 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvkb.d
create mode 100644 gas/testsuite/gas/riscv/zvkb.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 0bcf2fdcfa3..22a6954ff41 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1205,6 +1205,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zve64x", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zve64f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2415,6 +2416,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
|| riscv_subset_supports (rps, "zve64d")
|| riscv_subset_supports (rps, "zve64f")
|| riscv_subset_supports (rps, "zve32f"));
+ case INSN_CLASS_ZVKB:
+ return riscv_subset_supports (rps, "zvkb");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2573,6 +2576,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("v' or `zve64x' or `zve32x");
case INSN_CLASS_ZVEF:
return _("v' or `zve64d' or `zve64f' or `zve32f");
+ case INSN_CLASS_ZVKB:
+ return _("zvkb");
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 77c0d2e32ab..51d302127c5 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1322,6 +1322,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'i':
case 'j':
case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break;
+ case 'l': used_bits |= ENCODE_RVV_VI_UIMM6(-1U); break;
case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break;
case 'M': break; /* Macro operand, must be a mask register. */
case 'T': break; /* Macro operand, must be a vector register. */
@@ -2981,6 +2982,18 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
asarg = expr_end;
continue;
+ case 'l': /* 6-bit vector arith unsigned immediate */
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, FALSE);
+ if (imm_expr->X_add_number < 0
+ || imm_expr->X_add_number >= 64)
+ as_bad (_("bad value for vector immediate field, "
+ "value must be 0...63"));
+ ip->insn_opcode |= ENCODE_RVV_VI_UIMM6 (imm_expr->X_add_number);
+ imm_expr->X_op = O_absent;
+ asarg = expr_end;
+ continue;
+
case 'm': /* optional vector mask */
if (*asarg == '\0')
{
diff --git a/gas/testsuite/gas/riscv/zvkb.d b/gas/testsuite/gas/riscv/zvkb.d
new file mode 100644
index 00000000000..63aacba951c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkb.d
@@ -0,0 +1,36 @@
+#as: -march=rv64gc_zvkb
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+32862257[ ]+vclmul.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+30862257[ ]+vclmul.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+3285e257[ ]+vclmul.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+3085e257[ ]+vclmul.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+36862257[ ]+vclmulh.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+34862257[ ]+vclmulh.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+3685e257[ ]+vclmulh.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+3485e257[ ]+vclmulh.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+56860257[ ]+vrol.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+54860257[ ]+vrol.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+5685c257[ ]+vrol.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+5485c257[ ]+vrol.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+52860257[ ]+vror.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+50860257[ ]+vror.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+5285c257[ ]+vror.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+5085c257[ ]+vror.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+52803257[ ]+vror.vi[ ]+v4,v8,0
+[ ]+[0-9a-f]+:[ ]+548fb257[ ]+vror.vi[ ]+v4,v8,63,v0.t
+[ ]+[0-9a-f]+:[ ]+4a842257[ ]+vbrev8.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+48842257[ ]+vbrev8.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+06860257[ ]+vandn.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+04860257[ ]+vandn.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+0685c257[ ]+vandn.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+0485c257[ ]+vandn.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+0687b257[ ]+vandn.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+04883257[ ]+vandn.vi[ ]+v4,v8,-16,v0.t
diff --git a/gas/testsuite/gas/riscv/zvkb.s b/gas/testsuite/gas/riscv/zvkb.s
new file mode 100644
index 00000000000..fd741505883
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkb.s
@@ -0,0 +1,28 @@
+ vclmul.vv v4, v8, v12
+ vclmul.vv v4, v8, v12, v0.t
+ vclmul.vx v4, v8, a1
+ vclmul.vx v4, v8, a1, v0.t
+ vclmulh.vv v4, v8, v12
+ vclmulh.vv v4, v8, v12, v0.t
+ vclmulh.vx v4, v8, a1
+ vclmulh.vx v4, v8, a1, v0.t
+ vrol.vv v4, v8, v12
+ vrol.vv v4, v8, v12, v0.t
+ vrol.vx v4, v8, a1
+ vrol.vx v4, v8, a1, v0.t
+ vror.vv v4, v8, v12
+ vror.vv v4, v8, v12, v0.t
+ vror.vx v4, v8, a1
+ vror.vx v4, v8, a1, v0.t
+ vror.vi v4, v8, 0
+ vror.vi v4, v8, 63, v0.t
+ vbrev8.v v4, v8
+ vbrev8.v v4, v8, v0.t
+ vrev8.v v4, v8
+ vrev8.v v4, v8, v0.t
+ vandn.vv v4, v8, v12
+ vandn.vv v4, v8, v12, v0.t
+ vandn.vx v4, v8, a1
+ vandn.vx v4, v8, a1, v0.t
+ vandn.vi v4, v8, 15
+ vandn.vi v4, v8, -16, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 06e3df0f5a6..575fa5d322c 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2055,6 +2055,35 @@
#define MASK_VDOTUVV 0xfc00707f
#define MATCH_VFDOTVV 0xe4001057
#define MASK_VFDOTVV 0xfc00707f
+/* Zvkb instructions. */
+#define MATCH_VCLMULVV 0x30002057
+#define MASK_VCLMULVV 0xfc00707f
+#define MATCH_VCLMULVX 0x30006057
+#define MASK_VCLMULVX 0xfc00707f
+#define MATCH_VCLMULHVV 0x34002057
+#define MASK_VCLMULHVV 0xfc00707f
+#define MATCH_VCLMULHVX 0x34006057
+#define MASK_VCLMULHVX 0xfc00707f
+#define MATCH_VROLVV 0x54000057
+#define MASK_VROLVV 0xfc00707f
+#define MATCH_VROLVX 0x54004057
+#define MASK_VROLVX 0xfc00707f
+#define MATCH_VRORVV 0x50000057
+#define MASK_VRORVV 0xfc00707f
+#define MATCH_VRORVX 0x50004057
+#define MASK_VRORVX 0xfc00707f
+#define MATCH_VRORVI 0x50003057
+#define MASK_VRORVI 0xf800707f
+#define MATCH_VBREV8V 0x48042057
+#define MASK_VBREV8V 0xfc0ff07f
+#define MATCH_VREV8V 0x4804a057
+#define MASK_VREV8V 0xfc0ff07f
+#define MATCH_VANDNVV 0x04000057
+#define MASK_VANDNVV 0xfc00707f
+#define MATCH_VANDNVX 0x04004057
+#define MASK_VANDNVX 0xfc00707f
+#define MATCH_VANDNVI 0x04003057
+#define MASK_VANDNVI 0xfc00707f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3118,6 +3147,21 @@ DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
/* Zawrs instructions. */
DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
+/* Zvkb instructions. */
+DECLARE_INSN(vclmulvv, MATCH_VCLMULVV, MASK_VCLMULVV)
+DECLARE_INSN(vclmulvx, MATCH_VCLMULVX, MASK_VCLMULVX)
+DECLARE_INSN(vclmulhvv, MATCH_VCLMULHVV, MASK_VCLMULHVV)
+DECLARE_INSN(vclmulhvx, MATCH_VCLMULHVX, MASK_VCLMULHVX)
+DECLARE_INSN(vrolvv, MATCH_VROLVV, MASK_VROLVV)
+DECLARE_INSN(vrolvx, MATCH_VROLVX, MASK_VROLVX)
+DECLARE_INSN(vrorvv, MATCH_VRORVV, MASK_VRORVV)
+DECLARE_INSN(vrorvx, MATCH_VRORVX, MASK_VRORVX)
+DECLARE_INSN(vrorvi, MATCH_VRORVI, MASK_VRORVI)
+DECLARE_INSN(vbrev8v, MATCH_VBREV8V, MASK_VBREV8V)
+DECLARE_INSN(vrev8v, MATCH_VREV8V, MASK_VREV8V)
+DECLARE_INSN(vandnvv, MATCH_VANDNVV, MASK_VANDNVV)
+DECLARE_INSN(vandnvx, MATCH_VANDNVX, MASK_VANDNVX)
+DECLARE_INSN(vandnvi, MATCH_VANDNVI, MASK_VANDNVI)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index c3cbde600cb..1ba123e4933 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -100,6 +100,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
#define EXTRACT_RVV_VI_UIMM(x) \
(RV_X(x, 15, 5))
+#define EXTRACT_RVV_VI_UIMM6(x) \
+ (RV_X(x, 15, 5) | (RV_X(x, 26, 1) << 5))
#define EXTRACT_RVV_OFFSET(x) \
(RV_X(x, 29, 3))
#define EXTRACT_RVV_VB_IMM(x) \
@@ -151,6 +153,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 0, 10) << 20)
#define ENCODE_RVV_VC_IMM(x) \
(RV_X(x, 0, 11) << 20)
+#define ENCODE_RVV_VI_UIMM6(x) \
+ (RV_X(x, 0, 5) << 15 | RV_X(x, 5, 1) << 26)
#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
@@ -405,6 +409,7 @@ enum riscv_insn_class
INSN_CLASS_ZKND_OR_ZKNE,
INSN_CLASS_V,
INSN_CLASS_ZVEF,
+ INSN_CLASS_ZVKB,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 0e1f3b4610a..6bb21ebb56f 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -397,6 +397,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
print (info->stream, dis_style_immediate, "%d",
(int)EXTRACT_RVV_OFFSET (l));
break;
+ case 'l':
+ print (info->stream, dis_style_immediate, "%d",
+ (int)EXTRACT_RVV_VI_UIMM6 (l));
+ break;
case 'm':
if (!EXTRACT_OPERAND (VMASK, l))
{
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 0e691544f9b..98ca3a4cc56 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1815,6 +1815,22 @@ const struct riscv_opcode riscv_opcodes[] =
{"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_opcode, 0},
{"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_opcode, 0},
+/* Zvkb instructions. */
+{"vclmul.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VCLMULVV, MASK_VCLMULVV, match_opcode, 0},
+{"vclmul.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VCLMULVX, MASK_VCLMULVX, match_opcode, 0},
+{"vclmulh.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VCLMULHVV, MASK_VCLMULHVV, match_opcode, 0},
+{"vclmulh.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VCLMULHVX, MASK_VCLMULHVX, match_opcode, 0},
+{"vrol.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VROLVV, MASK_VROLVV, match_opcode, 0},
+{"vrol.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VROLVX, MASK_VROLVX, match_opcode, 0},
+{"vror.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VRORVV, MASK_VRORVV, match_opcode, 0},
+{"vror.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VRORVX, MASK_VRORVX, match_opcode, 0},
+{"vror.vi", 0, INSN_CLASS_ZVKB, "Vd,Vt,VlVm", MATCH_VRORVI, MASK_VRORVI, match_opcode, 0},
+{"vbrev8.v", 0, INSN_CLASS_ZVKB, "Vd,VtVm", MATCH_VBREV8V, MASK_VBREV8V, match_opcode, 0},
+{"vrev8.v", 0, INSN_CLASS_ZVKB, "Vd,VtVm", MATCH_VREV8V, MASK_VREV8V, match_opcode, 0},
+{"vandn.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDNVV, MASK_VANDNVV, match_opcode, 0},
+{"vandn.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDNVX, MASK_VANDNVX, match_opcode, 0},
+{"vandn.vi", 0, INSN_CLASS_ZVKB, "Vd,Vt,ViVm", MATCH_VANDNVI, MASK_VANDNVI, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
--
2.38.1
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [RFC PATCH 1/6] RISC-V: Add Zvkb ISA extension support
2022-12-21 17:07 ` [RFC PATCH 1/6] RISC-V: Add Zvkb ISA extension support Christoph Muellner
@ 2022-12-21 20:50 ` Jeff Law
2022-12-22 14:23 ` Christoph Müllner
2023-01-20 19:04 ` Philipp Tomsich
1 sibling, 1 reply; 19+ messages in thread
From: Jeff Law @ 2022-12-21 20:50 UTC (permalink / raw)
To: Christoph Muellner, binutils, Nelson Chu, Andrew Waterman,
Palmer Dabbelt, Jim Wilson, Philipp Tomsich, Aaron Durbin,
Andrew de los Reyes, Eric Gouriou, Barna Ibrahim
On 12/21/22 10:07, Christoph Muellner wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This commit adds the Zvkb ISA extension instructions, which are part
> of the vector crypto extensions.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
> bfd/elfxx-riscv.c | 5 ++++
> gas/config/tc-riscv.c | 13 ++++++++++
> gas/testsuite/gas/riscv/zvkb.d | 36 ++++++++++++++++++++++++++++
> gas/testsuite/gas/riscv/zvkb.s | 28 ++++++++++++++++++++++
> include/opcode/riscv-opc.h | 44 ++++++++++++++++++++++++++++++++++
> include/opcode/riscv.h | 5 ++++
> opcodes/riscv-dis.c | 4 ++++
> opcodes/riscv-opc.c | 16 +++++++++++++
> 8 files changed, 151 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/zvkb.d
> create mode 100644 gas/testsuite/gas/riscv/zvkb.s
It all looks quite sensible to me.
> +/* Zvkb instructions. */
> +#define MATCH_VCLMULVV 0x30002057
> +#define MASK_VCLMULVV 0xfc00707f
I'm just going to trust you got these right and that the MATCH value in
particular might need adjustment if the encodings change.
> +DECLARE_INSN(vclmulvv, MATCH_VCLMULVV, MASK_VCLMULVV)
So IIRC, these are only used in GDB's prologue/epilogue scanning code --
and we're quite unlikely to ever need any of these instructions for
prologues/epilogues. I'm guessing convention is to go ahead and add the
DECLARE_INSN instances for each instruction, even if they aren't likely
to be show up in a prologue or epilogue?
Jeff
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [RFC PATCH 1/6] RISC-V: Add Zvkb ISA extension support
2022-12-21 20:50 ` Jeff Law
@ 2022-12-22 14:23 ` Christoph Müllner
0 siblings, 0 replies; 19+ messages in thread
From: Christoph Müllner @ 2022-12-22 14:23 UTC (permalink / raw)
To: Jeff Law
Cc: binutils, Nelson Chu, Andrew Waterman, Palmer Dabbelt,
Jim Wilson, Philipp Tomsich, Aaron Durbin, Andrew de los Reyes,
Eric Gouriou, Barna Ibrahim
[-- Attachment #1: Type: text/plain, Size: 2083 bytes --]
On Wed, Dec 21, 2022 at 9:50 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
> On 12/21/22 10:07, Christoph Muellner wrote:
> > From: Christoph Müllner <christoph.muellner@vrull.eu>
> >
> > This commit adds the Zvkb ISA extension instructions, which are part
> > of the vector crypto extensions.
> >
> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > ---
> > bfd/elfxx-riscv.c | 5 ++++
> > gas/config/tc-riscv.c | 13 ++++++++++
> > gas/testsuite/gas/riscv/zvkb.d | 36 ++++++++++++++++++++++++++++
> > gas/testsuite/gas/riscv/zvkb.s | 28 ++++++++++++++++++++++
> > include/opcode/riscv-opc.h | 44 ++++++++++++++++++++++++++++++++++
> > include/opcode/riscv.h | 5 ++++
> > opcodes/riscv-dis.c | 4 ++++
> > opcodes/riscv-opc.c | 16 +++++++++++++
> > 8 files changed, 151 insertions(+)
> > create mode 100644 gas/testsuite/gas/riscv/zvkb.d
> > create mode 100644 gas/testsuite/gas/riscv/zvkb.s
> It all looks quite sensible to me.
>
>
> > +/* Zvkb instructions. */
> > +#define MATCH_VCLMULVV 0x30002057
> > +#define MASK_VCLMULVV 0xfc00707f
> I'm just going to trust you got these right and that the MATCH value in
> particular might need adjustment if the encodings change.
>
In fact, they changed two days ago (clmul, clmulh, rotl, rotr).
So I had to adjust these before sending the patchset on the list.
When doing so, I rechecked all Zvkb, so I'm quite sure they are good.
>
>
>
> > +DECLARE_INSN(vclmulvv, MATCH_VCLMULVV, MASK_VCLMULVV)
> So IIRC, these are only used in GDB's prologue/epilogue scanning code --
> and we're quite unlikely to ever need any of these instructions for
> prologues/epilogues. I'm guessing convention is to go ahead and add the
> DECLARE_INSN instances for each instruction, even if they aren't likely
> to be show up in a prologue or epilogue?
>
Honestly, I'm not sure what to list here and what not (and I did not see
any policy).
Therefore, in doubt, I always add these.
>
> Jeff
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [RFC PATCH 1/6] RISC-V: Add Zvkb ISA extension support
2022-12-21 17:07 ` [RFC PATCH 1/6] RISC-V: Add Zvkb ISA extension support Christoph Muellner
2022-12-21 20:50 ` Jeff Law
@ 2023-01-20 19:04 ` Philipp Tomsich
2023-01-20 19:21 ` Christoph Müllner
1 sibling, 1 reply; 19+ messages in thread
From: Philipp Tomsich @ 2023-01-20 19:04 UTC (permalink / raw)
To: Christoph Muellner
Cc: binutils, Nelson Chu, Andrew Waterman, Palmer Dabbelt,
Jim Wilson, Aaron Durbin, Andrew de los Reyes, Eric Gouriou,
Barna Ibrahim
On Wed, 21 Dec 2022 at 18:07, Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This commit adds the Zvkb ISA extension instructions, which are part
> of the vector crypto extensions.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
> bfd/elfxx-riscv.c | 5 ++++
> gas/config/tc-riscv.c | 13 ++++++++++
> gas/testsuite/gas/riscv/zvkb.d | 36 ++++++++++++++++++++++++++++
> gas/testsuite/gas/riscv/zvkb.s | 28 ++++++++++++++++++++++
> include/opcode/riscv-opc.h | 44 ++++++++++++++++++++++++++++++++++
> include/opcode/riscv.h | 5 ++++
> opcodes/riscv-dis.c | 4 ++++
> opcodes/riscv-opc.c | 16 +++++++++++++
> 8 files changed, 151 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/zvkb.d
> create mode 100644 gas/testsuite/gas/riscv/zvkb.s
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 0bcf2fdcfa3..22a6954ff41 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1205,6 +1205,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
> {"zve64x", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zve64f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> @@ -2415,6 +2416,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
> || riscv_subset_supports (rps, "zve64d")
> || riscv_subset_supports (rps, "zve64f")
> || riscv_subset_supports (rps, "zve32f"));
> + case INSN_CLASS_ZVKB:
> + return riscv_subset_supports (rps, "zvkb");
> case INSN_CLASS_SVINVAL:
> return riscv_subset_supports (rps, "svinval");
> case INSN_CLASS_H:
> @@ -2573,6 +2576,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
> return _("v' or `zve64x' or `zve32x");
> case INSN_CLASS_ZVEF:
> return _("v' or `zve64d' or `zve64f' or `zve32f");
> + case INSN_CLASS_ZVKB:
> + return _("zvkb");
> case INSN_CLASS_SVINVAL:
> return "svinval";
> case INSN_CLASS_H:
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 77c0d2e32ab..51d302127c5 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -1322,6 +1322,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
> case 'i':
> case 'j':
> case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break;
> + case 'l': used_bits |= ENCODE_RVV_VI_UIMM6(-1U); break;
> case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break;
> case 'M': break; /* Macro operand, must be a mask register. */
> case 'T': break; /* Macro operand, must be a vector register. */
> @@ -2981,6 +2982,18 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
> asarg = expr_end;
> continue;
>
> + case 'l': /* 6-bit vector arith unsigned immediate */
> + my_getExpression (imm_expr, asarg);
> + check_absolute_expr (ip, imm_expr, FALSE);
> + if (imm_expr->X_add_number < 0
> + || imm_expr->X_add_number >= 64)
> + as_bad (_("bad value for vector immediate field, "
> + "value must be 0...63"));
> + ip->insn_opcode |= ENCODE_RVV_VI_UIMM6 (imm_expr->X_add_number);
> + imm_expr->X_op = O_absent;
> + asarg = expr_end;
This has to be adjusted (after 6eb099ae9324), as expr_end has been
renamed to expr_parse_end.
Note that the old version will still compile (although with a
warning), as expr_end is now a function exported from expr.c.
Please roll this change/adjustment into the next version of the series.
Thanks,
Philipp.
> + continue;
> +
> case 'm': /* optional vector mask */
> if (*asarg == '\0')
> {
> diff --git a/gas/testsuite/gas/riscv/zvkb.d b/gas/testsuite/gas/riscv/zvkb.d
> new file mode 100644
> index 00000000000..63aacba951c
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zvkb.d
> @@ -0,0 +1,36 @@
> +#as: -march=rv64gc_zvkb
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +0+000 <.text>:
> +[ ]+[0-9a-f]+:[ ]+32862257[ ]+vclmul.vv[ ]+v4,v8,v12
> +[ ]+[0-9a-f]+:[ ]+30862257[ ]+vclmul.vv[ ]+v4,v8,v12,v0.t
> +[ ]+[0-9a-f]+:[ ]+3285e257[ ]+vclmul.vx[ ]+v4,v8,a1
> +[ ]+[0-9a-f]+:[ ]+3085e257[ ]+vclmul.vx[ ]+v4,v8,a1,v0.t
> +[ ]+[0-9a-f]+:[ ]+36862257[ ]+vclmulh.vv[ ]+v4,v8,v12
> +[ ]+[0-9a-f]+:[ ]+34862257[ ]+vclmulh.vv[ ]+v4,v8,v12,v0.t
> +[ ]+[0-9a-f]+:[ ]+3685e257[ ]+vclmulh.vx[ ]+v4,v8,a1
> +[ ]+[0-9a-f]+:[ ]+3485e257[ ]+vclmulh.vx[ ]+v4,v8,a1,v0.t
> +[ ]+[0-9a-f]+:[ ]+56860257[ ]+vrol.vv[ ]+v4,v8,v12
> +[ ]+[0-9a-f]+:[ ]+54860257[ ]+vrol.vv[ ]+v4,v8,v12,v0.t
> +[ ]+[0-9a-f]+:[ ]+5685c257[ ]+vrol.vx[ ]+v4,v8,a1
> +[ ]+[0-9a-f]+:[ ]+5485c257[ ]+vrol.vx[ ]+v4,v8,a1,v0.t
> +[ ]+[0-9a-f]+:[ ]+52860257[ ]+vror.vv[ ]+v4,v8,v12
> +[ ]+[0-9a-f]+:[ ]+50860257[ ]+vror.vv[ ]+v4,v8,v12,v0.t
> +[ ]+[0-9a-f]+:[ ]+5285c257[ ]+vror.vx[ ]+v4,v8,a1
> +[ ]+[0-9a-f]+:[ ]+5085c257[ ]+vror.vx[ ]+v4,v8,a1,v0.t
> +[ ]+[0-9a-f]+:[ ]+52803257[ ]+vror.vi[ ]+v4,v8,0
> +[ ]+[0-9a-f]+:[ ]+548fb257[ ]+vror.vi[ ]+v4,v8,63,v0.t
> +[ ]+[0-9a-f]+:[ ]+4a842257[ ]+vbrev8.v[ ]+v4,v8
> +[ ]+[0-9a-f]+:[ ]+48842257[ ]+vbrev8.v[ ]+v4,v8,v0.t
> +[ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8
> +[ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t
> +[ ]+[0-9a-f]+:[ ]+06860257[ ]+vandn.vv[ ]+v4,v8,v12
> +[ ]+[0-9a-f]+:[ ]+04860257[ ]+vandn.vv[ ]+v4,v8,v12,v0.t
> +[ ]+[0-9a-f]+:[ ]+0685c257[ ]+vandn.vx[ ]+v4,v8,a1
> +[ ]+[0-9a-f]+:[ ]+0485c257[ ]+vandn.vx[ ]+v4,v8,a1,v0.t
> +[ ]+[0-9a-f]+:[ ]+0687b257[ ]+vandn.vi[ ]+v4,v8,15
> +[ ]+[0-9a-f]+:[ ]+04883257[ ]+vandn.vi[ ]+v4,v8,-16,v0.t
> diff --git a/gas/testsuite/gas/riscv/zvkb.s b/gas/testsuite/gas/riscv/zvkb.s
> new file mode 100644
> index 00000000000..fd741505883
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zvkb.s
> @@ -0,0 +1,28 @@
> + vclmul.vv v4, v8, v12
> + vclmul.vv v4, v8, v12, v0.t
> + vclmul.vx v4, v8, a1
> + vclmul.vx v4, v8, a1, v0.t
> + vclmulh.vv v4, v8, v12
> + vclmulh.vv v4, v8, v12, v0.t
> + vclmulh.vx v4, v8, a1
> + vclmulh.vx v4, v8, a1, v0.t
> + vrol.vv v4, v8, v12
> + vrol.vv v4, v8, v12, v0.t
> + vrol.vx v4, v8, a1
> + vrol.vx v4, v8, a1, v0.t
> + vror.vv v4, v8, v12
> + vror.vv v4, v8, v12, v0.t
> + vror.vx v4, v8, a1
> + vror.vx v4, v8, a1, v0.t
> + vror.vi v4, v8, 0
> + vror.vi v4, v8, 63, v0.t
> + vbrev8.v v4, v8
> + vbrev8.v v4, v8, v0.t
> + vrev8.v v4, v8
> + vrev8.v v4, v8, v0.t
> + vandn.vv v4, v8, v12
> + vandn.vv v4, v8, v12, v0.t
> + vandn.vx v4, v8, a1
> + vandn.vx v4, v8, a1, v0.t
> + vandn.vi v4, v8, 15
> + vandn.vi v4, v8, -16, v0.t
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 06e3df0f5a6..575fa5d322c 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2055,6 +2055,35 @@
> #define MASK_VDOTUVV 0xfc00707f
> #define MATCH_VFDOTVV 0xe4001057
> #define MASK_VFDOTVV 0xfc00707f
> +/* Zvkb instructions. */
> +#define MATCH_VCLMULVV 0x30002057
> +#define MASK_VCLMULVV 0xfc00707f
> +#define MATCH_VCLMULVX 0x30006057
> +#define MASK_VCLMULVX 0xfc00707f
> +#define MATCH_VCLMULHVV 0x34002057
> +#define MASK_VCLMULHVV 0xfc00707f
> +#define MATCH_VCLMULHVX 0x34006057
> +#define MASK_VCLMULHVX 0xfc00707f
> +#define MATCH_VROLVV 0x54000057
> +#define MASK_VROLVV 0xfc00707f
> +#define MATCH_VROLVX 0x54004057
> +#define MASK_VROLVX 0xfc00707f
> +#define MATCH_VRORVV 0x50000057
> +#define MASK_VRORVV 0xfc00707f
> +#define MATCH_VRORVX 0x50004057
> +#define MASK_VRORVX 0xfc00707f
> +#define MATCH_VRORVI 0x50003057
> +#define MASK_VRORVI 0xf800707f
> +#define MATCH_VBREV8V 0x48042057
> +#define MASK_VBREV8V 0xfc0ff07f
> +#define MATCH_VREV8V 0x4804a057
> +#define MASK_VREV8V 0xfc0ff07f
> +#define MATCH_VANDNVV 0x04000057
> +#define MASK_VANDNVV 0xfc00707f
> +#define MATCH_VANDNVX 0x04004057
> +#define MASK_VANDNVX 0xfc00707f
> +#define MATCH_VANDNVI 0x04003057
> +#define MASK_VANDNVI 0xfc00707f
> /* Svinval instruction. */
> #define MATCH_SINVAL_VMA 0x16000073
> #define MASK_SINVAL_VMA 0xfe007fff
> @@ -3118,6 +3147,21 @@ DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
> /* Zawrs instructions. */
> DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
> DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
> +/* Zvkb instructions. */
> +DECLARE_INSN(vclmulvv, MATCH_VCLMULVV, MASK_VCLMULVV)
> +DECLARE_INSN(vclmulvx, MATCH_VCLMULVX, MASK_VCLMULVX)
> +DECLARE_INSN(vclmulhvv, MATCH_VCLMULHVV, MASK_VCLMULHVV)
> +DECLARE_INSN(vclmulhvx, MATCH_VCLMULHVX, MASK_VCLMULHVX)
> +DECLARE_INSN(vrolvv, MATCH_VROLVV, MASK_VROLVV)
> +DECLARE_INSN(vrolvx, MATCH_VROLVX, MASK_VROLVX)
> +DECLARE_INSN(vrorvv, MATCH_VRORVV, MASK_VRORVV)
> +DECLARE_INSN(vrorvx, MATCH_VRORVX, MASK_VRORVX)
> +DECLARE_INSN(vrorvi, MATCH_VRORVI, MASK_VRORVI)
> +DECLARE_INSN(vbrev8v, MATCH_VBREV8V, MASK_VBREV8V)
> +DECLARE_INSN(vrev8v, MATCH_VREV8V, MASK_VREV8V)
> +DECLARE_INSN(vandnvv, MATCH_VANDNVV, MASK_VANDNVV)
> +DECLARE_INSN(vandnvx, MATCH_VANDNVX, MASK_VANDNVX)
> +DECLARE_INSN(vandnvi, MATCH_VANDNVI, MASK_VANDNVI)
> /* Vendor-specific (T-Head) XTheadBa instructions. */
> DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
> /* Vendor-specific (T-Head) XTheadBb instructions. */
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index c3cbde600cb..1ba123e4933 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -100,6 +100,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
> (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
> #define EXTRACT_RVV_VI_UIMM(x) \
> (RV_X(x, 15, 5))
> +#define EXTRACT_RVV_VI_UIMM6(x) \
> + (RV_X(x, 15, 5) | (RV_X(x, 26, 1) << 5))
> #define EXTRACT_RVV_OFFSET(x) \
> (RV_X(x, 29, 3))
> #define EXTRACT_RVV_VB_IMM(x) \
> @@ -151,6 +153,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
> (RV_X(x, 0, 10) << 20)
> #define ENCODE_RVV_VC_IMM(x) \
> (RV_X(x, 0, 11) << 20)
> +#define ENCODE_RVV_VI_UIMM6(x) \
> + (RV_X(x, 0, 5) << 15 | RV_X(x, 5, 1) << 26)
>
> #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
> #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
> @@ -405,6 +409,7 @@ enum riscv_insn_class
> INSN_CLASS_ZKND_OR_ZKNE,
> INSN_CLASS_V,
> INSN_CLASS_ZVEF,
> + INSN_CLASS_ZVKB,
> INSN_CLASS_SVINVAL,
> INSN_CLASS_ZICBOM,
> INSN_CLASS_ZICBOP,
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index 0e1f3b4610a..6bb21ebb56f 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -397,6 +397,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
> print (info->stream, dis_style_immediate, "%d",
> (int)EXTRACT_RVV_OFFSET (l));
> break;
> + case 'l':
> + print (info->stream, dis_style_immediate, "%d",
> + (int)EXTRACT_RVV_VI_UIMM6 (l));
> + break;
> case 'm':
> if (!EXTRACT_OPERAND (VMASK, l))
> {
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 0e691544f9b..98ca3a4cc56 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -1815,6 +1815,22 @@ const struct riscv_opcode riscv_opcodes[] =
> {"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_opcode, 0},
> {"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_opcode, 0},
>
> +/* Zvkb instructions. */
> +{"vclmul.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VCLMULVV, MASK_VCLMULVV, match_opcode, 0},
> +{"vclmul.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VCLMULVX, MASK_VCLMULVX, match_opcode, 0},
> +{"vclmulh.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VCLMULHVV, MASK_VCLMULHVV, match_opcode, 0},
> +{"vclmulh.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VCLMULHVX, MASK_VCLMULHVX, match_opcode, 0},
> +{"vrol.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VROLVV, MASK_VROLVV, match_opcode, 0},
> +{"vrol.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VROLVX, MASK_VROLVX, match_opcode, 0},
> +{"vror.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VRORVV, MASK_VRORVV, match_opcode, 0},
> +{"vror.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VRORVX, MASK_VRORVX, match_opcode, 0},
> +{"vror.vi", 0, INSN_CLASS_ZVKB, "Vd,Vt,VlVm", MATCH_VRORVI, MASK_VRORVI, match_opcode, 0},
> +{"vbrev8.v", 0, INSN_CLASS_ZVKB, "Vd,VtVm", MATCH_VBREV8V, MASK_VBREV8V, match_opcode, 0},
> +{"vrev8.v", 0, INSN_CLASS_ZVKB, "Vd,VtVm", MATCH_VREV8V, MASK_VREV8V, match_opcode, 0},
> +{"vandn.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDNVV, MASK_VANDNVV, match_opcode, 0},
> +{"vandn.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDNVX, MASK_VANDNVX, match_opcode, 0},
> +{"vandn.vi", 0, INSN_CLASS_ZVKB, "Vd,Vt,ViVm", MATCH_VANDNVI, MASK_VANDNVI, match_opcode, 0},
> +
> /* Supervisor instructions. */
> {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
> {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
> --
> 2.38.1
>
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [RFC PATCH 1/6] RISC-V: Add Zvkb ISA extension support
2023-01-20 19:04 ` Philipp Tomsich
@ 2023-01-20 19:21 ` Christoph Müllner
0 siblings, 0 replies; 19+ messages in thread
From: Christoph Müllner @ 2023-01-20 19:21 UTC (permalink / raw)
To: Philipp Tomsich
Cc: binutils, Nelson Chu, Andrew Waterman, Palmer Dabbelt,
Jim Wilson, Aaron Durbin, Andrew de los Reyes, Eric Gouriou,
Barna Ibrahim
[-- Attachment #1: Type: text/plain, Size: 15689 bytes --]
On Fri, Jan 20, 2023 at 8:04 PM Philipp Tomsich <philipp.tomsich@vrull.eu>
wrote:
> On Wed, 21 Dec 2022 at 18:07, Christoph Muellner
> <christoph.muellner@vrull.eu> wrote:
> >
> > From: Christoph Müllner <christoph.muellner@vrull.eu>
> >
> > This commit adds the Zvkb ISA extension instructions, which are part
> > of the vector crypto extensions.
> >
> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > ---
> > bfd/elfxx-riscv.c | 5 ++++
> > gas/config/tc-riscv.c | 13 ++++++++++
> > gas/testsuite/gas/riscv/zvkb.d | 36 ++++++++++++++++++++++++++++
> > gas/testsuite/gas/riscv/zvkb.s | 28 ++++++++++++++++++++++
> > include/opcode/riscv-opc.h | 44 ++++++++++++++++++++++++++++++++++
> > include/opcode/riscv.h | 5 ++++
> > opcodes/riscv-dis.c | 4 ++++
> > opcodes/riscv-opc.c | 16 +++++++++++++
> > 8 files changed, 151 insertions(+)
> > create mode 100644 gas/testsuite/gas/riscv/zvkb.d
> > create mode 100644 gas/testsuite/gas/riscv/zvkb.s
> >
> > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> > index 0bcf2fdcfa3..22a6954ff41 100644
> > --- a/bfd/elfxx-riscv.c
> > +++ b/bfd/elfxx-riscv.c
> > @@ -1205,6 +1205,7 @@ static struct riscv_supported_ext
> riscv_supported_std_z_ext[] =
> > {"zve64x", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > {"zve64f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > + {"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > @@ -2415,6 +2416,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t
> *rps,
> > || riscv_subset_supports (rps, "zve64d")
> > || riscv_subset_supports (rps, "zve64f")
> > || riscv_subset_supports (rps, "zve32f"));
> > + case INSN_CLASS_ZVKB:
> > + return riscv_subset_supports (rps, "zvkb");
> > case INSN_CLASS_SVINVAL:
> > return riscv_subset_supports (rps, "svinval");
> > case INSN_CLASS_H:
> > @@ -2573,6 +2576,8 @@ riscv_multi_subset_supports_ext
> (riscv_parse_subset_t *rps,
> > return _("v' or `zve64x' or `zve32x");
> > case INSN_CLASS_ZVEF:
> > return _("v' or `zve64d' or `zve64f' or `zve32f");
> > + case INSN_CLASS_ZVKB:
> > + return _("zvkb");
> > case INSN_CLASS_SVINVAL:
> > return "svinval";
> > case INSN_CLASS_H:
> > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> > index 77c0d2e32ab..51d302127c5 100644
> > --- a/gas/config/tc-riscv.c
> > +++ b/gas/config/tc-riscv.c
> > @@ -1322,6 +1322,7 @@ validate_riscv_insn (const struct riscv_opcode
> *opc, int length)
> > case 'i':
> > case 'j':
> > case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break;
> > + case 'l': used_bits |= ENCODE_RVV_VI_UIMM6(-1U); break;
> > case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break;
> > case 'M': break; /* Macro operand, must be a mask register.
> */
> > case 'T': break; /* Macro operand, must be a vector
> register. */
> > @@ -2981,6 +2982,18 @@ riscv_ip (char *str, struct riscv_cl_insn *ip,
> expressionS *imm_expr,
> > asarg = expr_end;
> > continue;
> >
> > + case 'l': /* 6-bit vector arith unsigned immediate */
> > + my_getExpression (imm_expr, asarg);
> > + check_absolute_expr (ip, imm_expr, FALSE);
> > + if (imm_expr->X_add_number < 0
> > + || imm_expr->X_add_number >= 64)
> > + as_bad (_("bad value for vector immediate field, "
> > + "value must be 0...63"));
> > + ip->insn_opcode |= ENCODE_RVV_VI_UIMM6
> (imm_expr->X_add_number);
> > + imm_expr->X_op = O_absent;
> > + asarg = expr_end;
>
> This has to be adjusted (after 6eb099ae9324), as expr_end has been
> renamed to expr_parse_end.
> Note that the old version will still compile (although with a
> warning), as expr_end is now a function exported from expr.c.
>
> Please roll this change/adjustment into the next version of the series.
>
Thanks for the heads up!
A rebased patchset with all mentioned issues addressed and all tests passing
can be found here (branch might get force-pushed at any time):
https://github.com/cmuellner/binutils-gdb/tree/riscv-zvk-with-fixes
BR
Christoph
>
> Thanks,
> Philipp.
>
> > + continue;
> > +
> > case 'm': /* optional vector mask */
> > if (*asarg == '\0')
> > {
> > diff --git a/gas/testsuite/gas/riscv/zvkb.d
> b/gas/testsuite/gas/riscv/zvkb.d
> > new file mode 100644
> > index 00000000000..63aacba951c
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/zvkb.d
> > @@ -0,0 +1,36 @@
> > +#as: -march=rv64gc_zvkb
> > +#objdump: -dr
> > +
> > +.*:[ ]+file format .*
> > +
> > +
> > +Disassembly of section .text:
> > +0+000 <.text>:
> > +[ ]+[0-9a-f]+:[ ]+32862257[ ]+vclmul.vv[ ]+v4,v8,v12
> > +[ ]+[0-9a-f]+:[ ]+30862257[ ]+vclmul.vv[ ]+v4,v8,v12,v0.t
> > +[ ]+[0-9a-f]+:[ ]+3285e257[ ]+vclmul.vx[ ]+v4,v8,a1
> > +[ ]+[0-9a-f]+:[ ]+3085e257[ ]+vclmul.vx[ ]+v4,v8,a1,v0.t
> > +[ ]+[0-9a-f]+:[ ]+36862257[ ]+vclmulh.vv[ ]+v4,v8,v12
> > +[ ]+[0-9a-f]+:[ ]+34862257[ ]+vclmulh.vv[ ]+v4,v8,v12,v0.t
> > +[ ]+[0-9a-f]+:[ ]+3685e257[ ]+vclmulh.vx[ ]+v4,v8,a1
> > +[ ]+[0-9a-f]+:[ ]+3485e257[ ]+vclmulh.vx[ ]+v4,v8,a1,v0.t
> > +[ ]+[0-9a-f]+:[ ]+56860257[ ]+vrol.vv[ ]+v4,v8,v12
> > +[ ]+[0-9a-f]+:[ ]+54860257[ ]+vrol.vv[ ]+v4,v8,v12,v0.t
> > +[ ]+[0-9a-f]+:[ ]+5685c257[ ]+vrol.vx[ ]+v4,v8,a1
> > +[ ]+[0-9a-f]+:[ ]+5485c257[ ]+vrol.vx[ ]+v4,v8,a1,v0.t
> > +[ ]+[0-9a-f]+:[ ]+52860257[ ]+vror.vv[ ]+v4,v8,v12
> > +[ ]+[0-9a-f]+:[ ]+50860257[ ]+vror.vv[ ]+v4,v8,v12,v0.t
> > +[ ]+[0-9a-f]+:[ ]+5285c257[ ]+vror.vx[ ]+v4,v8,a1
> > +[ ]+[0-9a-f]+:[ ]+5085c257[ ]+vror.vx[ ]+v4,v8,a1,v0.t
> > +[ ]+[0-9a-f]+:[ ]+52803257[ ]+vror.vi[ ]+v4,v8,0
> > +[ ]+[0-9a-f]+:[ ]+548fb257[ ]+vror.vi[ ]+v4,v8,63,v0.t
> > +[ ]+[0-9a-f]+:[ ]+4a842257[ ]+vbrev8.v[ ]+v4,v8
> > +[ ]+[0-9a-f]+:[ ]+48842257[ ]+vbrev8.v[ ]+v4,v8,v0.t
> > +[ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8
> > +[ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t
> > +[ ]+[0-9a-f]+:[ ]+06860257[ ]+vandn.vv[ ]+v4,v8,v12
> > +[ ]+[0-9a-f]+:[ ]+04860257[ ]+vandn.vv[ ]+v4,v8,v12,v0.t
> > +[ ]+[0-9a-f]+:[ ]+0685c257[ ]+vandn.vx[ ]+v4,v8,a1
> > +[ ]+[0-9a-f]+:[ ]+0485c257[ ]+vandn.vx[ ]+v4,v8,a1,v0.t
> > +[ ]+[0-9a-f]+:[ ]+0687b257[ ]+vandn.vi[ ]+v4,v8,15
> > +[ ]+[0-9a-f]+:[ ]+04883257[ ]+vandn.vi[ ]+v4,v8,-16,v0.t
> > diff --git a/gas/testsuite/gas/riscv/zvkb.s
> b/gas/testsuite/gas/riscv/zvkb.s
> > new file mode 100644
> > index 00000000000..fd741505883
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/zvkb.s
> > @@ -0,0 +1,28 @@
> > + vclmul.vv v4, v8, v12
> > + vclmul.vv v4, v8, v12, v0.t
> > + vclmul.vx v4, v8, a1
> > + vclmul.vx v4, v8, a1, v0.t
> > + vclmulh.vv v4, v8, v12
> > + vclmulh.vv v4, v8, v12, v0.t
> > + vclmulh.vx v4, v8, a1
> > + vclmulh.vx v4, v8, a1, v0.t
> > + vrol.vv v4, v8, v12
> > + vrol.vv v4, v8, v12, v0.t
> > + vrol.vx v4, v8, a1
> > + vrol.vx v4, v8, a1, v0.t
> > + vror.vv v4, v8, v12
> > + vror.vv v4, v8, v12, v0.t
> > + vror.vx v4, v8, a1
> > + vror.vx v4, v8, a1, v0.t
> > + vror.vi v4, v8, 0
> > + vror.vi v4, v8, 63, v0.t
> > + vbrev8.v v4, v8
> > + vbrev8.v v4, v8, v0.t
> > + vrev8.v v4, v8
> > + vrev8.v v4, v8, v0.t
> > + vandn.vv v4, v8, v12
> > + vandn.vv v4, v8, v12, v0.t
> > + vandn.vx v4, v8, a1
> > + vandn.vx v4, v8, a1, v0.t
> > + vandn.vi v4, v8, 15
> > + vandn.vi v4, v8, -16, v0.t
> > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> > index 06e3df0f5a6..575fa5d322c 100644
> > --- a/include/opcode/riscv-opc.h
> > +++ b/include/opcode/riscv-opc.h
> > @@ -2055,6 +2055,35 @@
> > #define MASK_VDOTUVV 0xfc00707f
> > #define MATCH_VFDOTVV 0xe4001057
> > #define MASK_VFDOTVV 0xfc00707f
> > +/* Zvkb instructions. */
> > +#define MATCH_VCLMULVV 0x30002057
> > +#define MASK_VCLMULVV 0xfc00707f
> > +#define MATCH_VCLMULVX 0x30006057
> > +#define MASK_VCLMULVX 0xfc00707f
> > +#define MATCH_VCLMULHVV 0x34002057
> > +#define MASK_VCLMULHVV 0xfc00707f
> > +#define MATCH_VCLMULHVX 0x34006057
> > +#define MASK_VCLMULHVX 0xfc00707f
> > +#define MATCH_VROLVV 0x54000057
> > +#define MASK_VROLVV 0xfc00707f
> > +#define MATCH_VROLVX 0x54004057
> > +#define MASK_VROLVX 0xfc00707f
> > +#define MATCH_VRORVV 0x50000057
> > +#define MASK_VRORVV 0xfc00707f
> > +#define MATCH_VRORVX 0x50004057
> > +#define MASK_VRORVX 0xfc00707f
> > +#define MATCH_VRORVI 0x50003057
> > +#define MASK_VRORVI 0xf800707f
> > +#define MATCH_VBREV8V 0x48042057
> > +#define MASK_VBREV8V 0xfc0ff07f
> > +#define MATCH_VREV8V 0x4804a057
> > +#define MASK_VREV8V 0xfc0ff07f
> > +#define MATCH_VANDNVV 0x04000057
> > +#define MASK_VANDNVV 0xfc00707f
> > +#define MATCH_VANDNVX 0x04004057
> > +#define MASK_VANDNVX 0xfc00707f
> > +#define MATCH_VANDNVI 0x04003057
> > +#define MASK_VANDNVI 0xfc00707f
> > /* Svinval instruction. */
> > #define MATCH_SINVAL_VMA 0x16000073
> > #define MASK_SINVAL_VMA 0xfe007fff
> > @@ -3118,6 +3147,21 @@ DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO,
> MASK_CBO_ZERO);
> > /* Zawrs instructions. */
> > DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
> > DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
> > +/* Zvkb instructions. */
> > +DECLARE_INSN(vclmulvv, MATCH_VCLMULVV, MASK_VCLMULVV)
> > +DECLARE_INSN(vclmulvx, MATCH_VCLMULVX, MASK_VCLMULVX)
> > +DECLARE_INSN(vclmulhvv, MATCH_VCLMULHVV, MASK_VCLMULHVV)
> > +DECLARE_INSN(vclmulhvx, MATCH_VCLMULHVX, MASK_VCLMULHVX)
> > +DECLARE_INSN(vrolvv, MATCH_VROLVV, MASK_VROLVV)
> > +DECLARE_INSN(vrolvx, MATCH_VROLVX, MASK_VROLVX)
> > +DECLARE_INSN(vrorvv, MATCH_VRORVV, MASK_VRORVV)
> > +DECLARE_INSN(vrorvx, MATCH_VRORVX, MASK_VRORVX)
> > +DECLARE_INSN(vrorvi, MATCH_VRORVI, MASK_VRORVI)
> > +DECLARE_INSN(vbrev8v, MATCH_VBREV8V, MASK_VBREV8V)
> > +DECLARE_INSN(vrev8v, MATCH_VREV8V, MASK_VREV8V)
> > +DECLARE_INSN(vandnvv, MATCH_VANDNVV, MASK_VANDNVV)
> > +DECLARE_INSN(vandnvx, MATCH_VANDNVX, MASK_VANDNVX)
> > +DECLARE_INSN(vandnvi, MATCH_VANDNVI, MASK_VANDNVI)
> > /* Vendor-specific (T-Head) XTheadBa instructions. */
> > DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
> > /* Vendor-specific (T-Head) XTheadBb instructions. */
> > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> > index c3cbde600cb..1ba123e4933 100644
> > --- a/include/opcode/riscv.h
> > +++ b/include/opcode/riscv.h
> > @@ -100,6 +100,8 @@ static inline unsigned int riscv_insn_length (insn_t
> insn)
> > (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
> > #define EXTRACT_RVV_VI_UIMM(x) \
> > (RV_X(x, 15, 5))
> > +#define EXTRACT_RVV_VI_UIMM6(x) \
> > + (RV_X(x, 15, 5) | (RV_X(x, 26, 1) << 5))
> > #define EXTRACT_RVV_OFFSET(x) \
> > (RV_X(x, 29, 3))
> > #define EXTRACT_RVV_VB_IMM(x) \
> > @@ -151,6 +153,8 @@ static inline unsigned int riscv_insn_length (insn_t
> insn)
> > (RV_X(x, 0, 10) << 20)
> > #define ENCODE_RVV_VC_IMM(x) \
> > (RV_X(x, 0, 11) << 20)
> > +#define ENCODE_RVV_VI_UIMM6(x) \
> > + (RV_X(x, 0, 5) << 15 | RV_X(x, 5, 1) << 26)
> >
> > #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) ==
> (x))
> > #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) ==
> (x))
> > @@ -405,6 +409,7 @@ enum riscv_insn_class
> > INSN_CLASS_ZKND_OR_ZKNE,
> > INSN_CLASS_V,
> > INSN_CLASS_ZVEF,
> > + INSN_CLASS_ZVKB,
> > INSN_CLASS_SVINVAL,
> > INSN_CLASS_ZICBOM,
> > INSN_CLASS_ZICBOP,
> > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> > index 0e1f3b4610a..6bb21ebb56f 100644
> > --- a/opcodes/riscv-dis.c
> > +++ b/opcodes/riscv-dis.c
> > @@ -397,6 +397,10 @@ print_insn_args (const char *oparg, insn_t l,
> bfd_vma pc, disassemble_info *info
> > print (info->stream, dis_style_immediate, "%d",
> > (int)EXTRACT_RVV_OFFSET (l));
> > break;
> > + case 'l':
> > + print (info->stream, dis_style_immediate, "%d",
> > + (int)EXTRACT_RVV_VI_UIMM6 (l));
> > + break;
> > case 'm':
> > if (!EXTRACT_OPERAND (VMASK, l))
> > {
> > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> > index 0e691544f9b..98ca3a4cc56 100644
> > --- a/opcodes/riscv-opc.c
> > +++ b/opcodes/riscv-opc.c
> > @@ -1815,6 +1815,22 @@ const struct riscv_opcode riscv_opcodes[] =
> > {"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV,
> match_opcode, 0},
> > {"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV,
> match_opcode, 0},
> >
> > +/* Zvkb instructions. */
> > +{"vclmul.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VCLMULVV,
> MASK_VCLMULVV, match_opcode, 0},
> > +{"vclmul.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VCLMULVX,
> MASK_VCLMULVX, match_opcode, 0},
> > +{"vclmulh.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VCLMULHVV,
> MASK_VCLMULHVV, match_opcode, 0},
> > +{"vclmulh.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VCLMULHVX,
> MASK_VCLMULHVX, match_opcode, 0},
> > +{"vrol.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VROLVV,
> MASK_VROLVV, match_opcode, 0},
> > +{"vrol.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VROLVX,
> MASK_VROLVX, match_opcode, 0},
> > +{"vror.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VRORVV,
> MASK_VRORVV, match_opcode, 0},
> > +{"vror.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VRORVX,
> MASK_VRORVX, match_opcode, 0},
> > +{"vror.vi", 0, INSN_CLASS_ZVKB, "Vd,Vt,VlVm", MATCH_VRORVI,
> MASK_VRORVI, match_opcode, 0},
> > +{"vbrev8.v", 0, INSN_CLASS_ZVKB, "Vd,VtVm", MATCH_VBREV8V,
> MASK_VBREV8V, match_opcode, 0},
> > +{"vrev8.v", 0, INSN_CLASS_ZVKB, "Vd,VtVm", MATCH_VREV8V,
> MASK_VREV8V, match_opcode, 0},
> > +{"vandn.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDNVV,
> MASK_VANDNVV, match_opcode, 0},
> > +{"vandn.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDNVX,
> MASK_VANDNVX, match_opcode, 0},
> > +{"vandn.vi", 0, INSN_CLASS_ZVKB, "Vd,Vt,ViVm", MATCH_VANDNVI,
> MASK_VANDNVI, match_opcode, 0},
> > +
> > /* Supervisor instructions. */
> > {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS,
> MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
> > {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW,
> MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
> > --
> > 2.38.1
> >
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [RFC PATCH 2/6] RISC-V: Add Zvkg ISA extension support
2022-12-21 17:07 [RFC PATCH 0/6] RISC-V: Add support for vector crypto extensions Christoph Muellner
2022-12-21 17:07 ` [RFC PATCH 1/6] RISC-V: Add Zvkb ISA extension support Christoph Muellner
@ 2022-12-21 17:07 ` Christoph Muellner
2022-12-21 21:16 ` Jeff Law
2022-12-21 17:07 ` [RFC PATCH 3/6] RISC-V: Add Zvkh[a,b] " Christoph Muellner
` (4 subsequent siblings)
6 siblings, 1 reply; 19+ messages in thread
From: Christoph Muellner @ 2022-12-21 17:07 UTC (permalink / raw)
To: binutils, Nelson Chu, Andrew Waterman, Palmer Dabbelt,
Jim Wilson, Philipp Tomsich, Aaron Durbin, Andrew de los Reyes,
Eric Gouriou, Barna Ibrahim
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
This commit adds the Zvkg ISA extension instruction, which is part
of the vector crypto extensions.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 5 +++++
gas/testsuite/gas/riscv/zvkg.d | 9 +++++++++
gas/testsuite/gas/riscv/zvkg.s | 1 +
include/opcode/riscv-opc.h | 5 +++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 3 +++
6 files changed, 24 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvkg.d
create mode 100644 gas/testsuite/gas/riscv/zvkg.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 22a6954ff41..6dfae35ff0b 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1206,6 +1206,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zve64f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2418,6 +2419,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
|| riscv_subset_supports (rps, "zve32f"));
case INSN_CLASS_ZVKB:
return riscv_subset_supports (rps, "zvkb");
+ case INSN_CLASS_ZVKG:
+ return riscv_subset_supports (rps, "zvkg");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2578,6 +2581,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("v' or `zve64d' or `zve64f' or `zve32f");
case INSN_CLASS_ZVKB:
return _("zvkb");
+ case INSN_CLASS_ZVKG:
+ return _("zvkg");
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvkg.d b/gas/testsuite/gas/riscv/zvkg.d
new file mode 100644
index 00000000000..abca83ea3a8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkg.d
@@ -0,0 +1,9 @@
+#as: -march=rv64gc_zvkg
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+b2862277[ ]+vghmac.vv[ ]+v4,v8,v12
diff --git a/gas/testsuite/gas/riscv/zvkg.s b/gas/testsuite/gas/riscv/zvkg.s
new file mode 100644
index 00000000000..7c97108a396
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkg.s
@@ -0,0 +1 @@
+ vghmac.vv v4, v8, v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 575fa5d322c..4daffed4d84 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2084,6 +2084,9 @@
#define MASK_VANDNVX 0xfc00707f
#define MATCH_VANDNVI 0x04003057
#define MASK_VANDNVI 0xfc00707f
+/* Zvkg instructions. */
+#define MATCH_VGHMACVV 0xb2002077
+#define MASK_VGHMACVV 0xfe00707f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3162,6 +3165,8 @@ DECLARE_INSN(vrev8v, MATCH_VREV8V, MASK_VREV8V)
DECLARE_INSN(vandnvv, MATCH_VANDNVV, MASK_VANDNVV)
DECLARE_INSN(vandnvx, MATCH_VANDNVX, MASK_VANDNVX)
DECLARE_INSN(vandnvi, MATCH_VANDNVI, MASK_VANDNVI)
+/* Zvkg instructions. */
+DECLARE_INSN(vghmacvv, MATCH_VGHMACVV, MASK_VGHMACVV)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 1ba123e4933..060438a64d0 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -410,6 +410,7 @@ enum riscv_insn_class
INSN_CLASS_V,
INSN_CLASS_ZVEF,
INSN_CLASS_ZVKB,
+ INSN_CLASS_ZVKG,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 98ca3a4cc56..bb716c8c9d0 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1831,6 +1831,9 @@ const struct riscv_opcode riscv_opcodes[] =
{"vandn.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDNVX, MASK_VANDNVX, match_opcode, 0},
{"vandn.vi", 0, INSN_CLASS_ZVKB, "Vd,Vt,ViVm", MATCH_VANDNVI, MASK_VANDNVI, match_opcode, 0},
+/* Zvkg instructions. */
+{"vghmac.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHMACVV, MASK_VGHMACVV, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
--
2.38.1
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [RFC PATCH 2/6] RISC-V: Add Zvkg ISA extension support
2022-12-21 17:07 ` [RFC PATCH 2/6] RISC-V: Add Zvkg " Christoph Muellner
@ 2022-12-21 21:16 ` Jeff Law
0 siblings, 0 replies; 19+ messages in thread
From: Jeff Law @ 2022-12-21 21:16 UTC (permalink / raw)
To: Christoph Muellner, binutils, Nelson Chu, Andrew Waterman,
Palmer Dabbelt, Jim Wilson, Philipp Tomsich, Aaron Durbin,
Andrew de los Reyes, Eric Gouriou, Barna Ibrahim
On 12/21/22 10:07, Christoph Muellner wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This commit adds the Zvkg ISA extension instruction, which is part
> of the vector crypto extensions.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
> bfd/elfxx-riscv.c | 5 +++++
> gas/testsuite/gas/riscv/zvkg.d | 9 +++++++++
> gas/testsuite/gas/riscv/zvkg.s | 1 +
> include/opcode/riscv-opc.h | 5 +++++
> include/opcode/riscv.h | 1 +
> opcodes/riscv-opc.c | 3 +++
> 6 files changed, 24 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/zvkg.d
> create mode 100644 gas/testsuite/gas/riscv/zvkg.s
Looks sensible as well.
jeff
^ permalink raw reply [flat|nested] 19+ messages in thread
* [RFC PATCH 3/6] RISC-V: Add Zvkh[a,b] ISA extension support
2022-12-21 17:07 [RFC PATCH 0/6] RISC-V: Add support for vector crypto extensions Christoph Muellner
2022-12-21 17:07 ` [RFC PATCH 1/6] RISC-V: Add Zvkb ISA extension support Christoph Muellner
2022-12-21 17:07 ` [RFC PATCH 2/6] RISC-V: Add Zvkg " Christoph Muellner
@ 2022-12-21 17:07 ` Christoph Muellner
2022-12-21 21:24 ` Jeff Law
2023-01-03 22:00 ` Philipp Tomsich
2022-12-21 17:07 ` [RFC PATCH 4/6] RISC-V: Add Zvkn " Christoph Muellner
` (3 subsequent siblings)
6 siblings, 2 replies; 19+ messages in thread
From: Christoph Muellner @ 2022-12-21 17:07 UTC (permalink / raw)
To: binutils, Nelson Chu, Andrew Waterman, Palmer Dabbelt,
Jim Wilson, Philipp Tomsich, Aaron Durbin, Andrew de los Reyes,
Eric Gouriou, Barna Ibrahim
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
This commit adds the Zvkh[a,b] ISA extension instructions, which are part
of the vector crypto extensions.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 13 +++++++++++++
gas/testsuite/gas/riscv/zvkha.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zvkha_zvkhb.s | 3 +++
gas/testsuite/gas/riscv/zvkhb.d | 12 ++++++++++++
include/opcode/riscv-opc.h | 11 +++++++++++
include/opcode/riscv.h | 3 +++
opcodes/riscv-opc.c | 5 +++++
7 files changed, 59 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvkha.d
create mode 100644 gas/testsuite/gas/riscv/zvkha_zvkhb.s
create mode 100644 gas/testsuite/gas/riscv/zvkhb.d
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 6dfae35ff0b..fad49e4176a 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1207,6 +1207,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvkha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvkhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2421,6 +2423,13 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zvkb");
case INSN_CLASS_ZVKG:
return riscv_subset_supports (rps, "zvkg");
+ case INSN_CLASS_ZVKHA:
+ return riscv_subset_supports (rps, "zvkha");
+ case INSN_CLASS_ZVKHB:
+ return riscv_subset_supports (rps, "zvkhb");
+ case INSN_CLASS_ZVKHA_OR_ZVKHB:
+ return (riscv_subset_supports (rps, "zvkha")
+ || riscv_subset_supports (rps, "zvkhb"));
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2583,6 +2592,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zvkb");
case INSN_CLASS_ZVKG:
return _("zvkg");
+ case INSN_CLASS_ZVKHA:
+ return _("zvkha");
+ case INSN_CLASS_ZVKHB:
+ return _("zvkhb");
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvkha.d b/gas/testsuite/gas/riscv/zvkha.d
new file mode 100644
index 00000000000..61d6f4e77bb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkha.d
@@ -0,0 +1,12 @@
+#as: -march=rv64gc_zvkha
+#source: zvkha_zvkhb.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+be862277[ ]+vsha2cl.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+b6862277[ ]+vsha2ms.vv[ ]+v4,v8,v12
diff --git a/gas/testsuite/gas/riscv/zvkha_zvkhb.s b/gas/testsuite/gas/riscv/zvkha_zvkhb.s
new file mode 100644
index 00000000000..d20e6310531
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkha_zvkhb.s
@@ -0,0 +1,3 @@
+ vsha2ch.vv v4, v8, v12
+ vsha2cl.vv v4, v8, v12
+ vsha2ms.vv v4, v8, v12
diff --git a/gas/testsuite/gas/riscv/zvkhb.d b/gas/testsuite/gas/riscv/zvkhb.d
new file mode 100644
index 00000000000..61d0c1c4652
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkhb.d
@@ -0,0 +1,12 @@
+#as: -march=rv64gc_zvkhb
+#source: zvkha_zvkhb.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+be862277[ ]+vsha2cl.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+b6862277[ ]+vsha2ms.vv[ ]+v4,v8,v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 4daffed4d84..2d22f88acb7 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2087,6 +2087,13 @@
/* Zvkg instructions. */
#define MATCH_VGHMACVV 0xb2002077
#define MASK_VGHMACVV 0xfe00707f
+/* Zvkh[a,b] instructions. */
+#define MATCH_VSHA2CHVV 0xba002077
+#define MASK_VSHA2CHVV 0xfe00707f
+#define MATCH_VSHA2CLVV 0xbe002077
+#define MASK_VSHA2CLVV 0xfe00707f
+#define MATCH_VSHA2MSVV 0xb6002077
+#define MASK_VSHA2MSVV 0xfe00707f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3167,6 +3174,10 @@ DECLARE_INSN(vandnvx, MATCH_VANDNVX, MASK_VANDNVX)
DECLARE_INSN(vandnvi, MATCH_VANDNVI, MASK_VANDNVI)
/* Zvkg instructions. */
DECLARE_INSN(vghmacvv, MATCH_VGHMACVV, MASK_VGHMACVV)
+/* Zvkh[a,b] instructions. */
+DECLARE_INSN(vsha2chvv, MATCH_VSHA2CHVV, MASK_VSHA2CHVV)
+DECLARE_INSN(vsha2clvv, MATCH_VSHA2CLVV, MASK_VSHA2CLVV)
+DECLARE_INSN(vsha2msvv, MATCH_VSHA2MSVV, MASK_VSHA2MSVV)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 060438a64d0..be5650297a7 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -411,6 +411,9 @@ enum riscv_insn_class
INSN_CLASS_ZVEF,
INSN_CLASS_ZVKB,
INSN_CLASS_ZVKG,
+ INSN_CLASS_ZVKHA,
+ INSN_CLASS_ZVKHB,
+ INSN_CLASS_ZVKHA_OR_ZVKHB,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index bb716c8c9d0..35d3e653147 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1834,6 +1834,11 @@ const struct riscv_opcode riscv_opcodes[] =
/* Zvkg instructions. */
{"vghmac.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHMACVV, MASK_VGHMACVV, match_opcode, 0},
+/* Xvkh[a,b] instructions. */
+{"vsha2ch.vv", 0, INSN_CLASS_ZVKHA_OR_ZVKHB, "Vd,Vt,Vs", MATCH_VSHA2CHVV, MASK_VSHA2CHVV, match_opcode, 0},
+{"vsha2cl.vv", 0, INSN_CLASS_ZVKHA_OR_ZVKHB, "Vd,Vt,Vs", MATCH_VSHA2CLVV, MASK_VSHA2CLVV, match_opcode, 0},
+{"vsha2ms.vv", 0, INSN_CLASS_ZVKHA_OR_ZVKHB, "Vd,Vt,Vs", MATCH_VSHA2MSVV, MASK_VSHA2MSVV, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
--
2.38.1
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [RFC PATCH 3/6] RISC-V: Add Zvkh[a,b] ISA extension support
2022-12-21 17:07 ` [RFC PATCH 3/6] RISC-V: Add Zvkh[a,b] " Christoph Muellner
@ 2022-12-21 21:24 ` Jeff Law
2022-12-22 14:17 ` Christoph Müllner
2023-01-03 22:00 ` Philipp Tomsich
1 sibling, 1 reply; 19+ messages in thread
From: Jeff Law @ 2022-12-21 21:24 UTC (permalink / raw)
To: Christoph Muellner, binutils, Nelson Chu, Andrew Waterman,
Palmer Dabbelt, Jim Wilson, Philipp Tomsich, Aaron Durbin,
Andrew de los Reyes, Eric Gouriou, Barna Ibrahim
On 12/21/22 10:07, Christoph Muellner wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This commit adds the Zvkh[a,b] ISA extension instructions, which are part
> of the vector crypto extensions.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
> bfd/elfxx-riscv.c | 13 +++++++++++++
> gas/testsuite/gas/riscv/zvkha.d | 12 ++++++++++++
> gas/testsuite/gas/riscv/zvkha_zvkhb.s | 3 +++
> gas/testsuite/gas/riscv/zvkhb.d | 12 ++++++++++++
> include/opcode/riscv-opc.h | 11 +++++++++++
> include/opcode/riscv.h | 3 +++
> opcodes/riscv-opc.c | 5 +++++
> 7 files changed, 59 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/zvkha.d
> create mode 100644 gas/testsuite/gas/riscv/zvkha_zvkhb.s
> create mode 100644 gas/testsuite/gas/riscv/zvkhb.d
Looks reasonable to me. Just one comment nit below...
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index bb716c8c9d0..35d3e653147 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -1834,6 +1834,11 @@ const struct riscv_opcode riscv_opcodes[] =
> /* Zvkg instructions. */
> {"vghmac.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHMACVV, MASK_VGHMACVV, match_opcode, 0},
>
> +/* Xvkh[a,b] instructions. */
Are these X or Z?
Jeff
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [RFC PATCH 3/6] RISC-V: Add Zvkh[a,b] ISA extension support
2022-12-21 21:24 ` Jeff Law
@ 2022-12-22 14:17 ` Christoph Müllner
0 siblings, 0 replies; 19+ messages in thread
From: Christoph Müllner @ 2022-12-22 14:17 UTC (permalink / raw)
To: Jeff Law
Cc: binutils, Nelson Chu, Andrew Waterman, Palmer Dabbelt,
Jim Wilson, Philipp Tomsich, Aaron Durbin, Andrew de los Reyes,
Eric Gouriou, Barna Ibrahim
[-- Attachment #1: Type: text/plain, Size: 1591 bytes --]
On Wed, Dec 21, 2022 at 10:24 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
> On 12/21/22 10:07, Christoph Muellner wrote:
> > From: Christoph Müllner <christoph.muellner@vrull.eu>
> >
> > This commit adds the Zvkh[a,b] ISA extension instructions, which are part
> > of the vector crypto extensions.
> >
> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > ---
> > bfd/elfxx-riscv.c | 13 +++++++++++++
> > gas/testsuite/gas/riscv/zvkha.d | 12 ++++++++++++
> > gas/testsuite/gas/riscv/zvkha_zvkhb.s | 3 +++
> > gas/testsuite/gas/riscv/zvkhb.d | 12 ++++++++++++
> > include/opcode/riscv-opc.h | 11 +++++++++++
> > include/opcode/riscv.h | 3 +++
> > opcodes/riscv-opc.c | 5 +++++
> > 7 files changed, 59 insertions(+)
> > create mode 100644 gas/testsuite/gas/riscv/zvkha.d
> > create mode 100644 gas/testsuite/gas/riscv/zvkha_zvkhb.s
> > create mode 100644 gas/testsuite/gas/riscv/zvkhb.d
> Looks reasonable to me. Just one comment nit below...
>
>
>
> > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> > index bb716c8c9d0..35d3e653147 100644
> > --- a/opcodes/riscv-opc.c
> > +++ b/opcodes/riscv-opc.c
> > @@ -1834,6 +1834,11 @@ const struct riscv_opcode riscv_opcodes[] =
> > /* Zvkg instructions. */
> > {"vghmac.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHMACVV,
> MASK_VGHMACVV, match_opcode, 0},
> >
> > +/* Xvkh[a,b] instructions. */
> Are these X or Z?
>
Thanks for spotting this!
>
> Jeff
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [RFC PATCH 3/6] RISC-V: Add Zvkh[a,b] ISA extension support
2022-12-21 17:07 ` [RFC PATCH 3/6] RISC-V: Add Zvkh[a,b] " Christoph Muellner
2022-12-21 21:24 ` Jeff Law
@ 2023-01-03 22:00 ` Philipp Tomsich
1 sibling, 0 replies; 19+ messages in thread
From: Philipp Tomsich @ 2023-01-03 22:00 UTC (permalink / raw)
To: Christoph Muellner
Cc: binutils, Nelson Chu, Andrew Waterman, Palmer Dabbelt,
Jim Wilson, Aaron Durbin, Andrew de los Reyes, Eric Gouriou,
Barna Ibrahim
On Wed, 21 Dec 2022 at 18:07, Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This commit adds the Zvkh[a,b] ISA extension instructions, which are part
> of the vector crypto extensions.
This should be Zvknh[ab] (the 'n' has been missing throughout the
patch: i.e., filenames, march, INSN_CLASS_*, etc.), as that's what the
specification uses.
Watch this space for a v2 of the series.
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
> bfd/elfxx-riscv.c | 13 +++++++++++++
> gas/testsuite/gas/riscv/zvkha.d | 12 ++++++++++++
> gas/testsuite/gas/riscv/zvkha_zvkhb.s | 3 +++
> gas/testsuite/gas/riscv/zvkhb.d | 12 ++++++++++++
> include/opcode/riscv-opc.h | 11 +++++++++++
> include/opcode/riscv.h | 3 +++
> opcodes/riscv-opc.c | 5 +++++
> 7 files changed, 59 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/zvkha.d
> create mode 100644 gas/testsuite/gas/riscv/zvkha_zvkhb.s
> create mode 100644 gas/testsuite/gas/riscv/zvkhb.d
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 6dfae35ff0b..fad49e4176a 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1207,6 +1207,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
> {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zvkha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zvkhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> @@ -2421,6 +2423,13 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
> return riscv_subset_supports (rps, "zvkb");
> case INSN_CLASS_ZVKG:
> return riscv_subset_supports (rps, "zvkg");
> + case INSN_CLASS_ZVKHA:
> + return riscv_subset_supports (rps, "zvkha");
> + case INSN_CLASS_ZVKHB:
> + return riscv_subset_supports (rps, "zvkhb");
> + case INSN_CLASS_ZVKHA_OR_ZVKHB:
> + return (riscv_subset_supports (rps, "zvkha")
> + || riscv_subset_supports (rps, "zvkhb"));
> case INSN_CLASS_SVINVAL:
> return riscv_subset_supports (rps, "svinval");
> case INSN_CLASS_H:
> @@ -2583,6 +2592,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
> return _("zvkb");
> case INSN_CLASS_ZVKG:
> return _("zvkg");
> + case INSN_CLASS_ZVKHA:
> + return _("zvkha");
> + case INSN_CLASS_ZVKHB:
> + return _("zvkhb");
> case INSN_CLASS_SVINVAL:
> return "svinval";
> case INSN_CLASS_H:
> diff --git a/gas/testsuite/gas/riscv/zvkha.d b/gas/testsuite/gas/riscv/zvkha.d
> new file mode 100644
> index 00000000000..61d6f4e77bb
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zvkha.d
> @@ -0,0 +1,12 @@
> +#as: -march=rv64gc_zvkha
> +#source: zvkha_zvkhb.s
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +0+000 <.text>:
> +[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12
> +[ ]+[0-9a-f]+:[ ]+be862277[ ]+vsha2cl.vv[ ]+v4,v8,v12
> +[ ]+[0-9a-f]+:[ ]+b6862277[ ]+vsha2ms.vv[ ]+v4,v8,v12
> diff --git a/gas/testsuite/gas/riscv/zvkha_zvkhb.s b/gas/testsuite/gas/riscv/zvkha_zvkhb.s
> new file mode 100644
> index 00000000000..d20e6310531
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zvkha_zvkhb.s
> @@ -0,0 +1,3 @@
> + vsha2ch.vv v4, v8, v12
> + vsha2cl.vv v4, v8, v12
> + vsha2ms.vv v4, v8, v12
> diff --git a/gas/testsuite/gas/riscv/zvkhb.d b/gas/testsuite/gas/riscv/zvkhb.d
> new file mode 100644
> index 00000000000..61d0c1c4652
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zvkhb.d
> @@ -0,0 +1,12 @@
> +#as: -march=rv64gc_zvkhb
> +#source: zvkha_zvkhb.s
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +0+000 <.text>:
> +[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12
> +[ ]+[0-9a-f]+:[ ]+be862277[ ]+vsha2cl.vv[ ]+v4,v8,v12
> +[ ]+[0-9a-f]+:[ ]+b6862277[ ]+vsha2ms.vv[ ]+v4,v8,v12
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 4daffed4d84..2d22f88acb7 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2087,6 +2087,13 @@
> /* Zvkg instructions. */
> #define MATCH_VGHMACVV 0xb2002077
> #define MASK_VGHMACVV 0xfe00707f
> +/* Zvkh[a,b] instructions. */
> +#define MATCH_VSHA2CHVV 0xba002077
> +#define MASK_VSHA2CHVV 0xfe00707f
> +#define MATCH_VSHA2CLVV 0xbe002077
> +#define MASK_VSHA2CLVV 0xfe00707f
> +#define MATCH_VSHA2MSVV 0xb6002077
> +#define MASK_VSHA2MSVV 0xfe00707f
> /* Svinval instruction. */
> #define MATCH_SINVAL_VMA 0x16000073
> #define MASK_SINVAL_VMA 0xfe007fff
> @@ -3167,6 +3174,10 @@ DECLARE_INSN(vandnvx, MATCH_VANDNVX, MASK_VANDNVX)
> DECLARE_INSN(vandnvi, MATCH_VANDNVI, MASK_VANDNVI)
> /* Zvkg instructions. */
> DECLARE_INSN(vghmacvv, MATCH_VGHMACVV, MASK_VGHMACVV)
> +/* Zvkh[a,b] instructions. */
> +DECLARE_INSN(vsha2chvv, MATCH_VSHA2CHVV, MASK_VSHA2CHVV)
> +DECLARE_INSN(vsha2clvv, MATCH_VSHA2CLVV, MASK_VSHA2CLVV)
> +DECLARE_INSN(vsha2msvv, MATCH_VSHA2MSVV, MASK_VSHA2MSVV)
> /* Vendor-specific (T-Head) XTheadBa instructions. */
> DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
> /* Vendor-specific (T-Head) XTheadBb instructions. */
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 060438a64d0..be5650297a7 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -411,6 +411,9 @@ enum riscv_insn_class
> INSN_CLASS_ZVEF,
> INSN_CLASS_ZVKB,
> INSN_CLASS_ZVKG,
> + INSN_CLASS_ZVKHA,
> + INSN_CLASS_ZVKHB,
> + INSN_CLASS_ZVKHA_OR_ZVKHB,
> INSN_CLASS_SVINVAL,
> INSN_CLASS_ZICBOM,
> INSN_CLASS_ZICBOP,
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index bb716c8c9d0..35d3e653147 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -1834,6 +1834,11 @@ const struct riscv_opcode riscv_opcodes[] =
> /* Zvkg instructions. */
> {"vghmac.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHMACVV, MASK_VGHMACVV, match_opcode, 0},
>
> +/* Xvkh[a,b] instructions. */
> +{"vsha2ch.vv", 0, INSN_CLASS_ZVKHA_OR_ZVKHB, "Vd,Vt,Vs", MATCH_VSHA2CHVV, MASK_VSHA2CHVV, match_opcode, 0},
> +{"vsha2cl.vv", 0, INSN_CLASS_ZVKHA_OR_ZVKHB, "Vd,Vt,Vs", MATCH_VSHA2CLVV, MASK_VSHA2CLVV, match_opcode, 0},
> +{"vsha2ms.vv", 0, INSN_CLASS_ZVKHA_OR_ZVKHB, "Vd,Vt,Vs", MATCH_VSHA2MSVV, MASK_VSHA2MSVV, match_opcode, 0},
> +
> /* Supervisor instructions. */
> {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
> {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
> --
> 2.38.1
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [RFC PATCH 4/6] RISC-V: Add Zvkn ISA extension support
2022-12-21 17:07 [RFC PATCH 0/6] RISC-V: Add support for vector crypto extensions Christoph Muellner
` (2 preceding siblings ...)
2022-12-21 17:07 ` [RFC PATCH 3/6] RISC-V: Add Zvkh[a,b] " Christoph Muellner
@ 2022-12-21 17:07 ` Christoph Muellner
2022-12-21 21:26 ` Jeff Law
2022-12-21 17:07 ` [RFC PATCH 5/6] RISC-V: Add Zvksed " Christoph Muellner
` (2 subsequent siblings)
6 siblings, 1 reply; 19+ messages in thread
From: Christoph Muellner @ 2022-12-21 17:07 UTC (permalink / raw)
To: binutils, Nelson Chu, Andrew Waterman, Palmer Dabbelt,
Jim Wilson, Philipp Tomsich, Aaron Durbin, Andrew de los Reyes,
Eric Gouriou, Barna Ibrahim
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
This commit adds the Zvkn ISA extension instructions, which are
part of the vector crypto extensions.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 5 +++++
gas/testsuite/gas/riscv/zvkn.d | 21 ++++++++++++++++++++
gas/testsuite/gas/riscv/zvkn.s | 13 +++++++++++++
include/opcode/riscv-opc.h | 35 ++++++++++++++++++++++++++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 13 +++++++++++++
6 files changed, 88 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvkn.d
create mode 100644 gas/testsuite/gas/riscv/zvkn.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index fad49e4176a..b672e610a54 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1209,6 +1209,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2430,6 +2431,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
case INSN_CLASS_ZVKHA_OR_ZVKHB:
return (riscv_subset_supports (rps, "zvkha")
|| riscv_subset_supports (rps, "zvkhb"));
+ case INSN_CLASS_ZVKN:
+ return riscv_subset_supports (rps, "zvkn");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2596,6 +2599,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zvkha");
case INSN_CLASS_ZVKHB:
return _("zvkhb");
+ case INSN_CLASS_ZVKN:
+ return _("zvkn");
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvkn.d b/gas/testsuite/gas/riscv/zvkn.d
new file mode 100644
index 00000000000..5d477721442
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkn.d
@@ -0,0 +1,21 @@
+#as: -march=rv64gc_zvkn
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+a280a277[ ]+vaesdf.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a680a277[ ]+vaesdf.vs[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a2802277[ ]+vaesdm.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a6802277[ ]+vaesdm.vs[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a281a277[ ]+vaesef.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a681a277[ ]+vaesef.vs[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a2812277[ ]+vaesem.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a6812277[ ]+vaesem.vs[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8a812277[ ]+vaeskf1.vi[ ]+v4,v8,2
+[ ]+[0-9a-f]+:[ ]+8a872277[ ]+vaeskf1.vi[ ]+v4,v8,14
+[ ]+[0-9a-f]+:[ ]+aa812277[ ]+vaeskf2.vi[ ]+v4,v8,2
+[ ]+[0-9a-f]+:[ ]+aa872277[ ]+vaeskf2.vi[ ]+v4,v8,14
+[ ]+[0-9a-f]+:[ ]+a683a277[ ]+vaesz.vs[ ]+v4,v8
diff --git a/gas/testsuite/gas/riscv/zvkn.s b/gas/testsuite/gas/riscv/zvkn.s
new file mode 100644
index 00000000000..f0f3811eaec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkn.s
@@ -0,0 +1,13 @@
+ vaesdf.vv v4, v8
+ vaesdf.vs v4, v8
+ vaesdm.vv v4, v8
+ vaesdm.vs v4, v8
+ vaesef.vv v4, v8
+ vaesef.vs v4, v8
+ vaesem.vv v4, v8
+ vaesem.vs v4, v8
+ vaeskf1.vi v4, v8, 2
+ vaeskf1.vi v4, v8, 14
+ vaeskf2.vi v4, v8, 2
+ vaeskf2.vi v4, v8, 14
+ vaesz.vs v4, v8
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 2d22f88acb7..86b04ce16a0 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2094,6 +2094,29 @@
#define MASK_VSHA2CLVV 0xfe00707f
#define MATCH_VSHA2MSVV 0xb6002077
#define MASK_VSHA2MSVV 0xfe00707f
+/* Zvkn instructions. */
+#define MATCH_VAESDFVV 0xa200a077
+#define MASK_VAESDFVV 0xfe0ff07f
+#define MATCH_VAESDFVS 0xa600a077
+#define MASK_VAESDFVS 0xfe0ff07f
+#define MATCH_VAESDMVV 0xa2002077
+#define MASK_VAESDMVV 0xfe0ff07f
+#define MATCH_VAESDMVS 0xa6002077
+#define MASK_VAESDMVS 0xfe0ff07f
+#define MATCH_VAESEFVV 0xa201a077
+#define MASK_VAESEFVV 0xfe0ff07f
+#define MATCH_VAESEFVS 0xa601a077
+#define MASK_VAESEFVS 0xfe0ff07f
+#define MATCH_VAESEMVV 0xa2012077
+#define MASK_VAESEMVV 0xfe0ff07f
+#define MATCH_VAESEMVS 0xa6012077
+#define MASK_VAESEMVS 0xfe0ff07f
+#define MATCH_VAESKF1VI 0x8a002077
+#define MASK_VAESKF1VI 0xfe00707f
+#define MATCH_VAESKF2VI 0xaa002077
+#define MASK_VAESKF2VI 0xfe00707f
+#define MATCH_VAESZVS 0xa603a077
+#define MASK_VAESZVS 0xfe0ff07f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3178,6 +3201,18 @@ DECLARE_INSN(vghmacvv, MATCH_VGHMACVV, MASK_VGHMACVV)
DECLARE_INSN(vsha2chvv, MATCH_VSHA2CHVV, MASK_VSHA2CHVV)
DECLARE_INSN(vsha2clvv, MATCH_VSHA2CLVV, MASK_VSHA2CLVV)
DECLARE_INSN(vsha2msvv, MATCH_VSHA2MSVV, MASK_VSHA2MSVV)
+/* Zvkn instructions. */
+DECLARE_INSN(vaesdfvv, MATCH_VAESDFVV, MASK_VAESDFVV)
+DECLARE_INSN(vaesdfvs, MATCH_VAESDFVS, MASK_VAESDFVS)
+DECLARE_INSN(vaesdmvv, MATCH_VAESDMVV, MASK_VAESDMVV)
+DECLARE_INSN(vaesdmvs, MATCH_VAESDMVS, MASK_VAESDMVS)
+DECLARE_INSN(vaesefvv, MATCH_VAESEFVV, MASK_VAESEFVV)
+DECLARE_INSN(vaesefvs, MATCH_VAESEFVS, MASK_VAESEFVS)
+DECLARE_INSN(vaesemvv, MATCH_VAESEMVV, MASK_VAESEMVV)
+DECLARE_INSN(vaesemvs, MATCH_VAESEMVS, MASK_VAESEMVS)
+DECLARE_INSN(vaeskf1vi, MATCH_VAESKF1VI, MASK_VAESKF1VI)
+DECLARE_INSN(vaeskf2vi, MATCH_VAESKF2VI, MASK_VAESKF2VI)
+DECLARE_INSN(vaeszvs, MATCH_VAESZVS, MASK_VAESZVS)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index be5650297a7..f36fc1be2ed 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -414,6 +414,7 @@ enum riscv_insn_class
INSN_CLASS_ZVKHA,
INSN_CLASS_ZVKHB,
INSN_CLASS_ZVKHA_OR_ZVKHB,
+ INSN_CLASS_ZVKN,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 35d3e653147..79c123927b7 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1839,6 +1839,19 @@ const struct riscv_opcode riscv_opcodes[] =
{"vsha2cl.vv", 0, INSN_CLASS_ZVKHA_OR_ZVKHB, "Vd,Vt,Vs", MATCH_VSHA2CLVV, MASK_VSHA2CLVV, match_opcode, 0},
{"vsha2ms.vv", 0, INSN_CLASS_ZVKHA_OR_ZVKHB, "Vd,Vt,Vs", MATCH_VSHA2MSVV, MASK_VSHA2MSVV, match_opcode, 0},
+/* Zvkn instructions. */
+{"vaesdf.vv", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESDFVV, MASK_VAESDFVV, match_opcode, 0},
+{"vaesdf.vs", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESDFVS, MASK_VAESDFVV, match_opcode, 0},
+{"vaesdm.vv", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESDMVV, MASK_VAESDMVV, match_opcode, 0},
+{"vaesdm.vs", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESDMVS, MASK_VAESDMVV, match_opcode, 0},
+{"vaesef.vv", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESEFVV, MASK_VAESEFVV, match_opcode, 0},
+{"vaesef.vs", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESEFVS, MASK_VAESEFVV, match_opcode, 0},
+{"vaesem.vv", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESEMVV, MASK_VAESEMVV, match_opcode, 0},
+{"vaesem.vs", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESEMVS, MASK_VAESEMVV, match_opcode, 0},
+{"vaeskf1.vi", 0, INSN_CLASS_ZVKN, "Vd,Vt,Vj", MATCH_VAESKF1VI, MASK_VAESKF1VI, match_opcode, 0},
+{"vaeskf2.vi", 0, INSN_CLASS_ZVKN, "Vd,Vt,Vj", MATCH_VAESKF2VI, MASK_VAESKF2VI, match_opcode, 0},
+{"vaesz.vs", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESZVS, MASK_VAESZVS, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
--
2.38.1
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [RFC PATCH 4/6] RISC-V: Add Zvkn ISA extension support
2022-12-21 17:07 ` [RFC PATCH 4/6] RISC-V: Add Zvkn " Christoph Muellner
@ 2022-12-21 21:26 ` Jeff Law
0 siblings, 0 replies; 19+ messages in thread
From: Jeff Law @ 2022-12-21 21:26 UTC (permalink / raw)
To: Christoph Muellner, binutils, Nelson Chu, Andrew Waterman,
Palmer Dabbelt, Jim Wilson, Philipp Tomsich, Aaron Durbin,
Andrew de los Reyes, Eric Gouriou, Barna Ibrahim
On 12/21/22 10:07, Christoph Muellner wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This commit adds the Zvkn ISA extension instructions, which are
> part of the vector crypto extensions.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
> bfd/elfxx-riscv.c | 5 +++++
> gas/testsuite/gas/riscv/zvkn.d | 21 ++++++++++++++++++++
> gas/testsuite/gas/riscv/zvkn.s | 13 +++++++++++++
> include/opcode/riscv-opc.h | 35 ++++++++++++++++++++++++++++++++++
> include/opcode/riscv.h | 1 +
> opcodes/riscv-opc.c | 13 +++++++++++++
> 6 files changed, 88 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/zvkn.d
> create mode 100644 gas/testsuite/gas/riscv/zvkn.s
Looks sensible as well.
jeff
^ permalink raw reply [flat|nested] 19+ messages in thread
* [RFC PATCH 5/6] RISC-V: Add Zvksed ISA extension support
2022-12-21 17:07 [RFC PATCH 0/6] RISC-V: Add support for vector crypto extensions Christoph Muellner
` (3 preceding siblings ...)
2022-12-21 17:07 ` [RFC PATCH 4/6] RISC-V: Add Zvkn " Christoph Muellner
@ 2022-12-21 17:07 ` Christoph Muellner
2022-12-21 21:30 ` Jeff Law
2022-12-21 17:07 ` [RFC PATCH 6/6] RISC-V: Add Zvksh " Christoph Muellner
2022-12-22 2:46 ` [RFC PATCH 0/6] RISC-V: Add support for vector crypto extensions Kito Cheng
6 siblings, 1 reply; 19+ messages in thread
From: Christoph Muellner @ 2022-12-21 17:07 UTC (permalink / raw)
To: binutils, Nelson Chu, Andrew Waterman, Palmer Dabbelt,
Jim Wilson, Philipp Tomsich, Aaron Durbin, Andrew de los Reyes,
Eric Gouriou, Barna Ibrahim
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
This commit adds the Zvksed ISA extension instructions, which are
part of the vector crypto extensions.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 5 +++++
gas/testsuite/gas/riscv/zvksed.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zvksed.s | 4 ++++
include/opcode/riscv-opc.h | 11 +++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 5 +++++
6 files changed, 38 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvksed.d
create mode 100644 gas/testsuite/gas/riscv/zvksed.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index b672e610a54..c7956a22abb 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1210,6 +1210,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvkha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2433,6 +2434,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
|| riscv_subset_supports (rps, "zvkhb"));
case INSN_CLASS_ZVKN:
return riscv_subset_supports (rps, "zvkn");
+ case INSN_CLASS_ZVKSED:
+ return riscv_subset_supports (rps, "zvksed");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2601,6 +2604,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zvkhb");
case INSN_CLASS_ZVKN:
return _("zvkn");
+ case INSN_CLASS_ZVKSED:
+ return _("zvksed");
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvksed.d b/gas/testsuite/gas/riscv/zvksed.d
new file mode 100644
index 00000000000..48b4aafdbb1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksed.d
@@ -0,0 +1,12 @@
+#as: -march=rv64gc_zvksed
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+86802277[ ]+vsm4k.vi[ ]+v4,v8,0
+[ ]+[0-9a-f]+:[ ]+8683a277[ ]+vsm4k.vi[ ]+v4,v8,7
+[ ]+[0-9a-f]+:[ ]+a2882277[ ]+vsm4r.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a6882277[ ]+vsm4r.vs[ ]+v4,v8
diff --git a/gas/testsuite/gas/riscv/zvksed.s b/gas/testsuite/gas/riscv/zvksed.s
new file mode 100644
index 00000000000..754b4646adf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksed.s
@@ -0,0 +1,4 @@
+ vsm4k.vi v4, v8, 0
+ vsm4k.vi v4, v8, 7
+ vsm4r.vv v4, v8
+ vsm4r.vs v4, v8
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 86b04ce16a0..b44d2190250 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2117,6 +2117,13 @@
#define MASK_VAESKF2VI 0xfe00707f
#define MATCH_VAESZVS 0xa603a077
#define MASK_VAESZVS 0xfe0ff07f
+/* Zvksed instructions. */
+#define MATCH_VSM4KVI 0x86002077
+#define MASK_VSM4KVI 0xfe00707f
+#define MATCH_VSM4RVV 0xa2082077
+#define MASK_VSM4RVV 0xfe0ff07f
+#define MATCH_VSM4RVS 0xa6082077
+#define MASK_VSM4RVS 0xfe0ff07f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3213,6 +3220,10 @@ DECLARE_INSN(vaesemvs, MATCH_VAESEMVS, MASK_VAESEMVS)
DECLARE_INSN(vaeskf1vi, MATCH_VAESKF1VI, MASK_VAESKF1VI)
DECLARE_INSN(vaeskf2vi, MATCH_VAESKF2VI, MASK_VAESKF2VI)
DECLARE_INSN(vaeszvs, MATCH_VAESZVS, MASK_VAESZVS)
+/* Zvksed instructions. */
+DECLARE_INSN(vsm4kvi, MATCH_VSM4KVI, MASK_VSM4KVI)
+DECLARE_INSN(vsm4rvv, MATCH_VSM4RVV, MASK_VSM4RVV)
+DECLARE_INSN(vsm4rvs, MATCH_VSM4RVS, MASK_VSM4RVS)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index f36fc1be2ed..d6465c2a2a4 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -415,6 +415,7 @@ enum riscv_insn_class
INSN_CLASS_ZVKHB,
INSN_CLASS_ZVKHA_OR_ZVKHB,
INSN_CLASS_ZVKN,
+ INSN_CLASS_ZVKSED,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 79c123927b7..69e833f666c 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1852,6 +1852,11 @@ const struct riscv_opcode riscv_opcodes[] =
{"vaeskf2.vi", 0, INSN_CLASS_ZVKN, "Vd,Vt,Vj", MATCH_VAESKF2VI, MASK_VAESKF2VI, match_opcode, 0},
{"vaesz.vs", 0, INSN_CLASS_ZVKN, "Vd,Vt", MATCH_VAESZVS, MASK_VAESZVS, match_opcode, 0},
+/* Zvksed instructions. */
+{"vsm4k.vi", 0, INSN_CLASS_ZVKSED, "Vd,Vt,Vj", MATCH_VSM4KVI, MASK_VSM4KVI, match_opcode, 0},
+{"vsm4r.vv", 0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4RVV, MASK_VSM4RVV, match_opcode, 0},
+{"vsm4r.vs", 0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4RVS, MASK_VSM4RVS, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
--
2.38.1
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [RFC PATCH 5/6] RISC-V: Add Zvksed ISA extension support
2022-12-21 17:07 ` [RFC PATCH 5/6] RISC-V: Add Zvksed " Christoph Muellner
@ 2022-12-21 21:30 ` Jeff Law
0 siblings, 0 replies; 19+ messages in thread
From: Jeff Law @ 2022-12-21 21:30 UTC (permalink / raw)
To: Christoph Muellner, binutils, Nelson Chu, Andrew Waterman,
Palmer Dabbelt, Jim Wilson, Philipp Tomsich, Aaron Durbin,
Andrew de los Reyes, Eric Gouriou, Barna Ibrahim
On 12/21/22 10:07, Christoph Muellner wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This commit adds the Zvksed ISA extension instructions, which are
> part of the vector crypto extensions.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
> bfd/elfxx-riscv.c | 5 +++++
> gas/testsuite/gas/riscv/zvksed.d | 12 ++++++++++++
> gas/testsuite/gas/riscv/zvksed.s | 4 ++++
> include/opcode/riscv-opc.h | 11 +++++++++++
> include/opcode/riscv.h | 1 +
> opcodes/riscv-opc.c | 5 +++++
> 6 files changed, 38 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/zvksed.d
> create mode 100644 gas/testsuite/gas/riscv/zvksed.s
Looks sensible to me.
jeff
^ permalink raw reply [flat|nested] 19+ messages in thread
* [RFC PATCH 6/6] RISC-V: Add Zvksh ISA extension support
2022-12-21 17:07 [RFC PATCH 0/6] RISC-V: Add support for vector crypto extensions Christoph Muellner
` (4 preceding siblings ...)
2022-12-21 17:07 ` [RFC PATCH 5/6] RISC-V: Add Zvksed " Christoph Muellner
@ 2022-12-21 17:07 ` Christoph Muellner
2022-12-21 21:33 ` Jeff Law
2022-12-22 2:46 ` [RFC PATCH 0/6] RISC-V: Add support for vector crypto extensions Kito Cheng
6 siblings, 1 reply; 19+ messages in thread
From: Christoph Muellner @ 2022-12-21 17:07 UTC (permalink / raw)
To: binutils, Nelson Chu, Andrew Waterman, Palmer Dabbelt,
Jim Wilson, Philipp Tomsich, Aaron Durbin, Andrew de los Reyes,
Eric Gouriou, Barna Ibrahim
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
This commit adds the Zvksh ISA extension instructions, which are
part of the vector crypto extensions.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 5 +++++
gas/testsuite/gas/riscv/zvksh.d | 11 +++++++++++
gas/testsuite/gas/riscv/zvksh.s | 3 +++
include/opcode/riscv-opc.h | 8 ++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 4 ++++
6 files changed, 32 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvksh.d
create mode 100644 gas/testsuite/gas/riscv/zvksh.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index c7956a22abb..2c968825707 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1211,6 +1211,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvkhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2436,6 +2437,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zvkn");
case INSN_CLASS_ZVKSED:
return riscv_subset_supports (rps, "zvksed");
+ case INSN_CLASS_ZVKSH:
+ return riscv_subset_supports (rps, "zvksh");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2606,6 +2609,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zvkn");
case INSN_CLASS_ZVKSED:
return _("zvksed");
+ case INSN_CLASS_ZVKSH:
+ return _("zvksh");
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvksh.d b/gas/testsuite/gas/riscv/zvksh.d
new file mode 100644
index 00000000000..b24d126ed7b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksh.d
@@ -0,0 +1,11 @@
+#as: -march=rv64gc_zvksh
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+ae802277[ ]+vsm3c.vi[ ]+v4,v8,0
+[ ]+[0-9a-f]+:[ ]+ae8fa277[ ]+vsm3c.vi[ ]+v4,v8,31
+[ ]+[0-9a-f]+:[ ]+82862277[ ]+vsm3me.vv[ ]+v4,v8,v12
diff --git a/gas/testsuite/gas/riscv/zvksh.s b/gas/testsuite/gas/riscv/zvksh.s
new file mode 100644
index 00000000000..bde705c5e33
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksh.s
@@ -0,0 +1,3 @@
+ vsm3c.vi v4, v8, 0
+ vsm3c.vi v4, v8, 31
+ vsm3me.vv v4, v8, v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index b44d2190250..8d60eaf260e 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2124,6 +2124,11 @@
#define MASK_VSM4RVV 0xfe0ff07f
#define MATCH_VSM4RVS 0xa6082077
#define MASK_VSM4RVS 0xfe0ff07f
+/* Zvksh instructions. */
+#define MATCH_VSM3CVI 0xae002077
+#define MASK_VSM3CVI 0xfe00707f
+#define MATCH_VSM3MEVV 0x82002077
+#define MASK_VSM3MEVV 0xfe00707f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3224,6 +3229,9 @@ DECLARE_INSN(vaeszvs, MATCH_VAESZVS, MASK_VAESZVS)
DECLARE_INSN(vsm4kvi, MATCH_VSM4KVI, MASK_VSM4KVI)
DECLARE_INSN(vsm4rvv, MATCH_VSM4RVV, MASK_VSM4RVV)
DECLARE_INSN(vsm4rvs, MATCH_VSM4RVS, MASK_VSM4RVS)
+/* Zvksh instructions. */
+DECLARE_INSN(vsm3cvi, MATCH_VSM3CVI, MASK_VSM3CVI)
+DECLARE_INSN(vsm3mevv, MATCH_VSM3MEVV, MASK_VSM3MEVV)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index d6465c2a2a4..864644f9f9b 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -416,6 +416,7 @@ enum riscv_insn_class
INSN_CLASS_ZVKHA_OR_ZVKHB,
INSN_CLASS_ZVKN,
INSN_CLASS_ZVKSED,
+ INSN_CLASS_ZVKSH,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 69e833f666c..86b07e8c1ce 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1857,6 +1857,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"vsm4r.vv", 0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4RVV, MASK_VSM4RVV, match_opcode, 0},
{"vsm4r.vs", 0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4RVS, MASK_VSM4RVS, match_opcode, 0},
+/* Zvksh instructions. */
+{"vsm3c.vi", 0, INSN_CLASS_ZVKSH, "Vd,Vt,Vj", MATCH_VSM3CVI, MASK_VSM3CVI, match_opcode, 0},
+{"vsm3me.vv", 0, INSN_CLASS_ZVKSH, "Vd,Vt,Vs", MATCH_VSM3MEVV, MASK_VSM3MEVV, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
--
2.38.1
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [RFC PATCH 6/6] RISC-V: Add Zvksh ISA extension support
2022-12-21 17:07 ` [RFC PATCH 6/6] RISC-V: Add Zvksh " Christoph Muellner
@ 2022-12-21 21:33 ` Jeff Law
0 siblings, 0 replies; 19+ messages in thread
From: Jeff Law @ 2022-12-21 21:33 UTC (permalink / raw)
To: Christoph Muellner, binutils, Nelson Chu, Andrew Waterman,
Palmer Dabbelt, Jim Wilson, Philipp Tomsich, Aaron Durbin,
Andrew de los Reyes, Eric Gouriou, Barna Ibrahim
On 12/21/22 10:07, Christoph Muellner wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This commit adds the Zvksh ISA extension instructions, which are
> part of the vector crypto extensions.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
> bfd/elfxx-riscv.c | 5 +++++
> gas/testsuite/gas/riscv/zvksh.d | 11 +++++++++++
> gas/testsuite/gas/riscv/zvksh.s | 3 +++
> include/opcode/riscv-opc.h | 8 ++++++++
> include/opcode/riscv.h | 1 +
> opcodes/riscv-opc.c | 4 ++++
> 6 files changed, 32 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/zvksh.d
> create mode 100644 gas/testsuite/gas/riscv/zvksh.s
Also looks sensible.
jeff
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [RFC PATCH 0/6] RISC-V: Add support for vector crypto extensions
2022-12-21 17:07 [RFC PATCH 0/6] RISC-V: Add support for vector crypto extensions Christoph Muellner
` (5 preceding siblings ...)
2022-12-21 17:07 ` [RFC PATCH 6/6] RISC-V: Add Zvksh " Christoph Muellner
@ 2022-12-22 2:46 ` Kito Cheng
6 siblings, 0 replies; 19+ messages in thread
From: Kito Cheng @ 2022-12-22 2:46 UTC (permalink / raw)
To: Christoph Muellner
Cc: binutils, Nelson Chu, Andrew Waterman, Palmer Dabbelt,
Jim Wilson, Philipp Tomsich, Aaron Durbin, Andrew de los Reyes,
Eric Gouriou, Barna Ibrahim
Thanks for the patch! actually I've a downstream version for that too,
but apparently isn't as complete as your version (due to lack
testsuite) :P
On Thu, Dec 22, 2022 at 1:08 AM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This series add support for the vector crypto extensions:
> * Zvkb
> * Zvkg
> * Zvkh[a,b]
> * Zvkn
> * Zvksed
> * Zvksh
>
> The implementation follows the version 20221220 of the specification,
> which can be found here:
> https://github.com/riscv/riscv-crypto/releases/tag/v20221220
>
> Note, that this specification is not frozen yet, meaning that
> incompatible changes are possible.
> Therefore, this patchset is marked as RFC and should not be considered
> for upstream inclusion.
>
> All extensions come with (passing) tests.
>
> A branch with all patches applied can be found in this GitHub repo:
> https://github.com/cmuellner/binutils-gdb/tree/riscv-zvk
>
> Christoph Müllner (6):
> RISC-V: Add Zvkb ISA extension support
> RISC-V: Add Zvkg ISA extension support
> RISC-V: Add Zvkh[a,b] ISA extension support
> RISC-V: Add Zvkn ISA extension support
> RISC-V: Add Zvksed ISA extension support
> RISC-V: Add Zvksh ISA extension support
>
> bfd/elfxx-riscv.c | 38 +++++++++
> gas/config/tc-riscv.c | 13 +++
> gas/testsuite/gas/riscv/zvkb.d | 36 ++++++++
> gas/testsuite/gas/riscv/zvkb.s | 28 +++++++
> gas/testsuite/gas/riscv/zvkg.d | 9 ++
> gas/testsuite/gas/riscv/zvkg.s | 1 +
> gas/testsuite/gas/riscv/zvkha.d | 12 +++
> gas/testsuite/gas/riscv/zvkha_zvkhb.s | 3 +
> gas/testsuite/gas/riscv/zvkhb.d | 12 +++
> gas/testsuite/gas/riscv/zvkn.d | 21 +++++
> gas/testsuite/gas/riscv/zvkn.s | 13 +++
> gas/testsuite/gas/riscv/zvksed.d | 12 +++
> gas/testsuite/gas/riscv/zvksed.s | 4 +
> gas/testsuite/gas/riscv/zvksh.d | 11 +++
> gas/testsuite/gas/riscv/zvksh.s | 3 +
> include/opcode/riscv-opc.h | 114 ++++++++++++++++++++++++++
> include/opcode/riscv.h | 12 +++
> opcodes/riscv-dis.c | 4 +
> opcodes/riscv-opc.c | 46 +++++++++++
> 19 files changed, 392 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/zvkb.d
> create mode 100644 gas/testsuite/gas/riscv/zvkb.s
> create mode 100644 gas/testsuite/gas/riscv/zvkg.d
> create mode 100644 gas/testsuite/gas/riscv/zvkg.s
> create mode 100644 gas/testsuite/gas/riscv/zvkha.d
> create mode 100644 gas/testsuite/gas/riscv/zvkha_zvkhb.s
> create mode 100644 gas/testsuite/gas/riscv/zvkhb.d
> create mode 100644 gas/testsuite/gas/riscv/zvkn.d
> create mode 100644 gas/testsuite/gas/riscv/zvkn.s
> create mode 100644 gas/testsuite/gas/riscv/zvksed.d
> create mode 100644 gas/testsuite/gas/riscv/zvksed.s
> create mode 100644 gas/testsuite/gas/riscv/zvksh.d
> create mode 100644 gas/testsuite/gas/riscv/zvksh.s
>
> --
> 2.38.1
>
^ permalink raw reply [flat|nested] 19+ messages in thread