* [PATCH 1/5] RISC-V: Add mininal support for Zicbo[mpz]
2021-12-16 11:04 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Tsukasa OI
@ 2021-12-16 11:04 ` Tsukasa OI
2021-12-16 11:04 ` [PATCH 2/5] RISC-V: Cache management instructions Tsukasa OI
` (4 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Tsukasa OI @ 2021-12-16 11:04 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
Minimal support for Zicbom, Zicboz and Zicbop extensions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_supported_std_z_ext): Add Zicbom, Zicbop
and Zicboz standard Z extensions.
---
bfd/elfxx-riscv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index c575ab093f9..14089e8d7d4 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1179,6 +1179,9 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{
+ {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
--
2.32.0
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH 2/5] RISC-V: Cache management instructions
2021-12-16 11:04 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Tsukasa OI
2021-12-16 11:04 ` [PATCH 1/5] RISC-V: Add mininal support for Zicbo[mpz] Tsukasa OI
@ 2021-12-16 11:04 ` Tsukasa OI
2022-01-04 8:01 ` Jan Beulich
2021-12-16 11:04 ` [PATCH 3/5] RISC-V: Cache management instruction testcases Tsukasa OI
` (3 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Tsukasa OI @ 2021-12-16 11:04 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds Zicbom/Zicboz instructions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add probing for
new instruction classes.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN,
MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL,
MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add cache-block management
instructions.
---
bfd/elfxx-riscv.c | 4 ++++
include/opcode/riscv-opc.h | 8 ++++++++
include/opcode/riscv.h | 2 ++
opcodes/riscv-opc.c | 6 ++++++
4 files changed, 20 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 14089e8d7d4..a0a043cb5a8 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -2332,6 +2332,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
{
case INSN_CLASS_I:
return riscv_subset_supports (rps, "i");
+ case INSN_CLASS_ZICBOM:
+ return riscv_subset_supports (rps, "zicbom");
+ case INSN_CLASS_ZICBOZ:
+ return riscv_subset_supports (rps, "zicboz");
case INSN_CLASS_ZICSR:
return riscv_subset_supports (rps, "zicsr");
case INSN_CLASS_ZIFENCEI:
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index a6ece366fa4..c804c1afd95 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -1998,6 +1998,14 @@
#define MASK_HINVAL_VVMA 0xfe007fff
#define MATCH_HINVAL_GVMA 0x66000073
#define MASK_HINVAL_GVMA 0xfe007fff
+#define MATCH_CBO_CLEAN 0x10200f
+#define MASK_CBO_CLEAN 0xfff07fff
+#define MATCH_CBO_FLUSH 0x20200f
+#define MASK_CBO_FLUSH 0xfff07fff
+#define MATCH_CBO_INVAL 0x200f
+#define MASK_CBO_INVAL 0xfff07fff
+#define MATCH_CBO_ZERO 0x40200f
+#define MASK_CBO_ZERO 0xfff07fff
/* Privileged CSR addresses. */
#define CSR_USTATUS 0x0
#define CSR_UIE 0x4
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index cbc90b00008..37f60a8b61c 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -388,6 +388,8 @@ enum riscv_insn_class
INSN_CLASS_V,
INSN_CLASS_ZVEF,
INSN_CLASS_SVINVAL,
+ INSN_CLASS_ZICBOM,
+ INSN_CLASS_ZICBOZ,
};
/* This structure holds information for a particular instruction. */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index f220006fc93..fc2a1107784 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -849,6 +849,12 @@ const struct riscv_opcode riscv_opcodes[] =
{"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
+/* Zicbom and Zicboz instructions. */
+{"cbo.clean", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
+{"cbo.flush", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
+{"cbo.inval", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
+{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "s", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
+
/* Zbb or zbkb instructions. */
{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
--
2.32.0
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 2/5] RISC-V: Cache management instructions
2021-12-16 11:04 ` [PATCH 2/5] RISC-V: Cache management instructions Tsukasa OI
@ 2022-01-04 8:01 ` Jan Beulich
2022-01-04 22:15 ` Andrew Waterman
2022-01-05 3:17 ` Tsukasa OI
0 siblings, 2 replies; 13+ messages in thread
From: Jan Beulich @ 2022-01-04 8:01 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
On 16.12.2021 12:04, Tsukasa OI via Binutils wrote:
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -849,6 +849,12 @@ const struct riscv_opcode riscv_opcodes[] =
> {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
> {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
>
> +/* Zicbom and Zicboz instructions. */
> +{"cbo.clean", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
> +{"cbo.flush", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
> +{"cbo.inval", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
> +{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "s", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
Perhaps more a spec question / remark than one on the implementation:
Wouldn't it be more natural for CBO.* to have memory-like operands,
e.g. "cbo.zero (x1)" instead of "cbo.zero x1"?
Jan
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 2/5] RISC-V: Cache management instructions
2022-01-04 8:01 ` Jan Beulich
@ 2022-01-04 22:15 ` Andrew Waterman
2022-01-05 3:17 ` Tsukasa OI
1 sibling, 0 replies; 13+ messages in thread
From: Andrew Waterman @ 2022-01-04 22:15 UTC (permalink / raw)
To: Jan Beulich; +Cc: Tsukasa OI, Binutils
On Tue, Jan 4, 2022 at 12:01 AM Jan Beulich via Binutils
<binutils@sourceware.org> wrote:
>
> On 16.12.2021 12:04, Tsukasa OI via Binutils wrote:
> > --- a/opcodes/riscv-opc.c
> > +++ b/opcodes/riscv-opc.c
> > @@ -849,6 +849,12 @@ const struct riscv_opcode riscv_opcodes[] =
> > {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
> > {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
> >
> > +/* Zicbom and Zicboz instructions. */
> > +{"cbo.clean", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
> > +{"cbo.flush", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
> > +{"cbo.inval", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
> > +{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "s", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
>
> Perhaps more a spec question / remark than one on the implementation:
> Wouldn't it be more natural for CBO.* to have memory-like operands,
> e.g. "cbo.zero (x1)" instead of "cbo.zero x1"?
Without taking a position, I'll mention that there is precedent for
the latter, too: in particular, the rs1 argument to SFENCE.VMA is an
address operand that doesn't use parens.
>
> Jan
>
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 2/5] RISC-V: Cache management instructions
2022-01-04 8:01 ` Jan Beulich
2022-01-04 22:15 ` Andrew Waterman
@ 2022-01-05 3:17 ` Tsukasa OI
1 sibling, 0 replies; 13+ messages in thread
From: Tsukasa OI @ 2022-01-05 3:17 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
Jan,
On 2022/01/04 17:01, Jan Beulich wrote:
> On 16.12.2021 12:04, Tsukasa OI via Binutils wrote:
>> --- a/opcodes/riscv-opc.c
>> +++ b/opcodes/riscv-opc.c
>> @@ -849,6 +849,12 @@ const struct riscv_opcode riscv_opcodes[] =
>> {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
>> {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
>>
>> +/* Zicbom and Zicboz instructions. */
>> +{"cbo.clean", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
>> +{"cbo.flush", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
>> +{"cbo.inval", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
>> +{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "s", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
>
> Perhaps more a spec question / remark than one on the implementation:
> Wouldn't it be more natural for CBO.* to have memory-like operands,
> e.g. "cbo.zero (x1)" instead of "cbo.zero x1"?
I would have been agreed unless mnemonic is specified on the spec.
Actually, I used "0(s)" instead of "s" for Zicbom/z instructions until
my re-review of the specification (before submission of PATCH v1).
note: "0(s)" allows "cbo.zero (x1)", "cbo.zero 0(x1)" and its equivalents.
https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0-rc2.pdf
[5.1 - cbo.clean]
Mnemonic:
cbo.clean base
[5.5 - prefetch.i]
Mnemonic:
prefetch.i offset(base)
If we really want to change that, we need to talk some RISC-V guys to
change the specification.
Thanks,
Tsukasa
>
> Jan
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/5] RISC-V: Cache management instruction testcases
2021-12-16 11:04 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Tsukasa OI
2021-12-16 11:04 ` [PATCH 1/5] RISC-V: Add mininal support for Zicbo[mpz] Tsukasa OI
2021-12-16 11:04 ` [PATCH 2/5] RISC-V: Cache management instructions Tsukasa OI
@ 2021-12-16 11:04 ` Tsukasa OI
2021-12-16 11:04 ` [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set Tsukasa OI
` (2 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Tsukasa OI @ 2021-12-16 11:04 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds assembler testsuite for Zicbom/Zicboz instructions.
* testsuite/gas/riscv/zicbom.d: New cache-block management
instruction tests.
* testsuite/gas/riscv/zicbom.s: Likewise.
* testsuite/gas/riscv/zicboz.d: New cache-block zero instruction
tests.
* testsuite/gas/riscv/zicboz.s: Likewise.
---
gas/testsuite/gas/riscv/zicbom.d | 15 +++++++++++++++
gas/testsuite/gas/riscv/zicbom.s | 7 +++++++
gas/testsuite/gas/riscv/zicboz.d | 11 +++++++++++
gas/testsuite/gas/riscv/zicboz.s | 3 +++
4 files changed, 36 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zicbom.d
create mode 100644 gas/testsuite/gas/riscv/zicbom.s
create mode 100644 gas/testsuite/gas/riscv/zicboz.d
create mode 100644 gas/testsuite/gas/riscv/zicboz.s
diff --git a/gas/testsuite/gas/riscv/zicbom.d b/gas/testsuite/gas/riscv/zicbom.d
new file mode 100644
index 00000000000..3a194cf6edf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom.d
@@ -0,0 +1,15 @@
+#as: -march=rv64g_zicbom
+#source: zicbom.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0010a00f[ ]+cbo\.clean[ ]+ra
+[ ]+[0-9a-f]+:[ ]+001f200f[ ]+cbo\.clean[ ]+t5
+[ ]+[0-9a-f]+:[ ]+0020a00f[ ]+cbo\.flush[ ]+ra
+[ ]+[0-9a-f]+:[ ]+002f200f[ ]+cbo\.flush[ ]+t5
+[ ]+[0-9a-f]+:[ ]+0000a00f[ ]+cbo\.inval[ ]+ra
+[ ]+[0-9a-f]+:[ ]+000f200f[ ]+cbo\.inval[ ]+t5
diff --git a/gas/testsuite/gas/riscv/zicbom.s b/gas/testsuite/gas/riscv/zicbom.s
new file mode 100644
index 00000000000..778a61e76f3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom.s
@@ -0,0 +1,7 @@
+target:
+ cbo.clean x1
+ cbo.clean x30
+ cbo.flush x1
+ cbo.flush x30
+ cbo.inval x1
+ cbo.inval x30
diff --git a/gas/testsuite/gas/riscv/zicboz.d b/gas/testsuite/gas/riscv/zicboz.d
new file mode 100644
index 00000000000..7686edbe677
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz.d
@@ -0,0 +1,11 @@
+#as: -march=rv64g_zicboz
+#source: zicboz.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+ra
+[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+t5
diff --git a/gas/testsuite/gas/riscv/zicboz.s b/gas/testsuite/gas/riscv/zicboz.s
new file mode 100644
index 00000000000..ba75b787b00
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz.s
@@ -0,0 +1,3 @@
+target:
+ cbo.zero x1
+ cbo.zero x30
--
2.32.0
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set
2021-12-16 11:04 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Tsukasa OI
` (2 preceding siblings ...)
2021-12-16 11:04 ` [PATCH 3/5] RISC-V: Cache management instruction testcases Tsukasa OI
@ 2021-12-16 11:04 ` Tsukasa OI
2021-12-17 15:15 ` Nelson Chu
2021-12-16 11:04 ` [PATCH 5/5] RISC-V: Prefetch hint instruction testcases Tsukasa OI
2021-12-17 15:23 ` [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Nelson Chu
5 siblings, 1 reply; 13+ messages in thread
From: Tsukasa OI @ 2021-12-16 11:04 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds Zicbop hint instructions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add probing for
new instruction class.
gas/ChangeLog:
* config/tc-riscv.c (riscv_ip): Add handling for new operand
type 'f' (32-byte aligned pseudo S-type immediate for prefetch
hints).
(validate_riscv_insn): Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I,
MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W,
MASK_PREFETCH_W): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
class INSN_CLASS_ZICBOP.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add handling for new operand
type.
* riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.
---
bfd/elfxx-riscv.c | 2 ++
gas/config/tc-riscv.c | 17 +++++++++++++++++
include/opcode/riscv-opc.h | 6 ++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-dis.c | 4 ++++
opcodes/riscv-opc.c | 3 +++
6 files changed, 33 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index a0a043cb5a8..2efc621fa07 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -2334,6 +2334,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "i");
case INSN_CLASS_ZICBOM:
return riscv_subset_supports (rps, "zicbom");
+ case INSN_CLASS_ZICBOP:
+ return riscv_subset_supports (rps, "zicbop");
case INSN_CLASS_ZICBOZ:
return riscv_subset_supports (rps, "zicboz");
case INSN_CLASS_ZICSR:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index e8061217e7c..4bb5b767140 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1160,6 +1160,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break;
case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break;
case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
+ case 'f': used_bits |= ENCODE_STYPE_IMM (-1U); break;
case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
case 'z': break; /* Zero immediate. */
case '[': break; /* Unused operand. */
@@ -3163,6 +3164,22 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
imm_expr->X_op = O_absent;
continue;
+ case 'f': /* Prefetch offset, pseudo S-type but lower 5-bits zero. */
+ if (riscv_handle_implicit_zero_offset (imm_expr, asarg))
+ continue;
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, false);
+ if (((unsigned) (imm_expr->X_add_number) & 0x1f)
+ || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
+ || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
+ as_bad (_("improper prefetch offset (%ld)"),
+ (long) imm_expr->X_add_number);
+ ip->insn_opcode |= ENCODE_STYPE_IMM (imm_expr->X_add_number);
+ ip->insn_opcode &= ~ ENCODE_STYPE_IMM (0x1fU);
+ imm_expr->X_op = O_absent;
+ asarg = expr_end;
+ continue;
+
default:
unknown_riscv_ip_operand:
as_fatal (_("internal: unknown argument type `%s'"),
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index c804c1afd95..ccd33ed4278 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2006,6 +2006,12 @@
#define MASK_CBO_INVAL 0xfff07fff
#define MATCH_CBO_ZERO 0x40200f
#define MASK_CBO_ZERO 0xfff07fff
+#define MATCH_PREFETCH_I 0x6013
+#define MASK_PREFETCH_I 0x1f07fff
+#define MATCH_PREFETCH_R 0x106013
+#define MASK_PREFETCH_R 0x1f07fff
+#define MATCH_PREFETCH_W 0x306013
+#define MASK_PREFETCH_W 0x1f07fff
/* Privileged CSR addresses. */
#define CSR_USTATUS 0x0
#define CSR_UIE 0x4
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 37f60a8b61c..4ff24cc21b4 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -389,6 +389,7 @@ enum riscv_insn_class
INSN_CLASS_ZVEF,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
+ INSN_CLASS_ZICBOP,
INSN_CLASS_ZICBOZ,
};
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index d646dd56e64..07644dbca7b 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -424,6 +424,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
break;
+ case 'f':
+ print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
+ break;
+
case 'a':
info->target = EXTRACT_JTYPE_IMM (l) + pc;
(*info->print_address_func) (info->target, info);
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index fc2a1107784..c85f1042621 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -388,6 +388,9 @@ const struct riscv_opcode riscv_opcodes[] =
{"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE },
{"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_LW, match_never, INSN_MACRO },
{"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI|MASK_IMM, MASK_XORI|MASK_IMM, match_opcode, INSN_ALIAS },
+{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 },
+{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 },
+{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 },
{"ori", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 },
{"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
{"or", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
--
2.32.0
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set
2021-12-16 11:04 ` [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set Tsukasa OI
@ 2021-12-17 15:15 ` Nelson Chu
0 siblings, 0 replies; 13+ messages in thread
From: Nelson Chu @ 2021-12-17 15:15 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Binutils
Hi Tsukasa,
On Thu, Dec 16, 2021 at 7:11 PM Tsukasa OI via Binutils
<binutils@sourceware.org> wrote:
>
> This commit adds Zicbop hint instructions.
>
> bfd/ChangeLog:
>
> * elfxx-riscv.c (riscv_multi_subset_supports): Add probing for
> new instruction class.
>
> gas/ChangeLog:
>
> * config/tc-riscv.c (riscv_ip): Add handling for new operand
> type 'f' (32-byte aligned pseudo S-type immediate for prefetch
> hints).
> (validate_riscv_insn): Likewise.
>
> include/ChangeLog:
>
> * opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I,
> MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W,
> MASK_PREFETCH_W): New macros.
> * opcode/riscv.h (enum riscv_insn_class): Add new instruction
> class INSN_CLASS_ZICBOP.
>
> opcodes/ChangeLog:
>
> * riscv-dis.c (print_insn_args): Add handling for new operand
> type.
> * riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.
> ---
> bfd/elfxx-riscv.c | 2 ++
> gas/config/tc-riscv.c | 17 +++++++++++++++++
> include/opcode/riscv-opc.h | 6 ++++++
> include/opcode/riscv.h | 1 +
> opcodes/riscv-dis.c | 4 ++++
> opcodes/riscv-opc.c | 3 +++
> 6 files changed, 33 insertions(+)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index a0a043cb5a8..2efc621fa07 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -2334,6 +2334,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
> return riscv_subset_supports (rps, "i");
> case INSN_CLASS_ZICBOM:
> return riscv_subset_supports (rps, "zicbom");
> + case INSN_CLASS_ZICBOP:
> + return riscv_subset_supports (rps, "zicbop");
> case INSN_CLASS_ZICBOZ:
> return riscv_subset_supports (rps, "zicboz");
> case INSN_CLASS_ZICSR:
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index e8061217e7c..4bb5b767140 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -1160,6 +1160,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
> case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break;
> case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break;
> case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
> + case 'f': used_bits |= ENCODE_STYPE_IMM (-1U); break;
> case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
> case 'z': break; /* Zero immediate. */
> case '[': break; /* Unused operand. */
> @@ -3163,6 +3164,22 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
> imm_expr->X_op = O_absent;
> continue;
>
> + case 'f': /* Prefetch offset, pseudo S-type but lower 5-bits zero. */
> + if (riscv_handle_implicit_zero_offset (imm_expr, asarg))
> + continue;
> + my_getExpression (imm_expr, asarg);
> + check_absolute_expr (ip, imm_expr, false);
> + if (((unsigned) (imm_expr->X_add_number) & 0x1f)
> + || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
> + || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
> + as_bad (_("improper prefetch offset (%ld)"),
> + (long) imm_expr->X_add_number);
> + ip->insn_opcode |= ENCODE_STYPE_IMM (imm_expr->X_add_number);
> + ip->insn_opcode &= ~ ENCODE_STYPE_IMM (0x1fU);
At first I felt we didn't need this line since we should already make
sure the 0-4 bits are zero of the immediate, which means the immediate
is a multiple of 32. But if I remove this line, then I will get
multiple extra illegal operand errors, which seems redundant... So I
spend some time, and notice that the redundant operand errors are
generated because we will call insn->match_func later. Therefore,
masking the low 0-4 bits will let the errors look more clean. So
LGTM.
> + imm_expr->X_op = O_absent;
> + asarg = expr_end;
> + continue;
> +
> default:
> unknown_riscv_ip_operand:
> as_fatal (_("internal: unknown argument type `%s'"),
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index c804c1afd95..ccd33ed4278 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2006,6 +2006,12 @@
> #define MASK_CBO_INVAL 0xfff07fff
> #define MATCH_CBO_ZERO 0x40200f
> #define MASK_CBO_ZERO 0xfff07fff
> +#define MATCH_PREFETCH_I 0x6013
> +#define MASK_PREFETCH_I 0x1f07fff
> +#define MATCH_PREFETCH_R 0x106013
> +#define MASK_PREFETCH_R 0x1f07fff
> +#define MATCH_PREFETCH_W 0x306013
> +#define MASK_PREFETCH_W 0x1f07fff
> /* Privileged CSR addresses. */
> #define CSR_USTATUS 0x0
> #define CSR_UIE 0x4
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 37f60a8b61c..4ff24cc21b4 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -389,6 +389,7 @@ enum riscv_insn_class
> INSN_CLASS_ZVEF,
> INSN_CLASS_SVINVAL,
> INSN_CLASS_ZICBOM,
> + INSN_CLASS_ZICBOP,
> INSN_CLASS_ZICBOZ,
> };
>
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index d646dd56e64..07644dbca7b 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -424,6 +424,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
> print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
> break;
>
> + case 'f':
> + print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
> + break;
> +
> case 'a':
> info->target = EXTRACT_JTYPE_IMM (l) + pc;
> (*info->print_address_func) (info->target, info);
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index fc2a1107784..c85f1042621 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -388,6 +388,9 @@ const struct riscv_opcode riscv_opcodes[] =
> {"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE },
> {"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_LW, match_never, INSN_MACRO },
> {"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI|MASK_IMM, MASK_XORI|MASK_IMM, match_opcode, INSN_ALIAS },
> +{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 },
> +{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 },
> +{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 },
> {"ori", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 },
> {"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
> {"or", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 5/5] RISC-V: Prefetch hint instruction testcases
2021-12-16 11:04 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Tsukasa OI
` (3 preceding siblings ...)
2021-12-16 11:04 ` [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set Tsukasa OI
@ 2021-12-16 11:04 ` Tsukasa OI
2021-12-17 15:23 ` [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Nelson Chu
5 siblings, 0 replies; 13+ messages in thread
From: Tsukasa OI @ 2021-12-16 11:04 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds assembler testsuite for Zicbop hint instructions.
gas/ChangeLog:
* testsuite/gas/riscv/zicbop-fail.d: New testcase for invalid
prefetch hint instructions.
* testsuite/gas/riscv/zicbop-fail.l: Likewise.
* testsuite/gas/riscv/zicbop-fail.s: Likewise.
* testsuite/gas/riscv/zicbop.d: New testcase for prefetch hint
instructions.
* testsuite/gas/riscv/zicbop.s: Likewise.
---
gas/testsuite/gas/riscv/zicbop-fail.d | 3 +++
gas/testsuite/gas/riscv/zicbop-fail.l | 4 ++++
gas/testsuite/gas/riscv/zicbop-fail.s | 4 ++++
gas/testsuite/gas/riscv/zicbop.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zicbop.s | 4 ++++
5 files changed, 27 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.d
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.l
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.s
create mode 100644 gas/testsuite/gas/riscv/zicbop.d
create mode 100644 gas/testsuite/gas/riscv/zicbop.s
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.d b/gas/testsuite/gas/riscv/zicbop-fail.d
new file mode 100644
index 00000000000..d734c7d4d15
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64g_zicbop
+#source: zicbop-fail.s
+#error_output: zicbop-fail.l
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.l b/gas/testsuite/gas/riscv/zicbop-fail.l
new file mode 100644
index 00000000000..4b5d5fc84fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop-fail.l
@@ -0,0 +1,4 @@
+.*: Assembler messages:
+.*: Error: improper prefetch offset \(2048\)
+.*: Error: improper prefetch offset \(-2080\)
+.*: Error: improper prefetch offset \(255\)
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.s b/gas/testsuite/gas/riscv/zicbop-fail.s
new file mode 100644
index 00000000000..0353c5ff80a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop-fail.s
@@ -0,0 +1,4 @@
+target:
+ prefetch.i 2048(x1)
+ prefetch.r -0x820(x16)
+ prefetch.w +0xff(x31)
diff --git a/gas/testsuite/gas/riscv/zicbop.d b/gas/testsuite/gas/riscv/zicbop.d
new file mode 100644
index 00000000000..056a8a501ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop.d
@@ -0,0 +1,12 @@
+#as: -march=rv64g_zicbop
+#source: zicbop.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0200e013[ ]+prefetch\.i[ ]+32\(ra\)
+[ ]+[0-9a-f]+:[ ]+80186013[ ]+prefetch\.r[ ]+-2048\(a6\)
+[ ]+[0-9a-f]+:[ ]+7e3fe013[ ]+prefetch\.w[ ]+2016\(t6\)
diff --git a/gas/testsuite/gas/riscv/zicbop.s b/gas/testsuite/gas/riscv/zicbop.s
new file mode 100644
index 00000000000..ffe2014be6f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop.s
@@ -0,0 +1,4 @@
+target:
+ prefetch.i 0x20(x1)
+ prefetch.r -2048(x16)
+ prefetch.w +0x7e0(x31)
--
2.32.0
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions
2021-12-16 11:04 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Tsukasa OI
` (4 preceding siblings ...)
2021-12-16 11:04 ` [PATCH 5/5] RISC-V: Prefetch hint instruction testcases Tsukasa OI
@ 2021-12-17 15:23 ` Nelson Chu
2021-12-17 17:24 ` Tsukasa OI
5 siblings, 1 reply; 13+ messages in thread
From: Nelson Chu @ 2021-12-17 15:23 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Binutils
Hi Tsukasa,
Thanks for implementing these extensions, LGTM. But I notice that
your copyright assignment is only for GNU WGET, and it seems it
doesn't cover the changes of binutils. It would be great if you could
check this for us, thanks.
Nelson
On Thu, Dec 16, 2021 at 7:10 PM Tsukasa OI via Binutils
<binutils@sourceware.org> wrote:
>
> This patchset adds support for three recently ratified RISC-V extensions:
>
> - Zicbom (Cache-Block Management Instructions)
> - Zicbop (Cache-Block Prefetch hint instructions)
> - Zicboz (Cache-Block Zero Instructions)
>
> `prefetch.[irw]' hint instructions in Zicbop extension require new operand
> type which is pseudo S-type immediate with low 5-bits set to zero
> (32-byte aligned). So, Zicbop changes are separate from Zicbom/Zicboz:
>
> Patch 1: Zicbom/z/p (common)
> Patch 2/3: Zicbom/z (regular CBO instructions)
> Patch 4/5: Zicbop (prefetch hint instructions)
>
> cf. <https://github.com/riscv/riscv-CMOs/blob/fc8e97a9531ac9811971a182ae431976b86216e1/specifications/cmobase-v1.0-rc2.pdf>
>
>
>
>
> Tsukasa OI (5):
> RISC-V: Add mininal support for Zicbo[mpz]
> RISC-V: Cache management instructions
> RISC-V: Cache management instruction testcases
> RISC-V: Prefetch hint instructions and operand set
> RISC-V: Prefetch hint instruction testcases
>
> bfd/elfxx-riscv.c | 9 +++++++++
> gas/config/tc-riscv.c | 17 +++++++++++++++++
> gas/testsuite/gas/riscv/zicbom.d | 15 +++++++++++++++
> gas/testsuite/gas/riscv/zicbom.s | 7 +++++++
> gas/testsuite/gas/riscv/zicbop-fail.d | 3 +++
> gas/testsuite/gas/riscv/zicbop-fail.l | 4 ++++
> gas/testsuite/gas/riscv/zicbop-fail.s | 4 ++++
> gas/testsuite/gas/riscv/zicbop.d | 12 ++++++++++++
> gas/testsuite/gas/riscv/zicbop.s | 4 ++++
> gas/testsuite/gas/riscv/zicboz.d | 11 +++++++++++
> gas/testsuite/gas/riscv/zicboz.s | 3 +++
> include/opcode/riscv-opc.h | 14 ++++++++++++++
> include/opcode/riscv.h | 3 +++
> opcodes/riscv-dis.c | 4 ++++
> opcodes/riscv-opc.c | 9 +++++++++
> 15 files changed, 119 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/zicbom.d
> create mode 100644 gas/testsuite/gas/riscv/zicbom.s
> create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.d
> create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.l
> create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.s
> create mode 100644 gas/testsuite/gas/riscv/zicbop.d
> create mode 100644 gas/testsuite/gas/riscv/zicbop.s
> create mode 100644 gas/testsuite/gas/riscv/zicboz.d
> create mode 100644 gas/testsuite/gas/riscv/zicboz.s
>
>
> base-commit: 23ff54c27d535727c1c467abdd4bed8fbd46d4a6
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions
2021-12-17 15:23 ` [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Nelson Chu
@ 2021-12-17 17:24 ` Tsukasa OI
2021-12-17 17:39 ` Nelson Chu
0 siblings, 1 reply; 13+ messages in thread
From: Tsukasa OI @ 2021-12-17 17:24 UTC (permalink / raw)
To: Nelson Chu; +Cc: Binutils
Hi Nelson,
Thanks for quick review and ...I didn't expect that you can view
my copyright assignment status.
Anyway, you are right. Considering I'm preparing far more larger patchset
(privileged specification 1.12 CSRs), I definitely need copyright
assignment including future changes.
I requested copyright assignment form based on request-assign.future and
legal procedures will complete in a few weeks (I guess).
Tsukasa
On 2021/12/18 0:23, Nelson Chu wrote:
> Hi Tsukasa,
>
> Thanks for implementing these extensions, LGTM. But I notice that
> your copyright assignment is only for GNU WGET, and it seems it
> doesn't cover the changes of binutils. It would be great if you could
> check this for us, thanks.
>
> Nelson
>
>
> On Thu, Dec 16, 2021 at 7:10 PM Tsukasa OI via Binutils
> <binutils@sourceware.org> wrote:
>>
>> This patchset adds support for three recently ratified RISC-V extensions:
>>
>> - Zicbom (Cache-Block Management Instructions)
>> - Zicbop (Cache-Block Prefetch hint instructions)
>> - Zicboz (Cache-Block Zero Instructions)
>>
>> `prefetch.[irw]' hint instructions in Zicbop extension require new operand
>> type which is pseudo S-type immediate with low 5-bits set to zero
>> (32-byte aligned). So, Zicbop changes are separate from Zicbom/Zicboz:
>>
>> Patch 1: Zicbom/z/p (common)
>> Patch 2/3: Zicbom/z (regular CBO instructions)
>> Patch 4/5: Zicbop (prefetch hint instructions)
>>
>> cf. <https://github.com/riscv/riscv-CMOs/blob/fc8e97a9531ac9811971a182ae431976b86216e1/specifications/cmobase-v1.0-rc2.pdf>
>>
>>
>>
>>
>> Tsukasa OI (5):
>> RISC-V: Add mininal support for Zicbo[mpz]
>> RISC-V: Cache management instructions
>> RISC-V: Cache management instruction testcases
>> RISC-V: Prefetch hint instructions and operand set
>> RISC-V: Prefetch hint instruction testcases
>>
>> bfd/elfxx-riscv.c | 9 +++++++++
>> gas/config/tc-riscv.c | 17 +++++++++++++++++
>> gas/testsuite/gas/riscv/zicbom.d | 15 +++++++++++++++
>> gas/testsuite/gas/riscv/zicbom.s | 7 +++++++
>> gas/testsuite/gas/riscv/zicbop-fail.d | 3 +++
>> gas/testsuite/gas/riscv/zicbop-fail.l | 4 ++++
>> gas/testsuite/gas/riscv/zicbop-fail.s | 4 ++++
>> gas/testsuite/gas/riscv/zicbop.d | 12 ++++++++++++
>> gas/testsuite/gas/riscv/zicbop.s | 4 ++++
>> gas/testsuite/gas/riscv/zicboz.d | 11 +++++++++++
>> gas/testsuite/gas/riscv/zicboz.s | 3 +++
>> include/opcode/riscv-opc.h | 14 ++++++++++++++
>> include/opcode/riscv.h | 3 +++
>> opcodes/riscv-dis.c | 4 ++++
>> opcodes/riscv-opc.c | 9 +++++++++
>> 15 files changed, 119 insertions(+)
>> create mode 100644 gas/testsuite/gas/riscv/zicbom.d
>> create mode 100644 gas/testsuite/gas/riscv/zicbom.s
>> create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.d
>> create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.l
>> create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.s
>> create mode 100644 gas/testsuite/gas/riscv/zicbop.d
>> create mode 100644 gas/testsuite/gas/riscv/zicbop.s
>> create mode 100644 gas/testsuite/gas/riscv/zicboz.d
>> create mode 100644 gas/testsuite/gas/riscv/zicboz.s
>>
>>
>> base-commit: 23ff54c27d535727c1c467abdd4bed8fbd46d4a6
>> --
>> 2.32.0
>>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions
2021-12-17 17:24 ` Tsukasa OI
@ 2021-12-17 17:39 ` Nelson Chu
0 siblings, 0 replies; 13+ messages in thread
From: Nelson Chu @ 2021-12-17 17:39 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Binutils
On Sat, Dec 18, 2021 at 1:24 AM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> Hi Nelson,
>
> Thanks for quick review and ...I didn't expect that you can view
> my copyright assignment status.
Yes, I can’t, but I ask someone with permission to check it out for me :P
> Anyway, you are right. Considering I'm preparing far more larger patchset
> (privileged specification 1.12 CSRs), I definitely need copyright
> assignment including future changes.
>
> I requested copyright assignment form based on request-assign.future and
> legal procedures will complete in a few weeks (I guess).
Yeah, sometimes it’s done quickly, but sometimes it takes a while. I
will wait for your good news, thanks.
Nelson
> Tsukasa
>
> On 2021/12/18 0:23, Nelson Chu wrote:
> > Hi Tsukasa,
> >
> > Thanks for implementing these extensions, LGTM. But I notice that
> > your copyright assignment is only for GNU WGET, and it seems it
> > doesn't cover the changes of binutils. It would be great if you could
> > check this for us, thanks.
> >
> > Nelson
> >
> >
> > On Thu, Dec 16, 2021 at 7:10 PM Tsukasa OI via Binutils
> > <binutils@sourceware.org> wrote:
> >>
> >> This patchset adds support for three recently ratified RISC-V extensions:
> >>
> >> - Zicbom (Cache-Block Management Instructions)
> >> - Zicbop (Cache-Block Prefetch hint instructions)
> >> - Zicboz (Cache-Block Zero Instructions)
> >>
> >> `prefetch.[irw]' hint instructions in Zicbop extension require new operand
> >> type which is pseudo S-type immediate with low 5-bits set to zero
> >> (32-byte aligned). So, Zicbop changes are separate from Zicbom/Zicboz:
> >>
> >> Patch 1: Zicbom/z/p (common)
> >> Patch 2/3: Zicbom/z (regular CBO instructions)
> >> Patch 4/5: Zicbop (prefetch hint instructions)
> >>
> >> cf. <https://github.com/riscv/riscv-CMOs/blob/fc8e97a9531ac9811971a182ae431976b86216e1/specifications/cmobase-v1.0-rc2.pdf>
> >>
> >>
> >>
> >>
> >> Tsukasa OI (5):
> >> RISC-V: Add mininal support for Zicbo[mpz]
> >> RISC-V: Cache management instructions
> >> RISC-V: Cache management instruction testcases
> >> RISC-V: Prefetch hint instructions and operand set
> >> RISC-V: Prefetch hint instruction testcases
> >>
> >> bfd/elfxx-riscv.c | 9 +++++++++
> >> gas/config/tc-riscv.c | 17 +++++++++++++++++
> >> gas/testsuite/gas/riscv/zicbom.d | 15 +++++++++++++++
> >> gas/testsuite/gas/riscv/zicbom.s | 7 +++++++
> >> gas/testsuite/gas/riscv/zicbop-fail.d | 3 +++
> >> gas/testsuite/gas/riscv/zicbop-fail.l | 4 ++++
> >> gas/testsuite/gas/riscv/zicbop-fail.s | 4 ++++
> >> gas/testsuite/gas/riscv/zicbop.d | 12 ++++++++++++
> >> gas/testsuite/gas/riscv/zicbop.s | 4 ++++
> >> gas/testsuite/gas/riscv/zicboz.d | 11 +++++++++++
> >> gas/testsuite/gas/riscv/zicboz.s | 3 +++
> >> include/opcode/riscv-opc.h | 14 ++++++++++++++
> >> include/opcode/riscv.h | 3 +++
> >> opcodes/riscv-dis.c | 4 ++++
> >> opcodes/riscv-opc.c | 9 +++++++++
> >> 15 files changed, 119 insertions(+)
> >> create mode 100644 gas/testsuite/gas/riscv/zicbom.d
> >> create mode 100644 gas/testsuite/gas/riscv/zicbom.s
> >> create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.d
> >> create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.l
> >> create mode 100644 gas/testsuite/gas/riscv/zicbop-fail.s
> >> create mode 100644 gas/testsuite/gas/riscv/zicbop.d
> >> create mode 100644 gas/testsuite/gas/riscv/zicbop.s
> >> create mode 100644 gas/testsuite/gas/riscv/zicboz.d
> >> create mode 100644 gas/testsuite/gas/riscv/zicboz.s
> >>
> >>
> >> base-commit: 23ff54c27d535727c1c467abdd4bed8fbd46d4a6
> >> --
> >> 2.32.0
> >>
> >
^ permalink raw reply [flat|nested] 13+ messages in thread