From: Andrea Corallo <andrea.corallo@arm.com>
To: <gcc-patches@gcc.gnu.org>
Cc: <kyrylo.tkachov@arm.com>, <Richard.Earnshaw@arm.com>,
Andrea Corallo <andrea.corallo@arm.com>
Subject: [PATCH 06/35] arm: improve tests and fix vdupq*
Date: Thu, 17 Nov 2022 17:37:40 +0100 [thread overview]
Message-ID: <20221117163809.1009526-7-andrea.corallo@arm.com> (raw)
In-Reply-To: <20221117163809.1009526-1-andrea.corallo@arm.com>
gcc/ChangeLog:
* config/arm/mve.md (mve_vdupq_n_f<mode>)
(mve_vdupq_n_<supf><mode>, mve_vdupq_m_n_<supf><mode>)
(mve_vdupq_m_n_f<mode>): Fix spacing.
gcc/testsuite/ChangeLog:
* gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c: Improve test.
* gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c: Likewise.
---
gcc/config/arm/mve.md | 8 ++--
.../arm/mve/intrinsics/vdupq_m_n_f16.c | 41 +++++++++++++++++--
.../arm/mve/intrinsics/vdupq_m_n_f32.c | 41 +++++++++++++++++--
.../arm/mve/intrinsics/vdupq_m_n_s16.c | 25 +++++++++--
.../arm/mve/intrinsics/vdupq_m_n_s32.c | 25 +++++++++--
.../arm/mve/intrinsics/vdupq_m_n_s8.c | 25 +++++++++--
.../arm/mve/intrinsics/vdupq_m_n_u16.c | 41 +++++++++++++++++--
.../arm/mve/intrinsics/vdupq_m_n_u32.c | 41 +++++++++++++++++--
.../arm/mve/intrinsics/vdupq_m_n_u8.c | 41 +++++++++++++++++--
.../arm/mve/intrinsics/vdupq_n_f16.c | 21 +++++++++-
.../arm/mve/intrinsics/vdupq_n_f32.c | 21 +++++++++-
.../arm/mve/intrinsics/vdupq_n_s16.c | 13 ++++--
.../arm/mve/intrinsics/vdupq_n_s32.c | 13 ++++--
.../arm/mve/intrinsics/vdupq_n_s8.c | 9 +++-
.../arm/mve/intrinsics/vdupq_n_u16.c | 23 ++++++++++-
.../arm/mve/intrinsics/vdupq_n_u32.c | 23 ++++++++++-
.../arm/mve/intrinsics/vdupq_n_u8.c | 23 ++++++++++-
.../arm/mve/intrinsics/vdupq_x_n_f16.c | 30 +++++++++++++-
.../arm/mve/intrinsics/vdupq_x_n_f32.c | 30 +++++++++++++-
.../arm/mve/intrinsics/vdupq_x_n_s16.c | 14 ++++++-
.../arm/mve/intrinsics/vdupq_x_n_s32.c | 14 ++++++-
.../arm/mve/intrinsics/vdupq_x_n_s8.c | 14 ++++++-
.../arm/mve/intrinsics/vdupq_x_n_u16.c | 30 +++++++++++++-
.../arm/mve/intrinsics/vdupq_x_n_u32.c | 30 +++++++++++++-
.../arm/mve/intrinsics/vdupq_x_n_u8.c | 30 +++++++++++++-
25 files changed, 567 insertions(+), 59 deletions(-)
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 58ffe03c499..6d5270281ec 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -266,7 +266,7 @@ (define_insn "mve_vdupq_n_f<mode>"
VDUPQ_N_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vdup.%#<V_sz_elem> %q0, %1"
+ "vdup.%#<V_sz_elem>\t%q0, %1"
[(set_attr "type" "mve_move")
])
@@ -435,7 +435,7 @@ (define_insn "mve_vdupq_n_<supf><mode>"
VDUPQ_N))
]
"TARGET_HAVE_MVE"
- "vdup.%#<V_sz_elem> %q0, %1"
+ "vdup.%#<V_sz_elem>\t%q0, %1"
[(set_attr "type" "mve_move")
])
@@ -3046,7 +3046,7 @@ (define_insn "mve_vdupq_m_n_<supf><mode>"
VDUPQ_M_N))
]
"TARGET_HAVE_MVE"
- "vpst\;vdupt.%#<V_sz_elem> %q0, %2"
+ "vpst\;vdupt.%#<V_sz_elem>\t%q0, %2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -3991,7 +3991,7 @@ (define_insn "mve_vdupq_m_n_f<mode>"
VDUPQ_M_N_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vdupt.%#<V_sz_elem> %q0, %2"
+ "vpst\;vdupt.%#<V_sz_elem>\t%q0, %2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c
index 0b749be3527..bfa471bcb31 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c
@@ -1,22 +1,57 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16_t a, mve_pred16_t p)
{
return vdupq_m_n_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16_t a, mve_pred16_t p)
{
return vdupq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+float16x8_t
+foo2 (float16x8_t inactive, mve_pred16_t p)
+{
+ return vdupq_m (inactive, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c
index 9cca5310c7a..e1dd8f58ad0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c
@@ -1,22 +1,57 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32_t a, mve_pred16_t p)
{
return vdupq_m_n_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32_t a, mve_pred16_t p)
{
return vdupq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+float32x4_t
+foo2 (float32x4_t inactive, mve_pred16_t p)
+{
+ return vdupq_m (inactive, 1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c
index b521f13e94f..52304ace03a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16_t a, mve_pred16_t p)
{
return vdupq_m_n_s16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16_t a, mve_pred16_t p)
{
return vdupq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c
index 96aa195dc18..44a80c5d5bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32_t a, mve_pred16_t p)
{
return vdupq_m_n_s32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32_t a, mve_pred16_t p)
{
return vdupq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c
index f1d222000c1..1630a3b9234 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8_t a, mve_pred16_t p)
{
return vdupq_m_n_s8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8_t a, mve_pred16_t p)
{
return vdupq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c
index 39d0c9f502d..d3df8b69248 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c
@@ -1,22 +1,57 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16_t a, mve_pred16_t p)
{
return vdupq_m_n_u16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16_t a, mve_pred16_t p)
{
return vdupq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+ return vdupq_m (inactive, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c
index fc107172e16..e6bb0cc2c38 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c
@@ -1,22 +1,57 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32_t a, mve_pred16_t p)
{
return vdupq_m_n_u32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32_t a, mve_pred16_t p)
{
return vdupq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+ return vdupq_m (inactive, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c
index 9fd3bc443cb..ad6f6d04ae3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c
@@ -1,22 +1,57 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8_t a, mve_pred16_t p)
{
return vdupq_m_n_u8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8_t a, mve_pred16_t p)
{
return vdupq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+ return vdupq_m (inactive, 1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c
index 62bfc194533..fc5a7933653 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c
@@ -1,13 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vdup.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16_t a)
{
return vdupq_n_f16 (a);
}
-/* { dg-final { scan-assembler "vdup.16" } } */
+/*
+**foo1:
+** ...
+** vdup.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 ()
+{
+ return vdupq_n_f16 (1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c
index f5ad2286d8d..a6be82e5927 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c
@@ -1,13 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vdup.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32_t a)
{
return vdupq_n_f32 (a);
}
-/* { dg-final { scan-assembler "vdup.32" } } */
+/*
+**foo1:
+** ...
+** vdup.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 ()
+{
+ return vdupq_n_f32 (1.1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c
index 1378522a18e..f842b96c3b1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c
@@ -1,13 +1,20 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vdup.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16_t a)
{
return vdupq_n_s16 (a);
}
-/* { dg-final { scan-assembler "vdup.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c
index 43affe856c0..05cbff8fdae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c
@@ -1,13 +1,20 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vdup.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32_t a)
{
return vdupq_n_s32 (a);
}
-/* { dg-final { scan-assembler "vdup.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c
index 3f934dc5d59..1d141161604 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c
@@ -1,13 +1,20 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vdup.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8_t a)
{
return vdupq_n_s8 (a);
}
-/* { dg-final { scan-assembler "vdup.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c
index 93268643fec..4839d427e65 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c
@@ -1,13 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vdup.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16_t a)
{
- return vdupq_n_u16 (a);
+ return vdupq_n_u16 (a);
}
-/* { dg-final { scan-assembler "vdup.16" } } */
+/*
+**foo1:
+** ...
+** vdup.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo1 ()
+{
+ return vdupq_n_u16 (1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c
index 276e9ddc67f..f0069eb7280 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c
@@ -1,13 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vdup.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32_t a)
{
- return vdupq_n_u32 (a);
+ return vdupq_n_u32 (a);
}
-/* { dg-final { scan-assembler "vdup.32" } } */
+/*
+**foo1:
+** ...
+** vdup.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint32x4_t
+foo1 ()
+{
+ return vdupq_n_u32 (1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c
index d0361c15047..fe26687ae45 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c
@@ -1,13 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vdup.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8_t a)
{
- return vdupq_n_u8 (a);
+ return vdupq_n_u8 (a);
}
-/* { dg-final { scan-assembler "vdup.8" } } */
+/*
+**foo1:
+** ...
+** vdup.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint8x16_t
+foo1 ()
+{
+ return vdupq_n_u8 (1);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c
index c91ee62791c..11ebb47f94f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c
@@ -1,14 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16_t a, mve_pred16_t p)
{
return vdupq_x_n_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (mve_pred16_t p)
+{
+ return vdupq_x_n_f16 (1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c
index c2b39051f5b..4e79bd54f71 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c
@@ -1,14 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32_t a, mve_pred16_t p)
{
return vdupq_x_n_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (mve_pred16_t p)
+{
+ return vdupq_x_n_f32 (1.1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c
index cc8a5bfeca1..90288777df7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c
@@ -1,14 +1,24 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16_t a, mve_pred16_t p)
{
return vdupq_x_n_s16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c
index b3ed3eb68e8..c4c906e0682 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c
@@ -1,14 +1,24 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32_t a, mve_pred16_t p)
{
return vdupq_x_n_s32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c
index 3be865dcc84..6234730827e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c
@@ -1,14 +1,24 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8_t a, mve_pred16_t p)
{
return vdupq_x_n_s8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c
index d01338aeb91..821fcddcab1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c
@@ -1,14 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16_t a, mve_pred16_t p)
{
return vdupq_x_n_u16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo1 (mve_pred16_t p)
+{
+ return vdupq_x_n_u16 (1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c
index 8fa7d4552bc..20125df6226 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c
@@ -1,14 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32_t a, mve_pred16_t p)
{
return vdupq_x_n_u32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint32x4_t
+foo1 (mve_pred16_t p)
+{
+ return vdupq_x_n_u32 (1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c
index 96ad899c9c2..defaaeebfcf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c
@@ -1,14 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8_t a, mve_pred16_t p)
{
return vdupq_x_n_u8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint8x16_t
+foo1 (mve_pred16_t p)
+{
+ return vdupq_x_n_u8 (1, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--
2.25.1
next prev parent reply other threads:[~2022-11-17 16:38 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-17 16:37 [PATCH 00/35] arm: rework MVE testsuite and rework backend where necessary (1st chunk) Andrea Corallo
2022-11-17 16:37 ` [PATCH 01/35] arm: improve vcreateq* tests Andrea Corallo
2022-11-18 9:47 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 02/35] arm: fix 'vmsr' spacing and register capitalization Andrea Corallo
2022-11-18 16:33 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 03/35] arm: improve tests and fix vddupq* Andrea Corallo
2022-11-18 16:34 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 04/35] arm: improve tests and fix vdwdupq* Andrea Corallo
2022-11-18 16:35 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 05/35] arm: improve vidupq* tests Andrea Corallo
2022-11-18 16:36 ` Kyrylo Tkachov
2022-11-17 16:37 ` Andrea Corallo [this message]
2022-11-18 16:37 ` [PATCH 06/35] arm: improve tests and fix vdupq* Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 07/35] arm: improve tests and fix vcmp* Andrea Corallo
2022-11-18 16:40 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 08/35] arm: improve tests for vmin* Andrea Corallo
2022-11-18 16:41 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 09/35] arm: improve tests for vmax* Andrea Corallo
2022-11-18 16:42 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 10/35] arm: improve tests for vabavq* Andrea Corallo
2022-11-18 16:43 ` Kyrylo Tkachov
2022-11-21 14:49 ` Andrea Corallo
2022-11-17 16:37 ` [PATCH 11/35] arm: improve tests for vabdq* Andrea Corallo
2022-11-18 16:44 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 12/35] arm: improve tests and fix vabsq* Andrea Corallo
2022-11-18 16:45 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 13/35] arm: further fix overloading of MVE vaddq[_m]_n intrinsic Andrea Corallo
2022-11-18 16:49 ` Kyrylo Tkachov
2022-11-21 10:45 ` Stam Markianos-Wright
2022-11-17 16:37 ` [PATCH 14/35] arm: propagate fixed overloading of MVE intrinsic scalar parameters Andrea Corallo
2022-11-18 16:51 ` Kyrylo Tkachov
2022-11-21 10:46 ` Stam Markianos-Wright
2022-11-17 16:37 ` [PATCH 15/35] arm: Explicitly specify other float types for _Generic overloading [PR107515] Andrea Corallo
2022-11-18 16:58 ` Kyrylo Tkachov
2022-11-20 22:49 ` Ramana Radhakrishnan
2022-11-21 14:11 ` Stam Markianos-Wright
2022-11-21 10:45 ` Stam Markianos-Wright
2022-11-17 16:37 ` [PATCH 16/35] arm: Add integer vector overloading of vsubq_x instrinsic Andrea Corallo
2022-11-22 10:00 ` Christophe Lyon
2022-11-22 10:54 ` Andrea Corallo
2022-11-22 16:48 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 17/35] arm: improve tests and fix vadd* Andrea Corallo
2022-11-22 16:49 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 18/35] arm: improve tests for vmulq* Andrea Corallo
2022-11-22 16:51 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 19/35] arm: improve tests and fix vsubq* Andrea Corallo
2022-11-22 16:51 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 20/35] arm: improve tests for vfmasq_m* Andrea Corallo
2022-11-22 16:52 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 21/35] arm: improve tests for vhaddq_m* Andrea Corallo
2022-11-22 16:53 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 22/35] arm: improve tests for vhsubq_m* Andrea Corallo
2022-11-22 16:53 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 23/35] arm: improve tests for viwdupq* Andrea Corallo
2022-11-22 16:54 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 24/35] arm: improve tests for vmladavaq* Andrea Corallo
2022-11-22 16:54 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 25/35] arm: improve tests and fix vmlaldavaxq* Andrea Corallo
2022-11-22 16:56 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 26/35] arm: improve tests for vmlasq* Andrea Corallo
2022-11-22 16:56 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 27/35] arm: improve tests for vqaddq_m* Andrea Corallo
2022-11-22 16:57 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 28/35] arm: improve tests for vqdmlahq_m* Andrea Corallo
2022-11-22 16:57 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 29/35] arm: improve tests for vqdmul* Andrea Corallo
2022-11-22 16:58 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 30/35] arm: improve tests for vqrdmlahq* Andrea Corallo
2022-11-22 17:01 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 31/35] arm: improve tests for vqrdmlashq_m* Andrea Corallo
2022-11-22 17:02 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 32/35] arm: improve tests for vqsubq* Andrea Corallo
2022-11-22 17:03 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 33/35] arm: improve tests and fix vrmlaldavhaq* Andrea Corallo
2022-11-22 17:03 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 34/35] arm: improve tests for vrshlq* Andrea Corallo
2022-11-22 17:04 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 35/35] arm: improve tests for vsetq_lane* Andrea Corallo
2022-11-22 17:06 ` Kyrylo Tkachov
2022-11-24 14:43 ` [PATCH 35/35 V2] " Andrea Corallo
2022-11-24 15:28 ` Kyrylo Tkachov
2022-11-28 9:20 ` [PATCH 00/35] arm: rework MVE testsuite and rework backend where necessary (1st chunk) Andrea Corallo
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