From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
To: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>,
Andrea Corallo <Andrea.Corallo@arm.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>
Subject: Re: [PATCH 13/35] arm: further fix overloading of MVE vaddq[_m]_n intrinsic
Date: Mon, 21 Nov 2022 10:45:39 +0000 [thread overview]
Message-ID: <dd22a8f0-d97d-98a0-9d91-68239e7e989f@arm.com> (raw)
In-Reply-To: <PAXPR08MB6926679F8C3858D577D4769B93099@PAXPR08MB6926.eurprd08.prod.outlook.com>
On 11/18/22 16:49, Kyrylo Tkachov wrote:
>
>> -----Original Message-----
>> From: Andrea Corallo <andrea.corallo@arm.com>
>> Sent: Thursday, November 17, 2022 4:38 PM
>> To: gcc-patches@gcc.gnu.org
>> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
>> <Richard.Earnshaw@arm.com>; Stam Markianos-Wright <Stam.Markianos-
>> Wright@arm.com>
>> Subject: [PATCH 13/35] arm: further fix overloading of MVE vaddq[_m]_n
>> intrinsic
>>
>> From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
>>
>> It was observed that in tests `vaddq_m_n_[s/u][8/16/32].c`, the _Generic
>> resolution would fall back to the `__ARM_undef` failure state.
>>
>> This is a regression since `dc39db873670bea8d8e655444387ceaa53a01a79`
>> and
>> `6bd4ce64eb48a72eca300cb52773e6101d646004`, but it previously wasn't
>> identified, because the tests were not checking for this kind of failure.
>>
>> The above commits changed the definitions of the intrinsics from using
>> `[u]int[8/16/32]_t` types for the scalar argument to using `int`. This
>> allowed `int` to be supported in user code through the overloaded
>> `#defines`, but seems to have broken the `[u]int[8/16/32]_t` types
>>
>> The solution implemented by this patch is to explicitly use a new
>> _Generic mapping from all the `[u]int[8/16/32]_t` types for int. With this
>> change, both `int` and `[u]int[8/16/32]_t` parameters are supported from
>> user code and are handled by the overloading mechanism correctly.
>>
>> gcc/ChangeLog:
>>
>> * config/arm/arm_mve.h (__arm_vaddq_m_n_s8): Change types.
>> (__arm_vaddq_m_n_s32): Likewise.
>> (__arm_vaddq_m_n_s16): Likewise.
>> (__arm_vaddq_m_n_u8): Likewise.
>> (__arm_vaddq_m_n_u32): Likewise.
>> (__arm_vaddq_m_n_u16): Likewise.
>> (__arm_vaddq_m): Fix Overloading.
>> (__ARM_mve_coerce3): New.
> Ok. Wasn't there a PR in Bugzilla about this that we can cite in the commit message?
> Thanks,
> Kyrill
Thanks for the review! Ah yes, there was this one:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96795
which was closed last time around.
It does make sense to add it, though, so we'll do that.
Thanks!
>
>> ---
>> gcc/config/arm/arm_mve.h | 78 ++++++++++++++++++++--------------------
>> 1 file changed, 40 insertions(+), 38 deletions(-)
>>
>> diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
>> index 684f997520f..951dc25374b 100644
>> --- a/gcc/config/arm/arm_mve.h
>> +++ b/gcc/config/arm/arm_mve.h
>> @@ -9675,42 +9675,42 @@ __arm_vabdq_m_u16 (uint16x8_t __inactive,
>> uint16x8_t __a, uint16x8_t __b, mve_pr
>>
>> __extension__ extern __inline int8x16_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> -__arm_vaddq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int __b,
>> mve_pred16_t __p)
>> +__arm_vaddq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b,
>> mve_pred16_t __p)
>> {
>> return __builtin_mve_vaddq_m_n_sv16qi (__inactive, __a, __b, __p);
>> }
>>
>> __extension__ extern __inline int32x4_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> -__arm_vaddq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int __b,
>> mve_pred16_t __p)
>> +__arm_vaddq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b,
>> mve_pred16_t __p)
>> {
>> return __builtin_mve_vaddq_m_n_sv4si (__inactive, __a, __b, __p);
>> }
>>
>> __extension__ extern __inline int16x8_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> -__arm_vaddq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int __b,
>> mve_pred16_t __p)
>> +__arm_vaddq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b,
>> mve_pred16_t __p)
>> {
>> return __builtin_mve_vaddq_m_n_sv8hi (__inactive, __a, __b, __p);
>> }
>>
>> __extension__ extern __inline uint8x16_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> -__arm_vaddq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, int __b,
>> mve_pred16_t __p)
>> +__arm_vaddq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b,
>> mve_pred16_t __p)
>> {
>> return __builtin_mve_vaddq_m_n_uv16qi (__inactive, __a, __b, __p);
>> }
>>
>> __extension__ extern __inline uint32x4_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> -__arm_vaddq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, int __b,
>> mve_pred16_t __p)
>> +__arm_vaddq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t
>> __b, mve_pred16_t __p)
>> {
>> return __builtin_mve_vaddq_m_n_uv4si (__inactive, __a, __b, __p);
>> }
>>
>> __extension__ extern __inline uint16x8_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> -__arm_vaddq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, int __b,
>> mve_pred16_t __p)
>> +__arm_vaddq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t
>> __b, mve_pred16_t __p)
>> {
>> return __builtin_mve_vaddq_m_n_uv8hi (__inactive, __a, __b, __p);
>> }
>> @@ -26417,42 +26417,42 @@ __arm_vabdq_m (uint16x8_t __inactive,
>> uint16x8_t __a, uint16x8_t __b, mve_pred16
>>
>> __extension__ extern __inline int8x16_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> -__arm_vaddq_m (int8x16_t __inactive, int8x16_t __a, int __b,
>> mve_pred16_t __p)
>> +__arm_vaddq_m (int8x16_t __inactive, int8x16_t __a, int8_t __b,
>> mve_pred16_t __p)
>> {
>> return __arm_vaddq_m_n_s8 (__inactive, __a, __b, __p);
>> }
>>
>> __extension__ extern __inline int32x4_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> -__arm_vaddq_m (int32x4_t __inactive, int32x4_t __a, int __b,
>> mve_pred16_t __p)
>> +__arm_vaddq_m (int32x4_t __inactive, int32x4_t __a, int32_t __b,
>> mve_pred16_t __p)
>> {
>> return __arm_vaddq_m_n_s32 (__inactive, __a, __b, __p);
>> }
>>
>> __extension__ extern __inline int16x8_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> -__arm_vaddq_m (int16x8_t __inactive, int16x8_t __a, int __b,
>> mve_pred16_t __p)
>> +__arm_vaddq_m (int16x8_t __inactive, int16x8_t __a, int16_t __b,
>> mve_pred16_t __p)
>> {
>> return __arm_vaddq_m_n_s16 (__inactive, __a, __b, __p);
>> }
>>
>> __extension__ extern __inline uint8x16_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> -__arm_vaddq_m (uint8x16_t __inactive, uint8x16_t __a, int __b,
>> mve_pred16_t __p)
>> +__arm_vaddq_m (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b,
>> mve_pred16_t __p)
>> {
>> return __arm_vaddq_m_n_u8 (__inactive, __a, __b, __p);
>> }
>>
>> __extension__ extern __inline uint32x4_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> -__arm_vaddq_m (uint32x4_t __inactive, uint32x4_t __a, int __b,
>> mve_pred16_t __p)
>> +__arm_vaddq_m (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b,
>> mve_pred16_t __p)
>> {
>> return __arm_vaddq_m_n_u32 (__inactive, __a, __b, __p);
>> }
>>
>> __extension__ extern __inline uint16x8_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> -__arm_vaddq_m (uint16x8_t __inactive, uint16x8_t __a, int __b,
>> mve_pred16_t __p)
>> +__arm_vaddq_m (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b,
>> mve_pred16_t __p)
>> {
>> return __arm_vaddq_m_n_u16 (__inactive, __a, __b, __p);
>> }
>> @@ -35657,6 +35657,8 @@ extern void *__ARM_undef;
>> _Generic(param, type: param, const type: param, default: *(type
>> *)__ARM_undef)
>> #define __ARM_mve_coerce2(param, type) \
>> _Generic(param, type: param, float16_t: param, float32_t: param, default:
>> *(type *)__ARM_undef)
>> +#define __ARM_mve_coerce3(param, type) \
>> + _Generic(param, type: param, int8_t: param, int16_t: param, int32_t:
>> param, int64_t: param, uint8_t: param, uint16_t: param, uint32_t: param,
>> uint64_t: param, default: *(type *)__ARM_undef)
>>
>> #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */
>>
>> @@ -35871,14 +35873,14 @@ extern void *__ARM_undef;
>> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
>> __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
>> __ARM_mve_coerce(__p1, uint8x16_t)), \
>> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
>> __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
>> __ARM_mve_coerce(__p1, uint16x8_t)), \
>> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
>> __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
>> __ARM_mve_coerce(__p1, uint32x4_t)), \
>> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]:
>> __arm_vaddq_f16 (__ARM_mve_coerce(p0, float16x8_t),
>> __ARM_mve_coerce(p1, float16x8_t)), \
>> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]:
>> __arm_vaddq_f32 (__ARM_mve_coerce(p0, float32x4_t),
>> __ARM_mve_coerce(p1, float32x4_t)), \
>> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
>> __ARM_mve_coerce(__p1, int)), \
>> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
>> __ARM_mve_coerce(__p1, int)), \
>> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
>> __ARM_mve_coerce(__p1, int)), \
>> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
>> __ARM_mve_coerce(__p1, int)), \
>> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
>> __ARM_mve_coerce(__p1, int)), \
>> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
>> __ARM_mve_coerce(__p1, int)), \
>> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]:
>> __arm_vaddq_f16 (__ARM_mve_coerce(__p0, float16x8_t),
>> __ARM_mve_coerce(__p1, float16x8_t)), \
>> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]:
>> __arm_vaddq_f32 (__ARM_mve_coerce(__p0, float32x4_t),
>> __ARM_mve_coerce(__p1, float32x4_t)), \
>> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
>> __ARM_mve_coerce3(p1, int)), \
>> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
>> __ARM_mve_coerce3(p1, int)), \
>> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
>> __ARM_mve_coerce3(p1, int)), \
>> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
>> __ARM_mve_coerce3(p1, int)), \
>> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
>> __ARM_mve_coerce3(p1, int)), \
>> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
>> __ARM_mve_coerce3(p1, int)), \
>> int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
>> __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
>> __ARM_mve_coerce2(__p1, double)), \
>> int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
>> __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
>> __ARM_mve_coerce2(__p1, double)));})
>>
>> @@ -37316,12 +37318,12 @@ extern void *__ARM_undef;
>> int
>> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
>> ve_type_uint32x4_t]: __arm_vaddq_m_u32 (__ARM_mve_coerce(__p0,
>> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
>> __ARM_mve_coerce(__p2, uint32x4_t), p3), \
>> int
>> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
>> mve_type_float16x8_t]: __arm_vaddq_m_f16 (__ARM_mve_coerce(__p0,
>> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
>> __ARM_mve_coerce(__p2, float16x8_t), p3), \
>> int
>> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
>> mve_type_float32x4_t]: __arm_vaddq_m_f32 (__ARM_mve_coerce(__p0,
>> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
>> __ARM_mve_coerce(__p2, float32x4_t), p3), \
>> - int
>> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
>> _type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
>> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int), p3), \
>> - int
>> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
>> _type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0,
>> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
>> int), p3), \
>> - int
>> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
>> _type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0,
>> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
>> int), p3), \
>> - int
>> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
>> ve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0,
>> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
>> __ARM_mve_coerce(__p2, int), p3), \
>> - int
>> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
>> ve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0,
>> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
>> __ARM_mve_coerce(__p2, int), p3), \
>> - int
>> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
>> ve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0,
>> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
>> __ARM_mve_coerce(__p2, int), p3), \
>> + int
>> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
>> _type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
>> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
>> + int
>> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
>> _type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0,
>> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
>> int), p3), \
>> + int
>> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
>> _type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0,
>> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
>> int), p3), \
>> + int
>> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
>> ve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0,
>> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
>> __ARM_mve_coerce3(p2, int), p3), \
>> + int
>> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
>> ve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0,
>> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
>> __ARM_mve_coerce3(p2, int), p3), \
>> + int
>> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
>> ve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0,
>> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
>> __ARM_mve_coerce3(p2, int), p3), \
>> int
>> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
>> mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0,
>> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
>> __ARM_mve_coerce2(__p2, double), p3), \
>> int
>> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
>> mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0,
>> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
>> __ARM_mve_coerce2(__p2, double), p3));})
>>
>> @@ -38820,12 +38822,12 @@ extern void *__ARM_undef;
>> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
>> __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
>> __ARM_mve_coerce(__p1, uint8x16_t)), \
>> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
>> __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
>> __ARM_mve_coerce(__p1, uint16x8_t)), \
>> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
>> __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
>> __ARM_mve_coerce(__p1, uint32x4_t)), \
>> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
>> __ARM_mve_coerce(__p1, int)), \
>> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
>> __ARM_mve_coerce(__p1, int)), \
>> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
>> __ARM_mve_coerce(__p1, int)), \
>> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
>> __ARM_mve_coerce(__p1, int)), \
>> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
>> __ARM_mve_coerce(__p1, int)), \
>> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
>> __ARM_mve_coerce(__p1, int)));})
>> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
>> __ARM_mve_coerce3(p1, int)), \
>> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
>> __ARM_mve_coerce3(p1, int)), \
>> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
>> __ARM_mve_coerce3(p1, int)), \
>> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
>> __ARM_mve_coerce3(p1, int)), \
>> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
>> __ARM_mve_coerce3(p1, int)), \
>> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
>> __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
>> __ARM_mve_coerce3(p1, int)));})
>>
>> #define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
>> __typeof(p1) __p1 = (p1); \
>> @@ -39641,12 +39643,12 @@ extern void *__ARM_undef;
>> __typeof(p1) __p1 = (p1); \
>> __typeof(p2) __p2 = (p2); \
>> _Generic( (int
>> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
>> eid(__p2)])0, \
>> - int
>> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
>> _type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
>> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int), p3), \
>> - int
>> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
>> _type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0,
>> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
>> int), p3), \
>> - int
>> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
>> _type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0,
>> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
>> int), p3), \
>> - int
>> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
>> ve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0,
>> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
>> __ARM_mve_coerce(__p2, int), p3), \
>> - int
>> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
>> ve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0,
>> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
>> __ARM_mve_coerce(__p2, int), p3), \
>> - int
>> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
>> ve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0,
>> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
>> __ARM_mve_coerce(__p2, int), p3), \
>> + int
>> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
>> _type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
>> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
>> + int
>> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
>> _type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0,
>> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
>> int), p3), \
>> + int
>> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
>> _type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0,
>> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
>> int), p3), \
>> + int
>> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
>> ve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0,
>> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
>> __ARM_mve_coerce3(p2, int), p3), \
>> + int
>> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
>> ve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0,
>> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
>> __ARM_mve_coerce3(p2, int), p3), \
>> + int
>> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
>> ve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0,
>> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
>> __ARM_mve_coerce3(p2, int), p3), \
>> int
>> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
>> _type_int8x16_t]: __arm_vaddq_m_s8 (__ARM_mve_coerce(__p0,
>> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2,
>> int8x16_t), p3), \
>> int
>> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
>> _type_int16x8_t]: __arm_vaddq_m_s16 (__ARM_mve_coerce(__p0,
>> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
>> int16x8_t), p3), \
>> int
>> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
>> _type_int32x4_t]: __arm_vaddq_m_s32 (__ARM_mve_coerce(__p0,
>> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
>> int32x4_t), p3), \
>> --
>> 2.25.1
next prev parent reply other threads:[~2022-11-21 10:46 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-17 16:37 [PATCH 00/35] arm: rework MVE testsuite and rework backend where necessary (1st chunk) Andrea Corallo
2022-11-17 16:37 ` [PATCH 01/35] arm: improve vcreateq* tests Andrea Corallo
2022-11-18 9:47 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 02/35] arm: fix 'vmsr' spacing and register capitalization Andrea Corallo
2022-11-18 16:33 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 03/35] arm: improve tests and fix vddupq* Andrea Corallo
2022-11-18 16:34 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 04/35] arm: improve tests and fix vdwdupq* Andrea Corallo
2022-11-18 16:35 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 05/35] arm: improve vidupq* tests Andrea Corallo
2022-11-18 16:36 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 06/35] arm: improve tests and fix vdupq* Andrea Corallo
2022-11-18 16:37 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 07/35] arm: improve tests and fix vcmp* Andrea Corallo
2022-11-18 16:40 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 08/35] arm: improve tests for vmin* Andrea Corallo
2022-11-18 16:41 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 09/35] arm: improve tests for vmax* Andrea Corallo
2022-11-18 16:42 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 10/35] arm: improve tests for vabavq* Andrea Corallo
2022-11-18 16:43 ` Kyrylo Tkachov
2022-11-21 14:49 ` Andrea Corallo
2022-11-17 16:37 ` [PATCH 11/35] arm: improve tests for vabdq* Andrea Corallo
2022-11-18 16:44 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 12/35] arm: improve tests and fix vabsq* Andrea Corallo
2022-11-18 16:45 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 13/35] arm: further fix overloading of MVE vaddq[_m]_n intrinsic Andrea Corallo
2022-11-18 16:49 ` Kyrylo Tkachov
2022-11-21 10:45 ` Stam Markianos-Wright [this message]
2022-11-17 16:37 ` [PATCH 14/35] arm: propagate fixed overloading of MVE intrinsic scalar parameters Andrea Corallo
2022-11-18 16:51 ` Kyrylo Tkachov
2022-11-21 10:46 ` Stam Markianos-Wright
2022-11-17 16:37 ` [PATCH 15/35] arm: Explicitly specify other float types for _Generic overloading [PR107515] Andrea Corallo
2022-11-18 16:58 ` Kyrylo Tkachov
2022-11-20 22:49 ` Ramana Radhakrishnan
2022-11-21 14:11 ` Stam Markianos-Wright
2022-11-21 10:45 ` Stam Markianos-Wright
2022-11-17 16:37 ` [PATCH 16/35] arm: Add integer vector overloading of vsubq_x instrinsic Andrea Corallo
2022-11-22 10:00 ` Christophe Lyon
2022-11-22 10:54 ` Andrea Corallo
2022-11-22 16:48 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 17/35] arm: improve tests and fix vadd* Andrea Corallo
2022-11-22 16:49 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 18/35] arm: improve tests for vmulq* Andrea Corallo
2022-11-22 16:51 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 19/35] arm: improve tests and fix vsubq* Andrea Corallo
2022-11-22 16:51 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 20/35] arm: improve tests for vfmasq_m* Andrea Corallo
2022-11-22 16:52 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 21/35] arm: improve tests for vhaddq_m* Andrea Corallo
2022-11-22 16:53 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 22/35] arm: improve tests for vhsubq_m* Andrea Corallo
2022-11-22 16:53 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 23/35] arm: improve tests for viwdupq* Andrea Corallo
2022-11-22 16:54 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 24/35] arm: improve tests for vmladavaq* Andrea Corallo
2022-11-22 16:54 ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 25/35] arm: improve tests and fix vmlaldavaxq* Andrea Corallo
2022-11-22 16:56 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 26/35] arm: improve tests for vmlasq* Andrea Corallo
2022-11-22 16:56 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 27/35] arm: improve tests for vqaddq_m* Andrea Corallo
2022-11-22 16:57 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 28/35] arm: improve tests for vqdmlahq_m* Andrea Corallo
2022-11-22 16:57 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 29/35] arm: improve tests for vqdmul* Andrea Corallo
2022-11-22 16:58 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 30/35] arm: improve tests for vqrdmlahq* Andrea Corallo
2022-11-22 17:01 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 31/35] arm: improve tests for vqrdmlashq_m* Andrea Corallo
2022-11-22 17:02 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 32/35] arm: improve tests for vqsubq* Andrea Corallo
2022-11-22 17:03 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 33/35] arm: improve tests and fix vrmlaldavhaq* Andrea Corallo
2022-11-22 17:03 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 34/35] arm: improve tests for vrshlq* Andrea Corallo
2022-11-22 17:04 ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 35/35] arm: improve tests for vsetq_lane* Andrea Corallo
2022-11-22 17:06 ` Kyrylo Tkachov
2022-11-24 14:43 ` [PATCH 35/35 V2] " Andrea Corallo
2022-11-24 15:28 ` Kyrylo Tkachov
2022-11-28 9:20 ` [PATCH 00/35] arm: rework MVE testsuite and rework backend where necessary (1st chunk) Andrea Corallo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=dd22a8f0-d97d-98a0-9d91-68239e7e989f@arm.com \
--to=stam.markianos-wright@arm.com \
--cc=Andrea.Corallo@arm.com \
--cc=Kyrylo.Tkachov@arm.com \
--cc=Richard.Earnshaw@arm.com \
--cc=gcc-patches@gcc.gnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).