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From: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
To: Andrea Corallo <Andrea.Corallo@arm.com>,
	"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>,
	Andrea Corallo <Andrea.Corallo@arm.com>
Subject: RE: [PATCH 35/35] arm: improve tests for vsetq_lane*
Date: Tue, 22 Nov 2022 17:06:10 +0000	[thread overview]
Message-ID: <PAXPR08MB69261695B4748D6046FAF975930D9@PAXPR08MB6926.eurprd08.prod.outlook.com> (raw)
In-Reply-To: <20221117163809.1009526-36-andrea.corallo@arm.com>



> -----Original Message-----
> From: Andrea Corallo <andrea.corallo@arm.com>
> Sent: Thursday, November 17, 2022 4:38 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; Andrea Corallo <Andrea.Corallo@arm.com>
> Subject: [PATCH 35/35] arm: improve tests for vsetq_lane*
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c: Improve test.
> 	* gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c: Likewise.
> 	* gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c: Likewise.
> 	* gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c: Likewise.
> 	* gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c: Likewise.
> 	* gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c: Likewise.
> 	* gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c: Likewise.
> 	* gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c: Likewise.
> 	* gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c: Likewise.
> 	* gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c: Likewise.
> ---
>  .../arm/mve/intrinsics/vsetq_lane_f16.c       | 36 +++++++++++++++--
>  .../arm/mve/intrinsics/vsetq_lane_f32.c       | 36 +++++++++++++++--
>  .../arm/mve/intrinsics/vsetq_lane_s16.c       | 24 ++++++++++--
>  .../arm/mve/intrinsics/vsetq_lane_s32.c       | 24 ++++++++++--
>  .../arm/mve/intrinsics/vsetq_lane_s64.c       | 27 ++++++++++---
>  .../arm/mve/intrinsics/vsetq_lane_s8.c        | 24 ++++++++++--
>  .../arm/mve/intrinsics/vsetq_lane_u16.c       | 36 +++++++++++++++--
>  .../arm/mve/intrinsics/vsetq_lane_u32.c       | 36 +++++++++++++++--
>  .../arm/mve/intrinsics/vsetq_lane_u64.c       | 39 ++++++++++++++++---
>  .../arm/mve/intrinsics/vsetq_lane_u8.c        | 36 +++++++++++++++--
>  10 files changed, 284 insertions(+), 34 deletions(-)
> 
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c
> index e03e9620528..b5c9f4d5eb8 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c
> @@ -1,15 +1,45 @@
> -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
>  /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
>  /* { dg-add-options arm_v8_1m_mve_fp } */
>  /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> 
>  #include "arm_mve.h"
> 
> +/*
> +**foo:
> +**	...
> +**	vmov.16	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
>  float16x8_t
>  foo (float16_t a, float16x8_t b)
>  {
> -    return vsetq_lane_f16 (a, b, 0);
> +  return vsetq_lane_f16 (a, b, 1);
>  }
> 

Hmm, for these tests we should be able to scan for more specific codegen as we're setting individual lanes, so we should be able to scan for lane 1 in the vmov instruction, though it may need to be flipped for big-endian.
Thanks,
Kyrill

> -/* { dg-final { scan-assembler "vmov.16"  }  } */
> 
> +/*
> +**foo1:
> +**	...
> +**	vmov.16	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
> +float16x8_t
> +foo1 (float16_t a, float16x8_t b)
> +{
> +  return vsetq_lane (a, b, 1);
> +}
> +
> +/*
> +**foo2:
> +**	...
> +**	vmov.16	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
> +float16x8_t
> +foo2 (float16x8_t b)
> +{
> +  return vsetq_lane (1.1, b, 1);
> +}
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c
> index 2b9f1a7e627..211083ce5d4 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c
> @@ -1,15 +1,45 @@
> -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
>  /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
>  /* { dg-add-options arm_v8_1m_mve_fp } */
>  /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> 
>  #include "arm_mve.h"
> 
> +/*
> +**foo:
> +**	...
> +**	vmov.32	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
>  float32x4_t
>  foo (float32_t a, float32x4_t b)
>  {
> -    return vsetq_lane_f32 (a, b, 0);
> +  return vsetq_lane_f32 (a, b, 1);
>  }
> 
> -/* { dg-final { scan-assembler "vmov.32"  }  } */
> 
> +/*
> +**foo1:
> +**	...
> +**	vmov.32	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
> +float32x4_t
> +foo1 (float32_t a, float32x4_t b)
> +{
> +  return vsetq_lane (a, b, 1);
> +}
> +
> +/*
> +**foo2:
> +**	...
> +**	vmov.32	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
> +float32x4_t
> +foo2 (float32x4_t b)
> +{
> +  return vsetq_lane (1.1, b, 1);
> +}
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c
> index 92ad0dd16a8..9cdaeae1e74 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c
> @@ -1,15 +1,33 @@
> -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
>  /* { dg-require-effective-target arm_v8_1m_mve_ok } */
>  /* { dg-add-options arm_v8_1m_mve } */
>  /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> 
>  #include "arm_mve.h"
> 
> +/*
> +**foo:
> +**	...
> +**	vmov.16	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
>  int16x8_t
>  foo (int16_t a, int16x8_t b)
>  {
> -    return vsetq_lane_s16 (a, b, 0);
> +  return vsetq_lane_s16 (a, b, 1);
>  }
> 
> -/* { dg-final { scan-assembler "vmov.16"  }  } */
> 
> +/*
> +**foo1:
> +**	...
> +**	vmov.16	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
> +int16x8_t
> +foo1 (int16_t a, int16x8_t b)
> +{
> +  return vsetq_lane (a, b, 1);
> +}
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c
> index e60c8f26700..edd06bce1bd 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c
> @@ -1,15 +1,33 @@
> -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
>  /* { dg-require-effective-target arm_v8_1m_mve_ok } */
>  /* { dg-add-options arm_v8_1m_mve } */
>  /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> 
>  #include "arm_mve.h"
> 
> +/*
> +**foo:
> +**	...
> +**	vmov.32	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
>  int32x4_t
>  foo (int32_t a, int32x4_t b)
>  {
> -    return vsetq_lane_s32 (a, b, 0);
> +  return vsetq_lane_s32 (a, b, 1);
>  }
> 
> -/* { dg-final { scan-assembler "vmov.32"  }  } */
> 
> +/*
> +**foo1:
> +**	...
> +**	vmov.32	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
> +int32x4_t
> +foo1 (int32_t a, int32x4_t b)
> +{
> +  return vsetq_lane (a, b, 1);
> +}
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c
> index 430df669f2a..95ba4da1f51 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c
> @@ -1,16 +1,33 @@
> -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
> -/* { dg-require-effective-target arm_hard_ok } */
>  /* { dg-require-effective-target arm_v8_1m_mve_ok } */
>  /* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-mfloat-abi=hard -O2" } */
> +/* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> 
>  #include "arm_mve.h"
> 
> +/*
> +**foo:
> +**	...
> +**	vmov	d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
>  int64x2_t
>  foo (int64_t a, int64x2_t b)
>  {
> -    return vsetq_lane_s64 (a, b, 0);
> +  return vsetq_lane_s64 (a, b, 1);
>  }
> 
> -/* { dg-final { scan-assembler {vmov\td0, r[1-9]*[0-9], r[1-9]*[0-9]}  }  } */
> 
> +/*
> +**foo1:
> +**	...
> +**	vmov	d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
> +int64x2_t
> +foo1 (int64_t a, int64x2_t b)
> +{
> +  return vsetq_lane (a, b, 1);
> +}
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c
> index d8ccbb524fd..f5bf0dd663b 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c
> @@ -1,15 +1,33 @@
> -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
>  /* { dg-require-effective-target arm_v8_1m_mve_ok } */
>  /* { dg-add-options arm_v8_1m_mve } */
>  /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> 
>  #include "arm_mve.h"
> 
> +/*
> +**foo:
> +**	...
> +**	vmov.8	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
>  int8x16_t
>  foo (int8_t a, int8x16_t b)
>  {
> -    return vsetq_lane_s8 (a, b, 0);
> +  return vsetq_lane_s8 (a, b, 1);
>  }
> 
> -/* { dg-final { scan-assembler "vmov.8"  }  } */
> 
> +/*
> +**foo1:
> +**	...
> +**	vmov.8	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
> +int8x16_t
> +foo1 (int8_t a, int8x16_t b)
> +{
> +  return vsetq_lane (a, b, 1);
> +}
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c
> index 156a5d1de1b..33944dcbd45 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c
> @@ -1,15 +1,45 @@
> -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
>  /* { dg-require-effective-target arm_v8_1m_mve_ok } */
>  /* { dg-add-options arm_v8_1m_mve } */
>  /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> 
>  #include "arm_mve.h"
> 
> +/*
> +**foo:
> +**	...
> +**	vmov.16	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
>  uint16x8_t
>  foo (uint16_t a, uint16x8_t b)
>  {
> -    return vsetq_lane_u16 (a, b, 0);
> +  return vsetq_lane_u16 (a, b, 1);
>  }
> 
> -/* { dg-final { scan-assembler "vmov.16"  }  } */
> 
> +/*
> +**foo1:
> +**	...
> +**	vmov.16	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
> +uint16x8_t
> +foo1 (uint16_t a, uint16x8_t b)
> +{
> +  return vsetq_lane (a, b, 1);
> +}
> +
> +/*
> +**foo2:
> +**	...
> +**	vmov.16	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
> +uint16x8_t
> +foo2 (uint16x8_t b)
> +{
> +  return vsetq_lane (1, b, 1);
> +}
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c
> index e9575483cc9..8f9a3a78cc5 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c
> @@ -1,15 +1,45 @@
> -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
>  /* { dg-require-effective-target arm_v8_1m_mve_ok } */
>  /* { dg-add-options arm_v8_1m_mve } */
>  /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> 
>  #include "arm_mve.h"
> 
> +/*
> +**foo:
> +**	...
> +**	vmov.32	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
>  uint32x4_t
>  foo (uint32_t a, uint32x4_t b)
>  {
> -    return vsetq_lane_u32 (a, b, 0);
> +  return vsetq_lane_u32 (a, b, 1);
>  }
> 
> -/* { dg-final { scan-assembler "vmov.32"  }  } */
> 
> +/*
> +**foo1:
> +**	...
> +**	vmov.32	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
> +uint32x4_t
> +foo1 (uint32_t a, uint32x4_t b)
> +{
> +  return vsetq_lane (a, b, 1);
> +}
> +
> +/*
> +**foo2:
> +**	...
> +**	vmov.32	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
> +uint32x4_t
> +foo2 (uint32x4_t b)
> +{
> +  return vsetq_lane (1, b, 1);
> +}
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c
> index 0e040121cf0..5ce4c544c25 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c
> @@ -1,16 +1,45 @@
> -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
> -/* { dg-require-effective-target arm_hard_ok } */
>  /* { dg-require-effective-target arm_v8_1m_mve_ok } */
>  /* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-mfloat-abi=hard -O2" } */
> +/* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> 
>  #include "arm_mve.h"
> 
> +/*
> +**foo:
> +**	...
> +**	vmov	d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
>  uint64x2_t
>  foo (uint64_t a, uint64x2_t b)
>  {
> -    return vsetq_lane_u64 (a, b, 0);
> +  return vsetq_lane_u64 (a, b, 1);
>  }
> 
> -/* { dg-final { scan-assembler {vmov\td0, r[1-9]*[0-9], r[1-9]*[0-9]}  }  } */
> 
> +/*
> +**foo1:
> +**	...
> +**	vmov	d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
> +uint64x2_t
> +foo1 (uint64_t a, uint64x2_t b)
> +{
> +  return vsetq_lane (a, b, 1);
> +}
> +
> +/*
> +**foo2:
> +**	...
> +**	vmov	d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
> +uint64x2_t
> +foo2 (uint64x2_t b)
> +{
> +  return vsetq_lane (1, b, 1);
> +}
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c
> index 668b3fea953..d37021c91b0 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c
> @@ -1,15 +1,45 @@
> -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
>  /* { dg-require-effective-target arm_v8_1m_mve_ok } */
>  /* { dg-add-options arm_v8_1m_mve } */
>  /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> 
>  #include "arm_mve.h"
> 
> +/*
> +**foo:
> +**	...
> +**	vmov.8	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
>  uint8x16_t
>  foo (uint8_t a, uint8x16_t b)
>  {
> -    return vsetq_lane_u8 (a, b, 0);
> +  return vsetq_lane_u8 (a, b, 1);
>  }
> 
> -/* { dg-final { scan-assembler "vmov.8"  }  } */
> 
> +/*
> +**foo1:
> +**	...
> +**	vmov.8	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
> +uint8x16_t
> +foo1 (uint8_t a, uint8x16_t b)
> +{
> +  return vsetq_lane (a, b, 1);
> +}
> +
> +/*
> +**foo2:
> +**	...
> +**	vmov.8	q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +*/
> +uint8x16_t
> +foo2 (uint8x16_t b)
> +{
> +  return vsetq_lane (1, b, 1);
> +}
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> --
> 2.25.1


  reply	other threads:[~2022-11-22 17:06 UTC|newest]

Thread overview: 82+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-17 16:37 [PATCH 00/35] arm: rework MVE testsuite and rework backend where necessary (1st chunk) Andrea Corallo
2022-11-17 16:37 ` [PATCH 01/35] arm: improve vcreateq* tests Andrea Corallo
2022-11-18  9:47   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 02/35] arm: fix 'vmsr' spacing and register capitalization Andrea Corallo
2022-11-18 16:33   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 03/35] arm: improve tests and fix vddupq* Andrea Corallo
2022-11-18 16:34   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 04/35] arm: improve tests and fix vdwdupq* Andrea Corallo
2022-11-18 16:35   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 05/35] arm: improve vidupq* tests Andrea Corallo
2022-11-18 16:36   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 06/35] arm: improve tests and fix vdupq* Andrea Corallo
2022-11-18 16:37   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 07/35] arm: improve tests and fix vcmp* Andrea Corallo
2022-11-18 16:40   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 08/35] arm: improve tests for vmin* Andrea Corallo
2022-11-18 16:41   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 09/35] arm: improve tests for vmax* Andrea Corallo
2022-11-18 16:42   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 10/35] arm: improve tests for vabavq* Andrea Corallo
2022-11-18 16:43   ` Kyrylo Tkachov
2022-11-21 14:49     ` Andrea Corallo
2022-11-17 16:37 ` [PATCH 11/35] arm: improve tests for vabdq* Andrea Corallo
2022-11-18 16:44   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 12/35] arm: improve tests and fix vabsq* Andrea Corallo
2022-11-18 16:45   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 13/35] arm: further fix overloading of MVE vaddq[_m]_n intrinsic Andrea Corallo
2022-11-18 16:49   ` Kyrylo Tkachov
2022-11-21 10:45     ` Stam Markianos-Wright
2022-11-17 16:37 ` [PATCH 14/35] arm: propagate fixed overloading of MVE intrinsic scalar parameters Andrea Corallo
2022-11-18 16:51   ` Kyrylo Tkachov
2022-11-21 10:46     ` Stam Markianos-Wright
2022-11-17 16:37 ` [PATCH 15/35] arm: Explicitly specify other float types for _Generic overloading [PR107515] Andrea Corallo
2022-11-18 16:58   ` Kyrylo Tkachov
2022-11-20 22:49     ` Ramana Radhakrishnan
2022-11-21 14:11       ` Stam Markianos-Wright
2022-11-21 10:45     ` Stam Markianos-Wright
2022-11-17 16:37 ` [PATCH 16/35] arm: Add integer vector overloading of vsubq_x instrinsic Andrea Corallo
2022-11-22 10:00   ` Christophe Lyon
2022-11-22 10:54     ` Andrea Corallo
2022-11-22 16:48   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 17/35] arm: improve tests and fix vadd* Andrea Corallo
2022-11-22 16:49   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 18/35] arm: improve tests for vmulq* Andrea Corallo
2022-11-22 16:51   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 19/35] arm: improve tests and fix vsubq* Andrea Corallo
2022-11-22 16:51   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 20/35] arm: improve tests for vfmasq_m* Andrea Corallo
2022-11-22 16:52   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 21/35] arm: improve tests for vhaddq_m* Andrea Corallo
2022-11-22 16:53   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 22/35] arm: improve tests for vhsubq_m* Andrea Corallo
2022-11-22 16:53   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 23/35] arm: improve tests for viwdupq* Andrea Corallo
2022-11-22 16:54   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 24/35] arm: improve tests for vmladavaq* Andrea Corallo
2022-11-22 16:54   ` Kyrylo Tkachov
2022-11-17 16:37 ` [PATCH 25/35] arm: improve tests and fix vmlaldavaxq* Andrea Corallo
2022-11-22 16:56   ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 26/35] arm: improve tests for vmlasq* Andrea Corallo
2022-11-22 16:56   ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 27/35] arm: improve tests for vqaddq_m* Andrea Corallo
2022-11-22 16:57   ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 28/35] arm: improve tests for vqdmlahq_m* Andrea Corallo
2022-11-22 16:57   ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 29/35] arm: improve tests for vqdmul* Andrea Corallo
2022-11-22 16:58   ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 30/35] arm: improve tests for vqrdmlahq* Andrea Corallo
2022-11-22 17:01   ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 31/35] arm: improve tests for vqrdmlashq_m* Andrea Corallo
2022-11-22 17:02   ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 32/35] arm: improve tests for vqsubq* Andrea Corallo
2022-11-22 17:03   ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 33/35] arm: improve tests and fix vrmlaldavhaq* Andrea Corallo
2022-11-22 17:03   ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 34/35] arm: improve tests for vrshlq* Andrea Corallo
2022-11-22 17:04   ` Kyrylo Tkachov
2022-11-17 16:38 ` [PATCH 35/35] arm: improve tests for vsetq_lane* Andrea Corallo
2022-11-22 17:06   ` Kyrylo Tkachov [this message]
2022-11-24 14:43     ` [PATCH 35/35 V2] " Andrea Corallo
2022-11-24 15:28       ` Kyrylo Tkachov
2022-11-28  9:20 ` [PATCH 00/35] arm: rework MVE testsuite and rework backend where necessary (1st chunk) Andrea Corallo

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