* [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
@ 2023-06-06 12:36 pan2.li
2023-06-06 14:07 ` 钟居哲
` (9 more replies)
0 siblings, 10 replies; 39+ messages in thread
From: pan2.li @ 2023-06-06 12:36 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, yanzhang.wang
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the ZVFHMIN implementation by
separated iterator and pattern. Thus, we can tell the sub extension
between the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Move ZVFHMIN related
items to separated iterators.
* config/riscv/vector.md (@pred_extend<mode>): New pattern for
the ZVFHMIN instruction.
(@pred_trunc<mode>): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md | 28 ++++++++-----
gcc/config/riscv/vector.md | 40 +++++++++++++++++++
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 ++++++++++++
3 files changed, 83 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..986195489f2 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -497,13 +497,6 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
-
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
(VNx4DF "TARGET_VECTOR_ELEN_FP_64")
@@ -511,6 +504,15 @@ (define_mode_iterator VWEXTF [
(VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator V_ZVFHMIN_SF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VWCONVERTI [
(VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
(VNx2SI "TARGET_VECTOR_ELEN_FP_16")
@@ -1175,12 +1177,19 @@ (define_mode_attr V_DOUBLE_TRUNC [
(VNx16SI "VNx16HI") (VNx32SI "VNx32HI")
(VNx1DI "VNx1SI") (VNx2DI "VNx2SI") (VNx4DI "VNx4SI") (VNx8DI "VNx8SI")
(VNx16DI "VNx16SI")
-
- (VNx1SF "VNx1HF") (VNx2SF "VNx2HF") (VNx4SF "VNx4HF") (VNx8SF "VNx8HF") (VNx16SF "VNx16HF") (VNx32SF "VNx32HF")
(VNx1DF "VNx1SF") (VNx2DF "VNx2SF") (VNx4DF "VNx4SF") (VNx8DF "VNx8SF")
(VNx16DF "VNx16SF")
])
+(define_mode_attr V_ZVFHMIN [
+ (VNx1SF "VNx1HF")
+ (VNx2SF "VNx2HF")
+ (VNx4SF "VNx4HF")
+ (VNx8SF "VNx8HF")
+ (VNx16SF "VNx16HF")
+ (VNx32SF "VNx32HF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
(VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
(VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
@@ -1201,7 +1210,6 @@ (define_mode_attr v_double_trunc [
(VNx16SI "vnx16hi") (VNx32SI "vnx32hi")
(VNx1DI "vnx1si") (VNx2DI "vnx2si") (VNx4DI "vnx4si") (VNx8DI "vnx8si")
(VNx16DI "vnx16si")
- (VNx1SF "vnx1hf") (VNx2SF "vnx2hf") (VNx4SF "vnx4hf") (VNx8SF "vnx8hf") (VNx16SF "vnx16hf") (VNx32SF "vnx32hf")
(VNx1DF "vnx1sf") (VNx2DF "vnx2sf") (VNx4DF "vnx4sf") (VNx8DF "vnx8sf")
(VNx16DF "vnx16sf")
])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..b498669b874 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7124,6 +7124,25 @@ (define_insn "@pred_extend<mode>"
[(set_attr "type" "vfwcvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
+(define_insn "@pred_extend<mode>"
+ [(set (match_operand:V_ZVFHMIN_SF 0 "register_operand" "=&vr, &vr")
+ (if_then_else:V_ZVFHMIN_SF
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (float_extend:V_ZVFHMIN_SF
+ (match_operand:<V_ZVFHMIN> 3 "register_operand" " vr, vr"))
+ (match_operand:V_ZVFHMIN_SF 2 "vector_merge_operand" " vu, 0")))]
+ "TARGET_VECTOR"
+ "vfwcvt.f.f.v\t%0,%3%p1"
+ [(set_attr "type" "vfwcvtftof")
+ (set_attr "mode" "<V_ZVFHMIN>")])
+
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
;; -------------------------------------------------------------------------------
@@ -7213,6 +7232,27 @@ (define_insn "@pred_trunc<mode>"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
+(define_insn "@pred_trunc<mode>"
+ [(set (match_operand:<V_ZVFHMIN> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
+ (if_then_else:<V_ZVFHMIN>
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+ (float_truncate:<V_ZVFHMIN>
+ (match_operand:V_ZVFHMIN_SF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
+ (match_operand:<V_ZVFHMIN> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
+ "TARGET_VECTOR"
+ "vfncvt.f.f.w\t%0,%3%p1"
+ [(set_attr "type" "vfncvtftof")
+ (set_attr "mode" "<V_ZVFHMIN>")])
+
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
(if_then_else:<V_DOUBLE_TRUNC>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
2023-06-06 12:36 [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern pan2.li
@ 2023-06-06 14:07 ` 钟居哲
2023-06-06 14:34 ` Li, Pan2
2023-06-06 15:32 ` [PATCH v2] RISC-V: Refactor requirement of ZVFH and ZVFHMIN pan2.li
` (8 subsequent siblings)
9 siblings, 1 reply; 39+ messages in thread
From: 钟居哲 @ 2023-06-06 14:07 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: kito.cheng, pan2.li, yanzhang.wang
[-- Attachment #1: Type: text/plain, Size: 8924 bytes --]
+(define_mode_iterator V_ZVFHMIN_SF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN >= 128")
+])
why not just use "TARGET_VECTOR_ELEN_FP_16"
instead of TARGET_ZVFH || TARGET_ZVFHMIN ?
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-06-06 20:36
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the ZVFHMIN implementation by
separated iterator and pattern. Thus, we can tell the sub extension
between the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Move ZVFHMIN related
items to separated iterators.
* config/riscv/vector.md (@pred_extend<mode>): New pattern for
the ZVFHMIN instruction.
(@pred_trunc<mode>): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md | 28 ++++++++-----
gcc/config/riscv/vector.md | 40 +++++++++++++++++++
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 ++++++++++++
3 files changed, 83 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..986195489f2 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -497,13 +497,6 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
-
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
(VNx4DF "TARGET_VECTOR_ELEN_FP_64")
@@ -511,6 +504,15 @@ (define_mode_iterator VWEXTF [
(VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator V_ZVFHMIN_SF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VWCONVERTI [
(VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
(VNx2SI "TARGET_VECTOR_ELEN_FP_16")
@@ -1175,12 +1177,19 @@ (define_mode_attr V_DOUBLE_TRUNC [
(VNx16SI "VNx16HI") (VNx32SI "VNx32HI")
(VNx1DI "VNx1SI") (VNx2DI "VNx2SI") (VNx4DI "VNx4SI") (VNx8DI "VNx8SI")
(VNx16DI "VNx16SI")
-
- (VNx1SF "VNx1HF") (VNx2SF "VNx2HF") (VNx4SF "VNx4HF") (VNx8SF "VNx8HF") (VNx16SF "VNx16HF") (VNx32SF "VNx32HF")
(VNx1DF "VNx1SF") (VNx2DF "VNx2SF") (VNx4DF "VNx4SF") (VNx8DF "VNx8SF")
(VNx16DF "VNx16SF")
])
+(define_mode_attr V_ZVFHMIN [
+ (VNx1SF "VNx1HF")
+ (VNx2SF "VNx2HF")
+ (VNx4SF "VNx4HF")
+ (VNx8SF "VNx8HF")
+ (VNx16SF "VNx16HF")
+ (VNx32SF "VNx32HF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
(VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
(VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
@@ -1201,7 +1210,6 @@ (define_mode_attr v_double_trunc [
(VNx16SI "vnx16hi") (VNx32SI "vnx32hi")
(VNx1DI "vnx1si") (VNx2DI "vnx2si") (VNx4DI "vnx4si") (VNx8DI "vnx8si")
(VNx16DI "vnx16si")
- (VNx1SF "vnx1hf") (VNx2SF "vnx2hf") (VNx4SF "vnx4hf") (VNx8SF "vnx8hf") (VNx16SF "vnx16hf") (VNx32SF "vnx32hf")
(VNx1DF "vnx1sf") (VNx2DF "vnx2sf") (VNx4DF "vnx4sf") (VNx8DF "vnx8sf")
(VNx16DF "vnx16sf")
])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..b498669b874 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7124,6 +7124,25 @@ (define_insn "@pred_extend<mode>"
[(set_attr "type" "vfwcvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
+(define_insn "@pred_extend<mode>"
+ [(set (match_operand:V_ZVFHMIN_SF 0 "register_operand" "=&vr, &vr")
+ (if_then_else:V_ZVFHMIN_SF
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (float_extend:V_ZVFHMIN_SF
+ (match_operand:<V_ZVFHMIN> 3 "register_operand" " vr, vr"))
+ (match_operand:V_ZVFHMIN_SF 2 "vector_merge_operand" " vu, 0")))]
+ "TARGET_VECTOR"
+ "vfwcvt.f.f.v\t%0,%3%p1"
+ [(set_attr "type" "vfwcvtftof")
+ (set_attr "mode" "<V_ZVFHMIN>")])
+
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
;; -------------------------------------------------------------------------------
@@ -7213,6 +7232,27 @@ (define_insn "@pred_trunc<mode>"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
+(define_insn "@pred_trunc<mode>"
+ [(set (match_operand:<V_ZVFHMIN> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
+ (if_then_else:<V_ZVFHMIN>
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+ (float_truncate:<V_ZVFHMIN>
+ (match_operand:V_ZVFHMIN_SF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
+ (match_operand:<V_ZVFHMIN> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
+ "TARGET_VECTOR"
+ "vfncvt.f.f.w\t%0,%3%p1"
+ [(set_attr "type" "vfncvtftof")
+ (set_attr "mode" "<V_ZVFHMIN>")])
+
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
(if_then_else:<V_DOUBLE_TRUNC>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
2023-06-06 14:07 ` 钟居哲
@ 2023-06-06 14:34 ` Li, Pan2
2023-06-06 15:34 ` Li, Pan2
0 siblings, 1 reply; 39+ messages in thread
From: Li, Pan2 @ 2023-06-06 14:34 UTC (permalink / raw)
To: 钟居哲, gcc-patches; +Cc: kito.cheng, Wang, Yanzhang
[-- Attachment #1: Type: text/plain, Size: 9742 bytes --]
IMO, TARGET_ZVFH || TARGET_ZVFHMIN may be a little readable compares to FP_16, or some context I missed.
Anyway as we discussed offline, will refine this part and add zvfh part in V2.
Pan
From: 钟居哲 <juzhe.zhong@rivai.ai>
Sent: Tuesday, June 6, 2023 10:07 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@sifive.com>; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
+(define_mode_iterator V_ZVFHMIN_SF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN >= 128")
+])
why not just use "TARGET_VECTOR_ELEN_FP_16"
instead of TARGET_ZVFH || TARGET_ZVFHMIN ?
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-06-06 20:36
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@sifive.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
This patch would like to refactor the ZVFHMIN implementation by
separated iterator and pattern. Thus, we can tell the sub extension
between the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Move ZVFHMIN related
items to separated iterators.
* config/riscv/vector.md (@pred_extend<mode>): New pattern for
the ZVFHMIN instruction.
(@pred_trunc<mode>): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md | 28 ++++++++-----
gcc/config/riscv/vector.md | 40 +++++++++++++++++++
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 ++++++++++++
3 files changed, 83 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..986195489f2 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -497,13 +497,6 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
-
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
(VNx4DF "TARGET_VECTOR_ELEN_FP_64")
@@ -511,6 +504,15 @@ (define_mode_iterator VWEXTF [
(VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator V_ZVFHMIN_SF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VWCONVERTI [
(VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
(VNx2SI "TARGET_VECTOR_ELEN_FP_16")
@@ -1175,12 +1177,19 @@ (define_mode_attr V_DOUBLE_TRUNC [
(VNx16SI "VNx16HI") (VNx32SI "VNx32HI")
(VNx1DI "VNx1SI") (VNx2DI "VNx2SI") (VNx4DI "VNx4SI") (VNx8DI "VNx8SI")
(VNx16DI "VNx16SI")
-
- (VNx1SF "VNx1HF") (VNx2SF "VNx2HF") (VNx4SF "VNx4HF") (VNx8SF "VNx8HF") (VNx16SF "VNx16HF") (VNx32SF "VNx32HF")
(VNx1DF "VNx1SF") (VNx2DF "VNx2SF") (VNx4DF "VNx4SF") (VNx8DF "VNx8SF")
(VNx16DF "VNx16SF")
])
+(define_mode_attr V_ZVFHMIN [
+ (VNx1SF "VNx1HF")
+ (VNx2SF "VNx2HF")
+ (VNx4SF "VNx4HF")
+ (VNx8SF "VNx8HF")
+ (VNx16SF "VNx16HF")
+ (VNx32SF "VNx32HF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
(VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
(VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
@@ -1201,7 +1210,6 @@ (define_mode_attr v_double_trunc [
(VNx16SI "vnx16hi") (VNx32SI "vnx32hi")
(VNx1DI "vnx1si") (VNx2DI "vnx2si") (VNx4DI "vnx4si") (VNx8DI "vnx8si")
(VNx16DI "vnx16si")
- (VNx1SF "vnx1hf") (VNx2SF "vnx2hf") (VNx4SF "vnx4hf") (VNx8SF "vnx8hf") (VNx16SF "vnx16hf") (VNx32SF "vnx32hf")
(VNx1DF "vnx1sf") (VNx2DF "vnx2sf") (VNx4DF "vnx4sf") (VNx8DF "vnx8sf")
(VNx16DF "vnx16sf")
])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..b498669b874 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7124,6 +7124,25 @@ (define_insn "@pred_extend<mode>"
[(set_attr "type" "vfwcvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
+(define_insn "@pred_extend<mode>"
+ [(set (match_operand:V_ZVFHMIN_SF 0 "register_operand" "=&vr, &vr")
+ (if_then_else:V_ZVFHMIN_SF
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (float_extend:V_ZVFHMIN_SF
+ (match_operand:<V_ZVFHMIN> 3 "register_operand" " vr, vr"))
+ (match_operand:V_ZVFHMIN_SF 2 "vector_merge_operand" " vu, 0")))]
+ "TARGET_VECTOR"
+ "vfwcvt.f.f.v\t%0,%3%p1"
+ [(set_attr "type" "vfwcvtftof")
+ (set_attr "mode" "<V_ZVFHMIN>")])
+
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
;; -------------------------------------------------------------------------------
@@ -7213,6 +7232,27 @@ (define_insn "@pred_trunc<mode>"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
+(define_insn "@pred_trunc<mode>"
+ [(set (match_operand:<V_ZVFHMIN> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
+ (if_then_else:<V_ZVFHMIN>
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+ (float_truncate:<V_ZVFHMIN>
+ (match_operand:V_ZVFHMIN_SF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
+ (match_operand:<V_ZVFHMIN> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
+ "TARGET_VECTOR"
+ "vfncvt.f.f.w\t%0,%3%p1"
+ [(set_attr "type" "vfncvtftof")
+ (set_attr "mode" "<V_ZVFHMIN>")])
+
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
(if_then_else:<V_DOUBLE_TRUNC>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v2] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-06 12:36 [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern pan2.li
2023-06-06 14:07 ` 钟居哲
@ 2023-06-06 15:32 ` pan2.li
2023-06-07 3:00 ` [PATCH v3] " pan2.li
` (7 subsequent siblings)
9 siblings, 0 replies; 39+ messages in thread
From: pan2.li @ 2023-06-06 15:32 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, yanzhang.wang
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Add requirement to VF,
VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF.
* config/riscv/vector.md: Adjust FP convert to V_CONVERT_F
and VCONVERTF.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md | 68 +++++++++++++------
gcc/config/riscv/vector.md | 46 ++++++-------
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 +++++++
3 files changed, 97 insertions(+), 42 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..16350e1bddb 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [
])
(define_mode_iterator VF [
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
- (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+ (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_ZVFH")
+ (VNx4HF "TARGET_ZVFH")
+ (VNx8HF "TARGET_ZVFH")
+ (VNx16HF "TARGET_ZVFH")
+ (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
@@ -497,12 +497,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_ZVFH")
+ (VNx4SF "TARGET_ZVFH")
+ (VNx8SF "TARGET_ZVFH")
+ (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
@@ -512,12 +512,12 @@ (define_mode_iterator VWEXTF [
])
(define_mode_iterator VWCONVERTI [
- (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
- (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx4SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx8SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
- (VNx32SI "TARGET_MIN_VLEN >= 128 && TARGET_VECTOR_ELEN_FP_16")
+ (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SI "TARGET_ZVFH")
+ (VNx4SI "TARGET_ZVFH")
+ (VNx8SI "TARGET_ZVFH")
+ (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SI "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
@@ -526,6 +526,21 @@ (define_mode_iterator VWCONVERTI [
(VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator VCONVERTF [
+ (VNx1SF "(TARGET_ZVFHMIN || TARGET_ZVFH) && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_ZVFHMIN || TARGET_ZVFH")
+ (VNx4SF "TARGET_ZVFHMIN || TARGET_ZVFH")
+ (VNx8SF "TARGET_ZVFHMIN || TARGET_ZVFH")
+ (VNx16SF "(TARGET_ZVFHMIN || TARGET_ZVFH) && TARGET_MIN_VLEN > 32")
+ (VNx32SF "(TARGET_ZVFHMIN || TARGET_ZVFH) && TARGET_MIN_VLEN >= 128")
+
+ (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
+ (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VQEXTI [
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
@@ -1181,6 +1196,21 @@ (define_mode_attr V_DOUBLE_TRUNC [
(VNx16DF "VNx16SF")
])
+(define_mode_attr V_CONVERT_F [
+ (VNx1SF "VNx1HF")
+ (VNx2SF "VNx2HF")
+ (VNx4SF "VNx4HF")
+ (VNx8SF "VNx8HF")
+ (VNx16SF "VNx16HF")
+ (VNx32SF "VNx32HF")
+
+ (VNx1DF "VNx1SF")
+ (VNx2DF "VNx2SF")
+ (VNx4DF "VNx4SF")
+ (VNx8DF "VNx8SF")
+ (VNx16DF "VNx16SF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
(VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
(VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..97162b07642 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7106,23 +7106,23 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_extend<mode>"
- [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
- (if_then_else:VWEXTF
+ [(set (match_operand:VCONVERTF 0 "register_operand" "=&vr, &vr")
+ (if_then_else:VCONVERTF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
- (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
+ (float_extend:VCONVERTF
+ (match_operand:<V_CONVERT_F> 3 "register_operand" " vr, vr"))
+ (match_operand:VCONVERTF 2 "vector_merge_operand" " vu, 0")))]
"TARGET_VECTOR"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
@@ -7193,25 +7193,25 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_trunc<mode>"
- [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
- (if_then_else:<V_DOUBLE_TRUNC>
+ [(set (match_operand:<V_CONVERT_F> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
+ (if_then_else:<V_CONVERT_F>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
- (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (float_truncate:<V_DOUBLE_TRUNC>
- (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
- (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
+ (float_truncate:<V_CONVERT_F>
+ (match_operand:VCONVERTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
+ (match_operand:<V_CONVERT_F> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
2023-06-06 14:34 ` Li, Pan2
@ 2023-06-06 15:34 ` Li, Pan2
2023-06-07 3:02 ` Li, Pan2
0 siblings, 1 reply; 39+ messages in thread
From: Li, Pan2 @ 2023-06-06 15:34 UTC (permalink / raw)
To: 钟居哲, gcc-patches; +Cc: kito.cheng, Wang, Yanzhang
[-- Attachment #1: Type: text/plain, Size: 10323 bytes --]
Update the PATCH V2 as below.
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620787.html
Pan
From: Li, Pan2
Sent: Tuesday, June 6, 2023 10:34 PM
To: 钟居哲 <juzhe.zhong@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: RE: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
IMO, TARGET_ZVFH || TARGET_ZVFHMIN may be a little readable compares to FP_16, or some context I missed.
Anyway as we discussed offline, will refine this part and add zvfh part in V2.
Pan
From: 钟居哲 <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
Sent: Tuesday, June 6, 2023 10:07 PM
To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>
Cc: kito.cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>; Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
Subject: Re: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
+(define_mode_iterator V_ZVFHMIN_SF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN >= 128")
+])
why not just use "TARGET_VECTOR_ELEN_FP_16"
instead of TARGET_ZVFH || TARGET_ZVFHMIN ?
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-06-06 20:36
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@sifive.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
This patch would like to refactor the ZVFHMIN implementation by
separated iterator and pattern. Thus, we can tell the sub extension
between the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Move ZVFHMIN related
items to separated iterators.
* config/riscv/vector.md (@pred_extend<mode>): New pattern for
the ZVFHMIN instruction.
(@pred_trunc<mode>): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md | 28 ++++++++-----
gcc/config/riscv/vector.md | 40 +++++++++++++++++++
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 ++++++++++++
3 files changed, 83 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..986195489f2 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -497,13 +497,6 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
-
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
(VNx4DF "TARGET_VECTOR_ELEN_FP_64")
@@ -511,6 +504,15 @@ (define_mode_iterator VWEXTF [
(VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator V_ZVFHMIN_SF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VWCONVERTI [
(VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
(VNx2SI "TARGET_VECTOR_ELEN_FP_16")
@@ -1175,12 +1177,19 @@ (define_mode_attr V_DOUBLE_TRUNC [
(VNx16SI "VNx16HI") (VNx32SI "VNx32HI")
(VNx1DI "VNx1SI") (VNx2DI "VNx2SI") (VNx4DI "VNx4SI") (VNx8DI "VNx8SI")
(VNx16DI "VNx16SI")
-
- (VNx1SF "VNx1HF") (VNx2SF "VNx2HF") (VNx4SF "VNx4HF") (VNx8SF "VNx8HF") (VNx16SF "VNx16HF") (VNx32SF "VNx32HF")
(VNx1DF "VNx1SF") (VNx2DF "VNx2SF") (VNx4DF "VNx4SF") (VNx8DF "VNx8SF")
(VNx16DF "VNx16SF")
])
+(define_mode_attr V_ZVFHMIN [
+ (VNx1SF "VNx1HF")
+ (VNx2SF "VNx2HF")
+ (VNx4SF "VNx4HF")
+ (VNx8SF "VNx8HF")
+ (VNx16SF "VNx16HF")
+ (VNx32SF "VNx32HF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
(VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
(VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
@@ -1201,7 +1210,6 @@ (define_mode_attr v_double_trunc [
(VNx16SI "vnx16hi") (VNx32SI "vnx32hi")
(VNx1DI "vnx1si") (VNx2DI "vnx2si") (VNx4DI "vnx4si") (VNx8DI "vnx8si")
(VNx16DI "vnx16si")
- (VNx1SF "vnx1hf") (VNx2SF "vnx2hf") (VNx4SF "vnx4hf") (VNx8SF "vnx8hf") (VNx16SF "vnx16hf") (VNx32SF "vnx32hf")
(VNx1DF "vnx1sf") (VNx2DF "vnx2sf") (VNx4DF "vnx4sf") (VNx8DF "vnx8sf")
(VNx16DF "vnx16sf")
])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..b498669b874 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7124,6 +7124,25 @@ (define_insn "@pred_extend<mode>"
[(set_attr "type" "vfwcvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
+(define_insn "@pred_extend<mode>"
+ [(set (match_operand:V_ZVFHMIN_SF 0 "register_operand" "=&vr, &vr")
+ (if_then_else:V_ZVFHMIN_SF
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (float_extend:V_ZVFHMIN_SF
+ (match_operand:<V_ZVFHMIN> 3 "register_operand" " vr, vr"))
+ (match_operand:V_ZVFHMIN_SF 2 "vector_merge_operand" " vu, 0")))]
+ "TARGET_VECTOR"
+ "vfwcvt.f.f.v\t%0,%3%p1"
+ [(set_attr "type" "vfwcvtftof")
+ (set_attr "mode" "<V_ZVFHMIN>")])
+
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
;; -------------------------------------------------------------------------------
@@ -7213,6 +7232,27 @@ (define_insn "@pred_trunc<mode>"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
+(define_insn "@pred_trunc<mode>"
+ [(set (match_operand:<V_ZVFHMIN> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
+ (if_then_else:<V_ZVFHMIN>
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+ (float_truncate:<V_ZVFHMIN>
+ (match_operand:V_ZVFHMIN_SF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
+ (match_operand:<V_ZVFHMIN> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
+ "TARGET_VECTOR"
+ "vfncvt.f.f.w\t%0,%3%p1"
+ [(set_attr "type" "vfncvtftof")
+ (set_attr "mode" "<V_ZVFHMIN>")])
+
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
(if_then_else:<V_DOUBLE_TRUNC>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-06 12:36 [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern pan2.li
2023-06-06 14:07 ` 钟居哲
2023-06-06 15:32 ` [PATCH v2] RISC-V: Refactor requirement of ZVFH and ZVFHMIN pan2.li
@ 2023-06-07 3:00 ` pan2.li
2023-06-07 4:21 ` juzhe.zhong
2023-06-07 6:52 ` [PATCH] " pan2.li
` (6 subsequent siblings)
9 siblings, 1 reply; 39+ messages in thread
From: pan2.li @ 2023-06-07 3:00 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, yanzhang.wang
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Add requirement to VF,
VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF.
* config/riscv/vector.md: Adjust FP convert to V_CONVERT_F
and VCONVERTF.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md | 68 +++++++++++++------
gcc/config/riscv/vector.md | 46 ++++++-------
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 +++++++
3 files changed, 97 insertions(+), 42 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..1dc82bd44d3 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [
])
(define_mode_iterator VF [
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
- (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+ (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_ZVFH")
+ (VNx4HF "TARGET_ZVFH")
+ (VNx8HF "TARGET_ZVFH")
+ (VNx16HF "TARGET_ZVFH")
+ (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
@@ -497,12 +497,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_ZVFH")
+ (VNx4SF "TARGET_ZVFH")
+ (VNx8SF "TARGET_ZVFH")
+ (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
@@ -512,12 +512,12 @@ (define_mode_iterator VWEXTF [
])
(define_mode_iterator VWCONVERTI [
- (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
- (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx4SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx8SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
- (VNx32SI "TARGET_MIN_VLEN >= 128 && TARGET_VECTOR_ELEN_FP_16")
+ (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SI "TARGET_ZVFH")
+ (VNx4SI "TARGET_ZVFH")
+ (VNx8SI "TARGET_ZVFH")
+ (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SI "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
@@ -526,6 +526,21 @@ (define_mode_iterator VWCONVERTI [
(VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator VCONVERTF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
+ (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
+ (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VQEXTI [
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
@@ -1181,6 +1196,21 @@ (define_mode_attr V_DOUBLE_TRUNC [
(VNx16DF "VNx16SF")
])
+(define_mode_attr V_CONVERT_F [
+ (VNx1SF "VNx1HF")
+ (VNx2SF "VNx2HF")
+ (VNx4SF "VNx4HF")
+ (VNx8SF "VNx8HF")
+ (VNx16SF "VNx16HF")
+ (VNx32SF "VNx32HF")
+
+ (VNx1DF "VNx1SF")
+ (VNx2DF "VNx2SF")
+ (VNx4DF "VNx4SF")
+ (VNx8DF "VNx8SF")
+ (VNx16DF "VNx16SF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
(VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
(VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..97162b07642 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7106,23 +7106,23 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_extend<mode>"
- [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
- (if_then_else:VWEXTF
+ [(set (match_operand:VCONVERTF 0 "register_operand" "=&vr, &vr")
+ (if_then_else:VCONVERTF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
- (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
+ (float_extend:VCONVERTF
+ (match_operand:<V_CONVERT_F> 3 "register_operand" " vr, vr"))
+ (match_operand:VCONVERTF 2 "vector_merge_operand" " vu, 0")))]
"TARGET_VECTOR"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
@@ -7193,25 +7193,25 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_trunc<mode>"
- [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
- (if_then_else:<V_DOUBLE_TRUNC>
+ [(set (match_operand:<V_CONVERT_F> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
+ (if_then_else:<V_CONVERT_F>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
- (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (float_truncate:<V_DOUBLE_TRUNC>
- (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
- (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
+ (float_truncate:<V_CONVERT_F>
+ (match_operand:VCONVERTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
+ (match_operand:<V_CONVERT_F> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
2023-06-06 15:34 ` Li, Pan2
@ 2023-06-07 3:02 ` Li, Pan2
0 siblings, 0 replies; 39+ messages in thread
From: Li, Pan2 @ 2023-06-07 3:02 UTC (permalink / raw)
To: 钟居哲, gcc-patches; +Cc: kito.cheng, Wang, Yanzhang
Update the PATCH v3 with rvv.exp/riscv.exp all passed as below.
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620855.html
Pan
-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Li, Pan2 via Gcc-patches
Sent: Tuesday, June 6, 2023 11:34 PM
To: 钟居哲 <juzhe.zhong@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: RE: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
Update the PATCH V2 as below.
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620787.html
Pan
From: Li, Pan2
Sent: Tuesday, June 6, 2023 10:34 PM
To: 钟居哲 <juzhe.zhong@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: RE: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
IMO, TARGET_ZVFH || TARGET_ZVFHMIN may be a little readable compares to FP_16, or some context I missed.
Anyway as we discussed offline, will refine this part and add zvfh part in V2.
Pan
From: 钟居哲 <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
Sent: Tuesday, June 6, 2023 10:07 PM
To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>
Cc: kito.cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>; Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
Subject: Re: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
+(define_mode_iterator V_ZVFHMIN_SF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)
+&& TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH ||
+TARGET_ZVFHMIN)")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH ||
+TARGET_ZVFHMIN)")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH ||
+TARGET_ZVFHMIN)")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)
+&& TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)
+&& TARGET_MIN_VLEN >= 128")
+])
why not just use "TARGET_VECTOR_ELEN_FP_16"
instead of TARGET_ZVFH || TARGET_ZVFHMIN ?
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-06-06 20:36
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@sifive.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
This patch would like to refactor the ZVFHMIN implementation by separated iterator and pattern. Thus, we can tell the sub extension between the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Move ZVFHMIN related items to separated iterators.
* config/riscv/vector.md (@pred_extend<mode>): New pattern for the ZVFHMIN instruction.
(@pred_trunc<mode>): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md | 28 ++++++++-----
gcc/config/riscv/vector.md | 40 +++++++++++++++++++
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 ++++++++++++
3 files changed, 83 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..986195489f2 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -497,13 +497,6 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
-
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
(VNx4DF "TARGET_VECTOR_ELEN_FP_64")
@@ -511,6 +504,15 @@ (define_mode_iterator VWEXTF [
(VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator V_ZVFHMIN_SF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)
+&& TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH ||
+TARGET_ZVFHMIN)")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH ||
+TARGET_ZVFHMIN)")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH ||
+TARGET_ZVFHMIN)")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)
+&& TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)
+&& TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VWCONVERTI [
(VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
(VNx2SI "TARGET_VECTOR_ELEN_FP_16")
@@ -1175,12 +1177,19 @@ (define_mode_attr V_DOUBLE_TRUNC [
(VNx16SI "VNx16HI") (VNx32SI "VNx32HI")
(VNx1DI "VNx1SI") (VNx2DI "VNx2SI") (VNx4DI "VNx4SI") (VNx8DI "VNx8SI")
(VNx16DI "VNx16SI")
-
- (VNx1SF "VNx1HF") (VNx2SF "VNx2HF") (VNx4SF "VNx4HF") (VNx8SF "VNx8HF") (VNx16SF "VNx16HF") (VNx32SF "VNx32HF")
(VNx1DF "VNx1SF") (VNx2DF "VNx2SF") (VNx4DF "VNx4SF") (VNx8DF "VNx8SF")
(VNx16DF "VNx16SF")
])
+(define_mode_attr V_ZVFHMIN [
+ (VNx1SF "VNx1HF")
+ (VNx2SF "VNx2HF")
+ (VNx4SF "VNx4HF")
+ (VNx8SF "VNx8HF")
+ (VNx16SF "VNx16HF")
+ (VNx32SF "VNx32HF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
(VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
(VNx16SI "VNx16QI") (VNx32SI "VNx32QI") @@ -1201,7 +1210,6 @@ (define_mode_attr v_double_trunc [
(VNx16SI "vnx16hi") (VNx32SI "vnx32hi")
(VNx1DI "vnx1si") (VNx2DI "vnx2si") (VNx4DI "vnx4si") (VNx8DI "vnx8si")
(VNx16DI "vnx16si")
- (VNx1SF "vnx1hf") (VNx2SF "vnx2hf") (VNx4SF "vnx4hf") (VNx8SF "vnx8hf") (VNx16SF "vnx16hf") (VNx32SF "vnx32hf")
(VNx1DF "vnx1sf") (VNx2DF "vnx2sf") (VNx4DF "vnx4sf") (VNx8DF "vnx8sf")
(VNx16DF "vnx16sf")
])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 1d1847bd85a..b498669b874 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7124,6 +7124,25 @@ (define_insn "@pred_extend<mode>"
[(set_attr "type" "vfwcvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
+(define_insn "@pred_extend<mode>"
+ [(set (match_operand:V_ZVFHMIN_SF 0 "register_operand" "=&vr, &vr")
+ (if_then_else:V_ZVFHMIN_SF
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (float_extend:V_ZVFHMIN_SF
+ (match_operand:<V_ZVFHMIN> 3 "register_operand" " vr, vr"))
+ (match_operand:V_ZVFHMIN_SF 2 "vector_merge_operand" " vu, 0")))]
+ "TARGET_VECTOR"
+ "vfwcvt.f.f.v\t%0,%3%p1"
+ [(set_attr "type" "vfwcvtftof")
+ (set_attr "mode" "<V_ZVFHMIN>")])
+
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions ;; -------------------------------------------------------------------------------
@@ -7213,6 +7232,27 @@ (define_insn "@pred_trunc<mode>"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
+(define_insn "@pred_trunc<mode>"
+ [(set (match_operand:<V_ZVFHMIN> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
+ (if_then_else:<V_ZVFHMIN>
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+ (float_truncate:<V_ZVFHMIN>
+ (match_operand:V_ZVFHMIN_SF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
+ (match_operand:<V_ZVFHMIN> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
+ "TARGET_VECTOR"
+ "vfncvt.f.f.w\t%0,%3%p1"
+ [(set_attr "type" "vfncvtftof")
+ (set_attr "mode" "<V_ZVFHMIN>")])
+
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
(if_then_else:<V_DOUBLE_TRUNC>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16mf4(src, vl); }
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16m4(src, vl); }
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32mf2(src, vl); }
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32m8(src, vl); }
+
+/* { dg-final { scan-assembler-times
+{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times
+{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times
+{vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times
+{vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-07 3:00 ` [PATCH v3] " pan2.li
@ 2023-06-07 4:21 ` juzhe.zhong
2023-06-07 6:20 ` Li, Pan2
0 siblings, 1 reply; 39+ messages in thread
From: juzhe.zhong @ 2023-06-07 4:21 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: Kito.cheng, pan2.li, yanzhang.wang
[-- Attachment #1: Type: text/plain, Size: 11541 bytes --]
HI,
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
Add TARGET_VECTOR_ELEN_FP_32 here, for FP16->FP32 conversion,
we need both ELEN_FP16 and ELEN_FP32 enable.
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-06-07 11:00
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Add requirement to VF,
VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF.
* config/riscv/vector.md: Adjust FP convert to V_CONVERT_F
and VCONVERTF.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md | 68 +++++++++++++------
gcc/config/riscv/vector.md | 46 ++++++-------
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 +++++++
3 files changed, 97 insertions(+), 42 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..1dc82bd44d3 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [
])
(define_mode_iterator VF [
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
- (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+ (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_ZVFH")
+ (VNx4HF "TARGET_ZVFH")
+ (VNx8HF "TARGET_ZVFH")
+ (VNx16HF "TARGET_ZVFH")
+ (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
@@ -497,12 +497,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_ZVFH")
+ (VNx4SF "TARGET_ZVFH")
+ (VNx8SF "TARGET_ZVFH")
+ (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
@@ -512,12 +512,12 @@ (define_mode_iterator VWEXTF [
])
(define_mode_iterator VWCONVERTI [
- (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
- (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx4SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx8SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
- (VNx32SI "TARGET_MIN_VLEN >= 128 && TARGET_VECTOR_ELEN_FP_16")
+ (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SI "TARGET_ZVFH")
+ (VNx4SI "TARGET_ZVFH")
+ (VNx8SI "TARGET_ZVFH")
+ (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SI "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
@@ -526,6 +526,21 @@ (define_mode_iterator VWCONVERTI [
(VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator VCONVERTF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
+ (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
+ (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VQEXTI [
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
@@ -1181,6 +1196,21 @@ (define_mode_attr V_DOUBLE_TRUNC [
(VNx16DF "VNx16SF")
])
+(define_mode_attr V_CONVERT_F [
+ (VNx1SF "VNx1HF")
+ (VNx2SF "VNx2HF")
+ (VNx4SF "VNx4HF")
+ (VNx8SF "VNx8HF")
+ (VNx16SF "VNx16HF")
+ (VNx32SF "VNx32HF")
+
+ (VNx1DF "VNx1SF")
+ (VNx2DF "VNx2SF")
+ (VNx4DF "VNx4SF")
+ (VNx8DF "VNx8SF")
+ (VNx16DF "VNx16SF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
(VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
(VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..97162b07642 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7106,23 +7106,23 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_extend<mode>"
- [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
- (if_then_else:VWEXTF
+ [(set (match_operand:VCONVERTF 0 "register_operand" "=&vr, &vr")
+ (if_then_else:VCONVERTF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
- (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
+ (float_extend:VCONVERTF
+ (match_operand:<V_CONVERT_F> 3 "register_operand" " vr, vr"))
+ (match_operand:VCONVERTF 2 "vector_merge_operand" " vu, 0")))]
"TARGET_VECTOR"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
@@ -7193,25 +7193,25 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_trunc<mode>"
- [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
- (if_then_else:<V_DOUBLE_TRUNC>
+ [(set (match_operand:<V_CONVERT_F> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
+ (if_then_else:<V_CONVERT_F>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
- (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (float_truncate:<V_DOUBLE_TRUNC>
- (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
- (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
+ (float_truncate:<V_CONVERT_F>
+ (match_operand:VCONVERTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
+ (match_operand:<V_CONVERT_F> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-07 4:21 ` juzhe.zhong
@ 2023-06-07 6:20 ` Li, Pan2
2023-06-07 6:57 ` Li, Pan2
0 siblings, 1 reply; 39+ messages in thread
From: Li, Pan2 @ 2023-06-07 6:20 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: Kito.cheng, Wang, Yanzhang
[-- Attachment #1: Type: text/plain, Size: 12238 bytes --]
Thanks JuZhe, make sense, will update the V4 for this change.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Wednesday, June 7, 2023 12:21 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Kito.cheng <kito.cheng@sifive.com>; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
HI,
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
Add TARGET_VECTOR_ELEN_FP_32 here, for FP16->FP32 conversion,
we need both ELEN_FP16 and ELEN_FP32 enable.
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-06-07 11:00
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@sifive.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Add requirement to VF,
VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF.
* config/riscv/vector.md: Adjust FP convert to V_CONVERT_F
and VCONVERTF.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md | 68 +++++++++++++------
gcc/config/riscv/vector.md | 46 ++++++-------
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 +++++++
3 files changed, 97 insertions(+), 42 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..1dc82bd44d3 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [
])
(define_mode_iterator VF [
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
- (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+ (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_ZVFH")
+ (VNx4HF "TARGET_ZVFH")
+ (VNx8HF "TARGET_ZVFH")
+ (VNx16HF "TARGET_ZVFH")
+ (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
@@ -497,12 +497,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_ZVFH")
+ (VNx4SF "TARGET_ZVFH")
+ (VNx8SF "TARGET_ZVFH")
+ (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
@@ -512,12 +512,12 @@ (define_mode_iterator VWEXTF [
])
(define_mode_iterator VWCONVERTI [
- (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
- (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx4SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx8SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
- (VNx32SI "TARGET_MIN_VLEN >= 128 && TARGET_VECTOR_ELEN_FP_16")
+ (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SI "TARGET_ZVFH")
+ (VNx4SI "TARGET_ZVFH")
+ (VNx8SI "TARGET_ZVFH")
+ (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SI "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
@@ -526,6 +526,21 @@ (define_mode_iterator VWCONVERTI [
(VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator VCONVERTF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
+ (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
+ (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VQEXTI [
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
@@ -1181,6 +1196,21 @@ (define_mode_attr V_DOUBLE_TRUNC [
(VNx16DF "VNx16SF")
])
+(define_mode_attr V_CONVERT_F [
+ (VNx1SF "VNx1HF")
+ (VNx2SF "VNx2HF")
+ (VNx4SF "VNx4HF")
+ (VNx8SF "VNx8HF")
+ (VNx16SF "VNx16HF")
+ (VNx32SF "VNx32HF")
+
+ (VNx1DF "VNx1SF")
+ (VNx2DF "VNx2SF")
+ (VNx4DF "VNx4SF")
+ (VNx8DF "VNx8SF")
+ (VNx16DF "VNx16SF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
(VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
(VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..97162b07642 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7106,23 +7106,23 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_extend<mode>"
- [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
- (if_then_else:VWEXTF
+ [(set (match_operand:VCONVERTF 0 "register_operand" "=&vr, &vr")
+ (if_then_else:VCONVERTF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
- (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
+ (float_extend:VCONVERTF
+ (match_operand:<V_CONVERT_F> 3 "register_operand" " vr, vr"))
+ (match_operand:VCONVERTF 2 "vector_merge_operand" " vu, 0")))]
"TARGET_VECTOR"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
@@ -7193,25 +7193,25 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_trunc<mode>"
- [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
- (if_then_else:<V_DOUBLE_TRUNC>
+ [(set (match_operand:<V_CONVERT_F> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
+ (if_then_else:<V_CONVERT_F>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
- (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (float_truncate:<V_DOUBLE_TRUNC>
- (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
- (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
+ (float_truncate:<V_CONVERT_F>
+ (match_operand:VCONVERTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
+ (match_operand:<V_CONVERT_F> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-06 12:36 [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern pan2.li
` (2 preceding siblings ...)
2023-06-07 3:00 ` [PATCH v3] " pan2.li
@ 2023-06-07 6:52 ` pan2.li
2023-06-07 8:06 ` [PATCH v5] " pan2.li
` (5 subsequent siblings)
9 siblings, 0 replies; 39+ messages in thread
From: pan2.li @ 2023-06-07 6:52 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, rdapp.gcc, jeffreyalaw, pan2.li, yanzhang.wang
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Add requirement to VF,
VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF.
* config/riscv/vector.md: Adjust FP convert to V_CONVERT_F
and VCONVERTF, and fix V_WHOLE and V_FRACT.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md | 79 +++++++++++++------
gcc/config/riscv/vector.md | 46 +++++------
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 ++++++
3 files changed, 104 insertions(+), 46 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..0e580c5a9c4 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [
])
(define_mode_iterator VF [
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
- (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+ (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_ZVFH")
+ (VNx4HF "TARGET_ZVFH")
+ (VNx8HF "TARGET_ZVFH")
+ (VNx16HF "TARGET_ZVFH")
+ (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_ZVFH")
+ (VNx4SF "TARGET_ZVFH")
+ (VNx8SF "TARGET_ZVFH")
+ (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
@@ -512,12 +515,12 @@ (define_mode_iterator VWEXTF [
])
(define_mode_iterator VWCONVERTI [
- (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
- (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx4SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx8SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
- (VNx32SI "TARGET_MIN_VLEN >= 128 && TARGET_VECTOR_ELEN_FP_16")
+ (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SI "TARGET_ZVFH")
+ (VNx4SI "TARGET_ZVFH")
+ (VNx8SI "TARGET_ZVFH")
+ (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SI "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
@@ -526,6 +529,21 @@ (define_mode_iterator VWCONVERTI [
(VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator VCONVERTF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+
+ (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
+ (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VQEXTI [
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
@@ -1181,6 +1199,21 @@ (define_mode_attr V_DOUBLE_TRUNC [
(VNx16DF "VNx16SF")
])
+(define_mode_attr V_CONVERT_F [
+ (VNx1SF "VNx1HF")
+ (VNx2SF "VNx2HF")
+ (VNx4SF "VNx4HF")
+ (VNx8SF "VNx8HF")
+ (VNx16SF "VNx16HF")
+ (VNx32SF "VNx32HF")
+
+ (VNx1DF "VNx1SF")
+ (VNx2DF "VNx2SF")
+ (VNx4DF "VNx4SF")
+ (VNx8DF "VNx8SF")
+ (VNx16DF "VNx16SF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
(VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
(VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..97162b07642 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7106,23 +7106,23 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_extend<mode>"
- [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
- (if_then_else:VWEXTF
+ [(set (match_operand:VCONVERTF 0 "register_operand" "=&vr, &vr")
+ (if_then_else:VCONVERTF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
- (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
+ (float_extend:VCONVERTF
+ (match_operand:<V_CONVERT_F> 3 "register_operand" " vr, vr"))
+ (match_operand:VCONVERTF 2 "vector_merge_operand" " vu, 0")))]
"TARGET_VECTOR"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
@@ -7193,25 +7193,25 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_trunc<mode>"
- [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
- (if_then_else:<V_DOUBLE_TRUNC>
+ [(set (match_operand:<V_CONVERT_F> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
+ (if_then_else:<V_CONVERT_F>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
- (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (float_truncate:<V_DOUBLE_TRUNC>
- (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
- (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
+ (float_truncate:<V_CONVERT_F>
+ (match_operand:VCONVERTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
+ (match_operand:<V_CONVERT_F> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-07 6:20 ` Li, Pan2
@ 2023-06-07 6:57 ` Li, Pan2
2023-06-07 8:07 ` Li, Pan2
0 siblings, 1 reply; 39+ messages in thread
From: Li, Pan2 @ 2023-06-07 6:57 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: Kito.cheng, Wang, Yanzhang
[-- Attachment #1: Type: text/plain, Size: 12871 bytes --]
Update the PATCH V4 as below, sorry for missed the v4 prefix in subject.
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620879.html
Pan
From: Li, Pan2
Sent: Wednesday, June 7, 2023 2:21 PM
To: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: RE: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
Thanks JuZhe, make sense, will update the V4 for this change.
Pan
From: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai> <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
Sent: Wednesday, June 7, 2023 12:21 PM
To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>
Cc: Kito.cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>; Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
Subject: Re: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
HI,
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
Add TARGET_VECTOR_ELEN_FP_32 here, for FP16->FP32 conversion,
we need both ELEN_FP16 and ELEN_FP32 enable.
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-06-07 11:00
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@sifive.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Add requirement to VF,
VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF.
* config/riscv/vector.md: Adjust FP convert to V_CONVERT_F
and VCONVERTF.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md | 68 +++++++++++++------
gcc/config/riscv/vector.md | 46 ++++++-------
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 +++++++
3 files changed, 97 insertions(+), 42 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..1dc82bd44d3 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [
])
(define_mode_iterator VF [
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
- (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+ (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_ZVFH")
+ (VNx4HF "TARGET_ZVFH")
+ (VNx8HF "TARGET_ZVFH")
+ (VNx16HF "TARGET_ZVFH")
+ (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
@@ -497,12 +497,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_ZVFH")
+ (VNx4SF "TARGET_ZVFH")
+ (VNx8SF "TARGET_ZVFH")
+ (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
@@ -512,12 +512,12 @@ (define_mode_iterator VWEXTF [
])
(define_mode_iterator VWCONVERTI [
- (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
- (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx4SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx8SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
- (VNx32SI "TARGET_MIN_VLEN >= 128 && TARGET_VECTOR_ELEN_FP_16")
+ (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SI "TARGET_ZVFH")
+ (VNx4SI "TARGET_ZVFH")
+ (VNx8SI "TARGET_ZVFH")
+ (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SI "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
@@ -526,6 +526,21 @@ (define_mode_iterator VWCONVERTI [
(VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator VCONVERTF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
+ (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
+ (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VQEXTI [
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
@@ -1181,6 +1196,21 @@ (define_mode_attr V_DOUBLE_TRUNC [
(VNx16DF "VNx16SF")
])
+(define_mode_attr V_CONVERT_F [
+ (VNx1SF "VNx1HF")
+ (VNx2SF "VNx2HF")
+ (VNx4SF "VNx4HF")
+ (VNx8SF "VNx8HF")
+ (VNx16SF "VNx16HF")
+ (VNx32SF "VNx32HF")
+
+ (VNx1DF "VNx1SF")
+ (VNx2DF "VNx2SF")
+ (VNx4DF "VNx4SF")
+ (VNx8DF "VNx8SF")
+ (VNx16DF "VNx16SF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
(VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
(VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..97162b07642 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7106,23 +7106,23 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_extend<mode>"
- [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
- (if_then_else:VWEXTF
+ [(set (match_operand:VCONVERTF 0 "register_operand" "=&vr, &vr")
+ (if_then_else:VCONVERTF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
- (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
+ (float_extend:VCONVERTF
+ (match_operand:<V_CONVERT_F> 3 "register_operand" " vr, vr"))
+ (match_operand:VCONVERTF 2 "vector_merge_operand" " vu, 0")))]
"TARGET_VECTOR"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
@@ -7193,25 +7193,25 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_trunc<mode>"
- [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
- (if_then_else:<V_DOUBLE_TRUNC>
+ [(set (match_operand:<V_CONVERT_F> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
+ (if_then_else:<V_CONVERT_F>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
- (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (float_truncate:<V_DOUBLE_TRUNC>
- (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
- (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
+ (float_truncate:<V_CONVERT_F>
+ (match_operand:VCONVERTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
+ (match_operand:<V_CONVERT_F> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-06 12:36 [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern pan2.li
` (3 preceding siblings ...)
2023-06-07 6:52 ` [PATCH] " pan2.li
@ 2023-06-07 8:06 ` pan2.li
2023-06-07 8:11 ` juzhe.zhong
2023-06-07 8:27 ` juzhe.zhong
2023-06-08 5:20 ` [PATCH v6] " pan2.li
` (4 subsequent siblings)
9 siblings, 2 replies; 39+ messages in thread
From: pan2.li @ 2023-06-07 8:06 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, rdapp.gcc, jeffreyalaw, pan2.li, yanzhang.wang
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Add requirement to VF,
VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF.
* config/riscv/vector.md: Adjust FP convert to V_CONVERT_F
and VCONVERTF, and fix V_WHOLE and V_FRACT.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md | 79 +++++++++++++------
gcc/config/riscv/vector.md | 46 +++++------
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 ++++++
3 files changed, 104 insertions(+), 46 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..e6c2ecf7c86 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [
])
(define_mode_iterator VF [
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
- (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+ (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_ZVFH")
+ (VNx4HF "TARGET_ZVFH")
+ (VNx8HF "TARGET_ZVFH")
+ (VNx16HF "TARGET_ZVFH")
+ (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
@@ -512,12 +515,12 @@ (define_mode_iterator VWEXTF [
])
(define_mode_iterator VWCONVERTI [
- (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
- (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx4SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx8SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
- (VNx32SI "TARGET_MIN_VLEN >= 128 && TARGET_VECTOR_ELEN_FP_16")
+ (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SI "TARGET_ZVFH")
+ (VNx4SI "TARGET_ZVFH")
+ (VNx8SI "TARGET_ZVFH")
+ (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SI "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
@@ -526,6 +529,21 @@ (define_mode_iterator VWCONVERTI [
(VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator VCONVERTF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+
+ (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
+ (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VQEXTI [
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
@@ -1181,6 +1199,21 @@ (define_mode_attr V_DOUBLE_TRUNC [
(VNx16DF "VNx16SF")
])
+(define_mode_attr V_CONVERT_F [
+ (VNx1SF "VNx1HF")
+ (VNx2SF "VNx2HF")
+ (VNx4SF "VNx4HF")
+ (VNx8SF "VNx8HF")
+ (VNx16SF "VNx16HF")
+ (VNx32SF "VNx32HF")
+
+ (VNx1DF "VNx1SF")
+ (VNx2DF "VNx2SF")
+ (VNx4DF "VNx4SF")
+ (VNx8DF "VNx8SF")
+ (VNx16DF "VNx16SF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
(VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
(VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..97162b07642 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7106,23 +7106,23 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_extend<mode>"
- [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
- (if_then_else:VWEXTF
+ [(set (match_operand:VCONVERTF 0 "register_operand" "=&vr, &vr")
+ (if_then_else:VCONVERTF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
- (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
+ (float_extend:VCONVERTF
+ (match_operand:<V_CONVERT_F> 3 "register_operand" " vr, vr"))
+ (match_operand:VCONVERTF 2 "vector_merge_operand" " vu, 0")))]
"TARGET_VECTOR"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
@@ -7193,25 +7193,25 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_trunc<mode>"
- [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
- (if_then_else:<V_DOUBLE_TRUNC>
+ [(set (match_operand:<V_CONVERT_F> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
+ (if_then_else:<V_CONVERT_F>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
- (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (float_truncate:<V_DOUBLE_TRUNC>
- (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
- (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
+ (float_truncate:<V_CONVERT_F>
+ (match_operand:VCONVERTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
+ (match_operand:<V_CONVERT_F> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-07 6:57 ` Li, Pan2
@ 2023-06-07 8:07 ` Li, Pan2
0 siblings, 0 replies; 39+ messages in thread
From: Li, Pan2 @ 2023-06-07 8:07 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: Kito.cheng, Wang, Yanzhang
[-- Attachment #1: Type: text/plain, Size: 13465 bytes --]
Minor change in PATCH V5, please help to turn to V5 as below, sorry for inconvenient.
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620890.html
Pan
From: Li, Pan2
Sent: Wednesday, June 7, 2023 2:57 PM
To: 'juzhe.zhong@rivai.ai' <juzhe.zhong@rivai.ai>; 'gcc-patches' <gcc-patches@gcc.gnu.org>
Cc: 'Kito.cheng' <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: RE: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
Update the PATCH V4 as below, sorry for missed the v4 prefix in subject.
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620879.html
Pan
From: Li, Pan2
Sent: Wednesday, June 7, 2023 2:21 PM
To: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>
Cc: Kito.cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
Subject: RE: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
Thanks JuZhe, make sense, will update the V4 for this change.
Pan
From: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai> <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
Sent: Wednesday, June 7, 2023 12:21 PM
To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>
Cc: Kito.cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>; Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
Subject: Re: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
HI,
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
Add TARGET_VECTOR_ELEN_FP_32 here, for FP16->FP32 conversion,
we need both ELEN_FP16 and ELEN_FP32 enable.
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-06-07 11:00
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@sifive.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Add requirement to VF,
VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF.
* config/riscv/vector.md: Adjust FP convert to V_CONVERT_F
and VCONVERTF.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md | 68 +++++++++++++------
gcc/config/riscv/vector.md | 46 ++++++-------
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 +++++++
3 files changed, 97 insertions(+), 42 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..1dc82bd44d3 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [
])
(define_mode_iterator VF [
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
- (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+ (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_ZVFH")
+ (VNx4HF "TARGET_ZVFH")
+ (VNx8HF "TARGET_ZVFH")
+ (VNx16HF "TARGET_ZVFH")
+ (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
@@ -497,12 +497,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_ZVFH")
+ (VNx4SF "TARGET_ZVFH")
+ (VNx8SF "TARGET_ZVFH")
+ (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
@@ -512,12 +512,12 @@ (define_mode_iterator VWEXTF [
])
(define_mode_iterator VWCONVERTI [
- (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
- (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx4SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx8SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
- (VNx32SI "TARGET_MIN_VLEN >= 128 && TARGET_VECTOR_ELEN_FP_16")
+ (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SI "TARGET_ZVFH")
+ (VNx4SI "TARGET_ZVFH")
+ (VNx8SI "TARGET_ZVFH")
+ (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SI "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
@@ -526,6 +526,21 @@ (define_mode_iterator VWCONVERTI [
(VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator VCONVERTF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
+ (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
+ (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VQEXTI [
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
@@ -1181,6 +1196,21 @@ (define_mode_attr V_DOUBLE_TRUNC [
(VNx16DF "VNx16SF")
])
+(define_mode_attr V_CONVERT_F [
+ (VNx1SF "VNx1HF")
+ (VNx2SF "VNx2HF")
+ (VNx4SF "VNx4HF")
+ (VNx8SF "VNx8HF")
+ (VNx16SF "VNx16HF")
+ (VNx32SF "VNx32HF")
+
+ (VNx1DF "VNx1SF")
+ (VNx2DF "VNx2SF")
+ (VNx4DF "VNx4SF")
+ (VNx8DF "VNx8SF")
+ (VNx16DF "VNx16SF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
(VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
(VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..97162b07642 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7106,23 +7106,23 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_extend<mode>"
- [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
- (if_then_else:VWEXTF
+ [(set (match_operand:VCONVERTF 0 "register_operand" "=&vr, &vr")
+ (if_then_else:VCONVERTF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
- (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
+ (float_extend:VCONVERTF
+ (match_operand:<V_CONVERT_F> 3 "register_operand" " vr, vr"))
+ (match_operand:VCONVERTF 2 "vector_merge_operand" " vu, 0")))]
"TARGET_VECTOR"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
@@ -7193,25 +7193,25 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_trunc<mode>"
- [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
- (if_then_else:<V_DOUBLE_TRUNC>
+ [(set (match_operand:<V_CONVERT_F> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
+ (if_then_else:<V_CONVERT_F>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
- (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (float_truncate:<V_DOUBLE_TRUNC>
- (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
- (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
+ (float_truncate:<V_CONVERT_F>
+ (match_operand:VCONVERTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
+ (match_operand:<V_CONVERT_F> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-07 8:06 ` [PATCH v5] " pan2.li
@ 2023-06-07 8:11 ` juzhe.zhong
2023-06-07 8:27 ` juzhe.zhong
1 sibling, 0 replies; 39+ messages in thread
From: juzhe.zhong @ 2023-06-07 8:11 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: Robin Dapp, jeffreyalaw, pan2.li, yanzhang.wang
[-- Attachment #1: Type: text/plain, Size: 13130 bytes --]
I am not sure for load/stores of FP16 vector should be gated by ZVFHMIN or ZVFH?
Since IMHO, load/stores of FP16 is no different from load/stores of INT16?
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-06-07 16:06
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang
Subject: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Add requirement to VF,
VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF.
* config/riscv/vector.md: Adjust FP convert to V_CONVERT_F
and VCONVERTF, and fix V_WHOLE and V_FRACT.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md | 79 +++++++++++++------
gcc/config/riscv/vector.md | 46 +++++------
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 ++++++
3 files changed, 104 insertions(+), 46 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..e6c2ecf7c86 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [
])
(define_mode_iterator VF [
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
- (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+ (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_ZVFH")
+ (VNx4HF "TARGET_ZVFH")
+ (VNx8HF "TARGET_ZVFH")
+ (VNx16HF "TARGET_ZVFH")
+ (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
@@ -512,12 +515,12 @@ (define_mode_iterator VWEXTF [
])
(define_mode_iterator VWCONVERTI [
- (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
- (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx4SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx8SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
- (VNx32SI "TARGET_MIN_VLEN >= 128 && TARGET_VECTOR_ELEN_FP_16")
+ (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SI "TARGET_ZVFH")
+ (VNx4SI "TARGET_ZVFH")
+ (VNx8SI "TARGET_ZVFH")
+ (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SI "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
@@ -526,6 +529,21 @@ (define_mode_iterator VWCONVERTI [
(VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator VCONVERTF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+
+ (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
+ (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VQEXTI [
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
@@ -1181,6 +1199,21 @@ (define_mode_attr V_DOUBLE_TRUNC [
(VNx16DF "VNx16SF")
])
+(define_mode_attr V_CONVERT_F [
+ (VNx1SF "VNx1HF")
+ (VNx2SF "VNx2HF")
+ (VNx4SF "VNx4HF")
+ (VNx8SF "VNx8HF")
+ (VNx16SF "VNx16HF")
+ (VNx32SF "VNx32HF")
+
+ (VNx1DF "VNx1SF")
+ (VNx2DF "VNx2SF")
+ (VNx4DF "VNx4SF")
+ (VNx8DF "VNx8SF")
+ (VNx16DF "VNx16SF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
(VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
(VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..97162b07642 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7106,23 +7106,23 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_extend<mode>"
- [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
- (if_then_else:VWEXTF
+ [(set (match_operand:VCONVERTF 0 "register_operand" "=&vr, &vr")
+ (if_then_else:VCONVERTF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
- (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
+ (float_extend:VCONVERTF
+ (match_operand:<V_CONVERT_F> 3 "register_operand" " vr, vr"))
+ (match_operand:VCONVERTF 2 "vector_merge_operand" " vu, 0")))]
"TARGET_VECTOR"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
@@ -7193,25 +7193,25 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_trunc<mode>"
- [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
- (if_then_else:<V_DOUBLE_TRUNC>
+ [(set (match_operand:<V_CONVERT_F> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
+ (if_then_else:<V_CONVERT_F>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
- (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (float_truncate:<V_DOUBLE_TRUNC>
- (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
- (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
+ (float_truncate:<V_CONVERT_F>
+ (match_operand:VCONVERTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
+ (match_operand:<V_CONVERT_F> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-07 8:06 ` [PATCH v5] " pan2.li
2023-06-07 8:11 ` juzhe.zhong
@ 2023-06-07 8:27 ` juzhe.zhong
2023-06-07 8:42 ` Li, Pan2
1 sibling, 1 reply; 39+ messages in thread
From: juzhe.zhong @ 2023-06-07 8:27 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: Robin Dapp, jeffreyalaw, pan2.li, yanzhang.wang
[-- Attachment #1: Type: text/plain, Size: 14875 bytes --]
In this patch, you add TARGET_ZVFH into VF iterator which is not correct.
When TARGET_ZVFH is true, TARGET_ZVFHMIN is always true.
For vfadd, it is true we should enable "vfadd" for TARGET_ZVFH
For vle16, we should enable for TARGET_ZVFHMIN.
This patch will disable both "vle16" and "vfadd" for FP16 on ZVFHMIN which is not correct.
I think you should allow all FP16 vector modes in iterator enable by TARGET_VECTOR_FP_ELN_16 (TARGET_ZVFHMIN).
Then, when zvfhmin is enabled, all FP16 instructions are enabled by default.
To gate the situation only enable when TARGET_ZVFH, you add the predicate as below:
For example:
vfadd.vv (need
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
(match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(any_float_binop:VF
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
bool
float_mode_supported_p (machine_mode mode)
{
if (GET_MODE_INNER (mode) == HFmode)
return TARGET_ZVFH;
return true;
}
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-06-07 16:06
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang
Subject: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Add requirement to VF,
VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF.
* config/riscv/vector.md: Adjust FP convert to V_CONVERT_F
and VCONVERTF, and fix V_WHOLE and V_FRACT.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md | 79 +++++++++++++------
gcc/config/riscv/vector.md | 46 +++++------
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 ++++++
3 files changed, 104 insertions(+), 46 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..e6c2ecf7c86 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [
])
(define_mode_iterator VF [
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
- (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+ (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_ZVFH")
+ (VNx4HF "TARGET_ZVFH")
+ (VNx8HF "TARGET_ZVFH")
+ (VNx16HF "TARGET_ZVFH")
+ (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
@@ -512,12 +515,12 @@ (define_mode_iterator VWEXTF [
])
(define_mode_iterator VWCONVERTI [
- (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
- (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx4SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx8SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
- (VNx32SI "TARGET_MIN_VLEN >= 128 && TARGET_VECTOR_ELEN_FP_16")
+ (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SI "TARGET_ZVFH")
+ (VNx4SI "TARGET_ZVFH")
+ (VNx8SI "TARGET_ZVFH")
+ (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SI "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
@@ -526,6 +529,21 @@ (define_mode_iterator VWCONVERTI [
(VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator VCONVERTF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+
+ (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
+ (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VQEXTI [
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
@@ -1181,6 +1199,21 @@ (define_mode_attr V_DOUBLE_TRUNC [
(VNx16DF "VNx16SF")
])
+(define_mode_attr V_CONVERT_F [
+ (VNx1SF "VNx1HF")
+ (VNx2SF "VNx2HF")
+ (VNx4SF "VNx4HF")
+ (VNx8SF "VNx8HF")
+ (VNx16SF "VNx16HF")
+ (VNx32SF "VNx32HF")
+
+ (VNx1DF "VNx1SF")
+ (VNx2DF "VNx2SF")
+ (VNx4DF "VNx4SF")
+ (VNx8DF "VNx8SF")
+ (VNx16DF "VNx16SF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
(VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
(VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..97162b07642 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7106,23 +7106,23 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_extend<mode>"
- [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
- (if_then_else:VWEXTF
+ [(set (match_operand:VCONVERTF 0 "register_operand" "=&vr, &vr")
+ (if_then_else:VCONVERTF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
- (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
+ (float_extend:VCONVERTF
+ (match_operand:<V_CONVERT_F> 3 "register_operand" " vr, vr"))
+ (match_operand:VCONVERTF 2 "vector_merge_operand" " vu, 0")))]
"TARGET_VECTOR"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
@@ -7193,25 +7193,25 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_trunc<mode>"
- [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
- (if_then_else:<V_DOUBLE_TRUNC>
+ [(set (match_operand:<V_CONVERT_F> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
+ (if_then_else:<V_CONVERT_F>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
- (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (float_truncate:<V_DOUBLE_TRUNC>
- (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
- (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
+ (float_truncate:<V_CONVERT_F>
+ (match_operand:VCONVERTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
+ (match_operand:<V_CONVERT_F> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-07 8:27 ` juzhe.zhong
@ 2023-06-07 8:42 ` Li, Pan2
2023-06-08 6:07 ` Li, Pan2
0 siblings, 1 reply; 39+ messages in thread
From: Li, Pan2 @ 2023-06-07 8:42 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: Robin Dapp, jeffreyalaw, Wang, Yanzhang
[-- Attachment #1: Type: text/plain, Size: 15740 bytes --]
Thanks Juzhe for reviewing. I see, this way may have even smaller code change which treats the zvfhmin as minimal base sub extension.
I will have a try for PATCH V6.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Wednesday, June 7, 2023 4:27 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
In this patch, you add TARGET_ZVFH into VF iterator which is not correct.
When TARGET_ZVFH is true, TARGET_ZVFHMIN is always true.
For vfadd, it is true we should enable "vfadd" for TARGET_ZVFH
For vle16, we should enable for TARGET_ZVFHMIN.
This patch will disable both "vle16" and "vfadd" for FP16 on ZVFHMIN which is not correct.
I think you should allow all FP16 vector modes in iterator enable by TARGET_VECTOR_FP_ELN_16 (TARGET_ZVFHMIN).
Then, when zvfhmin is enabled, all FP16 instructions are enabled by default.
To gate the situation only enable when TARGET_ZVFH, you add the predicate as below:
For example:
vfadd.vv (need
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
(match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(any_float_binop:VF
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
bool
float_mode_supported_p (machine_mode mode)
{
if (GET_MODE_INNER (mode) == HFmode)
return TARGET_ZVFH;
return true;
}
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-06-07 16:06
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; rdapp.gcc<mailto:rdapp.gcc@gmail.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Add requirement to VF,
VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF.
* config/riscv/vector.md: Adjust FP convert to V_CONVERT_F
and VCONVERTF, and fix V_WHOLE and V_FRACT.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md | 79 +++++++++++++------
gcc/config/riscv/vector.md | 46 +++++------
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 ++++++
3 files changed, 104 insertions(+), 46 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..e6c2ecf7c86 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [
])
(define_mode_iterator VF [
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
- (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+ (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_ZVFH")
+ (VNx4HF "TARGET_ZVFH")
+ (VNx8HF "TARGET_ZVFH")
+ (VNx16HF "TARGET_ZVFH")
+ (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
@@ -512,12 +515,12 @@ (define_mode_iterator VWEXTF [
])
(define_mode_iterator VWCONVERTI [
- (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
- (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx4SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx8SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
- (VNx32SI "TARGET_MIN_VLEN >= 128 && TARGET_VECTOR_ELEN_FP_16")
+ (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SI "TARGET_ZVFH")
+ (VNx4SI "TARGET_ZVFH")
+ (VNx8SI "TARGET_ZVFH")
+ (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SI "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
@@ -526,6 +529,21 @@ (define_mode_iterator VWCONVERTI [
(VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator VCONVERTF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+
+ (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
+ (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VQEXTI [
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
@@ -1181,6 +1199,21 @@ (define_mode_attr V_DOUBLE_TRUNC [
(VNx16DF "VNx16SF")
])
+(define_mode_attr V_CONVERT_F [
+ (VNx1SF "VNx1HF")
+ (VNx2SF "VNx2HF")
+ (VNx4SF "VNx4HF")
+ (VNx8SF "VNx8HF")
+ (VNx16SF "VNx16HF")
+ (VNx32SF "VNx32HF")
+
+ (VNx1DF "VNx1SF")
+ (VNx2DF "VNx2SF")
+ (VNx4DF "VNx4SF")
+ (VNx8DF "VNx8SF")
+ (VNx16DF "VNx16SF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
(VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
(VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..97162b07642 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7106,23 +7106,23 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_extend<mode>"
- [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
- (if_then_else:VWEXTF
+ [(set (match_operand:VCONVERTF 0 "register_operand" "=&vr, &vr")
+ (if_then_else:VCONVERTF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
- (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
+ (float_extend:VCONVERTF
+ (match_operand:<V_CONVERT_F> 3 "register_operand" " vr, vr"))
+ (match_operand:VCONVERTF 2 "vector_merge_operand" " vu, 0")))]
"TARGET_VECTOR"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
@@ -7193,25 +7193,25 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_trunc<mode>"
- [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
- (if_then_else:<V_DOUBLE_TRUNC>
+ [(set (match_operand:<V_CONVERT_F> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
+ (if_then_else:<V_CONVERT_F>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
- (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (float_truncate:<V_DOUBLE_TRUNC>
- (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
- (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
+ (float_truncate:<V_CONVERT_F>
+ (match_operand:VCONVERTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
+ (match_operand:<V_CONVERT_F> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v6] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-06 12:36 [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern pan2.li
` (4 preceding siblings ...)
2023-06-07 8:06 ` [PATCH v5] " pan2.li
@ 2023-06-08 5:20 ` pan2.li
2023-06-08 6:06 ` [PATCH v7] " pan2.li
` (3 subsequent siblings)
9 siblings, 0 replies; 39+ messages in thread
From: pan2.li @ 2023-06-08 5:20 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, rdapp.gcc, jeffreyalaw, pan2.li, yanzhang.wang
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
iterators of RVV. And then the ZVFH will leverage one function as
the gate for FP16 supported or not.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv-protos.h (float_point_mode_supported_p):
New function to float point is supported by extension.
* config/riscv/riscv-v.cc (float_point_mode_supported_p):
Ditto.
* config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
* config/riscv/vector.md: Add condition to FP define insn.
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 12 +++
gcc/config/riscv/vector-iterators.md | 23 +++--
gcc/config/riscv/vector.md | 144 +++++++++++++++------------
4 files changed, 105 insertions(+), 75 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index ebbaac255f9..e4881786b53 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -177,6 +177,7 @@ rtx expand_builtin (unsigned int, tree, rtx);
bool check_builtin_call (location_t, vec<location_t>, unsigned int,
tree, unsigned int, tree *);
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
+bool float_point_mode_supported_p (machine_mode mode);
bool legitimize_move (rtx, rtx);
void emit_vlmax_vsetvl (machine_mode, rtx);
void emit_hard_vlmax_vsetvl (machine_mode, rtx);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 49752cd8899..1cc157f1858 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -418,6 +418,18 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
&& IN_RANGE (INTVAL (elt), minval, maxval));
}
+/* Return true if the inner of mode is HFmode when ZVFH enabled, or other
+ float point machine mode. */
+bool
+float_point_mode_supported_p (machine_mode mode)
+{
+ machine_mode inner_mode = GET_MODE_INNER (mode);
+
+ gcc_assert (FLOAT_MODE_P (inner_mode));
+
+ return inner_mode == HFmode ? TARGET_ZVFH : true;
+}
+
/* Return true if VEC is a constant in which every element is in the range
[MINVAL, MAXVAL]. The elements do not need to have the same value.
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..234b712bc9d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..438670e8aec 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1364,7 +1364,7 @@ (define_insn "*pred_broadcast<mode>"
(vec_duplicate:VF
(match_operand:<VEL> 3 "direct_broadcast_operand" " f, f,Wdm,Wdm,Wdm,Wdm, f, f"))
(match_operand:VF 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vfmv.v.f\t%0,%3
vfmv.v.f\t%0,%3
@@ -5685,7 +5685,7 @@ (define_insn "@pred_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5705,7 +5705,7 @@ (define_insn "@pred_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5728,7 +5728,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5749,7 +5749,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5772,7 +5772,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(vec_duplicate:VF
(match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5795,7 +5795,7 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfr<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5815,7 +5815,7 @@ (define_insn "@pred_<copysign><mode>"
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS)
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfsgnj<nx>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfsgnj")
(set_attr "mode" "<MODE>")])
@@ -5836,7 +5836,7 @@ (define_insn "@pred_<copysign><mode>_scalar"
(vec_duplicate:VF
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS)
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfsgnj<nx>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfsgnj")
(set_attr "mode" "<MODE>")])
@@ -5894,7 +5894,7 @@ (define_insn "*pred_<madd_msub><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<madd_msub>.vv\t%0,%3,%4%p1
vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
@@ -5927,7 +5927,7 @@ (define_insn "*pred_<macc_msac><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<macc_msac>.vv\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
@@ -5960,7 +5960,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[2], operands[5])
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
@@ -6021,7 +6021,7 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
(match_operand:VF 3 "register_operand" " 0, vr, 0, vr"))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 3)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<madd_msub>.vf\t%0,%2,%4%p1
vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
@@ -6055,7 +6055,7 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<macc_msac>.vf\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
@@ -6089,7 +6089,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
"@
@@ -6154,7 +6154,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
@@ -6188,7 +6188,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
@@ -6222,7 +6222,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr")))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[2], operands[5])
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
@@ -6285,7 +6285,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
(match_operand:VF 3 "register_operand" " 0, vr, 0, vr")))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 3)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
@@ -6320,7 +6320,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
@@ -6355,7 +6355,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr")))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
"@
@@ -6399,7 +6399,7 @@ (define_insn "@pred_<optab><mode>"
(any_float_unop:VF
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
@@ -6422,7 +6422,7 @@ (define_insn "@pred_<optab><mode>"
(any_float_unop_nofrm:VF
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
@@ -6445,7 +6445,7 @@ (define_insn "@pred_<misc_op><mode>"
(unspec:VF
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<misc_op>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -6464,7 +6464,7 @@ (define_insn "@pred_class<mode>"
(unspec:<VCONVERT>
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfclass.v\t%0,%3%p1"
[(set_attr "type" "vfclass")
(set_attr "mode" "<MODE>")])
@@ -6497,7 +6497,7 @@ (define_insn "@pred_dual_widen_<optab><mode>"
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6522,7 +6522,7 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
(vec_duplicate:<V_DOUBLE_TRUNC>
(match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6545,7 +6545,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>"
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.wv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6569,7 +6569,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
(vec_duplicate:<V_DOUBLE_TRUNC>
(match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.wf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6602,7 +6602,7 @@ (define_insn "@pred_widen_mul_<optab><mode>"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<macc_msac>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6629,7 +6629,7 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<macc_msac>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6656,7 +6656,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6684,7 +6684,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6728,7 +6728,8 @@ (define_insn "*pred_cmp<mode>"
[(match_operand:VF 4 "register_operand" " vr, vr")
(match_operand:VF 5 "register_operand" " vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vv\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6747,7 +6748,7 @@ (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
[(match_operand:VF 3 "register_operand" " vr")
(match_operand:VF 4 "register_operand" " vr")])
(match_dup 1)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B2.vv\t%0,%3,%4,v0.t"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")
@@ -6771,7 +6772,8 @@ (define_insn "*pred_cmp<mode>_narrow"
[(match_operand:VF 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
(match_operand:VF 5 "register_operand" " vr, vr, 0, 0, vr, 0, 0, vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
- "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vv\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6809,7 +6811,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
(vec_duplicate:VF
(match_operand:<VEL> 4 "register_operand" " f"))])
(match_dup 1)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B2.vf\t%0,%3,%4,v0.t"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")
@@ -6834,7 +6836,8 @@ (define_insn "*pred_cmp<mode>_scalar"
(vec_duplicate:VF
(match_operand:<VEL> 5 "register_operand" " f, f"))])
(match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6855,7 +6858,8 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(vec_duplicate:VF
(match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))])
(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6893,7 +6897,7 @@ (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
(match_operand:<VEL> 4 "register_operand" " f"))
(match_operand:VF 3 "register_operand" " vr")])
(match_dup 1)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B2.vf\t%0,%3,%4,v0.t"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")
@@ -6918,7 +6922,8 @@ (define_insn "*pred_eqne<mode>_scalar"
(match_operand:<VEL> 5 "register_operand" " f, f"))
(match_operand:VF 4 "register_operand" " vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6939,7 +6944,8 @@ (define_insn "*pred_eqne<mode>_scalar_narrow"
(match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
(match_operand:VF 4 "register_operand" " vr, 0, 0, vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6966,7 +6972,7 @@ (define_insn "@pred_merge<mode>_scalar"
(match_operand:VF 2 "register_operand" " vr,vr")
(match_operand:<VM> 4 "register_operand" " vm,vm"))
(match_operand:VF 1 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfmerge.vfm\t%0,%2,%3,%4"
[(set_attr "type" "vfmerge")
(set_attr "mode" "<MODE>")])
@@ -6994,7 +7000,7 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
(unspec:<VCONVERT>
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS)
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
(set_attr "mode" "<MODE>")])
@@ -7013,7 +7019,7 @@ (define_insn "@pred_<fix_cvt><mode>"
(any_fix:<VCONVERT>
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
(set_attr "mode" "<MODE>")])
@@ -7034,7 +7040,7 @@ (define_insn "@pred_<float_cvt><mode>"
(any_float:VF
(match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfcvtitof")
(set_attr "mode" "<MODE>")])
@@ -7062,7 +7068,7 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
(unspec:VWCONVERTI
[(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")] VFCVTS)
(match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<VNCONVERT>mode)"
"vfwcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7081,7 +7087,7 @@ (define_insn "@pred_widen_<fix_cvt><mode>"
(any_fix:VWCONVERTI
(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
(match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<VNCONVERT>mode)"
"vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7100,7 +7106,7 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(any_float:VF
(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfwcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtitof")
(set_attr "mode" "<VNCONVERT>")])
@@ -7119,7 +7125,7 @@ (define_insn "@pred_extend<mode>"
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -7147,7 +7153,7 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
(unspec:<VNCONVERT>
[(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS)
(match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfncvt.x<v_su>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7166,7 +7172,7 @@ (define_insn "@pred_narrow_<fix_cvt><mode>"
(any_fix:<VNCONVERT>
(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<VNCONVERT>mode)"
"vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7187,7 +7193,7 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(any_float:<VNCONVERT>
(match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<VNCONVERT>mode)"
"vfncvt.f.x<u>.w\t%0,%3%p1"
[(set_attr "type" "vfncvtitof")
(set_attr "mode" "<VNCONVERT>")])
@@ -7208,7 +7214,7 @@ (define_insn "@pred_trunc<mode>"
(float_truncate:<V_DOUBLE_TRUNC>
(match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -7228,7 +7234,7 @@ (define_insn "@pred_rod_trunc<mode>"
[(float_truncate:<V_DOUBLE_TRUNC>
(match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
(match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfncvt.rod.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -7389,7 +7395,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1>"
(parallel [(const_int 0)])))
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+ "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
@@ -7413,7 +7420,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve64>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 64
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
@@ -7437,7 +7445,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 32
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
@@ -7462,7 +7471,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1>"
(parallel [(const_int 0)])))
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+ "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
@@ -7487,7 +7497,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve64>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 64
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
@@ -7512,7 +7523,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve32>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 32
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
@@ -7533,7 +7545,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1>"
(match_operand:VWF 3 "register_operand" " vr, vr")
(match_operand:<VWLMUL1> 4 "register_operand" " vr, vr")
(match_operand:<VWLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+ "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
(set_attr "mode" "<MODE>")])
@@ -7554,7 +7567,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>"
(match_operand:VWF_ZVE64 3 "register_operand" " vr, vr")
(match_operand:<VWLMUL1_ZVE64> 4 "register_operand" " vr, vr")
(match_operand:<VWLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 64
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
(set_attr "mode" "<MODE>")])
@@ -7657,7 +7671,7 @@ (define_insn "*pred_extract_first<mode>"
(match_operand:VF 1 "register_operand" "vr")
(parallel [(const_int 0)]))
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfmv.f.s\t%0,%1"
[(set_attr "type" "vfmovvf")
(set_attr "mode" "<MODE>")])
@@ -7778,7 +7792,7 @@ (define_insn "@pred_slide<ud><mode>"
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:<VEL> 4 "register_operand" " f, f, f, f")] VFSLIDES1))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfslide<ud>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfslide<ud>")
(set_attr "mode" "<MODE>")])
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v7] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-06 12:36 [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern pan2.li
` (5 preceding siblings ...)
2023-06-08 5:20 ` [PATCH v6] " pan2.li
@ 2023-06-08 6:06 ` pan2.li
2023-06-08 6:09 ` juzhe.zhong
2023-06-08 6:29 ` [PATCH v8] " pan2.li
` (2 subsequent siblings)
9 siblings, 1 reply; 39+ messages in thread
From: pan2.li @ 2023-06-08 6:06 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, rdapp.gcc, jeffreyalaw, pan2.li, yanzhang.wang
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
iterators of RVV. And then the ZVFH will leverage one function as
the gate for FP16 supported or not.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv-protos.h (float_point_mode_supported_p):
New function to float point is supported by extension.
* config/riscv/riscv-v.cc (float_point_mode_supported_p):
Ditto.
* config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
* config/riscv/vector.md: Add condition to FP define insn.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
for ZVFHMIN.
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 12 ++
gcc/config/riscv/vector-iterators.md | 23 +--
gcc/config/riscv/vector.md | 144 ++++++++++--------
.../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +-
5 files changed, 118 insertions(+), 77 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index ebbaac255f9..e4881786b53 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -177,6 +177,7 @@ rtx expand_builtin (unsigned int, tree, rtx);
bool check_builtin_call (location_t, vec<location_t>, unsigned int,
tree, unsigned int, tree *);
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
+bool float_point_mode_supported_p (machine_mode mode);
bool legitimize_move (rtx, rtx);
void emit_vlmax_vsetvl (machine_mode, rtx);
void emit_hard_vlmax_vsetvl (machine_mode, rtx);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 49752cd8899..1cc157f1858 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -418,6 +418,18 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
&& IN_RANGE (INTVAL (elt), minval, maxval));
}
+/* Return true if the inner of mode is HFmode when ZVFH enabled, or other
+ float point machine mode. */
+bool
+float_point_mode_supported_p (machine_mode mode)
+{
+ machine_mode inner_mode = GET_MODE_INNER (mode);
+
+ gcc_assert (FLOAT_MODE_P (inner_mode));
+
+ return inner_mode == HFmode ? TARGET_ZVFH : true;
+}
+
/* Return true if VEC is a constant in which every element is in the range
[MINVAL, MAXVAL]. The elements do not need to have the same value.
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..234b712bc9d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..438670e8aec 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1364,7 +1364,7 @@ (define_insn "*pred_broadcast<mode>"
(vec_duplicate:VF
(match_operand:<VEL> 3 "direct_broadcast_operand" " f, f,Wdm,Wdm,Wdm,Wdm, f, f"))
(match_operand:VF 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vfmv.v.f\t%0,%3
vfmv.v.f\t%0,%3
@@ -5685,7 +5685,7 @@ (define_insn "@pred_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5705,7 +5705,7 @@ (define_insn "@pred_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5728,7 +5728,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5749,7 +5749,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5772,7 +5772,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(vec_duplicate:VF
(match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5795,7 +5795,7 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfr<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5815,7 +5815,7 @@ (define_insn "@pred_<copysign><mode>"
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS)
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfsgnj<nx>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfsgnj")
(set_attr "mode" "<MODE>")])
@@ -5836,7 +5836,7 @@ (define_insn "@pred_<copysign><mode>_scalar"
(vec_duplicate:VF
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS)
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfsgnj<nx>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfsgnj")
(set_attr "mode" "<MODE>")])
@@ -5894,7 +5894,7 @@ (define_insn "*pred_<madd_msub><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<madd_msub>.vv\t%0,%3,%4%p1
vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
@@ -5927,7 +5927,7 @@ (define_insn "*pred_<macc_msac><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<macc_msac>.vv\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
@@ -5960,7 +5960,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[2], operands[5])
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
@@ -6021,7 +6021,7 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
(match_operand:VF 3 "register_operand" " 0, vr, 0, vr"))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 3)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<madd_msub>.vf\t%0,%2,%4%p1
vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
@@ -6055,7 +6055,7 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<macc_msac>.vf\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
@@ -6089,7 +6089,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
"@
@@ -6154,7 +6154,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
@@ -6188,7 +6188,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
@@ -6222,7 +6222,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr")))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[2], operands[5])
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
@@ -6285,7 +6285,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
(match_operand:VF 3 "register_operand" " 0, vr, 0, vr")))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 3)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
@@ -6320,7 +6320,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
@@ -6355,7 +6355,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr")))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
"@
@@ -6399,7 +6399,7 @@ (define_insn "@pred_<optab><mode>"
(any_float_unop:VF
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
@@ -6422,7 +6422,7 @@ (define_insn "@pred_<optab><mode>"
(any_float_unop_nofrm:VF
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
@@ -6445,7 +6445,7 @@ (define_insn "@pred_<misc_op><mode>"
(unspec:VF
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<misc_op>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -6464,7 +6464,7 @@ (define_insn "@pred_class<mode>"
(unspec:<VCONVERT>
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfclass.v\t%0,%3%p1"
[(set_attr "type" "vfclass")
(set_attr "mode" "<MODE>")])
@@ -6497,7 +6497,7 @@ (define_insn "@pred_dual_widen_<optab><mode>"
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6522,7 +6522,7 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
(vec_duplicate:<V_DOUBLE_TRUNC>
(match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6545,7 +6545,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>"
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.wv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6569,7 +6569,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
(vec_duplicate:<V_DOUBLE_TRUNC>
(match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.wf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6602,7 +6602,7 @@ (define_insn "@pred_widen_mul_<optab><mode>"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<macc_msac>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6629,7 +6629,7 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<macc_msac>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6656,7 +6656,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6684,7 +6684,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6728,7 +6728,8 @@ (define_insn "*pred_cmp<mode>"
[(match_operand:VF 4 "register_operand" " vr, vr")
(match_operand:VF 5 "register_operand" " vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vv\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6747,7 +6748,7 @@ (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
[(match_operand:VF 3 "register_operand" " vr")
(match_operand:VF 4 "register_operand" " vr")])
(match_dup 1)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B2.vv\t%0,%3,%4,v0.t"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")
@@ -6771,7 +6772,8 @@ (define_insn "*pred_cmp<mode>_narrow"
[(match_operand:VF 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
(match_operand:VF 5 "register_operand" " vr, vr, 0, 0, vr, 0, 0, vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
- "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vv\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6809,7 +6811,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
(vec_duplicate:VF
(match_operand:<VEL> 4 "register_operand" " f"))])
(match_dup 1)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B2.vf\t%0,%3,%4,v0.t"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")
@@ -6834,7 +6836,8 @@ (define_insn "*pred_cmp<mode>_scalar"
(vec_duplicate:VF
(match_operand:<VEL> 5 "register_operand" " f, f"))])
(match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6855,7 +6858,8 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(vec_duplicate:VF
(match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))])
(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6893,7 +6897,7 @@ (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
(match_operand:<VEL> 4 "register_operand" " f"))
(match_operand:VF 3 "register_operand" " vr")])
(match_dup 1)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B2.vf\t%0,%3,%4,v0.t"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")
@@ -6918,7 +6922,8 @@ (define_insn "*pred_eqne<mode>_scalar"
(match_operand:<VEL> 5 "register_operand" " f, f"))
(match_operand:VF 4 "register_operand" " vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6939,7 +6944,8 @@ (define_insn "*pred_eqne<mode>_scalar_narrow"
(match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
(match_operand:VF 4 "register_operand" " vr, 0, 0, vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6966,7 +6972,7 @@ (define_insn "@pred_merge<mode>_scalar"
(match_operand:VF 2 "register_operand" " vr,vr")
(match_operand:<VM> 4 "register_operand" " vm,vm"))
(match_operand:VF 1 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfmerge.vfm\t%0,%2,%3,%4"
[(set_attr "type" "vfmerge")
(set_attr "mode" "<MODE>")])
@@ -6994,7 +7000,7 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
(unspec:<VCONVERT>
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS)
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
(set_attr "mode" "<MODE>")])
@@ -7013,7 +7019,7 @@ (define_insn "@pred_<fix_cvt><mode>"
(any_fix:<VCONVERT>
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
(set_attr "mode" "<MODE>")])
@@ -7034,7 +7040,7 @@ (define_insn "@pred_<float_cvt><mode>"
(any_float:VF
(match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfcvtitof")
(set_attr "mode" "<MODE>")])
@@ -7062,7 +7068,7 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
(unspec:VWCONVERTI
[(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")] VFCVTS)
(match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<VNCONVERT>mode)"
"vfwcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7081,7 +7087,7 @@ (define_insn "@pred_widen_<fix_cvt><mode>"
(any_fix:VWCONVERTI
(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
(match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<VNCONVERT>mode)"
"vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7100,7 +7106,7 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(any_float:VF
(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfwcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtitof")
(set_attr "mode" "<VNCONVERT>")])
@@ -7119,7 +7125,7 @@ (define_insn "@pred_extend<mode>"
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -7147,7 +7153,7 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
(unspec:<VNCONVERT>
[(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS)
(match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfncvt.x<v_su>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7166,7 +7172,7 @@ (define_insn "@pred_narrow_<fix_cvt><mode>"
(any_fix:<VNCONVERT>
(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<VNCONVERT>mode)"
"vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7187,7 +7193,7 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(any_float:<VNCONVERT>
(match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<VNCONVERT>mode)"
"vfncvt.f.x<u>.w\t%0,%3%p1"
[(set_attr "type" "vfncvtitof")
(set_attr "mode" "<VNCONVERT>")])
@@ -7208,7 +7214,7 @@ (define_insn "@pred_trunc<mode>"
(float_truncate:<V_DOUBLE_TRUNC>
(match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -7228,7 +7234,7 @@ (define_insn "@pred_rod_trunc<mode>"
[(float_truncate:<V_DOUBLE_TRUNC>
(match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
(match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfncvt.rod.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -7389,7 +7395,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1>"
(parallel [(const_int 0)])))
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+ "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
@@ -7413,7 +7420,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve64>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 64
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
@@ -7437,7 +7445,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 32
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
@@ -7462,7 +7471,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1>"
(parallel [(const_int 0)])))
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+ "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
@@ -7487,7 +7497,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve64>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 64
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
@@ -7512,7 +7523,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve32>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 32
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
@@ -7533,7 +7545,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1>"
(match_operand:VWF 3 "register_operand" " vr, vr")
(match_operand:<VWLMUL1> 4 "register_operand" " vr, vr")
(match_operand:<VWLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+ "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
(set_attr "mode" "<MODE>")])
@@ -7554,7 +7567,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>"
(match_operand:VWF_ZVE64 3 "register_operand" " vr, vr")
(match_operand:<VWLMUL1_ZVE64> 4 "register_operand" " vr, vr")
(match_operand:<VWLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 64
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
(set_attr "mode" "<MODE>")])
@@ -7657,7 +7671,7 @@ (define_insn "*pred_extract_first<mode>"
(match_operand:VF 1 "register_operand" "vr")
(parallel [(const_int 0)]))
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfmv.f.s\t%0,%1"
[(set_attr "type" "vfmovvf")
(set_attr "mode" "<MODE>")])
@@ -7778,7 +7792,7 @@ (define_insn "@pred_slide<ud><mode>"
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:<VEL> 4 "register_operand" " f, f, f, f")] VFSLIDES1))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfslide<ud>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfslide<ud>")
(set_attr "mode" "<MODE>")])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 0923b6bc4d2..f1a29b639e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -3,6 +3,8 @@
#include "riscv_vector.h"
+typedef _Float16 float16_t;
+
vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
}
@@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
}
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16mf4(base, vl);
+}
+
+vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16m8(base, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
-
+/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-07 8:42 ` Li, Pan2
@ 2023-06-08 6:07 ` Li, Pan2
0 siblings, 0 replies; 39+ messages in thread
From: Li, Pan2 @ 2023-06-08 6:07 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: Robin Dapp, jeffreyalaw, Wang, Yanzhang
[-- Attachment #1: Type: text/plain, Size: 16460 bytes --]
Update the PATCH v7 (please help to ignore v6) for this change, thanks Juzhe for the suggestion.
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621012.html
Pan
From: Li, Pan2
Sent: Wednesday, June 7, 2023 4:43 PM
To: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: RE: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
Thanks Juzhe for reviewing. I see, this way may have even smaller code change which treats the zvfhmin as minimal base sub extension.
I will have a try for PATCH V6.
Pan
From: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai> <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
Sent: Wednesday, June 7, 2023 4:27 PM
To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>
Cc: Robin Dapp <rdapp.gcc@gmail.com<mailto:rdapp.gcc@gmail.com>>; jeffreyalaw <jeffreyalaw@gmail.com<mailto:jeffreyalaw@gmail.com>>; Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
Subject: Re: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
In this patch, you add TARGET_ZVFH into VF iterator which is not correct.
When TARGET_ZVFH is true, TARGET_ZVFHMIN is always true.
For vfadd, it is true we should enable "vfadd" for TARGET_ZVFH
For vle16, we should enable for TARGET_ZVFHMIN.
This patch will disable both "vle16" and "vfadd" for FP16 on ZVFHMIN which is not correct.
I think you should allow all FP16 vector modes in iterator enable by TARGET_VECTOR_FP_ELN_16 (TARGET_ZVFHMIN).
Then, when zvfhmin is enabled, all FP16 instructions are enabled by default.
To gate the situation only enable when TARGET_ZVFH, you add the predicate as below:
For example:
vfadd.vv (need
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
(match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(any_float_binop:VF
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
bool
float_mode_supported_p (machine_mode mode)
{
if (GET_MODE_INNER (mode) == HFmode)
return TARGET_ZVFH;
return true;
}
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-06-07 16:06
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; rdapp.gcc<mailto:rdapp.gcc@gmail.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Add requirement to VF,
VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF.
* config/riscv/vector.md: Adjust FP convert to V_CONVERT_F
and VCONVERTF, and fix V_WHOLE and V_FRACT.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md | 79 +++++++++++++------
gcc/config/riscv/vector.md | 46 +++++------
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 ++++++
3 files changed, 104 insertions(+), 46 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..e6c2ecf7c86 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [
])
(define_mode_iterator VF [
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
- (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+ (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_ZVFH")
+ (VNx4HF "TARGET_ZVFH")
+ (VNx8HF "TARGET_ZVFH")
+ (VNx16HF "TARGET_ZVFH")
+ (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
@@ -512,12 +515,12 @@ (define_mode_iterator VWEXTF [
])
(define_mode_iterator VWCONVERTI [
- (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
- (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx4SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx8SI "TARGET_VECTOR_ELEN_FP_16")
- (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
- (VNx32SI "TARGET_MIN_VLEN >= 128 && TARGET_VECTOR_ELEN_FP_16")
+ (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+ (VNx2SI "TARGET_ZVFH")
+ (VNx4SI "TARGET_ZVFH")
+ (VNx8SI "TARGET_ZVFH")
+ (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+ (VNx32SI "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
@@ -526,6 +529,21 @@ (define_mode_iterator VWCONVERTI [
(VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator VCONVERTF [
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+
+ (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
+ (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VQEXTI [
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
@@ -1181,6 +1199,21 @@ (define_mode_attr V_DOUBLE_TRUNC [
(VNx16DF "VNx16SF")
])
+(define_mode_attr V_CONVERT_F [
+ (VNx1SF "VNx1HF")
+ (VNx2SF "VNx2HF")
+ (VNx4SF "VNx4HF")
+ (VNx8SF "VNx8HF")
+ (VNx16SF "VNx16HF")
+ (VNx32SF "VNx32HF")
+
+ (VNx1DF "VNx1SF")
+ (VNx2DF "VNx2SF")
+ (VNx4DF "VNx4SF")
+ (VNx8DF "VNx8SF")
+ (VNx16DF "VNx16SF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
(VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
(VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..97162b07642 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7106,23 +7106,23 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_extend<mode>"
- [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
- (if_then_else:VWEXTF
+ [(set (match_operand:VCONVERTF 0 "register_operand" "=&vr, &vr")
+ (if_then_else:VCONVERTF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
- (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
+ (float_extend:VCONVERTF
+ (match_operand:<V_CONVERT_F> 3 "register_operand" " vr, vr"))
+ (match_operand:VCONVERTF 2 "vector_merge_operand" " vu, 0")))]
"TARGET_VECTOR"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
@@ -7193,25 +7193,25 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_trunc<mode>"
- [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
- (if_then_else:<V_DOUBLE_TRUNC>
+ [(set (match_operand:<V_CONVERT_F> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
+ (if_then_else:<V_CONVERT_F>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
- (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (float_truncate:<V_DOUBLE_TRUNC>
- (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
- (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
+ (float_truncate:<V_CONVERT_F>
+ (match_operand:VCONVERTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
+ (match_operand:<V_CONVERT_F> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_CONVERT_F>")])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v7] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-08 6:06 ` [PATCH v7] " pan2.li
@ 2023-06-08 6:09 ` juzhe.zhong
2023-06-08 6:31 ` Li, Pan2
0 siblings, 1 reply; 39+ messages in thread
From: juzhe.zhong @ 2023-06-08 6:09 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: Robin Dapp, jeffreyalaw, pan2.li, yanzhang.wang
[-- Attachment #1: Type: text/plain, Size: 39510 bytes --]
Rename float_point_mode_supported_p into float_mode_supported_p
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-06-08 14:06
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang
Subject: [PATCH v7] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
iterators of RVV. And then the ZVFH will leverage one function as
the gate for FP16 supported or not.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv-protos.h (float_point_mode_supported_p):
New function to float point is supported by extension.
* config/riscv/riscv-v.cc (float_point_mode_supported_p):
Ditto.
* config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
* config/riscv/vector.md: Add condition to FP define insn.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
for ZVFHMIN.
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 12 ++
gcc/config/riscv/vector-iterators.md | 23 +--
gcc/config/riscv/vector.md | 144 ++++++++++--------
.../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +-
5 files changed, 118 insertions(+), 77 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index ebbaac255f9..e4881786b53 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -177,6 +177,7 @@ rtx expand_builtin (unsigned int, tree, rtx);
bool check_builtin_call (location_t, vec<location_t>, unsigned int,
tree, unsigned int, tree *);
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
+bool float_point_mode_supported_p (machine_mode mode);
bool legitimize_move (rtx, rtx);
void emit_vlmax_vsetvl (machine_mode, rtx);
void emit_hard_vlmax_vsetvl (machine_mode, rtx);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 49752cd8899..1cc157f1858 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -418,6 +418,18 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
&& IN_RANGE (INTVAL (elt), minval, maxval));
}
+/* Return true if the inner of mode is HFmode when ZVFH enabled, or other
+ float point machine mode. */
+bool
+float_point_mode_supported_p (machine_mode mode)
+{
+ machine_mode inner_mode = GET_MODE_INNER (mode);
+
+ gcc_assert (FLOAT_MODE_P (inner_mode));
+
+ return inner_mode == HFmode ? TARGET_ZVFH : true;
+}
+
/* Return true if VEC is a constant in which every element is in the range
[MINVAL, MAXVAL]. The elements do not need to have the same value.
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..234b712bc9d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..438670e8aec 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1364,7 +1364,7 @@ (define_insn "*pred_broadcast<mode>"
(vec_duplicate:VF
(match_operand:<VEL> 3 "direct_broadcast_operand" " f, f,Wdm,Wdm,Wdm,Wdm, f, f"))
(match_operand:VF 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vfmv.v.f\t%0,%3
vfmv.v.f\t%0,%3
@@ -5685,7 +5685,7 @@ (define_insn "@pred_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5705,7 +5705,7 @@ (define_insn "@pred_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5728,7 +5728,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5749,7 +5749,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5772,7 +5772,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(vec_duplicate:VF
(match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5795,7 +5795,7 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfr<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5815,7 +5815,7 @@ (define_insn "@pred_<copysign><mode>"
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS)
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfsgnj<nx>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfsgnj")
(set_attr "mode" "<MODE>")])
@@ -5836,7 +5836,7 @@ (define_insn "@pred_<copysign><mode>_scalar"
(vec_duplicate:VF
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS)
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfsgnj<nx>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfsgnj")
(set_attr "mode" "<MODE>")])
@@ -5894,7 +5894,7 @@ (define_insn "*pred_<madd_msub><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<madd_msub>.vv\t%0,%3,%4%p1
vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
@@ -5927,7 +5927,7 @@ (define_insn "*pred_<macc_msac><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<macc_msac>.vv\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
@@ -5960,7 +5960,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[2], operands[5])
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
@@ -6021,7 +6021,7 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
(match_operand:VF 3 "register_operand" " 0, vr, 0, vr"))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 3)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<madd_msub>.vf\t%0,%2,%4%p1
vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
@@ -6055,7 +6055,7 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<macc_msac>.vf\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
@@ -6089,7 +6089,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
"@
@@ -6154,7 +6154,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
@@ -6188,7 +6188,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
@@ -6222,7 +6222,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr")))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[2], operands[5])
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
@@ -6285,7 +6285,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
(match_operand:VF 3 "register_operand" " 0, vr, 0, vr")))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 3)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
@@ -6320,7 +6320,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
@@ -6355,7 +6355,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr")))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
"@
@@ -6399,7 +6399,7 @@ (define_insn "@pred_<optab><mode>"
(any_float_unop:VF
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
@@ -6422,7 +6422,7 @@ (define_insn "@pred_<optab><mode>"
(any_float_unop_nofrm:VF
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
@@ -6445,7 +6445,7 @@ (define_insn "@pred_<misc_op><mode>"
(unspec:VF
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<misc_op>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -6464,7 +6464,7 @@ (define_insn "@pred_class<mode>"
(unspec:<VCONVERT>
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfclass.v\t%0,%3%p1"
[(set_attr "type" "vfclass")
(set_attr "mode" "<MODE>")])
@@ -6497,7 +6497,7 @@ (define_insn "@pred_dual_widen_<optab><mode>"
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6522,7 +6522,7 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
(vec_duplicate:<V_DOUBLE_TRUNC>
(match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6545,7 +6545,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>"
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.wv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6569,7 +6569,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
(vec_duplicate:<V_DOUBLE_TRUNC>
(match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.wf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6602,7 +6602,7 @@ (define_insn "@pred_widen_mul_<optab><mode>"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<macc_msac>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6629,7 +6629,7 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<macc_msac>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6656,7 +6656,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6684,7 +6684,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6728,7 +6728,8 @@ (define_insn "*pred_cmp<mode>"
[(match_operand:VF 4 "register_operand" " vr, vr")
(match_operand:VF 5 "register_operand" " vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vv\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6747,7 +6748,7 @@ (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
[(match_operand:VF 3 "register_operand" " vr")
(match_operand:VF 4 "register_operand" " vr")])
(match_dup 1)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B2.vv\t%0,%3,%4,v0.t"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")
@@ -6771,7 +6772,8 @@ (define_insn "*pred_cmp<mode>_narrow"
[(match_operand:VF 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
(match_operand:VF 5 "register_operand" " vr, vr, 0, 0, vr, 0, 0, vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
- "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vv\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6809,7 +6811,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
(vec_duplicate:VF
(match_operand:<VEL> 4 "register_operand" " f"))])
(match_dup 1)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B2.vf\t%0,%3,%4,v0.t"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")
@@ -6834,7 +6836,8 @@ (define_insn "*pred_cmp<mode>_scalar"
(vec_duplicate:VF
(match_operand:<VEL> 5 "register_operand" " f, f"))])
(match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6855,7 +6858,8 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(vec_duplicate:VF
(match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))])
(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6893,7 +6897,7 @@ (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
(match_operand:<VEL> 4 "register_operand" " f"))
(match_operand:VF 3 "register_operand" " vr")])
(match_dup 1)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B2.vf\t%0,%3,%4,v0.t"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")
@@ -6918,7 +6922,8 @@ (define_insn "*pred_eqne<mode>_scalar"
(match_operand:<VEL> 5 "register_operand" " f, f"))
(match_operand:VF 4 "register_operand" " vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6939,7 +6944,8 @@ (define_insn "*pred_eqne<mode>_scalar_narrow"
(match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
(match_operand:VF 4 "register_operand" " vr, 0, 0, vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6966,7 +6972,7 @@ (define_insn "@pred_merge<mode>_scalar"
(match_operand:VF 2 "register_operand" " vr,vr")
(match_operand:<VM> 4 "register_operand" " vm,vm"))
(match_operand:VF 1 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfmerge.vfm\t%0,%2,%3,%4"
[(set_attr "type" "vfmerge")
(set_attr "mode" "<MODE>")])
@@ -6994,7 +7000,7 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
(unspec:<VCONVERT>
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS)
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
(set_attr "mode" "<MODE>")])
@@ -7013,7 +7019,7 @@ (define_insn "@pred_<fix_cvt><mode>"
(any_fix:<VCONVERT>
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
(set_attr "mode" "<MODE>")])
@@ -7034,7 +7040,7 @@ (define_insn "@pred_<float_cvt><mode>"
(any_float:VF
(match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfcvtitof")
(set_attr "mode" "<MODE>")])
@@ -7062,7 +7068,7 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
(unspec:VWCONVERTI
[(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")] VFCVTS)
(match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<VNCONVERT>mode)"
"vfwcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7081,7 +7087,7 @@ (define_insn "@pred_widen_<fix_cvt><mode>"
(any_fix:VWCONVERTI
(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
(match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<VNCONVERT>mode)"
"vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7100,7 +7106,7 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(any_float:VF
(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfwcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtitof")
(set_attr "mode" "<VNCONVERT>")])
@@ -7119,7 +7125,7 @@ (define_insn "@pred_extend<mode>"
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -7147,7 +7153,7 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
(unspec:<VNCONVERT>
[(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS)
(match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfncvt.x<v_su>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7166,7 +7172,7 @@ (define_insn "@pred_narrow_<fix_cvt><mode>"
(any_fix:<VNCONVERT>
(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<VNCONVERT>mode)"
"vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7187,7 +7193,7 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(any_float:<VNCONVERT>
(match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<VNCONVERT>mode)"
"vfncvt.f.x<u>.w\t%0,%3%p1"
[(set_attr "type" "vfncvtitof")
(set_attr "mode" "<VNCONVERT>")])
@@ -7208,7 +7214,7 @@ (define_insn "@pred_trunc<mode>"
(float_truncate:<V_DOUBLE_TRUNC>
(match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -7228,7 +7234,7 @@ (define_insn "@pred_rod_trunc<mode>"
[(float_truncate:<V_DOUBLE_TRUNC>
(match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
(match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfncvt.rod.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -7389,7 +7395,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1>"
(parallel [(const_int 0)])))
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+ "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
@@ -7413,7 +7420,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve64>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 64
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
@@ -7437,7 +7445,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 32
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
@@ -7462,7 +7471,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1>"
(parallel [(const_int 0)])))
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+ "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
@@ -7487,7 +7497,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve64>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 64
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
@@ -7512,7 +7523,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve32>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 32
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
@@ -7533,7 +7545,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1>"
(match_operand:VWF 3 "register_operand" " vr, vr")
(match_operand:<VWLMUL1> 4 "register_operand" " vr, vr")
(match_operand:<VWLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+ "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
(set_attr "mode" "<MODE>")])
@@ -7554,7 +7567,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>"
(match_operand:VWF_ZVE64 3 "register_operand" " vr, vr")
(match_operand:<VWLMUL1_ZVE64> 4 "register_operand" " vr, vr")
(match_operand:<VWLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 64
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
(set_attr "mode" "<MODE>")])
@@ -7657,7 +7671,7 @@ (define_insn "*pred_extract_first<mode>"
(match_operand:VF 1 "register_operand" "vr")
(parallel [(const_int 0)]))
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfmv.f.s\t%0,%1"
[(set_attr "type" "vfmovvf")
(set_attr "mode" "<MODE>")])
@@ -7778,7 +7792,7 @@ (define_insn "@pred_slide<ud><mode>"
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:<VEL> 4 "register_operand" " f, f, f, f")] VFSLIDES1))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfslide<ud>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfslide<ud>")
(set_attr "mode" "<MODE>")])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 0923b6bc4d2..f1a29b639e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -3,6 +3,8 @@
#include "riscv_vector.h"
+typedef _Float16 float16_t;
+
vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
}
@@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
}
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16mf4(base, vl);
+}
+
+vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16m8(base, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
-
+/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-06 12:36 [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern pan2.li
` (6 preceding siblings ...)
2023-06-08 6:06 ` [PATCH v7] " pan2.li
@ 2023-06-08 6:29 ` pan2.li
2023-06-08 6:34 ` juzhe.zhong
2023-06-09 5:59 ` [PATCH v9] " pan2.li
2023-06-09 7:07 ` [PATCH v10] " pan2.li
9 siblings, 1 reply; 39+ messages in thread
From: pan2.li @ 2023-06-08 6:29 UTC (permalink / raw)
To: gcc-patches
Cc: juzhe.zhong, rdapp.gcc, jeffreyalaw, pan2.li, yanzhang.wang, kito.cheng
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
iterators of RVV. And then the ZVFH will leverage one function as
the gate for FP16 supported or not.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv-protos.h (float_mode_supported_p):
New function to float point is supported by extension.
* config/riscv/riscv-v.cc (float_mode_supported_p):
Ditto.
* config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
* config/riscv/vector.md: Add condition to FP define insn.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
for ZVFHMIN.
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 12 ++
gcc/config/riscv/vector-iterators.md | 23 +--
gcc/config/riscv/vector.md | 144 ++++++++++--------
.../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +-
5 files changed, 118 insertions(+), 77 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index ebbaac255f9..1f606f59ce1 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -177,6 +177,7 @@ rtx expand_builtin (unsigned int, tree, rtx);
bool check_builtin_call (location_t, vec<location_t>, unsigned int,
tree, unsigned int, tree *);
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
+bool float_mode_supported_p (machine_mode mode);
bool legitimize_move (rtx, rtx);
void emit_vlmax_vsetvl (machine_mode, rtx);
void emit_hard_vlmax_vsetvl (machine_mode, rtx);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 49752cd8899..fe4eb058ec0 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -418,6 +418,18 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
&& IN_RANGE (INTVAL (elt), minval, maxval));
}
+/* Return true if the inner of mode is HFmode when ZVFH enabled, or other
+ float point machine mode. */
+bool
+float_mode_supported_p (machine_mode mode)
+{
+ machine_mode inner_mode = GET_MODE_INNER (mode);
+
+ gcc_assert (FLOAT_MODE_P (inner_mode));
+
+ return inner_mode == HFmode ? TARGET_ZVFH : true;
+}
+
/* Return true if VEC is a constant in which every element is in the range
[MINVAL, MAXVAL]. The elements do not need to have the same value.
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..234b712bc9d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..2fe0233f102 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1364,7 +1364,7 @@ (define_insn "*pred_broadcast<mode>"
(vec_duplicate:VF
(match_operand:<VEL> 3 "direct_broadcast_operand" " f, f,Wdm,Wdm,Wdm,Wdm, f, f"))
(match_operand:VF 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"@
vfmv.v.f\t%0,%3
vfmv.v.f\t%0,%3
@@ -5685,7 +5685,7 @@ (define_insn "@pred_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5705,7 +5705,7 @@ (define_insn "@pred_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5728,7 +5728,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5749,7 +5749,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5772,7 +5772,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(vec_duplicate:VF
(match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5795,7 +5795,7 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfr<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5815,7 +5815,7 @@ (define_insn "@pred_<copysign><mode>"
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS)
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfsgnj<nx>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfsgnj")
(set_attr "mode" "<MODE>")])
@@ -5836,7 +5836,7 @@ (define_insn "@pred_<copysign><mode>_scalar"
(vec_duplicate:VF
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS)
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfsgnj<nx>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfsgnj")
(set_attr "mode" "<MODE>")])
@@ -5894,7 +5894,7 @@ (define_insn "*pred_<madd_msub><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"@
vf<madd_msub>.vv\t%0,%3,%4%p1
vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
@@ -5927,7 +5927,7 @@ (define_insn "*pred_<macc_msac><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"@
vf<macc_msac>.vv\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
@@ -5960,7 +5960,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[2], operands[5])
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
@@ -6021,7 +6021,7 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
(match_operand:VF 3 "register_operand" " 0, vr, 0, vr"))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 3)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"@
vf<madd_msub>.vf\t%0,%2,%4%p1
vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
@@ -6055,7 +6055,7 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"@
vf<macc_msac>.vf\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
@@ -6089,7 +6089,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
"@
@@ -6154,7 +6154,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"@
vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
@@ -6188,7 +6188,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"@
vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
@@ -6222,7 +6222,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr")))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[2], operands[5])
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
@@ -6285,7 +6285,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
(match_operand:VF 3 "register_operand" " 0, vr, 0, vr")))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 3)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"@
vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
@@ -6320,7 +6320,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"@
vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
@@ -6355,7 +6355,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr")))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
"@
@@ -6399,7 +6399,7 @@ (define_insn "@pred_<optab><mode>"
(any_float_unop:VF
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<insn>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
@@ -6422,7 +6422,7 @@ (define_insn "@pred_<optab><mode>"
(any_float_unop_nofrm:VF
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<insn>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
@@ -6445,7 +6445,7 @@ (define_insn "@pred_<misc_op><mode>"
(unspec:VF
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<misc_op>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -6464,7 +6464,7 @@ (define_insn "@pred_class<mode>"
(unspec:<VCONVERT>
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfclass.v\t%0,%3%p1"
[(set_attr "type" "vfclass")
(set_attr "mode" "<MODE>")])
@@ -6497,7 +6497,7 @@ (define_insn "@pred_dual_widen_<optab><mode>"
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6522,7 +6522,7 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
(vec_duplicate:<V_DOUBLE_TRUNC>
(match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6545,7 +6545,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>"
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.wv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6569,7 +6569,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
(vec_duplicate:<V_DOUBLE_TRUNC>
(match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.wf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6602,7 +6602,7 @@ (define_insn "@pred_widen_mul_<optab><mode>"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<macc_msac>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6629,7 +6629,7 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<macc_msac>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6656,7 +6656,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6684,7 +6684,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6728,7 +6728,8 @@ (define_insn "*pred_cmp<mode>"
[(match_operand:VF 4 "register_operand" " vr, vr")
(match_operand:VF 5 "register_operand" " vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vmf%B3.vv\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6747,7 +6748,7 @@ (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
[(match_operand:VF 3 "register_operand" " vr")
(match_operand:VF 4 "register_operand" " vr")])
(match_dup 1)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vmf%B2.vv\t%0,%3,%4,v0.t"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")
@@ -6771,7 +6772,8 @@ (define_insn "*pred_cmp<mode>_narrow"
[(match_operand:VF 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
(match_operand:VF 5 "register_operand" " vr, vr, 0, 0, vr, 0, 0, vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
- "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vmf%B3.vv\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6809,7 +6811,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
(vec_duplicate:VF
(match_operand:<VEL> 4 "register_operand" " f"))])
(match_dup 1)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vmf%B2.vf\t%0,%3,%4,v0.t"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")
@@ -6834,7 +6836,8 @@ (define_insn "*pred_cmp<mode>_scalar"
(vec_duplicate:VF
(match_operand:<VEL> 5 "register_operand" " f, f"))])
(match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6855,7 +6858,8 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(vec_duplicate:VF
(match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))])
(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6893,7 +6897,7 @@ (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
(match_operand:<VEL> 4 "register_operand" " f"))
(match_operand:VF 3 "register_operand" " vr")])
(match_dup 1)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vmf%B2.vf\t%0,%3,%4,v0.t"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")
@@ -6918,7 +6922,8 @@ (define_insn "*pred_eqne<mode>_scalar"
(match_operand:<VEL> 5 "register_operand" " f, f"))
(match_operand:VF 4 "register_operand" " vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6939,7 +6944,8 @@ (define_insn "*pred_eqne<mode>_scalar_narrow"
(match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
(match_operand:VF 4 "register_operand" " vr, 0, 0, vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6966,7 +6972,7 @@ (define_insn "@pred_merge<mode>_scalar"
(match_operand:VF 2 "register_operand" " vr,vr")
(match_operand:<VM> 4 "register_operand" " vm,vm"))
(match_operand:VF 1 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfmerge.vfm\t%0,%2,%3,%4"
[(set_attr "type" "vfmerge")
(set_attr "mode" "<MODE>")])
@@ -6994,7 +7000,7 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
(unspec:<VCONVERT>
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS)
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
(set_attr "mode" "<MODE>")])
@@ -7013,7 +7019,7 @@ (define_insn "@pred_<fix_cvt><mode>"
(any_fix:<VCONVERT>
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
(set_attr "mode" "<MODE>")])
@@ -7034,7 +7040,7 @@ (define_insn "@pred_<float_cvt><mode>"
(any_float:VF
(match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfcvtitof")
(set_attr "mode" "<MODE>")])
@@ -7062,7 +7068,7 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
(unspec:VWCONVERTI
[(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")] VFCVTS)
(match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
"vfwcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7081,7 +7087,7 @@ (define_insn "@pred_widen_<fix_cvt><mode>"
(any_fix:VWCONVERTI
(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
(match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
"vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7100,7 +7106,7 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(any_float:VF
(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfwcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtitof")
(set_attr "mode" "<VNCONVERT>")])
@@ -7119,7 +7125,7 @@ (define_insn "@pred_extend<mode>"
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -7147,7 +7153,7 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
(unspec:<VNCONVERT>
[(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS)
(match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfncvt.x<v_su>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7166,7 +7172,7 @@ (define_insn "@pred_narrow_<fix_cvt><mode>"
(any_fix:<VNCONVERT>
(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
"vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7187,7 +7193,7 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(any_float:<VNCONVERT>
(match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
"vfncvt.f.x<u>.w\t%0,%3%p1"
[(set_attr "type" "vfncvtitof")
(set_attr "mode" "<VNCONVERT>")])
@@ -7208,7 +7214,7 @@ (define_insn "@pred_trunc<mode>"
(float_truncate:<V_DOUBLE_TRUNC>
(match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -7228,7 +7234,7 @@ (define_insn "@pred_rod_trunc<mode>"
[(float_truncate:<V_DOUBLE_TRUNC>
(match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
(match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfncvt.rod.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -7389,7 +7395,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1>"
(parallel [(const_int 0)])))
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+ "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
@@ -7413,7 +7420,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve64>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 64
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
@@ -7437,7 +7445,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 32
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
@@ -7462,7 +7471,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1>"
(parallel [(const_int 0)])))
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+ "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
@@ -7487,7 +7497,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve64>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 64
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
@@ -7512,7 +7523,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve32>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 32
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
@@ -7533,7 +7545,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1>"
(match_operand:VWF 3 "register_operand" " vr, vr")
(match_operand:<VWLMUL1> 4 "register_operand" " vr, vr")
(match_operand:<VWLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+ "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
(set_attr "mode" "<MODE>")])
@@ -7554,7 +7567,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>"
(match_operand:VWF_ZVE64 3 "register_operand" " vr, vr")
(match_operand:<VWLMUL1_ZVE64> 4 "register_operand" " vr, vr")
(match_operand:<VWLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 64
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
(set_attr "mode" "<MODE>")])
@@ -7657,7 +7671,7 @@ (define_insn "*pred_extract_first<mode>"
(match_operand:VF 1 "register_operand" "vr")
(parallel [(const_int 0)]))
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfmv.f.s\t%0,%1"
[(set_attr "type" "vfmovvf")
(set_attr "mode" "<MODE>")])
@@ -7778,7 +7792,7 @@ (define_insn "@pred_slide<ud><mode>"
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:<VEL> 4 "register_operand" " f, f, f, f")] VFSLIDES1))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfslide<ud>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfslide<ud>")
(set_attr "mode" "<MODE>")])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 0923b6bc4d2..f1a29b639e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -3,6 +3,8 @@
#include "riscv_vector.h"
+typedef _Float16 float16_t;
+
vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
}
@@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
}
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16mf4(base, vl);
+}
+
+vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16m8(base, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
-
+/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: [PATCH v7] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-08 6:09 ` juzhe.zhong
@ 2023-06-08 6:31 ` Li, Pan2
0 siblings, 0 replies; 39+ messages in thread
From: Li, Pan2 @ 2023-06-08 6:31 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: Robin Dapp, jeffreyalaw, Wang, Yanzhang
[-- Attachment #1: Type: text/plain, Size: 40909 bytes --]
Sure, update it in PATCH v8.
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621016.html
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Thursday, June 8, 2023 2:09 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v7] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
Rename float_point_mode_supported_p into float_mode_supported_p
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-06-08 14:06
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; rdapp.gcc<mailto:rdapp.gcc@gmail.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: [PATCH v7] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
iterators of RVV. And then the ZVFH will leverage one function as
the gate for FP16 supported or not.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
gcc/ChangeLog:
* config/riscv/riscv-protos.h (float_point_mode_supported_p):
New function to float point is supported by extension.
* config/riscv/riscv-v.cc (float_point_mode_supported_p):
Ditto.
* config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
* config/riscv/vector.md: Add condition to FP define insn.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
for ZVFHMIN.
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 12 ++
gcc/config/riscv/vector-iterators.md | 23 +--
gcc/config/riscv/vector.md | 144 ++++++++++--------
.../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +-
5 files changed, 118 insertions(+), 77 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index ebbaac255f9..e4881786b53 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -177,6 +177,7 @@ rtx expand_builtin (unsigned int, tree, rtx);
bool check_builtin_call (location_t, vec<location_t>, unsigned int,
tree, unsigned int, tree *);
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
+bool float_point_mode_supported_p (machine_mode mode);
bool legitimize_move (rtx, rtx);
void emit_vlmax_vsetvl (machine_mode, rtx);
void emit_hard_vlmax_vsetvl (machine_mode, rtx);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 49752cd8899..1cc157f1858 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -418,6 +418,18 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
&& IN_RANGE (INTVAL (elt), minval, maxval));
}
+/* Return true if the inner of mode is HFmode when ZVFH enabled, or other
+ float point machine mode. */
+bool
+float_point_mode_supported_p (machine_mode mode)
+{
+ machine_mode inner_mode = GET_MODE_INNER (mode);
+
+ gcc_assert (FLOAT_MODE_P (inner_mode));
+
+ return inner_mode == HFmode ? TARGET_ZVFH : true;
+}
+
/* Return true if VEC is a constant in which every element is in the range
[MINVAL, MAXVAL]. The elements do not need to have the same value.
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..234b712bc9d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..438670e8aec 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1364,7 +1364,7 @@ (define_insn "*pred_broadcast<mode>"
(vec_duplicate:VF
(match_operand:<VEL> 3 "direct_broadcast_operand" " f, f,Wdm,Wdm,Wdm,Wdm, f, f"))
(match_operand:VF 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@<mailto:%22@%0d %20vfmv.v.f\t%250,%253%0d %20vfmv.v.f\t%250,%253%0d@@%20-5685,7%20+5685,7%20@@%20(define_insn%20%22@pred_%3coptab%3e%3cmode>
vfmv.v.f\t%0,%3<mailto:%22@%0d %20vfmv.v.f\t%250,%253%0d %20vfmv.v.f\t%250,%253%0d@@%20-5685,7%20+5685,7%20@@%20(define_insn%20%22@pred_%3coptab%3e%3cmode>
vfmv.v.f\t%0,%3<mailto:%22@%0d %20vfmv.v.f\t%250,%253%0d %20vfmv.v.f\t%250,%253%0d@@%20-5685,7%20+5685,7%20@@%20(define_insn%20%22@pred_%3coptab%3e%3cmode>
@@ -5685,7 +5685,7 @@ (define_insn "@pred_<optab><mode<mailto:%22@%0d %20vfmv.v.f\t%250,%253%0d %20vfmv.v.f\t%250,%253%0d@@%20-5685,7%20+5685,7%20@@%20(define_insn%20%22@pred_%3coptab%3e%3cmode>>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5705,7 +5705,7 @@ (define_insn "@pred_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5728,7 +5728,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5749,7 +5749,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5772,7 +5772,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(vec_duplicate:VF
(match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5795,7 +5795,7 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfr<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5815,7 +5815,7 @@ (define_insn "@pred_<copysign><mode>"
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS)
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfsgnj<nx>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfsgnj")
(set_attr "mode" "<MODE>")])
@@ -5836,7 +5836,7 @@ (define_insn "@pred_<copysign><mode>_scalar"
(vec_duplicate:VF
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS)
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfsgnj<nx>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfsgnj")
(set_attr "mode" "<MODE>")])
@@ -5894,7 +5894,7 @@ (define_insn "*pred_<madd_msub><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<madd_msub>.vv\t%0,%3,%4%p1
vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
@@ -5927,7 +5927,7 @@ (define_insn "*pred_<macc_msac><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<macc_msac>.vv\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
@@ -5960,7 +5960,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[2], operands[5])
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
@@ -6021,7 +6021,7 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
(match_operand:VF 3 "register_operand" " 0, vr, 0, vr"))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 3)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<madd_msub>.vf\t%0,%2,%4%p1
vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
@@ -6055,7 +6055,7 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<macc_msac>.vf\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
@@ -6089,7 +6089,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
"@
@@ -6154,7 +6154,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
@@ -6188,7 +6188,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
@@ -6222,7 +6222,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr")))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[2], operands[5])
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
@@ -6285,7 +6285,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
(match_operand:VF 3 "register_operand" " 0, vr, 0, vr")))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 3)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
@@ -6320,7 +6320,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"@
vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
@@ -6355,7 +6355,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr")))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
"@
@@ -6399,7 +6399,7 @@ (define_insn "@pred_<optab><mode>"
(any_float_unop:VF
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
@@ -6422,7 +6422,7 @@ (define_insn "@pred_<optab><mode>"
(any_float_unop_nofrm:VF
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<insn>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
@@ -6445,7 +6445,7 @@ (define_insn "@pred_<misc_op><mode>"
(unspec:VF
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vf<misc_op>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -6464,7 +6464,7 @@ (define_insn "@pred_class<mode>"
(unspec:<VCONVERT>
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfclass.v\t%0,%3%p1"
[(set_attr "type" "vfclass")
(set_attr "mode" "<MODE>")])
@@ -6497,7 +6497,7 @@ (define_insn "@pred_dual_widen_<optab><mode>"
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6522,7 +6522,7 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
(vec_duplicate:<V_DOUBLE_TRUNC>
(match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6545,7 +6545,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>"
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.wv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6569,7 +6569,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
(vec_duplicate:<V_DOUBLE_TRUNC>
(match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.wf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6602,7 +6602,7 @@ (define_insn "@pred_widen_mul_<optab><mode>"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<macc_msac>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6629,7 +6629,7 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<macc_msac>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6656,7 +6656,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6684,7 +6684,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6728,7 +6728,8 @@ (define_insn "*pred_cmp<mode>"
[(match_operand:VF 4 "register_operand" " vr, vr")
(match_operand:VF 5 "register_operand" " vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vv\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6747,7 +6748,7 @@ (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
[(match_operand:VF 3 "register_operand" " vr")
(match_operand:VF 4 "register_operand" " vr")])
(match_dup 1)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B2.vv\t%0,%3,%4,v0.t"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")
@@ -6771,7 +6772,8 @@ (define_insn "*pred_cmp<mode>_narrow"
[(match_operand:VF 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
(match_operand:VF 5 "register_operand" " vr, vr, 0, 0, vr, 0, 0, vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
- "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vv\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6809,7 +6811,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
(vec_duplicate:VF
(match_operand:<VEL> 4 "register_operand" " f"))])
(match_dup 1)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B2.vf\t%0,%3,%4,v0.t"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")
@@ -6834,7 +6836,8 @@ (define_insn "*pred_cmp<mode>_scalar"
(vec_duplicate:VF
(match_operand:<VEL> 5 "register_operand" " f, f"))])
(match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6855,7 +6858,8 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(vec_duplicate:VF
(match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))])
(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6893,7 +6897,7 @@ (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
(match_operand:<VEL> 4 "register_operand" " f"))
(match_operand:VF 3 "register_operand" " vr")])
(match_dup 1)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B2.vf\t%0,%3,%4,v0.t"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")
@@ -6918,7 +6922,8 @@ (define_insn "*pred_eqne<mode>_scalar"
(match_operand:<VEL> 5 "register_operand" " f, f"))
(match_operand:VF 4 "register_operand" " vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6939,7 +6944,8 @@ (define_insn "*pred_eqne<mode>_scalar_narrow"
(match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
(match_operand:VF 4 "register_operand" " vr, 0, 0, vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6966,7 +6972,7 @@ (define_insn "@pred_merge<mode>_scalar"
(match_operand:VF 2 "register_operand" " vr,vr")
(match_operand:<VM> 4 "register_operand" " vm,vm"))
(match_operand:VF 1 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfmerge.vfm\t%0,%2,%3,%4"
[(set_attr "type" "vfmerge")
(set_attr "mode" "<MODE>")])
@@ -6994,7 +7000,7 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
(unspec:<VCONVERT>
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS)
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
(set_attr "mode" "<MODE>")])
@@ -7013,7 +7019,7 @@ (define_insn "@pred_<fix_cvt><mode>"
(any_fix:<VCONVERT>
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
(set_attr "mode" "<MODE>")])
@@ -7034,7 +7040,7 @@ (define_insn "@pred_<float_cvt><mode>"
(any_float:VF
(match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfcvtitof")
(set_attr "mode" "<MODE>")])
@@ -7062,7 +7068,7 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
(unspec:VWCONVERTI
[(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")] VFCVTS)
(match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<VNCONVERT>mode)"
"vfwcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7081,7 +7087,7 @@ (define_insn "@pred_widen_<fix_cvt><mode>"
(any_fix:VWCONVERTI
(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
(match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<VNCONVERT>mode)"
"vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7100,7 +7106,7 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(any_float:VF
(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfwcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtitof")
(set_attr "mode" "<VNCONVERT>")])
@@ -7119,7 +7125,7 @@ (define_insn "@pred_extend<mode>"
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -7147,7 +7153,7 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
(unspec:<VNCONVERT>
[(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS)
(match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfncvt.x<v_su>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7166,7 +7172,7 @@ (define_insn "@pred_narrow_<fix_cvt><mode>"
(any_fix:<VNCONVERT>
(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<VNCONVERT>mode)"
"vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7187,7 +7193,7 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(any_float:<VNCONVERT>
(match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<VNCONVERT>mode)"
"vfncvt.f.x<u>.w\t%0,%3%p1"
[(set_attr "type" "vfncvtitof")
(set_attr "mode" "<VNCONVERT>")])
@@ -7208,7 +7214,7 @@ (define_insn "@pred_trunc<mode>"
(float_truncate:<V_DOUBLE_TRUNC>
(match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -7228,7 +7234,7 @@ (define_insn "@pred_rod_trunc<mode>"
[(float_truncate:<V_DOUBLE_TRUNC>
(match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
(match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfncvt.rod.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -7389,7 +7395,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1>"
(parallel [(const_int 0)])))
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+ "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
@@ -7413,7 +7420,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve64>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 64
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
@@ -7437,7 +7445,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 32
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
@@ -7462,7 +7471,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1>"
(parallel [(const_int 0)])))
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+ "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
@@ -7487,7 +7497,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve64>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 64
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
@@ -7512,7 +7523,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve32>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 32
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
@@ -7533,7 +7545,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1>"
(match_operand:VWF 3 "register_operand" " vr, vr")
(match_operand:<VWLMUL1> 4 "register_operand" " vr, vr")
(match_operand:<VWLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+ "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
(set_attr "mode" "<MODE>")])
@@ -7554,7 +7567,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>"
(match_operand:VWF_ZVE64 3 "register_operand" " vr, vr")
(match_operand:<VWLMUL1_ZVE64> 4 "register_operand" " vr, vr")
(match_operand:<VWLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 64
+ && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
(set_attr "mode" "<MODE>")])
@@ -7657,7 +7671,7 @@ (define_insn "*pred_extract_first<mode>"
(match_operand:VF 1 "register_operand" "vr")
(parallel [(const_int 0)]))
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfmv.f.s\t%0,%1"
[(set_attr "type" "vfmovvf")
(set_attr "mode" "<MODE>")])
@@ -7778,7 +7792,7 @@ (define_insn "@pred_slide<ud><mode>"
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:<VEL> 4 "register_operand" " f, f, f, f")] VFSLIDES1))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (<MODE>mode)"
"vfslide<ud>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfslide<ud>")
(set_attr "mode" "<MODE>")])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 0923b6bc4d2..f1a29b639e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -3,6 +3,8 @@
#include "riscv_vector.h"
+typedef _Float16 float16_t;
+
vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
}
@@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
}
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16mf4(base, vl);
+}
+
+vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16m8(base, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
-
+/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-08 6:29 ` [PATCH v8] " pan2.li
@ 2023-06-08 6:34 ` juzhe.zhong
2023-06-08 7:58 ` Kito Cheng
0 siblings, 1 reply; 39+ messages in thread
From: juzhe.zhong @ 2023-06-08 6:34 UTC (permalink / raw)
To: pan2.li, gcc-patches
Cc: Robin Dapp, jeffreyalaw, pan2.li, yanzhang.wang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 39124 bytes --]
LGTM. Let's wait for Jeff and Robin. After this patch, we can start FP16 autovec.
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-06-08 14:29
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
iterators of RVV. And then the ZVFH will leverage one function as
the gate for FP16 supported or not.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv-protos.h (float_mode_supported_p):
New function to float point is supported by extension.
* config/riscv/riscv-v.cc (float_mode_supported_p):
Ditto.
* config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
* config/riscv/vector.md: Add condition to FP define insn.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
for ZVFHMIN.
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 12 ++
gcc/config/riscv/vector-iterators.md | 23 +--
gcc/config/riscv/vector.md | 144 ++++++++++--------
.../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +-
5 files changed, 118 insertions(+), 77 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index ebbaac255f9..1f606f59ce1 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -177,6 +177,7 @@ rtx expand_builtin (unsigned int, tree, rtx);
bool check_builtin_call (location_t, vec<location_t>, unsigned int,
tree, unsigned int, tree *);
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
+bool float_mode_supported_p (machine_mode mode);
bool legitimize_move (rtx, rtx);
void emit_vlmax_vsetvl (machine_mode, rtx);
void emit_hard_vlmax_vsetvl (machine_mode, rtx);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 49752cd8899..fe4eb058ec0 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -418,6 +418,18 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
&& IN_RANGE (INTVAL (elt), minval, maxval));
}
+/* Return true if the inner of mode is HFmode when ZVFH enabled, or other
+ float point machine mode. */
+bool
+float_mode_supported_p (machine_mode mode)
+{
+ machine_mode inner_mode = GET_MODE_INNER (mode);
+
+ gcc_assert (FLOAT_MODE_P (inner_mode));
+
+ return inner_mode == HFmode ? TARGET_ZVFH : true;
+}
+
/* Return true if VEC is a constant in which every element is in the range
[MINVAL, MAXVAL]. The elements do not need to have the same value.
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..234b712bc9d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..2fe0233f102 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1364,7 +1364,7 @@ (define_insn "*pred_broadcast<mode>"
(vec_duplicate:VF
(match_operand:<VEL> 3 "direct_broadcast_operand" " f, f,Wdm,Wdm,Wdm,Wdm, f, f"))
(match_operand:VF 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"@
vfmv.v.f\t%0,%3
vfmv.v.f\t%0,%3
@@ -5685,7 +5685,7 @@ (define_insn "@pred_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5705,7 +5705,7 @@ (define_insn "@pred_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5728,7 +5728,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5749,7 +5749,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5772,7 +5772,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(vec_duplicate:VF
(match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5795,7 +5795,7 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfr<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -5815,7 +5815,7 @@ (define_insn "@pred_<copysign><mode>"
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS)
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfsgnj<nx>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfsgnj")
(set_attr "mode" "<MODE>")])
@@ -5836,7 +5836,7 @@ (define_insn "@pred_<copysign><mode>_scalar"
(vec_duplicate:VF
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS)
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfsgnj<nx>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfsgnj")
(set_attr "mode" "<MODE>")])
@@ -5894,7 +5894,7 @@ (define_insn "*pred_<madd_msub><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"@
vf<madd_msub>.vv\t%0,%3,%4%p1
vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
@@ -5927,7 +5927,7 @@ (define_insn "*pred_<macc_msac><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"@
vf<macc_msac>.vv\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
@@ -5960,7 +5960,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[2], operands[5])
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
@@ -6021,7 +6021,7 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
(match_operand:VF 3 "register_operand" " 0, vr, 0, vr"))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 3)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"@
vf<madd_msub>.vf\t%0,%2,%4%p1
vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
@@ -6055,7 +6055,7 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"@
vf<macc_msac>.vf\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
@@ -6089,7 +6089,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
"@
@@ -6154,7 +6154,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"@
vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
@@ -6188,7 +6188,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"@
vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
@@ -6222,7 +6222,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
(match_operand:VF 3 "register_operand" " vr, vr")))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[2], operands[5])
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
@@ -6285,7 +6285,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
(match_operand:VF 3 "register_operand" " 0, vr, 0, vr")))
(match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
(match_dup 3)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"@
vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
@@ -6320,7 +6320,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
(match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
(match_dup 4)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"@
vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
@@ -6355,7 +6355,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
(match_operand:VF 3 "register_operand" " vr, vr")))
(match_operand:VF 4 "vector_arith_operand" " vr, vr"))
(match_operand:VF 5 "register_operand" " 0, vr")))]
- "TARGET_VECTOR
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
&& !rtx_equal_p (operands[3], operands[5])
&& !rtx_equal_p (operands[4], operands[5])"
"@
@@ -6399,7 +6399,7 @@ (define_insn "@pred_<optab><mode>"
(any_float_unop:VF
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<insn>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
@@ -6422,7 +6422,7 @@ (define_insn "@pred_<optab><mode>"
(any_float_unop_nofrm:VF
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<insn>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
@@ -6445,7 +6445,7 @@ (define_insn "@pred_<misc_op><mode>"
(unspec:VF
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vf<misc_op>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")])
@@ -6464,7 +6464,7 @@ (define_insn "@pred_class<mode>"
(unspec:<VCONVERT>
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfclass.v\t%0,%3%p1"
[(set_attr "type" "vfclass")
(set_attr "mode" "<MODE>")])
@@ -6497,7 +6497,7 @@ (define_insn "@pred_dual_widen_<optab><mode>"
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6522,7 +6522,7 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
(vec_duplicate:<V_DOUBLE_TRUNC>
(match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6545,7 +6545,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>"
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.wv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6569,7 +6569,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
(vec_duplicate:<V_DOUBLE_TRUNC>
(match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<insn>.wf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6602,7 +6602,7 @@ (define_insn "@pred_widen_mul_<optab><mode>"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<macc_msac>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6629,7 +6629,7 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<macc_msac>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6656,7 +6656,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6684,7 +6684,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
(match_operand:VWEXTF 2 "register_operand" " 0"))
(match_dup 2)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -6728,7 +6728,8 @@ (define_insn "*pred_cmp<mode>"
[(match_operand:VF 4 "register_operand" " vr, vr")
(match_operand:VF 5 "register_operand" " vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vmf%B3.vv\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6747,7 +6748,7 @@ (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
[(match_operand:VF 3 "register_operand" " vr")
(match_operand:VF 4 "register_operand" " vr")])
(match_dup 1)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vmf%B2.vv\t%0,%3,%4,v0.t"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")
@@ -6771,7 +6772,8 @@ (define_insn "*pred_cmp<mode>_narrow"
[(match_operand:VF 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
(match_operand:VF 5 "register_operand" " vr, vr, 0, 0, vr, 0, 0, vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
- "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vmf%B3.vv\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6809,7 +6811,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
(vec_duplicate:VF
(match_operand:<VEL> 4 "register_operand" " f"))])
(match_dup 1)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vmf%B2.vf\t%0,%3,%4,v0.t"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")
@@ -6834,7 +6836,8 @@ (define_insn "*pred_cmp<mode>_scalar"
(vec_duplicate:VF
(match_operand:<VEL> 5 "register_operand" " f, f"))])
(match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6855,7 +6858,8 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(vec_duplicate:VF
(match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))])
(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6893,7 +6897,7 @@ (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
(match_operand:<VEL> 4 "register_operand" " f"))
(match_operand:VF 3 "register_operand" " vr")])
(match_dup 1)))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vmf%B2.vf\t%0,%3,%4,v0.t"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")
@@ -6918,7 +6922,8 @@ (define_insn "*pred_eqne<mode>_scalar"
(match_operand:<VEL> 5 "register_operand" " f, f"))
(match_operand:VF 4 "register_operand" " vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6939,7 +6944,8 @@ (define_insn "*pred_eqne<mode>_scalar_narrow"
(match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
(match_operand:VF 4 "register_operand" " vr, 0, 0, vr, vr")])
(match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
+ "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
(set_attr "mode" "<MODE>")])
@@ -6966,7 +6972,7 @@ (define_insn "@pred_merge<mode>_scalar"
(match_operand:VF 2 "register_operand" " vr,vr")
(match_operand:<VM> 4 "register_operand" " vm,vm"))
(match_operand:VF 1 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfmerge.vfm\t%0,%2,%3,%4"
[(set_attr "type" "vfmerge")
(set_attr "mode" "<MODE>")])
@@ -6994,7 +7000,7 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
(unspec:<VCONVERT>
[(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS)
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
(set_attr "mode" "<MODE>")])
@@ -7013,7 +7019,7 @@ (define_insn "@pred_<fix_cvt><mode>"
(any_fix:<VCONVERT>
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
(set_attr "mode" "<MODE>")])
@@ -7034,7 +7040,7 @@ (define_insn "@pred_<float_cvt><mode>"
(any_float:VF
(match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfcvtitof")
(set_attr "mode" "<MODE>")])
@@ -7062,7 +7068,7 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
(unspec:VWCONVERTI
[(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")] VFCVTS)
(match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
"vfwcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7081,7 +7087,7 @@ (define_insn "@pred_widen_<fix_cvt><mode>"
(any_fix:VWCONVERTI
(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
(match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
"vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7100,7 +7106,7 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(any_float:VF
(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfwcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtitof")
(set_attr "mode" "<VNCONVERT>")])
@@ -7119,7 +7125,7 @@ (define_insn "@pred_extend<mode>"
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -7147,7 +7153,7 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
(unspec:<VNCONVERT>
[(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS)
(match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfncvt.x<v_su>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7166,7 +7172,7 @@ (define_insn "@pred_narrow_<fix_cvt><mode>"
(any_fix:<VNCONVERT>
(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
"vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
(set_attr "mode" "<VNCONVERT>")])
@@ -7187,7 +7193,7 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(any_float:<VNCONVERT>
(match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
"vfncvt.f.x<u>.w\t%0,%3%p1"
[(set_attr "type" "vfncvtitof")
(set_attr "mode" "<VNCONVERT>")])
@@ -7208,7 +7214,7 @@ (define_insn "@pred_trunc<mode>"
(float_truncate:<V_DOUBLE_TRUNC>
(match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -7228,7 +7234,7 @@ (define_insn "@pred_rod_trunc<mode>"
[(float_truncate:<V_DOUBLE_TRUNC>
(match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
(match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
"vfncvt.rod.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
@@ -7389,7 +7395,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1>"
(parallel [(const_int 0)])))
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+ "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
@@ -7413,7 +7420,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve64>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 64
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
@@ -7437,7 +7445,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 32
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
@@ -7462,7 +7471,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1>"
(parallel [(const_int 0)])))
(match_operand:VF 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+ "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
@@ -7487,7 +7497,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve64>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 64
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
@@ -7512,7 +7523,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve32>"
(parallel [(const_int 0)])))
(match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
(match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 32
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
@@ -7533,7 +7545,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1>"
(match_operand:VWF 3 "register_operand" " vr, vr")
(match_operand:<VWLMUL1> 4 "register_operand" " vr, vr")
(match_operand:<VWLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+ "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
(set_attr "mode" "<MODE>")])
@@ -7554,7 +7567,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>"
(match_operand:VWF_ZVE64 3 "register_operand" " vr, vr")
(match_operand:<VWLMUL1_ZVE64> 4 "register_operand" " vr, vr")
(match_operand:<VWLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
- "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+ "TARGET_VECTOR && TARGET_MIN_VLEN == 64
+ && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
(set_attr "mode" "<MODE>")])
@@ -7657,7 +7671,7 @@ (define_insn "*pred_extract_first<mode>"
(match_operand:VF 1 "register_operand" "vr")
(parallel [(const_int 0)]))
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfmv.f.s\t%0,%1"
[(set_attr "type" "vfmovvf")
(set_attr "mode" "<MODE>")])
@@ -7778,7 +7792,7 @@ (define_insn "@pred_slide<ud><mode>"
(match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")
(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
(match_operand:<VEL> 4 "register_operand" " f, f, f, f")] VFSLIDES1))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
"vfslide<ud>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfslide<ud>")
(set_attr "mode" "<MODE>")])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 0923b6bc4d2..f1a29b639e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -3,6 +3,8 @@
#include "riscv_vector.h"
+typedef _Float16 float16_t;
+
vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
}
@@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
}
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16mf4(base, vl);
+}
+
+vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16m8(base, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
-
+/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-08 6:34 ` juzhe.zhong
@ 2023-06-08 7:58 ` Kito Cheng
2023-06-08 8:00 ` juzhe.zhong
` (2 more replies)
0 siblings, 3 replies; 39+ messages in thread
From: Kito Cheng @ 2023-06-08 7:58 UTC (permalink / raw)
To: juzhe.zhong; +Cc: pan2.li, gcc-patches, Robin Dapp, jeffreyalaw, yanzhang.wang
I am thinking, is it possible to use mode attr to remove the overhead
of checking the mode for other FP modes other than FP16?
e.g.
(define_mode_attr TARGET_FP_FULL_OPERATION_CHECKING [
(VNx1HF "TARGET_ZVFH")
...
(VNx1SF "1")
...
])
"TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
->
"TARGET_VECTOR && <TARGET_FP_FULL_OPERATION_CHECKING>"
On Thu, Jun 8, 2023 at 2:35 PM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> LGTM. Let's wait for Jeff and Robin. After this patch, we can start FP16 autovec.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: pan2.li
> Date: 2023-06-08 14:29
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
> Subject: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to refactor the requirement of both the ZVFH
> and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
> iterators of RVV. And then the ZVFH will leverage one function as
> the gate for FP16 supported or not.
>
> Please note the ZVFH will cover the ZVFHMIN instructions. This patch
> add one test for this.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (float_mode_supported_p):
> New function to float point is supported by extension.
> * config/riscv/riscv-v.cc (float_mode_supported_p):
> Ditto.
> * config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
> * config/riscv/vector.md: Add condition to FP define insn.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
> for ZVFHMIN.
> ---
> gcc/config/riscv/riscv-protos.h | 1 +
> gcc/config/riscv/riscv-v.cc | 12 ++
> gcc/config/riscv/vector-iterators.md | 23 +--
> gcc/config/riscv/vector.md | 144 ++++++++++--------
> .../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +-
> 5 files changed, 118 insertions(+), 77 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index ebbaac255f9..1f606f59ce1 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -177,6 +177,7 @@ rtx expand_builtin (unsigned int, tree, rtx);
> bool check_builtin_call (location_t, vec<location_t>, unsigned int,
> tree, unsigned int, tree *);
> bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
> +bool float_mode_supported_p (machine_mode mode);
> bool legitimize_move (rtx, rtx);
> void emit_vlmax_vsetvl (machine_mode, rtx);
> void emit_hard_vlmax_vsetvl (machine_mode, rtx);
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 49752cd8899..fe4eb058ec0 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -418,6 +418,18 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
> && IN_RANGE (INTVAL (elt), minval, maxval));
> }
> +/* Return true if the inner of mode is HFmode when ZVFH enabled, or other
> + float point machine mode. */
> +bool
> +float_mode_supported_p (machine_mode mode)
> +{
> + machine_mode inner_mode = GET_MODE_INNER (mode);
> +
> + gcc_assert (FLOAT_MODE_P (inner_mode));
> +
> + return inner_mode == HFmode ? TARGET_ZVFH : true;
> +}
> +
> /* Return true if VEC is a constant in which every element is in the range
> [MINVAL, MAXVAL]. The elements do not need to have the same value.
> diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
> index f4946d84449..234b712bc9d 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
> (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
> (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
> - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> - (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
> - (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
> + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
> + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
> (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
> (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
> (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
> @@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
> (define_mode_iterator V_FRACT [
> (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
> (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
> - (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
> +
> + (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
> + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
> +
> (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
> (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
> (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> @@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
> ])
> (define_mode_iterator VWEXTF [
> - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> - (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
> - (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> + (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> + (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> + (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> + (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> + (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
> + (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
> (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index 1d1847bd85a..2fe0233f102 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -1364,7 +1364,7 @@ (define_insn "*pred_broadcast<mode>"
> (vec_duplicate:VF
> (match_operand:<VEL> 3 "direct_broadcast_operand" " f, f,Wdm,Wdm,Wdm,Wdm, f, f"))
> (match_operand:VF 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vfmv.v.f\t%0,%3
> vfmv.v.f\t%0,%3
> @@ -5685,7 +5685,7 @@ (define_insn "@pred_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5705,7 +5705,7 @@ (define_insn "@pred_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5728,7 +5728,7 @@ (define_insn "@pred_<optab><mode>_scalar"
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5749,7 +5749,7 @@ (define_insn "@pred_<optab><mode>_scalar"
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5772,7 +5772,7 @@ (define_insn "@pred_<optab><mode>_scalar"
> (vec_duplicate:VF
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5795,7 +5795,7 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfr<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5815,7 +5815,7 @@ (define_insn "@pred_<copysign><mode>"
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS)
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfsgnj<nx>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vfsgnj")
> (set_attr "mode" "<MODE>")])
> @@ -5836,7 +5836,7 @@ (define_insn "@pred_<copysign><mode>_scalar"
> (vec_duplicate:VF
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS)
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfsgnj<nx>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfsgnj")
> (set_attr "mode" "<MODE>")])
> @@ -5894,7 +5894,7 @@ (define_insn "*pred_<madd_msub><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<madd_msub>.vv\t%0,%3,%4%p1
> vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
> @@ -5927,7 +5927,7 @@ (define_insn "*pred_<macc_msac><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<macc_msac>.vv\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
> @@ -5960,7 +5960,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[2], operands[5])
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> @@ -6021,7 +6021,7 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
> (match_operand:VF 3 "register_operand" " 0, vr, 0, vr"))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 3)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<madd_msub>.vf\t%0,%2,%4%p1
> vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
> @@ -6055,7 +6055,7 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<macc_msac>.vf\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
> @@ -6089,7 +6089,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> "@
> @@ -6154,7 +6154,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
> vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
> @@ -6188,7 +6188,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
> @@ -6222,7 +6222,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr")))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[2], operands[5])
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> @@ -6285,7 +6285,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
> (match_operand:VF 3 "register_operand" " 0, vr, 0, vr")))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 3)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
> vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
> @@ -6320,7 +6320,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
> @@ -6355,7 +6355,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr")))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> "@
> @@ -6399,7 +6399,7 @@ (define_insn "@pred_<optab><mode>"
> (any_float_unop:VF
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")
> @@ -6422,7 +6422,7 @@ (define_insn "@pred_<optab><mode>"
> (any_float_unop_nofrm:VF
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")
> @@ -6445,7 +6445,7 @@ (define_insn "@pred_<misc_op><mode>"
> (unspec:VF
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<misc_op>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -6464,7 +6464,7 @@ (define_insn "@pred_class<mode>"
> (unspec:<VCONVERT>
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
> (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfclass.v\t%0,%3%p1"
> [(set_attr "type" "vfclass")
> (set_attr "mode" "<MODE>")])
> @@ -6497,7 +6497,7 @@ (define_insn "@pred_dual_widen_<optab><mode>"
> (float_extend:VWEXTF
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6522,7 +6522,7 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
> (vec_duplicate:<V_DOUBLE_TRUNC>
> (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6545,7 +6545,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>"
> (float_extend:VWEXTF
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.wv\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6569,7 +6569,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
> (vec_duplicate:<V_DOUBLE_TRUNC>
> (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.wf\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6602,7 +6602,7 @@ (define_insn "@pred_widen_mul_<optab><mode>"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<macc_msac>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6629,7 +6629,7 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<macc_msac>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6656,7 +6656,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6684,7 +6684,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6728,7 +6728,8 @@ (define_insn "*pred_cmp<mode>"
> [(match_operand:VF 4 "register_operand" " vr, vr")
> (match_operand:VF 5 "register_operand" " vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vv\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6747,7 +6748,7 @@ (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
> [(match_operand:VF 3 "register_operand" " vr")
> (match_operand:VF 4 "register_operand" " vr")])
> (match_dup 1)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B2.vv\t%0,%3,%4,v0.t"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")
> @@ -6771,7 +6772,8 @@ (define_insn "*pred_cmp<mode>_narrow"
> [(match_operand:VF 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
> (match_operand:VF 5 "register_operand" " vr, vr, 0, 0, vr, 0, 0, vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
> - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vv\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6809,7 +6811,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
> (vec_duplicate:VF
> (match_operand:<VEL> 4 "register_operand" " f"))])
> (match_dup 1)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B2.vf\t%0,%3,%4,v0.t"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")
> @@ -6834,7 +6836,8 @@ (define_insn "*pred_cmp<mode>_scalar"
> (vec_duplicate:VF
> (match_operand:<VEL> 5 "register_operand" " f, f"))])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6855,7 +6858,8 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
> (vec_duplicate:VF
> (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
> - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6893,7 +6897,7 @@ (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
> (match_operand:<VEL> 4 "register_operand" " f"))
> (match_operand:VF 3 "register_operand" " vr")])
> (match_dup 1)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B2.vf\t%0,%3,%4,v0.t"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")
> @@ -6918,7 +6922,8 @@ (define_insn "*pred_eqne<mode>_scalar"
> (match_operand:<VEL> 5 "register_operand" " f, f"))
> (match_operand:VF 4 "register_operand" " vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6939,7 +6944,8 @@ (define_insn "*pred_eqne<mode>_scalar_narrow"
> (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
> (match_operand:VF 4 "register_operand" " vr, 0, 0, vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
> - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6966,7 +6972,7 @@ (define_insn "@pred_merge<mode>_scalar"
> (match_operand:VF 2 "register_operand" " vr,vr")
> (match_operand:<VM> 4 "register_operand" " vm,vm"))
> (match_operand:VF 1 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfmerge.vfm\t%0,%2,%3,%4"
> [(set_attr "type" "vfmerge")
> (set_attr "mode" "<MODE>")])
> @@ -6994,7 +7000,7 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
> (unspec:<VCONVERT>
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS)
> (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfcvt.x<v_su>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfcvtftoi")
> (set_attr "mode" "<MODE>")])
> @@ -7013,7 +7019,7 @@ (define_insn "@pred_<fix_cvt><mode>"
> (any_fix:<VCONVERT>
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfcvtftoi")
> (set_attr "mode" "<MODE>")])
> @@ -7034,7 +7040,7 @@ (define_insn "@pred_<float_cvt><mode>"
> (any_float:VF
> (match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfcvt.f.x<u>.v\t%0,%3%p1"
> [(set_attr "type" "vfcvtitof")
> (set_attr "mode" "<MODE>")])
> @@ -7062,7 +7068,7 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
> (unspec:VWCONVERTI
> [(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")] VFCVTS)
> (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfwcvt.x<v_su>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7081,7 +7087,7 @@ (define_insn "@pred_widen_<fix_cvt><mode>"
> (any_fix:VWCONVERTI
> (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
> (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7100,7 +7106,7 @@ (define_insn "@pred_widen_<float_cvt><mode>"
> (any_float:VF
> (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwcvt.f.x<u>.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtitof")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7119,7 +7125,7 @@ (define_insn "@pred_extend<mode>"
> (float_extend:VWEXTF
> (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwcvt.f.f.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtftof")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -7147,7 +7153,7 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
> (unspec:<VNCONVERT>
> [(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS)
> (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfncvt.x<v_su>.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7166,7 +7172,7 @@ (define_insn "@pred_narrow_<fix_cvt><mode>"
> (any_fix:<VNCONVERT>
> (match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
> (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7187,7 +7193,7 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
> (any_float:<VNCONVERT>
> (match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
> (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfncvt.f.x<u>.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtitof")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7208,7 +7214,7 @@ (define_insn "@pred_trunc<mode>"
> (float_truncate:<V_DOUBLE_TRUNC>
> (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
> (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfncvt.f.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftof")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -7228,7 +7234,7 @@ (define_insn "@pred_rod_trunc<mode>"
> [(float_truncate:<V_DOUBLE_TRUNC>
> (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
> (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfncvt.rod.f.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftof")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -7389,7 +7395,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1>"
> (parallel [(const_int 0)])))
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> + "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<reduc>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfredu")
> (set_attr "mode" "<MODE>")])
> @@ -7413,7 +7420,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve64>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<reduc>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfredu")
> (set_attr "mode" "<MODE>")])
> @@ -7437,7 +7445,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 32
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<reduc>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfredu")
> (set_attr "mode" "<MODE>")])
> @@ -7462,7 +7471,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1>"
> (parallel [(const_int 0)])))
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> + "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7487,7 +7497,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve64>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7512,7 +7523,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve32>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 32
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7533,7 +7545,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1>"
> (match_operand:VWF 3 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1> 4 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> + "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfwred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7554,7 +7567,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>"
> (match_operand:VWF_ZVE64 3 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1_ZVE64> 4 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfwred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7657,7 +7671,7 @@ (define_insn "*pred_extract_first<mode>"
> (match_operand:VF 1 "register_operand" "vr")
> (parallel [(const_int 0)]))
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfmv.f.s\t%0,%1"
> [(set_attr "type" "vfmovvf")
> (set_attr "mode" "<MODE>")])
> @@ -7778,7 +7792,7 @@ (define_insn "@pred_slide<ud><mode>"
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f")] VFSLIDES1))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfslide<ud>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfslide<ud>")
> (set_attr "mode" "<MODE>")])
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> index 0923b6bc4d2..f1a29b639e0 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> @@ -3,6 +3,8 @@
> #include "riscv_vector.h"
> +typedef _Float16 float16_t;
> +
> vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
> return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
> }
> @@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
> return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
> }
> -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
> +vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
> + return __riscv_vle16_v_f16mf4(base, vl);
> +}
> +
> +vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
> + return __riscv_vle16_v_f16m8(base, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
> /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> -
> +/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-08 7:58 ` Kito Cheng
@ 2023-06-08 8:00 ` juzhe.zhong
2023-06-08 8:01 ` Li, Pan2
2023-06-08 8:32 ` juzhe.zhong
2 siblings, 0 replies; 39+ messages in thread
From: juzhe.zhong @ 2023-06-08 8:00 UTC (permalink / raw)
To: kito.cheng; +Cc: pan2.li, gcc-patches, Robin Dapp, jeffreyalaw, yanzhang.wang
[-- Attachment #1: Type: text/plain, Size: 41427 bytes --]
Oh. Good suggestion. It's much better than my solution I think.
juzhe.zhong@rivai.ai
From: Kito Cheng
Date: 2023-06-08 15:58
To: juzhe.zhong@rivai.ai
CC: pan2.li; gcc-patches; Robin Dapp; jeffreyalaw; yanzhang.wang
Subject: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
I am thinking, is it possible to use mode attr to remove the overhead
of checking the mode for other FP modes other than FP16?
e.g.
(define_mode_attr TARGET_FP_FULL_OPERATION_CHECKING [
(VNx1HF "TARGET_ZVFH")
...
(VNx1SF "1")
...
])
"TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
->
"TARGET_VECTOR && <TARGET_FP_FULL_OPERATION_CHECKING>"
On Thu, Jun 8, 2023 at 2:35 PM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> LGTM. Let's wait for Jeff and Robin. After this patch, we can start FP16 autovec.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: pan2.li
> Date: 2023-06-08 14:29
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
> Subject: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to refactor the requirement of both the ZVFH
> and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
> iterators of RVV. And then the ZVFH will leverage one function as
> the gate for FP16 supported or not.
>
> Please note the ZVFH will cover the ZVFHMIN instructions. This patch
> add one test for this.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (float_mode_supported_p):
> New function to float point is supported by extension.
> * config/riscv/riscv-v.cc (float_mode_supported_p):
> Ditto.
> * config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
> * config/riscv/vector.md: Add condition to FP define insn.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
> for ZVFHMIN.
> ---
> gcc/config/riscv/riscv-protos.h | 1 +
> gcc/config/riscv/riscv-v.cc | 12 ++
> gcc/config/riscv/vector-iterators.md | 23 +--
> gcc/config/riscv/vector.md | 144 ++++++++++--------
> .../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +-
> 5 files changed, 118 insertions(+), 77 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index ebbaac255f9..1f606f59ce1 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -177,6 +177,7 @@ rtx expand_builtin (unsigned int, tree, rtx);
> bool check_builtin_call (location_t, vec<location_t>, unsigned int,
> tree, unsigned int, tree *);
> bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
> +bool float_mode_supported_p (machine_mode mode);
> bool legitimize_move (rtx, rtx);
> void emit_vlmax_vsetvl (machine_mode, rtx);
> void emit_hard_vlmax_vsetvl (machine_mode, rtx);
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 49752cd8899..fe4eb058ec0 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -418,6 +418,18 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
> && IN_RANGE (INTVAL (elt), minval, maxval));
> }
> +/* Return true if the inner of mode is HFmode when ZVFH enabled, or other
> + float point machine mode. */
> +bool
> +float_mode_supported_p (machine_mode mode)
> +{
> + machine_mode inner_mode = GET_MODE_INNER (mode);
> +
> + gcc_assert (FLOAT_MODE_P (inner_mode));
> +
> + return inner_mode == HFmode ? TARGET_ZVFH : true;
> +}
> +
> /* Return true if VEC is a constant in which every element is in the range
> [MINVAL, MAXVAL]. The elements do not need to have the same value.
> diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
> index f4946d84449..234b712bc9d 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
> (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
> (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
> - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> - (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
> - (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
> + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
> + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
> (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
> (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
> (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
> @@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
> (define_mode_iterator V_FRACT [
> (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
> (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
> - (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
> +
> + (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
> + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
> +
> (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
> (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
> (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> @@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
> ])
> (define_mode_iterator VWEXTF [
> - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> - (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
> - (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> + (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> + (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> + (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> + (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> + (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
> + (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
> (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index 1d1847bd85a..2fe0233f102 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -1364,7 +1364,7 @@ (define_insn "*pred_broadcast<mode>"
> (vec_duplicate:VF
> (match_operand:<VEL> 3 "direct_broadcast_operand" " f, f,Wdm,Wdm,Wdm,Wdm, f, f"))
> (match_operand:VF 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vfmv.v.f\t%0,%3
> vfmv.v.f\t%0,%3
> @@ -5685,7 +5685,7 @@ (define_insn "@pred_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5705,7 +5705,7 @@ (define_insn "@pred_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5728,7 +5728,7 @@ (define_insn "@pred_<optab><mode>_scalar"
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5749,7 +5749,7 @@ (define_insn "@pred_<optab><mode>_scalar"
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5772,7 +5772,7 @@ (define_insn "@pred_<optab><mode>_scalar"
> (vec_duplicate:VF
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5795,7 +5795,7 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfr<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5815,7 +5815,7 @@ (define_insn "@pred_<copysign><mode>"
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS)
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfsgnj<nx>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vfsgnj")
> (set_attr "mode" "<MODE>")])
> @@ -5836,7 +5836,7 @@ (define_insn "@pred_<copysign><mode>_scalar"
> (vec_duplicate:VF
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS)
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfsgnj<nx>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfsgnj")
> (set_attr "mode" "<MODE>")])
> @@ -5894,7 +5894,7 @@ (define_insn "*pred_<madd_msub><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<madd_msub>.vv\t%0,%3,%4%p1
> vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
> @@ -5927,7 +5927,7 @@ (define_insn "*pred_<macc_msac><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<macc_msac>.vv\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
> @@ -5960,7 +5960,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[2], operands[5])
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> @@ -6021,7 +6021,7 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
> (match_operand:VF 3 "register_operand" " 0, vr, 0, vr"))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 3)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<madd_msub>.vf\t%0,%2,%4%p1
> vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
> @@ -6055,7 +6055,7 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<macc_msac>.vf\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
> @@ -6089,7 +6089,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> "@
> @@ -6154,7 +6154,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
> vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
> @@ -6188,7 +6188,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
> @@ -6222,7 +6222,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr")))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[2], operands[5])
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> @@ -6285,7 +6285,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
> (match_operand:VF 3 "register_operand" " 0, vr, 0, vr")))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 3)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
> vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
> @@ -6320,7 +6320,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
> @@ -6355,7 +6355,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr")))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> "@
> @@ -6399,7 +6399,7 @@ (define_insn "@pred_<optab><mode>"
> (any_float_unop:VF
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")
> @@ -6422,7 +6422,7 @@ (define_insn "@pred_<optab><mode>"
> (any_float_unop_nofrm:VF
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")
> @@ -6445,7 +6445,7 @@ (define_insn "@pred_<misc_op><mode>"
> (unspec:VF
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<misc_op>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -6464,7 +6464,7 @@ (define_insn "@pred_class<mode>"
> (unspec:<VCONVERT>
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
> (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfclass.v\t%0,%3%p1"
> [(set_attr "type" "vfclass")
> (set_attr "mode" "<MODE>")])
> @@ -6497,7 +6497,7 @@ (define_insn "@pred_dual_widen_<optab><mode>"
> (float_extend:VWEXTF
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6522,7 +6522,7 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
> (vec_duplicate:<V_DOUBLE_TRUNC>
> (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6545,7 +6545,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>"
> (float_extend:VWEXTF
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.wv\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6569,7 +6569,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
> (vec_duplicate:<V_DOUBLE_TRUNC>
> (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.wf\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6602,7 +6602,7 @@ (define_insn "@pred_widen_mul_<optab><mode>"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<macc_msac>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6629,7 +6629,7 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<macc_msac>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6656,7 +6656,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6684,7 +6684,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6728,7 +6728,8 @@ (define_insn "*pred_cmp<mode>"
> [(match_operand:VF 4 "register_operand" " vr, vr")
> (match_operand:VF 5 "register_operand" " vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vv\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6747,7 +6748,7 @@ (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
> [(match_operand:VF 3 "register_operand" " vr")
> (match_operand:VF 4 "register_operand" " vr")])
> (match_dup 1)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B2.vv\t%0,%3,%4,v0.t"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")
> @@ -6771,7 +6772,8 @@ (define_insn "*pred_cmp<mode>_narrow"
> [(match_operand:VF 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
> (match_operand:VF 5 "register_operand" " vr, vr, 0, 0, vr, 0, 0, vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
> - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vv\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6809,7 +6811,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
> (vec_duplicate:VF
> (match_operand:<VEL> 4 "register_operand" " f"))])
> (match_dup 1)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B2.vf\t%0,%3,%4,v0.t"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")
> @@ -6834,7 +6836,8 @@ (define_insn "*pred_cmp<mode>_scalar"
> (vec_duplicate:VF
> (match_operand:<VEL> 5 "register_operand" " f, f"))])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6855,7 +6858,8 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
> (vec_duplicate:VF
> (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
> - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6893,7 +6897,7 @@ (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
> (match_operand:<VEL> 4 "register_operand" " f"))
> (match_operand:VF 3 "register_operand" " vr")])
> (match_dup 1)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B2.vf\t%0,%3,%4,v0.t"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")
> @@ -6918,7 +6922,8 @@ (define_insn "*pred_eqne<mode>_scalar"
> (match_operand:<VEL> 5 "register_operand" " f, f"))
> (match_operand:VF 4 "register_operand" " vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6939,7 +6944,8 @@ (define_insn "*pred_eqne<mode>_scalar_narrow"
> (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
> (match_operand:VF 4 "register_operand" " vr, 0, 0, vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
> - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6966,7 +6972,7 @@ (define_insn "@pred_merge<mode>_scalar"
> (match_operand:VF 2 "register_operand" " vr,vr")
> (match_operand:<VM> 4 "register_operand" " vm,vm"))
> (match_operand:VF 1 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfmerge.vfm\t%0,%2,%3,%4"
> [(set_attr "type" "vfmerge")
> (set_attr "mode" "<MODE>")])
> @@ -6994,7 +7000,7 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
> (unspec:<VCONVERT>
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS)
> (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfcvt.x<v_su>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfcvtftoi")
> (set_attr "mode" "<MODE>")])
> @@ -7013,7 +7019,7 @@ (define_insn "@pred_<fix_cvt><mode>"
> (any_fix:<VCONVERT>
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfcvtftoi")
> (set_attr "mode" "<MODE>")])
> @@ -7034,7 +7040,7 @@ (define_insn "@pred_<float_cvt><mode>"
> (any_float:VF
> (match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfcvt.f.x<u>.v\t%0,%3%p1"
> [(set_attr "type" "vfcvtitof")
> (set_attr "mode" "<MODE>")])
> @@ -7062,7 +7068,7 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
> (unspec:VWCONVERTI
> [(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")] VFCVTS)
> (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfwcvt.x<v_su>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7081,7 +7087,7 @@ (define_insn "@pred_widen_<fix_cvt><mode>"
> (any_fix:VWCONVERTI
> (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
> (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7100,7 +7106,7 @@ (define_insn "@pred_widen_<float_cvt><mode>"
> (any_float:VF
> (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwcvt.f.x<u>.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtitof")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7119,7 +7125,7 @@ (define_insn "@pred_extend<mode>"
> (float_extend:VWEXTF
> (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwcvt.f.f.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtftof")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -7147,7 +7153,7 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
> (unspec:<VNCONVERT>
> [(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS)
> (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfncvt.x<v_su>.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7166,7 +7172,7 @@ (define_insn "@pred_narrow_<fix_cvt><mode>"
> (any_fix:<VNCONVERT>
> (match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
> (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7187,7 +7193,7 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
> (any_float:<VNCONVERT>
> (match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
> (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfncvt.f.x<u>.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtitof")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7208,7 +7214,7 @@ (define_insn "@pred_trunc<mode>"
> (float_truncate:<V_DOUBLE_TRUNC>
> (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
> (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfncvt.f.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftof")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -7228,7 +7234,7 @@ (define_insn "@pred_rod_trunc<mode>"
> [(float_truncate:<V_DOUBLE_TRUNC>
> (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
> (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfncvt.rod.f.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftof")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -7389,7 +7395,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1>"
> (parallel [(const_int 0)])))
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> + "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<reduc>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfredu")
> (set_attr "mode" "<MODE>")])
> @@ -7413,7 +7420,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve64>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<reduc>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfredu")
> (set_attr "mode" "<MODE>")])
> @@ -7437,7 +7445,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 32
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<reduc>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfredu")
> (set_attr "mode" "<MODE>")])
> @@ -7462,7 +7471,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1>"
> (parallel [(const_int 0)])))
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> + "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7487,7 +7497,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve64>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7512,7 +7523,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve32>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 32
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7533,7 +7545,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1>"
> (match_operand:VWF 3 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1> 4 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> + "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfwred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7554,7 +7567,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>"
> (match_operand:VWF_ZVE64 3 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1_ZVE64> 4 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfwred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7657,7 +7671,7 @@ (define_insn "*pred_extract_first<mode>"
> (match_operand:VF 1 "register_operand" "vr")
> (parallel [(const_int 0)]))
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfmv.f.s\t%0,%1"
> [(set_attr "type" "vfmovvf")
> (set_attr "mode" "<MODE>")])
> @@ -7778,7 +7792,7 @@ (define_insn "@pred_slide<ud><mode>"
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f")] VFSLIDES1))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfslide<ud>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfslide<ud>")
> (set_attr "mode" "<MODE>")])
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> index 0923b6bc4d2..f1a29b639e0 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> @@ -3,6 +3,8 @@
> #include "riscv_vector.h"
> +typedef _Float16 float16_t;
> +
> vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
> return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
> }
> @@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
> return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
> }
> -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
> +vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
> + return __riscv_vle16_v_f16mf4(base, vl);
> +}
> +
> +vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
> + return __riscv_vle16_v_f16m8(base, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
> /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> -
> +/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-08 7:58 ` Kito Cheng
2023-06-08 8:00 ` juzhe.zhong
@ 2023-06-08 8:01 ` Li, Pan2
2023-06-08 8:32 ` juzhe.zhong
2 siblings, 0 replies; 39+ messages in thread
From: Li, Pan2 @ 2023-06-08 8:01 UTC (permalink / raw)
To: Kito Cheng, juzhe.zhong
Cc: gcc-patches, Robin Dapp, jeffreyalaw, Wang, Yanzhang
Looks doable up to a point, I will have a try and keep you posted.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Thursday, June 8, 2023 3:58 PM
To: juzhe.zhong@rivai.ai
Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>; Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
I am thinking, is it possible to use mode attr to remove the overhead of checking the mode for other FP modes other than FP16?
e.g.
(define_mode_attr TARGET_FP_FULL_OPERATION_CHECKING [
(VNx1HF "TARGET_ZVFH")
...
(VNx1SF "1")
...
])
"TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
->
"TARGET_VECTOR && <TARGET_FP_FULL_OPERATION_CHECKING>"
On Thu, Jun 8, 2023 at 2:35 PM juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai> wrote:
>
> LGTM. Let's wait for Jeff and Robin. After this patch, we can start FP16 autovec.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: pan2.li
> Date: 2023-06-08 14:29
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang;
> kito.cheng
> Subject: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to refactor the requirement of both the ZVFH and
> ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
> iterators of RVV. And then the ZVFH will leverage one function as the
> gate for FP16 supported or not.
>
> Please note the ZVFH will cover the ZVFHMIN instructions. This patch
> add one test for this.
>
> Signed-off-by: Pan Li <pan2.li@intel.com> Co-Authored by: Juzhe-Zhong
> <juzhe.zhong@rivai.ai>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (float_mode_supported_p):
> New function to float point is supported by extension.
> * config/riscv/riscv-v.cc (float_mode_supported_p):
> Ditto.
> * config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
> * config/riscv/vector.md: Add condition to FP define insn.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test for
> ZVFHMIN.
> ---
> gcc/config/riscv/riscv-protos.h | 1 +
> gcc/config/riscv/riscv-v.cc | 12 ++
> gcc/config/riscv/vector-iterators.md | 23 +--
> gcc/config/riscv/vector.md | 144 ++++++++++--------
> .../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +-
> 5 files changed, 118 insertions(+), 77 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h
> b/gcc/config/riscv/riscv-protos.h index ebbaac255f9..1f606f59ce1
> 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -177,6 +177,7 @@ rtx expand_builtin (unsigned int, tree, rtx); bool
> check_builtin_call (location_t, vec<location_t>, unsigned int,
> tree, unsigned int, tree *);
> bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT,
> HOST_WIDE_INT);
> +bool float_mode_supported_p (machine_mode mode);
> bool legitimize_move (rtx, rtx);
> void emit_vlmax_vsetvl (machine_mode, rtx); void
> emit_hard_vlmax_vsetvl (machine_mode, rtx); diff --git
> a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index
> 49752cd8899..fe4eb058ec0 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -418,6 +418,18 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
> && IN_RANGE (INTVAL (elt), minval, maxval)); }
> +/* Return true if the inner of mode is HFmode when ZVFH enabled, or other
> + float point machine mode. */
> +bool
> +float_mode_supported_p (machine_mode mode) {
> + machine_mode inner_mode = GET_MODE_INNER (mode);
> +
> + gcc_assert (FLOAT_MODE_P (inner_mode));
> +
> + return inner_mode == HFmode ? TARGET_ZVFH : true; }
> +
> /* Return true if VEC is a constant in which every element is in the range
> [MINVAL, MAXVAL]. The elements do not need to have the same value.
> diff --git a/gcc/config/riscv/vector-iterators.md
> b/gcc/config/riscv/vector-iterators.md
> index f4946d84449..234b712bc9d 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
> (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
> (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64")
> (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
> - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> - (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
> - (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
> + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
> + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
> (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
> (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
> (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") @@
> -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
> (define_mode_iterator V_FRACT [
> (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
> (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32")
> (VNx4HI "TARGET_MIN_VLEN >= 128")
> - (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32")
> (VNx4HF "TARGET_MIN_VLEN >= 128")
> +
> + (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") (VNx4HF
> + "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
> +
> (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
> (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
> (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") @@
> -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
> ])
> (define_mode_iterator VWEXTF [
> - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> - (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
> - (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> + (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 &&
> + TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_16 &&
> + TARGET_VECTOR_ELEN_FP_32") (VNx4SF "TARGET_VECTOR_ELEN_FP_16 &&
> + TARGET_VECTOR_ELEN_FP_32") (VNx8SF "TARGET_VECTOR_ELEN_FP_16 &&
> + TARGET_VECTOR_ELEN_FP_32") (VNx16SF "TARGET_VECTOR_ELEN_FP_16 &&
> + TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") (VNx32SF
> + "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 &&
> + TARGET_MIN_VLEN >= 128")
> (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
> (VNx2DF "TARGET_VECTOR_ELEN_FP_64") diff --git
> a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index
> 1d1847bd85a..2fe0233f102 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -1364,7 +1364,7 @@ (define_insn "*pred_broadcast<mode>"
> (vec_duplicate:VF
> (match_operand:<VEL> 3 "direct_broadcast_operand" " f, f,Wdm,Wdm,Wdm,Wdm, f, f"))
> (match_operand:VF 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vfmv.v.f\t%0,%3
> vfmv.v.f\t%0,%3
> @@ -5685,7 +5685,7 @@ (define_insn "@pred_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5705,7 +5705,7 @@ (define_insn "@pred_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5728,7 +5728,7 @@ (define_insn "@pred_<optab><mode>_scalar"
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5749,7 +5749,7 @@ (define_insn "@pred_<optab><mode>_scalar"
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5772,7 +5772,7 @@ (define_insn "@pred_<optab><mode>_scalar"
> (vec_duplicate:VF
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5795,7 +5795,7 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfr<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5815,7 +5815,7 @@ (define_insn "@pred_<copysign><mode>"
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS)
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfsgnj<nx>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vfsgnj")
> (set_attr "mode" "<MODE>")])
> @@ -5836,7 +5836,7 @@ (define_insn "@pred_<copysign><mode>_scalar"
> (vec_duplicate:VF
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS)
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfsgnj<nx>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfsgnj")
> (set_attr "mode" "<MODE>")])
> @@ -5894,7 +5894,7 @@ (define_insn "*pred_<madd_msub><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<madd_msub>.vv\t%0,%3,%4%p1
> vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
> @@ -5927,7 +5927,7 @@ (define_insn "*pred_<macc_msac><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<macc_msac>.vv\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
> @@ -5960,7 +5960,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[2], operands[5])
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> @@ -6021,7 +6021,7 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
> (match_operand:VF 3 "register_operand" " 0, vr, 0, vr"))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 3)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<madd_msub>.vf\t%0,%2,%4%p1
> vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
> @@ -6055,7 +6055,7 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<macc_msac>.vf\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
> @@ -6089,7 +6089,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> "@
> @@ -6154,7 +6154,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
> vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
> @@ -6188,7 +6188,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
> @@ -6222,7 +6222,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr")))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[2], operands[5])
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> @@ -6285,7 +6285,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
> (match_operand:VF 3 "register_operand" " 0, vr, 0, vr")))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 3)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
> vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
> @@ -6320,7 +6320,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
> @@ -6355,7 +6355,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr")))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> "@
> @@ -6399,7 +6399,7 @@ (define_insn "@pred_<optab><mode>"
> (any_float_unop:VF
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")
> @@ -6422,7 +6422,7 @@ (define_insn "@pred_<optab><mode>"
> (any_float_unop_nofrm:VF
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")
> @@ -6445,7 +6445,7 @@ (define_insn "@pred_<misc_op><mode>"
> (unspec:VF
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<misc_op>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -6464,7 +6464,7 @@ (define_insn "@pred_class<mode>"
> (unspec:<VCONVERT>
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
> (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu,
> 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfclass.v\t%0,%3%p1"
> [(set_attr "type" "vfclass")
> (set_attr "mode" "<MODE>")])
> @@ -6497,7 +6497,7 @@ (define_insn "@pred_dual_widen_<optab><mode>"
> (float_extend:VWEXTF
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")]) @@ -6522,7 +6522,7 @@
> (define_insn "@pred_dual_widen_<optab><mode>_scalar"
> (vec_duplicate:<V_DOUBLE_TRUNC>
> (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")]) @@ -6545,7 +6545,7 @@
> (define_insn "@pred_single_widen_<plus_minus:optab><mode>"
> (float_extend:VWEXTF
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.wv\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")]) @@ -6569,7 +6569,7 @@
> (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
> (vec_duplicate:<V_DOUBLE_TRUNC>
> (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.wf\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")]) @@ -6602,7 +6602,7 @@
> (define_insn "@pred_widen_mul_<optab><mode>"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<macc_msac>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")]) @@ -6629,7 +6629,7 @@
> (define_insn "@pred_widen_mul_<optab><mode>_scalar"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<macc_msac>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")]) @@ -6656,7 +6656,7 @@
> (define_insn "@pred_widen_mul_neg_<optab><mode>"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")]) @@ -6684,7 +6684,7 @@
> (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")]) @@ -6728,7 +6728,8 @@
> (define_insn "*pred_cmp<mode>"
> [(match_operand:VF 4 "register_operand" " vr, vr")
> (match_operand:VF 5 "register_operand" " vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vv\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6747,7 +6748,7 @@ (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
> [(match_operand:VF 3 "register_operand" " vr")
> (match_operand:VF 4 "register_operand" " vr")])
> (match_dup 1)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B2.vv\t%0,%3,%4,v0.t"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")
> @@ -6771,7 +6772,8 @@ (define_insn "*pred_cmp<mode>_narrow"
> [(match_operand:VF 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
> (match_operand:VF 5 "register_operand" " vr, vr, 0, 0, vr, 0, 0, vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
> - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vv\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6809,7 +6811,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
> (vec_duplicate:VF
> (match_operand:<VEL> 4 "register_operand" " f"))])
> (match_dup 1)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B2.vf\t%0,%3,%4,v0.t"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")
> @@ -6834,7 +6836,8 @@ (define_insn "*pred_cmp<mode>_scalar"
> (vec_duplicate:VF
> (match_operand:<VEL> 5 "register_operand" " f, f"))])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6855,7 +6858,8 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
> (vec_duplicate:VF
> (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
> - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6893,7 +6897,7 @@ (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
> (match_operand:<VEL> 4 "register_operand" " f"))
> (match_operand:VF 3 "register_operand" " vr")])
> (match_dup 1)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B2.vf\t%0,%3,%4,v0.t"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")
> @@ -6918,7 +6922,8 @@ (define_insn "*pred_eqne<mode>_scalar"
> (match_operand:<VEL> 5 "register_operand" " f, f"))
> (match_operand:VF 4 "register_operand" " vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6939,7 +6944,8 @@ (define_insn "*pred_eqne<mode>_scalar_narrow"
> (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
> (match_operand:VF 4 "register_operand" " vr, 0, 0, vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
> - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6966,7 +6972,7 @@ (define_insn "@pred_merge<mode>_scalar"
> (match_operand:VF 2 "register_operand" " vr,vr")
> (match_operand:<VM> 4 "register_operand" " vm,vm"))
> (match_operand:VF 1 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfmerge.vfm\t%0,%2,%3,%4"
> [(set_attr "type" "vfmerge")
> (set_attr "mode" "<MODE>")])
> @@ -6994,7 +7000,7 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
> (unspec:<VCONVERT>
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS)
> (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu,
> 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfcvt.x<v_su>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfcvtftoi")
> (set_attr "mode" "<MODE>")])
> @@ -7013,7 +7019,7 @@ (define_insn "@pred_<fix_cvt><mode>"
> (any_fix:<VCONVERT>
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu,
> 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfcvtftoi")
> (set_attr "mode" "<MODE>")])
> @@ -7034,7 +7040,7 @@ (define_insn "@pred_<float_cvt><mode>"
> (any_float:VF
> (match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfcvt.f.x<u>.v\t%0,%3%p1"
> [(set_attr "type" "vfcvtitof")
> (set_attr "mode" "<MODE>")])
> @@ -7062,7 +7068,7 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
> (unspec:VWCONVERTI
> [(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")] VFCVTS)
> (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfwcvt.x<v_su>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7081,7 +7087,7 @@ (define_insn "@pred_widen_<fix_cvt><mode>"
> (any_fix:VWCONVERTI
> (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
> (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7100,7 +7106,7 @@ (define_insn "@pred_widen_<float_cvt><mode>"
> (any_float:VF
> (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwcvt.f.x<u>.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtitof")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7119,7 +7125,7 @@ (define_insn "@pred_extend<mode>"
> (float_extend:VWEXTF
> (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwcvt.f.f.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtftof")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")]) @@ -7147,7 +7153,7 @@
> (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
> (unspec:<VNCONVERT>
> [(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS)
> (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfncvt.x<v_su>.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7166,7 +7172,7 @@ (define_insn "@pred_narrow_<fix_cvt><mode>"
> (any_fix:<VNCONVERT>
> (match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
> (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7187,7 +7193,7 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
> (any_float:<VNCONVERT>
> (match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
> (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfncvt.f.x<u>.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtitof")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7208,7 +7214,7 @@ (define_insn "@pred_trunc<mode>"
> (float_truncate:<V_DOUBLE_TRUNC>
> (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
> (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfncvt.f.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftof")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")]) @@ -7228,7 +7234,7 @@
> (define_insn "@pred_rod_trunc<mode>"
> [(float_truncate:<V_DOUBLE_TRUNC>
> (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
> (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfncvt.rod.f.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftof")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")]) @@ -7389,7 +7395,8 @@
> (define_insn "@pred_reduc_<reduc><mode><vlmul1>"
> (parallel [(const_int 0)])))
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> + "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<reduc>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfredu")
> (set_attr "mode" "<MODE>")])
> @@ -7413,7 +7420,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve64>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<reduc>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfredu")
> (set_attr "mode" "<MODE>")])
> @@ -7437,7 +7445,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 32
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<reduc>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfredu")
> (set_attr "mode" "<MODE>")])
> @@ -7462,7 +7471,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1>"
> (parallel [(const_int 0)])))
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> + "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7487,7 +7497,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve64>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7512,7 +7523,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve32>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 32
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7533,7 +7545,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1>"
> (match_operand:VWF 3 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1> 4 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> + "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfwred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7554,7 +7567,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>"
> (match_operand:VWF_ZVE64 3 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1_ZVE64> 4 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfwred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7657,7 +7671,7 @@ (define_insn "*pred_extract_first<mode>"
> (match_operand:VF 1 "register_operand" "vr")
> (parallel [(const_int 0)]))
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfmv.f.s\t%0,%1"
> [(set_attr "type" "vfmovvf")
> (set_attr "mode" "<MODE>")])
> @@ -7778,7 +7792,7 @@ (define_insn "@pred_slide<ud><mode>"
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f")] VFSLIDES1))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfslide<ud>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfslide<ud>")
> (set_attr "mode" "<MODE>")])
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> index 0923b6bc4d2..f1a29b639e0 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> @@ -3,6 +3,8 @@
> #include "riscv_vector.h"
> +typedef _Float16 float16_t;
> +
> vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
> return __riscv_vfncvt_f_f_w_f16mf4(src, vl); } @@ -43,11 +45,20 @@
> vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
> return __riscv_vfwcvt_f_f_v_f32m8(src, vl); }
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
> +vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
> + return __riscv_vle16_v_f16mf4(base, vl); }
> +
> +vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
> + return __riscv_vle16_v_f16m8(base, vl); }
> +
> +/* { dg-final { scan-assembler-times
> +{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } }
> +*/
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
> +/* { dg-final { scan-assembler-times
> +{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
> /* { dg-final { scan-assembler-times
> {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> /* { dg-final { scan-assembler-times
> {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> -
> +/* { dg-final { scan-assembler-times
> +{vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-08 7:58 ` Kito Cheng
2023-06-08 8:00 ` juzhe.zhong
2023-06-08 8:01 ` Li, Pan2
@ 2023-06-08 8:32 ` juzhe.zhong
2023-06-08 13:13 ` Li, Pan2
2 siblings, 1 reply; 39+ messages in thread
From: juzhe.zhong @ 2023-06-08 8:32 UTC (permalink / raw)
To: kito.cheng; +Cc: pan2.li, gcc-patches, Robin Dapp, jeffreyalaw, yanzhang.wang
[-- Attachment #1: Type: text/plain, Size: 42336 bytes --]
I have an idea base on what Kito said.
We enable vfadd FP16 for TARGET_ZVFH. But we don't need to add TARGET_VECTOR && <TARGET_FP_FULL_OPERATION_CHECKING>
for each instruction.
We can reference riscv.md:
(define_attr "ext_enabled" "no,yes"
(cond [(eq_attr "ext" "base")
(const_string "yes")
(and (eq_attr "ext" "f")
(match_test "TARGET_HARD_FLOAT"))
(const_string "yes")
(and (eq_attr "ext" "d")
(match_test "TARGET_DOUBLE_FLOAT"))
(const_string "yes")
(and (eq_attr "ext" "vector")
(match_test "TARGET_VECTOR"))
(const_string "yes")
]
(const_string "no")))
Define a new attribute as follows:
(define_attr "fp16_vector_enabled" "no,yes"
(cond [
(and (eq_attr "type" "vfalu")
(and eq_attr "mode" "VNx1HF")
(match_test "!TARGET_ZVFH")))
(const_string "no")
]
(const_string "yes")))
I think you can do experiment with this to see whether it can disable MD pattern.
juzhe.zhong@rivai.ai
From: Kito Cheng
Date: 2023-06-08 15:58
To: juzhe.zhong@rivai.ai
CC: pan2.li; gcc-patches; Robin Dapp; jeffreyalaw; yanzhang.wang
Subject: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
I am thinking, is it possible to use mode attr to remove the overhead
of checking the mode for other FP modes other than FP16?
e.g.
(define_mode_attr TARGET_FP_FULL_OPERATION_CHECKING [
(VNx1HF "TARGET_ZVFH")
...
(VNx1SF "1")
...
])
"TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
->
"TARGET_VECTOR && <TARGET_FP_FULL_OPERATION_CHECKING>"
On Thu, Jun 8, 2023 at 2:35 PM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> LGTM. Let's wait for Jeff and Robin. After this patch, we can start FP16 autovec.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: pan2.li
> Date: 2023-06-08 14:29
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
> Subject: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to refactor the requirement of both the ZVFH
> and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
> iterators of RVV. And then the ZVFH will leverage one function as
> the gate for FP16 supported or not.
>
> Please note the ZVFH will cover the ZVFHMIN instructions. This patch
> add one test for this.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (float_mode_supported_p):
> New function to float point is supported by extension.
> * config/riscv/riscv-v.cc (float_mode_supported_p):
> Ditto.
> * config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
> * config/riscv/vector.md: Add condition to FP define insn.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
> for ZVFHMIN.
> ---
> gcc/config/riscv/riscv-protos.h | 1 +
> gcc/config/riscv/riscv-v.cc | 12 ++
> gcc/config/riscv/vector-iterators.md | 23 +--
> gcc/config/riscv/vector.md | 144 ++++++++++--------
> .../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +-
> 5 files changed, 118 insertions(+), 77 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index ebbaac255f9..1f606f59ce1 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -177,6 +177,7 @@ rtx expand_builtin (unsigned int, tree, rtx);
> bool check_builtin_call (location_t, vec<location_t>, unsigned int,
> tree, unsigned int, tree *);
> bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
> +bool float_mode_supported_p (machine_mode mode);
> bool legitimize_move (rtx, rtx);
> void emit_vlmax_vsetvl (machine_mode, rtx);
> void emit_hard_vlmax_vsetvl (machine_mode, rtx);
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 49752cd8899..fe4eb058ec0 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -418,6 +418,18 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
> && IN_RANGE (INTVAL (elt), minval, maxval));
> }
> +/* Return true if the inner of mode is HFmode when ZVFH enabled, or other
> + float point machine mode. */
> +bool
> +float_mode_supported_p (machine_mode mode)
> +{
> + machine_mode inner_mode = GET_MODE_INNER (mode);
> +
> + gcc_assert (FLOAT_MODE_P (inner_mode));
> +
> + return inner_mode == HFmode ? TARGET_ZVFH : true;
> +}
> +
> /* Return true if VEC is a constant in which every element is in the range
> [MINVAL, MAXVAL]. The elements do not need to have the same value.
> diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
> index f4946d84449..234b712bc9d 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
> (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
> (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
> - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> - (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
> - (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
> + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
> + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
> (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
> (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
> (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
> @@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
> (define_mode_iterator V_FRACT [
> (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
> (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
> - (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
> +
> + (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
> + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
> +
> (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
> (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
> (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> @@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
> ])
> (define_mode_iterator VWEXTF [
> - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> - (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
> - (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> + (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> + (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> + (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> + (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> + (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
> + (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
> (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index 1d1847bd85a..2fe0233f102 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -1364,7 +1364,7 @@ (define_insn "*pred_broadcast<mode>"
> (vec_duplicate:VF
> (match_operand:<VEL> 3 "direct_broadcast_operand" " f, f,Wdm,Wdm,Wdm,Wdm, f, f"))
> (match_operand:VF 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vfmv.v.f\t%0,%3
> vfmv.v.f\t%0,%3
> @@ -5685,7 +5685,7 @@ (define_insn "@pred_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5705,7 +5705,7 @@ (define_insn "@pred_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5728,7 +5728,7 @@ (define_insn "@pred_<optab><mode>_scalar"
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5749,7 +5749,7 @@ (define_insn "@pred_<optab><mode>_scalar"
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5772,7 +5772,7 @@ (define_insn "@pred_<optab><mode>_scalar"
> (vec_duplicate:VF
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5795,7 +5795,7 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfr<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5815,7 +5815,7 @@ (define_insn "@pred_<copysign><mode>"
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS)
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfsgnj<nx>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vfsgnj")
> (set_attr "mode" "<MODE>")])
> @@ -5836,7 +5836,7 @@ (define_insn "@pred_<copysign><mode>_scalar"
> (vec_duplicate:VF
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS)
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfsgnj<nx>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfsgnj")
> (set_attr "mode" "<MODE>")])
> @@ -5894,7 +5894,7 @@ (define_insn "*pred_<madd_msub><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<madd_msub>.vv\t%0,%3,%4%p1
> vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
> @@ -5927,7 +5927,7 @@ (define_insn "*pred_<macc_msac><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<macc_msac>.vv\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
> @@ -5960,7 +5960,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[2], operands[5])
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> @@ -6021,7 +6021,7 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
> (match_operand:VF 3 "register_operand" " 0, vr, 0, vr"))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 3)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<madd_msub>.vf\t%0,%2,%4%p1
> vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
> @@ -6055,7 +6055,7 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<macc_msac>.vf\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
> @@ -6089,7 +6089,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> "@
> @@ -6154,7 +6154,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
> vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
> @@ -6188,7 +6188,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
> @@ -6222,7 +6222,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr")))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[2], operands[5])
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> @@ -6285,7 +6285,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
> (match_operand:VF 3 "register_operand" " 0, vr, 0, vr")))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 3)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
> vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
> @@ -6320,7 +6320,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
> @@ -6355,7 +6355,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr")))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> "@
> @@ -6399,7 +6399,7 @@ (define_insn "@pred_<optab><mode>"
> (any_float_unop:VF
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")
> @@ -6422,7 +6422,7 @@ (define_insn "@pred_<optab><mode>"
> (any_float_unop_nofrm:VF
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")
> @@ -6445,7 +6445,7 @@ (define_insn "@pred_<misc_op><mode>"
> (unspec:VF
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<misc_op>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -6464,7 +6464,7 @@ (define_insn "@pred_class<mode>"
> (unspec:<VCONVERT>
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
> (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfclass.v\t%0,%3%p1"
> [(set_attr "type" "vfclass")
> (set_attr "mode" "<MODE>")])
> @@ -6497,7 +6497,7 @@ (define_insn "@pred_dual_widen_<optab><mode>"
> (float_extend:VWEXTF
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6522,7 +6522,7 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
> (vec_duplicate:<V_DOUBLE_TRUNC>
> (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6545,7 +6545,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>"
> (float_extend:VWEXTF
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.wv\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6569,7 +6569,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
> (vec_duplicate:<V_DOUBLE_TRUNC>
> (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.wf\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6602,7 +6602,7 @@ (define_insn "@pred_widen_mul_<optab><mode>"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<macc_msac>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6629,7 +6629,7 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<macc_msac>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6656,7 +6656,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6684,7 +6684,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6728,7 +6728,8 @@ (define_insn "*pred_cmp<mode>"
> [(match_operand:VF 4 "register_operand" " vr, vr")
> (match_operand:VF 5 "register_operand" " vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vv\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6747,7 +6748,7 @@ (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
> [(match_operand:VF 3 "register_operand" " vr")
> (match_operand:VF 4 "register_operand" " vr")])
> (match_dup 1)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B2.vv\t%0,%3,%4,v0.t"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")
> @@ -6771,7 +6772,8 @@ (define_insn "*pred_cmp<mode>_narrow"
> [(match_operand:VF 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
> (match_operand:VF 5 "register_operand" " vr, vr, 0, 0, vr, 0, 0, vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
> - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vv\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6809,7 +6811,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
> (vec_duplicate:VF
> (match_operand:<VEL> 4 "register_operand" " f"))])
> (match_dup 1)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B2.vf\t%0,%3,%4,v0.t"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")
> @@ -6834,7 +6836,8 @@ (define_insn "*pred_cmp<mode>_scalar"
> (vec_duplicate:VF
> (match_operand:<VEL> 5 "register_operand" " f, f"))])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6855,7 +6858,8 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
> (vec_duplicate:VF
> (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
> - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6893,7 +6897,7 @@ (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
> (match_operand:<VEL> 4 "register_operand" " f"))
> (match_operand:VF 3 "register_operand" " vr")])
> (match_dup 1)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B2.vf\t%0,%3,%4,v0.t"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")
> @@ -6918,7 +6922,8 @@ (define_insn "*pred_eqne<mode>_scalar"
> (match_operand:<VEL> 5 "register_operand" " f, f"))
> (match_operand:VF 4 "register_operand" " vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6939,7 +6944,8 @@ (define_insn "*pred_eqne<mode>_scalar_narrow"
> (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
> (match_operand:VF 4 "register_operand" " vr, 0, 0, vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
> - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6966,7 +6972,7 @@ (define_insn "@pred_merge<mode>_scalar"
> (match_operand:VF 2 "register_operand" " vr,vr")
> (match_operand:<VM> 4 "register_operand" " vm,vm"))
> (match_operand:VF 1 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfmerge.vfm\t%0,%2,%3,%4"
> [(set_attr "type" "vfmerge")
> (set_attr "mode" "<MODE>")])
> @@ -6994,7 +7000,7 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
> (unspec:<VCONVERT>
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS)
> (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfcvt.x<v_su>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfcvtftoi")
> (set_attr "mode" "<MODE>")])
> @@ -7013,7 +7019,7 @@ (define_insn "@pred_<fix_cvt><mode>"
> (any_fix:<VCONVERT>
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfcvtftoi")
> (set_attr "mode" "<MODE>")])
> @@ -7034,7 +7040,7 @@ (define_insn "@pred_<float_cvt><mode>"
> (any_float:VF
> (match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfcvt.f.x<u>.v\t%0,%3%p1"
> [(set_attr "type" "vfcvtitof")
> (set_attr "mode" "<MODE>")])
> @@ -7062,7 +7068,7 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
> (unspec:VWCONVERTI
> [(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")] VFCVTS)
> (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfwcvt.x<v_su>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7081,7 +7087,7 @@ (define_insn "@pred_widen_<fix_cvt><mode>"
> (any_fix:VWCONVERTI
> (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
> (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7100,7 +7106,7 @@ (define_insn "@pred_widen_<float_cvt><mode>"
> (any_float:VF
> (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwcvt.f.x<u>.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtitof")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7119,7 +7125,7 @@ (define_insn "@pred_extend<mode>"
> (float_extend:VWEXTF
> (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwcvt.f.f.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtftof")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -7147,7 +7153,7 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
> (unspec:<VNCONVERT>
> [(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS)
> (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfncvt.x<v_su>.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7166,7 +7172,7 @@ (define_insn "@pred_narrow_<fix_cvt><mode>"
> (any_fix:<VNCONVERT>
> (match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
> (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7187,7 +7193,7 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
> (any_float:<VNCONVERT>
> (match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
> (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfncvt.f.x<u>.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtitof")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7208,7 +7214,7 @@ (define_insn "@pred_trunc<mode>"
> (float_truncate:<V_DOUBLE_TRUNC>
> (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
> (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfncvt.f.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftof")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -7228,7 +7234,7 @@ (define_insn "@pred_rod_trunc<mode>"
> [(float_truncate:<V_DOUBLE_TRUNC>
> (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
> (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfncvt.rod.f.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftof")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -7389,7 +7395,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1>"
> (parallel [(const_int 0)])))
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> + "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<reduc>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfredu")
> (set_attr "mode" "<MODE>")])
> @@ -7413,7 +7420,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve64>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<reduc>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfredu")
> (set_attr "mode" "<MODE>")])
> @@ -7437,7 +7445,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 32
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<reduc>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfredu")
> (set_attr "mode" "<MODE>")])
> @@ -7462,7 +7471,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1>"
> (parallel [(const_int 0)])))
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> + "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7487,7 +7497,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve64>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7512,7 +7523,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve32>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 32
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7533,7 +7545,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1>"
> (match_operand:VWF 3 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1> 4 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> + "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfwred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7554,7 +7567,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>"
> (match_operand:VWF_ZVE64 3 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1_ZVE64> 4 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfwred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7657,7 +7671,7 @@ (define_insn "*pred_extract_first<mode>"
> (match_operand:VF 1 "register_operand" "vr")
> (parallel [(const_int 0)]))
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfmv.f.s\t%0,%1"
> [(set_attr "type" "vfmovvf")
> (set_attr "mode" "<MODE>")])
> @@ -7778,7 +7792,7 @@ (define_insn "@pred_slide<ud><mode>"
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f")] VFSLIDES1))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfslide<ud>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfslide<ud>")
> (set_attr "mode" "<MODE>")])
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> index 0923b6bc4d2..f1a29b639e0 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> @@ -3,6 +3,8 @@
> #include "riscv_vector.h"
> +typedef _Float16 float16_t;
> +
> vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
> return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
> }
> @@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
> return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
> }
> -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
> +vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
> + return __riscv_vle16_v_f16mf4(base, vl);
> +}
> +
> +vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
> + return __riscv_vle16_v_f16m8(base, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
> /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> -
> +/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-08 8:32 ` juzhe.zhong
@ 2023-06-08 13:13 ` Li, Pan2
2023-06-08 13:24 ` Kito Cheng
0 siblings, 1 reply; 39+ messages in thread
From: Li, Pan2 @ 2023-06-08 13:13 UTC (permalink / raw)
To: juzhe.zhong, kito.cheng
Cc: gcc-patches, Robin Dapp, jeffreyalaw, Wang, Yanzhang
[-- Attachment #1: Type: text/plain, Size: 44288 bytes --]
Thanks Juzhe for the idea. It looks work well as we expected, with the following try.
1. Allow all FP=16 types for vfadd, then _zvfh and _zvfhmin will be OK.
2. Add restriction define_attr as juzhe mentioned, then _zvfh works well, and _zvfhmin will meet error like unsatisfied insn.
I think only we need to do is the define_attr, and there will be no changes to vector.md. If no more concern, will have a try for this approach.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Thursday, June 8, 2023 4:32 PM
To: kito.cheng <kito.cheng@gmail.com>
Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>; Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
I have an idea base on what Kito said.
We enable vfadd FP16 for TARGET_ZVFH. But we don't need to add TARGET_VECTOR && <TARGET_FP_FULL_OPERATION_CHECKING>
for each instruction.
We can reference riscv.md:
(define_attr "ext_enabled" "no,yes"
(cond [(eq_attr "ext" "base")
(const_string "yes")
(and (eq_attr "ext" "f")
(match_test "TARGET_HARD_FLOAT"))
(const_string "yes")
(and (eq_attr "ext" "d")
(match_test "TARGET_DOUBLE_FLOAT"))
(const_string "yes")
(and (eq_attr "ext" "vector")
(match_test "TARGET_VECTOR"))
(const_string "yes")
]
(const_string "no")))
Define a new attribute as follows:
(define_attr "fp16_vector_enabled" "no,yes"
(cond [
(and (eq_attr "type" "vfalu")
(and eq_attr "mode" "VNx1HF")
(match_test "!TARGET_ZVFH")))
(const_string "no")
]
(const_string "yes")))
I think you can do experiment with this to see whether it can disable MD pattern.
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: Kito Cheng<mailto:kito.cheng@gmail.com>
Date: 2023-06-08 15:58
To: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
CC: pan2.li<mailto:pan2.li@intel.com>; gcc-patches<mailto:gcc-patches@gcc.gnu.org>; Robin Dapp<mailto:rdapp.gcc@gmail.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
I am thinking, is it possible to use mode attr to remove the overhead
of checking the mode for other FP modes other than FP16?
e.g.
(define_mode_attr TARGET_FP_FULL_OPERATION_CHECKING [
(VNx1HF "TARGET_ZVFH")
...
(VNx1SF "1")
...
])
"TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
->
"TARGET_VECTOR && <TARGET_FP_FULL_OPERATION_CHECKING>"
On Thu, Jun 8, 2023 at 2:35 PM juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
<juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>> wrote:
>
> LGTM. Let's wait for Jeff and Robin. After this patch, we can start FP16 autovec.
>
>
>
> juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
>
> From: pan2.li
> Date: 2023-06-08 14:29
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
> Subject: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
> From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
>
> This patch would like to refactor the requirement of both the ZVFH
> and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
> iterators of RVV. And then the ZVFH will leverage one function as
> the gate for FP16 supported or not.
>
> Please note the ZVFH will cover the ZVFHMIN instructions. This patch
> add one test for this.
>
> Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
> Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (float_mode_supported_p):
> New function to float point is supported by extension.
> * config/riscv/riscv-v.cc (float_mode_supported_p):
> Ditto.
> * config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
> * config/riscv/vector.md: Add condition to FP define insn.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
> for ZVFHMIN.
> ---
> gcc/config/riscv/riscv-protos.h | 1 +
> gcc/config/riscv/riscv-v.cc | 12 ++
> gcc/config/riscv/vector-iterators.md | 23 +--
> gcc/config/riscv/vector.md | 144 ++++++++++--------
> .../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +-
> 5 files changed, 118 insertions(+), 77 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index ebbaac255f9..1f606f59ce1 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -177,6 +177,7 @@ rtx expand_builtin (unsigned int, tree, rtx);
> bool check_builtin_call (location_t, vec<location_t>, unsigned int,
> tree, unsigned int, tree *);
> bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
> +bool float_mode_supported_p (machine_mode mode);
> bool legitimize_move (rtx, rtx);
> void emit_vlmax_vsetvl (machine_mode, rtx);
> void emit_hard_vlmax_vsetvl (machine_mode, rtx);
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 49752cd8899..fe4eb058ec0 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -418,6 +418,18 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
> && IN_RANGE (INTVAL (elt), minval, maxval));
> }
> +/* Return true if the inner of mode is HFmode when ZVFH enabled, or other
> + float point machine mode. */
> +bool
> +float_mode_supported_p (machine_mode mode)
> +{
> + machine_mode inner_mode = GET_MODE_INNER (mode);
> +
> + gcc_assert (FLOAT_MODE_P (inner_mode));
> +
> + return inner_mode == HFmode ? TARGET_ZVFH : true;
> +}
> +
> /* Return true if VEC is a constant in which every element is in the range
> [MINVAL, MAXVAL]. The elements do not need to have the same value.
> diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
> index f4946d84449..234b712bc9d 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
> (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
> (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
> - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> - (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
> - (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
> + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
> + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
> (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
> (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
> (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
> @@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
> (define_mode_iterator V_FRACT [
> (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
> (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
> - (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
> +
> + (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
> + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
> +
> (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
> (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
> (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> @@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
> ])
> (define_mode_iterator VWEXTF [
> - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> - (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
> - (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> + (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> + (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> + (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> + (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> + (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
> + (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
> (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index 1d1847bd85a..2fe0233f102 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -1364,7 +1364,7 @@ (define_insn "*pred_broadcast<mode>"
> (vec_duplicate:VF
> (match_operand:<VEL> 3 "direct_broadcast_operand" " f, f,Wdm,Wdm,Wdm,Wdm, f, f"))
> (match_operand:VF 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@<mailto:%22@%0d%3e %20vfmv.v.f\t%250,%253%0d%3e %20vfmv.v.f\t%250,%253%0d%3e%20@@%20-5685,7%20+5685,7%20@@%20(define_insn%20%22@pred_%3coptab%3e%3cmode>
> vfmv.v.f\t%0,%3<mailto:%22@%0d%3e %20vfmv.v.f\t%250,%253%0d%3e %20vfmv.v.f\t%250,%253%0d%3e%20@@%20-5685,7%20+5685,7%20@@%20(define_insn%20%22@pred_%3coptab%3e%3cmode>
> vfmv.v.f\t%0,%3<mailto:%22@%0d%3e %20vfmv.v.f\t%250,%253%0d%3e %20vfmv.v.f\t%250,%253%0d%3e%20@@%20-5685,7%20+5685,7%20@@%20(define_insn%20%22@pred_%3coptab%3e%3cmode>
> @@ -5685,7 +5685,7 @@ (define_insn "@pred_<optab><mode<mailto:%22@%0d%3e %20vfmv.v.f\t%250,%253%0d%3e %20vfmv.v.f\t%250,%253%0d%3e%20@@%20-5685,7%20+5685,7%20@@%20(define_insn%20%22@pred_%3coptab%3e%3cmode>>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5705,7 +5705,7 @@ (define_insn "@pred_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5728,7 +5728,7 @@ (define_insn "@pred_<optab><mode>_scalar"
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5749,7 +5749,7 @@ (define_insn "@pred_<optab><mode>_scalar"
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5772,7 +5772,7 @@ (define_insn "@pred_<optab><mode>_scalar"
> (vec_duplicate:VF
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5795,7 +5795,7 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfr<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -5815,7 +5815,7 @@ (define_insn "@pred_<copysign><mode>"
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS)
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfsgnj<nx>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vfsgnj")
> (set_attr "mode" "<MODE>")])
> @@ -5836,7 +5836,7 @@ (define_insn "@pred_<copysign><mode>_scalar"
> (vec_duplicate:VF
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS)
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfsgnj<nx>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfsgnj")
> (set_attr "mode" "<MODE>")])
> @@ -5894,7 +5894,7 @@ (define_insn "*pred_<madd_msub><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<madd_msub>.vv\t%0,%3,%4%p1
> vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
> @@ -5927,7 +5927,7 @@ (define_insn "*pred_<macc_msac><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<macc_msac>.vv\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
> @@ -5960,7 +5960,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[2], operands[5])
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> @@ -6021,7 +6021,7 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
> (match_operand:VF 3 "register_operand" " 0, vr, 0, vr"))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 3)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<madd_msub>.vf\t%0,%2,%4%p1
> vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
> @@ -6055,7 +6055,7 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<macc_msac>.vf\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
> @@ -6089,7 +6089,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> "@
> @@ -6154,7 +6154,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
> vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
> @@ -6188,7 +6188,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
> @@ -6222,7 +6222,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
> (match_operand:VF 3 "register_operand" " vr, vr")))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[2], operands[5])
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> @@ -6285,7 +6285,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
> (match_operand:VF 3 "register_operand" " 0, vr, 0, vr")))
> (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> (match_dup 3)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
> vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
> @@ -6320,7 +6320,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
> (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> (match_dup 4)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "@
> vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
> vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
> @@ -6355,7 +6355,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
> (match_operand:VF 3 "register_operand" " vr, vr")))
> (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> (match_operand:VF 5 "register_operand" " 0, vr")))]
> - "TARGET_VECTOR
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> && !rtx_equal_p (operands[3], operands[5])
> && !rtx_equal_p (operands[4], operands[5])"
> "@
> @@ -6399,7 +6399,7 @@ (define_insn "@pred_<optab><mode>"
> (any_float_unop:VF
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")
> @@ -6422,7 +6422,7 @@ (define_insn "@pred_<optab><mode>"
> (any_float_unop_nofrm:VF
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<insn>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")
> @@ -6445,7 +6445,7 @@ (define_insn "@pred_<misc_op><mode>"
> (unspec:VF
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vf<misc_op>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
> @@ -6464,7 +6464,7 @@ (define_insn "@pred_class<mode>"
> (unspec:<VCONVERT>
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
> (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfclass.v\t%0,%3%p1"
> [(set_attr "type" "vfclass")
> (set_attr "mode" "<MODE>")])
> @@ -6497,7 +6497,7 @@ (define_insn "@pred_dual_widen_<optab><mode>"
> (float_extend:VWEXTF
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6522,7 +6522,7 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
> (vec_duplicate:<V_DOUBLE_TRUNC>
> (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6545,7 +6545,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>"
> (float_extend:VWEXTF
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.wv\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6569,7 +6569,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
> (vec_duplicate:<V_DOUBLE_TRUNC>
> (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<insn>.wf\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6602,7 +6602,7 @@ (define_insn "@pred_widen_mul_<optab><mode>"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<macc_msac>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6629,7 +6629,7 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<macc_msac>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6656,7 +6656,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6684,7 +6684,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
> (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
> (match_operand:VWEXTF 2 "register_operand" " 0"))
> (match_dup 2)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -6728,7 +6728,8 @@ (define_insn "*pred_cmp<mode>"
> [(match_operand:VF 4 "register_operand" " vr, vr")
> (match_operand:VF 5 "register_operand" " vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vv\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6747,7 +6748,7 @@ (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
> [(match_operand:VF 3 "register_operand" " vr")
> (match_operand:VF 4 "register_operand" " vr")])
> (match_dup 1)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B2.vv\t%0,%3,%4,v0.t"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")
> @@ -6771,7 +6772,8 @@ (define_insn "*pred_cmp<mode>_narrow"
> [(match_operand:VF 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
> (match_operand:VF 5 "register_operand" " vr, vr, 0, 0, vr, 0, 0, vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
> - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vv\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6809,7 +6811,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
> (vec_duplicate:VF
> (match_operand:<VEL> 4 "register_operand" " f"))])
> (match_dup 1)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B2.vf\t%0,%3,%4,v0.t"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")
> @@ -6834,7 +6836,8 @@ (define_insn "*pred_cmp<mode>_scalar"
> (vec_duplicate:VF
> (match_operand:<VEL> 5 "register_operand" " f, f"))])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6855,7 +6858,8 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
> (vec_duplicate:VF
> (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
> - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6893,7 +6897,7 @@ (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
> (match_operand:<VEL> 4 "register_operand" " f"))
> (match_operand:VF 3 "register_operand" " vr")])
> (match_dup 1)))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B2.vf\t%0,%3,%4,v0.t"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")
> @@ -6918,7 +6922,8 @@ (define_insn "*pred_eqne<mode>_scalar"
> (match_operand:<VEL> 5 "register_operand" " f, f"))
> (match_operand:VF 4 "register_operand" " vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6939,7 +6944,8 @@ (define_insn "*pred_eqne<mode>_scalar_narrow"
> (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
> (match_operand:VF 4 "register_operand" " vr, 0, 0, vr, vr")])
> (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
> - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vmf%B3.vf\t%0,%4,%5%p1"
> [(set_attr "type" "vfcmp")
> (set_attr "mode" "<MODE>")])
> @@ -6966,7 +6972,7 @@ (define_insn "@pred_merge<mode>_scalar"
> (match_operand:VF 2 "register_operand" " vr,vr")
> (match_operand:<VM> 4 "register_operand" " vm,vm"))
> (match_operand:VF 1 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfmerge.vfm\t%0,%2,%3,%4"
> [(set_attr "type" "vfmerge")
> (set_attr "mode" "<MODE>")])
> @@ -6994,7 +7000,7 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
> (unspec:<VCONVERT>
> [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS)
> (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfcvt.x<v_su>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfcvtftoi")
> (set_attr "mode" "<MODE>")])
> @@ -7013,7 +7019,7 @@ (define_insn "@pred_<fix_cvt><mode>"
> (any_fix:<VCONVERT>
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfcvtftoi")
> (set_attr "mode" "<MODE>")])
> @@ -7034,7 +7040,7 @@ (define_insn "@pred_<float_cvt><mode>"
> (any_float:VF
> (match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfcvt.f.x<u>.v\t%0,%3%p1"
> [(set_attr "type" "vfcvtitof")
> (set_attr "mode" "<MODE>")])
> @@ -7062,7 +7068,7 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
> (unspec:VWCONVERTI
> [(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")] VFCVTS)
> (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfwcvt.x<v_su>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7081,7 +7087,7 @@ (define_insn "@pred_widen_<fix_cvt><mode>"
> (any_fix:VWCONVERTI
> (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
> (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7100,7 +7106,7 @@ (define_insn "@pred_widen_<float_cvt><mode>"
> (any_float:VF
> (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwcvt.f.x<u>.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtitof")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7119,7 +7125,7 @@ (define_insn "@pred_extend<mode>"
> (float_extend:VWEXTF
> (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwcvt.f.f.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtftof")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -7147,7 +7153,7 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
> (unspec:<VNCONVERT>
> [(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS)
> (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfncvt.x<v_su>.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7166,7 +7172,7 @@ (define_insn "@pred_narrow_<fix_cvt><mode>"
> (any_fix:<VNCONVERT>
> (match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
> (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftoi")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7187,7 +7193,7 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
> (any_float:<VNCONVERT>
> (match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
> (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> "vfncvt.f.x<u>.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtitof")
> (set_attr "mode" "<VNCONVERT>")])
> @@ -7208,7 +7214,7 @@ (define_insn "@pred_trunc<mode>"
> (float_truncate:<V_DOUBLE_TRUNC>
> (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
> (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfncvt.f.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftof")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -7228,7 +7234,7 @@ (define_insn "@pred_rod_trunc<mode>"
> [(float_truncate:<V_DOUBLE_TRUNC>
> (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
> (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> "vfncvt.rod.f.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftof")
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> @@ -7389,7 +7395,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1>"
> (parallel [(const_int 0)])))
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> + "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<reduc>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfredu")
> (set_attr "mode" "<MODE>")])
> @@ -7413,7 +7420,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve64>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<reduc>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfredu")
> (set_attr "mode" "<MODE>")])
> @@ -7437,7 +7445,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 32
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<reduc>.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfredu")
> (set_attr "mode" "<MODE>")])
> @@ -7462,7 +7471,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1>"
> (parallel [(const_int 0)])))
> (match_operand:VF 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> + "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7487,7 +7497,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve64>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
> (match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7512,7 +7523,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve32>"
> (parallel [(const_int 0)])))
> (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
> (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 32
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7533,7 +7545,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1>"
> (match_operand:VWF 3 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1> 4 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> + "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfwred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7554,7 +7567,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>"
> (match_operand:VWF_ZVE64 3 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1_ZVE64> 4 "register_operand" " vr, vr")
> (match_operand:<VWLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
> - "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> + "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfwred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfwred<order>")
> (set_attr "mode" "<MODE>")])
> @@ -7657,7 +7671,7 @@ (define_insn "*pred_extract_first<mode>"
> (match_operand:VF 1 "register_operand" "vr")
> (parallel [(const_int 0)]))
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfmv.f.s\t%0,%1"
> [(set_attr "type" "vfmovvf")
> (set_attr "mode" "<MODE>")])
> @@ -7778,7 +7792,7 @@ (define_insn "@pred_slide<ud><mode>"
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:<VEL> 4 "register_operand" " f, f, f, f")] VFSLIDES1))]
> - "TARGET_VECTOR"
> + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> "vfslide<ud>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfslide<ud>")
> (set_attr "mode" "<MODE>")])
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> index 0923b6bc4d2..f1a29b639e0 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> @@ -3,6 +3,8 @@
> #include "riscv_vector.h"
> +typedef _Float16 float16_t;
> +
> vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
> return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
> }
> @@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
> return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
> }
> -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
> +vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
> + return __riscv_vle16_v_f16mf4(base, vl);
> +}
> +
> +vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
> + return __riscv_vle16_v_f16m8(base, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
> /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> -
> +/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-08 13:13 ` Li, Pan2
@ 2023-06-08 13:24 ` Kito Cheng
0 siblings, 0 replies; 39+ messages in thread
From: Kito Cheng @ 2023-06-08 13:24 UTC (permalink / raw)
To: Li, Pan2
Cc: juzhe.zhong, gcc-patches, Robin Dapp, jeffreyalaw, Wang, Yanzhang
I like JuZhe's proposal too since it's a less invasive way :)
On Thu, Jun 8, 2023 at 9:18 PM Li, Pan2 via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Thanks Juzhe for the idea. It looks work well as we expected, with the following try.
>
>
> 1. Allow all FP=16 types for vfadd, then _zvfh and _zvfhmin will be OK.
> 2. Add restriction define_attr as juzhe mentioned, then _zvfh works well, and _zvfhmin will meet error like unsatisfied insn.
>
> I think only we need to do is the define_attr, and there will be no changes to vector.md. If no more concern, will have a try for this approach.
>
> Pan
>
> From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
> Sent: Thursday, June 8, 2023 4:32 PM
> To: kito.cheng <kito.cheng@gmail.com>
> Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>; Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: Re: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
>
> I have an idea base on what Kito said.
> We enable vfadd FP16 for TARGET_ZVFH. But we don't need to add TARGET_VECTOR && <TARGET_FP_FULL_OPERATION_CHECKING>
> for each instruction.
>
> We can reference riscv.md:
> (define_attr "ext_enabled" "no,yes"
> (cond [(eq_attr "ext" "base")
> (const_string "yes")
>
> (and (eq_attr "ext" "f")
> (match_test "TARGET_HARD_FLOAT"))
> (const_string "yes")
>
> (and (eq_attr "ext" "d")
> (match_test "TARGET_DOUBLE_FLOAT"))
> (const_string "yes")
>
> (and (eq_attr "ext" "vector")
> (match_test "TARGET_VECTOR"))
> (const_string "yes")
> ]
> (const_string "no")))
>
> Define a new attribute as follows:
> (define_attr "fp16_vector_enabled" "no,yes"
> (cond [
> (and (eq_attr "type" "vfalu")
> (and eq_attr "mode" "VNx1HF")
> (match_test "!TARGET_ZVFH")))
> (const_string "no")
> ]
> (const_string "yes")))
>
>
> I think you can do experiment with this to see whether it can disable MD pattern.
>
> ________________________________
> juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
>
> From: Kito Cheng<mailto:kito.cheng@gmail.com>
> Date: 2023-06-08 15:58
> To: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
> CC: pan2.li<mailto:pan2.li@intel.com>; gcc-patches<mailto:gcc-patches@gcc.gnu.org>; Robin Dapp<mailto:rdapp.gcc@gmail.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
> Subject: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
> I am thinking, is it possible to use mode attr to remove the overhead
> of checking the mode for other FP modes other than FP16?
>
> e.g.
> (define_mode_attr TARGET_FP_FULL_OPERATION_CHECKING [
> (VNx1HF "TARGET_ZVFH")
> ...
> (VNx1SF "1")
> ...
> ])
>
>
> "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> ->
> "TARGET_VECTOR && <TARGET_FP_FULL_OPERATION_CHECKING>"
>
>
> On Thu, Jun 8, 2023 at 2:35 PM juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
> <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>> wrote:
> >
> > LGTM. Let's wait for Jeff and Robin. After this patch, we can start FP16 autovec.
> >
> >
> >
> > juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
> >
> > From: pan2.li
> > Date: 2023-06-08 14:29
> > To: gcc-patches
> > CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
> > Subject: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
> > From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
> >
> > This patch would like to refactor the requirement of both the ZVFH
> > and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
> > iterators of RVV. And then the ZVFH will leverage one function as
> > the gate for FP16 supported or not.
> >
> > Please note the ZVFH will cover the ZVFHMIN instructions. This patch
> > add one test for this.
> >
> > Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
> > Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv-protos.h (float_mode_supported_p):
> > New function to float point is supported by extension.
> > * config/riscv/riscv-v.cc (float_mode_supported_p):
> > Ditto.
> > * config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
> > * config/riscv/vector.md: Add condition to FP define insn.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
> > for ZVFHMIN.
> > ---
> > gcc/config/riscv/riscv-protos.h | 1 +
> > gcc/config/riscv/riscv-v.cc | 12 ++
> > gcc/config/riscv/vector-iterators.md | 23 +--
> > gcc/config/riscv/vector.md | 144 ++++++++++--------
> > .../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +-
> > 5 files changed, 118 insertions(+), 77 deletions(-)
> >
> > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> > index ebbaac255f9..1f606f59ce1 100644
> > --- a/gcc/config/riscv/riscv-protos.h
> > +++ b/gcc/config/riscv/riscv-protos.h
> > @@ -177,6 +177,7 @@ rtx expand_builtin (unsigned int, tree, rtx);
> > bool check_builtin_call (location_t, vec<location_t>, unsigned int,
> > tree, unsigned int, tree *);
> > bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
> > +bool float_mode_supported_p (machine_mode mode);
> > bool legitimize_move (rtx, rtx);
> > void emit_vlmax_vsetvl (machine_mode, rtx);
> > void emit_hard_vlmax_vsetvl (machine_mode, rtx);
> > diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> > index 49752cd8899..fe4eb058ec0 100644
> > --- a/gcc/config/riscv/riscv-v.cc
> > +++ b/gcc/config/riscv/riscv-v.cc
> > @@ -418,6 +418,18 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
> > && IN_RANGE (INTVAL (elt), minval, maxval));
> > }
> > +/* Return true if the inner of mode is HFmode when ZVFH enabled, or other
> > + float point machine mode. */
> > +bool
> > +float_mode_supported_p (machine_mode mode)
> > +{
> > + machine_mode inner_mode = GET_MODE_INNER (mode);
> > +
> > + gcc_assert (FLOAT_MODE_P (inner_mode));
> > +
> > + return inner_mode == HFmode ? TARGET_ZVFH : true;
> > +}
> > +
> > /* Return true if VEC is a constant in which every element is in the range
> > [MINVAL, MAXVAL]. The elements do not need to have the same value.
> > diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
> > index f4946d84449..234b712bc9d 100644
> > --- a/gcc/config/riscv/vector-iterators.md
> > +++ b/gcc/config/riscv/vector-iterators.md
> > @@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
> > (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
> > (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
> > - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> > - (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
> > - (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
> > + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
> > + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
> > (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
> > (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
> > (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
> > @@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
> > (define_mode_iterator V_FRACT [
> > (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
> > (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
> > - (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
> > +
> > + (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> > + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
> > + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
> > +
> > (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
> > (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
> > (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> > @@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
> > ])
> > (define_mode_iterator VWEXTF [
> > - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> > - (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
> > - (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
> > - (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
> > - (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
> > - (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> > + (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> > + (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> > + (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> > + (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> > + (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
> > + (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> > (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
> > (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
> > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> > index 1d1847bd85a..2fe0233f102 100644
> > --- a/gcc/config/riscv/vector.md
> > +++ b/gcc/config/riscv/vector.md
> > @@ -1364,7 +1364,7 @@ (define_insn "*pred_broadcast<mode>"
> > (vec_duplicate:VF
> > (match_operand:<VEL> 3 "direct_broadcast_operand" " f, f,Wdm,Wdm,Wdm,Wdm, f, f"))
> > (match_operand:VF 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "@<mailto:%22@%0d%3e %20vfmv.v.f\t%250,%253%0d%3e %20vfmv.v.f\t%250,%253%0d%3e%20@@%20-5685,7%20+5685,7%20@@%20(define_insn%20%22@pred_%3coptab%3e%3cmode>
> > vfmv.v.f\t%0,%3<mailto:%22@%0d%3e %20vfmv.v.f\t%250,%253%0d%3e %20vfmv.v.f\t%250,%253%0d%3e%20@@%20-5685,7%20+5685,7%20@@%20(define_insn%20%22@pred_%3coptab%3e%3cmode>
> > vfmv.v.f\t%0,%3<mailto:%22@%0d%3e %20vfmv.v.f\t%250,%253%0d%3e %20vfmv.v.f\t%250,%253%0d%3e%20@@%20-5685,7%20+5685,7%20@@%20(define_insn%20%22@pred_%3coptab%3e%3cmode>
> > @@ -5685,7 +5685,7 @@ (define_insn "@pred_<optab><mode<mailto:%22@%0d%3e %20vfmv.v.f\t%250,%253%0d%3e %20vfmv.v.f\t%250,%253%0d%3e%20@@%20-5685,7%20+5685,7%20@@%20(define_insn%20%22@pred_%3coptab%3e%3cmode>>"
> > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> > (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vf<insn>.vv\t%0,%3,%4%p1"
> > [(set_attr "type" "<float_insn_type>")
> > (set_attr "mode" "<MODE>")])
> > @@ -5705,7 +5705,7 @@ (define_insn "@pred_<optab><mode>"
> > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> > (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vf<insn>.vv\t%0,%3,%4%p1"
> > [(set_attr "type" "<float_insn_type>")
> > (set_attr "mode" "<MODE>")])
> > @@ -5728,7 +5728,7 @@ (define_insn "@pred_<optab><mode>_scalar"
> > (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
> > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vf<insn>.vf\t%0,%3,%4%p1"
> > [(set_attr "type" "<float_insn_type>")
> > (set_attr "mode" "<MODE>")])
> > @@ -5749,7 +5749,7 @@ (define_insn "@pred_<optab><mode>_scalar"
> > (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
> > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vf<insn>.vf\t%0,%3,%4%p1"
> > [(set_attr "type" "<float_insn_type>")
> > (set_attr "mode" "<MODE>")])
> > @@ -5772,7 +5772,7 @@ (define_insn "@pred_<optab><mode>_scalar"
> > (vec_duplicate:VF
> > (match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
> > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vf<insn>.vf\t%0,%3,%4%p1"
> > [(set_attr "type" "<float_insn_type>")
> > (set_attr "mode" "<MODE>")])
> > @@ -5795,7 +5795,7 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
> > (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
> > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfr<insn>.vf\t%0,%3,%4%p1"
> > [(set_attr "type" "<float_insn_type>")
> > (set_attr "mode" "<MODE>")])
> > @@ -5815,7 +5815,7 @@ (define_insn "@pred_<copysign><mode>"
> > [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> > (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS)
> > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfsgnj<nx>.vv\t%0,%3,%4%p1"
> > [(set_attr "type" "vfsgnj")
> > (set_attr "mode" "<MODE>")])
> > @@ -5836,7 +5836,7 @@ (define_insn "@pred_<copysign><mode>_scalar"
> > (vec_duplicate:VF
> > (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS)
> > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfsgnj<nx>.vf\t%0,%3,%4%p1"
> > [(set_attr "type" "vfsgnj")
> > (set_attr "mode" "<MODE>")])
> > @@ -5894,7 +5894,7 @@ (define_insn "*pred_<madd_msub><mode>"
> > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> > (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> > (match_dup 2)))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "@
> > vf<madd_msub>.vv\t%0,%3,%4%p1
> > vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
> > @@ -5927,7 +5927,7 @@ (define_insn "*pred_<macc_msac><mode>"
> > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> > (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> > (match_dup 4)))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "@
> > vf<macc_msac>.vv\t%0,%2,%3%p1
> > vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
> > @@ -5960,7 +5960,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
> > (match_operand:VF 3 "register_operand" " vr, vr"))
> > (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> > (match_operand:VF 5 "register_operand" " 0, vr")))]
> > - "TARGET_VECTOR
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> > && !rtx_equal_p (operands[2], operands[5])
> > && !rtx_equal_p (operands[3], operands[5])
> > && !rtx_equal_p (operands[4], operands[5])"
> > @@ -6021,7 +6021,7 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
> > (match_operand:VF 3 "register_operand" " 0, vr, 0, vr"))
> > (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> > (match_dup 3)))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "@
> > vf<madd_msub>.vf\t%0,%2,%4%p1
> > vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
> > @@ -6055,7 +6055,7 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
> > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> > (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> > (match_dup 4)))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "@
> > vf<macc_msac>.vf\t%0,%2,%3%p1
> > vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
> > @@ -6089,7 +6089,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
> > (match_operand:VF 3 "register_operand" " vr, vr"))
> > (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> > (match_operand:VF 5 "register_operand" " 0, vr")))]
> > - "TARGET_VECTOR
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> > && !rtx_equal_p (operands[3], operands[5])
> > && !rtx_equal_p (operands[4], operands[5])"
> > "@
> > @@ -6154,7 +6154,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
> > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
> > (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> > (match_dup 2)))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "@
> > vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
> > vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
> > @@ -6188,7 +6188,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
> > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
> > (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> > (match_dup 4)))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "@
> > vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
> > vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
> > @@ -6222,7 +6222,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
> > (match_operand:VF 3 "register_operand" " vr, vr")))
> > (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> > (match_operand:VF 5 "register_operand" " 0, vr")))]
> > - "TARGET_VECTOR
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> > && !rtx_equal_p (operands[2], operands[5])
> > && !rtx_equal_p (operands[3], operands[5])
> > && !rtx_equal_p (operands[4], operands[5])"
> > @@ -6285,7 +6285,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
> > (match_operand:VF 3 "register_operand" " 0, vr, 0, vr")))
> > (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"))
> > (match_dup 3)))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "@
> > vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
> > vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
> > @@ -6320,7 +6320,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
> > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")))
> > (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"))
> > (match_dup 4)))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "@
> > vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
> > vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
> > @@ -6355,7 +6355,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
> > (match_operand:VF 3 "register_operand" " vr, vr")))
> > (match_operand:VF 4 "vector_arith_operand" " vr, vr"))
> > (match_operand:VF 5 "register_operand" " 0, vr")))]
> > - "TARGET_VECTOR
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)
> > && !rtx_equal_p (operands[3], operands[5])
> > && !rtx_equal_p (operands[4], operands[5])"
> > "@
> > @@ -6399,7 +6399,7 @@ (define_insn "@pred_<optab><mode>"
> > (any_float_unop:VF
> > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vf<insn>.v\t%0,%3%p1"
> > [(set_attr "type" "<float_insn_type>")
> > (set_attr "mode" "<MODE>")
> > @@ -6422,7 +6422,7 @@ (define_insn "@pred_<optab><mode>"
> > (any_float_unop_nofrm:VF
> > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vf<insn>.v\t%0,%3%p1"
> > [(set_attr "type" "<float_insn_type>")
> > (set_attr "mode" "<MODE>")
> > @@ -6445,7 +6445,7 @@ (define_insn "@pred_<misc_op><mode>"
> > (unspec:VF
> > [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
> > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vf<misc_op>.v\t%0,%3%p1"
> > [(set_attr "type" "<float_insn_type>")
> > (set_attr "mode" "<MODE>")])
> > @@ -6464,7 +6464,7 @@ (define_insn "@pred_class<mode>"
> > (unspec:<VCONVERT>
> > [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
> > (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfclass.v\t%0,%3%p1"
> > [(set_attr "type" "vfclass")
> > (set_attr "mode" "<MODE>")])
> > @@ -6497,7 +6497,7 @@ (define_insn "@pred_dual_widen_<optab><mode>"
> > (float_extend:VWEXTF
> > (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
> > (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> > "vfw<insn>.vv\t%0,%3,%4%p1"
> > [(set_attr "type" "vf<widen_binop_insn_type>")
> > (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> > @@ -6522,7 +6522,7 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
> > (vec_duplicate:<V_DOUBLE_TRUNC>
> > (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
> > (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> > "vfw<insn>.vf\t%0,%3,%4%p1"
> > [(set_attr "type" "vf<widen_binop_insn_type>")
> > (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> > @@ -6545,7 +6545,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>"
> > (float_extend:VWEXTF
> > (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
> > (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> > "vfw<insn>.wv\t%0,%3,%4%p1"
> > [(set_attr "type" "vf<widen_binop_insn_type>")
> > (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> > @@ -6569,7 +6569,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
> > (vec_duplicate:<V_DOUBLE_TRUNC>
> > (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
> > (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> > "vfw<insn>.wf\t%0,%3,%4%p1"
> > [(set_attr "type" "vf<widen_binop_insn_type>")
> > (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> > @@ -6602,7 +6602,7 @@ (define_insn "@pred_widen_mul_<optab><mode>"
> > (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
> > (match_operand:VWEXTF 2 "register_operand" " 0"))
> > (match_dup 2)))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> > "vfw<macc_msac>.vv\t%0,%3,%4%p1"
> > [(set_attr "type" "vfwmuladd")
> > (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> > @@ -6629,7 +6629,7 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
> > (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
> > (match_operand:VWEXTF 2 "register_operand" " 0"))
> > (match_dup 2)))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> > "vfw<macc_msac>.vf\t%0,%3,%4%p1"
> > [(set_attr "type" "vfwmuladd")
> > (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> > @@ -6656,7 +6656,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
> > (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
> > (match_operand:VWEXTF 2 "register_operand" " 0"))
> > (match_dup 2)))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> > "vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
> > [(set_attr "type" "vfwmuladd")
> > (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> > @@ -6684,7 +6684,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
> > (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
> > (match_operand:VWEXTF 2 "register_operand" " 0"))
> > (match_dup 2)))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> > "vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
> > [(set_attr "type" "vfwmuladd")
> > (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> > @@ -6728,7 +6728,8 @@ (define_insn "*pred_cmp<mode>"
> > [(match_operand:VF 4 "register_operand" " vr, vr")
> > (match_operand:VF 5 "register_operand" " vr, vr")])
> > (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
> > - "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> > + "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> > + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vmf%B3.vv\t%0,%4,%5%p1"
> > [(set_attr "type" "vfcmp")
> > (set_attr "mode" "<MODE>")])
> > @@ -6747,7 +6748,7 @@ (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
> > [(match_operand:VF 3 "register_operand" " vr")
> > (match_operand:VF 4 "register_operand" " vr")])
> > (match_dup 1)))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vmf%B2.vv\t%0,%3,%4,v0.t"
> > [(set_attr "type" "vfcmp")
> > (set_attr "mode" "<MODE>")
> > @@ -6771,7 +6772,8 @@ (define_insn "*pred_cmp<mode>_narrow"
> > [(match_operand:VF 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
> > (match_operand:VF 5 "register_operand" " vr, vr, 0, 0, vr, 0, 0, vr, vr")])
> > (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
> > - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> > + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> > + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vmf%B3.vv\t%0,%4,%5%p1"
> > [(set_attr "type" "vfcmp")
> > (set_attr "mode" "<MODE>")])
> > @@ -6809,7 +6811,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
> > (vec_duplicate:VF
> > (match_operand:<VEL> 4 "register_operand" " f"))])
> > (match_dup 1)))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vmf%B2.vf\t%0,%3,%4,v0.t"
> > [(set_attr "type" "vfcmp")
> > (set_attr "mode" "<MODE>")
> > @@ -6834,7 +6836,8 @@ (define_insn "*pred_cmp<mode>_scalar"
> > (vec_duplicate:VF
> > (match_operand:<VEL> 5 "register_operand" " f, f"))])
> > (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
> > - "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> > + "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> > + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vmf%B3.vf\t%0,%4,%5%p1"
> > [(set_attr "type" "vfcmp")
> > (set_attr "mode" "<MODE>")])
> > @@ -6855,7 +6858,8 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
> > (vec_duplicate:VF
> > (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))])
> > (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
> > - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> > + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> > + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vmf%B3.vf\t%0,%4,%5%p1"
> > [(set_attr "type" "vfcmp")
> > (set_attr "mode" "<MODE>")])
> > @@ -6893,7 +6897,7 @@ (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
> > (match_operand:<VEL> 4 "register_operand" " f"))
> > (match_operand:VF 3 "register_operand" " vr")])
> > (match_dup 1)))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vmf%B2.vf\t%0,%3,%4,v0.t"
> > [(set_attr "type" "vfcmp")
> > (set_attr "mode" "<MODE>")
> > @@ -6918,7 +6922,8 @@ (define_insn "*pred_eqne<mode>_scalar"
> > (match_operand:<VEL> 5 "register_operand" " f, f"))
> > (match_operand:VF 4 "register_operand" " vr, vr")])
> > (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
> > - "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> > + "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> > + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vmf%B3.vf\t%0,%4,%5%p1"
> > [(set_attr "type" "vfcmp")
> > (set_attr "mode" "<MODE>")])
> > @@ -6939,7 +6944,8 @@ (define_insn "*pred_eqne<mode>_scalar_narrow"
> > (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
> > (match_operand:VF 4 "register_operand" " vr, 0, 0, vr, vr")])
> > (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
> > - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
> > + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)
> > + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vmf%B3.vf\t%0,%4,%5%p1"
> > [(set_attr "type" "vfcmp")
> > (set_attr "mode" "<MODE>")])
> > @@ -6966,7 +6972,7 @@ (define_insn "@pred_merge<mode>_scalar"
> > (match_operand:VF 2 "register_operand" " vr,vr")
> > (match_operand:<VM> 4 "register_operand" " vm,vm"))
> > (match_operand:VF 1 "vector_merge_operand" " vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfmerge.vfm\t%0,%2,%3,%4"
> > [(set_attr "type" "vfmerge")
> > (set_attr "mode" "<MODE>")])
> > @@ -6994,7 +7000,7 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
> > (unspec:<VCONVERT>
> > [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS)
> > (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfcvt.x<v_su>.f.v\t%0,%3%p1"
> > [(set_attr "type" "vfcvtftoi")
> > (set_attr "mode" "<MODE>")])
> > @@ -7013,7 +7019,7 @@ (define_insn "@pred_<fix_cvt><mode>"
> > (any_fix:<VCONVERT>
> > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> > (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
> > [(set_attr "type" "vfcvtftoi")
> > (set_attr "mode" "<MODE>")])
> > @@ -7034,7 +7040,7 @@ (define_insn "@pred_<float_cvt><mode>"
> > (any_float:VF
> > (match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
> > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfcvt.f.x<u>.v\t%0,%3%p1"
> > [(set_attr "type" "vfcvtitof")
> > (set_attr "mode" "<MODE>")])
> > @@ -7062,7 +7068,7 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
> > (unspec:VWCONVERTI
> > [(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")] VFCVTS)
> > (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> > "vfwcvt.x<v_su>.f.v\t%0,%3%p1"
> > [(set_attr "type" "vfwcvtftoi")
> > (set_attr "mode" "<VNCONVERT>")])
> > @@ -7081,7 +7087,7 @@ (define_insn "@pred_widen_<fix_cvt><mode>"
> > (any_fix:VWCONVERTI
> > (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
> > (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> > "vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
> > [(set_attr "type" "vfwcvtftoi")
> > (set_attr "mode" "<VNCONVERT>")])
> > @@ -7100,7 +7106,7 @@ (define_insn "@pred_widen_<float_cvt><mode>"
> > (any_float:VF
> > (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
> > (match_operand:VF 2 "vector_merge_operand" " vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfwcvt.f.x<u>.v\t%0,%3%p1"
> > [(set_attr "type" "vfwcvtitof")
> > (set_attr "mode" "<VNCONVERT>")])
> > @@ -7119,7 +7125,7 @@ (define_insn "@pred_extend<mode>"
> > (float_extend:VWEXTF
> > (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
> > (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfwcvt.f.f.v\t%0,%3%p1"
> > [(set_attr "type" "vfwcvtftof")
> > (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> > @@ -7147,7 +7153,7 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
> > (unspec:<VNCONVERT>
> > [(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS)
> > (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfncvt.x<v_su>.f.w\t%0,%3%p1"
> > [(set_attr "type" "vfncvtftoi")
> > (set_attr "mode" "<VNCONVERT>")])
> > @@ -7166,7 +7172,7 @@ (define_insn "@pred_narrow_<fix_cvt><mode>"
> > (any_fix:<VNCONVERT>
> > (match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
> > (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> > "vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
> > [(set_attr "type" "vfncvtftoi")
> > (set_attr "mode" "<VNCONVERT>")])
> > @@ -7187,7 +7193,7 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
> > (any_float:<VNCONVERT>
> > (match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
> > (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<VNCONVERT>mode)"
> > "vfncvt.f.x<u>.w\t%0,%3%p1"
> > [(set_attr "type" "vfncvtitof")
> > (set_attr "mode" "<VNCONVERT>")])
> > @@ -7208,7 +7214,7 @@ (define_insn "@pred_trunc<mode>"
> > (float_truncate:<V_DOUBLE_TRUNC>
> > (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
> > (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfncvt.f.f.w\t%0,%3%p1"
> > [(set_attr "type" "vfncvtftof")
> > (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> > @@ -7228,7 +7234,7 @@ (define_insn "@pred_rod_trunc<mode>"
> > [(float_truncate:<V_DOUBLE_TRUNC>
> > (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
> > (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<V_DOUBLE_TRUNC>mode)"
> > "vfncvt.rod.f.f.w\t%0,%3%p1"
> > [(set_attr "type" "vfncvtftof")
> > (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> > @@ -7389,7 +7395,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1>"
> > (parallel [(const_int 0)])))
> > (match_operand:VF 3 "register_operand" " vr, vr"))
> > (match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
> > - "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> > + "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> > + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfred<reduc>.vs\t%0,%3,%4%p1"
> > [(set_attr "type" "vfredu")
> > (set_attr "mode" "<MODE>")])
> > @@ -7413,7 +7420,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve64>"
> > (parallel [(const_int 0)])))
> > (match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
> > (match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
> > - "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> > + "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> > + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfred<reduc>.vs\t%0,%3,%4%p1"
> > [(set_attr "type" "vfredu")
> > (set_attr "mode" "<MODE>")])
> > @@ -7437,7 +7445,8 @@ (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
> > (parallel [(const_int 0)])))
> > (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
> > (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))]
> > - "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
> > + "TARGET_VECTOR && TARGET_MIN_VLEN == 32
> > + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfred<reduc>.vs\t%0,%3,%4%p1"
> > [(set_attr "type" "vfredu")
> > (set_attr "mode" "<MODE>")])
> > @@ -7462,7 +7471,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1>"
> > (parallel [(const_int 0)])))
> > (match_operand:VF 3 "register_operand" " vr, vr"))
> > (match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
> > - "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> > + "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> > + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfred<order>sum.vs\t%0,%3,%4%p1"
> > [(set_attr "type" "vfred<order>")
> > (set_attr "mode" "<MODE>")])
> > @@ -7487,7 +7497,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve64>"
> > (parallel [(const_int 0)])))
> > (match_operand:VF_ZVE64 3 "register_operand" " vr, vr"))
> > (match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
> > - "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> > + "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> > + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfred<order>sum.vs\t%0,%3,%4%p1"
> > [(set_attr "type" "vfred<order>")
> > (set_attr "mode" "<MODE>")])
> > @@ -7512,7 +7523,8 @@ (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve32>"
> > (parallel [(const_int 0)])))
> > (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
> > (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC)] ORDER))]
> > - "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
> > + "TARGET_VECTOR && TARGET_MIN_VLEN == 32
> > + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfred<order>sum.vs\t%0,%3,%4%p1"
> > [(set_attr "type" "vfred<order>")
> > (set_attr "mode" "<MODE>")])
> > @@ -7533,7 +7545,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1>"
> > (match_operand:VWF 3 "register_operand" " vr, vr")
> > (match_operand:<VWLMUL1> 4 "register_operand" " vr, vr")
> > (match_operand:<VWLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
> > - "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
> > + "TARGET_VECTOR && TARGET_MIN_VLEN >= 128
> > + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfwred<order>sum.vs\t%0,%3,%4%p1"
> > [(set_attr "type" "vfwred<order>")
> > (set_attr "mode" "<MODE>")])
> > @@ -7554,7 +7567,8 @@ (define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>"
> > (match_operand:VWF_ZVE64 3 "register_operand" " vr, vr")
> > (match_operand:<VWLMUL1_ZVE64> 4 "register_operand" " vr, vr")
> > (match_operand:<VWLMUL1_ZVE64> 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
> > - "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
> > + "TARGET_VECTOR && TARGET_MIN_VLEN == 64
> > + && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfwred<order>sum.vs\t%0,%3,%4%p1"
> > [(set_attr "type" "vfwred<order>")
> > (set_attr "mode" "<MODE>")])
> > @@ -7657,7 +7671,7 @@ (define_insn "*pred_extract_first<mode>"
> > (match_operand:VF 1 "register_operand" "vr")
> > (parallel [(const_int 0)]))
> > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfmv.f.s\t%0,%1"
> > [(set_attr "type" "vfmovvf")
> > (set_attr "mode" "<MODE>")])
> > @@ -7778,7 +7792,7 @@ (define_insn "@pred_slide<ud><mode>"
> > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")
> > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> > (match_operand:<VEL> 4 "register_operand" " f, f, f, f")] VFSLIDES1))]
> > - "TARGET_VECTOR"
> > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (<MODE>mode)"
> > "vfslide<ud>.vf\t%0,%3,%4%p1"
> > [(set_attr "type" "vfslide<ud>")
> > (set_attr "mode" "<MODE>")])
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> > index 0923b6bc4d2..f1a29b639e0 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> > @@ -3,6 +3,8 @@
> > #include "riscv_vector.h"
> > +typedef _Float16 float16_t;
> > +
> > vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
> > return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
> > }
> > @@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
> > return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
> > }
> > -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
> > +vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
> > + return __riscv_vle16_v_f16mf4(base, vl);
> > +}
> > +
> > +vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
> > + return __riscv_vle16_v_f16m8(base, vl);
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
> > /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
> > /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
> > /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
> > /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
> > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
> > /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> > /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> > -
> > +/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
> > --
> > 2.34.1
> >
> >
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-06 12:36 [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern pan2.li
` (7 preceding siblings ...)
2023-06-08 6:29 ` [PATCH v8] " pan2.li
@ 2023-06-09 5:59 ` pan2.li
2023-06-09 6:13 ` juzhe.zhong
2023-06-09 7:07 ` [PATCH v10] " pan2.li
9 siblings, 1 reply; 39+ messages in thread
From: pan2.li @ 2023-06-09 5:59 UTC (permalink / raw)
To: gcc-patches
Cc: juzhe.zhong, rdapp.gcc, jeffreyalaw, pan2.li, yanzhang.wang, kito.cheng
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
iterators of RVV. And then the ZVFH will leverage one define attr
the gate for FP16 supported or not.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Co-Authored by: Kito Cheng <kito.cheng@sifive.com>
gcc/ChangeLog:
* config/riscv/riscv.md (ext): Move to another place.
(ext_enabled): Ditto.
(fp_vector_disabled): New define attr.
(enabled): Add fp_vector_disabled to the cond.
* config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
for ZVFHMIN.
---
gcc/config/riscv/riscv.md | 84 ++++++++++++-------
gcc/config/riscv/vector-iterators.md | 23 ++---
.../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +++-
3 files changed, 81 insertions(+), 41 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 38b8fba2a53..d1c7c3a3008 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -216,35 +216,6 @@ (define_attr "dword_mode" "no,yes"
(const_string "yes")]
(const_string "no")))
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
- (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
-
-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
- (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))
-
;; Classification of each insn.
;; branch conditional branch
;; jump unconditional jump
@@ -434,6 +405,61 @@ (define_attr "type"
(eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")]
(const_string "unknown")))
+;; ISA attributes.
+(define_attr "ext" "base,f,d,vector"
+ (const_string "base"))
+
+;; True if the extension is enabled.
+(define_attr "ext_enabled" "no,yes"
+ (cond [(eq_attr "ext" "base")
+ (const_string "yes")
+
+ (and (eq_attr "ext" "f")
+ (match_test "TARGET_HARD_FLOAT"))
+ (const_string "yes")
+
+ (and (eq_attr "ext" "d")
+ (match_test "TARGET_DOUBLE_FLOAT"))
+ (const_string "yes")
+
+ (and (eq_attr "ext" "vector")
+ (match_test "TARGET_VECTOR"))
+ (const_string "yes")
+ ]
+ (const_string "no")))
+
+;; True if the float point vector is disabled.
+(define_attr "fp_vector_disabled" "no,yes"
+ (cond [
+ (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
+ vfwalu,vfwmul,vfmuladd,vfwmuladd,
+ vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
+ vfclass,vfmerge,
+ vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
+ vfredo,vfredu,vfwredo,vfwredu,
+ vfslide1up,vfslide1down")
+ (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+
+ (and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
+ (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+ ]
+ (const_string "no")))
+
+;; Attribute to control enable or disable instructions.
+(define_attr "enabled" "no,yes"
+ (cond [
+ (eq_attr "ext_enabled" "no")
+ (const_string "no")
+
+ (eq_attr "fp_vector_disabled" "yes")
+ (const_string "no")
+ ]
+ (const_string "yes")))
+
;; Length of instruction in bytes.
(define_attr "length" ""
(cond [
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..234b712bc9d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 0923b6bc4d2..f1a29b639e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -3,6 +3,8 @@
#include "riscv_vector.h"
+typedef _Float16 float16_t;
+
vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
}
@@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
}
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16mf4(base, vl);
+}
+
+vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16m8(base, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
-
+/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-09 5:59 ` [PATCH v9] " pan2.li
@ 2023-06-09 6:13 ` juzhe.zhong
2023-06-09 6:23 ` Li, Pan2
0 siblings, 1 reply; 39+ messages in thread
From: juzhe.zhong @ 2023-06-09 6:13 UTC (permalink / raw)
To: pan2.li, gcc-patches
Cc: Robin Dapp, jeffreyalaw, pan2.li, yanzhang.wang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 10627 bytes --]
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
- (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
Why change this ?
-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
- (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))
I think it should only add fp16_vector_disable. However, it seems the whole thing is removed?
+;; True if the float point vector is disabled.
+(define_attr "fp_vector_disabled" "no,yes"
+ (cond [
+ (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
+ vfwalu,vfwmul,vfmuladd,vfwmuladd,
+ vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
+ vfclass,vfmerge,
+ vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
+ vfredo,vfredu,vfwredo,vfwredu,
+ vfslide1up,vfslide1down")
+ (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+
+ (and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
+ (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+ ]
+ (const_string "no")))
This should be in vector.md instead of riscv.md
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-06-09 13:59
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
iterators of RVV. And then the ZVFH will leverage one define attr
the gate for FP16 supported or not.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Co-Authored by: Kito Cheng <kito.cheng@sifive.com>
gcc/ChangeLog:
* config/riscv/riscv.md (ext): Move to another place.
(ext_enabled): Ditto.
(fp_vector_disabled): New define attr.
(enabled): Add fp_vector_disabled to the cond.
* config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
for ZVFHMIN.
---
gcc/config/riscv/riscv.md | 84 ++++++++++++-------
gcc/config/riscv/vector-iterators.md | 23 ++---
.../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +++-
3 files changed, 81 insertions(+), 41 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 38b8fba2a53..d1c7c3a3008 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -216,35 +216,6 @@ (define_attr "dword_mode" "no,yes"
(const_string "yes")]
(const_string "no")))
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
- (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
-
-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
- (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))
-
;; Classification of each insn.
;; branch conditional branch
;; jump unconditional jump
@@ -434,6 +405,61 @@ (define_attr "type"
(eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")]
(const_string "unknown")))
+;; ISA attributes.
+(define_attr "ext" "base,f,d,vector"
+ (const_string "base"))
+
+;; True if the extension is enabled.
+(define_attr "ext_enabled" "no,yes"
+ (cond [(eq_attr "ext" "base")
+ (const_string "yes")
+
+ (and (eq_attr "ext" "f")
+ (match_test "TARGET_HARD_FLOAT"))
+ (const_string "yes")
+
+ (and (eq_attr "ext" "d")
+ (match_test "TARGET_DOUBLE_FLOAT"))
+ (const_string "yes")
+
+ (and (eq_attr "ext" "vector")
+ (match_test "TARGET_VECTOR"))
+ (const_string "yes")
+ ]
+ (const_string "no")))
+
+;; True if the float point vector is disabled.
+(define_attr "fp_vector_disabled" "no,yes"
+ (cond [
+ (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
+ vfwalu,vfwmul,vfmuladd,vfwmuladd,
+ vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
+ vfclass,vfmerge,
+ vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
+ vfredo,vfredu,vfwredo,vfwredu,
+ vfslide1up,vfslide1down")
+ (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+
+ (and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
+ (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+ ]
+ (const_string "no")))
+
+;; Attribute to control enable or disable instructions.
+(define_attr "enabled" "no,yes"
+ (cond [
+ (eq_attr "ext_enabled" "no")
+ (const_string "no")
+
+ (eq_attr "fp_vector_disabled" "yes")
+ (const_string "no")
+ ]
+ (const_string "yes")))
+
;; Length of instruction in bytes.
(define_attr "length" ""
(cond [
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..234b712bc9d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 0923b6bc4d2..f1a29b639e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -3,6 +3,8 @@
#include "riscv_vector.h"
+typedef _Float16 float16_t;
+
vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
}
@@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
}
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16mf4(base, vl);
+}
+
+vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16m8(base, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
-
+/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-09 6:13 ` juzhe.zhong
@ 2023-06-09 6:23 ` Li, Pan2
2023-06-09 6:31 ` juzhe.zhong
0 siblings, 1 reply; 39+ messages in thread
From: Li, Pan2 @ 2023-06-09 6:23 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches
Cc: Robin Dapp, jeffreyalaw, Wang, Yanzhang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 12717 bytes --]
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
- (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
>> Why change this ?
As the fp will reference the type attr, we should move this part after the type attr definition.
-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
- (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))
>> I think it should only add fp16_vector_disable. However, it seems the whole thing is removed?
The same as above, move to the place after than type attr definition and only add fp_vector_disable here.
>> This should be in vector.md instead of riscv.md
It will trigger "unknown attribute `fp_vector_disabled' in definition of attribute `enabled'", because riscv.md include the vector.md at the end of file.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Friday, June 9, 2023 2:14 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
- (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
Why change this ?
-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
- (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))
I think it should only add fp16_vector_disable. However, it seems the whole thing is removed?
+;; True if the float point vector is disabled.
+(define_attr "fp_vector_disabled" "no,yes"
+ (cond [
+ (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
+ vfwalu,vfwmul,vfmuladd,vfwmuladd,
+ vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
+ vfclass,vfmerge,
+ vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
+ vfredo,vfredu,vfwredo,vfwredu,
+ vfslide1up,vfslide1down")
+ (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+
+ (and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
+ (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+ ]
+ (const_string "no")))
This should be in vector.md instead of riscv.md
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-06-09 13:59
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; rdapp.gcc<mailto:rdapp.gcc@gmail.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
iterators of RVV. And then the ZVFH will leverage one define attr
the gate for FP16 supported or not.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
Co-Authored by: Kito Cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>
gcc/ChangeLog:
* config/riscv/riscv.md (ext): Move to another place.
(ext_enabled): Ditto.
(fp_vector_disabled): New define attr.
(enabled): Add fp_vector_disabled to the cond.
* config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
for ZVFHMIN.
---
gcc/config/riscv/riscv.md | 84 ++++++++++++-------
gcc/config/riscv/vector-iterators.md | 23 ++---
.../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +++-
3 files changed, 81 insertions(+), 41 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 38b8fba2a53..d1c7c3a3008 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -216,35 +216,6 @@ (define_attr "dword_mode" "no,yes"
(const_string "yes")]
(const_string "no")))
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
- (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
-
-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
- (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))
-
;; Classification of each insn.
;; branch conditional branch
;; jump unconditional jump
@@ -434,6 +405,61 @@ (define_attr "type"
(eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")]
(const_string "unknown")))
+;; ISA attributes.
+(define_attr "ext" "base,f,d,vector"
+ (const_string "base"))
+
+;; True if the extension is enabled.
+(define_attr "ext_enabled" "no,yes"
+ (cond [(eq_attr "ext" "base")
+ (const_string "yes")
+
+ (and (eq_attr "ext" "f")
+ (match_test "TARGET_HARD_FLOAT"))
+ (const_string "yes")
+
+ (and (eq_attr "ext" "d")
+ (match_test "TARGET_DOUBLE_FLOAT"))
+ (const_string "yes")
+
+ (and (eq_attr "ext" "vector")
+ (match_test "TARGET_VECTOR"))
+ (const_string "yes")
+ ]
+ (const_string "no")))
+
+;; True if the float point vector is disabled.
+(define_attr "fp_vector_disabled" "no,yes"
+ (cond [
+ (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
+ vfwalu,vfwmul,vfmuladd,vfwmuladd,
+ vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
+ vfclass,vfmerge,
+ vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
+ vfredo,vfredu,vfwredo,vfwredu,
+ vfslide1up,vfslide1down")
+ (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+
+ (and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
+ (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+ ]
+ (const_string "no")))
+
+;; Attribute to control enable or disable instructions.
+(define_attr "enabled" "no,yes"
+ (cond [
+ (eq_attr "ext_enabled" "no")
+ (const_string "no")
+
+ (eq_attr "fp_vector_disabled" "yes")
+ (const_string "no")
+ ]
+ (const_string "yes")))
+
;; Length of instruction in bytes.
(define_attr "length" ""
(cond [
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..234b712bc9d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 0923b6bc4d2..f1a29b639e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -3,6 +3,8 @@
#include "riscv_vector.h"
+typedef _Float16 float16_t;
+
vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
}
@@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
}
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16mf4(base, vl);
+}
+
+vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16m8(base, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
-
+/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-09 6:23 ` Li, Pan2
@ 2023-06-09 6:31 ` juzhe.zhong
2023-06-09 6:41 ` Li, Pan2
0 siblings, 1 reply; 39+ messages in thread
From: juzhe.zhong @ 2023-06-09 6:31 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: Robin Dapp, jeffreyalaw, yanzhang.wang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 13216 bytes --]
OK. But why change the place of these
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
- (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
I think it should not be changed.
juzhe.zhong@rivai.ai
From: Li, Pan2
Date: 2023-06-09 14:23
To: juzhe.zhong@rivai.ai; gcc-patches
CC: Robin Dapp; jeffreyalaw; Wang, Yanzhang; kito.cheng
Subject: RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
- (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
>> Why change this ?
As the fp will reference the type attr, we should move this part after the type attr definition.
-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
- (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))
>> I think it should only add fp16_vector_disable. However, it seems the whole thing is removed?
The same as above, move to the place after than type attr definition and only add fp_vector_disable here.
>> This should be in vector.md instead of riscv.md
It will trigger “unknown attribute `fp_vector_disabled' in definition of attribute `enabled'”, because riscv.md include the vector.md at the end of file.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Friday, June 9, 2023 2:14 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
- (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
Why change this ?
-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
- (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))
I think it should only add fp16_vector_disable. However, it seems the whole thing is removed?
+;; True if the float point vector is disabled.
+(define_attr "fp_vector_disabled" "no,yes"
+ (cond [
+ (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
+ vfwalu,vfwmul,vfmuladd,vfwmuladd,
+ vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
+ vfclass,vfmerge,
+ vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
+ vfredo,vfredu,vfwredo,vfwredu,
+ vfslide1up,vfslide1down")
+ (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+
+ (and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
+ (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+ ]
+ (const_string "no")))
This should be in vector.md instead of riscv.md
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-06-09 13:59
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
iterators of RVV. And then the ZVFH will leverage one define attr
the gate for FP16 supported or not.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Co-Authored by: Kito Cheng <kito.cheng@sifive.com>
gcc/ChangeLog:
* config/riscv/riscv.md (ext): Move to another place.
(ext_enabled): Ditto.
(fp_vector_disabled): New define attr.
(enabled): Add fp_vector_disabled to the cond.
* config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
for ZVFHMIN.
---
gcc/config/riscv/riscv.md | 84 ++++++++++++-------
gcc/config/riscv/vector-iterators.md | 23 ++---
.../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +++-
3 files changed, 81 insertions(+), 41 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 38b8fba2a53..d1c7c3a3008 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -216,35 +216,6 @@ (define_attr "dword_mode" "no,yes"
(const_string "yes")]
(const_string "no")))
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
- (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
-
-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
- (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))
-
;; Classification of each insn.
;; branch conditional branch
;; jump unconditional jump
@@ -434,6 +405,61 @@ (define_attr "type"
(eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")]
(const_string "unknown")))
+;; ISA attributes.
+(define_attr "ext" "base,f,d,vector"
+ (const_string "base"))
+
+;; True if the extension is enabled.
+(define_attr "ext_enabled" "no,yes"
+ (cond [(eq_attr "ext" "base")
+ (const_string "yes")
+
+ (and (eq_attr "ext" "f")
+ (match_test "TARGET_HARD_FLOAT"))
+ (const_string "yes")
+
+ (and (eq_attr "ext" "d")
+ (match_test "TARGET_DOUBLE_FLOAT"))
+ (const_string "yes")
+
+ (and (eq_attr "ext" "vector")
+ (match_test "TARGET_VECTOR"))
+ (const_string "yes")
+ ]
+ (const_string "no")))
+
+;; True if the float point vector is disabled.
+(define_attr "fp_vector_disabled" "no,yes"
+ (cond [
+ (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
+ vfwalu,vfwmul,vfmuladd,vfwmuladd,
+ vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
+ vfclass,vfmerge,
+ vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
+ vfredo,vfredu,vfwredo,vfwredu,
+ vfslide1up,vfslide1down")
+ (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+
+ (and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
+ (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+ ]
+ (const_string "no")))
+
+;; Attribute to control enable or disable instructions.
+(define_attr "enabled" "no,yes"
+ (cond [
+ (eq_attr "ext_enabled" "no")
+ (const_string "no")
+
+ (eq_attr "fp_vector_disabled" "yes")
+ (const_string "no")
+ ]
+ (const_string "yes")))
+
;; Length of instruction in bytes.
(define_attr "length" ""
(cond [
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..234b712bc9d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 0923b6bc4d2..f1a29b639e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -3,6 +3,8 @@
#include "riscv_vector.h"
+typedef _Float16 float16_t;
+
vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
}
@@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
}
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16mf4(base, vl);
+}
+
+vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16m8(base, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
-
+/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-09 6:31 ` juzhe.zhong
@ 2023-06-09 6:41 ` Li, Pan2
2023-06-09 7:08 ` Li, Pan2
0 siblings, 1 reply; 39+ messages in thread
From: Li, Pan2 @ 2023-06-09 6:41 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches
Cc: Robin Dapp, jeffreyalaw, Wang, Yanzhang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 14698 bytes --]
By logically, Yes, we should not change that but here I would like to put all enable related code together, will remove this part as it may has no relationship with this patch.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Friday, June 9, 2023 2:31 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
OK. But why change the place of these
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
- (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
I think it should not be changed.
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: Li, Pan2<mailto:pan2.li@intel.com>
Date: 2023-06-09 14:23
To: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>; gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: Robin Dapp<mailto:rdapp.gcc@gmail.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>; Wang, Yanzhang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
- (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
>> Why change this ?
As the fp will reference the type attr, we should move this part after the type attr definition.
-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
- (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))
>> I think it should only add fp16_vector_disable. However, it seems the whole thing is removed?
The same as above, move to the place after than type attr definition and only add fp_vector_disable here.
>> This should be in vector.md instead of riscv.md
It will trigger “unknown attribute `fp_vector_disabled' in definition of attribute `enabled'”, because riscv.md include the vector.md at the end of file.
Pan
From: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai> <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
Sent: Friday, June 9, 2023 2:14 PM
To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>
Cc: Robin Dapp <rdapp.gcc@gmail.com<mailto:rdapp.gcc@gmail.com>>; jeffreyalaw <jeffreyalaw@gmail.com<mailto:jeffreyalaw@gmail.com>>; Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>; kito.cheng <kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>
Subject: Re: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
- (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
Why change this ?
-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
- (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))
I think it should only add fp16_vector_disable. However, it seems the whole thing is removed?
+;; True if the float point vector is disabled.
+(define_attr "fp_vector_disabled" "no,yes"
+ (cond [
+ (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
+ vfwalu,vfwmul,vfmuladd,vfwmuladd,
+ vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
+ vfclass,vfmerge,
+ vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
+ vfredo,vfredu,vfwredo,vfwredu,
+ vfslide1up,vfslide1down")
+ (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+
+ (and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
+ (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+ ]
+ (const_string "no")))
This should be in vector.md instead of riscv.md
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-06-09 13:59
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; rdapp.gcc<mailto:rdapp.gcc@gmail.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
iterators of RVV. And then the ZVFH will leverage one define attr
the gate for FP16 supported or not.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
Co-Authored by: Kito Cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>
gcc/ChangeLog:
* config/riscv/riscv.md (ext): Move to another place.
(ext_enabled): Ditto.
(fp_vector_disabled): New define attr.
(enabled): Add fp_vector_disabled to the cond.
* config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
for ZVFHMIN.
---
gcc/config/riscv/riscv.md | 84 ++++++++++++-------
gcc/config/riscv/vector-iterators.md | 23 ++---
.../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +++-
3 files changed, 81 insertions(+), 41 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 38b8fba2a53..d1c7c3a3008 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -216,35 +216,6 @@ (define_attr "dword_mode" "no,yes"
(const_string "yes")]
(const_string "no")))
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
- (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
-
-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
- (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))
-
;; Classification of each insn.
;; branch conditional branch
;; jump unconditional jump
@@ -434,6 +405,61 @@ (define_attr "type"
(eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")]
(const_string "unknown")))
+;; ISA attributes.
+(define_attr "ext" "base,f,d,vector"
+ (const_string "base"))
+
+;; True if the extension is enabled.
+(define_attr "ext_enabled" "no,yes"
+ (cond [(eq_attr "ext" "base")
+ (const_string "yes")
+
+ (and (eq_attr "ext" "f")
+ (match_test "TARGET_HARD_FLOAT"))
+ (const_string "yes")
+
+ (and (eq_attr "ext" "d")
+ (match_test "TARGET_DOUBLE_FLOAT"))
+ (const_string "yes")
+
+ (and (eq_attr "ext" "vector")
+ (match_test "TARGET_VECTOR"))
+ (const_string "yes")
+ ]
+ (const_string "no")))
+
+;; True if the float point vector is disabled.
+(define_attr "fp_vector_disabled" "no,yes"
+ (cond [
+ (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
+ vfwalu,vfwmul,vfmuladd,vfwmuladd,
+ vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
+ vfclass,vfmerge,
+ vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
+ vfredo,vfredu,vfwredo,vfwredu,
+ vfslide1up,vfslide1down")
+ (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+
+ (and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
+ (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+ ]
+ (const_string "no")))
+
+;; Attribute to control enable or disable instructions.
+(define_attr "enabled" "no,yes"
+ (cond [
+ (eq_attr "ext_enabled" "no")
+ (const_string "no")
+
+ (eq_attr "fp_vector_disabled" "yes")
+ (const_string "no")
+ ]
+ (const_string "yes")))
+
;; Length of instruction in bytes.
(define_attr "length" ""
(cond [
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..234b712bc9d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 0923b6bc4d2..f1a29b639e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -3,6 +3,8 @@
#include "riscv_vector.h"
+typedef _Float16 float16_t;
+
vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
}
@@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
}
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16mf4(base, vl);
+}
+
+vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16m8(base, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
-
+/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-06 12:36 [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern pan2.li
` (8 preceding siblings ...)
2023-06-09 5:59 ` [PATCH v9] " pan2.li
@ 2023-06-09 7:07 ` pan2.li
2023-06-09 7:14 ` juzhe.zhong
9 siblings, 1 reply; 39+ messages in thread
From: pan2.li @ 2023-06-09 7:07 UTC (permalink / raw)
To: gcc-patches
Cc: juzhe.zhong, rdapp.gcc, jeffreyalaw, pan2.li, yanzhang.wang, kito.cheng
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
iterators of RVV. And then the ZVFH will leverage one define attr as
the gate for FP16 supported or not.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Co-Authored by: Kito Cheng <kito.cheng@sifive.com>
gcc/ChangeLog:
* config/riscv/riscv.md (enabled): Move to another place, and
add fp_vector_disabled to the cond.
(fp_vector_disabled): New attr defined for disabling fp.
* config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
for ZVFHMIN.
---
gcc/config/riscv/riscv.md | 39 ++++++++++++++++---
gcc/config/riscv/vector-iterators.md | 23 ++++++-----
.../riscv/rvv/base/zvfhmin-intrinsic.c | 15 ++++++-
3 files changed, 59 insertions(+), 18 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 38b8fba2a53..d8e935cb934 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -239,12 +239,6 @@ (define_attr "ext_enabled" "no,yes"
]
(const_string "no")))
-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
- (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))
-
;; Classification of each insn.
;; branch conditional branch
;; jump unconditional jump
@@ -434,6 +428,39 @@ (define_attr "type"
(eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")]
(const_string "unknown")))
+;; True if the float point vector is disabled.
+(define_attr "fp_vector_disabled" "no,yes"
+ (cond [
+ (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
+ vfwalu,vfwmul,vfmuladd,vfwmuladd,
+ vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
+ vfclass,vfmerge,
+ vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
+ vfredo,vfredu,vfwredo,vfwredu,
+ vfslide1up,vfslide1down")
+ (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+
+ ;; The mode records as QI for the FP16 <=> INT8 instruction.
+ (and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
+ (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+ ]
+ (const_string "no")))
+
+;; Attribute to control enable or disable instructions.
+(define_attr "enabled" "no,yes"
+ (cond [
+ (eq_attr "ext_enabled" "no")
+ (const_string "no")
+
+ (eq_attr "fp_vector_disabled" "yes")
+ (const_string "no")
+ ]
+ (const_string "yes")))
+
;; Length of instruction in bytes.
(define_attr "length" ""
(cond [
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..234b712bc9d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 0923b6bc4d2..f1a29b639e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -3,6 +3,8 @@
#include "riscv_vector.h"
+typedef _Float16 float16_t;
+
vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
}
@@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
}
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16mf4(base, vl);
+}
+
+vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16m8(base, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
-
+/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-09 6:41 ` Li, Pan2
@ 2023-06-09 7:08 ` Li, Pan2
0 siblings, 0 replies; 39+ messages in thread
From: Li, Pan2 @ 2023-06-09 7:08 UTC (permalink / raw)
To: Li, Pan2, juzhe.zhong, gcc-patches
Cc: Robin Dapp, jeffreyalaw, Wang, Yanzhang, kito.cheng
Thanks Juzhe and Kito for reviewing, update the PATCH v10 as below.
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621104.html
Pan
-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Li, Pan2 via Gcc-patches
Sent: Friday, June 9, 2023 2:41 PM
To: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: RE: RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
By logically, Yes, we should not change that but here I would like to put all enable related code together, will remove this part as it may has no relationship with this patch.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Friday, June 9, 2023 2:31 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
OK. But why change the place of these
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
- (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
I think it should not be changed.
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: Li, Pan2<mailto:pan2.li@intel.com>
Date: 2023-06-09 14:23
To: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>; gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: Robin Dapp<mailto:rdapp.gcc@gmail.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>; Wang, Yanzhang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
- (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
>> Why change this ?
As the fp will reference the type attr, we should move this part after the type attr definition.
-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
- (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))
>> I think it should only add fp16_vector_disable. However, it seems the whole thing is removed?
The same as above, move to the place after than type attr definition and only add fp_vector_disable here.
>> This should be in vector.md instead of riscv.md
It will trigger “unknown attribute `fp_vector_disabled' in definition of attribute `enabled'”, because riscv.md include the vector.md at the end of file.
Pan
From: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai> <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
Sent: Friday, June 9, 2023 2:14 PM
To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>
Cc: Robin Dapp <rdapp.gcc@gmail.com<mailto:rdapp.gcc@gmail.com>>; jeffreyalaw <jeffreyalaw@gmail.com<mailto:jeffreyalaw@gmail.com>>; Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>; kito.cheng <kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>
Subject: Re: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
- (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
Why change this ?
-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
- (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))
I think it should only add fp16_vector_disable. However, it seems the whole thing is removed?
+;; True if the float point vector is disabled.
+(define_attr "fp_vector_disabled" "no,yes"
+ (cond [
+ (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
+ vfwalu,vfwmul,vfmuladd,vfwmuladd,
+ vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
+ vfclass,vfmerge,
+ vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
+ vfredo,vfredu,vfwredo,vfwredu,
+ vfslide1up,vfslide1down")
+ (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+
+ (and (eq_attr "type" "vfncvtftoi,vfwcvtitof") (and (eq_attr "mode"
+ "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+ ]
+ (const_string "no")))
This should be in vector.md instead of riscv.md
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-06-09 13:59
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; rdapp.gcc<mailto:rdapp.gcc@gmail.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
This patch would like to refactor the requirement of both the ZVFH and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the iterators of RVV. And then the ZVFH will leverage one define attr the gate for FP16 supported or not.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
Co-Authored by: Kito Cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>
gcc/ChangeLog:
* config/riscv/riscv.md (ext): Move to another place.
(ext_enabled): Ditto.
(fp_vector_disabled): New define attr.
(enabled): Add fp_vector_disabled to the cond.
* config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test for ZVFHMIN.
---
gcc/config/riscv/riscv.md | 84 ++++++++++++-------
gcc/config/riscv/vector-iterators.md | 23 ++---
.../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +++-
3 files changed, 81 insertions(+), 41 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 38b8fba2a53..d1c7c3a3008 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -216,35 +216,6 @@ (define_attr "dword_mode" "no,yes"
(const_string "yes")]
(const_string "no")))
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
- (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
-
-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
- (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))
-
;; Classification of each insn.
;; branch conditional branch
;; jump unconditional jump
@@ -434,6 +405,61 @@ (define_attr "type"
(eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")] (const_string "unknown")))
+;; ISA attributes.
+(define_attr "ext" "base,f,d,vector"
+ (const_string "base"))
+
+;; True if the extension is enabled.
+(define_attr "ext_enabled" "no,yes"
+ (cond [(eq_attr "ext" "base")
+ (const_string "yes")
+
+ (and (eq_attr "ext" "f")
+ (match_test "TARGET_HARD_FLOAT")) (const_string "yes")
+
+ (and (eq_attr "ext" "d")
+ (match_test "TARGET_DOUBLE_FLOAT")) (const_string "yes")
+
+ (and (eq_attr "ext" "vector")
+ (match_test "TARGET_VECTOR"))
+ (const_string "yes")
+ ]
+ (const_string "no")))
+
+;; True if the float point vector is disabled.
+(define_attr "fp_vector_disabled" "no,yes"
+ (cond [
+ (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
+ vfwalu,vfwmul,vfmuladd,vfwmuladd,
+ vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
+ vfclass,vfmerge,
+ vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
+ vfredo,vfredu,vfwredo,vfwredu,
+ vfslide1up,vfslide1down")
+ (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+
+ (and (eq_attr "type" "vfncvtftoi,vfwcvtitof") (and (eq_attr "mode"
+ "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+ ]
+ (const_string "no")))
+
+;; Attribute to control enable or disable instructions.
+(define_attr "enabled" "no,yes"
+ (cond [
+ (eq_attr "ext_enabled" "no")
+ (const_string "no")
+
+ (eq_attr "fp_vector_disabled" "yes")
+ (const_string "no")
+ ]
+ (const_string "yes")))
+
;; Length of instruction in bytes.
(define_attr "length" ""
(cond [
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..234b712bc9d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32") (VNx4HF
+ "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") @@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [ (define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") (VNx2HF
+ "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") (VNx4HF
+ "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") @@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 &&
+ TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_16 &&
+ TARGET_VECTOR_ELEN_FP_32") (VNx4SF "TARGET_VECTOR_ELEN_FP_16 &&
+ TARGET_VECTOR_ELEN_FP_32") (VNx8SF "TARGET_VECTOR_ELEN_FP_16 &&
+ TARGET_VECTOR_ELEN_FP_32") (VNx16SF "TARGET_VECTOR_ELEN_FP_16 &&
+ TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") (VNx32SF
+ "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 &&
+ TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 0923b6bc4d2..f1a29b639e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -3,6 +3,8 @@
#include "riscv_vector.h"
+typedef _Float16 float16_t;
+
vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
return __riscv_vfncvt_f_f_w_f16mf4(src, vl); } @@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
return __riscv_vfwcvt_f_f_v_f32m8(src, vl); }
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16mf4(base, vl); }
+
+vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16m8(base, vl); }
+
+/* { dg-final { scan-assembler-times
+{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times
+{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
-
+/* { dg-final { scan-assembler-times
+{vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-09 7:07 ` [PATCH v10] " pan2.li
@ 2023-06-09 7:14 ` juzhe.zhong
2023-06-09 8:28 ` Kito Cheng
0 siblings, 1 reply; 39+ messages in thread
From: juzhe.zhong @ 2023-06-09 7:14 UTC (permalink / raw)
To: pan2.li, gcc-patches
Cc: Robin Dapp, jeffreyalaw, pan2.li, yanzhang.wang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 7916 bytes --]
LGTM.
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-06-09 15:07
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li <pan2.li@intel.com>
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
iterators of RVV. And then the ZVFH will leverage one define attr as
the gate for FP16 supported or not.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Co-Authored by: Kito Cheng <kito.cheng@sifive.com>
gcc/ChangeLog:
* config/riscv/riscv.md (enabled): Move to another place, and
add fp_vector_disabled to the cond.
(fp_vector_disabled): New attr defined for disabling fp.
* config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
for ZVFHMIN.
---
gcc/config/riscv/riscv.md | 39 ++++++++++++++++---
gcc/config/riscv/vector-iterators.md | 23 ++++++-----
.../riscv/rvv/base/zvfhmin-intrinsic.c | 15 ++++++-
3 files changed, 59 insertions(+), 18 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 38b8fba2a53..d8e935cb934 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -239,12 +239,6 @@ (define_attr "ext_enabled" "no,yes"
]
(const_string "no")))
-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
- (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))
-
;; Classification of each insn.
;; branch conditional branch
;; jump unconditional jump
@@ -434,6 +428,39 @@ (define_attr "type"
(eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")]
(const_string "unknown")))
+;; True if the float point vector is disabled.
+(define_attr "fp_vector_disabled" "no,yes"
+ (cond [
+ (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
+ vfwalu,vfwmul,vfmuladd,vfwmuladd,
+ vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
+ vfclass,vfmerge,
+ vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
+ vfredo,vfredu,vfwredo,vfwredu,
+ vfslide1up,vfslide1down")
+ (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+
+ ;; The mode records as QI for the FP16 <=> INT8 instruction.
+ (and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
+ (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
+ (match_test "!TARGET_ZVFH")))
+ (const_string "yes")
+ ]
+ (const_string "no")))
+
+;; Attribute to control enable or disable instructions.
+(define_attr "enabled" "no,yes"
+ (cond [
+ (eq_attr "ext_enabled" "no")
+ (const_string "no")
+
+ (eq_attr "fp_vector_disabled" "yes")
+ (const_string "no")
+ ]
+ (const_string "yes")))
+
;; Length of instruction in bytes.
(define_attr "length" ""
(cond [
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..234b712bc9d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
- (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
- (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
- (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+ (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+ (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
- (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
- (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
- (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+ (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+ (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 0923b6bc4d2..f1a29b639e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -3,6 +3,8 @@
#include "riscv_vector.h"
+typedef _Float16 float16_t;
+
vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
}
@@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
}
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16mf4(base, vl);
+}
+
+vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16m8(base, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
-
+/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-09 7:14 ` juzhe.zhong
@ 2023-06-09 8:28 ` Kito Cheng
2023-06-09 8:32 ` Li, Pan2
0 siblings, 1 reply; 39+ messages in thread
From: Kito Cheng @ 2023-06-09 8:28 UTC (permalink / raw)
To: juzhe.zhong; +Cc: pan2.li, gcc-patches, Robin Dapp, jeffreyalaw, yanzhang.wang
lgtm too, thanks :)
On Fri, Jun 9, 2023 at 3:15 PM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> LGTM.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: pan2.li
> Date: 2023-06-09 15:07
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
> Subject: [PATCH v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to refactor the requirement of both the ZVFH
> and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
> iterators of RVV. And then the ZVFH will leverage one define attr as
> the gate for FP16 supported or not.
>
> Please note the ZVFH will cover the ZVFHMIN instructions. This patch
> add one test for this.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
> Co-Authored by: Kito Cheng <kito.cheng@sifive.com>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md (enabled): Move to another place, and
> add fp_vector_disabled to the cond.
> (fp_vector_disabled): New attr defined for disabling fp.
> * config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
> for ZVFHMIN.
> ---
> gcc/config/riscv/riscv.md | 39 ++++++++++++++++---
> gcc/config/riscv/vector-iterators.md | 23 ++++++-----
> .../riscv/rvv/base/zvfhmin-intrinsic.c | 15 ++++++-
> 3 files changed, 59 insertions(+), 18 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 38b8fba2a53..d8e935cb934 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -239,12 +239,6 @@ (define_attr "ext_enabled" "no,yes"
> ]
> (const_string "no")))
> -;; Attribute to control enable or disable instructions.
> -(define_attr "enabled" "no,yes"
> - (cond [(eq_attr "ext_enabled" "no")
> - (const_string "no")]
> - (const_string "yes")))
> -
> ;; Classification of each insn.
> ;; branch conditional branch
> ;; jump unconditional jump
> @@ -434,6 +428,39 @@ (define_attr "type"
> (eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")]
> (const_string "unknown")))
> +;; True if the float point vector is disabled.
> +(define_attr "fp_vector_disabled" "no,yes"
> + (cond [
> + (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
> + vfwalu,vfwmul,vfmuladd,vfwmuladd,
> + vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
> + vfclass,vfmerge,
> + vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
> + vfredo,vfredu,vfwredo,vfwredu,
> + vfslide1up,vfslide1down")
> + (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
> + (match_test "!TARGET_ZVFH")))
> + (const_string "yes")
> +
> + ;; The mode records as QI for the FP16 <=> INT8 instruction.
> + (and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
> + (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
> + (match_test "!TARGET_ZVFH")))
> + (const_string "yes")
> + ]
> + (const_string "no")))
> +
> +;; Attribute to control enable or disable instructions.
> +(define_attr "enabled" "no,yes"
> + (cond [
> + (eq_attr "ext_enabled" "no")
> + (const_string "no")
> +
> + (eq_attr "fp_vector_disabled" "yes")
> + (const_string "no")
> + ]
> + (const_string "yes")))
> +
> ;; Length of instruction in bytes.
> (define_attr "length" ""
> (cond [
> diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
> index f4946d84449..234b712bc9d 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
> (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
> (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
> - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> - (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
> - (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
> + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
> + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
> (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
> (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
> (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
> @@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
> (define_mode_iterator V_FRACT [
> (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
> (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
> - (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
> +
> + (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
> + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
> +
> (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
> (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
> (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> @@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
> ])
> (define_mode_iterator VWEXTF [
> - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> - (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
> - (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> + (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> + (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> + (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> + (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> + (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
> + (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
> (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> index 0923b6bc4d2..f1a29b639e0 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> @@ -3,6 +3,8 @@
> #include "riscv_vector.h"
> +typedef _Float16 float16_t;
> +
> vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
> return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
> }
> @@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
> return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
> }
> -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
> +vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
> + return __riscv_vle16_v_f16mf4(base, vl);
> +}
> +
> +vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
> + return __riscv_vle16_v_f16m8(base, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
> /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> -
> +/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: [PATCH v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
2023-06-09 8:28 ` Kito Cheng
@ 2023-06-09 8:32 ` Li, Pan2
0 siblings, 0 replies; 39+ messages in thread
From: Li, Pan2 @ 2023-06-09 8:32 UTC (permalink / raw)
To: Kito Cheng, juzhe.zhong
Cc: gcc-patches, Robin Dapp, jeffreyalaw, Wang, Yanzhang
Committed, thanks Juzhe and Kito.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Friday, June 9, 2023 4:28 PM
To: juzhe.zhong@rivai.ai
Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>; Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
lgtm too, thanks :)
On Fri, Jun 9, 2023 at 3:15 PM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> LGTM.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: pan2.li
> Date: 2023-06-09 15:07
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
> Subject: [PATCH v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to refactor the requirement of both the ZVFH
> and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
> iterators of RVV. And then the ZVFH will leverage one define attr as
> the gate for FP16 supported or not.
>
> Please note the ZVFH will cover the ZVFHMIN instructions. This patch
> add one test for this.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
> Co-Authored by: Kito Cheng <kito.cheng@sifive.com>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md (enabled): Move to another place, and
> add fp_vector_disabled to the cond.
> (fp_vector_disabled): New attr defined for disabling fp.
> * config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
> for ZVFHMIN.
> ---
> gcc/config/riscv/riscv.md | 39 ++++++++++++++++---
> gcc/config/riscv/vector-iterators.md | 23 ++++++-----
> .../riscv/rvv/base/zvfhmin-intrinsic.c | 15 ++++++-
> 3 files changed, 59 insertions(+), 18 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 38b8fba2a53..d8e935cb934 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -239,12 +239,6 @@ (define_attr "ext_enabled" "no,yes"
> ]
> (const_string "no")))
> -;; Attribute to control enable or disable instructions.
> -(define_attr "enabled" "no,yes"
> - (cond [(eq_attr "ext_enabled" "no")
> - (const_string "no")]
> - (const_string "yes")))
> -
> ;; Classification of each insn.
> ;; branch conditional branch
> ;; jump unconditional jump
> @@ -434,6 +428,39 @@ (define_attr "type"
> (eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")]
> (const_string "unknown")))
> +;; True if the float point vector is disabled.
> +(define_attr "fp_vector_disabled" "no,yes"
> + (cond [
> + (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
> + vfwalu,vfwmul,vfmuladd,vfwmuladd,
> + vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
> + vfclass,vfmerge,
> + vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
> + vfredo,vfredu,vfwredo,vfwredu,
> + vfslide1up,vfslide1down")
> + (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
> + (match_test "!TARGET_ZVFH")))
> + (const_string "yes")
> +
> + ;; The mode records as QI for the FP16 <=> INT8 instruction.
> + (and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
> + (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
> + (match_test "!TARGET_ZVFH")))
> + (const_string "yes")
> + ]
> + (const_string "no")))
> +
> +;; Attribute to control enable or disable instructions.
> +(define_attr "enabled" "no,yes"
> + (cond [
> + (eq_attr "ext_enabled" "no")
> + (const_string "no")
> +
> + (eq_attr "fp_vector_disabled" "yes")
> + (const_string "no")
> + ]
> + (const_string "yes")))
> +
> ;; Length of instruction in bytes.
> (define_attr "length" ""
> (cond [
> diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
> index f4946d84449..234b712bc9d 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
> (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
> (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
> - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> - (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
> - (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
> + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
> + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
> (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
> (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
> (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
> @@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
> (define_mode_iterator V_FRACT [
> (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
> (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
> - (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
> +
> + (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
> + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
> +
> (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
> (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
> (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> @@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
> ])
> (define_mode_iterator VWEXTF [
> - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> - (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
> - (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
> - (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> + (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> + (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> + (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> + (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
> + (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
> + (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
> (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> index 0923b6bc4d2..f1a29b639e0 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> @@ -3,6 +3,8 @@
> #include "riscv_vector.h"
> +typedef _Float16 float16_t;
> +
> vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
> return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
> }
> @@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
> return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
> }
> -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
> +vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
> + return __riscv_vle16_v_f16mf4(base, vl);
> +}
> +
> +vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
> + return __riscv_vle16_v_f16m8(base, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
> /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> -
> +/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2023-06-09 8:32 UTC | newest]
Thread overview: 39+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-06 12:36 [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern pan2.li
2023-06-06 14:07 ` 钟居哲
2023-06-06 14:34 ` Li, Pan2
2023-06-06 15:34 ` Li, Pan2
2023-06-07 3:02 ` Li, Pan2
2023-06-06 15:32 ` [PATCH v2] RISC-V: Refactor requirement of ZVFH and ZVFHMIN pan2.li
2023-06-07 3:00 ` [PATCH v3] " pan2.li
2023-06-07 4:21 ` juzhe.zhong
2023-06-07 6:20 ` Li, Pan2
2023-06-07 6:57 ` Li, Pan2
2023-06-07 8:07 ` Li, Pan2
2023-06-07 6:52 ` [PATCH] " pan2.li
2023-06-07 8:06 ` [PATCH v5] " pan2.li
2023-06-07 8:11 ` juzhe.zhong
2023-06-07 8:27 ` juzhe.zhong
2023-06-07 8:42 ` Li, Pan2
2023-06-08 6:07 ` Li, Pan2
2023-06-08 5:20 ` [PATCH v6] " pan2.li
2023-06-08 6:06 ` [PATCH v7] " pan2.li
2023-06-08 6:09 ` juzhe.zhong
2023-06-08 6:31 ` Li, Pan2
2023-06-08 6:29 ` [PATCH v8] " pan2.li
2023-06-08 6:34 ` juzhe.zhong
2023-06-08 7:58 ` Kito Cheng
2023-06-08 8:00 ` juzhe.zhong
2023-06-08 8:01 ` Li, Pan2
2023-06-08 8:32 ` juzhe.zhong
2023-06-08 13:13 ` Li, Pan2
2023-06-08 13:24 ` Kito Cheng
2023-06-09 5:59 ` [PATCH v9] " pan2.li
2023-06-09 6:13 ` juzhe.zhong
2023-06-09 6:23 ` Li, Pan2
2023-06-09 6:31 ` juzhe.zhong
2023-06-09 6:41 ` Li, Pan2
2023-06-09 7:08 ` Li, Pan2
2023-06-09 7:07 ` [PATCH v10] " pan2.li
2023-06-09 7:14 ` juzhe.zhong
2023-06-09 8:28 ` Kito Cheng
2023-06-09 8:32 ` Li, Pan2
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