* [PATCH 01/10] arm: Mve testsuite improvements
@ 2023-04-28 11:29 Andrea Corallo
2023-04-28 11:29 ` [PATCH 02/10] arm: Fix vstrwq* backend + testsuite Andrea Corallo
` (9 more replies)
0 siblings, 10 replies; 31+ messages in thread
From: Andrea Corallo @ 2023-04-28 11:29 UTC (permalink / raw)
To: gcc-patches; +Cc: kyrylo.tkachov, Richard.Earnshaw, Andrea Corallo
Hello all,
this patch improves a number of MVE tests in the testsuite for more
precise and better coverage using check-function-bodies instead of
scan-assembler checks. Also all intrusctions prescribed in the ACLE[1]
are now checked.
Best Regards
Andrea
[1] <https://github.com/ARM-software/acle>
gcc/testsuite/ChangeLog:
* gcc.target/arm/mve/intrinsics/vld1q_f16.c: Use
check-function-bodies instead of scan-assembler checks. Use
extern "C" for C++ testing.
* gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_z_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_z_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_z_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_z_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_z_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_z_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_z_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld4q_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld4q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld4q_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld4q_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld4q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld4q_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld4q_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld4q_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst2q_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst2q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst2q_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst2q_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst2q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst2q_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst2q_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst2q_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst4q_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst4q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst4q_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst4q_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst4q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst4q_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst4q_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst4q_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_u32.c: Likewise.
---
.../gcc.target/arm/mve/intrinsics/vld1q_f16.c | 29 +++++++++--
.../gcc.target/arm/mve/intrinsics/vld1q_f32.c | 29 +++++++++--
.../gcc.target/arm/mve/intrinsics/vld1q_s16.c | 29 +++++++++--
.../gcc.target/arm/mve/intrinsics/vld1q_s32.c | 29 +++++++++--
.../gcc.target/arm/mve/intrinsics/vld1q_s8.c | 29 +++++++++--
.../gcc.target/arm/mve/intrinsics/vld1q_u16.c | 29 +++++++++--
.../gcc.target/arm/mve/intrinsics/vld1q_u32.c | 29 +++++++++--
.../gcc.target/arm/mve/intrinsics/vld1q_u8.c | 29 +++++++++--
.../arm/mve/intrinsics/vld1q_z_f16.c | 38 ++++++++++++--
.../arm/mve/intrinsics/vld1q_z_f32.c | 38 ++++++++++++--
.../arm/mve/intrinsics/vld1q_z_s16.c | 38 ++++++++++++--
.../arm/mve/intrinsics/vld1q_z_s32.c | 38 ++++++++++++--
.../arm/mve/intrinsics/vld1q_z_s8.c | 38 ++++++++++++--
.../arm/mve/intrinsics/vld1q_z_u16.c | 38 ++++++++++++--
.../arm/mve/intrinsics/vld1q_z_u32.c | 38 ++++++++++++--
.../arm/mve/intrinsics/vld1q_z_u8.c | 38 ++++++++++++--
.../gcc.target/arm/mve/intrinsics/vld4q_f16.c | 37 +++++++++++---
.../gcc.target/arm/mve/intrinsics/vld4q_f32.c | 37 +++++++++++---
.../gcc.target/arm/mve/intrinsics/vld4q_s16.c | 37 +++++++++++---
.../gcc.target/arm/mve/intrinsics/vld4q_s32.c | 37 +++++++++++---
.../gcc.target/arm/mve/intrinsics/vld4q_s8.c | 37 +++++++++++---
.../gcc.target/arm/mve/intrinsics/vld4q_u16.c | 37 +++++++++++---
.../gcc.target/arm/mve/intrinsics/vld4q_u32.c | 37 +++++++++++---
.../gcc.target/arm/mve/intrinsics/vld4q_u8.c | 37 +++++++++++---
.../mve/intrinsics/vldrbq_gather_offset_s16.c | 28 +++++++++--
.../mve/intrinsics/vldrbq_gather_offset_s32.c | 28 +++++++++--
.../mve/intrinsics/vldrbq_gather_offset_s8.c | 28 +++++++++--
.../mve/intrinsics/vldrbq_gather_offset_u16.c | 28 +++++++++--
.../mve/intrinsics/vldrbq_gather_offset_u32.c | 28 +++++++++--
.../mve/intrinsics/vldrbq_gather_offset_u8.c | 28 +++++++++--
.../intrinsics/vldrbq_gather_offset_z_s16.c | 36 +++++++++++--
.../intrinsics/vldrbq_gather_offset_z_s32.c | 36 +++++++++++--
.../intrinsics/vldrbq_gather_offset_z_s8.c | 36 +++++++++++--
.../intrinsics/vldrbq_gather_offset_z_u16.c | 36 +++++++++++--
.../intrinsics/vldrbq_gather_offset_z_u32.c | 36 +++++++++++--
.../intrinsics/vldrbq_gather_offset_z_u8.c | 36 +++++++++++--
.../arm/mve/intrinsics/vldrbq_s16.c | 19 ++++++-
.../arm/mve/intrinsics/vldrbq_s32.c | 19 ++++++-
.../gcc.target/arm/mve/intrinsics/vldrbq_s8.c | 20 ++++++--
.../arm/mve/intrinsics/vldrbq_u16.c | 19 ++++++-
.../arm/mve/intrinsics/vldrbq_u32.c | 19 ++++++-
.../gcc.target/arm/mve/intrinsics/vldrbq_u8.c | 20 ++++++--
.../arm/mve/intrinsics/vldrbq_z_s16.c | 23 ++++++++-
.../arm/mve/intrinsics/vldrbq_z_s32.c | 23 ++++++++-
.../arm/mve/intrinsics/vldrbq_z_s8.c | 25 ++++++++--
.../arm/mve/intrinsics/vldrbq_z_u16.c | 23 ++++++++-
.../arm/mve/intrinsics/vldrbq_z_u32.c | 23 ++++++++-
.../arm/mve/intrinsics/vldrbq_z_u8.c | 25 ++++++++--
.../mve/intrinsics/vldrdq_gather_base_s64.c | 19 ++++++-
.../mve/intrinsics/vldrdq_gather_base_u64.c | 19 ++++++-
.../intrinsics/vldrdq_gather_base_wb_s64.c | 24 ++++++---
.../intrinsics/vldrdq_gather_base_wb_u64.c | 24 ++++++---
.../intrinsics/vldrdq_gather_base_wb_z_s64.c | 31 +++++++++---
.../intrinsics/vldrdq_gather_base_wb_z_u64.c | 31 +++++++++---
.../mve/intrinsics/vldrdq_gather_base_z_s64.c | 23 ++++++++-
.../mve/intrinsics/vldrdq_gather_base_z_u64.c | 23 ++++++++-
.../mve/intrinsics/vldrdq_gather_offset_s64.c | 28 +++++++++--
.../mve/intrinsics/vldrdq_gather_offset_u64.c | 28 +++++++++--
.../intrinsics/vldrdq_gather_offset_z_s64.c | 36 +++++++++++--
.../intrinsics/vldrdq_gather_offset_z_u64.c | 36 +++++++++++--
.../vldrdq_gather_shifted_offset_s64.c | 28 +++++++++--
.../vldrdq_gather_shifted_offset_u64.c | 28 +++++++++--
.../vldrdq_gather_shifted_offset_z_s64.c | 36 +++++++++++--
.../vldrdq_gather_shifted_offset_z_u64.c | 36 +++++++++++--
.../arm/mve/intrinsics/vldrhq_f16.c | 20 ++++++--
.../mve/intrinsics/vldrhq_gather_offset_f16.c | 28 +++++++++--
.../mve/intrinsics/vldrhq_gather_offset_s16.c | 28 +++++++++--
.../mve/intrinsics/vldrhq_gather_offset_s32.c | 28 +++++++++--
.../mve/intrinsics/vldrhq_gather_offset_u16.c | 28 +++++++++--
.../mve/intrinsics/vldrhq_gather_offset_u32.c | 28 +++++++++--
.../intrinsics/vldrhq_gather_offset_z_f16.c | 36 +++++++++++--
.../intrinsics/vldrhq_gather_offset_z_s16.c | 36 +++++++++++--
.../intrinsics/vldrhq_gather_offset_z_s32.c | 36 +++++++++++--
.../intrinsics/vldrhq_gather_offset_z_u16.c | 36 +++++++++++--
.../intrinsics/vldrhq_gather_offset_z_u32.c | 36 +++++++++++--
.../vldrhq_gather_shifted_offset_f16.c | 28 +++++++++--
.../vldrhq_gather_shifted_offset_s16.c | 28 +++++++++--
.../vldrhq_gather_shifted_offset_s32.c | 28 +++++++++--
.../vldrhq_gather_shifted_offset_u16.c | 28 +++++++++--
.../vldrhq_gather_shifted_offset_u32.c | 28 +++++++++--
.../vldrhq_gather_shifted_offset_z_f16.c | 36 +++++++++++--
.../vldrhq_gather_shifted_offset_z_s16.c | 36 +++++++++++--
.../vldrhq_gather_shifted_offset_z_s32.c | 36 +++++++++++--
.../vldrhq_gather_shifted_offset_z_u16.c | 36 +++++++++++--
.../vldrhq_gather_shifted_offset_z_u32.c | 36 +++++++++++--
.../arm/mve/intrinsics/vldrhq_s16.c | 20 ++++++--
.../arm/mve/intrinsics/vldrhq_s32.c | 20 ++++++--
.../arm/mve/intrinsics/vldrhq_u16.c | 20 ++++++--
.../arm/mve/intrinsics/vldrhq_u32.c | 20 ++++++--
.../arm/mve/intrinsics/vldrhq_z_f16.c | 23 +++++++--
.../arm/mve/intrinsics/vldrhq_z_s16.c | 23 +++++++--
.../arm/mve/intrinsics/vldrhq_z_s32.c | 25 ++++++++--
.../arm/mve/intrinsics/vldrhq_z_u16.c | 23 +++++++--
.../arm/mve/intrinsics/vldrhq_z_u32.c | 25 ++++++++--
.../arm/mve/intrinsics/vldrwq_f32.c | 18 ++++++-
.../mve/intrinsics/vldrwq_gather_base_f32.c | 19 ++++++-
.../mve/intrinsics/vldrwq_gather_base_s32.c | 19 ++++++-
.../mve/intrinsics/vldrwq_gather_base_u32.c | 19 ++++++-
.../intrinsics/vldrwq_gather_base_wb_f32.c | 22 ++++++--
.../intrinsics/vldrwq_gather_base_wb_s32.c | 22 ++++++--
.../intrinsics/vldrwq_gather_base_wb_u32.c | 22 ++++++--
.../intrinsics/vldrwq_gather_base_wb_z_f32.c | 28 ++++++++---
.../intrinsics/vldrwq_gather_base_wb_z_s32.c | 28 ++++++++---
.../intrinsics/vldrwq_gather_base_wb_z_u32.c | 28 ++++++++---
.../mve/intrinsics/vldrwq_gather_base_z_f32.c | 23 ++++++++-
.../mve/intrinsics/vldrwq_gather_base_z_s32.c | 23 ++++++++-
.../mve/intrinsics/vldrwq_gather_base_z_u32.c | 23 ++++++++-
.../mve/intrinsics/vldrwq_gather_offset_f32.c | 28 +++++++++--
.../mve/intrinsics/vldrwq_gather_offset_s32.c | 28 +++++++++--
.../mve/intrinsics/vldrwq_gather_offset_u32.c | 28 +++++++++--
.../intrinsics/vldrwq_gather_offset_z_f32.c | 36 +++++++++++--
.../intrinsics/vldrwq_gather_offset_z_s32.c | 36 +++++++++++--
.../intrinsics/vldrwq_gather_offset_z_u32.c | 36 +++++++++++--
.../vldrwq_gather_shifted_offset_f32.c | 28 +++++++++--
.../vldrwq_gather_shifted_offset_s32.c | 28 +++++++++--
.../vldrwq_gather_shifted_offset_u32.c | 28 +++++++++--
.../vldrwq_gather_shifted_offset_z_f32.c | 36 +++++++++++--
.../vldrwq_gather_shifted_offset_z_s32.c | 36 +++++++++++--
.../vldrwq_gather_shifted_offset_z_u32.c | 36 +++++++++++--
.../arm/mve/intrinsics/vldrwq_s32.c | 18 ++++++-
.../arm/mve/intrinsics/vldrwq_u32.c | 18 ++++++-
.../arm/mve/intrinsics/vldrwq_z_f32.c | 23 +++++++--
.../arm/mve/intrinsics/vldrwq_z_s32.c | 23 +++++++--
.../arm/mve/intrinsics/vldrwq_z_u32.c | 23 +++++++--
.../gcc.target/arm/mve/intrinsics/vst2q_f16.c | 37 +++++++++++---
.../gcc.target/arm/mve/intrinsics/vst2q_f32.c | 37 +++++++++++---
.../gcc.target/arm/mve/intrinsics/vst2q_s16.c | 37 +++++++++++---
.../gcc.target/arm/mve/intrinsics/vst2q_s32.c | 37 +++++++++++---
.../gcc.target/arm/mve/intrinsics/vst2q_s8.c | 37 +++++++++++---
.../gcc.target/arm/mve/intrinsics/vst2q_u16.c | 37 +++++++++++---
.../gcc.target/arm/mve/intrinsics/vst2q_u32.c | 37 +++++++++++---
.../gcc.target/arm/mve/intrinsics/vst2q_u8.c | 37 +++++++++++---
.../gcc.target/arm/mve/intrinsics/vst4q_f16.c | 50 +++++++++++--------
.../gcc.target/arm/mve/intrinsics/vst4q_f32.c | 50 +++++++++++--------
.../gcc.target/arm/mve/intrinsics/vst4q_s16.c | 50 +++++++++++--------
.../gcc.target/arm/mve/intrinsics/vst4q_s32.c | 50 +++++++++++--------
.../gcc.target/arm/mve/intrinsics/vst4q_s8.c | 50 +++++++++++--------
.../gcc.target/arm/mve/intrinsics/vst4q_u16.c | 50 +++++++++++--------
.../gcc.target/arm/mve/intrinsics/vst4q_u32.c | 50 +++++++++++--------
.../gcc.target/arm/mve/intrinsics/vst4q_u8.c | 50 +++++++++++--------
.../arm/mve/intrinsics/vstrbq_p_s16.c | 40 ++++++++++++---
.../arm/mve/intrinsics/vstrbq_p_s32.c | 40 ++++++++++++---
.../arm/mve/intrinsics/vstrbq_p_s8.c | 40 ++++++++++++---
.../arm/mve/intrinsics/vstrbq_p_u16.c | 40 ++++++++++++---
.../arm/mve/intrinsics/vstrbq_p_u32.c | 40 ++++++++++++---
.../arm/mve/intrinsics/vstrbq_p_u8.c | 40 ++++++++++++---
.../arm/mve/intrinsics/vstrbq_s16.c | 32 +++++++++---
.../arm/mve/intrinsics/vstrbq_s32.c | 32 +++++++++---
.../gcc.target/arm/mve/intrinsics/vstrbq_s8.c | 32 +++++++++---
.../intrinsics/vstrbq_scatter_offset_p_s16.c | 40 ++++++++++++---
.../intrinsics/vstrbq_scatter_offset_p_s32.c | 40 ++++++++++++---
.../intrinsics/vstrbq_scatter_offset_p_s8.c | 40 ++++++++++++---
.../intrinsics/vstrbq_scatter_offset_p_u16.c | 40 ++++++++++++---
.../intrinsics/vstrbq_scatter_offset_p_u32.c | 40 ++++++++++++---
.../intrinsics/vstrbq_scatter_offset_p_u8.c | 40 ++++++++++++---
.../intrinsics/vstrbq_scatter_offset_s16.c | 32 +++++++++---
.../intrinsics/vstrbq_scatter_offset_s32.c | 32 +++++++++---
.../mve/intrinsics/vstrbq_scatter_offset_s8.c | 32 +++++++++---
.../intrinsics/vstrbq_scatter_offset_u16.c | 32 +++++++++---
.../intrinsics/vstrbq_scatter_offset_u32.c | 32 +++++++++---
.../mve/intrinsics/vstrbq_scatter_offset_u8.c | 32 +++++++++---
.../arm/mve/intrinsics/vstrbq_u16.c | 32 +++++++++---
.../arm/mve/intrinsics/vstrbq_u32.c | 32 +++++++++---
.../gcc.target/arm/mve/intrinsics/vstrbq_u8.c | 32 +++++++++---
.../arm/mve/intrinsics/vstrhq_f16.c | 32 +++++++++---
.../arm/mve/intrinsics/vstrhq_p_f16.c | 40 ++++++++++++---
.../arm/mve/intrinsics/vstrhq_p_s16.c | 40 ++++++++++++---
.../arm/mve/intrinsics/vstrhq_p_s32.c | 40 ++++++++++++---
.../arm/mve/intrinsics/vstrhq_p_u16.c | 40 ++++++++++++---
.../arm/mve/intrinsics/vstrhq_p_u32.c | 40 ++++++++++++---
.../arm/mve/intrinsics/vstrhq_s16.c | 32 +++++++++---
.../arm/mve/intrinsics/vstrhq_s32.c | 32 +++++++++---
.../intrinsics/vstrhq_scatter_offset_f16.c | 32 +++++++++---
.../intrinsics/vstrhq_scatter_offset_p_f16.c | 40 ++++++++++++---
.../intrinsics/vstrhq_scatter_offset_p_s16.c | 40 ++++++++++++---
.../intrinsics/vstrhq_scatter_offset_p_s32.c | 40 ++++++++++++---
.../intrinsics/vstrhq_scatter_offset_p_u16.c | 40 ++++++++++++---
.../intrinsics/vstrhq_scatter_offset_p_u32.c | 40 ++++++++++++---
.../intrinsics/vstrhq_scatter_offset_s16.c | 32 +++++++++---
.../intrinsics/vstrhq_scatter_offset_s32.c | 32 +++++++++---
.../intrinsics/vstrhq_scatter_offset_u16.c | 32 +++++++++---
.../intrinsics/vstrhq_scatter_offset_u32.c | 32 +++++++++---
.../vstrhq_scatter_shifted_offset_f16.c | 32 +++++++++---
.../vstrhq_scatter_shifted_offset_p_f16.c | 40 ++++++++++++---
.../vstrhq_scatter_shifted_offset_p_s16.c | 40 ++++++++++++---
.../vstrhq_scatter_shifted_offset_p_s32.c | 40 ++++++++++++---
.../vstrhq_scatter_shifted_offset_p_u16.c | 40 ++++++++++++---
.../vstrhq_scatter_shifted_offset_p_u32.c | 40 ++++++++++++---
.../vstrhq_scatter_shifted_offset_s16.c | 32 +++++++++---
.../vstrhq_scatter_shifted_offset_s32.c | 32 +++++++++---
.../vstrhq_scatter_shifted_offset_u16.c | 32 +++++++++---
.../vstrhq_scatter_shifted_offset_u32.c | 32 +++++++++---
.../arm/mve/intrinsics/vstrhq_u16.c | 32 +++++++++---
.../arm/mve/intrinsics/vstrhq_u32.c | 32 +++++++++---
194 files changed, 5171 insertions(+), 1035 deletions(-)
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c
index 699e40d0e3b..f0a9243a6d5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c
@@ -1,20 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16_t const * base)
+foo (float16_t const *base)
{
return vld1q_f16 (base);
}
+
+/*
+**foo1:
+** ...
+** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16_t const * base)
+foo1 (float16_t const *base)
{
return vld1q (base);
}
-/* { dg-final { scan-assembler-times "vldrh.16" 2 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c
index 86592303362..129d256dd86 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c
@@ -1,20 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32_t const * base)
+foo (float32_t const *base)
{
return vld1q_f32 (base);
}
+
+/*
+**foo1:
+** ...
+** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32_t const * base)
+foo1 (float32_t const *base)
{
return vld1q (base);
}
-/* { dg-final { scan-assembler-times "vldrw.32" 2 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c
index f4f04f534db..a95bf6c4260 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c
@@ -1,20 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int16x8_t
-foo (int16_t const * base)
+foo (int16_t const *base)
{
return vld1q_s16 (base);
}
+
+/*
+**foo1:
+** ...
+** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int16x8_t
-foo1 (int16_t const * base)
+foo1 (int16_t const *base)
{
return vld1q (base);
}
-/* { dg-final { scan-assembler-times "vldrh.16" 2 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c
index e0f66166751..bb24e52d164 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c
@@ -1,20 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32_t const * base)
+foo (int32_t const *base)
{
return vld1q_s32 (base);
}
+
+/*
+**foo1:
+** ...
+** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32_t const * base)
+foo1 (int32_t const *base)
{
return vld1q (base);
}
-/* { dg-final { scan-assembler-times "vldrw.32" 2 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c
index 1b7edead6b1..0d89c2f19cd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c
@@ -1,20 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int8x16_t
-foo (int8_t const * base)
+foo (int8_t const *base)
{
return vld1q_s8 (base);
}
+
+/*
+**foo1:
+** ...
+** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int8x16_t
-foo1 (int8_t const * base)
+foo1 (int8_t const *base)
{
return vld1q (base);
}
-/* { dg-final { scan-assembler-times "vldrb.8" 2 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c
index 50e1f5cedcb..a31baf75fed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c
@@ -1,20 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint16_t const * base)
+foo (uint16_t const *base)
{
return vld1q_u16 (base);
}
+
+/*
+**foo1:
+** ...
+** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo1 (uint16_t const * base)
+foo1 (uint16_t const *base)
{
return vld1q (base);
}
-/* { dg-final { scan-assembler-times "vldrh.16" 2 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c
index a13fe824382..7d4f858c784 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c
@@ -1,20 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32_t const * base)
+foo (uint32_t const *base)
{
return vld1q_u32 (base);
}
+
+/*
+**foo1:
+** ...
+** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32_t const * base)
+foo1 (uint32_t const *base)
{
return vld1q (base);
}
-/* { dg-final { scan-assembler-times "vldrw.32" 2 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c
index dfd1deb93f0..455ec5ce105 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c
@@ -1,20 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint8x16_t
-foo (uint8_t const * base)
+foo (uint8_t const *base)
{
return vld1q_u8 (base);
}
+
+/*
+**foo1:
+** ...
+** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint8x16_t
-foo1 (uint8_t const * base)
+foo1 (uint8_t const *base)
{
return vld1q (base);
}
-/* { dg-final { scan-assembler-times "vldrb.8" 2 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c
index 3c32e408e42..951b795fd59 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16_t const * base, mve_pred16_t p)
+foo (float16_t const *base, mve_pred16_t p)
{
return vld1q_z_f16 (base, p);
}
+
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16_t const * base, mve_pred16_t p)
+foo1 (float16_t const *base, mve_pred16_t p)
{
return vld1q_z (base, p);
}
-/* { dg-final { scan-assembler-times "vpst" 2 } } */
-/* { dg-final { scan-assembler-times "vldrht.16" 2 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c
index 3fc935c889b..4b43f0f4be3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32_t const * base, mve_pred16_t p)
+foo (float32_t const *base, mve_pred16_t p)
{
return vld1q_z_f32 (base, p);
}
+
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32_t const * base, mve_pred16_t p)
+foo1 (float32_t const *base, mve_pred16_t p)
{
return vld1q_z (base, p);
}
-/* { dg-final { scan-assembler-times "vpst" 2 } } */
-/* { dg-final { scan-assembler-times "vldrwt.32" 2 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c
index 49cc81092f3..a65c10c5fc1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int16x8_t
-foo (int16_t const * base, mve_pred16_t p)
+foo (int16_t const *base, mve_pred16_t p)
{
return vld1q_z_s16 (base, p);
}
+
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int16x8_t
-foo1 (int16_t const * base, mve_pred16_t p)
+foo1 (int16_t const *base, mve_pred16_t p)
{
return vld1q_z (base, p);
}
-/* { dg-final { scan-assembler-times "vpst" 2 } } */
-/* { dg-final { scan-assembler-times "vldrht.16" 2 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c
index ec317cd70e8..31749046fc6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32_t const * base, mve_pred16_t p)
+foo (int32_t const *base, mve_pred16_t p)
{
return vld1q_z_s32 (base, p);
}
+
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32_t const * base, mve_pred16_t p)
+foo1 (int32_t const *base, mve_pred16_t p)
{
return vld1q_z (base, p);
}
-/* { dg-final { scan-assembler-times "vpst" 2 } } */
-/* { dg-final { scan-assembler-times "vldrwt.32" 2 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c
index 538c140e78e..990522faee8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int8x16_t
-foo (int8_t const * base, mve_pred16_t p)
+foo (int8_t const *base, mve_pred16_t p)
{
return vld1q_z_s8 (base, p);
}
+
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int8x16_t
-foo1 (int8_t const * base, mve_pred16_t p)
+foo1 (int8_t const *base, mve_pred16_t p)
{
return vld1q_z (base, p);
}
-/* { dg-final { scan-assembler-times "vpst" 2 } } */
-/* { dg-final { scan-assembler-times "vldrbt.8" 2 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c
index e5e588a187e..8a41b42306c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint16_t const * base, mve_pred16_t p)
+foo (uint16_t const *base, mve_pred16_t p)
{
return vld1q_z_u16 (base, p);
}
+
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo1 (uint16_t const * base, mve_pred16_t p)
+foo1 (uint16_t const *base, mve_pred16_t p)
{
return vld1q_z (base, p);
}
-/* { dg-final { scan-assembler-times "vpst" 2 } } */
-/* { dg-final { scan-assembler-times "vldrht.16" 2 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c
index 999beefa7e8..67b200f6028 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32_t const * base, mve_pred16_t p)
+foo (uint32_t const *base, mve_pred16_t p)
{
return vld1q_z_u32 (base, p);
}
+
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32_t const * base, mve_pred16_t p)
+foo1 (uint32_t const *base, mve_pred16_t p)
{
return vld1q_z (base, p);
}
-/* { dg-final { scan-assembler-times "vpst" 2 } } */
-/* { dg-final { scan-assembler-times "vldrwt.32" 2 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c
index 172053c7142..c113a0db3e1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint8x16_t
-foo (uint8_t const * base, mve_pred16_t p)
+foo (uint8_t const *base, mve_pred16_t p)
{
return vld1q_z_u8 (base, p);
}
+
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint8x16_t
-foo1 (uint8_t const * base, mve_pred16_t p)
+foo1 (uint8_t const *base, mve_pred16_t p)
{
return vld1q_z (base, p);
}
-/* { dg-final { scan-assembler-times "vpst" 2 } } */
-/* { dg-final { scan-assembler-times "vldrbt.8" 2 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c
index db50f27bb60..e554cdab33d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c
@@ -1,24 +1,47 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
float16x8x4_t
-foo (float16_t const * addr)
+foo (float16_t const *addr)
{
return vld4q_f16 (addr);
}
-/* { dg-final { scan-assembler "vld40.16" } } */
-/* { dg-final { scan-assembler "vld41.16" } } */
-/* { dg-final { scan-assembler "vld42.16" } } */
-/* { dg-final { scan-assembler "vld43.16" } } */
+/*
+**foo1:
+** ...
+** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
float16x8x4_t
-foo1 (float16_t const * addr)
+foo1 (float16_t const *addr)
{
return vld4q (addr);
}
-/* { dg-final { scan-assembler "vld40.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c
index de3fe0e79fc..be61054d331 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c
@@ -1,24 +1,47 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
float32x4x4_t
-foo (float32_t const * addr)
+foo (float32_t const *addr)
{
return vld4q_f32 (addr);
}
-/* { dg-final { scan-assembler "vld40.32" } } */
-/* { dg-final { scan-assembler "vld41.32" } } */
-/* { dg-final { scan-assembler "vld42.32" } } */
-/* { dg-final { scan-assembler "vld43.32" } } */
+/*
+**foo1:
+** ...
+** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
float32x4x4_t
-foo1 (float32_t const * addr)
+foo1 (float32_t const *addr)
{
return vld4q (addr);
}
-/* { dg-final { scan-assembler "vld40.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c
index 41a9dd86a4f..f9cbc17da61 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c
@@ -1,24 +1,47 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
int16x8x4_t
-foo (int16_t const * addr)
+foo (int16_t const *addr)
{
return vld4q_s16 (addr);
}
-/* { dg-final { scan-assembler "vld40.16" } } */
-/* { dg-final { scan-assembler "vld41.16" } } */
-/* { dg-final { scan-assembler "vld42.16" } } */
-/* { dg-final { scan-assembler "vld43.16" } } */
+/*
+**foo1:
+** ...
+** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
int16x8x4_t
-foo1 (int16_t const * addr)
+foo1 (int16_t const *addr)
{
return vld4q (addr);
}
-/* { dg-final { scan-assembler "vld40.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c
index 6f29c1b28c0..056e26023a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c
@@ -1,24 +1,47 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
int32x4x4_t
-foo (int32_t const * addr)
+foo (int32_t const *addr)
{
return vld4q_s32 (addr);
}
-/* { dg-final { scan-assembler "vld40.32" } } */
-/* { dg-final { scan-assembler "vld41.32" } } */
-/* { dg-final { scan-assembler "vld42.32" } } */
-/* { dg-final { scan-assembler "vld43.32" } } */
+/*
+**foo1:
+** ...
+** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
int32x4x4_t
-foo1 (int32_t const * addr)
+foo1 (int32_t const *addr)
{
return vld4q (addr);
}
-/* { dg-final { scan-assembler "vld40.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c
index 7701facb55c..2bec51ab4f6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c
@@ -1,24 +1,47 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
int8x16x4_t
-foo (int8_t const * addr)
+foo (int8_t const *addr)
{
return vld4q_s8 (addr);
}
-/* { dg-final { scan-assembler "vld40.8" } } */
-/* { dg-final { scan-assembler "vld41.8" } } */
-/* { dg-final { scan-assembler "vld42.8" } } */
-/* { dg-final { scan-assembler "vld43.8" } } */
+/*
+**foo1:
+** ...
+** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
int8x16x4_t
-foo1 (int8_t const * addr)
+foo1 (int8_t const *addr)
{
return vld4q (addr);
}
-/* { dg-final { scan-assembler "vld40.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c
index 5a5e22d36d0..a2c98670174 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c
@@ -1,24 +1,47 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
uint16x8x4_t
-foo (uint16_t const * addr)
+foo (uint16_t const *addr)
{
return vld4q_u16 (addr);
}
-/* { dg-final { scan-assembler "vld40.16" } } */
-/* { dg-final { scan-assembler "vld41.16" } } */
-/* { dg-final { scan-assembler "vld42.16" } } */
-/* { dg-final { scan-assembler "vld43.16" } } */
+/*
+**foo1:
+** ...
+** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
uint16x8x4_t
-foo1 (uint16_t const * addr)
+foo1 (uint16_t const *addr)
{
return vld4q (addr);
}
-/* { dg-final { scan-assembler "vld40.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c
index e40d9b24fb4..4bbe56db205 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c
@@ -1,24 +1,47 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
uint32x4x4_t
-foo (uint32_t const * addr)
+foo (uint32_t const *addr)
{
return vld4q_u32 (addr);
}
-/* { dg-final { scan-assembler "vld40.32" } } */
-/* { dg-final { scan-assembler "vld41.32" } } */
-/* { dg-final { scan-assembler "vld42.32" } } */
-/* { dg-final { scan-assembler "vld43.32" } } */
+/*
+**foo1:
+** ...
+** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
uint32x4x4_t
-foo1 (uint32_t const * addr)
+foo1 (uint32_t const *addr)
{
return vld4q (addr);
}
-/* { dg-final { scan-assembler "vld40.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c
index 0d9abc36190..63353dba4b6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c
@@ -1,24 +1,47 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
uint8x16x4_t
-foo (uint8_t const * addr)
+foo (uint8_t const *addr)
{
return vld4q_u8 (addr);
}
-/* { dg-final { scan-assembler "vld40.8" } } */
-/* { dg-final { scan-assembler "vld41.8" } } */
-/* { dg-final { scan-assembler "vld42.8" } } */
-/* { dg-final { scan-assembler "vld43.8" } } */
+/*
+**foo1:
+** ...
+** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
uint8x16x4_t
-foo1 (uint8_t const * addr)
+foo1 (uint8_t const *addr)
{
return vld4q (addr);
}
-/* { dg-final { scan-assembler "vld40.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c
index 0f6c24dde0a..ce4255b8430 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrb.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int16x8_t
-foo (int8_t const * base, uint16x8_t offset)
+foo (int8_t const *base, uint16x8_t offset)
{
return vldrbq_gather_offset_s16 (base, offset);
}
-/* { dg-final { scan-assembler "vldrb.s16" } } */
+/*
+**foo1:
+** ...
+** vldrb.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int16x8_t
-foo1 (int8_t const * base, uint16x8_t offset)
+foo1 (int8_t const *base, uint16x8_t offset)
{
return vldrbq_gather_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrb.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c
index 4c1415d2c5f..cd5eb6b9e66 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrb.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int32x4_t
-foo (int8_t const * base, uint32x4_t offset)
+foo (int8_t const *base, uint32x4_t offset)
{
return vldrbq_gather_offset_s32 (base, offset);
}
-/* { dg-final { scan-assembler "vldrb.s32" } } */
+/*
+**foo1:
+** ...
+** vldrb.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int8_t const * base, uint32x4_t offset)
+foo1 (int8_t const *base, uint32x4_t offset)
{
return vldrbq_gather_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrb.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c
index 4108bbae3e2..5ef4a895082 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int8x16_t
-foo (int8_t const * base, uint8x16_t offset)
+foo (int8_t const *base, uint8x16_t offset)
{
return vldrbq_gather_offset_s8 (base, offset);
}
-/* { dg-final { scan-assembler "vldrb.u8" } } */
+/*
+**foo1:
+** ...
+** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int8x16_t
-foo1 (int8_t const * base, uint8x16_t offset)
+foo1 (int8_t const *base, uint8x16_t offset)
{
return vldrbq_gather_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrb.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c
index 5d5b005a8f4..cfec3c66a54 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrb.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint8_t const * base, uint16x8_t offset)
+foo (uint8_t const *base, uint16x8_t offset)
{
return vldrbq_gather_offset_u16 (base, offset);
}
-/* { dg-final { scan-assembler "vldrb.u16" } } */
+/*
+**foo1:
+** ...
+** vldrb.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo1 (uint8_t const * base, uint16x8_t offset)
+foo1 (uint8_t const *base, uint16x8_t offset)
{
return vldrbq_gather_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrb.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c
index 7c2d92b7c58..f416a03c325 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrb.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint8_t const * base, uint32x4_t offset)
+foo (uint8_t const *base, uint32x4_t offset)
{
return vldrbq_gather_offset_u32 (base, offset);
}
-/* { dg-final { scan-assembler "vldrb.u32" } } */
+/*
+**foo1:
+** ...
+** vldrb.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint8_t const * base, uint32x4_t offset)
+foo1 (uint8_t const *base, uint32x4_t offset)
{
return vldrbq_gather_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrb.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c
index 110f9db0296..e8bdd1eabb6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint8x16_t
-foo (uint8_t const * base, uint8x16_t offset)
+foo (uint8_t const *base, uint8x16_t offset)
{
return vldrbq_gather_offset_u8 (base, offset);
}
-/* { dg-final { scan-assembler "vldrb.u8" } } */
+/*
+**foo1:
+** ...
+** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint8x16_t
-foo1 (uint8_t const * base, uint8x16_t offset)
+foo1 (uint8_t const *base, uint8x16_t offset)
{
return vldrbq_gather_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrb.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c
index f0616b5ab8d..9a134609780 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int16x8_t
-foo (int8_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (int8_t const *base, uint16x8_t offset, mve_pred16_t p)
{
return vldrbq_gather_offset_z_s16 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int16x8_t
-foo1 (int8_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (int8_t const *base, uint16x8_t offset, mve_pred16_t p)
{
return vldrbq_gather_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrbt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c
index 5bf291d4ba5..f47e02076b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int32x4_t
-foo (int8_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (int8_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrbq_gather_offset_z_s32 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrbt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int8_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (int8_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrbq_gather_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrbt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c
index a3798a01b5f..e2b58b47f1d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int8x16_t
-foo (int8_t const * base, uint8x16_t offset, mve_pred16_t p)
+foo (int8_t const *base, uint8x16_t offset, mve_pred16_t p)
{
return vldrbq_gather_offset_z_s8 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrbt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int8x16_t
-foo1 (int8_t const * base, uint8x16_t offset, mve_pred16_t p)
+foo1 (int8_t const *base, uint8x16_t offset, mve_pred16_t p)
{
return vldrbq_gather_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrbt.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c
index 578bd15c66e..2a1801fc941 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint8_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (uint8_t const *base, uint16x8_t offset, mve_pred16_t p)
{
return vldrbq_gather_offset_z_u16 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrbt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo1 (uint8_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (uint8_t const *base, uint16x8_t offset, mve_pred16_t p)
{
return vldrbq_gather_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrbt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c
index a58044af176..c415fe26ba8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint8_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (uint8_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrbq_gather_offset_z_u32 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrbt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint8_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (uint8_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrbq_gather_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrbt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c
index 0e06833961b..90a19680999 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint8x16_t
-foo (uint8_t const * base, uint8x16_t offset, mve_pred16_t p)
+foo (uint8_t const *base, uint8x16_t offset, mve_pred16_t p)
{
return vldrbq_gather_offset_z_u8 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrbt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint8x16_t
-foo1 (uint8_t const * base, uint8x16_t offset, mve_pred16_t p)
+foo1 (uint8_t const *base, uint8x16_t offset, mve_pred16_t p)
{
return vldrbq_gather_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrbt.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c
index 4403092b988..c54e04dbdda 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrb.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int16x8_t
-foo (int8_t const * base)
+foo (int8_t const *base)
{
return vldrbq_s16 (base);
}
-/* { dg-final { scan-assembler "vldrb.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c
index 95ea9364ffc..1623f53d971 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrb.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int32x4_t
-foo (int8_t const * base)
+foo (int8_t const *base)
{
return vldrbq_s32 (base);
}
-/* { dg-final { scan-assembler "vldrb.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c
index ec2f2176ccf..b1c141ae287 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c
@@ -1,14 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int8x16_t
-foo (int8_t const * base)
+foo (int8_t const *base)
{
return vldrbq_s8 (base);
}
-/* { dg-final { scan-assembler-times "vldrb.8" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c
index 2fb297f92ad..203e2e9de83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrb.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint8_t const * base)
+foo (uint8_t const *base)
{
return vldrbq_u16 (base);
}
-/* { dg-final { scan-assembler "vldrb.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c
index dc555c1be2d..2005c3a2bbf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrb.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint8_t const * base)
+foo (uint8_t const *base)
{
return vldrbq_u32 (base);
}
-/* { dg-final { scan-assembler "vldrb.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c
index d07b472a4ff..b4c109eb147 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c
@@ -1,14 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint8x16_t
-foo (uint8_t const * base)
+foo (uint8_t const *base)
{
return vldrbq_u8 (base);
}
-/* { dg-final { scan-assembler-times "vldrb.8" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c
index 8bd08ab5cff..813f6a31a25 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c
@@ -1,13 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int16x8_t
-foo (int8_t const * base, mve_pred16_t p)
+foo (int8_t const *base, mve_pred16_t p)
{
return vldrbq_z_s16 (base, p);
}
-/* { dg-final { scan-assembler "vldrbt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c
index 0309ff4111b..10e1dbf6ad9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c
@@ -1,13 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int32x4_t
-foo (int8_t const * base, mve_pred16_t p)
+foo (int8_t const *base, mve_pred16_t p)
{
return vldrbq_z_s32 (base, p);
}
-/* { dg-final { scan-assembler "vldrbt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c
index aed3c910063..de361d4c9a0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c
@@ -1,15 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int8x16_t
-foo (int8_t const * base, mve_pred16_t p)
+foo (int8_t const *base, mve_pred16_t p)
{
return vldrbq_z_s8 (base, p);
}
-/* { dg-final { scan-assembler-times "vpst" 1 } } */
-/* { dg-final { scan-assembler-times "vldrbt.8" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c
index adcb0cfa2ae..ba4401045e7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c
@@ -1,13 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint8_t const * base, mve_pred16_t p)
+foo (uint8_t const *base, mve_pred16_t p)
{
return vldrbq_z_u16 (base, p);
}
-/* { dg-final { scan-assembler "vldrbt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c
index 6b7bce60d62..adc88a59a71 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c
@@ -1,13 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint8_t const * base, mve_pred16_t p)
+foo (uint8_t const *base, mve_pred16_t p)
{
return vldrbq_z_u32 (base, p);
}
-/* { dg-final { scan-assembler "vldrbt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c
index 54c61e74454..b13d9fb426f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c
@@ -1,15 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint8x16_t
-foo (uint8_t const * base, mve_pred16_t p)
+foo (uint8_t const *base, mve_pred16_t p)
{
return vldrbq_z_u8 (base, p);
}
-/* { dg-final { scan-assembler-times "vpst" 1 } } */
-/* { dg-final { scan-assembler-times "vldrbt.8" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c
index 6499f930c40..3539c1e40ba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
int64x2_t
foo (uint64x2_t addr)
{
- return vldrdq_gather_base_s64 (addr, 8);
+ return vldrdq_gather_base_s64 (addr, 0);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vldrd.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c
index 9a11638a261..2245df61a4e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
uint64x2_t
foo (uint64x2_t addr)
{
- return vldrdq_gather_base_u64 (addr, 8);
+ return vldrdq_gather_base_u64 (addr, 0);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vldrd.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c
index a9b1f81b62d..e3fd7f16a31 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c
@@ -1,16 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
int64x2_t
-foo (uint64x2_t * addr)
+foo (uint64x2_t *addr)
{
- return vldrdq_gather_base_wb_s64 (addr, 8);
+ return vldrdq_gather_base_wb_s64 (addr, 0);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c
index e32a06695ae..161cf00b65e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c
@@ -1,16 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
uint64x2_t
-foo (uint64x2_t * addr)
+foo (uint64x2_t *addr)
{
- return vldrdq_gather_base_wb_u64 (addr, 8);
+ return vldrdq_gather_base_wb_u64 (addr, 0);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c
index bb06cf88e32..0716baa635a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c
@@ -1,15 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
#include "arm_mve.h"
-int64x2_t foo (uint64x2_t * addr, mve_pred16_t p)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
+int64x2_t
+foo (uint64x2_t *addr, mve_pred16_t p)
{
- return vldrdq_gather_base_wb_z_s64 (addr, 1016, p);
+ return vldrdq_gather_base_wb_z_s64 (addr, 0, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c
index 558115d49ef..242c7c06e27 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c
@@ -1,15 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
#include "arm_mve.h"
-uint64x2_t foo (uint64x2_t * addr, mve_pred16_t p)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
+uint64x2_t
+foo (uint64x2_t *addr, mve_pred16_t p)
{
- return vldrdq_gather_base_wb_z_u64 (addr, 8, p);
+ return vldrdq_gather_base_wb_z_u64 (addr, 0, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c
index d7455b49206..d451f4e693f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c
@@ -1,13 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
int64x2_t
foo (uint64x2_t addr, mve_pred16_t p)
{
- return vldrdq_gather_base_z_s64 (addr, 8, p);
+ return vldrdq_gather_base_z_s64 (addr, 0, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vldrdt.u64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c
index 07f72d422b4..508db3ca538 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c
@@ -1,13 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
uint64x2_t
foo (uint64x2_t addr, mve_pred16_t p)
{
- return vldrdq_gather_base_z_u64 (addr, 8, p);
+ return vldrdq_gather_base_z_u64 (addr, 0, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vldrdt.u64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c
index 1d2d904efc4..9431491f3fd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int64x2_t
-foo (int64_t const * base, uint64x2_t offset)
+foo (int64_t const *base, uint64x2_t offset)
{
return vldrdq_gather_offset_s64 (base, offset);
}
-/* { dg-final { scan-assembler "vldrd.u64" } } */
+/*
+**foo1:
+** ...
+** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int64x2_t
-foo1 (int64_t const * base, uint64x2_t offset)
+foo1 (int64_t const *base, uint64x2_t offset)
{
return vldrdq_gather_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrd.u64" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c
index 49a3b134d2f..11c0872f5a7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint64x2_t
-foo (uint64_t const * base, uint64x2_t offset)
+foo (uint64_t const *base, uint64x2_t offset)
{
return vldrdq_gather_offset_u64 (base, offset);
}
-/* { dg-final { scan-assembler "vldrd.u64" } } */
+/*
+**foo1:
+** ...
+** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint64x2_t
-foo1 (uint64_t const * base, uint64x2_t offset)
+foo1 (uint64_t const *base, uint64x2_t offset)
{
return vldrdq_gather_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrd.u64" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c
index 1ff5f2acd1b..f474cbef788 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int64x2_t
-foo (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo (int64_t const *base, uint64x2_t offset, mve_pred16_t p)
{
return vldrdq_gather_offset_z_s64 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrdt.u64" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int64x2_t
-foo1 (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo1 (int64_t const *base, uint64x2_t offset, mve_pred16_t p)
{
return vldrdq_gather_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrdt.u64" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c
index 63b2254d171..19136d7f451 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint64x2_t
-foo (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo (uint64_t const *base, uint64x2_t offset, mve_pred16_t p)
{
return vldrdq_gather_offset_z_u64 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrdt.u64" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint64x2_t
-foo1 (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo1 (uint64_t const *base, uint64x2_t offset, mve_pred16_t p)
{
return vldrdq_gather_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrdt.u64" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c
index 4feb9c06fcd..ad11d8fa5cb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
int64x2_t
-foo (int64_t const * base, uint64x2_t offset)
+foo (int64_t const *base, uint64x2_t offset)
{
return vldrdq_gather_shifted_offset_s64 (base, offset);
}
-/* { dg-final { scan-assembler "vldrd.u64" } } */
+/*
+**foo1:
+** ...
+** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
int64x2_t
-foo1 (int64_t const * base, uint64x2_t offset)
+foo1 (int64_t const *base, uint64x2_t offset)
{
return vldrdq_gather_shifted_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrd.u64" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c
index 999735039c8..a466494974b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
uint64x2_t
-foo (uint64_t const * base, uint64x2_t offset)
+foo (uint64_t const *base, uint64x2_t offset)
{
return vldrdq_gather_shifted_offset_u64 (base, offset);
}
-/* { dg-final { scan-assembler "vldrd.u64" } } */
+/*
+**foo1:
+** ...
+** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
uint64x2_t
-foo1 (uint64_t const * base, uint64x2_t offset)
+foo1 (uint64_t const *base, uint64x2_t offset)
{
return vldrdq_gather_shifted_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrd.u64" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c
index 77303a47a08..3555105d09e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
int64x2_t
-foo (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo (int64_t const *base, uint64x2_t offset, mve_pred16_t p)
{
return vldrdq_gather_shifted_offset_z_s64 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrdt.u64" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
int64x2_t
-foo1 (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo1 (int64_t const *base, uint64x2_t offset, mve_pred16_t p)
{
return vldrdq_gather_shifted_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrdt.u64" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c
index 0273b242031..f7cfbfcddb3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
uint64x2_t
-foo (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo (uint64_t const *base, uint64x2_t offset, mve_pred16_t p)
{
return vldrdq_gather_shifted_offset_z_u64 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrdt.u64" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
uint64x2_t
-foo1 (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo1 (uint64_t const *base, uint64x2_t offset, mve_pred16_t p)
{
return vldrdq_gather_shifted_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrdt.u64" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c
index 05bef418d82..87c746f4ad7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c
@@ -1,14 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16_t const * base)
+foo (float16_t const *base)
{
return vldrhq_f16 (base);
}
-/* { dg-final { scan-assembler-times "vldrh.16" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c
index 525e54c72f5..287276e41f9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16_t const * base, uint16x8_t offset)
+foo (float16_t const *base, uint16x8_t offset)
{
return vldrhq_gather_offset_f16 (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.f16" } } */
+/*
+**foo1:
+** ...
+** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16_t const * base, uint16x8_t offset)
+foo1 (float16_t const *base, uint16x8_t offset)
{
return vldrhq_gather_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c
index 47ef03445b4..e2493a62b3a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int16x8_t
-foo (int16_t const * base, uint16x8_t offset)
+foo (int16_t const *base, uint16x8_t offset)
{
return vldrhq_gather_offset_s16 (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.u16" } } */
+/*
+**foo1:
+** ...
+** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int16x8_t
-foo1 (int16_t const * base, uint16x8_t offset)
+foo1 (int16_t const *base, uint16x8_t offset)
{
return vldrhq_gather_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c
index 39379aaedd3..5d1e348cc86 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int32x4_t
-foo (int16_t const * base, uint32x4_t offset)
+foo (int16_t const *base, uint32x4_t offset)
{
return vldrhq_gather_offset_s32 (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.s32" } } */
+/*
+**foo1:
+** ...
+** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int16_t const * base, uint32x4_t offset)
+foo1 (int16_t const *base, uint32x4_t offset)
{
return vldrhq_gather_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c
index fa345e24b48..6d5f6f877dc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint16_t const * base, uint16x8_t offset)
+foo (uint16_t const *base, uint16x8_t offset)
{
return vldrhq_gather_offset_u16 (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.u16" } } */
+/*
+**foo1:
+** ...
+** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo1 (uint16_t const * base, uint16x8_t offset)
+foo1 (uint16_t const *base, uint16x8_t offset)
{
return vldrhq_gather_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c
index b888660dc37..c39afbe6119 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint16_t const * base, uint32x4_t offset)
+foo (uint16_t const *base, uint32x4_t offset)
{
return vldrhq_gather_offset_u32 (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.u32" } } */
+/*
+**foo1:
+** ...
+** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint16_t const * base, uint32x4_t offset)
+foo1 (uint16_t const *base, uint32x4_t offset)
{
return vldrhq_gather_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c
index 7ee84232f04..53c673e3644 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (float16_t const *base, uint16x8_t offset, mve_pred16_t p)
{
return vldrhq_gather_offset_z_f16 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (float16_t const *base, uint16x8_t offset, mve_pred16_t p)
{
return vldrhq_gather_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c
index 9b354fad50d..1e68a77824e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int16x8_t
-foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (int16_t const *base, uint16x8_t offset, mve_pred16_t p)
{
return vldrhq_gather_offset_z_s16 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int16x8_t
-foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (int16_t const *base, uint16x8_t offset, mve_pred16_t p)
{
return vldrhq_gather_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c
index 0e252291944..06c208f31c5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int32x4_t
-foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (int16_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrhq_gather_offset_z_s32 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (int16_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrhq_gather_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c
index 763e33d90bb..f50f026b00e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (uint16_t const *base, uint16x8_t offset, mve_pred16_t p)
{
return vldrhq_gather_offset_z_u16 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (uint16_t const *base, uint16x8_t offset, mve_pred16_t p)
{
return vldrhq_gather_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c
index 36baa252aa4..eff32dc6718 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (uint16_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrhq_gather_offset_z_u32 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (uint16_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrhq_gather_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c
index 843904a7041..f8468be41fa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16_t const * base, uint16x8_t offset)
+foo (float16_t const *base, uint16x8_t offset)
{
return vldrhq_gather_shifted_offset_f16 (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.f16" } } */
+/*
+**foo1:
+** ...
+** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16_t const * base, uint16x8_t offset)
+foo1 (float16_t const *base, uint16x8_t offset)
{
return vldrhq_gather_shifted_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c
index 6d013c835b5..ac2491ea143 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
int16x8_t
-foo (int16_t const * base, uint16x8_t offset)
+foo (int16_t const *base, uint16x8_t offset)
{
return vldrhq_gather_shifted_offset_s16 (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.u16" } } */
+/*
+**foo1:
+** ...
+** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
int16x8_t
-foo1 (int16_t const * base, uint16x8_t offset)
+foo1 (int16_t const *base, uint16x8_t offset)
{
return vldrhq_gather_shifted_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c
index 5ec8e8c1dc8..6919b3a3cc2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
int32x4_t
-foo (int16_t const * base, uint32x4_t offset)
+foo (int16_t const *base, uint32x4_t offset)
{
return vldrhq_gather_shifted_offset_s32 (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.s32" } } */
+/*
+**foo1:
+** ...
+** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int16_t const * base, uint32x4_t offset)
+foo1 (int16_t const *base, uint32x4_t offset)
{
return vldrhq_gather_shifted_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c
index fa5f3d04548..7e8fdf3799d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint16_t const * base, uint16x8_t offset)
+foo (uint16_t const *base, uint16x8_t offset)
{
return vldrhq_gather_shifted_offset_u16 (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.u16" } } */
+/*
+**foo1:
+** ...
+** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo1 (uint16_t const * base, uint16x8_t offset)
+foo1 (uint16_t const *base, uint16x8_t offset)
{
return vldrhq_gather_shifted_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c
index 227b18d7864..de2d22d985d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint16_t const * base, uint32x4_t offset)
+foo (uint16_t const *base, uint32x4_t offset)
{
return vldrhq_gather_shifted_offset_u32 (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.u32" } } */
+/*
+**foo1:
+** ...
+** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint16_t const * base, uint32x4_t offset)
+foo1 (uint16_t const *base, uint32x4_t offset)
{
return vldrhq_gather_shifted_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrh.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c
index cae37837c7e..a55ada003ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (float16_t const *base, uint16x8_t offset, mve_pred16_t p)
{
return vldrhq_gather_shifted_offset_z_f16 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (float16_t const *base, uint16x8_t offset, mve_pred16_t p)
{
return vldrhq_gather_shifted_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c
index 1aff290a6b0..ee57d77e3db 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
int16x8_t
-foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (int16_t const *base, uint16x8_t offset, mve_pred16_t p)
{
return vldrhq_gather_shifted_offset_z_s16 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
int16x8_t
-foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (int16_t const *base, uint16x8_t offset, mve_pred16_t p)
{
return vldrhq_gather_shifted_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c
index 92ee073adf9..9f8963f56bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
int32x4_t
-foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (int16_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrhq_gather_shifted_offset_z_s32 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (int16_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrhq_gather_shifted_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c
index 792510d3639..90be7020ac2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (uint16_t const *base, uint16x8_t offset, mve_pred16_t p)
{
return vldrhq_gather_shifted_offset_z_u16 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (uint16_t const *base, uint16x8_t offset, mve_pred16_t p)
{
return vldrhq_gather_shifted_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c
index 8ae845418e8..0ff6d021b51 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (uint16_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrhq_gather_shifted_offset_z_u32 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (uint16_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrhq_gather_shifted_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrht.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c
index 7c977b6a699..107ce22856b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c
@@ -1,14 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int16x8_t
-foo (int16_t const * base)
+foo (int16_t const *base)
{
return vldrhq_s16 (base);
}
-/* { dg-final { scan-assembler-times "vldrh.16" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c
index 229b52163fa..5cc864c38e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c
@@ -1,14 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int32x4_t
-foo (int16_t const * base)
+foo (int16_t const *base)
{
return vldrhq_s32 (base);
}
-/* { dg-final { scan-assembler-times "vldrh.s32" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c
index 07f6d9e3944..12f807da03b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c
@@ -1,14 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint16_t const * base)
+foo (uint16_t const *base)
{
return vldrhq_u16 (base);
}
-/* { dg-final { scan-assembler-times "vldrh.16" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c
index cd24f01831f..5d4f34f9789 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c
@@ -1,14 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint16_t const * base)
+foo (uint16_t const *base)
{
return vldrhq_u32 (base);
}
-/* { dg-final { scan-assembler-times "vldrh.u32" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c
index dd0fc9c7b73..582061bbab3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c
@@ -1,15 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16_t const * base, mve_pred16_t p)
+foo (float16_t const *base, mve_pred16_t p)
{
return vldrhq_z_f16 (base, p);
}
-/* { dg-final { scan-assembler-times "vpst" 1 } } */
-/* { dg-final { scan-assembler-times "vldrht.16" 1 } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c
index 36d3458d95c..dc32460ccdd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c
@@ -1,15 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int16x8_t
-foo (int16_t const * base, mve_pred16_t p)
+foo (int16_t const *base, mve_pred16_t p)
{
return vldrhq_z_s16 (base, p);
}
-/* { dg-final { scan-assembler-times "vpst" 1 } } */
-/* { dg-final { scan-assembler-times "vldrht.16" 1 } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c
index 9c67b479be7..15dd77cb36c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c
@@ -1,15 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int32x4_t
-foo (int16_t const * base, mve_pred16_t p)
+foo (int16_t const *base, mve_pred16_t p)
{
return vldrhq_z_s32 (base, p);
}
-/* { dg-final { scan-assembler-times "vpst" 1 } } */
-/* { dg-final { scan-assembler-times "vldrht.s32" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c
index 26354b5971a..91ab2caf1c6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c
@@ -1,15 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint16_t const * base, mve_pred16_t p)
+foo (uint16_t const *base, mve_pred16_t p)
{
return vldrhq_z_u16 (base, p);
}
-/* { dg-final { scan-assembler-times "vpst" 1 } } */
-/* { dg-final { scan-assembler-times "vldrht.16" 1 } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c
index 948fe5ee5b4..1682ec1987a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c
@@ -1,15 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint16_t const * base, mve_pred16_t p)
+foo (uint16_t const *base, mve_pred16_t p)
{
return vldrhq_z_u32 (base, p);
}
-/* { dg-final { scan-assembler-times "vpst" 1 } } */
-/* { dg-final { scan-assembler-times "vldrht.u32" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c
index 143079aa23f..9cf47332b38 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c
@@ -1,14 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32_t const * base)
+foo (float32_t const *base)
{
return vldrwq_f32 (base);
}
-/* { dg-final { scan-assembler-times "vldrw.32" 1 } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c
index 5e0faaad8dd..c3f052efbc6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
float32x4_t
foo (uint32x4_t addr)
{
- return vldrwq_gather_base_f32 (addr, 4);
+ return vldrwq_gather_base_f32 (addr, 0);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vldrw.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c
index 8ca44199e3e..f2dbcfb9f6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
int32x4_t
foo (uint32x4_t addr)
{
- return vldrwq_gather_base_s32 (addr, 4);
+ return vldrwq_gather_base_s32 (addr, 0);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vldrw.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c
index 3c3e90f1c0a..0926689805f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t addr)
{
- return vldrwq_gather_base_u32 (addr, 4);
+ return vldrwq_gather_base_u32 (addr, 0);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vldrw.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c
index 8e2994f75d7..f9cd0a3ffe0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c
@@ -1,16 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
float32x4_t
-foo (uint32x4_t * addr)
+foo (uint32x4_t *addr)
{
- return vldrwq_gather_base_wb_f32 (addr, 8);
+ return vldrwq_gather_base_wb_f32 (addr, 0);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c
index e5054738b75..b8f16969a31 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c
@@ -1,16 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
int32x4_t
-foo (uint32x4_t * addr)
+foo (uint32x4_t *addr)
{
- return vldrwq_gather_base_wb_s32 (addr, 8);
+ return vldrwq_gather_base_wb_s32 (addr, 0);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c
index 7f39414143b..387d0115f46 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c
@@ -1,16 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t * addr)
+foo (uint32x4_t *addr)
{
- return vldrwq_gather_base_wb_u32 (addr, 8);
+ return vldrwq_gather_base_wb_u32 (addr, 0);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c
index 1e57ca40739..bea7ecdee83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c
@@ -1,18 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
float32x4_t
-foo (uint32x4_t * addr, mve_pred16_t p)
+foo (uint32x4_t *addr, mve_pred16_t p)
{
- return vldrwq_gather_base_wb_z_f32 (addr, 8, p);
+ return vldrwq_gather_base_wb_z_f32 (addr, 0, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c
index f8d77fdfd5b..4469ac14a0a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c
@@ -1,18 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
int32x4_t
-foo (uint32x4_t * addr, mve_pred16_t p)
+foo (uint32x4_t *addr, mve_pred16_t p)
{
- return vldrwq_gather_base_wb_z_s32 (addr, 8, p);
+ return vldrwq_gather_base_wb_z_s32 (addr, 0, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c
index 8a0e109c70c..9d4d81b3afe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c
@@ -1,18 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t * addr, mve_pred16_t p)
+foo (uint32x4_t *addr, mve_pred16_t p)
{
- return vldrwq_gather_base_wb_z_u32 (addr, 8, p);
+ return vldrwq_gather_base_wb_z_u32 (addr, 0, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c
index 81aac523728..905000a31a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c
@@ -1,13 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
float32x4_t
foo (uint32x4_t addr, mve_pred16_t p)
{
- return vldrwq_gather_base_z_f32 (addr, 4, p);
+ return vldrwq_gather_base_z_f32 (addr, 0, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vldrwt.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c
index fec49bbde06..3ee6a219b80 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c
@@ -1,13 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
int32x4_t
foo (uint32x4_t addr, mve_pred16_t p)
{
- return vldrwq_gather_base_z_s32 (addr, 4, p);
+ return vldrwq_gather_base_z_s32 (addr, 0, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vldrwt.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c
index b64a11d6620..488adf58b78 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c
@@ -1,13 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t addr, mve_pred16_t p)
{
- return vldrwq_gather_base_z_u32 (addr, 4, p);
+ return vldrwq_gather_base_z_u32 (addr, 0, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vldrwt.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c
index 6a4ea041137..a513452a12d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32_t const * base, uint32x4_t offset)
+foo (float32_t const *base, uint32x4_t offset)
{
return vldrwq_gather_offset_f32 (base, offset);
}
-/* { dg-final { scan-assembler "vldrw.u32" } } */
+/*
+**foo1:
+** ...
+** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32_t const * base, uint32x4_t offset)
+foo1 (float32_t const *base, uint32x4_t offset)
{
return vldrwq_gather_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrw.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c
index ee15fa4a0b0..57ad6583153 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32_t const * base, uint32x4_t offset)
+foo (int32_t const *base, uint32x4_t offset)
{
return vldrwq_gather_offset_s32 (base, offset);
}
-/* { dg-final { scan-assembler "vldrw.u32" } } */
+/*
+**foo1:
+** ...
+** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32_t const * base, uint32x4_t offset)
+foo1 (int32_t const *base, uint32x4_t offset)
{
return vldrwq_gather_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrw.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c
index d344779058f..30fc36c6f97 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32_t const * base, uint32x4_t offset)
+foo (uint32_t const *base, uint32x4_t offset)
{
return vldrwq_gather_offset_u32 (base, offset);
}
-/* { dg-final { scan-assembler "vldrw.u32" } } */
+/*
+**foo1:
+** ...
+** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32_t const * base, uint32x4_t offset)
+foo1 (uint32_t const *base, uint32x4_t offset)
{
return vldrwq_gather_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrw.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c
index 93253119418..1f84edcdb8e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (float32_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_offset_z_f32 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrwt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (float32_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrwt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c
index 4537427bef3..3fe5a986cc3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (int32_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_offset_z_s32 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrwt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (int32_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrwt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c
index e59c4c996bf..087e5d0ce1e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (uint32_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_offset_z_u32 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrwt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (uint32_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrwt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c
index 1ba2cb0ccde..bed16f5fa72 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32_t const * base, uint32x4_t offset)
+foo (float32_t const *base, uint32x4_t offset)
{
return vldrwq_gather_shifted_offset_f32 (base, offset);
}
-/* { dg-final { scan-assembler "vldrw.u32" } } */
+/*
+**foo1:
+** ...
+** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32_t const * base, uint32x4_t offset)
+foo1 (float32_t const *base, uint32x4_t offset)
{
return vldrwq_gather_shifted_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrw.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c
index 39d976bb676..e6c589020f3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32_t const * base, uint32x4_t offset)
+foo (int32_t const *base, uint32x4_t offset)
{
return vldrwq_gather_shifted_offset_s32 (base, offset);
}
-/* { dg-final { scan-assembler "vldrw.u32" } } */
+/*
+**foo1:
+** ...
+** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32_t const * base, uint32x4_t offset)
+foo1 (int32_t const *base, uint32x4_t offset)
{
return vldrwq_gather_shifted_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrw.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c
index 971f482dfff..8e287da0dbf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32_t const * base, uint32x4_t offset)
+foo (uint32_t const *base, uint32x4_t offset)
{
return vldrwq_gather_shifted_offset_u32 (base, offset);
}
-/* { dg-final { scan-assembler "vldrw.u32" } } */
+/*
+**foo1:
+** ...
+** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32_t const * base, uint32x4_t offset)
+foo1 (uint32_t const *base, uint32x4_t offset)
{
return vldrwq_gather_shifted_offset (base, offset);
}
-/* { dg-final { scan-assembler "vldrw.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c
index e4110cd50aa..f69d67fd2aa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (float32_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_shifted_offset_z_f32 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrwt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (float32_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_shifted_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrwt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c
index 71dd8a757ce..3aff6de03b6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (int32_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_shifted_offset_z_s32 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrwt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (int32_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_shifted_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrwt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c
index f95d6f0f708..ed8873d0c53 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (uint32_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_shifted_offset_z_u32 (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrwt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (uint32_t const *base, uint32x4_t offset, mve_pred16_t p)
{
return vldrwq_gather_shifted_offset_z (base, offset, p);
}
-/* { dg-final { scan-assembler "vldrwt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c
index 860dd324d25..87c3ac9f9d2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c
@@ -1,14 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32_t const * base)
+foo (int32_t const *base)
{
return vldrwq_s32 (base);
}
-/* { dg-final { scan-assembler-times "vldrw.32" 1 } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c
index 513ed49fb6e..5b560c534a1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c
@@ -1,14 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32_t const * base)
+foo (uint32_t const *base)
{
return vldrwq_u32 (base);
}
-/* { dg-final { scan-assembler-times "vldrw.32" 1 } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c
index 3e0a6a60bcf..14a61fcfbd4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c
@@ -1,15 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32_t const * base, mve_pred16_t p)
+foo (float32_t const *base, mve_pred16_t p)
{
return vldrwq_z_f32 (base, p);
}
-/* { dg-final { scan-assembler-times "vpst" 1 } } */
-/* { dg-final { scan-assembler-times "vldrwt.32" 1 } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c
index 82b914885b5..5c90707becc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c
@@ -1,15 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32_t const * base, mve_pred16_t p)
+foo (int32_t const *base, mve_pred16_t p)
{
return vldrwq_z_s32 (base, p);
}
-/* { dg-final { scan-assembler-times "vpst" 1 } } */
-/* { dg-final { scan-assembler-times "vldrwt.32" 1 } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c
index 6a66e167881..16b50335fe7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c
@@ -1,15 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32_t const * base, mve_pred16_t p)
+foo (uint32_t const *base, mve_pred16_t p)
{
return vldrwq_z_u32 (base, p);
}
-/* { dg-final { scan-assembler-times "vpst" 1 } } */
-/* { dg-final { scan-assembler-times "vldrwt.32" 1 } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c
index 64650e26bcb..5180667658e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c
@@ -1,22 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (float16_t * addr, float16x8x2_t value)
+foo (float16_t *addr, float16x8x2_t value)
{
- vst2q_f16 (addr, value);
+ return vst2q_f16 (addr, value);
}
-/* { dg-final { scan-assembler "vst20.16" } } */
-/* { dg-final { scan-assembler "vst21.16" } } */
+/*
+**foo1:
+** ...
+** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (float16_t * addr, float16x8x2_t value)
+foo1 (float16_t *addr, float16x8x2_t value)
{
- vst2q (addr, value);
+ return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vst20.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c
index 8840afb867d..3e6f5b0ed75 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c
@@ -1,22 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (float32_t * addr, float32x4x2_t value)
+foo (float32_t *addr, float32x4x2_t value)
{
- vst2q_f32 (addr, value);
+ return vst2q_f32 (addr, value);
}
-/* { dg-final { scan-assembler "vst20.32" } } */
-/* { dg-final { scan-assembler "vst21.32" } } */
+/*
+**foo1:
+** ...
+** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (float32_t * addr, float32x4x2_t value)
+foo1 (float32_t *addr, float32x4x2_t value)
{
- vst2q (addr, value);
+ return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vst20.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c
index 15182c5eee0..1c939317779 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c
@@ -1,22 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int16_t * addr, int16x8x2_t value)
+foo (int16_t *addr, int16x8x2_t value)
{
- vst2q_s16 (addr, value);
+ return vst2q_s16 (addr, value);
}
-/* { dg-final { scan-assembler "vst20.16" } } */
-/* { dg-final { scan-assembler "vst21.16" } } */
+/*
+**foo1:
+** ...
+** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int16_t * addr, int16x8x2_t value)
+foo1 (int16_t *addr, int16x8x2_t value)
{
- vst2q (addr, value);
+ return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vst20.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c
index 11c92463ae4..28c8e078942 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c
@@ -1,22 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int32_t * addr, int32x4x2_t value)
+foo (int32_t *addr, int32x4x2_t value)
{
- vst2q_s32 (addr, value);
+ return vst2q_s32 (addr, value);
}
-/* { dg-final { scan-assembler "vst20.32" } } */
-/* { dg-final { scan-assembler "vst21.32" } } */
+/*
+**foo1:
+** ...
+** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int32_t * addr, int32x4x2_t value)
+foo1 (int32_t *addr, int32x4x2_t value)
{
- vst2q (addr, value);
+ return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vst20.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c
index 90257ae5dae..e882c01bd63 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c
@@ -1,22 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int8_t * addr, int8x16x2_t value)
+foo (int8_t *addr, int8x16x2_t value)
{
- vst2q_s8 (addr, value);
+ return vst2q_s8 (addr, value);
}
-/* { dg-final { scan-assembler "vst20.8" } } */
-/* { dg-final { scan-assembler "vst21.8" } } */
+/*
+**foo1:
+** ...
+** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int8_t * addr, int8x16x2_t value)
+foo1 (int8_t *addr, int8x16x2_t value)
{
- vst2q (addr, value);
+ return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vst20.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c
index a8a7c49757a..0cfbd6b9902 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c
@@ -1,22 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint16_t * addr, uint16x8x2_t value)
+foo (uint16_t *addr, uint16x8x2_t value)
{
- vst2q_u16 (addr, value);
+ return vst2q_u16 (addr, value);
}
-/* { dg-final { scan-assembler "vst20.16" } } */
-/* { dg-final { scan-assembler "vst21.16" } } */
+/*
+**foo1:
+** ...
+** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint16_t * addr, uint16x8x2_t value)
+foo1 (uint16_t *addr, uint16x8x2_t value)
{
- vst2q (addr, value);
+ return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vst20.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c
index b5d78180995..ea46a5969d0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c
@@ -1,22 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint32_t * addr, uint32x4x2_t value)
+foo (uint32_t *addr, uint32x4x2_t value)
{
- vst2q_u32 (addr, value);
+ return vst2q_u32 (addr, value);
}
-/* { dg-final { scan-assembler "vst20.32" } } */
-/* { dg-final { scan-assembler "vst21.32" } } */
+/*
+**foo1:
+** ...
+** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint32_t * addr, uint32x4x2_t value)
+foo1 (uint32_t *addr, uint32x4x2_t value)
{
- vst2q (addr, value);
+ return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vst20.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c
index 4e7d6fea7ed..895c2ccf425 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c
@@ -1,22 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint8_t * addr, uint8x16x2_t value)
+foo (uint8_t *addr, uint8x16x2_t value)
{
- vst2q_u8 (addr, value);
+ return vst2q_u8 (addr, value);
}
-/* { dg-final { scan-assembler "vst20.8" } } */
-/* { dg-final { scan-assembler "vst21.8" } } */
+/*
+**foo1:
+** ...
+** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint8_t * addr, uint8x16x2_t value)
+foo1 (uint8_t *addr, uint8x16x2_t value)
{
- vst2q (addr, value);
+ return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vst20.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c
index 0da66894e2c..94066089f58 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c
@@ -1,37 +1,47 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
void
-foo (float16_t * addr, float16x8x4_t value)
+foo (float16_t *addr, float16x8x4_t value)
{
- vst4q_f16 (addr, value);
+ return vst4q_f16 (addr, value);
}
-/* { dg-final { scan-assembler "vst40.16" } } */
-/* { dg-final { scan-assembler "vst41.16" } } */
-/* { dg-final { scan-assembler "vst42.16" } } */
-/* { dg-final { scan-assembler "vst43.16" } } */
+/*
+**foo1:
+** ...
+** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
void
-foo1 (float16_t * addr, float16x8x4_t value)
+foo1 (float16_t *addr, float16x8x4_t value)
{
- vst4q (addr, value);
+ return vst4q (addr, value);
}
-/* { dg-final { scan-assembler "vst40.16" } } */
-/* { dg-final { scan-assembler "vst41.16" } } */
-/* { dg-final { scan-assembler "vst42.16" } } */
-/* { dg-final { scan-assembler "vst43.16" } } */
-
-void
-foo2 (float16_t * addr, float16x8x4_t value)
-{
- vst4q_f16 (addr, value);
- addr += 32;
- vst4q_f16 (addr, value);
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c
index c1614bd10fc..0150ba7ca56 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c
@@ -1,37 +1,47 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
void
-foo (float32_t * addr, float32x4x4_t value)
+foo (float32_t *addr, float32x4x4_t value)
{
- vst4q_f32 (addr, value);
+ return vst4q_f32 (addr, value);
}
-/* { dg-final { scan-assembler "vst40.32" } } */
-/* { dg-final { scan-assembler "vst41.32" } } */
-/* { dg-final { scan-assembler "vst42.32" } } */
-/* { dg-final { scan-assembler "vst43.32" } } */
+/*
+**foo1:
+** ...
+** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
void
-foo1 (float32_t * addr, float32x4x4_t value)
+foo1 (float32_t *addr, float32x4x4_t value)
{
- vst4q (addr, value);
+ return vst4q (addr, value);
}
-/* { dg-final { scan-assembler "vst40.32" } } */
-/* { dg-final { scan-assembler "vst41.32" } } */
-/* { dg-final { scan-assembler "vst42.32" } } */
-/* { dg-final { scan-assembler "vst43.32" } } */
-
-void
-foo2 (float32_t * addr, float32x4x4_t value)
-{
- vst4q_f32 (addr, value);
- addr += 16;
- vst4q_f32 (addr, value);
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c
index e1250449bee..8c9df15b3c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c
@@ -1,37 +1,47 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
void
-foo (int16_t * addr, int16x8x4_t value)
+foo (int16_t *addr, int16x8x4_t value)
{
- vst4q_s16 (addr, value);
+ return vst4q_s16 (addr, value);
}
-/* { dg-final { scan-assembler "vst40.16" } } */
-/* { dg-final { scan-assembler "vst41.16" } } */
-/* { dg-final { scan-assembler "vst42.16" } } */
-/* { dg-final { scan-assembler "vst43.16" } } */
+/*
+**foo1:
+** ...
+** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
void
-foo1 (int16_t * addr, int16x8x4_t value)
+foo1 (int16_t *addr, int16x8x4_t value)
{
- vst4q (addr, value);
+ return vst4q (addr, value);
}
-/* { dg-final { scan-assembler "vst40.16" } } */
-/* { dg-final { scan-assembler "vst41.16" } } */
-/* { dg-final { scan-assembler "vst42.16" } } */
-/* { dg-final { scan-assembler "vst43.16" } } */
-
-void
-foo2 (int16_t * addr, int16x8x4_t value)
-{
- vst4q_s16 (addr, value);
- addr += 32;
- vst4q_s16 (addr, value);
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c
index e6e1272744e..1a1a9797360 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c
@@ -1,37 +1,47 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
void
-foo (int32_t * addr, int32x4x4_t value)
+foo (int32_t *addr, int32x4x4_t value)
{
- vst4q_s32 (addr, value);
+ return vst4q_s32 (addr, value);
}
-/* { dg-final { scan-assembler "vst40.32" } } */
-/* { dg-final { scan-assembler "vst41.32" } } */
-/* { dg-final { scan-assembler "vst42.32" } } */
-/* { dg-final { scan-assembler "vst43.32" } } */
+/*
+**foo1:
+** ...
+** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
void
-foo1 (int32_t * addr, int32x4x4_t value)
+foo1 (int32_t *addr, int32x4x4_t value)
{
- vst4q (addr, value);
+ return vst4q (addr, value);
}
-/* { dg-final { scan-assembler "vst40.32" } } */
-/* { dg-final { scan-assembler "vst41.32" } } */
-/* { dg-final { scan-assembler "vst42.32" } } */
-/* { dg-final { scan-assembler "vst43.32" } } */
-
-void
-foo2 (int32_t * addr, int32x4x4_t value)
-{
- vst4q_s32 (addr, value);
- addr += 16;
- vst4q_s32 (addr, value);
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c
index 16eb488ff99..d23032a73bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c
@@ -1,37 +1,47 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
void
-foo (int8_t * addr, int8x16x4_t value)
+foo (int8_t *addr, int8x16x4_t value)
{
- vst4q_s8 (addr, value);
+ return vst4q_s8 (addr, value);
}
-/* { dg-final { scan-assembler "vst40.8" } } */
-/* { dg-final { scan-assembler "vst41.8" } } */
-/* { dg-final { scan-assembler "vst42.8" } } */
-/* { dg-final { scan-assembler "vst43.8" } } */
+/*
+**foo1:
+** ...
+** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
void
-foo1 (int8_t * addr, int8x16x4_t value)
+foo1 (int8_t *addr, int8x16x4_t value)
{
- vst4q (addr, value);
+ return vst4q (addr, value);
}
-/* { dg-final { scan-assembler "vst40.8" } } */
-/* { dg-final { scan-assembler "vst41.8" } } */
-/* { dg-final { scan-assembler "vst42.8" } } */
-/* { dg-final { scan-assembler "vst43.8" } } */
-
-void
-foo2 (int8_t * addr, int8x16x4_t value)
-{
- vst4q_s8 (addr, value);
- addr += 16*4;
- vst4q_s8 (addr, value);
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler {vst43.8\s\{.*\}, \[.*\]!} } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c
index afd60306d0d..76cc4311e1b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c
@@ -1,37 +1,47 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
void
-foo (uint16_t * addr, uint16x8x4_t value)
+foo (uint16_t *addr, uint16x8x4_t value)
{
- vst4q_u16 (addr, value);
+ return vst4q_u16 (addr, value);
}
-/* { dg-final { scan-assembler "vst40.16" } } */
-/* { dg-final { scan-assembler "vst41.16" } } */
-/* { dg-final { scan-assembler "vst42.16" } } */
-/* { dg-final { scan-assembler "vst43.16" } } */
+/*
+**foo1:
+** ...
+** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
void
-foo1 (uint16_t * addr, uint16x8x4_t value)
+foo1 (uint16_t *addr, uint16x8x4_t value)
{
- vst4q (addr, value);
+ return vst4q (addr, value);
}
-/* { dg-final { scan-assembler "vst40.16" } } */
-/* { dg-final { scan-assembler "vst41.16" } } */
-/* { dg-final { scan-assembler "vst42.16" } } */
-/* { dg-final { scan-assembler "vst43.16" } } */
-
-void
-foo2 (uint16_t * addr, uint16x8x4_t value)
-{
- vst4q_u16 (addr, value);
- addr += 32;
- vst4q_u16 (addr, value);
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c
index 755dd689dff..e5f62858eee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c
@@ -1,37 +1,47 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
void
-foo (uint32_t * addr, uint32x4x4_t value)
+foo (uint32_t *addr, uint32x4x4_t value)
{
- vst4q_u32 (addr, value);
+ return vst4q_u32 (addr, value);
}
-/* { dg-final { scan-assembler "vst40.32" } } */
-/* { dg-final { scan-assembler "vst41.32" } } */
-/* { dg-final { scan-assembler "vst42.32" } } */
-/* { dg-final { scan-assembler "vst43.32" } } */
+/*
+**foo1:
+** ...
+** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
void
-foo1 (uint32_t * addr, uint32x4x4_t value)
+foo1 (uint32_t *addr, uint32x4x4_t value)
{
- vst4q (addr, value);
+ return vst4q (addr, value);
}
-/* { dg-final { scan-assembler "vst40.32" } } */
-/* { dg-final { scan-assembler "vst41.32" } } */
-/* { dg-final { scan-assembler "vst42.32" } } */
-/* { dg-final { scan-assembler "vst43.32" } } */
-
-void
-foo2 (uint32_t * addr, uint32x4x4_t value)
-{
- vst4q_u32 (addr, value);
- addr += 16;
- vst4q_u32 (addr, value);
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c
index 0b28451df55..923cd0d3b10 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c
@@ -1,37 +1,47 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
void
-foo (uint8_t * addr, uint8x16x4_t value)
+foo (uint8_t *addr, uint8x16x4_t value)
{
- vst4q_u8 (addr, value);
+ return vst4q_u8 (addr, value);
}
-/* { dg-final { scan-assembler "vst40.8" } } */
-/* { dg-final { scan-assembler "vst41.8" } } */
-/* { dg-final { scan-assembler "vst42.8" } } */
-/* { dg-final { scan-assembler "vst43.8" } } */
+/*
+**foo1:
+** ...
+** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+** ...
+*/
void
-foo1 (uint8_t * addr, uint8x16x4_t value)
+foo1 (uint8_t *addr, uint8x16x4_t value)
{
- vst4q (addr, value);
+ return vst4q (addr, value);
}
-/* { dg-final { scan-assembler "vst40.8" } } */
-/* { dg-final { scan-assembler "vst41.8" } } */
-/* { dg-final { scan-assembler "vst42.8" } } */
-/* { dg-final { scan-assembler "vst43.8" } } */
-
-void
-foo2 (uint8_t * addr, uint8x16x4_t value)
-{
- vst4q_u8 (addr, value);
- addr += 16*4;
- vst4q_u8 (addr, value);
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler {vst43.8\s\{.*\}, \[.*\]!} } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c
index ad74d8aa2e9..19804443e01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int8_t * addr, int16x8_t value, mve_pred16_t p)
+foo (int8_t *base, int16x8_t value, mve_pred16_t p)
{
- vstrbq_p_s16 (addr, value, p);
+ return vstrbq_p_s16 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrbt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int8_t * addr, int16x8_t value, mve_pred16_t p)
+foo1 (int8_t *base, int16x8_t value, mve_pred16_t p)
{
- vstrbq_p (addr, value, p);
+ return vstrbq_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrbt.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c
index 46fd4549ffb..26be212770b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int8_t * addr, int32x4_t value, mve_pred16_t p)
+foo (int8_t *base, int32x4_t value, mve_pred16_t p)
{
- vstrbq_p_s32 (addr, value, p);
+ return vstrbq_p_s32 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrbt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int8_t * addr, int32x4_t value, mve_pred16_t p)
+foo1 (int8_t *base, int32x4_t value, mve_pred16_t p)
{
- vstrbq_p (addr, value, p);
+ return vstrbq_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrbt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c
index 8e70b9eb098..a0d08772a50 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int8_t * addr, int8x16_t value, mve_pred16_t p)
+foo (int8_t *base, int8x16_t value, mve_pred16_t p)
{
- vstrbq_p_s8 (addr, value, p);
+ return vstrbq_p_s8 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrbt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int8_t * addr, int8x16_t value, mve_pred16_t p)
+foo1 (int8_t *base, int8x16_t value, mve_pred16_t p)
{
- vstrbq_p (addr, value, p);
+ return vstrbq_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrbt.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c
index 180f9033edd..bc02c59887a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint8_t * addr, uint16x8_t value, mve_pred16_t p)
+foo (uint8_t *base, uint16x8_t value, mve_pred16_t p)
{
- vstrbq_p_u16 (addr, value, p);
+ return vstrbq_p_u16 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrbt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint8_t * addr, uint16x8_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint16x8_t value, mve_pred16_t p)
{
- vstrbq_p (addr, value, p);
+ return vstrbq_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrbt.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c
index 1b944fc9ffc..1215d5f0978 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint8_t * addr, uint32x4_t value, mve_pred16_t p)
+foo (uint8_t *base, uint32x4_t value, mve_pred16_t p)
{
- vstrbq_p_u32 (addr, value, p);
+ return vstrbq_p_u32 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrbt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint8_t * addr, uint32x4_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint32x4_t value, mve_pred16_t p)
{
- vstrbq_p (addr, value, p);
+ return vstrbq_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrbt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c
index 7e73cbff84e..a88234e411d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint8_t * addr, uint8x16_t value, mve_pred16_t p)
+foo (uint8_t *base, uint8x16_t value, mve_pred16_t p)
{
- vstrbq_p_u8 (addr, value, p);
+ return vstrbq_p_u8 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrbt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint8_t * addr, uint8x16_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint8x16_t value, mve_pred16_t p)
{
- vstrbq_p (addr, value, p);
+ return vstrbq_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrbt.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c
index 4d12bc2cd19..1e88d3aa600 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int8_t * addr, int16x8_t value)
+foo (int8_t *base, int16x8_t value)
{
- vstrbq_s16 (addr, value);
+ return vstrbq_s16 (base, value);
}
-/* { dg-final { scan-assembler "vstrb.16" } } */
+/*
+**foo1:
+** ...
+** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int8_t * addr, int16x8_t value)
+foo1 (int8_t *base, int16x8_t value)
{
- vstrbq (addr, value);
+ return vstrbq (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrb.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c
index 750413f35ae..12764bf3041 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int8_t * addr, int32x4_t value)
+foo (int8_t *base, int32x4_t value)
{
- vstrbq_s32 (addr, value);
+ return vstrbq_s32 (base, value);
}
-/* { dg-final { scan-assembler "vstrb.32" } } */
+/*
+**foo1:
+** ...
+** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int8_t * addr, int32x4_t value)
+foo1 (int8_t *base, int32x4_t value)
{
- vstrbq (addr, value);
+ return vstrbq (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrb.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c
index 7ffb2c51976..05a9e5c42ce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int8_t * addr, int8x16_t value)
+foo (int8_t *base, int8x16_t value)
{
- vstrbq_s8 (addr, value);
+ return vstrbq_s8 (base, value);
}
-/* { dg-final { scan-assembler "vstrb.8" } } */
+/*
+**foo1:
+** ...
+** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int8_t * addr, int8x16_t value)
+foo1 (int8_t *base, int8x16_t value)
{
- vstrbq (addr, value);
+ return vstrbq (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrb.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c
index f59fa349cc0..052c3f85b75 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (int8_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
+foo (int8_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
{
- vstrbq_scatter_offset_p_s16 (base, offset, value, p);
+ return vstrbq_scatter_offset_p_s16 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrbt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (int8_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
+foo1 (int8_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
{
- vstrbq_scatter_offset_p (base, offset, value, p);
+ return vstrbq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrbt.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c
index 737c1008976..57410e46a8a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (int8_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo (int8_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
{
- vstrbq_scatter_offset_p_s32 (base, offset, value, p);
+ return vstrbq_scatter_offset_p_s32 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrbt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (int8_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo1 (int8_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
{
- vstrbq_scatter_offset_p (base, offset, value, p);
+ return vstrbq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrbt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c
index 8b2d06807b4..c3cdefdf078 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (int8_t * base, uint8x16_t offset, int8x16_t value, mve_pred16_t p)
+foo (int8_t *base, uint8x16_t offset, int8x16_t value, mve_pred16_t p)
{
- vstrbq_scatter_offset_p_s8 (base, offset, value, p);
+ return vstrbq_scatter_offset_p_s8 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrbt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (int8_t * base, uint8x16_t offset, int8x16_t value, mve_pred16_t p)
+foo1 (int8_t *base, uint8x16_t offset, int8x16_t value, mve_pred16_t p)
{
- vstrbq_scatter_offset_p (base, offset, value, p);
+ return vstrbq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrbt.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c
index 0adccaac39c..0868cc2248b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint8_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
+foo (uint8_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
{
- vstrbq_scatter_offset_p_u16 (base, offset, value, p);
+ return vstrbq_scatter_offset_p_u16 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrbt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
{
- vstrbq_scatter_offset_p (base, offset, value, p);
+ return vstrbq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrbt.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c
index 308119294df..9d769941569 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint8_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo (uint8_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
{
- vstrbq_scatter_offset_p_u32 (base, offset, value, p);
+ return vstrbq_scatter_offset_p_u32 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrbt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
{
- vstrbq_scatter_offset_p (base, offset, value, p);
+ return vstrbq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrbt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c
index 28b2ca4b83a..4586535d600 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint8_t * base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p)
+foo (uint8_t *base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p)
{
- vstrbq_scatter_offset_p_u8 (base, offset, value, p);
+ return vstrbq_scatter_offset_p_u8 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrbt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p)
{
- vstrbq_scatter_offset_p (base, offset, value, p);
+ return vstrbq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrbt.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c
index e6cf1828b33..179b96f4973 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (int8_t * base, uint16x8_t offset, int16x8_t value)
+foo (int8_t *base, uint16x8_t offset, int16x8_t value)
{
- vstrbq_scatter_offset_s16 (base, offset, value);
+ return vstrbq_scatter_offset_s16 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrb.16" } } */
+/*
+**foo1:
+** ...
+** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (int8_t * base, uint16x8_t offset, int16x8_t value)
+foo1 (int8_t *base, uint16x8_t offset, int16x8_t value)
{
- vstrbq_scatter_offset (base, offset, value);
+ return vstrbq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrb.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c
index 052e02a7cf9..e7b7767c9f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (int8_t * base, uint32x4_t offset, int32x4_t value)
+foo (int8_t *base, uint32x4_t offset, int32x4_t value)
{
- vstrbq_scatter_offset_s32 (base, offset, value);
+ return vstrbq_scatter_offset_s32 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrb.32" } } */
+/*
+**foo1:
+** ...
+** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (int8_t * base, uint32x4_t offset, int32x4_t value)
+foo1 (int8_t *base, uint32x4_t offset, int32x4_t value)
{
- vstrbq_scatter_offset (base, offset, value);
+ return vstrbq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrb.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c
index 523f318e73c..f47bdd1a630 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (int8_t * base, uint8x16_t offset, int8x16_t value)
+foo (int8_t *base, uint8x16_t offset, int8x16_t value)
{
- vstrbq_scatter_offset_s8 (base, offset, value);
+ return vstrbq_scatter_offset_s8 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrb.8" } } */
+/*
+**foo1:
+** ...
+** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (int8_t * base, uint8x16_t offset, int8x16_t value)
+foo1 (int8_t *base, uint8x16_t offset, int8x16_t value)
{
- vstrbq_scatter_offset (base, offset, value);
+ return vstrbq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrb.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c
index 49d4d31ad21..90e8cf351f9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint8_t * base, uint16x8_t offset, uint16x8_t value)
+foo (uint8_t *base, uint16x8_t offset, uint16x8_t value)
{
- vstrbq_scatter_offset_u16 (base, offset, value);
+ return vstrbq_scatter_offset_u16 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrb.16" } } */
+/*
+**foo1:
+** ...
+** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value)
+foo1 (uint8_t *base, uint16x8_t offset, uint16x8_t value)
{
- vstrbq_scatter_offset (base, offset, value);
+ return vstrbq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrb.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c
index 0012852298c..e5449aa0942 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint8_t * base, uint32x4_t offset, uint32x4_t value)
+foo (uint8_t *base, uint32x4_t offset, uint32x4_t value)
{
- vstrbq_scatter_offset_u32 (base, offset, value);
+ return vstrbq_scatter_offset_u32 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrb.32" } } */
+/*
+**foo1:
+** ...
+** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value)
+foo1 (uint8_t *base, uint32x4_t offset, uint32x4_t value)
{
- vstrbq_scatter_offset (base, offset, value);
+ return vstrbq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrb.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c
index e54422a1afe..06c8c45e877 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint8_t * base, uint8x16_t offset, uint8x16_t value)
+foo (uint8_t *base, uint8x16_t offset, uint8x16_t value)
{
- vstrbq_scatter_offset_u8 (base, offset, value);
+ return vstrbq_scatter_offset_u8 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrb.8" } } */
+/*
+**foo1:
+** ...
+** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value)
+foo1 (uint8_t *base, uint8x16_t offset, uint8x16_t value)
{
- vstrbq_scatter_offset (base, offset, value);
+ return vstrbq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrb.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c
index 9fa9d18c6a1..0b350e2491b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint8_t * addr, uint16x8_t value)
+foo (uint8_t *base, uint16x8_t value)
{
- vstrbq_u16 (addr, value);
+ return vstrbq_u16 (base, value);
}
-/* { dg-final { scan-assembler "vstrb.16" } } */
+/*
+**foo1:
+** ...
+** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint8_t * addr, uint16x8_t value)
+foo1 (uint8_t *base, uint16x8_t value)
{
- vstrbq (addr, value);
+ return vstrbq (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrb.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c
index e535aa275ef..2f809356420 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint8_t * addr, uint32x4_t value)
+foo (uint8_t *base, uint32x4_t value)
{
- vstrbq_u32 (addr, value);
+ return vstrbq_u32 (base, value);
}
-/* { dg-final { scan-assembler "vstrb.32" } } */
+/*
+**foo1:
+** ...
+** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint8_t * addr, uint32x4_t value)
+foo1 (uint8_t *base, uint32x4_t value)
{
- vstrbq (addr, value);
+ return vstrbq (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrb.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c
index 93771aabcbd..deeea98dda5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint8_t * addr, uint8x16_t value)
+foo (uint8_t *base, uint8x16_t value)
{
- vstrbq_u8 (addr, value);
+ return vstrbq_u8 (base, value);
}
-/* { dg-final { scan-assembler "vstrb.8" } } */
+/*
+**foo1:
+** ...
+** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint8_t * addr, uint8x16_t value)
+foo1 (uint8_t *base, uint8x16_t value)
{
- vstrbq (addr, value);
+ return vstrbq (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrb.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c
index 74e2617c380..a41217b24f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (float16_t * addr, float16x8_t value)
+foo (float16_t *base, float16x8_t value)
{
- vstrhq_f16 (addr, value);
+ return vstrhq_f16 (base, value);
}
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/*
+**foo1:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (float16_t * addr, float16x8_t value)
+foo1 (float16_t *base, float16x8_t value)
{
- vstrhq (addr, value);
+ return vstrhq (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c
index 227da4f10aa..8398a60023d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (float16_t * addr, float16x8_t value, mve_pred16_t p)
+foo (float16_t *base, float16x8_t value, mve_pred16_t p)
{
- vstrhq_p_f16 (addr, value, p);
+ return vstrhq_p_f16 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (float16_t * addr, float16x8_t value, mve_pred16_t p)
+foo1 (float16_t *base, float16x8_t value, mve_pred16_t p)
{
- vstrhq_p (addr, value, p);
+ return vstrhq_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c
index f3ba71f0ce1..ee1026801be 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int16_t * addr, int16x8_t value, mve_pred16_t p)
+foo (int16_t *base, int16x8_t value, mve_pred16_t p)
{
- vstrhq_p_s16 (addr, value, p);
+ return vstrhq_p_s16 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int16_t * addr, int16x8_t value, mve_pred16_t p)
+foo1 (int16_t *base, int16x8_t value, mve_pred16_t p)
{
- vstrhq_p (addr, value, p);
+ return vstrhq_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c
index dab646706ce..b8490209644 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int16_t * addr, int32x4_t value, mve_pred16_t p)
+foo (int16_t *base, int32x4_t value, mve_pred16_t p)
{
- vstrhq_p_s32 (addr, value, p);
+ return vstrhq_p_s32 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrht.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int16_t * addr, int32x4_t value, mve_pred16_t p)
+foo1 (int16_t *base, int32x4_t value, mve_pred16_t p)
{
- vstrhq_p (addr, value, p);
+ return vstrhq_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c
index e575c70cc44..59fb73cef19 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint16_t * addr, uint16x8_t value, mve_pred16_t p)
+foo (uint16_t *base, uint16x8_t value, mve_pred16_t p)
{
- vstrhq_p_u16 (addr, value, p);
+ return vstrhq_p_u16 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint16_t * addr, uint16x8_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint16x8_t value, mve_pred16_t p)
{
- vstrhq_p (addr, value, p);
+ return vstrhq_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c
index e863e284c3c..ed66db7f8ce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint16_t * addr, uint32x4_t value, mve_pred16_t p)
+foo (uint16_t *base, uint32x4_t value, mve_pred16_t p)
{
- vstrhq_p_u32 (addr, value, p);
+ return vstrhq_p_u32 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrht.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint16_t * addr, uint32x4_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint32x4_t value, mve_pred16_t p)
{
- vstrhq_p (addr, value, p);
+ return vstrhq_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c
index 5e47fb4e1a6..972d733c5bd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int16_t * addr, int16x8_t value)
+foo (int16_t *base, int16x8_t value)
{
- vstrhq_s16 (addr, value);
+ return vstrhq_s16 (base, value);
}
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/*
+**foo1:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int16_t * addr, int16x8_t value)
+foo1 (int16_t *base, int16x8_t value)
{
- vstrhq (addr, value);
+ return vstrhq (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c
index 73e01c9acfb..f260c61c3a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int16_t * addr, int32x4_t value)
+foo (int16_t *base, int32x4_t value)
{
- vstrhq_s32 (addr, value);
+ return vstrhq_s32 (base, value);
}
-/* { dg-final { scan-assembler "vstrh.32" } } */
+/*
+**foo1:
+** ...
+** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int16_t * addr, int32x4_t value)
+foo1 (int16_t *base, int32x4_t value)
{
- vstrhq (addr, value);
+ return vstrhq (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrh.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c
index d29bd08ad0a..794d75e76ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (float16_t * base, uint16x8_t offset, float16x8_t value)
+foo (float16_t *base, uint16x8_t offset, float16x8_t value)
{
- vstrhq_scatter_offset_f16 (base, offset, value);
+ return vstrhq_scatter_offset_f16 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/*
+**foo1:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value)
+foo1 (float16_t *base, uint16x8_t offset, float16x8_t value)
{
- vstrhq_scatter_offset (base, offset, value);
+ return vstrhq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c
index 79d9827b378..1fd5a0773dc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
+foo (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
{
- vstrhq_scatter_offset_p_f16 (base, offset, value, p);
+ return vstrhq_scatter_offset_p_f16 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
+foo1 (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
{
- vstrhq_scatter_offset_p (base, offset, value, p);
+ return vstrhq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c
index 1b401d4c5b7..34c44a90541 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
+foo (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
{
- vstrhq_scatter_offset_p_s16 (base, offset, value, p);
+ return vstrhq_scatter_offset_p_s16 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
+foo1 (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
{
- vstrhq_scatter_offset_p (base, offset, value, p);
+ return vstrhq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c
index afb325b9789..2a84b28a3f5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
{
- vstrhq_scatter_offset_p_s32 (base, offset, value, p);
+ return vstrhq_scatter_offset_p_s32 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrht.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo1 (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
{
- vstrhq_scatter_offset_p (base, offset, value, p);
+ return vstrhq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c
index 73bee831282..f1c875657ce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
+foo (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
{
- vstrhq_scatter_offset_p_u16 (base, offset, value, p);
+ return vstrhq_scatter_offset_p_u16 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
{
- vstrhq_scatter_offset_p (base, offset, value, p);
+ return vstrhq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c
index bae7c2d14c2..913fd8d5591 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
{
- vstrhq_scatter_offset_p_u32 (base, offset, value, p);
+ return vstrhq_scatter_offset_p_u32 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrht.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
{
- vstrhq_scatter_offset_p (base, offset, value, p);
+ return vstrhq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c
index bf3c03a85c6..b322d0fa02e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (int16_t * base, uint16x8_t offset, int16x8_t value)
+foo (int16_t *base, uint16x8_t offset, int16x8_t value)
{
- vstrhq_scatter_offset_s16 (base, offset, value);
+ return vstrhq_scatter_offset_s16 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/*
+**foo1:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value)
+foo1 (int16_t *base, uint16x8_t offset, int16x8_t value)
{
- vstrhq_scatter_offset (base, offset, value);
+ return vstrhq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c
index 0591ab55c07..49fcc3a382b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (int16_t * base, uint32x4_t offset, int32x4_t value)
+foo (int16_t *base, uint32x4_t offset, int32x4_t value)
{
- vstrhq_scatter_offset_s32 (base, offset, value);
+ return vstrhq_scatter_offset_s32 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrh.32" } } */
+/*
+**foo1:
+** ...
+** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value)
+foo1 (int16_t *base, uint32x4_t offset, int32x4_t value)
{
- vstrhq_scatter_offset (base, offset, value);
+ return vstrhq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrh.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c
index 0a2fa1f410e..b5de540a74c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value)
+foo (uint16_t *base, uint16x8_t offset, uint16x8_t value)
{
- vstrhq_scatter_offset_u16 (base, offset, value);
+ return vstrhq_scatter_offset_u16 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/*
+**foo1:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value)
+foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value)
{
- vstrhq_scatter_offset (base, offset, value);
+ return vstrhq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c
index 809a44dee16..7808f25d4a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value)
+foo (uint16_t *base, uint32x4_t offset, uint32x4_t value)
{
- vstrhq_scatter_offset_u32 (base, offset, value);
+ return vstrhq_scatter_offset_u32 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrh.32" } } */
+/*
+**foo1:
+** ...
+** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value)
+foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value)
{
- vstrhq_scatter_offset (base, offset, value);
+ return vstrhq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrh.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c
index 1dcb1f7692d..6d57a22fe41 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo (float16_t * base, uint16x8_t offset, float16x8_t value)
+foo (float16_t *base, uint16x8_t offset, float16x8_t value)
{
- vstrhq_scatter_shifted_offset_f16 (base, offset, value);
+ return vstrhq_scatter_shifted_offset_f16 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/*
+**foo1:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value)
+foo1 (float16_t *base, uint16x8_t offset, float16x8_t value)
{
- vstrhq_scatter_shifted_offset (base, offset, value);
+ return vstrhq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c
index c46eec95adf..2e77dd492a1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
+foo (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
{
- vstrhq_scatter_shifted_offset_p_f16 (base, offset, value, p);
+ return vstrhq_scatter_shifted_offset_p_f16 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
+foo1 (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
{
- vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+ return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c
index 7e9a549e8c2..1c83a13ffdf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
+foo (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
{
- vstrhq_scatter_shifted_offset_p_s16 (base, offset, value, p);
+ return vstrhq_scatter_shifted_offset_p_s16 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
+foo1 (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
{
- vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+ return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c
index 502b4b00e2a..6d786de4379 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
{
- vstrhq_scatter_shifted_offset_p_s32 (base, offset, value, p);
+ return vstrhq_scatter_shifted_offset_p_s32 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrht.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo1 (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
{
- vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+ return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c
index 151145ce174..fd73168ddbb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
+foo (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
{
- vstrhq_scatter_shifted_offset_p_u16 (base, offset, value, p);
+ return vstrhq_scatter_shifted_offset_p_u16 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
{
- vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+ return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c
index 14efd952593..689195ce603 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
{
- vstrhq_scatter_shifted_offset_p_u32 (base, offset, value, p);
+ return vstrhq_scatter_shifted_offset_p_u32 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrht.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
{
- vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+ return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c
index e5142ed85f7..0edacd938f6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo (int16_t * base, uint16x8_t offset, int16x8_t value)
+foo (int16_t *base, uint16x8_t offset, int16x8_t value)
{
- vstrhq_scatter_shifted_offset_s16 (base, offset, value);
+ return vstrhq_scatter_shifted_offset_s16 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/*
+**foo1:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value)
+foo1 (int16_t *base, uint16x8_t offset, int16x8_t value)
{
- vstrhq_scatter_shifted_offset (base, offset, value);
+ return vstrhq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c
index 431808f9008..ebda2faec92 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo (int16_t * base, uint32x4_t offset, int32x4_t value)
+foo (int16_t *base, uint32x4_t offset, int32x4_t value)
{
- vstrhq_scatter_shifted_offset_s32 (base, offset, value);
+ return vstrhq_scatter_shifted_offset_s32 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrh.32" } } */
+/*
+**foo1:
+** ...
+** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value)
+foo1 (int16_t *base, uint32x4_t offset, int32x4_t value)
{
- vstrhq_scatter_shifted_offset (base, offset, value);
+ return vstrhq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrh.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c
index f93e5d51913..abe8bbf8045 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value)
+foo (uint16_t *base, uint16x8_t offset, uint16x8_t value)
{
- vstrhq_scatter_shifted_offset_u16 (base, offset, value);
+ return vstrhq_scatter_shifted_offset_u16 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/*
+**foo1:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value)
+foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value)
{
- vstrhq_scatter_shifted_offset (base, offset, value);
+ return vstrhq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c
index fc250706fa8..a01b04bd940 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value)
+foo (uint16_t *base, uint32x4_t offset, uint32x4_t value)
{
- vstrhq_scatter_shifted_offset_u32 (base, offset, value);
+ return vstrhq_scatter_shifted_offset_u32 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrh.32" } } */
+/*
+**foo1:
+** ...
+** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?: @.*|)
+** ...
+*/
void
-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value)
+foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value)
{
- vstrhq_scatter_shifted_offset (base, offset, value);
+ return vstrhq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrh.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c
index f7b3ef1012b..85f5790ff49 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint16_t * addr, uint16x8_t value)
+foo (uint16_t *base, uint16x8_t value)
{
- vstrhq_u16 (addr, value);
+ return vstrhq_u16 (base, value);
}
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/*
+**foo1:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint16_t * addr, uint16x8_t value)
+foo1 (uint16_t *base, uint16x8_t value)
{
- vstrhq (addr, value);
+ return vstrhq (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c
index 8e01fd10032..d0958e22222 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint16_t * addr, uint32x4_t value)
+foo (uint16_t *base, uint32x4_t value)
{
- vstrhq_u32 (addr, value);
+ return vstrhq_u32 (base, value);
}
-/* { dg-final { scan-assembler "vstrh.32" } } */
+/*
+**foo1:
+** ...
+** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint16_t * addr, uint32x4_t value)
+foo1 (uint16_t *base, uint32x4_t value)
{
- vstrhq (addr, value);
+ return vstrhq (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrh.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--
2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 02/10] arm: Fix vstrwq* backend + testsuite
2023-04-28 11:29 [PATCH 01/10] arm: Mve testsuite improvements Andrea Corallo
@ 2023-04-28 11:29 ` Andrea Corallo
2023-04-28 16:27 ` Kyrylo Tkachov
2023-05-02 8:21 ` Christophe Lyon
2023-04-28 11:29 ` [PATCH 03/10] arm: Mve backend + testsuite fixes 2 Andrea Corallo
` (8 subsequent siblings)
9 siblings, 2 replies; 31+ messages in thread
From: Andrea Corallo @ 2023-04-28 11:29 UTC (permalink / raw)
To: gcc-patches; +Cc: kyrylo.tkachov, Richard.Earnshaw, Andrea Corallo
Hi all,
this patch fixes the vstrwq* MVE instrinsics failing to emit the
correct sequence of instruction due to a missing predicates. Also the
immediate range is fixed to be multiples of 2 up between [-252, 252].
Best Regards
Andrea
gcc/ChangeLog:
* config/arm/constraints.md (mve_vldrd_immediate): Move it to
predicates.md.
(Ri): Move constraint definition from predicates.md.
(Rl): Define new constraint.
* config/arm/mve.md (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Add
missing constraint.
(mve_vstrwq_scatter_base_wb_p_fv4sf): Add missing Up constraint
for op 1, use mve_vstrw_immediate predicate and Rl constraint for
op 2. Fix asm output spacing.
(mve_vstrdq_scatter_base_wb_p_<supf>v2di): Add missing constraint.
* config/arm/predicates.md (Ri) Move constraint to constraints.md
(mve_vldrd_immediate): Move it from
constraints.md.
(mve_vstrw_immediate): New predicate.
gcc/testsuite/ChangeLog:
* gcc.target/arm/mve/intrinsics/vstrwq_f32.c: Use
check-function-bodies instead of scan-assembler checks. Use
extern "C" for C++ testing.
* gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_u32.c: Likewise.
---
gcc/config/arm/constraints.md | 20 ++++++++--
gcc/config/arm/mve.md | 10 ++---
gcc/config/arm/predicates.md | 14 +++----
.../arm/mve/intrinsics/vstrwq_f32.c | 32 ++++++++++++---
.../arm/mve/intrinsics/vstrwq_p_f32.c | 40 ++++++++++++++++---
.../arm/mve/intrinsics/vstrwq_p_s32.c | 40 ++++++++++++++++---
.../arm/mve/intrinsics/vstrwq_p_u32.c | 40 ++++++++++++++++---
.../arm/mve/intrinsics/vstrwq_s32.c | 32 ++++++++++++---
.../mve/intrinsics/vstrwq_scatter_base_f32.c | 28 +++++++++++--
.../intrinsics/vstrwq_scatter_base_p_f32.c | 36 +++++++++++++++--
.../intrinsics/vstrwq_scatter_base_p_s32.c | 36 +++++++++++++++--
.../intrinsics/vstrwq_scatter_base_p_u32.c | 36 +++++++++++++++--
.../mve/intrinsics/vstrwq_scatter_base_s32.c | 28 +++++++++++--
.../mve/intrinsics/vstrwq_scatter_base_u32.c | 28 +++++++++++--
.../intrinsics/vstrwq_scatter_base_wb_f32.c | 32 ++++++++++++---
.../intrinsics/vstrwq_scatter_base_wb_p_f32.c | 40 ++++++++++++++++---
.../intrinsics/vstrwq_scatter_base_wb_p_s32.c | 40 ++++++++++++++++---
.../intrinsics/vstrwq_scatter_base_wb_p_u32.c | 40 ++++++++++++++++---
.../intrinsics/vstrwq_scatter_base_wb_s32.c | 32 ++++++++++++---
.../intrinsics/vstrwq_scatter_base_wb_u32.c | 32 ++++++++++++---
.../intrinsics/vstrwq_scatter_offset_f32.c | 32 ++++++++++++---
.../intrinsics/vstrwq_scatter_offset_p_f32.c | 40 ++++++++++++++++---
.../intrinsics/vstrwq_scatter_offset_p_s32.c | 40 ++++++++++++++++---
.../intrinsics/vstrwq_scatter_offset_p_u32.c | 40 ++++++++++++++++---
.../intrinsics/vstrwq_scatter_offset_s32.c | 32 ++++++++++++---
.../intrinsics/vstrwq_scatter_offset_u32.c | 32 ++++++++++++---
.../vstrwq_scatter_shifted_offset_f32.c | 32 ++++++++++++---
.../vstrwq_scatter_shifted_offset_p_f32.c | 40 ++++++++++++++++---
.../vstrwq_scatter_shifted_offset_p_s32.c | 40 ++++++++++++++++---
.../vstrwq_scatter_shifted_offset_p_u32.c | 40 ++++++++++++++++---
.../vstrwq_scatter_shifted_offset_s32.c | 32 ++++++++++++---
.../vstrwq_scatter_shifted_offset_u32.c | 32 ++++++++++++---
.../arm/mve/intrinsics/vstrwq_u32.c | 32 ++++++++++++---
33 files changed, 922 insertions(+), 178 deletions(-)
diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md
index 504cd938b26..05a4ebbdd67 100644
--- a/gcc/config/arm/constraints.md
+++ b/gcc/config/arm/constraints.md
@@ -102,10 +102,6 @@ (define_constraint "Rg"
(match_test "TARGET_HAVE_MVE && ((ival == 1) || (ival == 2)
|| (ival == 4) || (ival == 8))")))
-;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE.
-(define_predicate "mve_vldrd_immediate"
- (match_test "satisfies_constraint_Ri (op)"))
-
(define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
"The VFP registers @code{s0}-@code{s31}.")
@@ -574,6 +570,22 @@ (define_constraint "US"
(match_code "symbol_ref")
)
+;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE.
+(define_constraint "Ri"
+ "@internal In Thumb-2 state a constant is multiple of 8 and in range
+ of -/+ 1016 for MVE"
+ (and (match_code "const_int")
+ (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016)
+ && ((ival % 8) == 0)")))
+
+;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE.
+(define_constraint "Rl"
+ "@internal In Thumb-2 state a constant is multiple of 2 and in range
+ of -/+ 252 for MVE"
+ (and (match_code "const_int")
+ (match_test "TARGET_HAVE_MVE && (-252 <= ival) && (ival <= 252)
+ && ((ival % 2) == 0)")))
+
(define_memory_constraint "Uz"
"@internal
A memory access that is accessible as an LDC/STC operand"
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 35eab6c94bf..161794e470c 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -9359,7 +9359,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_<supf>v4si"
[(match_operand:V4SI 1 "s_register_operand" "0")
(match_operand:SI 2 "mve_vldrd_immediate" "Ri")
(match_operand:V4SI 3 "s_register_operand" "w")
- (match_operand:V4BI 4 "vpr_register_operand")]
+ (match_operand:V4BI 4 "vpr_register_operand" "Up")]
VSTRWSBWBQ))
(set (match_operand:V4SI 0 "s_register_operand" "=w")
(unspec:V4SI [(match_dup 1) (match_dup 2)]
@@ -9408,9 +9408,9 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf"
[(set (mem:BLK (scratch))
(unspec:BLK
[(match_operand:V4SI 1 "s_register_operand" "0")
- (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
+ (match_operand:SI 2 "mve_vstrw_immediate" "Rl")
(match_operand:V4SF 3 "s_register_operand" "w")
- (match_operand:V4BI 4 "vpr_register_operand")]
+ (match_operand:V4BI 4 "vpr_register_operand" "Up")]
VSTRWQSBWB_F))
(set (match_operand:V4SI 0 "s_register_operand" "=w")
(unspec:V4SI [(match_dup 1) (match_dup 2)]
@@ -9422,7 +9422,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf"
ops[0] = operands[1];
ops[1] = operands[2];
ops[2] = operands[3];
- output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops);
+ output_asm_insn ("vpst\;vstrwt.u32\t%q2, [%q0, %1]!",ops);
return "";
}
[(set_attr "length" "8")])
@@ -9461,7 +9461,7 @@ (define_insn "mve_vstrdq_scatter_base_wb_p_<supf>v2di"
[(match_operand:V2DI 1 "s_register_operand" "0")
(match_operand:SI 2 "mve_vldrd_immediate" "Ri")
(match_operand:V2DI 3 "s_register_operand" "w")
- (match_operand:V2QI 4 "vpr_register_operand")]
+ (match_operand:V2QI 4 "vpr_register_operand" "Up")]
VSTRDSBWBQ))
(set (match_operand:V2DI 0 "s_register_operand" "=w")
(unspec:V2DI [(match_dup 1) (match_dup 2)]
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 3139750c606..00995a590ab 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -73,13 +73,13 @@ (define_predicate "mve_imm_32"
(define_predicate "mve_imm_selective_upto_8"
(match_test "satisfies_constraint_Rg (op)"))
-;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE.
-(define_constraint "Ri"
- "@internal In Thumb-2 state a constant is multiple of 8 and in range
- of -/+ 1016 for MVE"
- (and (match_code "const_int")
- (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016)
- && ((ival % 8) == 0)")))
+;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE.
+(define_predicate "mve_vldrd_immediate"
+ (match_test "satisfies_constraint_Ri (op)"))
+
+;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE.
+(define_predicate "mve_vstrw_immediate"
+ (match_test "satisfies_constraint_Rl (op)"))
; Predicate for stack protector guard's address in
; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
index 8aa04fcbdee..e92ecb0f6bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (float32_t * addr, float32x4_t value)
+foo (float32_t *base, float32x4_t value)
{
- vstrwq_f32 (addr, value);
+ return vstrwq_f32 (base, value);
}
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/*
+**foo1:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (float32_t * addr, float32x4_t value)
+foo1 (float32_t *base, float32x4_t value)
{
- vstrwq (addr, value);
+ return vstrwq (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
index 411de6414f7..f1992a67736 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (float32_t * addr, float32x4_t value, mve_pred16_t p)
+foo (float32_t *base, float32x4_t value, mve_pred16_t p)
{
- vstrwq_p_f32 (addr, value, p);
+ return vstrwq_p_f32 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p)
+foo1 (float32_t *base, float32x4_t value, mve_pred16_t p)
{
- vstrwq_p (addr, value, p);
+ return vstrwq_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
index 3b042814d27..a00aeabb9fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int32_t * addr, int32x4_t value, mve_pred16_t p)
+foo (int32_t *base, int32x4_t value, mve_pred16_t p)
{
- vstrwq_p_s32 (addr, value, p);
+ return vstrwq_p_s32 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p)
+foo1 (int32_t *base, int32x4_t value, mve_pred16_t p)
{
- vstrwq_p (addr, value, p);
+ return vstrwq_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
index b9e92204c88..05fded8aac8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
+foo (uint32_t *base, uint32x4_t value, mve_pred16_t p)
{
- vstrwq_p_u32 (addr, value, p);
+ return vstrwq_p_u32 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
+foo1 (uint32_t *base, uint32x4_t value, mve_pred16_t p)
{
- vstrwq_p (addr, value, p);
+ return vstrwq_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
index c7b3d91a972..b2a184f3c66 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int32_t * addr, int32x4_t value)
+foo (int32_t *base, int32x4_t value)
{
- vstrwq_s32 (addr, value);
+ return vstrwq_s32 (base, value);
}
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/*
+**foo1:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int32_t * addr, int32x4_t value)
+foo1 (int32_t *base, int32x4_t value)
{
- vstrwq (addr, value);
+ return vstrwq (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
index f8b56917295..c80e8d9cdc5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
foo (uint32x4_t addr, float32x4_t value)
{
- vstrwq_scatter_base_f32 (addr, 8, value);
+ return vstrwq_scatter_base_f32 (addr, 0, value);
}
-/* { dg-final { scan-assembler "vstrw.u32" } } */
+/*
+**foo1:
+** ...
+** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
foo1 (uint32x4_t addr, float32x4_t value)
{
- vstrwq_scatter_base (addr, 8, value);
+ return vstrwq_scatter_base (addr, 0, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrw.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
index 4a75e6503e1..237843c0661 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
foo (uint32x4_t addr, float32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_base_p_f32 (addr, 8, value, p);
+ return vstrwq_scatter_base_p_f32 (addr, 0, value, p);
}
-/* { dg-final { scan-assembler "vstrwt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
foo1 (uint32x4_t addr, float32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_base_p (addr, 8, value, p);
+ return vstrwq_scatter_base_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrwt.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
index 5ac4f300a7d..5f4f4a09664 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
foo (uint32x4_t addr, int32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_base_p_s32 (addr, 8, value, p);
+ return vstrwq_scatter_base_p_s32 (addr, 0, value, p);
}
-/* { dg-final { scan-assembler "vstrwt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
foo1 (uint32x4_t addr, int32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_base_p (addr, 8, value, p);
+ return vstrwq_scatter_base_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrwt.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
index e564f26b9c7..8c5cf63f861 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
foo (uint32x4_t addr, uint32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_base_p_u32 (addr, 8, value, p);
+ return vstrwq_scatter_base_p_u32 (addr, 0, value, p);
}
-/* { dg-final { scan-assembler "vstrwt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
foo1 (uint32x4_t addr, uint32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_base_p (addr, 8, value, p);
+ return vstrwq_scatter_base_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrwt.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
index 5bba36db5cb..5208cf4f808 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
foo (uint32x4_t addr, int32x4_t value)
{
- vstrwq_scatter_base_s32 (addr, 8, value);
+ return vstrwq_scatter_base_s32 (addr, 0, value);
}
-/* { dg-final { scan-assembler "vstrw.u32" } } */
+/*
+**foo1:
+** ...
+** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
foo1 (uint32x4_t addr, int32x4_t value)
{
- vstrwq_scatter_base (addr, 8, value);
+ return vstrwq_scatter_base (addr, 0, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrw.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
index 1dcbb5a739c..e728db2b9f1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
foo (uint32x4_t addr, uint32x4_t value)
{
- vstrwq_scatter_base_u32 (addr, 8, value);
+ return vstrwq_scatter_base_u32 (addr, 0, value);
}
-/* { dg-final { scan-assembler "vstrw.u32" } } */
+/*
+**foo1:
+** ...
+** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
foo1 (uint32x4_t addr, uint32x4_t value)
{
- vstrwq_scatter_base (addr, 8, value);
+ return vstrwq_scatter_base (addr, 0, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrw.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
index b2cc6e555ae..e481191aa57 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
@@ -1,19 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo (uint32x4_t * addr, const int offset, float32x4_t value)
+foo (uint32x4_t *addr, float32x4_t value)
{
- vstrwq_scatter_base_wb_f32 (addr, 8, value);
+ return vstrwq_scatter_base_wb_f32 (addr, 0, value);
}
+
+/*
+**foo1:
+** ...
+** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo1 (uint32x4_t * addr, const int offset, float32x4_t value)
+foo1 (uint32x4_t *addr, float32x4_t value)
{
- vstrwq_scatter_base_wb (addr, 8, value);
+ return vstrwq_scatter_base_wb (addr, 0, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c
index 4befd49d7b9..8d217d46230 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c
@@ -1,19 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p)
+foo (uint32x4_t *addr, float32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_base_wb_p_f32 (addr, 8, value, p);
+ return vstrwq_scatter_base_wb_p_f32 (addr, 0, value, p);
}
+
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo1 (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p)
+foo1 (uint32x4_t *addr, float32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_base_wb_p (addr, 8, value, p);
+ return vstrwq_scatter_base_wb_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c
index dfb1827c4f0..afc47adcd7f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c
@@ -1,19 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p)
+foo (uint32x4_t *addr, int32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_base_wb_p_s32 (addr, 8, value, p);
+ return vstrwq_scatter_base_wb_p_s32 (addr, 0, value, p);
}
+
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo1 (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p)
+foo1 (uint32x4_t *addr, int32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_base_wb_p (addr, 8, value, p);
+ return vstrwq_scatter_base_wb_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c
index 4eb78c600be..65191c2f1ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c
@@ -1,19 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p)
+foo (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_base_wb_p_u32 (addr, 8, value, p);
+ return vstrwq_scatter_base_wb_p_u32 (addr, 0, value, p);
}
+
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo1 (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p)
+foo1 (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_base_wb_p (addr, 8, value, p);
+ return vstrwq_scatter_base_wb_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
index 618dbaf5aa6..b6a9f6cd1f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
@@ -1,19 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo (uint32x4_t * addr, const int offset, int32x4_t value)
+foo (uint32x4_t *addr, int32x4_t value)
{
- vstrwq_scatter_base_wb_s32 (addr, 8, value);
+ return vstrwq_scatter_base_wb_s32 (addr, 0, value);
}
+
+/*
+**foo1:
+** ...
+** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo1 (uint32x4_t * addr, const int offset, int32x4_t value)
+foo1 (uint32x4_t *addr, int32x4_t value)
{
- vstrwq_scatter_base_wb (addr, 8, value);
+ return vstrwq_scatter_base_wb (addr, 0, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
index 912a4590cf5..81a278f4e2b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
@@ -1,19 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo (uint32x4_t * addr, uint32x4_t value)
+foo (uint32x4_t *addr, uint32x4_t value)
{
- vstrwq_scatter_base_wb_u32 (addr, 8, value);
+ return vstrwq_scatter_base_wb_u32 (addr, 0, value);
}
+
+/*
+**foo1:
+** ...
+** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo1 (uint32x4_t * addr, uint32x4_t value)
+foo1 (uint32x4_t *addr, uint32x4_t value)
{
- vstrwq_scatter_base_wb (addr, 8, value);
+ return vstrwq_scatter_base_wb (addr, 0, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
index c14d3ce607b..b81df68aa21 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (float32_t * base, uint32x4_t offset, float32x4_t value)
+foo (float32_t *base, uint32x4_t offset, float32x4_t value)
{
- vstrwq_scatter_offset_f32 (base, offset, value);
+ return vstrwq_scatter_offset_f32 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/*
+**foo1:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value)
+foo1 (float32_t *base, uint32x4_t offset, float32x4_t value)
{
- vstrwq_scatter_offset (base, offset, value);
+ return vstrwq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
index 115be56ec00..8aee42f76a3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
+foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_offset_p_f32 (base, offset, value, p);
+ return vstrwq_scatter_offset_p_f32 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
+foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_offset_p (base, offset, value, p);
+ return vstrwq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
index 48652af3cff..9c74ae7a8d8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_offset_p_s32 (base, offset, value, p);
+ return vstrwq_scatter_offset_p_s32 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_offset_p (base, offset, value, p);
+ return vstrwq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
index dcd42ec453f..015a202b548 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_offset_p_u32 (base, offset, value, p);
+ return vstrwq_scatter_offset_p_u32 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_offset_p (base, offset, value, p);
+ return vstrwq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
index 04672e5a4aa..df373111b78 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (int32_t * base, uint32x4_t offset, int32x4_t value)
+foo (int32_t *base, uint32x4_t offset, int32x4_t value)
{
- vstrwq_scatter_offset_s32 (base, offset, value);
+ return vstrwq_scatter_offset_s32 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/*
+**foo1:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value)
+foo1 (int32_t *base, uint32x4_t offset, int32x4_t value)
{
- vstrwq_scatter_offset (base, offset, value);
+ return vstrwq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
index e3d312550c6..a74696ca273 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value)
+foo (uint32_t *base, uint32x4_t offset, uint32x4_t value)
{
- vstrwq_scatter_offset_u32 (base, offset, value);
+ return vstrwq_scatter_offset_u32 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/*
+**foo1:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value)
+foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value)
{
- vstrwq_scatter_offset (base, offset, value);
+ return vstrwq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c
index b20c4c7ed3a..1c9b29a57b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
void
-foo (float32_t * base, uint32x4_t offset, float32x4_t value)
+foo (float32_t *base, uint32x4_t offset, float32x4_t value)
{
- vstrwq_scatter_shifted_offset_f32 (base, offset, value);
+ return vstrwq_scatter_shifted_offset_f32 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/*
+**foo1:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
void
-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value)
+foo1 (float32_t *base, uint32x4_t offset, float32x4_t value)
{
- vstrwq_scatter_shifted_offset (base, offset, value);
+ return vstrwq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c
index 1682f702dc6..08e1572854e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
void
-foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
+foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p);
+ return vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
void
-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
+foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_shifted_offset_p (base, offset, value, p);
+ return vstrwq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c
index eef6ea6e196..2b8f8a7d61f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
void
-foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p);
+ return vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
void
-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_shifted_offset_p (base, offset, value, p);
+ return vstrwq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c
index b11e7e04dc4..3e4e87bf79a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
void
-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p);
+ return vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
void
-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
{
- vstrwq_scatter_shifted_offset_p (base, offset, value, p);
+ return vstrwq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c
index 8ac25c47554..7f25490a69a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
void
-foo (int32_t * base, uint32x4_t offset, int32x4_t value)
+foo (int32_t *base, uint32x4_t offset, int32x4_t value)
{
- vstrwq_scatter_shifted_offset_s32 (base, offset, value);
+ return vstrwq_scatter_shifted_offset_s32 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/*
+**foo1:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
void
-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value)
+foo1 (int32_t *base, uint32x4_t offset, int32x4_t value)
{
- vstrwq_scatter_shifted_offset (base, offset, value);
+ return vstrwq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c
index 1ce0ddacc7a..a96220c4f6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
void
-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value)
+foo (uint32_t *base, uint32x4_t offset, uint32x4_t value)
{
- vstrwq_scatter_shifted_offset_u32 (base, offset, value);
+ return vstrwq_scatter_shifted_offset_u32 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/*
+**foo1:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
+** ...
+*/
void
-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value)
+foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value)
{
- vstrwq_scatter_shifted_offset (base, offset, value);
+ return vstrwq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
index 4aec9935b84..df554af79a6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint32_t * addr, uint32x4_t value)
+foo (uint32_t *base, uint32x4_t value)
{
- vstrwq_u32 (addr, value);
+ return vstrwq_u32 (base, value);
}
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/*
+**foo1:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint32_t * addr, uint32x4_t value)
+foo1 (uint32_t *base, uint32x4_t value)
{
- vstrwq (addr, value);
+ return vstrwq (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--
2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 03/10] arm: Mve backend + testsuite fixes 2
2023-04-28 11:29 [PATCH 01/10] arm: Mve testsuite improvements Andrea Corallo
2023-04-28 11:29 ` [PATCH 02/10] arm: Fix vstrwq* backend + testsuite Andrea Corallo
@ 2023-04-28 11:29 ` Andrea Corallo
2023-04-28 16:40 ` Kyrylo Tkachov
2023-04-28 11:29 ` [PATCH 04/10] arm: Stop vadcq, vsbcq intrinsics from overwriting the FPSCR NZ flags Andrea Corallo
` (7 subsequent siblings)
9 siblings, 1 reply; 31+ messages in thread
From: Andrea Corallo @ 2023-04-28 11:29 UTC (permalink / raw)
To: gcc-patches; +Cc: kyrylo.tkachov, Richard.Earnshaw, Andrea Corallo
Hi all,
this patch improves a number of MVE tests in the testsuite for more
precise and better coverage using check-function-bodies instead of
scan-assembler checks. Also all intrusctions prescribed in the
ACLE[1] are now checked.
Also a number of simple fixes are done in the backend to fix
capitalization and spacing.
Best Regards
Andrea
[1] <https://github.com/ARM-software/acle>
gcc/ChangeLog:
* config/arm/mve.md (mve_vrndq_m_f<mode>, mve_vrev64q_f<mode>)
(mve_vrev32q_fv8hf, mve_vcvttq_f32_f16v4sf)
(mve_vcvtbq_f32_f16v4sf, mve_vcvtq_to_f_<supf><mode>)
(mve_vrev64q_<supf><mode>, mve_vcvtq_from_f_<supf><mode>)
(mve_vmovltq_<supf><mode>, mve_vmovlbq_<supf><mode>)
(mve_vcvtpq_<supf><mode>, mve_vcvtnq_<supf><mode>)
(mve_vcvtmq_<supf><mode>, mve_vcvtaq_<supf><mode>)
(mve_vmvnq_n_<supf><mode>, mve_vrev16q_<supf>v16qi)
(mve_vctp<MVE_vctp>q<MVE_vpred>, mve_vbrsrq_n_f<mode>)
(mve_vbrsrq_n_<supf><mode>, mve_vandq_f<mode>, mve_vbicq_f<mode>)
(mve_vbicq_n_<supf><mode>, mve_vctp<MVE_vctp>q_m<MVE_vpred>)
(mve_vcvtbq_f16_f32v8hf, mve_vcvttq_f16_f32v8hf)
(mve_veorq_f<mode>, mve_vmlaldavxq_s<mode>, mve_vmlsldavq_s<mode>)
(mve_vmlsldavxq_s<mode>, mve_vornq_f<mode>, mve_vorrq_f<mode>)
(mve_vrmlaldavhxq_sv4si, mve_vbicq_m_n_<supf><mode>)
(mve_vcvtq_m_to_f_<supf><mode>, mve_vshlcq_<supf><mode>)
(mve_vmvnq_m_<supf><mode>, mve_vpselq_<supf><mode>)
(mve_vcvtbq_m_f16_f32v8hf, mve_vcvtbq_m_f32_f16v4sf)
(mve_vcvttq_m_f16_f32v8hf, mve_vcvttq_m_f32_f16v4sf)
(mve_vmlaldavq_p_<supf><mode>, mve_vmlsldavaq_s<mode>)
(mve_vmlsldavaxq_s<mode>, mve_vmlsldavq_p_s<mode>)
(mve_vmlsldavxq_p_s<mode>, mve_vmvnq_m_n_<supf><mode>)
(mve_vorrq_m_n_<supf><mode>, mve_vpselq_f<mode>)
(mve_vrev32q_m_fv8hf, mve_vrev32q_m_<supf><mode>)
(mve_vrev64q_m_f<mode>, mve_vrmlaldavhaxq_sv4si)
(mve_vrmlaldavhxq_p_sv4si, mve_vrmlsldavhaxq_sv4si)
(mve_vrmlsldavhq_p_sv4si, mve_vrmlsldavhxq_p_sv4si)
(mve_vrev16q_m_<supf>v16qi, mve_vrmlaldavhq_p_<supf>v4si)
(mve_vrmlsldavhaq_sv4si, mve_vandq_m_<supf><mode>)
(mve_vbicq_m_<supf><mode>, mve_veorq_m_<supf><mode>)
(mve_vornq_m_<supf><mode>, mve_vorrq_m_<supf><mode>)
(mve_vandq_m_f<mode>, mve_vbicq_m_f<mode>, mve_veorq_m_f<mode>)
(mve_vornq_m_f<mode>, mve_vorrq_m_f<mode>)
(mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn)
(mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn)
(mve_vstrdq_scatter_base_wb_p_<supf>v2di) : Fix spacing and
capitalization in the emitted asm.
gcc/testsuite/ChangeLog:
* gcc.target/arm/mve/intrinsics/asrl.c: Use
check-function-bodies instead of scan-assembler checks. Use
extern "C" for C++ testing.
* gcc.target/arm/mve/intrinsics/lsll.c: Likewise.
* gcc.target/arm/mve/intrinsics/sqrshr.c: Likewise.
* gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c: Likewise.
* gcc.target/arm/mve/intrinsics/sqshl.c: Likewise.
* gcc.target/arm/mve/intrinsics/sqshll.c: Likewise.
* gcc.target/arm/mve/intrinsics/srshr.c: Likewise.
* gcc.target/arm/mve/intrinsics/srshrl.c: Likewise.
* gcc.target/arm/mve/intrinsics/uqrshl.c: Likewise.
* gcc.target/arm/mve/intrinsics/uqrshll_sat48.c: Likewise.
* gcc.target/arm/mve/intrinsics/uqshl.c: Likewise.
* gcc.target/arm/mve/intrinsics/uqshll.c: Likewise.
* gcc.target/arm/mve/intrinsics/urshr.c: Likewise.
* gcc.target/arm/mve/intrinsics/urshrl.c: Likewise.
* gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vadciq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vadciq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vadcq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vadcq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp16q.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp16q_m.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp32q.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp32q_m.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp64q.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp64q_m.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp8q.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp8q_m.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmaq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmaq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmsq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmsq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavxq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpnot.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev16q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev16q_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndaq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndaq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndmq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndmq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndnq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndnq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndpq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndpq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndxq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndxq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_r_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_r_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_r_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_r_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_r_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_r_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c: Likewise.
---
gcc/config/arm/mve.md | 146 +++++++++---------
.../gcc.target/arm/mve/intrinsics/asrl.c | 21 ++-
.../gcc.target/arm/mve/intrinsics/lsll.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/sqrshr.c | 21 ++-
.../arm/mve/intrinsics/sqrshrl_sat48.c | 21 ++-
.../gcc.target/arm/mve/intrinsics/sqshl.c | 21 ++-
.../gcc.target/arm/mve/intrinsics/sqshll.c | 21 ++-
.../gcc.target/arm/mve/intrinsics/srshr.c | 21 ++-
.../gcc.target/arm/mve/intrinsics/srshrl.c | 21 ++-
.../gcc.target/arm/mve/intrinsics/uqrshl.c | 33 +++-
.../arm/mve/intrinsics/uqrshll_sat48.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/uqshl.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/uqshll.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/urshr.c | 35 ++++-
.../gcc.target/arm/mve/intrinsics/urshrl.c | 33 +++-
.../arm/mve/intrinsics/vadciq_m_s32.c | 50 +++++-
.../arm/mve/intrinsics/vadciq_m_u32.c | 50 +++++-
.../arm/mve/intrinsics/vadciq_s32.c | 40 ++++-
.../arm/mve/intrinsics/vadciq_u32.c | 40 ++++-
.../arm/mve/intrinsics/vadcq_m_s32.c | 62 +++++++-
.../arm/mve/intrinsics/vadcq_m_u32.c | 62 +++++++-
.../gcc.target/arm/mve/intrinsics/vadcq_s32.c | 52 ++++++-
.../gcc.target/arm/mve/intrinsics/vadcq_u32.c | 52 ++++++-
.../gcc.target/arm/mve/intrinsics/vandq_f16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vandq_f32.c | 24 ++-
.../arm/mve/intrinsics/vandq_m_f16.c | 34 +++-
.../arm/mve/intrinsics/vandq_m_f32.c | 34 +++-
.../arm/mve/intrinsics/vandq_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vandq_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vandq_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vandq_m_u16.c | 34 +++-
.../arm/mve/intrinsics/vandq_m_u32.c | 34 +++-
.../arm/mve/intrinsics/vandq_m_u8.c | 34 +++-
.../gcc.target/arm/mve/intrinsics/vandq_s16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vandq_s32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vandq_s8.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vandq_u16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vandq_u32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vandq_u8.c | 24 ++-
.../arm/mve/intrinsics/vandq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vandq_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vandq_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vandq_x_s32.c | 33 +++-
.../arm/mve/intrinsics/vandq_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vandq_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vandq_x_u32.c | 33 +++-
.../arm/mve/intrinsics/vandq_x_u8.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/vbicq_f16.c | 23 ++-
.../gcc.target/arm/mve/intrinsics/vbicq_f32.c | 23 ++-
.../arm/mve/intrinsics/vbicq_m_f16.c | 34 +++-
.../arm/mve/intrinsics/vbicq_m_f32.c | 34 +++-
.../arm/mve/intrinsics/vbicq_m_n_s16.c | 37 ++++-
.../arm/mve/intrinsics/vbicq_m_n_s32.c | 33 +++-
.../arm/mve/intrinsics/vbicq_m_n_u16.c | 33 +++-
.../arm/mve/intrinsics/vbicq_m_n_u32.c | 33 +++-
.../arm/mve/intrinsics/vbicq_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vbicq_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vbicq_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vbicq_m_u16.c | 34 +++-
.../arm/mve/intrinsics/vbicq_m_u32.c | 34 +++-
.../arm/mve/intrinsics/vbicq_m_u8.c | 34 +++-
.../arm/mve/intrinsics/vbicq_n_s16.c | 23 ++-
.../arm/mve/intrinsics/vbicq_n_s32.c | 23 ++-
.../arm/mve/intrinsics/vbicq_n_u16.c | 23 ++-
.../arm/mve/intrinsics/vbicq_n_u32.c | 23 ++-
.../gcc.target/arm/mve/intrinsics/vbicq_s16.c | 23 ++-
.../gcc.target/arm/mve/intrinsics/vbicq_s32.c | 23 ++-
.../gcc.target/arm/mve/intrinsics/vbicq_s8.c | 23 ++-
.../gcc.target/arm/mve/intrinsics/vbicq_u16.c | 23 ++-
.../gcc.target/arm/mve/intrinsics/vbicq_u32.c | 23 ++-
.../gcc.target/arm/mve/intrinsics/vbicq_u8.c | 23 ++-
.../arm/mve/intrinsics/vbicq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vbicq_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vbicq_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vbicq_x_s32.c | 33 +++-
.../arm/mve/intrinsics/vbicq_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vbicq_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vbicq_x_u32.c | 33 +++-
.../arm/mve/intrinsics/vbicq_x_u8.c | 33 +++-
.../arm/mve/intrinsics/vbrsrq_m_n_f16.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_m_n_f32.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_m_n_s8.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_m_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_m_n_u8.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_n_f16.c | 24 ++-
.../arm/mve/intrinsics/vbrsrq_n_f32.c | 24 ++-
.../arm/mve/intrinsics/vbrsrq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vbrsrq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vbrsrq_n_s8.c | 24 ++-
.../arm/mve/intrinsics/vbrsrq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vbrsrq_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vbrsrq_n_u8.c | 24 ++-
.../arm/mve/intrinsics/vbrsrq_x_n_f16.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_x_n_f32.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_x_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_x_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_x_n_s8.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_x_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_x_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_x_n_u8.c | 34 +++-
.../arm/mve/intrinsics/vcmpgtq_n_f16.c | 2 +-
.../gcc.target/arm/mve/intrinsics/vctp16q.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/vctp16q_m.c | 42 ++++-
.../gcc.target/arm/mve/intrinsics/vctp32q.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/vctp32q_m.c | 42 ++++-
.../gcc.target/arm/mve/intrinsics/vctp64q.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/vctp64q_m.c | 42 ++++-
.../gcc.target/arm/mve/intrinsics/vctp8q.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/vctp8q_m.c | 42 ++++-
.../arm/mve/intrinsics/vcvtaq_m_s16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtaq_m_s32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtaq_m_u16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtaq_m_u32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtaq_s16_f16.c | 17 +-
.../arm/mve/intrinsics/vcvtaq_s32_f32.c | 17 +-
.../arm/mve/intrinsics/vcvtaq_u16_f16.c | 19 ++-
.../arm/mve/intrinsics/vcvtaq_u32_f32.c | 19 ++-
.../arm/mve/intrinsics/vcvtaq_x_s16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtaq_x_s32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtaq_x_u16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtaq_x_u32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtbq_f16_f32.c | 17 +-
.../arm/mve/intrinsics/vcvtbq_f32_f16.c | 17 +-
.../arm/mve/intrinsics/vcvtbq_m_f16_f32.c | 26 +++-
.../arm/mve/intrinsics/vcvtbq_m_f32_f16.c | 26 +++-
.../arm/mve/intrinsics/vcvtbq_x_f32_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtmq_m_s16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtmq_m_s32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtmq_m_u16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtmq_m_u32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtmq_s16_f16.c | 17 +-
.../arm/mve/intrinsics/vcvtmq_s32_f32.c | 17 +-
.../arm/mve/intrinsics/vcvtmq_u16_f16.c | 19 ++-
.../arm/mve/intrinsics/vcvtmq_u32_f32.c | 19 ++-
.../arm/mve/intrinsics/vcvtmq_x_s16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtmq_x_s32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtmq_x_u16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtmq_x_u32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtnq_m_s16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtnq_m_s32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtnq_m_u16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtnq_m_u32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtnq_s16_f16.c | 17 +-
.../arm/mve/intrinsics/vcvtnq_s32_f32.c | 17 +-
.../arm/mve/intrinsics/vcvtnq_u16_f16.c | 19 ++-
.../arm/mve/intrinsics/vcvtnq_u32_f32.c | 17 +-
.../arm/mve/intrinsics/vcvtnq_x_s16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtnq_x_s32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtnq_x_u16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtnq_x_u32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtpq_m_s16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtpq_m_s32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtpq_m_u16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtpq_m_u32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtpq_s16_f16.c | 17 +-
.../arm/mve/intrinsics/vcvtpq_s32_f32.c | 17 +-
.../arm/mve/intrinsics/vcvtpq_u16_f16.c | 19 ++-
.../arm/mve/intrinsics/vcvtpq_u32_f32.c | 19 ++-
.../arm/mve/intrinsics/vcvtpq_x_s16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtpq_x_s32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtpq_x_u16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtpq_x_u32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtq_f16_s16.c | 30 +++-
.../arm/mve/intrinsics/vcvtq_f16_u16.c | 30 +++-
.../arm/mve/intrinsics/vcvtq_f32_s32.c | 30 +++-
.../arm/mve/intrinsics/vcvtq_f32_u32.c | 30 +++-
.../arm/mve/intrinsics/vcvtq_m_f16_s16.c | 33 +++-
.../arm/mve/intrinsics/vcvtq_m_f16_u16.c | 33 +++-
.../arm/mve/intrinsics/vcvtq_m_f32_s32.c | 33 +++-
.../arm/mve/intrinsics/vcvtq_m_f32_u32.c | 33 +++-
.../arm/mve/intrinsics/vcvtq_m_n_f16_s16.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_m_n_f16_u16.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_m_n_f32_s32.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_m_n_f32_u32.c | 38 ++++-
.../arm/mve/intrinsics/vcvtq_m_n_s16_f16.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_m_n_s32_f32.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_m_n_u16_f16.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_m_n_u32_f32.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_m_s16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtq_m_s32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtq_m_u16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtq_m_u32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtq_n_f16_s16.c | 24 ++-
.../arm/mve/intrinsics/vcvtq_n_f16_u16.c | 24 ++-
.../arm/mve/intrinsics/vcvtq_n_f32_s32.c | 24 ++-
.../arm/mve/intrinsics/vcvtq_n_f32_u32.c | 24 ++-
.../arm/mve/intrinsics/vcvtq_n_s16_f16.c | 17 +-
.../arm/mve/intrinsics/vcvtq_n_s32_f32.c | 17 +-
.../arm/mve/intrinsics/vcvtq_n_u16_f16.c | 17 +-
.../arm/mve/intrinsics/vcvtq_n_u32_f32.c | 17 +-
.../arm/mve/intrinsics/vcvtq_s16_f16.c | 17 +-
.../arm/mve/intrinsics/vcvtq_s32_f32.c | 17 +-
.../arm/mve/intrinsics/vcvtq_u16_f16.c | 19 ++-
.../arm/mve/intrinsics/vcvtq_u32_f32.c | 19 ++-
.../arm/mve/intrinsics/vcvtq_x_f16_s16.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_x_f16_u16.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_x_f32_s32.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_x_f32_u32.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_x_n_f16_s16.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_x_n_f16_u16.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_x_n_f32_s32.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_x_n_f32_u32.c | 38 ++++-
.../arm/mve/intrinsics/vcvtq_x_n_s16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtq_x_n_s32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtq_x_n_u16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtq_x_n_u32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtq_x_s16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtq_x_s32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtq_x_u16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtq_x_u32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvttq_f16_f32.c | 17 +-
.../arm/mve/intrinsics/vcvttq_f32_f16.c | 17 +-
.../arm/mve/intrinsics/vcvttq_m_f16_f32.c | 26 +++-
.../arm/mve/intrinsics/vcvttq_m_f32_f16.c | 26 +++-
.../arm/mve/intrinsics/vcvttq_x_f32_f16.c | 22 ++-
.../gcc.target/arm/mve/intrinsics/veorq_f16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/veorq_f32.c | 24 ++-
.../arm/mve/intrinsics/veorq_m_f16.c | 34 +++-
.../arm/mve/intrinsics/veorq_m_f32.c | 34 +++-
.../arm/mve/intrinsics/veorq_m_s16.c | 34 +++-
.../arm/mve/intrinsics/veorq_m_s32.c | 34 +++-
.../arm/mve/intrinsics/veorq_m_s8.c | 34 +++-
.../arm/mve/intrinsics/veorq_m_u16.c | 34 +++-
.../arm/mve/intrinsics/veorq_m_u32.c | 34 +++-
.../arm/mve/intrinsics/veorq_m_u8.c | 34 +++-
.../gcc.target/arm/mve/intrinsics/veorq_s16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/veorq_s32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/veorq_s8.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/veorq_u16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/veorq_u32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/veorq_u8.c | 24 ++-
.../arm/mve/intrinsics/veorq_x_f16.c | 34 +++-
.../arm/mve/intrinsics/veorq_x_f32.c | 34 +++-
.../arm/mve/intrinsics/veorq_x_s16.c | 34 +++-
.../arm/mve/intrinsics/veorq_x_s32.c | 34 +++-
.../arm/mve/intrinsics/veorq_x_s8.c | 34 +++-
.../arm/mve/intrinsics/veorq_x_u16.c | 34 +++-
.../arm/mve/intrinsics/veorq_x_u32.c | 34 +++-
.../arm/mve/intrinsics/veorq_x_u8.c | 34 +++-
.../gcc.target/arm/mve/intrinsics/vfmaq_f16.c | 32 +++-
.../gcc.target/arm/mve/intrinsics/vfmaq_f32.c | 32 +++-
.../arm/mve/intrinsics/vfmaq_m_f16.c | 42 ++++-
.../arm/mve/intrinsics/vfmaq_m_f32.c | 42 ++++-
.../arm/mve/intrinsics/vfmaq_m_n_f16.c | 58 ++++++-
.../arm/mve/intrinsics/vfmaq_m_n_f32.c | 58 ++++++-
.../arm/mve/intrinsics/vfmaq_n_f16.c | 44 +++++-
.../arm/mve/intrinsics/vfmaq_n_f32.c | 44 +++++-
.../arm/mve/intrinsics/vfmasq_m_n_f16.c | 2 +-
.../arm/mve/intrinsics/vfmasq_m_n_f32.c | 2 +-
.../arm/mve/intrinsics/vfmasq_n_f16.c | 44 +++++-
.../arm/mve/intrinsics/vfmasq_n_f32.c | 44 +++++-
.../gcc.target/arm/mve/intrinsics/vfmsq_f16.c | 32 +++-
.../gcc.target/arm/mve/intrinsics/vfmsq_f32.c | 32 +++-
.../arm/mve/intrinsics/vfmsq_m_f16.c | 42 ++++-
.../arm/mve/intrinsics/vfmsq_m_f32.c | 42 ++++-
.../arm/mve/intrinsics/vhcaddq_rot270_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vhcaddq_rot270_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vhcaddq_rot270_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vhcaddq_rot270_s16.c | 24 ++-
.../arm/mve/intrinsics/vhcaddq_rot270_s32.c | 24 ++-
.../arm/mve/intrinsics/vhcaddq_rot270_s8.c | 24 ++-
.../arm/mve/intrinsics/vhcaddq_rot270_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vhcaddq_rot270_x_s32.c | 33 +++-
.../arm/mve/intrinsics/vhcaddq_rot270_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vhcaddq_rot90_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vhcaddq_rot90_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vhcaddq_rot90_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vhcaddq_rot90_s16.c | 24 ++-
.../arm/mve/intrinsics/vhcaddq_rot90_s32.c | 24 ++-
.../arm/mve/intrinsics/vhcaddq_rot90_s8.c | 24 ++-
.../arm/mve/intrinsics/vhcaddq_rot90_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vhcaddq_rot90_x_s32.c | 33 +++-
.../arm/mve/intrinsics/vhcaddq_rot90_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vmladavq_p_s16.c | 40 ++++-
.../arm/mve/intrinsics/vmladavq_p_s32.c | 40 ++++-
.../arm/mve/intrinsics/vmladavq_p_s8.c | 40 ++++-
.../arm/mve/intrinsics/vmladavq_p_u16.c | 40 ++++-
.../arm/mve/intrinsics/vmladavq_p_u32.c | 40 ++++-
.../arm/mve/intrinsics/vmladavq_p_u8.c | 40 ++++-
.../arm/mve/intrinsics/vmladavq_s16.c | 32 +++-
.../arm/mve/intrinsics/vmladavq_s32.c | 32 +++-
.../arm/mve/intrinsics/vmladavq_s8.c | 32 +++-
.../arm/mve/intrinsics/vmladavq_u16.c | 32 +++-
.../arm/mve/intrinsics/vmladavq_u32.c | 32 +++-
.../arm/mve/intrinsics/vmladavq_u8.c | 32 +++-
.../arm/mve/intrinsics/vmladavxq_p_s16.c | 40 ++++-
.../arm/mve/intrinsics/vmladavxq_p_s32.c | 40 ++++-
.../arm/mve/intrinsics/vmladavxq_p_s8.c | 40 ++++-
.../arm/mve/intrinsics/vmladavxq_s16.c | 32 +++-
.../arm/mve/intrinsics/vmladavxq_s32.c | 32 +++-
.../arm/mve/intrinsics/vmladavxq_s8.c | 32 +++-
.../arm/mve/intrinsics/vmlaldavaq_p_s16.c | 40 ++++-
.../arm/mve/intrinsics/vmlaldavaq_p_s32.c | 40 ++++-
.../arm/mve/intrinsics/vmlaldavaq_p_u16.c | 56 ++++++-
.../arm/mve/intrinsics/vmlaldavaq_p_u32.c | 56 ++++++-
.../arm/mve/intrinsics/vmlaldavaq_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlaldavaq_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlaldavaq_u16.c | 44 +++++-
.../arm/mve/intrinsics/vmlaldavaq_u32.c | 44 +++++-
.../arm/mve/intrinsics/vmlaldavaxq_p_s16.c | 2 +-
.../arm/mve/intrinsics/vmlaldavaxq_p_s32.c | 2 +-
.../arm/mve/intrinsics/vmlaldavaxq_s16.c | 2 +-
.../arm/mve/intrinsics/vmlaldavaxq_s32.c | 2 +-
.../arm/mve/intrinsics/vmlaldavq_p_s16.c | 40 ++++-
.../arm/mve/intrinsics/vmlaldavq_p_s32.c | 40 ++++-
.../arm/mve/intrinsics/vmlaldavq_p_u16.c | 40 ++++-
.../arm/mve/intrinsics/vmlaldavq_p_u32.c | 40 ++++-
.../arm/mve/intrinsics/vmlaldavq_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlaldavq_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlaldavq_u16.c | 32 +++-
.../arm/mve/intrinsics/vmlaldavq_u32.c | 32 +++-
.../arm/mve/intrinsics/vmlaldavxq_p_s16.c | 40 ++++-
.../arm/mve/intrinsics/vmlaldavxq_p_s32.c | 40 ++++-
.../arm/mve/intrinsics/vmlaldavxq_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlaldavxq_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlaq_m_n_s16.c | 42 ++++-
.../arm/mve/intrinsics/vmlaq_m_n_s32.c | 42 ++++-
.../arm/mve/intrinsics/vmlaq_m_n_s8.c | 42 ++++-
.../arm/mve/intrinsics/vmlaq_m_n_u16.c | 58 ++++++-
.../arm/mve/intrinsics/vmlaq_m_n_u32.c | 58 ++++++-
.../arm/mve/intrinsics/vmlaq_m_n_u8.c | 58 ++++++-
.../arm/mve/intrinsics/vmlaq_n_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlaq_n_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlaq_n_s8.c | 32 +++-
.../arm/mve/intrinsics/vmlaq_n_u16.c | 44 +++++-
.../arm/mve/intrinsics/vmlaq_n_u32.c | 44 +++++-
.../arm/mve/intrinsics/vmlaq_n_u8.c | 44 +++++-
.../arm/mve/intrinsics/vmlsdavaq_p_s16.c | 33 +++-
.../arm/mve/intrinsics/vmlsdavaq_p_s32.c | 33 +++-
.../arm/mve/intrinsics/vmlsdavaq_p_s8.c | 33 +++-
.../arm/mve/intrinsics/vmlsdavaq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavaq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavaq_s8.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavaxq_p_s16.c | 33 +++-
.../arm/mve/intrinsics/vmlsdavaxq_p_s32.c | 33 +++-
.../arm/mve/intrinsics/vmlsdavaxq_p_s8.c | 33 +++-
.../arm/mve/intrinsics/vmlsdavaxq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavaxq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavaxq_s8.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavq_p_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlsdavq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlsdavq_p_s8.c | 32 +++-
.../arm/mve/intrinsics/vmlsdavq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavq_s8.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavxq_p_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlsdavxq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlsdavxq_p_s8.c | 32 +++-
.../arm/mve/intrinsics/vmlsdavxq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavxq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavxq_s8.c | 24 ++-
.../arm/mve/intrinsics/vmlsldavaq_p_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlsldavaq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlsldavaq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmlsldavaq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmlsldavaxq_p_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlsldavaxq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlsldavaxq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmlsldavaxq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmlsldavq_p_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlsldavq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlsldavq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmlsldavq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmlsldavxq_p_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlsldavxq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlsldavxq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmlsldavxq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmovlbq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vmovlbq_m_s8.c | 33 +++-
.../arm/mve/intrinsics/vmovlbq_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vmovlbq_m_u8.c | 33 +++-
.../arm/mve/intrinsics/vmovlbq_s16.c | 28 +++-
.../arm/mve/intrinsics/vmovlbq_s8.c | 24 ++-
.../arm/mve/intrinsics/vmovlbq_u16.c | 28 +++-
.../arm/mve/intrinsics/vmovlbq_u8.c | 28 +++-
.../arm/mve/intrinsics/vmovlbq_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vmovlbq_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vmovlbq_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vmovlbq_x_u8.c | 33 +++-
.../arm/mve/intrinsics/vmovltq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vmovltq_m_s8.c | 33 +++-
.../arm/mve/intrinsics/vmovltq_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vmovltq_m_u8.c | 33 +++-
.../arm/mve/intrinsics/vmovltq_s16.c | 28 +++-
.../arm/mve/intrinsics/vmovltq_s8.c | 24 ++-
.../arm/mve/intrinsics/vmovltq_u16.c | 28 +++-
.../arm/mve/intrinsics/vmovltq_u8.c | 28 +++-
.../arm/mve/intrinsics/vmovltq_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vmovltq_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vmovltq_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vmovltq_x_u8.c | 33 +++-
.../arm/mve/intrinsics/vmovnbq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vmovnbq_m_s32.c | 33 +++-
.../arm/mve/intrinsics/vmovnbq_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vmovnbq_m_u32.c | 33 +++-
.../arm/mve/intrinsics/vmovnbq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmovnbq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmovnbq_u16.c | 24 ++-
.../arm/mve/intrinsics/vmovnbq_u32.c | 24 ++-
.../arm/mve/intrinsics/vmovntq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vmovntq_m_s32.c | 33 +++-
.../arm/mve/intrinsics/vmovntq_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vmovntq_m_u32.c | 33 +++-
.../arm/mve/intrinsics/vmovntq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmovntq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmovntq_u16.c | 24 ++-
.../arm/mve/intrinsics/vmovntq_u32.c | 24 ++-
.../arm/mve/intrinsics/vmvnq_m_n_s16.c | 37 ++++-
.../arm/mve/intrinsics/vmvnq_m_n_s32.c | 37 ++++-
.../arm/mve/intrinsics/vmvnq_m_n_u16.c | 37 ++++-
.../arm/mve/intrinsics/vmvnq_m_n_u32.c | 37 ++++-
.../arm/mve/intrinsics/vmvnq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vmvnq_m_s32.c | 33 +++-
.../arm/mve/intrinsics/vmvnq_m_s8.c | 33 +++-
.../arm/mve/intrinsics/vmvnq_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vmvnq_m_u32.c | 33 +++-
.../arm/mve/intrinsics/vmvnq_m_u8.c | 33 +++-
.../arm/mve/intrinsics/vmvnq_n_s16.c | 17 +-
.../arm/mve/intrinsics/vmvnq_n_s32.c | 19 ++-
.../arm/mve/intrinsics/vmvnq_n_u16.c | 19 ++-
.../arm/mve/intrinsics/vmvnq_n_u32.c | 19 ++-
.../gcc.target/arm/mve/intrinsics/vmvnq_s16.c | 28 +++-
.../gcc.target/arm/mve/intrinsics/vmvnq_s32.c | 28 +++-
.../gcc.target/arm/mve/intrinsics/vmvnq_s8.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vmvnq_u16.c | 28 +++-
.../gcc.target/arm/mve/intrinsics/vmvnq_u32.c | 28 +++-
.../gcc.target/arm/mve/intrinsics/vmvnq_u8.c | 28 +++-
.../arm/mve/intrinsics/vmvnq_x_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vmvnq_x_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vmvnq_x_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vmvnq_x_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vmvnq_x_s16.c | 34 +++-
.../arm/mve/intrinsics/vmvnq_x_s32.c | 34 +++-
.../arm/mve/intrinsics/vmvnq_x_s8.c | 34 +++-
.../arm/mve/intrinsics/vmvnq_x_u16.c | 34 +++-
.../arm/mve/intrinsics/vmvnq_x_u32.c | 34 +++-
.../arm/mve/intrinsics/vmvnq_x_u8.c | 34 +++-
.../gcc.target/arm/mve/intrinsics/vornq_f16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vornq_f32.c | 24 ++-
.../arm/mve/intrinsics/vornq_m_f16.c | 34 +++-
.../arm/mve/intrinsics/vornq_m_f32.c | 34 +++-
.../arm/mve/intrinsics/vornq_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vornq_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vornq_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vornq_m_u16.c | 34 +++-
.../arm/mve/intrinsics/vornq_m_u32.c | 34 +++-
.../arm/mve/intrinsics/vornq_m_u8.c | 34 +++-
.../gcc.target/arm/mve/intrinsics/vornq_s16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vornq_s32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vornq_s8.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vornq_u16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vornq_u32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vornq_u8.c | 24 ++-
.../arm/mve/intrinsics/vornq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vornq_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vornq_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vornq_x_s32.c | 33 +++-
.../arm/mve/intrinsics/vornq_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vornq_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vornq_x_u32.c | 33 +++-
.../arm/mve/intrinsics/vornq_x_u8.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/vorrq_f16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vorrq_f32.c | 24 ++-
.../arm/mve/intrinsics/vorrq_m_f16.c | 34 +++-
.../arm/mve/intrinsics/vorrq_m_f32.c | 34 +++-
.../arm/mve/intrinsics/vorrq_m_n_s16.c | 37 ++++-
.../arm/mve/intrinsics/vorrq_m_n_s32.c | 33 +++-
.../arm/mve/intrinsics/vorrq_m_n_u16.c | 33 +++-
.../arm/mve/intrinsics/vorrq_m_n_u32.c | 33 +++-
.../arm/mve/intrinsics/vorrq_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vorrq_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vorrq_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vorrq_m_u16.c | 34 +++-
.../arm/mve/intrinsics/vorrq_m_u32.c | 34 +++-
.../arm/mve/intrinsics/vorrq_m_u8.c | 34 +++-
.../arm/mve/intrinsics/vorrq_n_s16.c | 30 +++-
.../arm/mve/intrinsics/vorrq_n_s32.c | 30 +++-
.../arm/mve/intrinsics/vorrq_n_u16.c | 30 +++-
.../arm/mve/intrinsics/vorrq_n_u32.c | 32 +++-
.../gcc.target/arm/mve/intrinsics/vorrq_s16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vorrq_s32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vorrq_s8.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vorrq_u16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vorrq_u32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vorrq_u8.c | 24 ++-
.../arm/mve/intrinsics/vorrq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vorrq_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vorrq_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vorrq_x_s32.c | 33 +++-
.../arm/mve/intrinsics/vorrq_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vorrq_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vorrq_x_u32.c | 33 +++-
.../arm/mve/intrinsics/vorrq_x_u8.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/vpnot.c | 25 ++-
.../arm/mve/intrinsics/vpselq_f16.c | 28 +++-
.../arm/mve/intrinsics/vpselq_f32.c | 28 +++-
.../arm/mve/intrinsics/vpselq_s16.c | 28 +++-
.../arm/mve/intrinsics/vpselq_s32.c | 28 +++-
.../arm/mve/intrinsics/vpselq_s64.c | 28 +++-
.../gcc.target/arm/mve/intrinsics/vpselq_s8.c | 28 +++-
.../arm/mve/intrinsics/vpselq_u16.c | 28 +++-
.../arm/mve/intrinsics/vpselq_u32.c | 28 +++-
.../arm/mve/intrinsics/vpselq_u64.c | 28 +++-
.../gcc.target/arm/mve/intrinsics/vpselq_u8.c | 28 +++-
.../arm/mve/intrinsics/vqmovnbq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vqmovnbq_m_s32.c | 33 +++-
.../arm/mve/intrinsics/vqmovnbq_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vqmovnbq_m_u32.c | 33 +++-
.../arm/mve/intrinsics/vqmovnbq_s16.c | 24 ++-
.../arm/mve/intrinsics/vqmovnbq_s32.c | 24 ++-
.../arm/mve/intrinsics/vqmovnbq_u16.c | 24 ++-
.../arm/mve/intrinsics/vqmovnbq_u32.c | 24 ++-
.../arm/mve/intrinsics/vqmovntq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vqmovntq_m_s32.c | 33 +++-
.../arm/mve/intrinsics/vqmovntq_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vqmovntq_m_u32.c | 33 +++-
.../arm/mve/intrinsics/vqmovntq_s16.c | 24 ++-
.../arm/mve/intrinsics/vqmovntq_s32.c | 24 ++-
.../arm/mve/intrinsics/vqmovntq_u16.c | 24 ++-
.../arm/mve/intrinsics/vqmovntq_u32.c | 24 ++-
.../arm/mve/intrinsics/vqmovunbq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vqmovunbq_m_s32.c | 33 +++-
.../arm/mve/intrinsics/vqmovunbq_s16.c | 24 ++-
.../arm/mve/intrinsics/vqmovunbq_s32.c | 24 ++-
.../arm/mve/intrinsics/vqmovuntq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vqmovuntq_m_s32.c | 33 +++-
.../arm/mve/intrinsics/vqmovuntq_s16.c | 24 ++-
.../arm/mve/intrinsics/vqmovuntq_s32.c | 24 ++-
.../arm/mve/intrinsics/vqrdmladhq_m_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhq_m_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhq_m_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhq_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhq_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhq_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhxq_m_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhxq_m_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhxq_m_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhxq_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhxq_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhxq_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmlahq_m_n_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmlahq_m_n_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmlahq_m_n_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmlahq_n_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmlahq_n_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmlahq_n_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmlashq_m_n_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmlashq_m_n_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmlashq_m_n_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmlashq_n_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmlashq_n_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmlashq_n_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhq_m_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhq_m_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhq_m_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhq_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhq_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhq_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhxq_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhxq_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhxq_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_m_n_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_m_n_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_m_n_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_m_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_m_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_m_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_n_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_n_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_n_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_s8.c | 2 +-
.../arm/mve/intrinsics/vqrshlq_m_n_s16.c | 33 +++-
.../arm/mve/intrinsics/vqrshlq_m_n_s32.c | 33 +++-
.../arm/mve/intrinsics/vqrshlq_m_n_s8.c | 33 +++-
.../arm/mve/intrinsics/vqrshlq_m_n_u16.c | 33 +++-
.../arm/mve/intrinsics/vqrshlq_m_n_u32.c | 33 +++-
.../arm/mve/intrinsics/vqrshlq_m_n_u8.c | 33 +++-
.../arm/mve/intrinsics/vqrshlq_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vqrshlq_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vqrshlq_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vqrshlq_m_u16.c | 34 +++-
.../arm/mve/intrinsics/vqrshlq_m_u32.c | 34 +++-
.../arm/mve/intrinsics/vqrshlq_m_u8.c | 34 +++-
.../arm/mve/intrinsics/vqrshlq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_n_s8.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_n_u8.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_s16.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_s32.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_s8.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_u16.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_u32.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_u8.c | 24 ++-
.../arm/mve/intrinsics/vqrshrnbq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vqrshrnbq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vqrshrnbq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vqrshrnbq_m_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vqrshrnbq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqrshrnbq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vqrshrnbq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vqrshrnbq_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vqrshrntq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vqrshrntq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vqrshrntq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vqrshrntq_m_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vqrshrntq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqrshrntq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vqrshrntq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vqrshrntq_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vqrshrunbq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vqrshrunbq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vqrshrunbq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqrshrunbq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vqrshruntq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vqrshruntq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vqrshruntq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqrshruntq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_n_s8.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_n_u8.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_r_s16.c | 33 +++-
.../arm/mve/intrinsics/vqshlq_m_r_s32.c | 33 +++-
.../arm/mve/intrinsics/vqshlq_m_r_s8.c | 33 +++-
.../arm/mve/intrinsics/vqshlq_m_r_u16.c | 33 +++-
.../arm/mve/intrinsics/vqshlq_m_r_u32.c | 33 +++-
.../arm/mve/intrinsics/vqshlq_m_r_u8.c | 33 +++-
.../arm/mve/intrinsics/vqshlq_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_u16.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_u32.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_u8.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_n_s8.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_n_u8.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_r_s16.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_r_s32.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_r_s8.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_r_u16.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_r_u32.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_r_u8.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_s16.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_s32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vqshlq_s8.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_u16.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_u32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vqshlq_u8.c | 24 ++-
.../arm/mve/intrinsics/vqshluq_m_n_s16.c | 37 ++++-
.../arm/mve/intrinsics/vqshluq_m_n_s32.c | 37 ++++-
.../arm/mve/intrinsics/vqshluq_m_n_s8.c | 37 ++++-
.../arm/mve/intrinsics/vqshluq_n_s16.c | 28 +++-
.../arm/mve/intrinsics/vqshluq_n_s32.c | 28 +++-
.../arm/mve/intrinsics/vqshluq_n_s8.c | 28 +++-
.../arm/mve/intrinsics/vqshrnbq_m_n_s16.c | 38 ++++-
.../arm/mve/intrinsics/vqshrnbq_m_n_s32.c | 38 ++++-
.../arm/mve/intrinsics/vqshrnbq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vqshrnbq_m_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vqshrnbq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqshrnbq_n_s32.c | 28 +++-
.../arm/mve/intrinsics/vqshrnbq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vqshrnbq_n_u32.c | 28 +++-
.../arm/mve/intrinsics/vqshrntq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vqshrntq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vqshrntq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vqshrntq_m_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vqshrntq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqshrntq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vqshrntq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vqshrntq_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vqshrunbq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vqshrunbq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vqshrunbq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqshrunbq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vqshruntq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vqshruntq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vqshruntq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqshruntq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vqsubq_m_n_s16.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_n_s32.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_n_s8.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_n_u16.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_n_u32.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_n_u8.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_s16.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_s32.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_s8.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_u16.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_u32.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_u8.c | 2 +-
.../arm/mve/intrinsics/vqsubq_n_s16.c | 2 +-
.../arm/mve/intrinsics/vqsubq_n_s32.c | 2 +-
.../arm/mve/intrinsics/vqsubq_n_s8.c | 2 +-
.../arm/mve/intrinsics/vqsubq_n_u16.c | 2 +-
.../arm/mve/intrinsics/vqsubq_n_u32.c | 2 +-
.../arm/mve/intrinsics/vqsubq_n_u8.c | 2 +-
.../arm/mve/intrinsics/vqsubq_s16.c | 2 +-
.../arm/mve/intrinsics/vqsubq_s32.c | 2 +-
.../gcc.target/arm/mve/intrinsics/vqsubq_s8.c | 2 +-
.../arm/mve/intrinsics/vqsubq_u16.c | 2 +-
.../arm/mve/intrinsics/vqsubq_u32.c | 2 +-
.../gcc.target/arm/mve/intrinsics/vqsubq_u8.c | 2 +-
.../arm/mve/intrinsics/vrev16q_m_s8.c | 33 +++-
.../arm/mve/intrinsics/vrev16q_m_u8.c | 33 +++-
.../arm/mve/intrinsics/vrev16q_s8.c | 24 ++-
.../arm/mve/intrinsics/vrev16q_u8.c | 28 +++-
.../arm/mve/intrinsics/vrev16q_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vrev16q_x_u8.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_f16.c | 30 +++-
.../arm/mve/intrinsics/vrev32q_m_f16.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_m_s8.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_m_u8.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_s16.c | 28 +++-
.../arm/mve/intrinsics/vrev32q_s8.c | 24 ++-
.../arm/mve/intrinsics/vrev32q_u16.c | 28 +++-
.../arm/mve/intrinsics/vrev32q_u8.c | 28 +++-
.../arm/mve/intrinsics/vrev32q_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_x_u8.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_f16.c | 30 +++-
.../arm/mve/intrinsics/vrev64q_f32.c | 30 +++-
.../arm/mve/intrinsics/vrev64q_m_f16.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_m_f32.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_m_s32.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_m_s8.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_m_u32.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_m_u8.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_s16.c | 24 ++-
.../arm/mve/intrinsics/vrev64q_s32.c | 24 ++-
.../arm/mve/intrinsics/vrev64q_s8.c | 24 ++-
.../arm/mve/intrinsics/vrev64q_u16.c | 28 +++-
.../arm/mve/intrinsics/vrev64q_u32.c | 28 +++-
.../arm/mve/intrinsics/vrev64q_u8.c | 28 +++-
.../arm/mve/intrinsics/vrev64q_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_x_s32.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_x_u32.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_x_u8.c | 33 +++-
.../arm/mve/intrinsics/vrhaddq_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vrhaddq_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vrhaddq_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vrhaddq_m_u16.c | 34 +++-
.../arm/mve/intrinsics/vrhaddq_m_u32.c | 34 +++-
.../arm/mve/intrinsics/vrhaddq_m_u8.c | 34 +++-
.../arm/mve/intrinsics/vrhaddq_s16.c | 24 ++-
.../arm/mve/intrinsics/vrhaddq_s32.c | 24 ++-
.../arm/mve/intrinsics/vrhaddq_s8.c | 24 ++-
.../arm/mve/intrinsics/vrhaddq_u16.c | 24 ++-
.../arm/mve/intrinsics/vrhaddq_u32.c | 24 ++-
.../arm/mve/intrinsics/vrhaddq_u8.c | 24 ++-
.../arm/mve/intrinsics/vrhaddq_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vrhaddq_x_s32.c | 33 +++-
.../arm/mve/intrinsics/vrhaddq_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vrhaddq_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vrhaddq_x_u32.c | 33 +++-
.../arm/mve/intrinsics/vrhaddq_x_u8.c | 33 +++-
.../arm/mve/intrinsics/vrmlaldavhaq_p_s32.c | 2 +-
.../arm/mve/intrinsics/vrmlaldavhaq_p_u32.c | 2 +-
.../arm/mve/intrinsics/vrmlaldavhaq_s32.c | 2 +-
.../arm/mve/intrinsics/vrmlaldavhaq_u32.c | 2 +-
.../arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vrmlaldavhaxq_s32.c | 24 ++-
.../arm/mve/intrinsics/vrmlaldavhq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vrmlaldavhq_p_u32.c | 32 +++-
.../arm/mve/intrinsics/vrmlaldavhq_s32.c | 24 ++-
.../arm/mve/intrinsics/vrmlaldavhq_u32.c | 24 ++-
.../arm/mve/intrinsics/vrmlaldavhxq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vrmlaldavhxq_s32.c | 24 ++-
.../arm/mve/intrinsics/vrmlsldavhaq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vrmlsldavhaq_s32.c | 24 ++-
.../arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vrmlsldavhaxq_s32.c | 24 ++-
.../arm/mve/intrinsics/vrmlsldavhq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vrmlsldavhq_s32.c | 24 ++-
.../arm/mve/intrinsics/vrmlsldavhxq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vrmlsldavhxq_s32.c | 24 ++-
.../arm/mve/intrinsics/vrmulhq_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vrmulhq_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vrmulhq_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vrmulhq_m_u16.c | 34 +++-
.../arm/mve/intrinsics/vrmulhq_m_u32.c | 34 +++-
.../arm/mve/intrinsics/vrmulhq_m_u8.c | 34 +++-
.../arm/mve/intrinsics/vrmulhq_s16.c | 24 ++-
.../arm/mve/intrinsics/vrmulhq_s32.c | 24 ++-
.../arm/mve/intrinsics/vrmulhq_s8.c | 24 ++-
.../arm/mve/intrinsics/vrmulhq_u16.c | 24 ++-
.../arm/mve/intrinsics/vrmulhq_u32.c | 24 ++-
.../arm/mve/intrinsics/vrmulhq_u8.c | 24 ++-
.../arm/mve/intrinsics/vrmulhq_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vrmulhq_x_s32.c | 33 +++-
.../arm/mve/intrinsics/vrmulhq_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vrmulhq_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vrmulhq_x_u32.c | 33 +++-
.../arm/mve/intrinsics/vrmulhq_x_u8.c | 33 +++-
.../arm/mve/intrinsics/vrndaq_f16.c | 30 +++-
.../arm/mve/intrinsics/vrndaq_f32.c | 30 +++-
.../arm/mve/intrinsics/vrndaq_m_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndaq_m_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndaq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndaq_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndmq_f16.c | 30 +++-
.../arm/mve/intrinsics/vrndmq_f32.c | 30 +++-
.../arm/mve/intrinsics/vrndmq_m_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndmq_m_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndmq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndmq_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndnq_f16.c | 30 +++-
.../arm/mve/intrinsics/vrndnq_f32.c | 30 +++-
.../arm/mve/intrinsics/vrndnq_m_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndnq_m_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndnq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndnq_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndpq_f16.c | 30 +++-
.../arm/mve/intrinsics/vrndpq_f32.c | 30 +++-
.../arm/mve/intrinsics/vrndpq_m_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndpq_m_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndpq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndpq_x_f32.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/vrndq_f16.c | 30 +++-
.../gcc.target/arm/mve/intrinsics/vrndq_f32.c | 30 +++-
.../arm/mve/intrinsics/vrndq_m_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndq_m_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndq_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndxq_f16.c | 30 +++-
.../arm/mve/intrinsics/vrndxq_f32.c | 30 +++-
.../arm/mve/intrinsics/vrndxq_m_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndxq_m_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndxq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndxq_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vrshrnbq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vrshrnbq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vrshrnbq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vrshrnbq_m_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vrshrnbq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vrshrnbq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vrshrnbq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vrshrnbq_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vrshrntq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vrshrntq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vrshrntq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vrshrntq_m_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vrshrntq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vrshrntq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vrshrntq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vrshrntq_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vrshrq_m_n_s16.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_m_n_s32.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_m_n_s8.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_m_n_u16.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_m_n_u32.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_m_n_u8.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_n_s16.c | 28 +++-
.../arm/mve/intrinsics/vrshrq_n_s32.c | 28 +++-
.../arm/mve/intrinsics/vrshrq_n_s8.c | 28 +++-
.../arm/mve/intrinsics/vrshrq_n_u16.c | 28 +++-
.../arm/mve/intrinsics/vrshrq_n_u32.c | 28 +++-
.../arm/mve/intrinsics/vrshrq_n_u8.c | 28 +++-
.../arm/mve/intrinsics/vrshrq_x_n_s16.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_x_n_s32.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_x_n_s8.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_x_n_u16.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_x_n_u32.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_x_n_u8.c | 38 ++++-
.../arm/mve/intrinsics/vsbciq_m_s32.c | 50 +++++-
.../arm/mve/intrinsics/vsbciq_m_u32.c | 50 +++++-
.../arm/mve/intrinsics/vsbciq_s32.c | 42 ++++-
.../arm/mve/intrinsics/vsbciq_u32.c | 42 ++++-
.../arm/mve/intrinsics/vsbcq_m_s32.c | 66 +++++++-
.../arm/mve/intrinsics/vsbcq_m_u32.c | 67 +++++++-
.../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 52 ++++++-
.../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 52 ++++++-
.../arm/mve/intrinsics/vshlcq_m_s16.c | 42 ++++-
.../arm/mve/intrinsics/vshlcq_m_s32.c | 38 ++++-
.../arm/mve/intrinsics/vshlcq_m_s8.c | 38 ++++-
.../arm/mve/intrinsics/vshlcq_m_u16.c | 38 ++++-
.../arm/mve/intrinsics/vshlcq_m_u32.c | 38 ++++-
.../arm/mve/intrinsics/vshlcq_m_u8.c | 38 ++++-
.../arm/mve/intrinsics/vshlcq_s16.c | 28 +++-
.../arm/mve/intrinsics/vshlcq_s32.c | 28 +++-
.../gcc.target/arm/mve/intrinsics/vshlcq_s8.c | 28 +++-
.../arm/mve/intrinsics/vshlcq_u16.c | 28 +++-
.../arm/mve/intrinsics/vshlcq_u32.c | 28 +++-
.../gcc.target/arm/mve/intrinsics/vshlcq_u8.c | 28 +++-
.../arm/mve/intrinsics/vshllbq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vshllbq_m_n_s8.c | 34 +++-
.../arm/mve/intrinsics/vshllbq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vshllbq_m_n_u8.c | 34 +++-
.../arm/mve/intrinsics/vshllbq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vshllbq_n_s8.c | 24 ++-
.../arm/mve/intrinsics/vshllbq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vshllbq_n_u8.c | 24 ++-
.../arm/mve/intrinsics/vshllbq_x_n_s16.c | 40 ++++-
.../arm/mve/intrinsics/vshllbq_x_n_s8.c | 40 ++++-
.../arm/mve/intrinsics/vshllbq_x_n_u16.c | 40 ++++-
.../arm/mve/intrinsics/vshllbq_x_n_u8.c | 40 ++++-
.../arm/mve/intrinsics/vshlltq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vshlltq_m_n_s8.c | 34 +++-
.../arm/mve/intrinsics/vshlltq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vshlltq_m_n_u8.c | 34 +++-
.../arm/mve/intrinsics/vshlltq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vshlltq_n_s8.c | 24 ++-
.../arm/mve/intrinsics/vshlltq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vshlltq_n_u8.c | 24 ++-
.../arm/mve/intrinsics/vshlltq_x_n_s16.c | 40 ++++-
.../arm/mve/intrinsics/vshlltq_x_n_s8.c | 40 ++++-
.../arm/mve/intrinsics/vshlltq_x_n_u16.c | 40 ++++-
.../arm/mve/intrinsics/vshlltq_x_n_u8.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vshlq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vshlq_m_n_s8.c | 34 +++-
.../arm/mve/intrinsics/vshlq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vshlq_m_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vshlq_m_n_u8.c | 34 +++-
.../arm/mve/intrinsics/vshlq_m_r_s16.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_r_s32.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_r_s8.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_r_u16.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_r_u32.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_r_u8.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_s32.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_s8.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_u32.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_u8.c | 33 +++-
.../arm/mve/intrinsics/vshlq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vshlq_n_s32.c | 28 +++-
.../arm/mve/intrinsics/vshlq_n_s8.c | 24 ++-
.../arm/mve/intrinsics/vshlq_n_u16.c | 28 +++-
.../arm/mve/intrinsics/vshlq_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vshlq_n_u8.c | 24 ++-
.../arm/mve/intrinsics/vshlq_r_s16.c | 24 ++-
.../arm/mve/intrinsics/vshlq_r_s32.c | 24 ++-
.../arm/mve/intrinsics/vshlq_r_s8.c | 24 ++-
.../arm/mve/intrinsics/vshlq_r_u16.c | 24 ++-
.../arm/mve/intrinsics/vshlq_r_u32.c | 24 ++-
.../arm/mve/intrinsics/vshlq_r_u8.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vshlq_s16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vshlq_s32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vshlq_s8.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vshlq_u16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vshlq_u32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vshlq_u8.c | 24 ++-
.../arm/mve/intrinsics/vshlq_x_n_s16.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_n_s32.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_n_s8.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_n_u16.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_n_u32.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_n_u8.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_s16.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_s32.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_s8.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_u16.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_u32.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_u8.c | 40 ++++-
.../arm/mve/intrinsics/vshrnbq_m_n_s16.c | 38 ++++-
.../arm/mve/intrinsics/vshrnbq_m_n_s32.c | 38 ++++-
.../arm/mve/intrinsics/vshrnbq_m_n_u16.c | 38 ++++-
.../arm/mve/intrinsics/vshrnbq_m_n_u32.c | 38 ++++-
.../arm/mve/intrinsics/vshrnbq_n_s16.c | 28 +++-
.../arm/mve/intrinsics/vshrnbq_n_s32.c | 28 +++-
.../arm/mve/intrinsics/vshrnbq_n_u16.c | 28 +++-
.../arm/mve/intrinsics/vshrnbq_n_u32.c | 28 +++-
.../arm/mve/intrinsics/vshrntq_m_n_s16.c | 38 ++++-
.../arm/mve/intrinsics/vshrntq_m_n_s32.c | 38 ++++-
.../arm/mve/intrinsics/vshrntq_m_n_u16.c | 38 ++++-
.../arm/mve/intrinsics/vshrntq_m_n_u32.c | 38 ++++-
.../arm/mve/intrinsics/vshrntq_n_s16.c | 28 +++-
.../arm/mve/intrinsics/vshrntq_n_s32.c | 28 +++-
.../arm/mve/intrinsics/vshrntq_n_u16.c | 28 +++-
.../arm/mve/intrinsics/vshrntq_n_u32.c | 28 +++-
.../arm/mve/intrinsics/vshrq_m_n_s16.c | 38 ++++-
.../arm/mve/intrinsics/vshrq_m_n_s32.c | 38 ++++-
.../arm/mve/intrinsics/vshrq_m_n_s8.c | 38 ++++-
.../arm/mve/intrinsics/vshrq_m_n_u16.c | 38 ++++-
.../arm/mve/intrinsics/vshrq_m_n_u32.c | 38 ++++-
.../arm/mve/intrinsics/vshrq_m_n_u8.c | 38 ++++-
.../arm/mve/intrinsics/vshrq_n_s16.c | 28 +++-
.../arm/mve/intrinsics/vshrq_n_s32.c | 28 +++-
.../arm/mve/intrinsics/vshrq_n_s8.c | 28 +++-
.../arm/mve/intrinsics/vshrq_n_u16.c | 28 +++-
.../arm/mve/intrinsics/vshrq_n_u32.c | 28 +++-
.../arm/mve/intrinsics/vshrq_n_u8.c | 28 +++-
.../arm/mve/intrinsics/vshrq_x_n_s16.c | 40 ++++-
.../arm/mve/intrinsics/vshrq_x_n_s32.c | 40 ++++-
.../arm/mve/intrinsics/vshrq_x_n_s8.c | 40 ++++-
.../arm/mve/intrinsics/vshrq_x_n_u16.c | 40 ++++-
.../arm/mve/intrinsics/vshrq_x_n_u8.c | 40 ++++-
.../arm/mve/intrinsics/vsliq_m_n_s16.c | 38 ++++-
.../arm/mve/intrinsics/vsliq_m_n_s32.c | 38 ++++-
.../arm/mve/intrinsics/vsliq_m_n_s8.c | 38 ++++-
.../arm/mve/intrinsics/vsliq_m_n_u16.c | 38 ++++-
.../arm/mve/intrinsics/vsliq_m_n_u32.c | 38 ++++-
.../arm/mve/intrinsics/vsliq_m_n_u8.c | 38 ++++-
.../arm/mve/intrinsics/vsliq_n_s16.c | 28 +++-
.../arm/mve/intrinsics/vsliq_n_s32.c | 28 +++-
.../arm/mve/intrinsics/vsliq_n_s8.c | 28 +++-
.../arm/mve/intrinsics/vsliq_n_u16.c | 28 +++-
.../arm/mve/intrinsics/vsliq_n_u32.c | 28 +++-
.../arm/mve/intrinsics/vsliq_n_u8.c | 28 +++-
.../arm/mve/intrinsics/vsriq_m_n_s16.c | 37 ++++-
.../arm/mve/intrinsics/vsriq_m_n_s32.c | 37 ++++-
.../arm/mve/intrinsics/vsriq_m_n_s8.c | 37 ++++-
.../arm/mve/intrinsics/vsriq_m_n_u16.c | 37 ++++-
.../arm/mve/intrinsics/vsriq_m_n_u32.c | 37 ++++-
.../arm/mve/intrinsics/vsriq_m_n_u8.c | 37 ++++-
.../arm/mve/intrinsics/vsriq_n_s16.c | 28 +++-
.../arm/mve/intrinsics/vsriq_n_s32.c | 28 +++-
.../arm/mve/intrinsics/vsriq_n_s8.c | 28 +++-
.../arm/mve/intrinsics/vsriq_n_u16.c | 28 +++-
.../arm/mve/intrinsics/vsriq_n_u32.c | 28 +++-
.../arm/mve/intrinsics/vsriq_n_u8.c | 28 +++-
.../gcc.target/arm/mve/intrinsics/vst1q_f16.c | 36 +++--
.../gcc.target/arm/mve/intrinsics/vst1q_f32.c | 32 +++-
.../arm/mve/intrinsics/vst1q_p_f16.c | 40 ++++-
.../arm/mve/intrinsics/vst1q_p_f32.c | 40 ++++-
.../arm/mve/intrinsics/vst1q_p_s16.c | 40 ++++-
.../arm/mve/intrinsics/vst1q_p_s32.c | 40 ++++-
.../arm/mve/intrinsics/vst1q_p_s8.c | 40 ++++-
.../arm/mve/intrinsics/vst1q_p_u16.c | 40 ++++-
.../arm/mve/intrinsics/vst1q_p_u32.c | 40 ++++-
.../arm/mve/intrinsics/vst1q_p_u8.c | 40 ++++-
.../gcc.target/arm/mve/intrinsics/vst1q_s16.c | 36 +++--
.../gcc.target/arm/mve/intrinsics/vst1q_s32.c | 32 +++-
.../gcc.target/arm/mve/intrinsics/vst1q_s8.c | 36 +++--
.../gcc.target/arm/mve/intrinsics/vst1q_u16.c | 36 +++--
.../gcc.target/arm/mve/intrinsics/vst1q_u32.c | 32 +++-
.../gcc.target/arm/mve/intrinsics/vst1q_u8.c | 36 +++--
.../intrinsics/vstrdq_scatter_base_p_s64.c | 40 ++++-
.../intrinsics/vstrdq_scatter_base_p_u64.c | 40 ++++-
.../mve/intrinsics/vstrdq_scatter_base_s64.c | 32 +++-
.../mve/intrinsics/vstrdq_scatter_base_u64.c | 32 +++-
.../intrinsics/vstrdq_scatter_base_wb_p_s64.c | 40 ++++-
.../intrinsics/vstrdq_scatter_base_wb_p_u64.c | 40 ++++-
.../intrinsics/vstrdq_scatter_base_wb_s64.c | 32 +++-
.../intrinsics/vstrdq_scatter_base_wb_u64.c | 32 +++-
.../intrinsics/vstrdq_scatter_offset_p_s64.c | 40 ++++-
.../intrinsics/vstrdq_scatter_offset_p_u64.c | 40 ++++-
.../intrinsics/vstrdq_scatter_offset_s64.c | 32 +++-
.../intrinsics/vstrdq_scatter_offset_u64.c | 32 +++-
.../vstrdq_scatter_shifted_offset_p_s64.c | 40 ++++-
.../vstrdq_scatter_shifted_offset_p_u64.c | 40 ++++-
.../vstrdq_scatter_shifted_offset_s64.c | 32 +++-
.../vstrdq_scatter_shifted_offset_u64.c | 32 +++-
1069 files changed, 27457 insertions(+), 3534 deletions(-)
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 161794e470c..5adbbb3bff6 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -141,7 +141,7 @@ (define_insn "mve_vrndq_m_f<mode>"
VRNDQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vrintzt.f%#<V_sz_elem> %q0, %q2"
+ "vpst\;vrintzt.f%#<V_sz_elem>\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -239,7 +239,7 @@ (define_insn "mve_vrev64q_f<mode>"
VREV64Q_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vrev64.%#<V_sz_elem> %q0, %q1"
+ "vrev64.%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -293,7 +293,7 @@ (define_insn "mve_vrev32q_fv8hf"
VREV32Q_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vrev32.16 %q0, %q1"
+ "vrev32.16\t%q0, %q1"
[(set_attr "type" "mve_move")
])
;;
@@ -306,7 +306,7 @@ (define_insn "mve_vcvttq_f32_f16v4sf"
VCVTTQ_F32_F16))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvtt.f32.f16 %q0, %q1"
+ "vcvtt.f32.f16\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -320,7 +320,7 @@ (define_insn "mve_vcvtbq_f32_f16v4sf"
VCVTBQ_F32_F16))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvtb.f32.f16 %q0, %q1"
+ "vcvtb.f32.f16\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -334,7 +334,7 @@ (define_insn "mve_vcvtq_to_f_<supf><mode>"
VCVTQ_TO_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q1"
+ "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -348,7 +348,7 @@ (define_insn "mve_vrev64q_<supf><mode>"
VREV64Q))
]
"TARGET_HAVE_MVE"
- "vrev64.%#<V_sz_elem> %q0, %q1"
+ "vrev64.%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -362,7 +362,7 @@ (define_insn "mve_vcvtq_from_f_<supf><mode>"
VCVTQ_FROM_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
+ "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
;; [vqnegq_s])
@@ -524,7 +524,7 @@ (define_insn "mve_vmovltq_<supf><mode>"
VMOVLTQ))
]
"TARGET_HAVE_MVE"
- "vmovlt.<supf>%#<V_sz_elem> %q0, %q1"
+ "vmovlt.<supf>%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -538,7 +538,7 @@ (define_insn "mve_vmovlbq_<supf><mode>"
VMOVLBQ))
]
"TARGET_HAVE_MVE"
- "vmovlb.<supf>%#<V_sz_elem> %q0, %q1"
+ "vmovlb.<supf>%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -552,7 +552,7 @@ (define_insn "mve_vcvtpq_<supf><mode>"
VCVTPQ))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
+ "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -566,7 +566,7 @@ (define_insn "mve_vcvtnq_<supf><mode>"
VCVTNQ))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
+ "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -580,7 +580,7 @@ (define_insn "mve_vcvtmq_<supf><mode>"
VCVTMQ))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
+ "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -594,7 +594,7 @@ (define_insn "mve_vcvtaq_<supf><mode>"
VCVTAQ))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
+ "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -608,7 +608,7 @@ (define_insn "mve_vmvnq_n_<supf><mode>"
VMVNQ_N))
]
"TARGET_HAVE_MVE"
- "vmvn.i%#<V_sz_elem> %q0, %1"
+ "vmvn.i%#<V_sz_elem>\t%q0, %1"
[(set_attr "type" "mve_move")
])
@@ -622,7 +622,7 @@ (define_insn "mve_vrev16q_<supf>v16qi"
VREV16Q))
]
"TARGET_HAVE_MVE"
- "vrev16.8 %q0, %q1"
+ "vrev16.8\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -650,7 +650,7 @@ (define_insn "mve_vctp<MVE_vctp>q<MVE_vpred>"
VCTP))
]
"TARGET_HAVE_MVE"
- "vctp.<MVE_vctp> %1"
+ "vctp.<MVE_vctp>\t%1"
[(set_attr "type" "mve_move")
])
@@ -694,7 +694,7 @@ (define_insn "mve_vbrsrq_n_f<mode>"
VBRSRQ_N_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vbrsr.<V_sz_elem> %q0, %q1, %2"
+ "vbrsr.<V_sz_elem>\t%q0, %q1, %2"
[(set_attr "type" "mve_move")
])
@@ -976,7 +976,7 @@ (define_insn "mve_vbrsrq_n_<supf><mode>"
VBRSRQ_N))
]
"TARGET_HAVE_MVE"
- "vbrsr.%#<V_sz_elem> %q0, %q1, %2"
+ "vbrsr.%#<V_sz_elem>\t%q0, %q1, %2"
[(set_attr "type" "mve_move")
])
@@ -1864,7 +1864,7 @@ (define_insn "mve_vandq_f<mode>"
(match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vand %q0, %q1, %q2"
+ "vand\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -1878,7 +1878,7 @@ (define_insn "mve_vbicq_f<mode>"
(match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vbic %q0, %q1, %q2"
+ "vbic\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -1893,7 +1893,7 @@ (define_insn "mve_vbicq_n_<supf><mode>"
VBICQ_N))
]
"TARGET_HAVE_MVE"
- "vbic.i%#<V_sz_elem> %q0, %2"
+ "vbic.i%#<V_sz_elem>\t%q0, %2"
[(set_attr "type" "mve_move")
])
@@ -1967,7 +1967,7 @@ (define_insn "mve_vctp<MVE_vctp>q_m<MVE_vpred>"
VCTP_M))
]
"TARGET_HAVE_MVE"
- "vpst\;vctpt.<MVE_vctp> %1"
+ "vpst\;vctpt.<MVE_vctp>\t%1"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -1982,7 +1982,7 @@ (define_insn "mve_vcvtbq_f16_f32v8hf"
VCVTBQ_F16_F32))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvtb.f16.f32 %q0, %q2"
+ "vcvtb.f16.f32\t%q0, %q2"
[(set_attr "type" "mve_move")
])
@@ -1997,7 +1997,7 @@ (define_insn "mve_vcvttq_f16_f32v8hf"
VCVTTQ_F16_F32))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvtt.f16.f32 %q0, %q2"
+ "vcvtt.f16.f32\t%q0, %q2"
[(set_attr "type" "mve_move")
])
@@ -2011,7 +2011,7 @@ (define_insn "mve_veorq_f<mode>"
(match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "veor %q0, %q1, %q2"
+ "veor\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -2159,7 +2159,7 @@ (define_insn "mve_vmlaldavxq_s<mode>"
VMLALDAVXQ_S))
]
"TARGET_HAVE_MVE"
- "vmlaldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+ "vmlaldavx.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -2174,7 +2174,7 @@ (define_insn "mve_vmlsldavq_s<mode>"
VMLSLDAVQ_S))
]
"TARGET_HAVE_MVE"
- "vmlsldav.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+ "vmlsldav.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -2189,7 +2189,7 @@ (define_insn "mve_vmlsldavxq_s<mode>"
VMLSLDAVXQ_S))
]
"TARGET_HAVE_MVE"
- "vmlsldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+ "vmlsldavx.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -2262,7 +2262,7 @@ (define_insn "mve_vornq_f<mode>"
(match_operand:MVE_0 1 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vorn %q0, %q1, %q2"
+ "vorn\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -2276,7 +2276,7 @@ (define_insn "mve_vorrq_f<mode>"
(match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vorr %q0, %q1, %q2"
+ "vorr\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -2426,7 +2426,7 @@ (define_insn "mve_vrmlaldavhxq_sv4si"
VRMLALDAVHXQ_S))
]
"TARGET_HAVE_MVE"
- "vrmlaldavhx.s32 %Q0, %R0, %q1, %q2"
+ "vrmlaldavhx.s32\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -2561,7 +2561,7 @@ (define_insn "mve_vbicq_m_n_<supf><mode>"
VBICQ_M_N))
]
"TARGET_HAVE_MVE"
- "vpst\;vbict.i%#<V_sz_elem> %q0, %2"
+ "vpst\;vbict.i%#<V_sz_elem>\t%q0, %2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
@@ -2606,7 +2606,7 @@ (define_insn "mve_vcvtq_m_to_f_<supf><mode>"
VCVTQ_M_TO_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q2"
+ "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
@@ -2714,7 +2714,7 @@ (define_insn "mve_vshlcq_<supf><mode>"
(match_dup 4)]
VSHLCQ))]
"TARGET_HAVE_MVE"
- "vshlc %q0, %1, %4")
+ "vshlc\t%q0, %1, %4")
;;
;; [vabsq_m_s])
@@ -3272,7 +3272,7 @@ (define_insn "mve_vmvnq_m_<supf><mode>"
VMVNQ_M))
]
"TARGET_HAVE_MVE"
- "vpst\;vmvnt %q0, %q2"
+ "vpst\;vmvnt\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -3304,7 +3304,7 @@ (define_insn "@mve_vpselq_<supf><mode>"
VPSELQ))
]
"TARGET_HAVE_MVE"
- "vpsel %q0, %q1, %q2"
+ "vpsel\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -3929,7 +3929,7 @@ (define_insn "mve_vcvtbq_m_f16_f32v8hf"
VCVTBQ_M_F16_F32))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcvtbt.f16.f32 %q0, %q2"
+ "vpst\;vcvtbt.f16.f32\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -3945,7 +3945,7 @@ (define_insn "mve_vcvtbq_m_f32_f16v4sf"
VCVTBQ_M_F32_F16))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcvtbt.f32.f16 %q0, %q2"
+ "vpst\;vcvtbt.f32.f16\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -3961,7 +3961,7 @@ (define_insn "mve_vcvttq_m_f16_f32v8hf"
VCVTTQ_M_F16_F32))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcvttt.f16.f32 %q0, %q2"
+ "vpst\;vcvttt.f16.f32\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -3977,7 +3977,7 @@ (define_insn "mve_vcvttq_m_f32_f16v4sf"
VCVTTQ_M_F32_F16))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcvttt.f32.f16 %q0, %q2"
+ "vpst\;vcvttt.f32.f16\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4197,7 +4197,7 @@ (define_insn "mve_vmlaldavq_p_<supf><mode>"
VMLALDAVQ_P))
]
"TARGET_HAVE_MVE"
- "vpst\;vmlaldavt.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+ "vpst\;vmlaldavt.<supf>%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4228,7 +4228,7 @@ (define_insn "mve_vmlsldavaq_s<mode>"
VMLSLDAVAQ_S))
]
"TARGET_HAVE_MVE"
- "vmlsldava.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
+ "vmlsldava.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
[(set_attr "type" "mve_move")
])
@@ -4244,7 +4244,7 @@ (define_insn "mve_vmlsldavaxq_s<mode>"
VMLSLDAVAXQ_S))
]
"TARGET_HAVE_MVE"
- "vmlsldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
+ "vmlsldavax.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
[(set_attr "type" "mve_move")
])
@@ -4260,7 +4260,7 @@ (define_insn "mve_vmlsldavq_p_s<mode>"
VMLSLDAVQ_P_S))
]
"TARGET_HAVE_MVE"
- "vpst\;vmlsldavt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+ "vpst\;vmlsldavt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4276,7 +4276,7 @@ (define_insn "mve_vmlsldavxq_p_s<mode>"
VMLSLDAVXQ_P_S))
]
"TARGET_HAVE_MVE"
- "vpst\;vmlsldavxt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+ "vpst\;vmlsldavxt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
@@ -4353,7 +4353,7 @@ (define_insn "mve_vmvnq_m_n_<supf><mode>"
VMVNQ_M_N))
]
"TARGET_HAVE_MVE"
- "vpst\;vmvnt.i%#<V_sz_elem> %q0, %2"
+ "vpst\;vmvnt.i%#<V_sz_elem>\t%q0, %2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
@@ -4384,7 +4384,7 @@ (define_insn "mve_vorrq_m_n_<supf><mode>"
VORRQ_M_N))
]
"TARGET_HAVE_MVE"
- "vpst\;vorrt.i%#<V_sz_elem> %q0, %2"
+ "vpst\;vorrt.i%#<V_sz_elem>\t%q0, %2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
@@ -4399,7 +4399,7 @@ (define_insn "@mve_vpselq_f<mode>"
VPSELQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpsel %q0, %q1, %q2"
+ "vpsel\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -4575,7 +4575,7 @@ (define_insn "mve_vrev32q_m_fv8hf"
VREV32Q_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vrev32t.16 %q0, %q2"
+ "vpst\;vrev32t.16\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4591,7 +4591,7 @@ (define_insn "mve_vrev32q_m_<supf><mode>"
VREV32Q_M))
]
"TARGET_HAVE_MVE"
- "vpst\;vrev32t.%#<V_sz_elem> %q0, %q2"
+ "vpst\;vrev32t.%#<V_sz_elem>\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4607,7 +4607,7 @@ (define_insn "mve_vrev64q_m_f<mode>"
VREV64Q_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vrev64t.%#<V_sz_elem> %q0, %q2"
+ "vpst\;vrev64t.%#<V_sz_elem>\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4623,7 +4623,7 @@ (define_insn "mve_vrmlaldavhaxq_sv4si"
VRMLALDAVHAXQ_S))
]
"TARGET_HAVE_MVE"
- "vrmlaldavhax.s32 %Q0, %R0, %q2, %q3"
+ "vrmlaldavhax.s32\t%Q0, %R0, %q2, %q3"
[(set_attr "type" "mve_move")
])
@@ -4639,7 +4639,7 @@ (define_insn "mve_vrmlaldavhxq_p_sv4si"
VRMLALDAVHXQ_P_S))
]
"TARGET_HAVE_MVE"
- "vpst\;vrmlaldavhxt.s32 %Q0, %R0, %q1, %q2"
+ "vpst\;vrmlaldavhxt.s32\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4655,7 +4655,7 @@ (define_insn "mve_vrmlsldavhaxq_sv4si"
VRMLSLDAVHAXQ_S))
]
"TARGET_HAVE_MVE"
- "vrmlsldavhax.s32 %Q0, %R0, %q2, %q3"
+ "vrmlsldavhax.s32\t%Q0, %R0, %q2, %q3"
[(set_attr "type" "mve_move")
])
@@ -4671,7 +4671,7 @@ (define_insn "mve_vrmlsldavhq_p_sv4si"
VRMLSLDAVHQ_P_S))
]
"TARGET_HAVE_MVE"
- "vpst\;vrmlsldavht.s32 %Q0, %R0, %q1, %q2"
+ "vpst\;vrmlsldavht.s32\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4687,7 +4687,7 @@ (define_insn "mve_vrmlsldavhxq_p_sv4si"
VRMLSLDAVHXQ_P_S))
]
"TARGET_HAVE_MVE"
- "vpst\;vrmlsldavhxt.s32 %Q0, %R0, %q1, %q2"
+ "vpst\;vrmlsldavhxt.s32\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4912,7 +4912,7 @@ (define_insn "mve_vrev16q_m_<supf>v16qi"
VREV16Q_M))
]
"TARGET_HAVE_MVE"
- "vpst\;vrev16t.8 %q0, %q2"
+ "vpst\;vrev16t.8\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4944,7 +4944,7 @@ (define_insn "mve_vrmlaldavhq_p_<supf>v4si"
VRMLALDAVHQ_P))
]
"TARGET_HAVE_MVE"
- "vpst\;vrmlaldavht.<supf>32 %Q0, %R0, %q1, %q2"
+ "vpst\;vrmlaldavht.<supf>32\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4960,7 +4960,7 @@ (define_insn "mve_vrmlsldavhaq_sv4si"
VRMLSLDAVHAQ_S))
]
"TARGET_HAVE_MVE"
- "vrmlsldavha.s32 %Q0, %R0, %q2, %q3"
+ "vrmlsldavha.s32\t%Q0, %R0, %q2, %q3"
[(set_attr "type" "mve_move")
])
@@ -5129,7 +5129,7 @@ (define_insn "mve_vandq_m_<supf><mode>"
VANDQ_M))
]
"TARGET_HAVE_MVE"
- "vpst\;vandt %q0, %q2, %q3"
+ "vpst\;vandt\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -5146,7 +5146,7 @@ (define_insn "mve_vbicq_m_<supf><mode>"
VBICQ_M))
]
"TARGET_HAVE_MVE"
- "vpst\;vbict %q0, %q2, %q3"
+ "vpst\;vbict\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -5214,7 +5214,7 @@ (define_insn "mve_veorq_m_<supf><mode>"
VEORQ_M))
]
"TARGET_HAVE_MVE"
- "vpst\;veort %q0, %q2, %q3"
+ "vpst\;veort\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -5469,7 +5469,7 @@ (define_insn "mve_vornq_m_<supf><mode>"
VORNQ_M))
]
"TARGET_HAVE_MVE"
- "vpst\;vornt %q0, %q2, %q3"
+ "vpst\;vornt\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -5486,7 +5486,7 @@ (define_insn "mve_vorrq_m_<supf><mode>"
VORRQ_M))
]
"TARGET_HAVE_MVE"
- "vpst\;vorrt %q0, %q2, %q3"
+ "vpst\;vorrt\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -6658,7 +6658,7 @@ (define_insn "mve_vandq_m_f<mode>"
VANDQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vandt %q0, %q2, %q3"
+ "vpst\;vandt\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -6675,7 +6675,7 @@ (define_insn "mve_vbicq_m_f<mode>"
VBICQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vbict %q0, %q2, %q3"
+ "vpst\;vbict\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -6879,7 +6879,7 @@ (define_insn "mve_veorq_m_f<mode>"
VEORQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;veort %q0, %q2, %q3"
+ "vpst\;veort\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -7032,7 +7032,7 @@ (define_insn "mve_vornq_m_f<mode>"
VORNQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vornt %q0, %q2, %q3"
+ "vpst\;vornt\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -7049,7 +7049,7 @@ (define_insn "mve_vorrq_m_f<mode>"
VORRQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vorrt %q0, %q2, %q3"
+ "vpst\;vorrt\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -8492,7 +8492,7 @@ (define_insn "mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn"
(match_operand:V2QI 3 "vpr_register_operand" "Up")]
VSTRDSSOQ))]
"TARGET_HAVE_MVE"
- "vpst\;vstrdt.64\t%q2, [%0, %q1, UXTW #3]"
+ "vpst\;vstrdt.64\t%q2, [%0, %q1, uxtw #3]"
[(set_attr "length" "8")])
;;
@@ -8521,7 +8521,7 @@ (define_insn "mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn"
(match_operand:V2DI 2 "s_register_operand" "w")]
VSTRDSSOQ))]
"TARGET_HAVE_MVE"
- "vstrd.64\t%q2, [%0, %q1, UXTW #3]"
+ "vstrd.64\t%q2, [%0, %q1, uxtw #3]"
[(set_attr "length" "4")])
;;
@@ -9473,7 +9473,7 @@ (define_insn "mve_vstrdq_scatter_base_wb_p_<supf>v2di"
ops[0] = operands[1];
ops[1] = operands[2];
ops[2] = operands[3];
- output_asm_insn ("vpst;vstrdt.u64\t%q2, [%q0, %1]!",ops);
+ output_asm_insn ("vpst\;vstrdt.u64\t%q2, [%q0, %1]!",ops);
return "";
}
[(set_attr "length" "8")])
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c
index a2d5160e518..1aa576afae3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** asrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int64_t
-asrl_reg (int64_t longval3, int32_t x)
+foo (int64_t value, int32_t shift)
{
- return asrl (longval3, x);
+ return asrl (value, shift);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "asrl\\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c
index 9c1b62fb9f2..5542ac8c316 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c
@@ -1,13 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** lsll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint64_t
-lsll_reg (uint64_t longval3, int32_t x)
+foo (uint64_t value, int32_t shift)
{
- return lsll (longval3, x);
+ return lsll (value, shift);
+}
+
+/*
+**foo1:
+** ...
+** lsll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint64_t
+foo1 (int32_t shift)
+{
+ return lsll (1, shift);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "lsll\\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c
index 1f0a228e4b4..ea8c7a0ce4a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** sqrshr (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32_t
-sqrshr_reg (int32_t longval3, int32_t x)
+foo (int32_t value, int32_t shift)
{
- return sqrshr (longval3, x);
+ return sqrshr (value, shift);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "sqrshr\\tr\[0-9\]+, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c
index 2f1612cde77..affa12c526d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** sqrshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #48, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int64_t
-sqrshrl_reg (int64_t longval3, int32_t x)
+foo (int64_t value, int32_t shift)
{
- return sqrshrl_sat48 (longval3, x);
+ return sqrshrl_sat48 (value, shift);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "sqrshrl\\tr\[0-9\]+, r\[0-9\]+, #48, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c
index 8cb8c74b268..e8c9c441163 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** sqshl (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-sqshl_imm (int32_t longval3)
+foo (int32_t value)
{
- return sqshl (longval3, 25);
+ return sqshl (value, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "sqshl\\tr\[0-9\]+, #25" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c
index 016ef2a336e..03dc91f3758 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** sqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-sqshll_imm(int64_t value)
+foo (int64_t value)
{
- return sqshll (value, 21);
+ return sqshll (value, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "sqshll\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
index 264f0bf09ce..94e3f42fd33 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** srshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
int32_t
-srshr_imm (int32_t longval3)
+foo (int32_t value)
{
- return srshr (longval3, 25);
+ return srshr (value, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "srshr\\tr\[0-9\]+, #25" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
index ab12d0da635..65f28ccbfde 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
int64_t
-srshrl_imm(int64_t value)
+foo (int64_t value)
{
- return srshrl (value, 21);
+ return srshrl (value, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "srshrl\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c
index 0064aa19fbc..4b6fd041210 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c
@@ -1,13 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** uqrshl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32_t
-uqrshl_reg (uint32_t longval3, int32_t x)
+foo (uint32_t value, int32_t shift)
{
- return uqrshl (longval3, x);
+ return uqrshl (value, shift);
+}
+
+/*
+**foo1:
+** ...
+** uqrshl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint32_t
+foo1 (int32_t shift)
+{
+ return uqrshl (1, shift);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "uqrshl\\tr\[0-9\]+, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c
index 24cd2324413..eaf36911eb6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c
@@ -1,13 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** uqrshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #48, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint64_t
-uqrshll_reg (uint64_t longval3, int32_t x)
+foo (uint64_t value, int32_t shift)
{
- return uqrshll_sat48 (longval3, x);
+ return uqrshll_sat48 (value, shift);
+}
+
+/*
+**foo1:
+** ...
+** uqrshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #48, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint64_t
+foo1 (int32_t shift)
+{
+ return uqrshll_sat48 (1, shift);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "uqrshll\\tr\[0-9\]+, r\[0-9\]+, #48, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
index 9e6ff649805..b23c9d97ba6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
@@ -1,13 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
uint32_t
-uqshl_imm (uint32_t longval3)
+foo (uint32_t value)
{
- return uqshl (longval3, 21);
+ return uqshl (value, 1);
+}
+
+/*
+**foo1:
+** ...
+** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
+uint32_t
+foo1 ()
+{
+ return uqshl (1, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "uqshl\\tr\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
index 52560721d6f..6a3d08eea75 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
@@ -1,13 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
uint64_t
-uqshll_imm(uint64_t value)
+foo (uint64_t value)
{
- return uqshll (value, 21);
+ return uqshll (value, 1);
+}
+
+/*
+**foo1:
+** ...
+** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
+uint64_t
+foo1 ()
+{
+ return uqshll (1, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "uqshll\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
index ec5d84bb009..23afcb8da4c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
@@ -1,13 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
-uint64_t
-urshr_imm (uint32_t longval3)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
+uint32_t
+foo (uint32_t value)
+{
+ return urshr (value, 1);
+}
+
+/*
+**foo1:
+** ...
+** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
+uint32_t
+foo1 ()
{
- return urshr (longval3, 21);
+ return urshr (1, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "urshr\\tr\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
index ea29412ab7a..8014371f47f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
@@ -1,13 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
uint64_t
-urshrl_imm(uint64_t value)
+foo (uint64_t value)
{
- return urshrl (value, 21);
+ return urshrl (value, 1);
+}
+
+/*
+**foo1:
+** ...
+** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
+uint64_t
+foo1 ()
+{
+ return urshrl (1, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "urshrl\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
index 1bfc101d5e8..b262bf94d39 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
@@ -1,23 +1,61 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vadcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p)
{
return vadciq_m_s32 (inactive, a, b, carry_out, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadcit.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vadcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p)
{
return vadciq_m (inactive, a, b, carry_out, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadcit.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
index f72fe34c33b..d349caed36a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
@@ -1,23 +1,61 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vadcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p)
{
return vadciq_m_u32 (inactive, a, b, carry_out, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadcit.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vadcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p)
{
return vadciq_m (inactive, a, b, carry_out, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadcit.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
index ff13841c581..5166993a355 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vadci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t a, int32x4_t b, unsigned * carry_out)
+foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
{
return vadciq_s32 (a, b, carry_out);
}
-/* { dg-final { scan-assembler "vadci.i32" } } */
+/*
+**foo1:
+** ...
+** vadci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t a, int32x4_t b, unsigned * carry_out)
+foo1 (int32x4_t a, int32x4_t b, unsigned *carry_out)
{
return vadciq (a, b, carry_out);
}
-/* { dg-final { scan-assembler "vadci.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
index e3560362225..080bd61d238 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vadci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, unsigned * carry_out)
+foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
{
return vadciq_u32 (a, b, carry_out);
}
-/* { dg-final { scan-assembler "vadci.i32" } } */
+/*
+**foo1:
+** ...
+** vadci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry_out)
+foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
{
return vadciq (a, b, carry_out);
}
-/* { dg-final { scan-assembler "vadci.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
index 668c4fdc82c..45e6ff03623 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
@@ -1,23 +1,73 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p)
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p)
{
return vadcq_m_s32 (inactive, a, b, carry, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadct.i32" } } */
+/*
+**foo1:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p)
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p)
{
return vadcq_m (inactive, a, b, carry, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadct.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
index 368c7c5c5f2..54f141b2093 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
@@ -1,23 +1,73 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p)
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p)
{
return vadcq_m_u32 (inactive, a, b, carry, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadct.i32" } } */
+/*
+**foo1:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p)
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p)
{
return vadcq_m (inactive, a, b, carry, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadct.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
index 9c8777c45ee..06d5bae09da 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
@@ -1,21 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vadc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t a, int32x4_t b, unsigned * carry)
+foo (int32x4_t a, int32x4_t b, unsigned *carry)
{
return vadcq_s32 (a, b, carry);
}
-/* { dg-final { scan-assembler "vadc.i32" } } */
+/*
+**foo1:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vadc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t a, int32x4_t b, unsigned * carry)
+foo1 (int32x4_t a, int32x4_t b, unsigned *carry)
{
return vadcq (a, b, carry);
}
-/* { dg-final { scan-assembler "vadc.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
index 78f48da5107..e2111cfd16a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
@@ -1,21 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vadc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, unsigned * carry)
+foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
{
return vadcq_u32 (a, b, carry);
}
-/* { dg-final { scan-assembler "vadc.i32" } } */
+/*
+**foo1:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vadc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry)
+foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry)
{
return vadcq (a, b, carry);
}
-/* { dg-final { scan-assembler "vadc.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c
index 2303b598a28..cb1820347bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vandq_f16 (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+/*
+**foo1:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vandq (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c
index 905f2b410c0..1034bcbaa62 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vandq_f32 (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+/*
+**foo1:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vandq (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c
index d061dbc390b..d6752a6fdc4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vandq_m_f16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vandq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c
index 77b2813dfad..fb8410d0b71 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vandq_m_f32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vandq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c
index 2840a33b433..5797ffa9a16 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vandq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vandq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c
index 2e8ec7e14de..d2ede670e40 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vandq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vandq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c
index 36226f6d9ac..76ed60c64a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vandq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vandq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c
index 49f0502f607..b3f7833e546 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vandq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vandq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c
index 194c7800a05..7d761c86622 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vandq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vandq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c
index 9b27c44ee82..8fd17e4f258 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vandq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vandq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c
index 86aa64fec96..9f3e9b0c078 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vandq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+/*
+**foo1:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vandq (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c
index 907fe89ced8..ab0e9627fb9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vandq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+/*
+**foo1:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vandq (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c
index 783ad042c87..980ba6b5f7a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vandq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+/*
+**foo1:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vandq (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c
index ae483869f11..fdd18e92476 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b)
{
return vandq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+/*
+**foo1:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b)
{
return vandq (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c
index 532926d894a..01df1828788 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b)
{
return vandq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+/*
+**foo1:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b)
{
return vandq (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c
index 4018308f66d..a4f0cec4483 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b)
{
return vandq_u8 (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+/*
+**foo1:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b)
{
return vandq (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c
index 6aa98910c7b..99c586d5604 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vandq_x_f16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vandq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c
index fd74ee6eee7..eda9d618409 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vandq_x_f32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vandq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c
index d8821d59be7..f0159ee7668 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vandq_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vandq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c
index 980b01436b6..09277b2d56b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vandq_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vandq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c
index 93dead71416..f1232168a7d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vandq_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vandq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c
index aa99c69bd84..836385f44f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vandq_x_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vandq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c
index 1178837d78a..06b5010738b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vandq_x_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vandq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c
index d46e2b235b9..37f4fc51f9a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vandq_x_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vandq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c
index c15f1f91d07..38a1a4adafa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vbicq_f16 (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+/*
+**foo1:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vbicq (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c
index c8659d460a0..224b535992b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vbicq_f32 (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+/*
+**foo1:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vbicq (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c
index 39a12a9fba3..e197a2aa1e3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vbicq_m_f16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vbicq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c
index 091027c4b19..b441e205a64 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vbicq_m_f32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vbicq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c
index 3d0d09859c1..4e2be3e4516 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
- return vbicq_m_n_s16 (a, 16, p);
+ return vbicq_m_n_s16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, mve_pred16_t p)
{
- return vbicq_m_n (a, 16, p);
+ return vbicq_m_n (a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c
index 47a9459580b..d8beab58024 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
return vbicq_m_n_s32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, mve_pred16_t p)
{
return vbicq_m_n (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c
index 7c0c691fd46..34b62aa557f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vbicq_m_n_u16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vbicq_m_n (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c
index e97b17aa27d..60681e3f045 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, mve_pred16_t p)
{
return vbicq_m_n_u32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, mve_pred16_t p)
{
return vbicq_m_n (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c
index 31a9e986b8d..c30658cf34c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vbicq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vbicq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c
index 9e7a2940b42..6a861cb80e5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vbicq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vbicq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c
index b5e3253384c..c19caf53658 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vbicq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vbicq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c
index 54370ab9548..443fcac6605 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vbicq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vbicq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c
index cfcae7c74a9..31b1e22ef7a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vbicq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vbicq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c
index cd9856f629e..6bddc5c2d30 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vbicq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vbicq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c
index 6258727d82f..8726b2c57a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c
@@ -1,20 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a)
{
return vbicq_n_s16 (a, 1);
}
+
+/*
+**foo1:
+** ...
+** vbic.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a)
{
return vbicq (a, 1);
}
-/* { dg-final { scan-assembler-times "vbic.i16" 2 } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c
index be641abf556..015af580ed0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c
@@ -1,20 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a)
{
return vbicq_n_s32 (a, 1);
}
+
+/*
+**foo1:
+** ...
+** vbic.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a)
{
return vbicq (a, 1);
}
-/* { dg-final { scan-assembler-times "vbic.i32" 2 } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c
index 0b26ffda0dc..1ad03b9d17f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c
@@ -1,20 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a)
{
return vbicq_n_u16 (a, 1);
}
+
+/*
+**foo1:
+** ...
+** vbic.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a)
{
return vbicq (a, 1);
}
-/* { dg-final { scan-assembler-times "vbic.i16" 2 } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c
index 47820bd184a..f3fe58fdf37 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c
@@ -1,20 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a)
{
return vbicq_n_u32 (a, 1);
}
+
+/*
+**foo1:
+** ...
+** vbic.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a)
{
return vbicq (a, 1);
}
-/* { dg-final { scan-assembler-times "vbic.i32" 2 } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c
index 4ffacdd9733..6fd2a9e5c0c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vbicq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+/*
+**foo1:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vbicq (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c
index 13fbff40746..37859e0dc6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vbicq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+/*
+**foo1:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vbicq (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c
index b9fba943a83..23db9afbcf1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vbicq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+/*
+**foo1:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vbicq (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c
index 5d94a6396c4..9ed4e533e52 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b)
{
return vbicq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+/*
+**foo1:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b)
{
return vbicq (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c
index 893dc3deefc..abaf2a9cf7b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b)
{
return vbicq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+/*
+**foo1:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b)
{
return vbicq (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c
index bd5e9bc0197..4a47bb9d0e7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b)
{
return vbicq_u8 (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+/*
+**foo1:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b)
{
return vbicq (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c
index 975d60c713e..aa4812568d7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vbicq_x_f16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vbicq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c
index e779224b5d5..db295df1cd5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vbicq_x_f32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vbicq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c
index be554c4b2fb..2b7a3594dd7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vbicq_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vbicq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c
index e49aabf11d6..bf3b755f9ee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vbicq_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vbicq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c
index c36cd1e6dc5..30df0904539 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vbicq_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vbicq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c
index 3b611591deb..eaa50a84fd4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vbicq_x_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vbicq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c
index fce2fab3dd6..aea2592d9cf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vbicq_x_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vbicq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c
index 672b3fb1e39..4ffee473ea6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vbicq_x_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vbicq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c
index 8f8d1bffd73..5985b7fed01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m_n_f16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c
index 336c8194cd7..1fff5a8bf95 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m_n_f32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c
index f597d8ccb9d..a5221f8d864 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m_n_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c
index 76f0463af1e..99106e81a30 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m_n_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c
index 30c6519236c..6bd4c8f4455 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m_n_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c
index 7052b8b5ff5..03ad4896029 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m_n_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c
index e19e02fbbd8..e65077001ec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m_n_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c
index ce658432fd9..61ca255e431 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m_n_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c
index 9b8dea6e7e8..6dc4c657cbf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, int32_t b)
{
return vbrsrq_n_f16 (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.16" } } */
+/*
+**foo1:
+** ...
+** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, int32_t b)
{
return vbrsrq (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c
index cd335197c3b..810cd1b86ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, int32_t b)
{
return vbrsrq_n_f32 (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.32" } } */
+/*
+**foo1:
+** ...
+** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, int32_t b)
{
return vbrsrq (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c
index efb17dd5250..109ccd72f0a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32_t b)
{
return vbrsrq_n_s16 (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.16" } } */
+/*
+**foo1:
+** ...
+** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32_t b)
{
return vbrsrq (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c
index fda78e6aa4b..78b2db49c87 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32_t b)
{
return vbrsrq_n_s32 (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.32" } } */
+/*
+**foo1:
+** ...
+** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32_t b)
{
return vbrsrq (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c
index cd75a2b88fa..dfd485240ea 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbrsr.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int32_t b)
{
return vbrsrq_n_s8 (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.8" } } */
+/*
+**foo1:
+** ...
+** vbrsr.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int32_t b)
{
return vbrsrq (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c
index ef7708e33f8..59e1fcc0fd9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32_t b)
{
return vbrsrq_n_u16 (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.16" } } */
+/*
+**foo1:
+** ...
+** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32_t b)
{
return vbrsrq (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c
index b33c533aeda..2d7792dd1cb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32_t b)
{
return vbrsrq_n_u32 (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.32" } } */
+/*
+**foo1:
+** ...
+** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32_t b)
{
return vbrsrq (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c
index 91156bd4325..5f4398ddbe1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbrsr.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int32_t b)
{
return vbrsrq_n_u8 (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.8" } } */
+/*
+**foo1:
+** ...
+** vbrsr.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int32_t b)
{
return vbrsrq (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c
index 0710b59b1ab..d9d404ccf82 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x_n_f16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c
index 67ab8cf80c9..8b176fe701c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x_n_f32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c
index ac0c13c0b4d..77f4f1852a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x_n_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c
index 98c87f17588..fc4a1c9c7e0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x_n_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c
index 8159f5da999..10322ac328a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x_n_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c
index dbad2940616..72d8a9e23b0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x_n_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c
index 04c812a2747..535af3600c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x_n_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c
index b3836936750..5f8f8c928fd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x_n_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
index 0339fbcafc6..89d8e2b9109 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
@@ -56,4 +56,4 @@ foo2 (float16x8_t a)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
index 2659f061cd9..1575966073d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
@@ -1,21 +1,44 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vctp.16 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
foo (uint32_t a)
{
return vctp16q (a);
}
-/* { dg-final { scan-assembler "vctp.16" } } */
-
+/*
+**foo1:
+** ...
+** vctp.16 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
-foo1 (uint32_t a)
+foo1 ()
{
- return vctp16q (a);
+ return vctp16q (1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vctp.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c
index d901c9ece0d..a14fbe97f86 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c
@@ -1,22 +1,52 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vctpt.16 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
foo (uint32_t a, mve_pred16_t p)
{
return vctp16q_m (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vctpt.16" } } */
-
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vctpt.16 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
-foo1 (uint32_t a, mve_pred16_t p)
+foo1 (mve_pred16_t p)
{
- return vctp16q_m (a, p);
+ return vctp16q_m (1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
index f54ecc33e4a..c53b6190019 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
@@ -1,21 +1,44 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vctp.32 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
foo (uint32_t a)
{
return vctp32q (a);
}
-/* { dg-final { scan-assembler "vctp.32" } } */
-
+/*
+**foo1:
+** ...
+** vctp.32 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
-foo1 (uint32_t a)
+foo1 ()
{
- return vctp32q (a);
+ return vctp32q (1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vctp.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c
index 3d2f101fb0c..6fa790d7039 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c
@@ -1,22 +1,52 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vctpt.32 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
foo (uint32_t a, mve_pred16_t p)
{
return vctp32q_m (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vctpt.32" } } */
-
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vctpt.32 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
-foo1 (uint32_t a, mve_pred16_t p)
+foo1 (mve_pred16_t p)
{
- return vctp32q_m (a, p);
+ return vctp32q_m (1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
index 8502ad3b600..dba63bae1a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
@@ -1,21 +1,44 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vctp.64 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
foo (uint32_t a)
{
return vctp64q (a);
}
-/* { dg-final { scan-assembler "vctp.64" } } */
-
+/*
+**foo1:
+** ...
+** vctp.64 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
-foo1 (uint32_t a)
+foo1 ()
{
- return vctp64q (a);
+ return vctp64q (1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vctp.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c
index 6f3d1c21d01..1faf8a0063c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c
@@ -1,22 +1,52 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vctpt.64 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
foo (uint32_t a, mve_pred16_t p)
{
return vctp64q_m (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vctpt.64" } } */
-
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vctpt.64 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
-foo1 (uint32_t a, mve_pred16_t p)
+foo1 (mve_pred16_t p)
{
- return vctp64q_m (a, p);
+ return vctp64q_m (1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
index 91283f82db1..56267fd861d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
@@ -1,21 +1,44 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vctp.8 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
foo (uint32_t a)
{
return vctp8q (a);
}
-/* { dg-final { scan-assembler "vctp.8" } } */
-
+/*
+**foo1:
+** ...
+** vctp.8 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
-foo1 (uint32_t a)
+foo1 ()
{
- return vctp8q (a);
+ return vctp8q (1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vctp.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c
index 2c640ba6801..937c33cbb83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c
@@ -1,22 +1,52 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vctpt.8 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
foo (uint32_t a, mve_pred16_t p)
{
return vctp8q_m (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vctpt.8" } } */
-
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vctpt.8 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
-foo1 (uint32_t a, mve_pred16_t p)
+foo1 (mve_pred16_t p)
{
- return vctp8q_m (a, p);
+ return vctp8q_m (1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c
index ad8b7d9eb06..fcf4cf817ff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtaq_m_s16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.s16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtaq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c
index 5649e342d1a..8aa640de6ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtaq_m_s32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.s32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtaq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c
index b73c3418758..8fdd3c1b1b0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtaq_m_u16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.u16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtaq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c
index 56c04f9f782..246941e7523 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtaq_m_u32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.u32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtaq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c
index e2d70e8901f..c45ba6ccfbf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvta.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a)
{
return vcvtaq_s16_f16 (a);
}
-/* { dg-final { scan-assembler "vcvta.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c
index d6fd45ae01e..baa20cc5f9a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvta.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a)
{
return vcvtaq_s32_f32 (a);
}
-/* { dg-final { scan-assembler "vcvta.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c
index 8f3b12d9101..de4ea927385 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvta.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a)
{
- return vcvtaq_u16_f16 (a);
+ return vcvtaq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vcvta.u16.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c
index 45e2916e288..93bf292980e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvta.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a)
{
- return vcvtaq_u32_f32 (a);
+ return vcvtaq_u32_f32 (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vcvta.u32.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c
index 26ff128217e..b046b7ad94d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtaq_x_s16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c
index 3a79e3aecd4..77a740867be 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtaq_x_s32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c
index 1f26e7f52d4..b8a10822bdb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtaq_x_u16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.u16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c
index 987e524d789..51184231b7a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtaq_x_u32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.u32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c
index f45e07de375..76b76a2f66e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtb.f16.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float32x4_t b)
{
return vcvtbq_f16_f32 (a, b);
}
-/* { dg-final { scan-assembler "vcvtb.f16.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c
index 39471a0a43b..347d4129b99 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtb.f32.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float16x8_t a)
{
return vcvtbq_f32_f16 (a);
}
-/* { dg-final { scan-assembler "vcvtb.f32.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c
index 6c8d9192417..0545d1e8e27 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c
@@ -1,22 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtbt.f16.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float32x4_t b, mve_pred16_t p)
{
return vcvtbq_m_f16_f32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtbt.f16.f32" } } */
-
-float16x8_t
-foo1 (float16x8_t a, float32x4_t b, mve_pred16_t p)
-{
- return vcvtbq_m (a, b, p);
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c
index 91775436e67..1b220ddfa19 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c
@@ -1,22 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtbt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtbq_m_f32_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtbt.f32.f16" } } */
-
-float32x4_t
-foo1 (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
-{
- return vcvtbq_m (inactive, a, p);
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c
index 0dcdb19d1e4..2a3559d2522 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtbt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtbq_x_f32_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtbt.f32.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c
index 75ff107ab15..b8f6ed855d6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtmq_m_s16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.s16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtmq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c
index b364533e08d..61445594524 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtmq_m_s32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.s32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtmq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c
index 249ef0e92b1..3e57ba58d0f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtmq_m_u16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.u16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtmq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c
index 52ff77ca4c5..8b8a1565332 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtmq_m_u32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.u32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtmq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c
index 70f43ddc220..4eafb5783b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtm.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a)
{
return vcvtmq_s16_f16 (a);
}
-/* { dg-final { scan-assembler "vcvtm.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c
index c2f62cf0717..bd3bfc1b4bd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtm.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a)
{
return vcvtmq_s32_f32 (a);
}
-/* { dg-final { scan-assembler "vcvtm.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c
index 62e4acd73b5..a1917eaf11a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtm.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a)
{
- return vcvtmq_u16_f16 (a);
+ return vcvtmq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vcvtm.u16.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c
index f7f59df1be9..c9f62479e85 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtm.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a)
{
- return vcvtmq_u32_f32 (a);
+ return vcvtmq_u32_f32 (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vcvtm.u32.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c
index 22597fb9cb1..211c2d0df83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtmq_x_s16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c
index 17a583c2641..7ca2cb6eb15 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtmq_x_s32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c
index b6e296f29ea..df212089bf5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtmq_x_u16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.u16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c
index 5f9909b5adb..8b5818fd029 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtmq_x_u32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.u32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c
index a7c3b66a2eb..67fa9cb720d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtnq_m_s16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.s16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c
index 38913a9e26c..26c0b09f7b5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtnq_m_s32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.s32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c
index 42d9e5ea79c..ee2a64747a2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtnq_m_u16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.u16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c
index 321fa35ceb3..cc61951abf5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtnq_m_u32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.u32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c
index d66c058834e..39c00f6ed04 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtn.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a)
{
return vcvtnq_s16_f16 (a);
}
-/* { dg-final { scan-assembler "vcvtn.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c
index 3dec6661411..c371598db24 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtn.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a)
{
return vcvtnq_s32_f32 (a);
}
-/* { dg-final { scan-assembler "vcvtn.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c
index 07637e84bf7..17ae06a57be 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtn.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a)
{
- return vcvtnq_u16_f16 (a);
+ return vcvtnq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vcvtn.u16.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c
index b6d5eb90493..4777b1b205a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtn.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a)
{
return vcvtnq_u32_f32 (a);
}
-/* { dg-final { scan-assembler "vcvtn.u32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c
index f552d633231..a9c91831881 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtnq_x_s16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c
index c3aa2e3daed..2ffb1d98736 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtnq_x_s32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c
index 9d9d12f9f2c..ce2ceb108b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtnq_x_u16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.u16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c
index e7df48de88d..c2c48ef1558 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtnq_x_u32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.u32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c
index c613fc8883d..f09c78b77c2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtpq_m_s16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.s16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtpq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c
index 7f4c7f600e5..7a3d7763406 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtpq_m_s32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.s32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtpq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c
index 192891021f0..f82103ca831 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtpq_m_u16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.u16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtpq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c
index 61858f7844a..7c848aa5157 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtpq_m_u32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.u32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtpq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c
index 8615e50bbaa..87258346b53 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtp.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a)
{
return vcvtpq_s16_f16 (a);
}
-/* { dg-final { scan-assembler "vcvtp.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c
index fed7a4b83f7..e4a7d0baaf1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtp.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a)
{
return vcvtpq_s32_f32 (a);
}
-/* { dg-final { scan-assembler "vcvtp.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c
index 37d1411067f..94edfcb0244 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtp.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a)
{
- return vcvtpq_u16_f16 (a);
+ return vcvtpq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vcvtp.u16.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c
index fcea4c51885..b84501ca72c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtp.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a)
{
- return vcvtpq_u32_f32 (a);
+ return vcvtpq_u32_f32 (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vcvtp.u32.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c
index 5d550772bfc..2b51cc56867 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtpq_x_s16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c
index 31823ab9528..6c4d6655300 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtpq_x_s32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c
index 0d1808c0fe8..2e663c8a472 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtpq_x_u16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.u16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c
index d73df212942..2d32425fdbf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtpq_x_u32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.u32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c
index 560127b7c9f..9f1647c1ac8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (int16x8_t a)
{
return vcvtq_f16_s16 (a);
}
-/* { dg-final { scan-assembler "vcvt.f16.s16" } } */
+
+/*
+**foo1:
+** ...
+** vcvt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (int16x8_t a)
+{
+ return vcvtq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c
index f571c535778..6704626bd1e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (uint16x8_t a)
{
return vcvtq_f16_u16 (a);
}
-/* { dg-final { scan-assembler "vcvt.f16.u16" } } */
+
+/*
+**foo1:
+** ...
+** vcvt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (uint16x8_t a)
+{
+ return vcvtq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c
index 898c74bfba4..898126468d9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (int32x4_t a)
{
return vcvtq_f32_s32 (a);
}
-/* { dg-final { scan-assembler "vcvt.f32.s32" } } */
+
+/*
+**foo1:
+** ...
+** vcvt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (int32x4_t a)
+{
+ return vcvtq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c
index a44add5d178..9e9aa1d703e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (uint32x4_t a)
{
return vcvtq_f32_u32 (a);
}
-/* { dg-final { scan-assembler "vcvt.f32.u32" } } */
+
+/*
+**foo1:
+** ...
+** vcvt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (uint32x4_t a)
+{
+ return vcvtq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c
index 45e9b045af6..b01a9a148c6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vcvtq_m_f16_s16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c
index b50f57234c3..805e26e72fd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vcvtq_m_f16_u16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c
index 4c1af180b58..7faa130fa3f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vcvtq_m_f32_s32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c
index 49acef80489..589d4efa61b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vcvtq_m_f32_u32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c
index d5ba7a690a6..3e23f1d88d8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n_f16_s16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c
index e53d7fa6ef1..f6f309cba25 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n_f16_u16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c
index 58519c04ff4..e6ff2fd6f44 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vcvtq_m_n_f32_s32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vcvtq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c
index 782d1f9e259..7368f127aab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
- return vcvtq_m_n_f32_u32 (inactive, a, 16, p);
+ return vcvtq_m_n_f32_u32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
- return vcvtq_m_n (inactive, a, 16, p);
+ return vcvtq_m_n (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c
index cd3f373aa77..edfb01203dd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n_s16_f16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c
index d1ff5072223..8084160e7e9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtq_m_n_s32_f32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c
index 4bf12e8b64e..1d217387ac6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n_u16_f16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c
index 4d0b1bf7a7f..868a1bcc1b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtq_m_n_u32_f32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c
index 606e43614ea..a998cdcb11a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtq_m_s16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c
index 2204e7929ec..fdaeac453a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtq_m_s32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c
index 1f814251c4f..f168d371615 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtq_m_u16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c
index 13cd6f28884..83e5ae38106 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtq_m_u32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c
index 565012e4e93..5c017221889 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (int16x8_t a)
{
return vcvtq_n_f16_s16 (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.f16.s16" } } */
+/*
+**foo1:
+** ...
+** vcvt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (int16x8_t a)
{
return vcvtq_n (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.f16.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c
index 95acc29683f..1080a5a0309 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (uint16x8_t a)
{
return vcvtq_n_f16_u16 (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.f16.u16" } } */
+/*
+**foo1:
+** ...
+** vcvt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (uint16x8_t a)
{
return vcvtq_n (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.f16.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c
index 5285099bc2a..020138b0084 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (int32x4_t a)
{
return vcvtq_n_f32_s32 (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.f32.s32" } } */
+/*
+**foo1:
+** ...
+** vcvt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (int32x4_t a)
{
return vcvtq_n (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.f32.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c
index ad6335116bc..3f1c3c8c9e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (uint32x4_t a)
{
return vcvtq_n_f32_u32 (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.f32.u32" } } */
+/*
+**foo1:
+** ...
+** vcvt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (uint32x4_t a)
{
return vcvtq_n (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.f32.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c
index ed3dd1a87d6..d16c114e00b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.s16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a)
{
return vcvtq_n_s16_f16 (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c
index e7f63f8cdd2..9256cb48a26 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.s32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a)
{
return vcvtq_n_s32_f32 (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c
index ca2fdca9b49..1038af8f890 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.u16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a)
{
return vcvtq_n_u16_f16 (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.u16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c
index 2919ea5b364..5c06365b320 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.u32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a)
{
return vcvtq_n_u32_f32 (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.u32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c
index 8269bf949bf..ecec3727529 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a)
{
return vcvtq_s16_f16 (a);
}
-/* { dg-final { scan-assembler "vcvt.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c
index 2af96d25917..9be17c0696c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a)
{
return vcvtq_s32_f32 (a);
}
-/* { dg-final { scan-assembler "vcvt.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c
index afac0f4d414..3c33f2ce5b1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a)
{
- return vcvtq_u16_f16 (a);
+ return vcvtq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vcvt.u16.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c
index 7380f73301a..8e70df955b9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a)
{
- return vcvtq_u32_f32 (a);
+ return vcvtq_u32_f32 (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vcvt.u32.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c
index c6b9c1005f5..73b368fdd4f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
return vcvtq_x_f16_s16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (int16x8_t a, mve_pred16_t p)
{
return vcvtq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c
index d3ef02c1931..13d7fed2f5b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vcvtq_x_f16_u16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vcvtq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c
index fa73ad69ce5..d14099c87a6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
return vcvtq_x_f32_s32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (int32x4_t a, mve_pred16_t p)
{
return vcvtq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c
index 99ca3881553..800d8aa8e8e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (uint32x4_t a, mve_pred16_t p)
{
return vcvtq_x_f32_u32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (uint32x4_t a, mve_pred16_t p)
{
return vcvtq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c
index 718c83e74df..f91021d5735 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
return vcvtq_x_n_f16_s16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (int16x8_t a, mve_pred16_t p)
{
return vcvtq_x_n (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c
index 510c29c383a..f4c444b5540 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vcvtq_x_n_f16_u16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vcvtq_x_n (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c
index 34f7cc1e061..7c11f1f0c34 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
return vcvtq_x_n_f32_s32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (int32x4_t a, mve_pred16_t p)
{
return vcvtq_x_n (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c
index b5b20efc1b8..96a1d2c8876 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (uint32x4_t a, mve_pred16_t p)
{
- return vcvtq_x_n_f32_u32 (a, 16, p);
+ return vcvtq_x_n_f32_u32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (uint32x4_t a, mve_pred16_t p)
{
- return vcvtq_x_n (a, 16, p);
+ return vcvtq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c
index 3c3343ae4e1..7c0f551d66f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtq_x_n_s16_f16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c
index 17ef866af39..c22eeb75a17 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtq_x_n_s32_f32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c
index 62e6f1638d5..7f07b0fac53 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtq_x_n_u16_f16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c
index 306e32016ff..7531db7d575 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtq_x_n_u32_f32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c
index 56867da3bb0..fd90d67b46c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtq_x_s16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c
index 4449bd68c54..e6cbbeaca2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtq_x_s32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c
index 580bb775c59..29d1d9d5c56 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtq_x_u16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c
index 3722de632e5..0181850d857 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtq_x_u32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c
index 599e30e3d26..3c9a6844e01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtt.f16.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float32x4_t b)
{
return vcvttq_f16_f32 (a, b);
}
-/* { dg-final { scan-assembler "vcvtt.f16.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c
index a4a7997d2dd..9d389382ae9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float16x8_t a)
{
return vcvttq_f32_f16 (a);
}
-/* { dg-final { scan-assembler "vcvtt.f32.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c
index 065974d7e76..2eeb670a5a2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c
@@ -1,22 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvttt.f16.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float32x4_t b, mve_pred16_t p)
{
return vcvttq_m_f16_f32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvttt.f16.f32" } } */
-
-float16x8_t
-foo1 (float16x8_t a, float32x4_t b, mve_pred16_t p)
-{
- return vcvttq_m (a, b, p);
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c
index 1eb69e4fee9..ba309114dae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c
@@ -1,22 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvttt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvttq_m_f32_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvttt.f32.f16" } } */
-
-float32x4_t
-foo1 (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
-{
- return vcvttq_m (inactive, a, p);
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c
index 921caba0e1b..29688a939dd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvttt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvttq_x_f32_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvttt.f32.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c
index 90cd663c7f3..0c27a1c5664 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return veorq_f16 (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+/*
+**foo1:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return veorq (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c
index e9ad87a9796..cbf67e335ef 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return veorq_f32 (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+/*
+**foo1:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return veorq (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c
index a39d680e0cd..5d9831f8d34 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return veorq_m_f16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return veorq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c
index a5dbfc4725e..ea992de1fbc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return veorq_m_f32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return veorq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c
index 9ab271ac987..f2b8b91aa13 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return veorq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return veorq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c
index 45d5074e32b..c9573f732aa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return veorq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return veorq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c
index 5b8ac0a286e..86cb8ed31c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return veorq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return veorq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c
index e436a9e6536..7b2b1ea1596 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return veorq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return veorq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c
index 631abb515fd..3d3b2bbb4e6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return veorq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return veorq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c
index ba65042f986..7d2baba6e8e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return veorq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return veorq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c
index b49e35c887f..8275da1d7fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return veorq_s16 (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+/*
+**foo1:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return veorq (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c
index 9b6414b8458..ea111b4256d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return veorq_s32 (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+/*
+**foo1:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return veorq (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c
index 4a18bf5a165..f40dddcbb6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return veorq_s8 (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+/*
+**foo1:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return veorq (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c
index 90d5a5a6021..f16ddc14e09 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b)
{
return veorq_u16 (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+/*
+**foo1:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b)
{
return veorq (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c
index b6103d68638..33213c53aa7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b)
{
return veorq_u32 (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+/*
+**foo1:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b)
{
return veorq (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c
index 86fccc1bef0..aba155b1023 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b)
{
return veorq_u8 (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+/*
+**foo1:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b)
{
return veorq (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c
index eb9e44cb777..8eac5ee6ae0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return veorq_x_f16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return veorq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c
index 3503250e5c3..3e71870daf0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return veorq_x_f32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return veorq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c
index 837210bb609..fd032647117 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return veorq_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return veorq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c
index 93796e333ab..ec67ddc761b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return veorq_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return veorq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c
index ed88d43834d..35a1dfdab8a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return veorq_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return veorq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c
index e6e82d8076d..7aad6d6f5c1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return veorq_x_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return veorq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c
index 17393d80233..315241581f8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return veorq_x_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return veorq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c
index 027968dab2d..615b1e645b1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return veorq_x_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return veorq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c
index 8c926bdf1c3..18a184a0e98 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vfma.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16x8_t a, float16x8_t b, float16x8_t c)
+foo (float16x8_t add, float16x8_t m1, float16x8_t m2)
{
- return vfmaq_f16 (a, b, c);
+ return vfmaq_f16 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vfma.f16" } } */
+/*
+**foo1:
+** ...
+** vfma.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
+foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2)
{
- return vfmaq (a, b, c);
+ return vfmaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vfma.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c
index c2fff9a43ea..5d67439b11e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vfma.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32x4_t a, float32x4_t b, float32x4_t c)
+foo (float32x4_t add, float32x4_t m1, float32x4_t m2)
{
- return vfmaq_f32 (a, b, c);
+ return vfmaq_f32 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vfma.f32" } } */
+/*
+**foo1:
+** ...
+** vfma.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
+foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2)
{
- return vfmaq (a, b, c);
+ return vfmaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vfma.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c
index e8453e0cb41..e094cba8acb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+foo (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p)
{
- return vfmaq_m_f16 (a, b, c, p);
+ return vfmaq_m_f16 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p)
{
- return vfmaq_m (a, b, c, p);
+ return vfmaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c
index 9d1844eba5a..3003eff236a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+foo (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p)
{
- return vfmaq_m_f32 (a, b, c, p);
+ return vfmaq_m_f32 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p)
{
- return vfmaq_m (a, b, c, p);
+ return vfmaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c
index 888016e8164..4603f038467 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c
@@ -1,23 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
+foo (float16x8_t add, float16x8_t m1, float16_t m2, mve_pred16_t p)
{
- return vfmaq_m_n_f16 (a, b, c, p);
+ return vfmaq_m_n_f16 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
+foo1 (float16x8_t add, float16x8_t m1, float16_t m2, mve_pred16_t p)
{
- return vfmaq_m (a, b, c, p);
+ return vfmaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+float16x8_t
+foo2 (float16x8_t add, float16x8_t m1, mve_pred16_t p)
+{
+ return vfmaq_m (add, m1, 1.1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c
index f9afc8845b0..ad0ff907810 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c
@@ -1,23 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
+foo (float32x4_t add, float32x4_t m1, float32_t m2, mve_pred16_t p)
{
- return vfmaq_m_n_f32 (a, b, c, p);
+ return vfmaq_m_n_f32 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
+foo1 (float32x4_t add, float32x4_t m1, float32_t m2, mve_pred16_t p)
{
- return vfmaq_m (a, b, c, p);
+ return vfmaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+float32x4_t
+foo2 (float32x4_t add, float32x4_t m1, mve_pred16_t p)
+{
+ return vfmaq_m (add, m1, 1.1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c
index 208c46f5960..8e8738bc10a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vfma.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16x8_t a, float16x8_t b, float16_t c)
+foo (float16x8_t add, float16x8_t m1, float16_t m2)
{
- return vfmaq_n_f16 (a, b, c);
+ return vfmaq_n_f16 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vfma.f16" } } */
+/*
+**foo1:
+** ...
+** vfma.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c)
+foo1 (float16x8_t add, float16x8_t m1, float16_t m2)
{
- return vfmaq (a, b, c);
+ return vfmaq (add, m1, m2);
+}
+
+/*
+**foo2:
+** ...
+** vfma.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+float16x8_t
+foo2 (float16x8_t add, float16x8_t m1)
+{
+ return vfmaq (add, m1, 1.1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vfma.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c
index 664533239b7..4781e089ffb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vfma.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32x4_t a, float32x4_t b, float32_t c)
+foo (float32x4_t add, float32x4_t m1, float32_t m2)
{
- return vfmaq_n_f32 (a, b, c);
+ return vfmaq_n_f32 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vfma.f32" } } */
+/*
+**foo1:
+** ...
+** vfma.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c)
+foo1 (float32x4_t add, float32x4_t m1, float32_t m2)
{
- return vfmaq (a, b, c);
+ return vfmaq (add, m1, m2);
+}
+
+/*
+**foo2:
+** ...
+** vfma.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+float32x4_t
+foo2 (float32x4_t add, float32x4_t m1)
+{
+ return vfmaq (add, m1, 1.1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vfma.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
index 7f427bd6140..3f57b80874e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
@@ -62,4 +62,4 @@ foo2 (float16x8_t m1, float16x8_t m2, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
index 99a106982fa..728633f5c9e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
@@ -62,4 +62,4 @@ foo2 (float32x4_t m1, float32x4_t m2, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c
index ce9bf48d657..def309387fa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vfmas.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16x8_t a, float16x8_t b, float16_t c)
+foo (float16x8_t m1, float16x8_t m2, float16_t add)
{
- return vfmasq_n_f16 (a, b, c);
+ return vfmasq_n_f16 (m1, m2, add);
}
-/* { dg-final { scan-assembler "vfmas.f16" } } */
+/*
+**foo1:
+** ...
+** vfmas.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c)
+foo1 (float16x8_t m1, float16x8_t m2, float16_t add)
{
- return vfmasq (a, b, c);
+ return vfmasq (m1, m2, add);
+}
+
+/*
+**foo2:
+** ...
+** vfmas.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+float16x8_t
+foo2 (float16x8_t m1, float16x8_t m2)
+{
+ return vfmasq (m1, m2, 1.1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vfmas.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c
index 46c5a320644..c761bdcb109 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vfmas.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32x4_t a, float32x4_t b, float32_t c)
+foo (float32x4_t m1, float32x4_t m2, float32_t add)
{
- return vfmasq_n_f32 (a, b, c);
+ return vfmasq_n_f32 (m1, m2, add);
}
-/* { dg-final { scan-assembler "vfmas.f32" } } */
+/*
+**foo1:
+** ...
+** vfmas.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c)
+foo1 (float32x4_t m1, float32x4_t m2, float32_t add)
{
- return vfmasq (a, b, c);
+ return vfmasq (m1, m2, add);
+}
+
+/*
+**foo2:
+** ...
+** vfmas.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+float32x4_t
+foo2 (float32x4_t m1, float32x4_t m2)
+{
+ return vfmasq (m1, m2, 1.1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vfmas.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c
index 32475013fd4..607668ebc47 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vfms.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16x8_t a, float16x8_t b, float16x8_t c)
+foo (float16x8_t add, float16x8_t m1, float16x8_t m2)
{
- return vfmsq_f16 (a, b, c);
+ return vfmsq_f16 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vfms.f16" } } */
+/*
+**foo1:
+** ...
+** vfms.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
+foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2)
{
- return vfmsq (a, b, c);
+ return vfmsq (add, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vfms.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c
index fbdabd188d5..ac18e9e3d9c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vfms.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32x4_t a, float32x4_t b, float32x4_t c)
+foo (float32x4_t add, float32x4_t m1, float32x4_t m2)
{
- return vfmsq_f32 (a, b, c);
+ return vfmsq_f32 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vfms.f32" } } */
+/*
+**foo1:
+** ...
+** vfms.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
+foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2)
{
- return vfmsq (a, b, c);
+ return vfmsq (add, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vfms.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c
index ccbbfc1606c..f530e0b0614 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmst.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+foo (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p)
{
- return vfmsq_m_f16 (a, b, c, p);
+ return vfmsq_m_f16 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmst.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmst.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p)
{
- return vfmsq_m (a, b, c, p);
+ return vfmsq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmst.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c
index 219492a2ad9..6faca5a2e84 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmst.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+foo (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p)
{
- return vfmsq_m_f32 (a, b, c, p);
+ return vfmsq_m_f32 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmst.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmst.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p)
{
- return vfmsq_m (a, b, c, p);
+ return vfmsq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmst.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c
index f4a1311980a..7e39b75a7bf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vhcaddq_rot270_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vhcaddq_rot270_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c
index 4697eb25458..57096076913 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vhcaddq_rot270_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vhcaddq_rot270_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c
index ff547e83588..d47a99e29a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vhcaddq_rot270_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vhcaddq_rot270_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c
index 75346b2e349..01324c003c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vhcadd.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vhcaddq_rot270_s16 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s16" } } */
+/*
+**foo1:
+** ...
+** vhcadd.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vhcaddq_rot270 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c
index 0d458f100af..344d1ebf4a7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vhcadd.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vhcaddq_rot270_s32 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s32" } } */
+/*
+**foo1:
+** ...
+** vhcadd.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vhcaddq_rot270 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c
index 5106bb7d45b..0ee4cfb4095 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vhcadd.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vhcaddq_rot270_s8 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s8" } } */
+/*
+**foo1:
+** ...
+** vhcadd.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vhcaddq_rot270 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c
index 73f4784cd35..c3e70ad9e2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vhcaddq_rot270_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vhcaddq_rot270_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c
index 69c7cb7b0e6..6f14d2af44d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vhcaddq_rot270_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vhcaddq_rot270_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c
index df4aff74bff..32bfb6cf3bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vhcaddq_rot270_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vhcaddq_rot270_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c
index 5461fc26741..a7a870e78df 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vhcaddq_rot90_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vhcaddq_rot90_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c
index 20d2711aadb..1e6ef8f9aaa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vhcaddq_rot90_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vhcaddq_rot90_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c
index 55475753512..147d647d27f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vhcaddq_rot90_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vhcaddq_rot90_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c
index 539f9b00bd2..76747d669bb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vhcadd.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vhcaddq_rot90_s16 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s16" } } */
+/*
+**foo1:
+** ...
+** vhcadd.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vhcaddq_rot90 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c
index 841c5294253..8b9b8ad7aa9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vhcadd.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vhcaddq_rot90_s32 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s32" } } */
+/*
+**foo1:
+** ...
+** vhcadd.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vhcaddq_rot90 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c
index d2992c2f280..5e9b004f7cc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vhcadd.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vhcaddq_rot90_s8 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s8" } } */
+/*
+**foo1:
+** ...
+** vhcadd.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vhcaddq_rot90 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c
index 0d677f7f149..d3416d65658 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vhcaddq_rot90_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vhcaddq_rot90_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c
index a54af77440f..b0255e5141c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vhcaddq_rot90_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vhcaddq_rot90_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c
index 5205cd37deb..10f5f31f26e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vhcaddq_rot90_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vhcaddq_rot90_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c
index 2a7a79e62ea..f05d04b1f3d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmladavq_p_s16 (a, b, p);
+ return vmladavq_p_s16 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmladavt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmladavq_p (a, b, p);
+ return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavt.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c
index 6b118144075..397bb9fb4ec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmladavq_p_s32 (a, b, p);
+ return vmladavq_p_s32 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmladavt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmladavq_p (a, b, p);
+ return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavt.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c
index b3a4e11fa24..25c11d200ad 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
+foo (int8x16_t m1, int8x16_t m2, mve_pred16_t p)
{
- return vmladavq_p_s8 (a, b, p);
+ return vmladavq_p_s8 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmladavt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+foo1 (int8x16_t m1, int8x16_t m2, mve_pred16_t p)
{
- return vmladavq_p (a, b, p);
+ return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavt.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c
index 0ff2ffdc5f2..064d2c22a23 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+foo (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
{
- return vmladavq_p_u16 (a, b, p);
+ return vmladavq_p_u16 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmladavt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+foo1 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
{
- return vmladavq_p (a, b, p);
+ return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavt.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c
index c5d213d4c0b..f5f3de9f0e8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+foo (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
{
- return vmladavq_p_u32 (a, b, p);
+ return vmladavq_p_u32 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmladavt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+foo1 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
{
- return vmladavq_p (a, b, p);
+ return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavt.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c
index 6fcc530c17c..243e61715e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+foo (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p)
{
- return vmladavq_p_u8 (a, b, p);
+ return vmladavq_p_u8 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmladavt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+foo1 (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p)
{
- return vmladavq_p (a, b, p);
+ return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavt.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c
index a140be6204d..b0ff042fc43 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmladav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int16x8_t a, int16x8_t b)
+foo (int16x8_t m1, int16x8_t m2)
{
- return vmladavq_s16 (a, b);
+ return vmladavq_s16 (m1, m2);
}
-/* { dg-final { scan-assembler "vmladav.s16" } } */
+/*
+**foo1:
+** ...
+** vmladav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int16x8_t a, int16x8_t b)
+foo1 (int16x8_t m1, int16x8_t m2)
{
- return vmladavq (a, b);
+ return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladav.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c
index 1413e480551..a2ef4b37e4d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmladav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int32x4_t a, int32x4_t b)
+foo (int32x4_t m1, int32x4_t m2)
{
- return vmladavq_s32 (a, b);
+ return vmladavq_s32 (m1, m2);
}
-/* { dg-final { scan-assembler "vmladav.s32" } } */
+/*
+**foo1:
+** ...
+** vmladav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int32x4_t a, int32x4_t b)
+foo1 (int32x4_t m1, int32x4_t m2)
{
- return vmladavq (a, b);
+ return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladav.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c
index d43dbb9fefc..e3e6e2982d7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmladav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int8x16_t a, int8x16_t b)
+foo (int8x16_t m1, int8x16_t m2)
{
- return vmladavq_s8 (a, b);
+ return vmladavq_s8 (m1, m2);
}
-/* { dg-final { scan-assembler "vmladav.s8" } } */
+/*
+**foo1:
+** ...
+** vmladav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int8x16_t a, int8x16_t b)
+foo1 (int8x16_t m1, int8x16_t m2)
{
- return vmladavq (a, b);
+ return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladav.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c
index e1c44d7b4ce..d021bc0e30d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmladav.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo (uint16x8_t a, uint16x8_t b)
+foo (uint16x8_t m1, uint16x8_t m2)
{
- return vmladavq_u16 (a, b);
+ return vmladavq_u16 (m1, m2);
}
-/* { dg-final { scan-assembler "vmladav.u16" } } */
+/*
+**foo1:
+** ...
+** vmladav.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo1 (uint16x8_t a, uint16x8_t b)
+foo1 (uint16x8_t m1, uint16x8_t m2)
{
- return vmladavq (a, b);
+ return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladav.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c
index 5e9bb56bae0..0848ca25b9f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmladav.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo (uint32x4_t a, uint32x4_t b)
+foo (uint32x4_t m1, uint32x4_t m2)
{
- return vmladavq_u32 (a, b);
+ return vmladavq_u32 (m1, m2);
}
-/* { dg-final { scan-assembler "vmladav.u32" } } */
+/*
+**foo1:
+** ...
+** vmladav.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo1 (uint32x4_t a, uint32x4_t b)
+foo1 (uint32x4_t m1, uint32x4_t m2)
{
- return vmladavq (a, b);
+ return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladav.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c
index f4223538170..2a735fbb654 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmladav.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo (uint8x16_t a, uint8x16_t b)
+foo (uint8x16_t m1, uint8x16_t m2)
{
- return vmladavq_u8 (a, b);
+ return vmladavq_u8 (m1, m2);
}
-/* { dg-final { scan-assembler "vmladav.u8" } } */
+/*
+**foo1:
+** ...
+** vmladav.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo1 (uint8x16_t a, uint8x16_t b)
+foo1 (uint8x16_t m1, uint8x16_t m2)
{
- return vmladavq (a, b);
+ return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladav.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c
index 7ee875eae6b..dc94ecada57 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmladavxq_p_s16 (a, b, p);
+ return vmladavxq_p_s16 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmladavxt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmladavxq_p (a, b, p);
+ return vmladavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavxt.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c
index d4f92ba9cf2..15a2abd7d13 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmladavxq_p_s32 (a, b, p);
+ return vmladavxq_p_s32 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmladavxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmladavxq_p (a, b, p);
+ return vmladavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavxt.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c
index d5f14c51ae8..e56874151a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
+foo (int8x16_t m1, int8x16_t m2, mve_pred16_t p)
{
- return vmladavxq_p_s8 (a, b, p);
+ return vmladavxq_p_s8 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmladavxt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+foo1 (int8x16_t m1, int8x16_t m2, mve_pred16_t p)
{
- return vmladavxq_p (a, b, p);
+ return vmladavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavxt.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c
index deac58d768e..e7e3b571efb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmladavx.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int16x8_t a, int16x8_t b)
+foo (int16x8_t m1, int16x8_t m2)
{
- return vmladavxq_s16 (a, b);
+ return vmladavxq_s16 (m1, m2);
}
-/* { dg-final { scan-assembler "vmladavx.s16" } } */
+/*
+**foo1:
+** ...
+** vmladavx.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int16x8_t a, int16x8_t b)
+foo1 (int16x8_t m1, int16x8_t m2)
{
- return vmladavxq (a, b);
+ return vmladavxq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavx.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c
index 56516d74173..c3841f59d57 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmladavx.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int32x4_t a, int32x4_t b)
+foo (int32x4_t m1, int32x4_t m2)
{
- return vmladavxq_s32 (a, b);
+ return vmladavxq_s32 (m1, m2);
}
-/* { dg-final { scan-assembler "vmladavx.s32" } } */
+/*
+**foo1:
+** ...
+** vmladavx.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int32x4_t a, int32x4_t b)
+foo1 (int32x4_t m1, int32x4_t m2)
{
- return vmladavxq (a, b);
+ return vmladavxq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavx.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c
index 3b1e8cd67cd..59cdc346ee5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmladavx.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int8x16_t a, int8x16_t b)
+foo (int8x16_t m1, int8x16_t m2)
{
- return vmladavxq_s8 (a, b);
+ return vmladavxq_s8 (m1, m2);
}
-/* { dg-final { scan-assembler "vmladavx.s8" } } */
+/*
+**foo1:
+** ...
+** vmladavx.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int8x16_t a, int8x16_t b)
+foo1 (int8x16_t m1, int8x16_t m2)
{
- return vmladavxq (a, b);
+ return vmladavxq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavx.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c
index 246b40fbe2c..fbdbb5c16a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmlaldavaq_p_s16 (a, b, c, p);
+ return vmlaldavaq_p_s16 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavat.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo1 (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmlaldavaq_p (a, b, c, p);
+ return vmlaldavaq_p (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavat.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c
index 6563af20061..9c59d0306a1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmlaldavaq_p_s32 (a, b, c, p);
+ return vmlaldavaq_p_s32 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavat.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo1 (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmlaldavaq_p (a, b, c, p);
+ return vmlaldavaq_p (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavat.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c
index 632e29f972d..b714b677339 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c
@@ -1,21 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+foo (uint64_t add, uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
{
- return vmlaldavaq_p_u16 (a, b, c, p);
+ return vmlaldavaq_p_u16 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavat.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo1 (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+foo1 (uint64_t add, uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
{
- return vmlaldavaq_p (a, b, c, p);
+ return vmlaldavaq_p (add, m1, m2, p);
+}
+
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+uint64_t
+foo2 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
+{
+ return vmlaldavaq_p (1, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavat.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c
index d2fcd5d14ed..29419a06458 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c
@@ -1,21 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+foo (uint64_t add, uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
{
- return vmlaldavaq_p_u32 (a, b, c, p);
+ return vmlaldavaq_p_u32 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavat.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo1 (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+foo1 (uint64_t add, uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
{
- return vmlaldavaq_p (a, b, c, p);
+ return vmlaldavaq_p (add, m1, m2, p);
+}
+
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+uint64_t
+foo2 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
+{
+ return vmlaldavaq_p (1, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavat.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c
index 1cb9b6ebc41..d1f049923c0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldava.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int64_t a, int16x8_t b, int16x8_t c)
+foo (int64_t add, int16x8_t m1, int16x8_t m2)
{
- return vmlaldavaq_s16 (a, b, c);
+ return vmlaldavaq_s16 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldava.s16" } } */
+/*
+**foo1:
+** ...
+** vmlaldava.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int64_t a, int16x8_t b, int16x8_t c)
+foo1 (int64_t add, int16x8_t m1, int16x8_t m2)
{
- return vmlaldavaq (a, b, c);
+ return vmlaldavaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldava.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c
index 56e59f5929d..dfce7d8f625 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldava.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int64_t a, int32x4_t b, int32x4_t c)
+foo (int64_t add, int32x4_t m1, int32x4_t m2)
{
- return vmlaldavaq_s32 (a, b, c);
+ return vmlaldavaq_s32 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldava.s32" } } */
+/*
+**foo1:
+** ...
+** vmlaldava.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int64_t a, int32x4_t b, int32x4_t c)
+foo1 (int64_t add, int32x4_t m1, int32x4_t m2)
{
- return vmlaldavaq (a, b, c);
+ return vmlaldavaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldava.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c
index 7c95abc271c..7e42054a4f3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldava.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo (uint64_t a, uint16x8_t b, uint16x8_t c)
+foo (uint64_t add, uint16x8_t m1, uint16x8_t m2)
{
- return vmlaldavaq_u16 (a, b, c);
+ return vmlaldavaq_u16 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldava.u16" } } */
+/*
+**foo1:
+** ...
+** vmlaldava.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo1 (uint64_t a, uint16x8_t b, uint16x8_t c)
+foo1 (uint64_t add, uint16x8_t m1, uint16x8_t m2)
{
- return vmlaldavaq (a, b, c);
+ return vmlaldavaq (add, m1, m2);
+}
+
+/*
+**foo2:
+** ...
+** vmlaldava.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+uint64_t
+foo2 (uint16x8_t m1, uint16x8_t m2)
+{
+ return vmlaldavaq (1, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldava.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c
index 239f5e32d8b..20ba6d377bf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldava.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo (uint64_t a, uint32x4_t b, uint32x4_t c)
+foo (uint64_t add, uint32x4_t m1, uint32x4_t m2)
{
- return vmlaldavaq_u32 (a, b, c);
+ return vmlaldavaq_u32 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldava.u32" } } */
+/*
+**foo1:
+** ...
+** vmlaldava.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo1 (uint64_t a, uint32x4_t b, uint32x4_t c)
+foo1 (uint64_t add, uint32x4_t m1, uint32x4_t m2)
{
- return vmlaldavaq (a, b, c);
+ return vmlaldavaq (add, m1, m2);
+}
+
+/*
+**foo2:
+** ...
+** vmlaldava.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+uint64_t
+foo2 (uint32x4_t m1, uint32x4_t m2)
+{
+ return vmlaldavaq (1, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldava.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c
index 11e32c76d5a..7c2f07f3495 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c
@@ -46,4 +46,4 @@ foo1 (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c
index 937fab4166c..6214235487b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c
@@ -46,4 +46,4 @@ foo1 (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c
index 4f10ec7d098..b5922b8c281 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c
@@ -38,4 +38,4 @@ foo1 (int64_t add, int16x8_t m1, int16x8_t m2)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c
index 1d78a7cd269..124125e2f29 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c
@@ -38,4 +38,4 @@ foo1 (int64_t add, int32x4_t m1, int32x4_t m2)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c
index 008efd95a35..de9cc0ed9c4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmlaldavq_p_s16 (a, b, p);
+ return vmlaldavq_p_s16 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmlaldavq_p (a, b, p);
+ return vmlaldavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavt.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c
index e824e6b7ce0..a2b1c59291b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmlaldavq_p_s32 (a, b, p);
+ return vmlaldavq_p_s32 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmlaldavq_p (a, b, p);
+ return vmlaldavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavt.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c
index 1fea6d5c117..6034b9b5454 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavt.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+foo (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
{
- return vmlaldavq_p_u16 (a, b, p);
+ return vmlaldavq_p_u16 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavt.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+foo1 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
{
- return vmlaldavq_p (a, b, p);
+ return vmlaldavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavt.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c
index 99300fcb6ec..a85d7de4dad 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavt.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+foo (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
{
- return vmlaldavq_p_u32 (a, b, p);
+ return vmlaldavq_p_u32 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavt.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+foo1 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
{
- return vmlaldavq_p (a, b, p);
+ return vmlaldavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavt.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c
index 1cdb44920e1..b18e8eb149e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldav.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int16x8_t a, int16x8_t b)
+foo (int16x8_t m1, int16x8_t m2)
{
- return vmlaldavq_s16 (a, b);
+ return vmlaldavq_s16 (m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldav.s16" } } */
+/*
+**foo1:
+** ...
+** vmlaldav.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int16x8_t a, int16x8_t b)
+foo1 (int16x8_t m1, int16x8_t m2)
{
- return vmlaldavq (a, b);
+ return vmlaldavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldav.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c
index 123ca0f4eeb..b0fe1c5132c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldav.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int32x4_t a, int32x4_t b)
+foo (int32x4_t m1, int32x4_t m2)
{
- return vmlaldavq_s32 (a, b);
+ return vmlaldavq_s32 (m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldav.s32" } } */
+/*
+**foo1:
+** ...
+** vmlaldav.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int32x4_t a, int32x4_t b)
+foo1 (int32x4_t m1, int32x4_t m2)
{
- return vmlaldavq (a, b);
+ return vmlaldavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldav.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c
index c9c40eeac0a..d1fcf715cb7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldav.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo (uint16x8_t a, uint16x8_t b)
+foo (uint16x8_t m1, uint16x8_t m2)
{
- return vmlaldavq_u16 (a, b);
+ return vmlaldavq_u16 (m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldav.u16" } } */
+/*
+**foo1:
+** ...
+** vmlaldav.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo1 (uint16x8_t a, uint16x8_t b)
+foo1 (uint16x8_t m1, uint16x8_t m2)
{
- return vmlaldavq (a, b);
+ return vmlaldavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldav.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c
index 4d1754697bf..76726e8255b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldav.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo (uint32x4_t a, uint32x4_t b)
+foo (uint32x4_t m1, uint32x4_t m2)
{
- return vmlaldavq_u32 (a, b);
+ return vmlaldavq_u32 (m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldav.u32" } } */
+/*
+**foo1:
+** ...
+** vmlaldav.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo1 (uint32x4_t a, uint32x4_t b)
+foo1 (uint32x4_t m1, uint32x4_t m2)
{
- return vmlaldavq (a, b);
+ return vmlaldavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldav.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c
index d41c2e16114..3b8392bcf7f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmlaldavxq_p_s16 (a, b, p);
+ return vmlaldavxq_p_s16 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavxt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmlaldavxq_p (a, b, p);
+ return vmlaldavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavxt.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c
index 8ad7b219a0f..578b7b68095 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmlaldavxq_p_s32 (a, b, p);
+ return vmlaldavxq_p_s32 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmlaldavxq_p (a, b, p);
+ return vmlaldavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavxt.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c
index ebe999393e8..7061bd2c13d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldavx.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int16x8_t a, int16x8_t b)
+foo (int16x8_t m1, int16x8_t m2)
{
- return vmlaldavxq_s16 (a, b);
+ return vmlaldavxq_s16 (m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldavx.s16" } } */
+/*
+**foo1:
+** ...
+** vmlaldavx.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int16x8_t a, int16x8_t b)
+foo1 (int16x8_t m1, int16x8_t m2)
{
- return vmlaldavxq (a, b);
+ return vmlaldavxq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavx.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c
index 0417eb867de..957dc174a36 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldavx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int32x4_t a, int32x4_t b)
+foo (int32x4_t m1, int32x4_t m2)
{
- return vmlaldavxq_s32 (a, b);
+ return vmlaldavxq_s32 (m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldavx.s32" } } */
+/*
+**foo1:
+** ...
+** vmlaldavx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int32x4_t a, int32x4_t b)
+foo1 (int32x4_t m1, int32x4_t m2)
{
- return vmlaldavxq (a, b);
+ return vmlaldavxq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavx.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c
index d48b020d595..f68fe8e49a3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
{
- return vmlaq_m_n_s16 (a, b, c, p);
+ return vmlaq_m_n_s16 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo1 (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
{
- return vmlaq_m (a, b, c, p);
+ return vmlaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c
index 315c1afc2c7..d3c49553596 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
{
- return vmlaq_m_n_s32 (a, b, c, p);
+ return vmlaq_m_n_s32 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo1 (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
{
- return vmlaq_m (a, b, c, p);
+ return vmlaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c
index a452f5de5e6..44dc3b57cdd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
{
- return vmlaq_m_n_s8 (a, b, c, p);
+ return vmlaq_m_n_s8 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo1 (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
{
- return vmlaq_m (a, b, c, p);
+ return vmlaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c
index 6ecdc689a61..cbb92fb39b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c
@@ -1,23 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p)
+foo (uint16x8_t add, uint16x8_t m1, uint16_t m2, mve_pred16_t p)
{
- return vmlaq_m_n_u16 (a, b, c, p);
+ return vmlaq_m_n_u16 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
-foo1 (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p)
+foo1 (uint16x8_t add, uint16x8_t m1, uint16_t m2, mve_pred16_t p)
{
- return vmlaq_m (a, b, c, p);
+ return vmlaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo2 (uint16x8_t add, uint16x8_t m1, mve_pred16_t p)
+{
+ return vmlaq_m (add, m1, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c
index 2c584a635e7..569ea91af36 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c
@@ -1,23 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p)
+foo (uint32x4_t add, uint32x4_t m1, uint32_t m2, mve_pred16_t p)
{
- return vmlaq_m_n_u32 (a, b, c, p);
+ return vmlaq_m_n_u32 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p)
+foo1 (uint32x4_t add, uint32x4_t m1, uint32_t m2, mve_pred16_t p)
{
- return vmlaq_m (a, b, c, p);
+ return vmlaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint32x4_t
+foo2 (uint32x4_t add, uint32x4_t m1, mve_pred16_t p)
+{
+ return vmlaq_m (add, m1, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c
index b75b3c95916..592ad3e072a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c
@@ -1,23 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
-foo (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p)
+foo (uint8x16_t add, uint8x16_t m1, uint8_t m2, mve_pred16_t p)
{
- return vmlaq_m_n_u8 (a, b, c, p);
+ return vmlaq_m_n_u8 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
-foo1 (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p)
+foo1 (uint8x16_t add, uint8x16_t m1, uint8_t m2, mve_pred16_t p)
{
- return vmlaq_m (a, b, c, p);
+ return vmlaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint8x16_t
+foo2 (uint8x16_t add, uint8x16_t m1, mve_pred16_t p)
+{
+ return vmlaq_m (add, m1, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c
index 29543c8f60d..d1fa73de1c9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmla.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c)
+foo (int16x8_t add, int16x8_t m1, int16_t m2)
{
- return vmlaq_n_s16 (a, b, c);
+ return vmlaq_n_s16 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmla.s16" } } */
+/*
+**foo1:
+** ...
+** vmla.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c)
+foo1 (int16x8_t add, int16x8_t m1, int16_t m2)
{
- return vmlaq (a, b, c);
+ return vmlaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmla.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c
index d74bacaffd7..c349c0c8d7f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmla.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c)
+foo (int32x4_t add, int32x4_t m1, int32_t m2)
{
- return vmlaq_n_s32 (a, b, c);
+ return vmlaq_n_s32 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmla.s32" } } */
+/*
+**foo1:
+** ...
+** vmla.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c)
+foo1 (int32x4_t add, int32x4_t m1, int32_t m2)
{
- return vmlaq (a, b, c);
+ return vmlaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmla.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c
index 38dd01a6580..c1cd39e5715 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmla.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c)
+foo (int8x16_t add, int8x16_t m1, int8_t m2)
{
- return vmlaq_n_s8 (a, b, c);
+ return vmlaq_n_s8 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmla.s8" } } */
+/*
+**foo1:
+** ...
+** vmla.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c)
+foo1 (int8x16_t add, int8x16_t m1, int8_t m2)
{
- return vmlaq (a, b, c);
+ return vmlaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmla.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c
index 55a5d0601d5..5eb201c05e8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmla.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint16x8_t a, uint16x8_t b, uint16_t c)
+foo (uint16x8_t add, uint16x8_t m1, uint16_t m2)
{
- return vmlaq_n_u16 (a, b, c);
+ return vmlaq_n_u16 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmla.u16" } } */
+/*
+**foo1:
+** ...
+** vmla.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
-foo1 (uint16x8_t a, uint16x8_t b, uint16_t c)
+foo1 (uint16x8_t add, uint16x8_t m1, uint16_t m2)
{
- return vmlaq (a, b, c);
+ return vmlaq (add, m1, m2);
+}
+
+/*
+**foo2:
+** ...
+** vmla.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo2 (uint16x8_t add, uint16x8_t m1)
+{
+ return vmlaq (add, m1, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmla.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c
index e160275a29b..d4820ea65d9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmla.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, uint32_t c)
+foo (uint32x4_t add, uint32x4_t m1, uint32_t m2)
{
- return vmlaq_n_u32 (a, b, c);
+ return vmlaq_n_u32 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmla.u32" } } */
+/*
+**foo1:
+** ...
+** vmla.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, uint32_t c)
+foo1 (uint32x4_t add, uint32x4_t m1, uint32_t m2)
{
- return vmlaq (a, b, c);
+ return vmlaq (add, m1, m2);
+}
+
+/*
+**foo2:
+** ...
+** vmla.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint32x4_t
+foo2 (uint32x4_t add, uint32x4_t m1)
+{
+ return vmlaq (add, m1, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmla.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c
index 5f0edef53d4..7f83f092b07 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmla.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
-foo (uint8x16_t a, uint8x16_t b, uint8_t c)
+foo (uint8x16_t add, uint8x16_t m1, uint8_t m2)
{
- return vmlaq_n_u8 (a, b, c);
+ return vmlaq_n_u8 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmla.u8" } } */
+/*
+**foo1:
+** ...
+** vmla.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
-foo1 (uint8x16_t a, uint8x16_t b, uint8_t c)
+foo1 (uint8x16_t add, uint8x16_t m1, uint8_t m2)
{
- return vmlaq (a, b, c);
+ return vmlaq (add, m1, m2);
+}
+
+/*
+**foo2:
+** ...
+** vmla.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint8x16_t
+foo2 (uint8x16_t add, uint8x16_t m1)
+{
+ return vmlaq (add, m1, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmla.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c
index 3b250c1bf79..e8d1b5fd3d0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavat.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
{
return vmlsdavaq_p_s16 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavat.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavat.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
{
return vmlsdavaq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavat.s16" } } */
-/* { dg-final { scan-assembler "vmlsdavat.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c
index 077c5980e66..effbf24d997 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavat.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vmlsdavaq_p_s32 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavat.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavat.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vmlsdavaq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavat.s32" } } */
-/* { dg-final { scan-assembler "vmlsdavat.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c
index 2e53f5530b1..de04f9fd089 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavat.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
{
return vmlsdavaq_p_s8 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavat.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavat.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
{
return vmlsdavaq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavat.s8" } } */
-/* { dg-final { scan-assembler "vmlsdavat.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c
index e127be940b4..f66f652f6fd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdava.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int16x8_t b, int16x8_t c)
{
return vmlsdavaq_s16 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdava.s16" } } */
+/*
+**foo1:
+** ...
+** vmlsdava.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int16x8_t b, int16x8_t c)
{
return vmlsdavaq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdava.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c
index 20f879c6b69..79ba85ddb02 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdava.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int32x4_t b, int32x4_t c)
{
return vmlsdavaq_s32 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdava.s32" } } */
+/*
+**foo1:
+** ...
+** vmlsdava.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int32x4_t b, int32x4_t c)
{
return vmlsdavaq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdava.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c
index 3cbed73f660..3e0f9dc2649 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdava.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int8x16_t b, int8x16_t c)
{
return vmlsdavaq_s8 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdava.s8" } } */
+/*
+**foo1:
+** ...
+** vmlsdava.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int8x16_t b, int8x16_t c)
{
return vmlsdavaq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdava.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c
index 37aee878b97..61e88ce8fb8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavaxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
{
return vmlsdavaxq_p_s16 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavaxt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavaxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
{
return vmlsdavaxq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavaxt.s16" } } */
-/* { dg-final { scan-assembler "vmlsdavaxt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c
index 6a15d3cf97b..cbc2c71423e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavaxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vmlsdavaxq_p_s32 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavaxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavaxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vmlsdavaxq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavaxt.s32" } } */
-/* { dg-final { scan-assembler "vmlsdavaxt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c
index d090e625e1b..2b30e8a9c12 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavaxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
{
return vmlsdavaxq_p_s8 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavaxt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavaxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
{
return vmlsdavaxq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavaxt.s8" } } */
-/* { dg-final { scan-assembler "vmlsdavaxt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c
index 0ef5302ef80..90fd85a170e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdavax.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int16x8_t b, int16x8_t c)
{
return vmlsdavaxq_s16 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdavax.s16" } } */
+/*
+**foo1:
+** ...
+** vmlsdavax.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int16x8_t b, int16x8_t c)
{
return vmlsdavaxq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdavax.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c
index 71a5e1a987f..06fe27faf49 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdavax.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int32x4_t b, int32x4_t c)
{
return vmlsdavaxq_s32 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdavax.s32" } } */
+/*
+**foo1:
+** ...
+** vmlsdavax.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int32x4_t b, int32x4_t c)
{
return vmlsdavaxq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdavax.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c
index 7df6b9f7f32..70a44b49d8e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdavax.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int8x16_t b, int8x16_t c)
{
return vmlsdavaxq_s8 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdavax.s8" } } */
+/*
+**foo1:
+** ...
+** vmlsdavax.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int8x16_t b, int8x16_t c)
{
return vmlsdavaxq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdavax.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c
index f71dda19c57..09db9a3a90a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vmlsdavq_p_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vmlsdavq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c
index 255235ba372..8eb9d24263a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vmlsdavq_p_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vmlsdavq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c
index 2fc892db2eb..166fedea45c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vmlsdavq_p_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vmlsdavq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c
index 7376b07865b..b97252f7225 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int16x8_t a, int16x8_t b)
{
return vmlsdavq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vmlsdav.s16" } } */
+/*
+**foo1:
+** ...
+** vmlsdav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int16x8_t a, int16x8_t b)
{
return vmlsdavq (a, b);
}
-/* { dg-final { scan-assembler "vmlsdav.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c
index a37042eab30..5473cfe22fc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32x4_t a, int32x4_t b)
{
return vmlsdavq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vmlsdav.s32" } } */
+/*
+**foo1:
+** ...
+** vmlsdav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32x4_t a, int32x4_t b)
{
return vmlsdavq (a, b);
}
-/* { dg-final { scan-assembler "vmlsdav.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c
index b44b98bc7e4..487097118fd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int8x16_t a, int8x16_t b)
{
return vmlsdavq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vmlsdav.s8" } } */
+/*
+**foo1:
+** ...
+** vmlsdav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int8x16_t a, int8x16_t b)
{
return vmlsdavq (a, b);
}
-/* { dg-final { scan-assembler "vmlsdav.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c
index aa4ac4e4f01..d1ff9a0fa1c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vmlsdavxq_p_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavxt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vmlsdavxq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavxt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c
index 0de81290d99..09c19c1f161 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vmlsdavxq_p_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vmlsdavxq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavxt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c
index 68588f6951a..1f364a3e846 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vmlsdavxq_p_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavxt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vmlsdavxq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavxt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c
index 8f49d6a6106..1c0675fb44b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdavx.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int16x8_t a, int16x8_t b)
{
return vmlsdavxq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vmlsdavx.s16" } } */
+/*
+**foo1:
+** ...
+** vmlsdavx.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int16x8_t a, int16x8_t b)
{
return vmlsdavxq (a, b);
}
-/* { dg-final { scan-assembler "vmlsdavx.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c
index 830cd4ca8b1..5986e130ec0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdavx.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32x4_t a, int32x4_t b)
{
return vmlsdavxq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vmlsdavx.s32" } } */
+/*
+**foo1:
+** ...
+** vmlsdavx.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32x4_t a, int32x4_t b)
{
return vmlsdavxq (a, b);
}
-/* { dg-final { scan-assembler "vmlsdavx.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c
index 74feb60b005..4f8aa44b57a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdavx.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int8x16_t a, int8x16_t b)
{
return vmlsdavxq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vmlsdavx.s8" } } */
+/*
+**foo1:
+** ...
+** vmlsdavx.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int8x16_t a, int8x16_t b)
{
return vmlsdavxq (a, b);
}
-/* { dg-final { scan-assembler "vmlsdavx.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c
index 78d29b058a3..8d0a03c0213 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavat.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
{
return vmlsldavaq_p_s16 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsldavat.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavat.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
{
return vmlsldavaq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsldavat.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c
index fca0ef1d3dc..fae2ad5c713 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vmlsldavaq_p_s32 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsldavat.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vmlsldavaq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsldavat.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c
index aecfcee4571..bfe4010df68 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsldava.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int16x8_t b, int16x8_t c)
{
return vmlsldavaq_s16 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsldava.s16" } } */
+/*
+**foo1:
+** ...
+** vmlsldava.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int16x8_t b, int16x8_t c)
{
return vmlsldavaq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsldava.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c
index 7344a50f02b..b023b1b67ee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsldava.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c)
{
return vmlsldavaq_s32 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsldava.s32" } } */
+/*
+**foo1:
+** ...
+** vmlsldava.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c)
{
return vmlsldavaq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsldava.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c
index 5278bd842cc..1ffa8c28ea9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavaxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
{
return vmlsldavaxq_p_s16 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsldavaxt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavaxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
{
return vmlsldavaxq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsldavaxt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c
index 07efdf96f10..aa5001705c1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vmlsldavaxq_p_s32 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsldavaxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vmlsldavaxq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsldavaxt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c
index 6a51d9f3d93..7772b3da069 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsldavax.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int16x8_t b, int16x8_t c)
{
return vmlsldavaxq_s16 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsldavax.s16" } } */
+/*
+**foo1:
+** ...
+** vmlsldavax.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int16x8_t b, int16x8_t c)
{
return vmlsldavaxq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsldavax.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c
index 275776388d2..eba923f15d8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsldavax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c)
{
return vmlsldavaxq_s32 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsldavax.s32" } } */
+/*
+**foo1:
+** ...
+** vmlsldavax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c)
{
return vmlsldavaxq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsldavax.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c
index 6eedf07efd6..79ed4c94b64 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vmlsldavq_p_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsldavt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vmlsldavq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsldavt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c
index b36ea49612c..44982f89edf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vmlsldavq_p_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsldavt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vmlsldavq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsldavt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c
index f05841798c9..dbdf1deae04 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsldav.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int16x8_t a, int16x8_t b)
{
return vmlsldavq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vmlsldav.s16" } } */
+/*
+**foo1:
+** ...
+** vmlsldav.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int16x8_t a, int16x8_t b)
{
return vmlsldavq (a, b);
}
-/* { dg-final { scan-assembler "vmlsldav.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c
index 45bee16ab79..458f14c446f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsldav.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b)
{
return vmlsldavq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vmlsldav.s32" } } */
+/*
+**foo1:
+** ...
+** vmlsldav.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b)
{
return vmlsldavq (a, b);
}
-/* { dg-final { scan-assembler "vmlsldav.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c
index 821f4eae90a..9481550f526 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vmlsldavxq_p_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsldavxt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vmlsldavxq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsldavxt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c
index 77e84d07486..cc20e554932 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vmlsldavxq_p_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsldavxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vmlsldavxq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsldavxt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c
index dcd88f8db73..7a4d9365ed6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsldavx.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int16x8_t a, int16x8_t b)
{
return vmlsldavxq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vmlsldavx.s16" } } */
+/*
+**foo1:
+** ...
+** vmlsldavx.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int16x8_t a, int16x8_t b)
{
return vmlsldavxq (a, b);
}
-/* { dg-final { scan-assembler "vmlsldavx.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c
index d59550ba69e..b241569d75c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsldavx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b)
{
return vmlsldavxq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vmlsldavx.s32" } } */
+/*
+**foo1:
+** ...
+** vmlsldavx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b)
{
return vmlsldavxq (a, b);
}
-/* { dg-final { scan-assembler "vmlsldavx.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c
index b7ce6ce9c2a..69c2f91b50e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
{
return vmovlbq_m_s16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
{
return vmovlbq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c
index d15df32831d..2b3cfacb5f3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
{
return vmovlbq_m_s8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
{
return vmovlbq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c
index dcd9dc43692..39398b2cde9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vmovlbq_m_u16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vmovlbq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c
index dbdeb263086..30ca18ad103 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vmovlbq_m_u8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vmovlbq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c
index a6b5cbb1527..8ce0da68113 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovlb.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int16x8_t a)
{
return vmovlbq_s16 (a);
}
-/* { dg-final { scan-assembler "vmovlb.s16" } } */
+/*
+**foo1:
+** ...
+** vmovlb.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int16x8_t a)
{
return vmovlbq (a);
}
-/* { dg-final { scan-assembler "vmovlb.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c
index 4ead765bb6e..36fbce37bf8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovlb.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int8x16_t a)
{
return vmovlbq_s8 (a);
}
-/* { dg-final { scan-assembler "vmovlb.s8" } } */
+/*
+**foo1:
+** ...
+** vmovlb.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int8x16_t a)
{
return vmovlbq (a);
}
-/* { dg-final { scan-assembler "vmovlb.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c
index fec88bb7f79..b90728e9956 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovlb.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint16x8_t a)
{
- return vmovlbq_u16 (a);
+ return vmovlbq_u16 (a);
}
-/* { dg-final { scan-assembler "vmovlb.u16" } } */
+/*
+**foo1:
+** ...
+** vmovlb.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint16x8_t a)
{
- return vmovlbq (a);
+ return vmovlbq (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmovlb.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c
index af6d804696a..5299f581329 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovlb.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint8x16_t a)
{
- return vmovlbq_u8 (a);
+ return vmovlbq_u8 (a);
}
-/* { dg-final { scan-assembler "vmovlb.u8" } } */
+/*
+**foo1:
+** ...
+** vmovlb.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint8x16_t a)
{
- return vmovlbq (a);
+ return vmovlbq (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmovlb.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c
index 393fc5523a7..63d2ddb9015 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int16x8_t a, mve_pred16_t p)
{
return vmovlbq_x_s16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int16x8_t a, mve_pred16_t p)
{
return vmovlbq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c
index 3773be0b621..b573f572012 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int8x16_t a, mve_pred16_t p)
{
return vmovlbq_x_s8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int8x16_t a, mve_pred16_t p)
{
return vmovlbq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c
index b668eeb6fcf..f039019f5b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vmovlbq_x_u16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vmovlbq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c
index 6019e2d09d7..7fb32ece22d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint8x16_t a, mve_pred16_t p)
{
return vmovlbq_x_u8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint8x16_t a, mve_pred16_t p)
{
return vmovlbq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c
index 47897a3913f..72ca8c8bb9b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
{
return vmovltq_m_s16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
{
return vmovltq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c
index c87b263db51..7e3b4f40bc5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
{
return vmovltq_m_s8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
{
return vmovltq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c
index cfe7cd7a5d3..4320df794ab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vmovltq_m_u16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vmovltq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c
index a9119fbb940..c9a75a590b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vmovltq_m_u8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vmovltq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c
index a7fd325e330..f431cda53ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovlt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int16x8_t a)
{
return vmovltq_s16 (a);
}
-/* { dg-final { scan-assembler "vmovlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmovlt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int16x8_t a)
{
return vmovltq (a);
}
-/* { dg-final { scan-assembler "vmovlt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c
index c392e56b60b..d65f8066454 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovlt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int8x16_t a)
{
return vmovltq_s8 (a);
}
-/* { dg-final { scan-assembler "vmovlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmovlt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int8x16_t a)
{
return vmovltq (a);
}
-/* { dg-final { scan-assembler "vmovlt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c
index 7634af6f45a..5469671041b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovlt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint16x8_t a)
{
- return vmovltq_u16 (a);
+ return vmovltq_u16 (a);
}
-/* { dg-final { scan-assembler "vmovlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmovlt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint16x8_t a)
{
- return vmovltq (a);
+ return vmovltq (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmovlt.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c
index 2c0d1a7c69d..a14c71cdfbc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovlt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint8x16_t a)
{
- return vmovltq_u8 (a);
+ return vmovltq_u8 (a);
}
-/* { dg-final { scan-assembler "vmovlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmovlt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint8x16_t a)
{
- return vmovltq (a);
+ return vmovltq (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmovlt.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c
index ae6c8999835..f8e24c4e0d3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int16x8_t a, mve_pred16_t p)
{
return vmovltq_x_s16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int16x8_t a, mve_pred16_t p)
{
return vmovltq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c
index 1172643218a..b97de081858 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int8x16_t a, mve_pred16_t p)
{
return vmovltq_x_s8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int8x16_t a, mve_pred16_t p)
{
return vmovltq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c
index 64442dcf935..851264e45ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vmovltq_x_u16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vmovltq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c
index 33e571890c0..82219b670db 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint8x16_t a, mve_pred16_t p)
{
return vmovltq_x_u8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint8x16_t a, mve_pred16_t p)
{
return vmovltq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c
index fdb392cbf81..3bd9b82cbb3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovnbt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vmovnbq_m_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovnbt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovnbt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vmovnbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c
index 9f32f49d24e..bc2f95c7d8a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovnbt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vmovnbq_m_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovnbt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovnbt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vmovnbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c
index ebc1599af54..1624237c67a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovnbt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vmovnbq_m_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovnbt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovnbt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vmovnbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c
index 502068713e9..1a2f1e8441e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovnbt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vmovnbq_m_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovnbt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovnbt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vmovnbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c
index a49943fd25a..d5286f11259 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovnb.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vmovnbq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vmovnb.i16" } } */
+/*
+**foo1:
+** ...
+** vmovnb.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vmovnbq (a, b);
}
-/* { dg-final { scan-assembler "vmovnb.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c
index 6dbce232399..b6b44837b8c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovnb.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vmovnbq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vmovnb.i32" } } */
+/*
+**foo1:
+** ...
+** vmovnb.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vmovnbq (a, b);
}
-/* { dg-final { scan-assembler "vmovnb.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c
index f3df71a43eb..1203ac5c7f5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovnb.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vmovnbq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vmovnb.i16" } } */
+/*
+**foo1:
+** ...
+** vmovnb.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vmovnbq (a, b);
}
-/* { dg-final { scan-assembler "vmovnb.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c
index e0369ed5fa2..de5bb111783 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovnb.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vmovnbq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vmovnb.i32" } } */
+/*
+**foo1:
+** ...
+** vmovnb.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vmovnbq (a, b);
}
-/* { dg-final { scan-assembler "vmovnb.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c
index f305ab30dc8..594f72c08f5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovntt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vmovntq_m_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovntt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovntt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vmovntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c
index 59820c610e6..b3e3e0442c5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovntt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vmovntq_m_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovntt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovntt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vmovntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c
index 079b162148e..a3e33db311e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovntt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vmovntq_m_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovntt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovntt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vmovntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c
index 7c09b2e4f9f..b5629493c72 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovntt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vmovntq_m_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovntt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovntt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vmovntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c
index 229cd5809d9..d7e369d266e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovnt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vmovntq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vmovnt.i16" } } */
+/*
+**foo1:
+** ...
+** vmovnt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vmovntq (a, b);
}
-/* { dg-final { scan-assembler "vmovnt.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c
index 01921cbd66e..6d87cc21aaa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovnt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vmovntq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vmovnt.i32" } } */
+/*
+**foo1:
+** ...
+** vmovnt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vmovntq (a, b);
}
-/* { dg-final { scan-assembler "vmovnt.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c
index 30e75b2169d..f85e45a666a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovnt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vmovntq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vmovnt.i16" } } */
+/*
+**foo1:
+** ...
+** vmovnt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vmovntq (a, b);
}
-/* { dg-final { scan-assembler "vmovnt.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c
index 9ed963dda70..05c4af3d614 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovnt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vmovntq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vmovnt.i32" } } */
+/*
+**foo1:
+** ...
+** vmovnt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vmovntq (a, b);
}
-/* { dg-final { scan-assembler "vmovnt.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c
index 1b6e683700c..9d4804a0057 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, mve_pred16_t p)
{
- return vmvnq_m_n_s16 (inactive, 2, p);
+ return vmvnq_m_n_s16 (inactive, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, mve_pred16_t p)
{
- return vmvnq_m (inactive, 2, p);
+ return vmvnq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c
index dcfd69fb7f1..607cdfca33e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, mve_pred16_t p)
{
- return vmvnq_m_n_s32 (inactive, 2, p);
+ return vmvnq_m_n_s32 (inactive, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, mve_pred16_t p)
{
- return vmvnq_m (inactive, 2, p);
+ return vmvnq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c
index bd86fa806b8..7b0b5a9ef83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, mve_pred16_t p)
{
- return vmvnq_m_n_u16 (inactive, 4, p);
+ return vmvnq_m_n_u16 (inactive, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, mve_pred16_t p)
{
- return vmvnq_m (inactive, 4, p);
+ return vmvnq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c
index 2ac6ef192d7..2217420081e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, mve_pred16_t p)
{
- return vmvnq_m_n_u32 (inactive, 4, p);
+ return vmvnq_m_n_u32 (inactive, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, mve_pred16_t p)
{
- return vmvnq_m (inactive, 4, p);
+ return vmvnq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c
index 5284b8fe054..e27d8111b54 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vmvnq_m_s16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vmvnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c
index da16a5d45d6..8a264a1e76f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vmvnq_m_s32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vmvnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c
index 206759247c5..c4374d0ffd4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vmvnq_m_s8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vmvnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c
index 9940cec4bfe..3d5d56eadfe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vmvnq_m_u16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vmvnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c
index 25179f13f95..fd1961e0673 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vmvnq_m_u32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vmvnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c
index 7237db35b33..037d1f4ce39 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vmvnq_m_u8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vmvnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c
index 336c6aa63c4..975639334d5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo ()
{
return vmvnq_n_s16 (1);
}
-/* { dg-final { scan-assembler "vmvn.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c
index 354c39c8f7b..0e09343e6c3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo ()
{
- return vmvnq_n_s32 (2);
+ return vmvnq_n_s32 (1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmvn.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c
index 178b003091b..84e158ade93 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo ()
{
- return vmvnq_n_u16 (1);
+ return vmvnq_n_u16 (1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmvn.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c
index 4819066bdbd..168b77a400a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo ()
{
- return vmvnq_n_u32 (2);
+ return vmvnq_n_u32 (1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmvn.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c
index 840d834ea9e..30ddcd9118e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a)
{
return vmvnq_s16 (a);
}
-/* { dg-final { scan-assembler "vmvn" } } */
+/*
+**foo1:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a)
{
return vmvnq (a);
}
-/* { dg-final { scan-assembler "vmvn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c
index cf73bc088c7..48d66753c0f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a)
{
return vmvnq_s32 (a);
}
-/* { dg-final { scan-assembler "vmvn" } } */
+/*
+**foo1:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a)
{
return vmvnq (a);
}
-/* { dg-final { scan-assembler "vmvn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c
index 6d239391cbb..199bb0f81c3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a)
{
return vmvnq_s8 (a);
}
-/* { dg-final { scan-assembler "vmvn" } } */
+/*
+**foo1:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a)
{
return vmvnq (a);
}
-/* { dg-final { scan-assembler "vmvn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c
index db348328513..c2d724f5375 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a)
{
- return vmvnq_u16 (a);
+ return vmvnq_u16 (a);
}
-/* { dg-final { scan-assembler "vmvn" } } */
+/*
+**foo1:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a)
{
- return vmvnq (a);
+ return vmvnq (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmvn" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c
index c007a959078..8bafe68f21c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a)
{
- return vmvnq_u32 (a);
+ return vmvnq_u32 (a);
}
-/* { dg-final { scan-assembler "vmvn" } } */
+/*
+**foo1:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a)
{
- return vmvnq (a);
+ return vmvnq (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmvn" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c
index 2288a283d60..684e5bc94f1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a)
{
- return vmvnq_u8 (a);
+ return vmvnq_u8 (a);
}
-/* { dg-final { scan-assembler "vmvn" } } */
+/*
+**foo1:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a)
{
- return vmvnq (a);
+ return vmvnq (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmvn" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c
index b00ccc3e672..a4d575e4aba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (mve_pred16_t p)
{
- return vmvnq_x_n_s16 (2, p);
+ return vmvnq_x_n_s16 (1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c
index ea65104b4b3..9ca5c90d80e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (mve_pred16_t p)
{
- return vmvnq_x_n_s32 (2, p);
+ return vmvnq_x_n_s32 (1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c
index 2fa4e40ad5d..9fbf2b978ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (mve_pred16_t p)
{
- return vmvnq_x_n_u16 (4, p);
+ return vmvnq_x_n_u16 (1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c
index b39e681c116..883e9af1609 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (mve_pred16_t p)
{
- return vmvnq_x_n_u32 (4, p);
+ return vmvnq_x_n_u32 (1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c
index d4b87a795fc..6bd04f7dd38 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
return vmvnq_x_s16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, mve_pred16_t p)
{
return vmvnq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c
index 0bcdba0c1d6..6af90408e9c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
return vmvnq_x_s32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, mve_pred16_t p)
{
return vmvnq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c
index ffa7306ace6..8c6f118c36f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, mve_pred16_t p)
{
return vmvnq_x_s8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, mve_pred16_t p)
{
return vmvnq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c
index 29b5ad950ea..2e9902f3858 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vmvnq_x_u16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vmvnq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c
index b3d5f73cd92..53b2ebdd457 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, mve_pred16_t p)
{
return vmvnq_x_u32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, mve_pred16_t p)
{
return vmvnq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c
index f085aa83662..ad7a5a9398c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, mve_pred16_t p)
{
return vmvnq_x_u8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, mve_pred16_t p)
{
return vmvnq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c
index 7cf00d94084..36543ee6bff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vornq_f16 (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+/*
+**foo1:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vornq (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c
index d187bde1dc2..c3d73059c31 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vornq_f32 (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+/*
+**foo1:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vornq (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c
index 081872bada1..7a5cabf4396 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vornq_m_f16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vornq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c
index fe92dae6ec6..8fb90212c88 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vornq_m_f32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vornq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c
index 56a2b64bc29..31123f853f8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vornq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vornq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c
index c2e4b1267b8..e5d6d63955b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vornq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vornq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c
index 6607808e96e..73bde2bcfde 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vornq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vornq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c
index 1905ed193ac..2872c0a7045 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vornq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vornq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c
index 6d6620c3e07..90e8df24b99 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vornq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vornq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c
index 23e8d046c73..eedbf3a1ae1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vornq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vornq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c
index 0f73ea28e0d..ac92a93f19c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vornq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+/*
+**foo1:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vornq (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c
index 7d9835fc1b8..38be3483872 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vornq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+/*
+**foo1:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vornq (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c
index f2ba62292f5..3d5e47fa1e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vornq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+/*
+**foo1:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vornq (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c
index baa3fd80813..e69212d59b0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b)
{
return vornq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+/*
+**foo1:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b)
{
return vornq (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c
index 481db437b77..c89622c830f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b)
{
return vornq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+/*
+**foo1:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b)
{
return vornq (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c
index 575a7365487..61ce5ad294a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b)
{
return vornq_u8 (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+/*
+**foo1:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b)
{
return vornq (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c
index d776bff2416..2bc10776f6d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vornq_x_f16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vornq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c
index 939e8fafb83..7b733cf6a6b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vornq_x_f32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vornq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c
index 77569b42cc8..beba497bbf9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vornq_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vornq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c
index 29cfd020c30..60e6125ed6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vornq_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vornq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c
index fd10ff8e719..f62c9b2a111 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vornq_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vornq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c
index 473f22abd52..2ac693ca30f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vornq_x_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vornq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c
index 010ac07454d..1981c8ca408 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vornq_x_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vornq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c
index 126a6d236b3..171dc0f58b6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vornq_x_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vornq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c
index 1481c43ae5f..3d222d5679b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vorrq_f16 (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+/*
+**foo1:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vorrq (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c
index 257edd99b7b..140817ee919 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vorrq_f32 (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+/*
+**foo1:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vorrq (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c
index 641c8f0f3bd..dbfac724131 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vorrq_m_f16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vorrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c
index b537a7c74c3..e13a1df44e2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vorrq_m_f32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vorrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c
index 757482a3a95..b591bd6fc11 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
- return vorrq_m_n_s16 (a, 253, p);
+ return vorrq_m_n_s16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, mve_pred16_t p)
{
- return vorrq_m_n (a, 253, p);
+ return vorrq_m_n (a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c
index 967e49e7a26..ce4dd3ee7bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
return vorrq_m_n_s32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, mve_pred16_t p)
{
return vorrq_m_n (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c
index 01022c32a88..9e7788484ad 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vorrq_m_n_u16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vorrq_m_n (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c
index 809237d1cf6..613c0e2f889 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, mve_pred16_t p)
{
return vorrq_m_n_u32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, mve_pred16_t p)
{
return vorrq_m_n (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c
index 2714810d591..d475f1e939f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vorrq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vorrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c
index c960b18631a..e171e93e4eb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vorrq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vorrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c
index d1d4bc721b0..17043b26c2e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vorrq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vorrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c
index 01190ea4812..19a752ec3b7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vorrq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vorrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c
index 502ceab2fe4..7f3985d1508 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vorrq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vorrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c
index 44cf1413ca6..5a04ebdf1de 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vorrq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vorrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c
index 63a369f9996..b95418d9668 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a)
{
return vorrq_n_s16 (a, 1);
}
-/* { dg-final { scan-assembler "vorr.i16" } } */
+
+/*
+**foo1:
+** ...
+** vorr.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int16x8_t
+foo1 (int16x8_t a)
+{
+ return vorrq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c
index cf7bbc8c46d..30248216012 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a)
{
return vorrq_n_s32 (a, 1);
}
-/* { dg-final { scan-assembler "vorr.i32" } } */
+
+/*
+**foo1:
+** ...
+** vorr.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int32x4_t
+foo1 (int32x4_t a)
+{
+ return vorrq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c
index 2d599e52f8d..1f131501aec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a)
{
return vorrq_n_u16 (a, 1);
}
-/* { dg-final { scan-assembler "vorr.i16" } } */
+
+/*
+**foo1:
+** ...
+** vorr.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo1 (uint16x8_t a)
+{
+ return vorrq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c
index 5a873d0d1a3..5bfdb0b2e14 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a)
{
- return vorrq_n_u32 (a, 44);
+ return vorrq_n_u32 (a, 1);
+}
+
+
+/*
+**foo1:
+** ...
+** vorr.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint32x4_t
+foo1 (uint32x4_t a)
+{
+ return vorrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vorr.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c
index 2a56912ab31..658df6f422f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vorrq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+/*
+**foo1:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vorrq (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c
index e80b991c95a..a0a24b7fd45 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vorrq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+/*
+**foo1:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vorrq (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c
index 3456477c07c..645c6144f46 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vorrq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+/*
+**foo1:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vorrq (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c
index bb7699c1e3b..cb618a1f793 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b)
{
return vorrq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+/*
+**foo1:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b)
{
return vorrq (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c
index e01f5413dc3..937102ff962 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b)
{
return vorrq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+/*
+**foo1:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b)
{
return vorrq (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c
index c7ad98805c4..07121b5b1c9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b)
{
return vorrq_u8 (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+/*
+**foo1:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b)
{
return vorrq (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c
index 2e678febb78..b34d102f470 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vorrq_x_f16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vorrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c
index 12acfb49773..d41a94e7a02 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vorrq_x_f32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vorrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c
index 75fe4541845..3e1d3e97d26 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vorrq_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vorrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c
index 37d17f046af..0982b3d2081 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vorrq_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vorrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c
index 3558db3b7b0..0a46246e124 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vorrq_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vorrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c
index 7c9a2559c87..ef83d9de2ee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vorrq_x_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vorrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c
index 13ff34d582a..b6abfd5b314 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vorrq_x_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vorrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c
index 781b2b59699..b724ed0562b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vorrq_x_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vorrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
index a84f84446c0..2b894d1d938 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
@@ -1,21 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpnot(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
foo (mve_pred16_t a)
{
return vpnot (a);
}
-/* { dg-final { scan-assembler "vpnot" } } */
-
-mve_pred16_t
-foo1 (mve_pred16_t a)
-{
- return vpnot (a);
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpnot" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c
index ff121b585ed..50127b4537d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vpselq_f16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c
index 35c84761f08..0733413f1ca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vpselq_f32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c
index 0e0c14ed49d..06ef70c4073 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vpselq_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c
index 0e746de6e07..87b4b2242eb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vpselq_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c
index f4bbb77e268..dedb812c11b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64x2_t
foo (int64x2_t a, int64x2_t b, mve_pred16_t p)
{
return vpselq_s64 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64x2_t
foo1 (int64x2_t a, int64x2_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c
index 65cd415c789..5050fc03556 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vpselq_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c
index 742ca17ac8e..055f3c00381 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vpselq_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c
index 9d2e01c31d4..11333822b19 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vpselq_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c
index 58c4169bc0a..c08e6c54d95 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64x2_t
foo (uint64x2_t a, uint64x2_t b, mve_pred16_t p)
{
return vpselq_u64 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64x2_t
foo1 (uint64x2_t a, uint64x2_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c
index 5f73ba44ea8..804aed384c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vpselq_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c
index bf5520ed1ff..dd6c0300c32 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovnbt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqmovnbq_m_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovnbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovnbt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqmovnbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c
index f07612a47d5..eb340ebe520 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovnbt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqmovnbq_m_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovnbt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovnbt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqmovnbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c
index 79f082fefab..673f453e7af 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovnbt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqmovnbq_m_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovnbt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovnbt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqmovnbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c
index 5d242dc497f..84f7f9bf897 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovnbt.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqmovnbq_m_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovnbt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovnbt.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqmovnbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c
index 18df48f5084..ed17eb81884 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovnb.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vqmovnbq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vqmovnb.s16" } } */
+/*
+**foo1:
+** ...
+** vqmovnb.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vqmovnbq (a, b);
}
-/* { dg-final { scan-assembler "vqmovnb.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c
index 37f9e817805..065ce9b246c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovnb.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vqmovnbq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vqmovnb.s32" } } */
+/*
+**foo1:
+** ...
+** vqmovnb.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vqmovnbq (a, b);
}
-/* { dg-final { scan-assembler "vqmovnb.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c
index 130dcb06944..29df4636e3d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovnb.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vqmovnbq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vqmovnb.u16" } } */
+/*
+**foo1:
+** ...
+** vqmovnb.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vqmovnbq (a, b);
}
-/* { dg-final { scan-assembler "vqmovnb.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c
index 8bf735294e5..422c33560d3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovnb.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vqmovnbq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vqmovnb.u32" } } */
+/*
+**foo1:
+** ...
+** vqmovnb.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vqmovnbq (a, b);
}
-/* { dg-final { scan-assembler "vqmovnb.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c
index bc624bcd877..b50964bd4f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovntt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqmovntq_m_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovntt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovntt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqmovntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c
index 429f25cdb0f..5d4947abb9f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovntt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqmovntq_m_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovntt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovntt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqmovntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c
index a453a9fc36a..8cfd62831eb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovntt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqmovntq_m_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovntt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovntt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqmovntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c
index 3f9ae8a5ee4..b9d3b7e75ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovntt.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqmovntq_m_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovntt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovntt.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqmovntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c
index 5de956cbac4..8838a242fd9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovnt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vqmovntq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vqmovnt.s16" } } */
+/*
+**foo1:
+** ...
+** vqmovnt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vqmovntq (a, b);
}
-/* { dg-final { scan-assembler "vqmovnt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c
index 30db31c47ee..1d8b0dc17ef 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovnt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vqmovntq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vqmovnt.s32" } } */
+/*
+**foo1:
+** ...
+** vqmovnt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vqmovntq (a, b);
}
-/* { dg-final { scan-assembler "vqmovnt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c
index 312ce4f865f..10badd5feb4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovnt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vqmovntq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vqmovnt.u16" } } */
+/*
+**foo1:
+** ...
+** vqmovnt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vqmovntq (a, b);
}
-/* { dg-final { scan-assembler "vqmovnt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c
index 20623384858..80460393001 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovnt.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vqmovntq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vqmovnt.u32" } } */
+/*
+**foo1:
+** ...
+** vqmovnt.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vqmovntq (a, b);
}
-/* { dg-final { scan-assembler "vqmovnt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c
index 8e46de63b84..d295b3f9155 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovunbt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqmovunbq_m_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovunbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovunbt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqmovunbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c
index d0ec95192f9..84b94db682f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovunbt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqmovunbq_m_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovunbt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovunbt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqmovunbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c
index 9b3b80d024f..070bb90bf12 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovunb.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b)
{
return vqmovunbq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vqmovunb.s16" } } */
+/*
+**foo1:
+** ...
+** vqmovunb.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b)
{
return vqmovunbq (a, b);
}
-/* { dg-final { scan-assembler "vqmovunb.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c
index 9cc43d987de..659e703a558 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovunb.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b)
{
return vqmovunbq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vqmovunb.s32" } } */
+/*
+**foo1:
+** ...
+** vqmovunb.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b)
{
return vqmovunbq (a, b);
}
-/* { dg-final { scan-assembler "vqmovunb.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c
index a81fb8863af..fb3b36c451e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovuntt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqmovuntq_m_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovuntt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovuntt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqmovuntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c
index e76ca2b5f48..f6fce6d4473 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovuntt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqmovuntq_m_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovuntt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovuntt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqmovuntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c
index 324d2e56f3c..3230f25998b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovunt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b)
{
return vqmovuntq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vqmovunt.s16" } } */
+/*
+**foo1:
+** ...
+** vqmovunt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b)
{
return vqmovuntq (a, b);
}
-/* { dg-final { scan-assembler "vqmovunt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c
index 80fee05b642..5333897a34a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovunt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b)
{
return vqmovuntq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vqmovunt.s32" } } */
+/*
+**foo1:
+** ...
+** vqmovunt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b)
{
return vqmovuntq (a, b);
}
-/* { dg-final { scan-assembler "vqmovunt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c
index 5b0e134a0ff..1140c25c4a2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c
index 6fdf3879cc2..b3e6dac19a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c
index ef75f737161..5ae74e1dd2d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c
index cf7cdb202ce..f515c3926da 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c
index 5a022fe3009..4693d01eeb4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c
index 2cb27df16f6..cea58e4f80a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c
index 1f68671b3f9..3b8ea613f1d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c
index eaea6e1f482..6ef932672bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c
index 0f582a91f3a..5b9dc5cadac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c
index a26898ebdab..745c70b84f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c
index 572486ecf82..94e976f724c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c
index 00e478b9d3e..f8c9f487068 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
index 304f86c6e51..f8400ac63d7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
index 265fecaf806..fa1131de6b5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
index d1687f79311..a7ce97cc2f6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c
index 4595d55711e..175a2f74416 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t add, int16x8_t m1, int16_t m2)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c
index 22d9ce56a35..56d5423bd3f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t add, int32x4_t m1, int32_t m2)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c
index 36a23ad2078..992be758837 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t add, int8x16_t m1, int8_t m2)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
index 2995682f252..d713c224b30 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
index 7e637e6900f..8af4928f833 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
index d81472d933a..9f30b7d0e13 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c
index 2710f2f0442..83caaab8926 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t m1, int16x8_t m2, int16_t add)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c
index 5fefc3938c5..337f33c51c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t m1, int32x4_t m2, int32_t add)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c
index df96fe85213..df005ee9b03 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t m1, int8x16_t m2, int8_t add)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c
index 6a5776215ca..52c7f16df12 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c
index 9539e249d6a..574809dde9b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c
index 69e54f53a76..9b509687ed9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c
index 3eb957d6029..19fdc151550 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c
index 3a3fb506c01..d50bd8500bd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c
index 65ac15da9c7..c3f6b3e462b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c
index 3598f50ccba..35fc3bde975 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c
index 1ab22edf9ca..7b5ee71194c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c
index 01103e99b61..0ceb9c55aa3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c
index 522d0ba4a3a..b94e4cca8b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c
index 5198dfa754e..0f508d9bca1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c
index b5baa3dea79..92607fe0265 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c
index fc3a33073aa..ae38058cc62 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c
index 897ad5bd28c..e923495f4b5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c
index 05ab0609af4..a6ce3b2ca01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c
index 1d9dc07787c..a8a749d07cb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c
index 76d7507e35a..ad6130dfbdc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c
index 7fd2119ea63..da29228e5f3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c
index 8a90a399858..342ef427bc9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t a, int16_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c
index 973464b3297..7ae72b75689 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t a, int32_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c
index 65aab964f4e..8acb72a2245 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t a, int8_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c
index f3153c86b4c..5e93d7758c0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t a, int16x8_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c
index 48b10dbd025..d2812c0aa05 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t a, int32x4_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c
index 9f0346fc841..5c188a6d91f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t a, int8x16_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c
index 8d5abfd7588..d9baa378fac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c
index 734f67ae251..ce4140a6fb8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c
index 3c6724f285b..ce576b01d65 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c
index 3e39599df8a..e861a7b1f6a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c
index 41f5945daf9..d4cb581c623 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c
index 9aad2599476..f170f225d95 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c
index 80045c5b583..7c5449fb168 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshlq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c
index 9b4cf1663cd..53a421cf830 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshlq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c
index 55e0dd57023..52ad4372916 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vqrshlq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vqrshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c
index cd5605444a1..e7ca4786363 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshlq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c
index 02c94d0a51f..3785bbea0dc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshlq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c
index e6058dfc4c5..c736abeceab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vqrshlq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vqrshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c
index 46fd917d2d9..231ce85f1a3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32_t b)
{
return vqrshlq_n_s16 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s16" } } */
+/*
+**foo1:
+** ...
+** vqrshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c
index 373de10b89c..05589eb86cc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32_t b)
{
return vqrshlq_n_s32 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s32" } } */
+/*
+**foo1:
+** ...
+** vqrshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c
index d05d2fc722f..182e7cf260a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int32_t b)
{
return vqrshlq_n_s8 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s8" } } */
+/*
+**foo1:
+** ...
+** vqrshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int32_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c
index 8a74d61e75d..1b5214623c6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32_t b)
{
return vqrshlq_n_u16 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u16" } } */
+/*
+**foo1:
+** ...
+** vqrshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c
index ccb0db7bb32..50d09bac3a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32_t b)
{
return vqrshlq_n_u32 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u32" } } */
+/*
+**foo1:
+** ...
+** vqrshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c
index c3319ea29d2..846d90a2470 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int32_t b)
{
return vqrshlq_n_u8 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u8" } } */
+/*
+**foo1:
+** ...
+** vqrshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int32_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c
index c5645cee518..2a4a0feb5e6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vqrshlq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s16" } } */
+/*
+**foo1:
+** ...
+** vqrshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c
index b773ccf9245..94665928299 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vqrshlq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s32" } } */
+/*
+**foo1:
+** ...
+** vqrshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c
index 1a61cb6de10..2836a6e4dc8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vqrshlq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s8" } } */
+/*
+**foo1:
+** ...
+** vqrshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c
index 8de05a290b7..2ea554253c1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int16x8_t b)
{
return vqrshlq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u16" } } */
+/*
+**foo1:
+** ...
+** vqrshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int16x8_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c
index 0ceee291bab..fef01d926b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32x4_t b)
{
return vqrshlq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u32" } } */
+/*
+**foo1:
+** ...
+** vqrshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32x4_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c
index 7779871c097..6ceafa0f473 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int8x16_t b)
{
return vqrshlq_u8 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u8" } } */
+/*
+**foo1:
+** ...
+** vqrshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int8x16_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c
index 16a4827e50d..76c38e07faa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrnbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshrnbq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrnbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c
index bb054bcf5a1..3af0ad96493 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrnbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshrnbq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrnbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c
index 45119720ed5..f81dd96efde 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrnbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqrshrnbq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrnbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqrshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c
index a3a7a7eac3e..ad52c378a07 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrnbt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqrshrnbq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrnbt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqrshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c
index d1b2ea58dd5..3f82f86029e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrnb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vqrshrnbq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnb.s16" } } */
+/*
+**foo1:
+** ...
+** vqrshrnb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vqrshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnb.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c
index da5db1b8951..02f303052a3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrnb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vqrshrnbq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnb.s32" } } */
+/*
+**foo1:
+** ...
+** vqrshrnb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vqrshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnb.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c
index 360999e3785..cda56ce3c48 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrnb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vqrshrnbq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnb.u16" } } */
+/*
+**foo1:
+** ...
+** vqrshrnb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vqrshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnb.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c
index f276f24a1dd..5202e6249a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrnb.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vqrshrnbq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnb.u32" } } */
+/*
+**foo1:
+** ...
+** vqrshrnb.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vqrshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnb.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c
index fb21072bfa0..39c0eff56f6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshrntq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c
index 77c4cb7e0b0..5fb6983237c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshrntq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c
index 1749f4866a4..91ec5795566 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrntt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqrshrntq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrntt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqrshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c
index e243319e256..986437e49ca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrntt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqrshrntq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrntt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqrshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c
index c7cdc394c35..5dfed5dcbaa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrnt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vqrshrntq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnt.s16" } } */
+/*
+**foo1:
+** ...
+** vqrshrnt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vqrshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c
index 68dfccccc66..7df82962342 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrnt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vqrshrntq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnt.s32" } } */
+/*
+**foo1:
+** ...
+** vqrshrnt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vqrshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c
index bc0572a454b..e76d98ee3f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrnt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vqrshrntq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnt.u16" } } */
+/*
+**foo1:
+** ...
+** vqrshrnt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vqrshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c
index 20bfdbf515a..bc0e39baeae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrnt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vqrshrntq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnt.u32" } } */
+/*
+**foo1:
+** ...
+** vqrshrnt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vqrshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c
index ea12f346b0e..299dd80a887 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrunbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshrunbq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrunbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrunbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshrunbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrunbt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c
index d127e5381bf..5c87efe4be9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrunbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshrunbq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrunbt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrunbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshrunbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrunbt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c
index 88cb39970d4..3bbf72d4def 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrunb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b)
{
return vqrshrunbq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrunb.s16" } } */
+/*
+**foo1:
+** ...
+** vqrshrunb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b)
{
return vqrshrunbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrunb.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c
index 46f96127b1b..4dfd8f60e72 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrunb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b)
{
return vqrshrunbq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrunb.s32" } } */
+/*
+**foo1:
+** ...
+** vqrshrunb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b)
{
return vqrshrunbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrunb.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c
index 5ff25eb2d32..48c17e5e5b6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshruntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshruntq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshruntt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshruntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshruntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshruntt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c
index 4876414e308..46912882ff1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshruntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshruntq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshruntt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshruntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshruntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshruntt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c
index 0f6258b3524..9dc8d3b8f5a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrunt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b)
{
return vqrshruntq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrunt.s16" } } */
+/*
+**foo1:
+** ...
+** vqrshrunt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b)
{
return vqrshruntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrunt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c
index d307f38ec6c..8071367fa2f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrunt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b)
{
return vqrshruntq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrunt.s32" } } */
+/*
+**foo1:
+** ...
+** vqrshrunt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b)
{
return vqrshruntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrunt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c
index a33856f17a5..6eb7443d45e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vqshlq_m_n_s16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vqshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c
index bcfe4fc2874..d10829c90c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vqshlq_m_n_s32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vqshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c
index fba2f0fe859..49886009d74 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vqshlq_m_n_s8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vqshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c
index 1383f6a9ab4..7eb330e6c18 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vqshlq_m_n_u16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vqshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c
index 7cff29f5a28..86ecdc6d563 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vqshlq_m_n_u32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vqshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c
index cbadcbeb77e..f3886e7bae6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vqshlq_m_n_u8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vqshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c
index a3057fec343..e89298c570b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c
index 6973b49a476..35e2552728a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c
index 282d4b45c59..366b45699a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c
index 111d7fa23d9..86774962f0f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c
index 96de168dd23..92a61fe4a2e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c
index 24e388824cc..bace3656143 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c
index ebae8beecb4..2df2ee5c836 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vqshlq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vqshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c
index 80e4d860fb9..e0b2de339f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vqshlq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vqshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c
index e8f88113003..b65df1998fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vqshlq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vqshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c
index 692ff54981d..bced90d13b9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vqshlq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vqshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c
index 1ece80681a7..409ef8524cb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vqshlq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vqshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c
index 7302669fe26..ce9a426ccc9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vqshlq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vqshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c
index b827993198d..859da655409 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a)
{
return vqshlq_n_s16 (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.s16" } } */
+/*
+**foo1:
+** ...
+** vqshl.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a)
{
return vqshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c
index dbc22df551e..1d61e880890 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a)
{
return vqshlq_n_s32 (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.s32" } } */
+/*
+**foo1:
+** ...
+** vqshl.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a)
{
return vqshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c
index e4e1d193c55..737c1bd3764 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a)
{
return vqshlq_n_s8 (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.s8" } } */
+/*
+**foo1:
+** ...
+** vqshl.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a)
{
return vqshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c
index 8227890fc4b..9ddb83e4287 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a)
{
return vqshlq_n_u16 (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.u16" } } */
+/*
+**foo1:
+** ...
+** vqshl.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a)
{
return vqshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c
index b91dc3b91d3..642060f2225 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a)
{
return vqshlq_n_u32 (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.u32" } } */
+/*
+**foo1:
+** ...
+** vqshl.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a)
{
return vqshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c
index ab4903ae407..bd8b9341007 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a)
{
return vqshlq_n_u8 (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.u8" } } */
+/*
+**foo1:
+** ...
+** vqshl.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a)
{
return vqshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c
index 4413d447b71..285f398b35a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32_t b)
{
return vqshlq_r_s16 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s16" } } */
+/*
+**foo1:
+** ...
+** vqshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32_t b)
{
return vqshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c
index 6df14afb48d..af594003c06 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32_t b)
{
return vqshlq_r_s32 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s32" } } */
+/*
+**foo1:
+** ...
+** vqshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32_t b)
{
return vqshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c
index c1b93793c8f..ef39f0c3924 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int32_t b)
{
return vqshlq_r_s8 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s8" } } */
+/*
+**foo1:
+** ...
+** vqshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int32_t b)
{
return vqshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c
index 20fa0263de4..e6cc0007a2b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32_t b)
{
return vqshlq_r_u16 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u16" } } */
+/*
+**foo1:
+** ...
+** vqshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32_t b)
{
return vqshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c
index 7d56784b3d5..b30ecdf4052 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32_t b)
{
return vqshlq_r_u32 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u32" } } */
+/*
+**foo1:
+** ...
+** vqshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32_t b)
{
return vqshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c
index 199249bf604..69b0a8d0b90 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int32_t b)
{
return vqshlq_r_u8 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u8" } } */
+/*
+**foo1:
+** ...
+** vqshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int32_t b)
{
return vqshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c
index 2b01d3e3d31..e7877019200 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vqshlq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s16" } } */
+/*
+**foo1:
+** ...
+** vqshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vqshlq (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c
index b9b66223ae9..a7787cabb62 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vqshlq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s32" } } */
+/*
+**foo1:
+** ...
+** vqshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vqshlq (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c
index 8096205cf28..73af1790b47 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vqshlq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s8" } } */
+/*
+**foo1:
+** ...
+** vqshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vqshlq (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c
index 61b6c18bd8a..26119eff397 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int16x8_t b)
{
return vqshlq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u16" } } */
+/*
+**foo1:
+** ...
+** vqshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int16x8_t b)
{
return vqshlq (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c
index 06b50442d30..01b66d5dfbc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32x4_t b)
{
return vqshlq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u32" } } */
+/*
+**foo1:
+** ...
+** vqshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32x4_t b)
{
return vqshlq (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c
index 0cc6a1dac4b..d4727de5de9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int8x16_t b)
{
return vqshlq_u8 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u8" } } */
+/*
+**foo1:
+** ...
+** vqshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int8x16_t b)
{
return vqshlq (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c
index 885874d13fb..ada03b165c5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlut.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
- return vqshluq_m_n_s16 (inactive, a, 7, p);
+ return vqshluq_m_n_s16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlut.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlut.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
- return vqshluq_m (inactive, a, 7, p);
+ return vqshluq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c
index bb2a3294727..6ae38f1ca84 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlut.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
- return vqshluq_m_n_s32 (inactive, a, 7, p);
+ return vqshluq_m_n_s32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlut.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlut.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
- return vqshluq_m (inactive, a, 7, p);
+ return vqshluq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c
index 7f9a42f8027..8d536a7b0f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlut.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
- return vqshluq_m_n_s8 (inactive, a, 7, p);
+ return vqshluq_m_n_s8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlut.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlut.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
- return vqshluq_m (inactive, a, 7, p);
+ return vqshluq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c
index 481a4465834..33ba80cbf97 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshlu.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (int16x8_t a)
{
- return vqshluq_n_s16 (a, 7);
+ return vqshluq_n_s16 (a, 1);
}
-/* { dg-final { scan-assembler "vqshlu.s16" } } */
+/*
+**foo1:
+** ...
+** vqshlu.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (int16x8_t a)
{
- return vqshluq (a, 7);
+ return vqshluq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vqshlu.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c
index 68298963824..0d5a35f1ed3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshlu.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (int32x4_t a)
{
- return vqshluq_n_s32 (a, 7);
+ return vqshluq_n_s32 (a, 1);
}
-/* { dg-final { scan-assembler "vqshlu.s32" } } */
+/*
+**foo1:
+** ...
+** vqshlu.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (int32x4_t a)
{
- return vqshluq (a, 7);
+ return vqshluq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vqshlu.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c
index 5d52c340667..1e2d9e044b9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshlu.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (int8x16_t a)
{
- return vqshluq_n_s8 (a, 7);
+ return vqshluq_n_s8 (a, 1);
}
-/* { dg-final { scan-assembler "vqshlu.s8" } } */
+/*
+**foo1:
+** ...
+** vqshlu.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (int8x16_t a)
{
- return vqshluq (a, 7);
+ return vqshluq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vqshlu.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c
index 9ea58e95d37..0266640a3ff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrnbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
- return vqshrnbq_m_n_s16 (a, b, 7, p);
+ return vqshrnbq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrnbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
- return vqshrnbq_m (a, b, 7, p);
+ return vqshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c
index b44f41b3699..59be6de392b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrnbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
- return vqshrnbq_m_n_s32 (a, b, 11, p);
+ return vqshrnbq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrnbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
- return vqshrnbq_m (a, b, 11, p);
+ return vqshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c
index f761d14ecec..f227a285ea9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrnbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqshrnbq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrnbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c
index 3073a5b223c..9711c2f9019 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrnbt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqshrnbq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrnbt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c
index 24133b57660..e7e9f974bd4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrnb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vqshrnbq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnb.s16" } } */
+/*
+**foo1:
+** ...
+** vqshrnb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vqshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnb.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c
index 34c11e156c3..b5e2b8af577 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrnb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
- return vqshrnbq_n_s32 (a, b, 2);
+ return vqshrnbq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnb.s32" } } */
+/*
+**foo1:
+** ...
+** vqshrnb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
- return vqshrnbq (a, b, 2);
+ return vqshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vqshrnb.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c
index 23a7596e0ab..708cf3e8d74 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrnb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vqshrnbq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnb.u16" } } */
+/*
+**foo1:
+** ...
+** vqshrnb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vqshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnb.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c
index 4cb7ceaf66b..07fbbaada67 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrnb.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
- return vqshrnbq_n_u32 (a, b, 15);
+ return vqshrnbq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnb.u32" } } */
+/*
+**foo1:
+** ...
+** vqshrnb.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
- return vqshrnbq (a, b, 15);
+ return vqshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vqshrnb.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c
index d2ff2d359e0..c25619df048 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqshrntq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c
index 50dde4047d4..1b1d435e282 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqshrntq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c
index 07949569581..f151a277cd1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrntt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqshrntq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrntt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c
index 17f0205c880..c336001c945 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrntt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqshrntq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrntt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c
index 9e8d5e88619..15b010d2c84 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrnt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vqshrntq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnt.s16" } } */
+/*
+**foo1:
+** ...
+** vqshrnt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vqshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c
index 0661cefa783..974e4a060ce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrnt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vqshrntq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnt.s32" } } */
+/*
+**foo1:
+** ...
+** vqshrnt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vqshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c
index cda26142559..3172a330f6b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrnt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vqshrntq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnt.u16" } } */
+/*
+**foo1:
+** ...
+** vqshrnt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vqshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c
index f242353f6b4..e9e31d63e98 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrnt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vqshrntq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnt.u32" } } */
+/*
+**foo1:
+** ...
+** vqshrnt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vqshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c
index 73c480646e7..b7fe0e51e82 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrunbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqshrunbq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrunbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrunbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqshrunbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrunbt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c
index f8887b1cecb..fb78dd44c5d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrunbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqshrunbq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrunbt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrunbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqshrunbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrunbt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c
index 2c64d7d0873..3c286e77a40 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrunb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b)
{
return vqshrunbq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrunb.s16" } } */
+/*
+**foo1:
+** ...
+** vqshrunb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b)
{
return vqshrunbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrunb.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c
index 17cb0aa5da1..e22fb2b2b36 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrunb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b)
{
return vqshrunbq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrunb.s32" } } */
+/*
+**foo1:
+** ...
+** vqshrunb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b)
{
return vqshrunbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrunb.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c
index 4b9758df7ec..22ca346d98b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshruntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqshruntq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshruntt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshruntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqshruntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshruntt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c
index 18b9f117fb2..2f6adf26e5e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshruntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqshruntq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshruntt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshruntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqshruntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshruntt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c
index f6247751c44..96a377e13b9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrunt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b)
{
return vqshruntq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrunt.s16" } } */
+/*
+**foo1:
+** ...
+** vqshrunt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b)
{
return vqshruntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrunt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c
index 076fd29c69f..2e2eb93a0d6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrunt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b)
{
return vqshruntq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrunt.s32" } } */
+/*
+**foo1:
+** ...
+** vqshrunt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b)
{
return vqshruntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrunt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c
index a64b6649938..f69649b58af 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c
index 350629cf234..a7843d07933 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c
index e5fa4c486bb..f1fb5ad2a05 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c
index 734ac2da8f7..7e7d2c07267 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c
@@ -62,4 +62,4 @@ foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c
index f54aec8dd00..13e54be06c1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c
@@ -62,4 +62,4 @@ foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c
index c96a8398bad..ae6baaba661 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c
@@ -62,4 +62,4 @@ foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c
index bd6a05e858d..fd52022fc26 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c
index baa9e9f192c..4225ec29c06 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c
index 746001d0efa..27496305ee8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c
index ed504fe3817..d840e51d350 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c
@@ -46,4 +46,4 @@ foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c
index 508b54ff41f..242903f9dc8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c
@@ -46,4 +46,4 @@ foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c
index 5cfb2c58940..e5a6b7aa0e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c
@@ -46,4 +46,4 @@ foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c
index a4407cc802f..7a286add743 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t a, int16_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c
index 80634f0a797..2532b216a34 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t a, int32_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c
index 172609a94e7..9e0a233baa0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t a, int8_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c
index 0a95d0ab3ce..20d3267e583 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c
@@ -50,4 +50,4 @@ foo2 (uint16x8_t a)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c
index 9964ea66ee8..4805e4cd969 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c
@@ -50,4 +50,4 @@ foo2 (uint32x4_t a)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c
index b28a93ffd00..db475615bbc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c
@@ -50,4 +50,4 @@ foo2 (uint8x16_t a)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c
index 1c5edd730ad..76def1b340d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t a, int16x8_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c
index a7b6c07fb4b..989ad501659 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t a, int32x4_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c
index 92676fdca4f..4cf804b4c99 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t a, int8x16_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c
index 0b816c6b765..4d937a35269 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c
@@ -38,4 +38,4 @@ foo1 (uint16x8_t a, uint16x8_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c
index 565508db865..5ee2c2d9cc2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c
@@ -38,4 +38,4 @@ foo1 (uint32x4_t a, uint32x4_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c
index cca60ff7247..14cfb55644c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c
@@ -38,4 +38,4 @@ foo1 (uint8x16_t a, uint8x16_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c
index 7b06f0b3644..b366057dfde 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vrev16q_m_s8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev16t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vrev16q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c
index 8cf374d97c1..7baad3ba72f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vrev16q_m_u8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev16t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vrev16q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c
index 52688402437..23fcd61a464 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev16.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a)
{
return vrev16q_s8 (a);
}
-/* { dg-final { scan-assembler "vrev16.8" } } */
+/*
+**foo1:
+** ...
+** vrev16.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a)
{
return vrev16q (a);
}
-/* { dg-final { scan-assembler "vrev16.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c
index 56c05c523f3..e08b4b6cda2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev16.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a)
{
- return vrev16q_u8 (a);
+ return vrev16q_u8 (a);
}
-/* { dg-final { scan-assembler "vrev16.8" } } */
+/*
+**foo1:
+** ...
+** vrev16.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a)
{
- return vrev16q (a);
+ return vrev16q (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrev16.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c
index 700a6774e2e..6496bf89931 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, mve_pred16_t p)
{
return vrev16q_x_s8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev16t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, mve_pred16_t p)
{
return vrev16q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c
index 3b424061f0e..e03f6f177ff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, mve_pred16_t p)
{
return vrev16q_x_u8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev16t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, mve_pred16_t p)
{
return vrev16q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c
index 946fd8ddf5b..6e4c5691760 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a)
{
return vrev32q_f16 (a);
}
-/* { dg-final { scan-assembler "vrev32.16" } } */
+
+/*
+**foo1:
+** ...
+** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+ return vrev32q (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c
index 623b48a92c4..3b25f0314c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrev32q_m_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrev32q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c
index 4040707d02c..36f671924b3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vrev32q_m_s16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vrev32q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c
index ad15e9d2bca..13960569138 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vrev32q_m_s8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vrev32q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c
index 8cd61e6bb1f..7683397030b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vrev32q_m_u16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vrev32q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c
index 44600e2d1e7..72fc03bff2d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vrev32q_m_u8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vrev32q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c
index 503616e2a29..cd02518fd9d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a)
{
return vrev32q_s16 (a);
}
-/* { dg-final { scan-assembler "vrev32.16" } } */
+/*
+**foo1:
+** ...
+** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a)
{
return vrev32q (a);
}
-/* { dg-final { scan-assembler "vrev32.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c
index aa98f965713..3a156b7014f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev32.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a)
{
return vrev32q_s8 (a);
}
-/* { dg-final { scan-assembler "vrev32.8" } } */
+/*
+**foo1:
+** ...
+** vrev32.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a)
{
return vrev32q (a);
}
-/* { dg-final { scan-assembler "vrev32.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c
index 6a441ed0edb..299f015bb04 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a)
{
- return vrev32q_u16 (a);
+ return vrev32q_u16 (a);
}
-/* { dg-final { scan-assembler "vrev32.16" } } */
+/*
+**foo1:
+** ...
+** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a)
{
- return vrev32q (a);
+ return vrev32q (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrev32.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c
index 787f236411d..fb65d0a3821 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev32.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a)
{
- return vrev32q_u8 (a);
+ return vrev32q_u8 (a);
}
-/* { dg-final { scan-assembler "vrev32.8" } } */
+/*
+**foo1:
+** ...
+** vrev32.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a)
{
- return vrev32q (a);
+ return vrev32q (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrev32.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c
index f7dc8fb14ec..d1c22aa72f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vrev32q_x_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, mve_pred16_t p)
{
return vrev32q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c
index 81ec83dec4b..0f0c19b1483 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
return vrev32q_x_s16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, mve_pred16_t p)
{
return vrev32q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c
index 8d3bac1e82c..2457dde2a58 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, mve_pred16_t p)
{
return vrev32q_x_s8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, mve_pred16_t p)
{
return vrev32q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c
index 36ba71752a8..b1b1237344e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vrev32q_x_u16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vrev32q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c
index 9d15c9df43c..21d39274577 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, mve_pred16_t p)
{
return vrev32q_x_u8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, mve_pred16_t p)
{
return vrev32q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c
index 7ec0962a95e..a2dc8957467 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a)
{
return vrev64q_f16 (a);
}
-/* { dg-final { scan-assembler "vrev64.16" } } */
+
+/*
+**foo1:
+** ...
+** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+ return vrev64q (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c
index 01c342496da..78add56a4da 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a)
{
return vrev64q_f32 (a);
}
-/* { dg-final { scan-assembler "vrev64.32" } } */
+
+/*
+**foo1:
+** ...
+** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+ return vrev64q (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c
index ef47bab0314..0fb44077ec4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrev64q_m_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrev64q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c
index 6df0ba62eff..ff62ea7d021 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrev64q_m_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrev64q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c
index 9f9bbe0e666..b30ce76c68f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vrev64q_m_s16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vrev64q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c
index 132628b5a80..b44d363a712 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vrev64q_m_s32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vrev64q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c
index eb6e560ac3c..4804b8acaf3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vrev64q_m_s8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vrev64q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c
index 4534a64ee84..12c26144cd2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vrev64q_m_u16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vrev64q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c
index 3f1ab24527c..ff90d92fff3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vrev64q_m_u32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vrev64q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c
index 4adb70963dd..267c3b6bee2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vrev64q_m_u8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vrev64q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c
index a886b0b0c6a..b6083f9d69c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a)
{
return vrev64q_s16 (a);
}
-/* { dg-final { scan-assembler "vrev64.16" } } */
+/*
+**foo1:
+** ...
+** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a)
{
return vrev64q (a);
}
-/* { dg-final { scan-assembler "vrev64.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c
index b0ba64b186b..81fc7d1bdd0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a)
{
return vrev64q_s32 (a);
}
-/* { dg-final { scan-assembler "vrev64.32" } } */
+/*
+**foo1:
+** ...
+** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a)
{
return vrev64q (a);
}
-/* { dg-final { scan-assembler "vrev64.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c
index 12f9f1ac389..3fced739681 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev64.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a)
{
return vrev64q_s8 (a);
}
-/* { dg-final { scan-assembler "vrev64.8" } } */
+/*
+**foo1:
+** ...
+** vrev64.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a)
{
return vrev64q (a);
}
-/* { dg-final { scan-assembler "vrev64.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c
index ee3813428c9..b25fccc6c2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a)
{
- return vrev64q_u16 (a);
+ return vrev64q_u16 (a);
}
-/* { dg-final { scan-assembler "vrev64.16" } } */
+/*
+**foo1:
+** ...
+** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a)
{
- return vrev64q (a);
+ return vrev64q (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrev64.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c
index c4a551dcc15..9d203b1f6bf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a)
{
- return vrev64q_u32 (a);
+ return vrev64q_u32 (a);
}
-/* { dg-final { scan-assembler "vrev64.32" } } */
+/*
+**foo1:
+** ...
+** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a)
{
- return vrev64q (a);
+ return vrev64q (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrev64.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c
index 578d538f019..9acd52439e5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev64.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a)
{
- return vrev64q_u8 (a);
+ return vrev64q_u8 (a);
}
-/* { dg-final { scan-assembler "vrev64.8" } } */
+/*
+**foo1:
+** ...
+** vrev64.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a)
{
- return vrev64q (a);
+ return vrev64q (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrev64.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c
index 467da7fe9ef..9c949028d8b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vrev64q_x_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, mve_pred16_t p)
{
return vrev64q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c
index 1a3cd17ebd6..445834a55f8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vrev64q_x_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, mve_pred16_t p)
{
return vrev64q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c
index b9932eddf38..66daa3d9131 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
return vrev64q_x_s16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, mve_pred16_t p)
{
return vrev64q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c
index 4eb3d4d09b1..2c5a5ee1a0c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
return vrev64q_x_s32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, mve_pred16_t p)
{
return vrev64q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c
index 5c22c387586..a24f17d5797 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, mve_pred16_t p)
{
return vrev64q_x_s8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, mve_pred16_t p)
{
return vrev64q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c
index bbf42931d92..4c11e79254b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vrev64q_x_u16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vrev64q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c
index 1b595c3ad2f..14f676e0cff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, mve_pred16_t p)
{
return vrev64q_x_u32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, mve_pred16_t p)
{
return vrev64q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c
index abff81e40b9..542dcaa782c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, mve_pred16_t p)
{
return vrev64q_x_u8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, mve_pred16_t p)
{
return vrev64q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c
index 01d72efc34b..0deef794352 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vrhaddq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vrhaddq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c
index dfe8d7334a8..e584987fb3e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrhaddq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrhaddq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c
index 9eceda2b115..40e3472bbf0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vrhaddq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vrhaddq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c
index ec11b660a4e..bd53871cc58 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vrhaddq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vrhaddq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c
index 25c6208ec06..30037083a01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrhaddq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrhaddq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c
index 7b25bf8faa8..3208ac1589b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vrhaddq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vrhaddq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c
index 36f36f77233..bafb1dc5795 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrhadd.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vrhaddq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.s16" } } */
+/*
+**foo1:
+** ...
+** vrhadd.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vrhaddq (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c
index 813cf91649e..bbee81fffd6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrhadd.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vrhaddq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.s32" } } */
+/*
+**foo1:
+** ...
+** vrhadd.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vrhaddq (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c
index 5ce1109d676..3fad58d4e0d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrhadd.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vrhaddq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.s8" } } */
+/*
+**foo1:
+** ...
+** vrhadd.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vrhaddq (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c
index 9d9bf18ec70..91273571ec8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrhadd.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b)
{
return vrhaddq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.u16" } } */
+/*
+**foo1:
+** ...
+** vrhadd.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b)
{
return vrhaddq (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c
index e465197505b..79a21051b0b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrhadd.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b)
{
return vrhaddq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.u32" } } */
+/*
+**foo1:
+** ...
+** vrhadd.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b)
{
return vrhaddq (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c
index cbede385f20..4bdd23419a3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrhadd.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b)
{
return vrhaddq_u8 (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.u8" } } */
+/*
+**foo1:
+** ...
+** vrhadd.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b)
{
return vrhaddq (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c
index 8507b436dc8..363dedd3304 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vrhaddq_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vrhaddq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c
index 756c52f8f1e..f1df6749f33 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrhaddq_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrhaddq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c
index 9b580782098..107cf2daa58 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vrhaddq_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vrhaddq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c
index ec534c8262e..5837437d33c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vrhaddq_x_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vrhaddq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c
index c79f406439e..0d8d118987e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrhaddq_x_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrhaddq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c
index c4c16f8a753..37711710ee8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vrhaddq_x_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vrhaddq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
index 2134e3fc0dd..c18ff82f8f5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
@@ -46,4 +46,4 @@ foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
index 4ebd337e8ee..ba0a9587e3f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
@@ -62,4 +62,4 @@ foo2 (uint32x4_t b, uint32x4_t c, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c
index 2efde824eb3..b2ced4b41c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c
@@ -38,4 +38,4 @@ foo1 (int64_t a, int32x4_t b, int32x4_t c)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c
index 745655f31d0..96f1ab72e92 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c
@@ -50,4 +50,4 @@ foo2 (uint32x4_t b, uint32x4_t c)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c
index 0e29e886ce1..a0164ed2bb7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlaldavhaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vrmlaldavhaxq_p_s32 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vrmlaldavhaxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlaldavhaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vrmlaldavhaxq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vrmlaldavhaxt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c
index 063c94d8c5b..4e71fd72e35 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmlaldavhax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c)
{
return vrmlaldavhaxq_s32 (a, b, c);
}
-/* { dg-final { scan-assembler "vrmlaldavhax.s32" } } */
+/*
+**foo1:
+** ...
+** vrmlaldavhax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c)
{
return vrmlaldavhaxq (a, b, c);
}
-/* { dg-final { scan-assembler "vrmlaldavhax.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c
index 1d7a5e3d690..b8f346f9740 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlaldavht.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmlaldavhq_p_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlaldavht.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlaldavht.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmlaldavhq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlaldavht.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c
index 539b04254cd..d6c6d503a9b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlaldavht.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrmlaldavhq_p_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlaldavht.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlaldavht.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrmlaldavhq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlaldavht.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c
index 566b85d1721..22c1164b6a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmlaldavh.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b)
{
return vrmlaldavhq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vrmlaldavh.s32" } } */
+/*
+**foo1:
+** ...
+** vrmlaldavh.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b)
{
return vrmlaldavhq (a, b);
}
-/* { dg-final { scan-assembler "vrmlaldavh.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c
index 352cd58c8e8..6517ee8cd60 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmlaldavh.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
foo (uint32x4_t a, uint32x4_t b)
{
return vrmlaldavhq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vrmlaldavh.u32" } } */
+/*
+**foo1:
+** ...
+** vrmlaldavh.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
foo1 (uint32x4_t a, uint32x4_t b)
{
return vrmlaldavhq (a, b);
}
-/* { dg-final { scan-assembler "vrmlaldavh.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c
index d99ebffbea0..ebe1012f53f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlaldavhxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmlaldavhxq_p_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlaldavhxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlaldavhxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmlaldavhxq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlaldavhxt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c
index 64f02971eb3..56a2071d61c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmlaldavhx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b)
{
return vrmlaldavhxq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vrmlaldavhx.s32" } } */
+/*
+**foo1:
+** ...
+** vrmlaldavhx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b)
{
return vrmlaldavhxq (a, b);
}
-/* { dg-final { scan-assembler "vrmlaldavhx.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c
index 83d5a8ce251..aad2f009ba3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlsldavhat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vrmlsldavhaq_p_s32 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vrmlsldavhat.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlsldavhat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vrmlsldavhaq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vrmlsldavhat.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c
index a8a320c6a43..f30870181b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmlsldavha.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c)
{
return vrmlsldavhaq_s32 (a, b, c);
}
-/* { dg-final { scan-assembler "vrmlsldavha.s32" } } */
+/*
+**foo1:
+** ...
+** vrmlsldavha.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c)
{
return vrmlsldavhaq (a, b, c);
}
-/* { dg-final { scan-assembler "vrmlsldavha.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c
index aa20ba1a7eb..2a3f441e429 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlsldavhaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vrmlsldavhaxq_p_s32 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vrmlsldavhaxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlsldavhaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vrmlsldavhaxq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vrmlsldavhaxt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c
index 78932840dfe..06afa309bfa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmlsldavhax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c)
{
return vrmlsldavhaxq_s32 (a, b, c);
}
-/* { dg-final { scan-assembler "vrmlsldavhax.s32" } } */
+/*
+**foo1:
+** ...
+** vrmlsldavhax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c)
{
return vrmlsldavhaxq (a, b, c);
}
-/* { dg-final { scan-assembler "vrmlsldavhax.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c
index 1e2127a17be..9f1f82a7c62 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlsldavht.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmlsldavhq_p_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlsldavht.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlsldavht.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmlsldavhq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlsldavht.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c
index 2a7844fa370..ff867d5c208 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmlsldavh.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b)
{
return vrmlsldavhq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vrmlsldavh.s32" } } */
+/*
+**foo1:
+** ...
+** vrmlsldavh.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b)
{
return vrmlsldavhq (a, b);
}
-/* { dg-final { scan-assembler "vrmlsldavh.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c
index ecbc9737d8f..2a127c76df8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlsldavhxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmlsldavhxq_p_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlsldavhxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlsldavhxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmlsldavhxq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlsldavhxt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c
index 0cea55724aa..41539059d7f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmlsldavhx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b)
{
return vrmlsldavhxq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vrmlsldavhx.s32" } } */
+/*
+**foo1:
+** ...
+** vrmlsldavhx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b)
{
return vrmlsldavhxq (a, b);
}
-/* { dg-final { scan-assembler "vrmlsldavhx.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c
index 6adaf3f6431..e5c70a0a323 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vrmulhq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vrmulhq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c
index a90a67971c8..6b373e1739a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmulhq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmulhq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c
index d0dd99aa4c3..961ba71ccb7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vrmulhq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vrmulhq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c
index 50d05c1de11..3a782c295e1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vrmulhq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vrmulhq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c
index a7da7330266..818fb631ff7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrmulhq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrmulhq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c
index 42b0b9f0f2f..3d1eb365c63 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vrmulhq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vrmulhq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c
index ac77b9f13ba..34c3f182628 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmulh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vrmulhq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.s16" } } */
+/*
+**foo1:
+** ...
+** vrmulh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vrmulhq (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c
index a7bbd19c393..fe4d11c5acd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmulh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vrmulhq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.s32" } } */
+/*
+**foo1:
+** ...
+** vrmulh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vrmulhq (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c
index b0d1a856794..4b5a2e656ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmulh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vrmulhq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.s8" } } */
+/*
+**foo1:
+** ...
+** vrmulh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vrmulhq (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c
index b43cb07b1bf..478d5885edd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmulh.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b)
{
return vrmulhq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.u16" } } */
+/*
+**foo1:
+** ...
+** vrmulh.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b)
{
return vrmulhq (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c
index f37eeb606f2..e3dc75d10aa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmulh.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b)
{
return vrmulhq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.u32" } } */
+/*
+**foo1:
+** ...
+** vrmulh.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b)
{
return vrmulhq (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c
index ab5d7597a43..108357b6d35 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmulh.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b)
{
return vrmulhq_u8 (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.u8" } } */
+/*
+**foo1:
+** ...
+** vrmulh.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b)
{
return vrmulhq (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c
index 3ef89bd686b..00f728bdaf2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vrmulhq_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vrmulhq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c
index 2a4b9d0d147..49a739d9a95 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmulhq_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmulhq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c
index d3ef8713dba..7d97cbc5f8e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vrmulhq_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vrmulhq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c
index 5ce4d01a235..31622dce8df 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vrmulhq_x_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vrmulhq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c
index 4a965976c2d..f6d2582bac8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrmulhq_x_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrmulhq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c
index 015530c08b2..15e947618f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vrmulhq_x_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vrmulhq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c
index ba8426fdff3..17b11972e84 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrinta.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a)
{
return vrndaq_f16 (a);
}
-/* { dg-final { scan-assembler "vrinta.f16" } } */
+
+/*
+**foo1:
+** ...
+** vrinta.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+ return vrndaq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c
index a8c9c28422f..dc3689a66d1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrinta.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a)
{
return vrndaq_f32 (a);
}
-/* { dg-final { scan-assembler "vrinta.f32" } } */
+
+/*
+**foo1:
+** ...
+** vrinta.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+ return vrndaq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c
index 3617d796351..ffbdf3dad94 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintat.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndaq_m_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintat.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintat.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndaq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c
index fdb9ddb3551..d20f8050c45 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintat.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndaq_m_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintat.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintat.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndaq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c
index f398e86b689..141f612ddcb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintat.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vrndaq_x_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintat.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintat.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, mve_pred16_t p)
{
return vrndaq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c
index f5f21808528..277d2a7b668 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintat.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vrndaq_x_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintat.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintat.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, mve_pred16_t p)
{
return vrndaq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c
index 911a2b1cb29..a51878645da 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintm.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a)
{
return vrndmq_f16 (a);
}
-/* { dg-final { scan-assembler "vrintm.f16" } } */
+
+/*
+**foo1:
+** ...
+** vrintm.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+ return vrndmq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c
index 496a2e55d55..4b79490cc21 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintm.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a)
{
return vrndmq_f32 (a);
}
-/* { dg-final { scan-assembler "vrintm.f32" } } */
+
+/*
+**foo1:
+** ...
+** vrintm.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+ return vrndmq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c
index 86f58e2eb88..e6eb2a1015d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintmt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndmq_m_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintmt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintmt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndmq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c
index 247595df56a..99f3f206823 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintmt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndmq_m_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintmt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintmt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndmq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c
index accc79579ec..cdef684f381 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintmt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vrndmq_x_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintmt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintmt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, mve_pred16_t p)
{
return vrndmq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c
index 0e4200dc2f5..94da7738d16 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintmt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vrndmq_x_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintmt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintmt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, mve_pred16_t p)
{
return vrndmq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c
index 23299c2a06f..b1b31bebb11 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintn.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a)
{
return vrndnq_f16 (a);
}
-/* { dg-final { scan-assembler "vrintn.f16" } } */
+
+/*
+**foo1:
+** ...
+** vrintn.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+ return vrndnq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c
index ce445f2249f..e2fec8a87e2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintn.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a)
{
return vrndnq_f32 (a);
}
-/* { dg-final { scan-assembler "vrintn.f32" } } */
+
+/*
+**foo1:
+** ...
+** vrintn.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+ return vrndnq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c
index c41e38070bf..04d828bde24 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintnt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndnq_m_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintnt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintnt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c
index 09b9b95d67d..b32eacd9b20 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintnt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndnq_m_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintnt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintnt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c
index beeb23cf364..093aaa04d57 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintnt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vrndnq_x_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintnt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintnt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, mve_pred16_t p)
{
return vrndnq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c
index d09e55d53b3..8428800d503 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintnt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vrndnq_x_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintnt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintnt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, mve_pred16_t p)
{
return vrndnq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c
index 25dcbd5f3bf..3145faf9f70 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintp.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a)
{
return vrndpq_f16 (a);
}
-/* { dg-final { scan-assembler "vrintp.f16" } } */
+
+/*
+**foo1:
+** ...
+** vrintp.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+ return vrndpq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c
index 5ab6f7ae9c3..2754af48612 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintp.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a)
{
return vrndpq_f32 (a);
}
-/* { dg-final { scan-assembler "vrintp.f32" } } */
+
+/*
+**foo1:
+** ...
+** vrintp.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+ return vrndpq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c
index 2cf8220c789..e62883c1edb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintpt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndpq_m_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintpt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintpt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndpq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c
index 7ed26e8d926..b8370b85373 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintpt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndpq_m_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintpt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintpt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndpq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c
index 233a6e843e8..57465385173 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintpt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vrndpq_x_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintpt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintpt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, mve_pred16_t p)
{
return vrndpq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c
index f689ce6510b..86a94c0dfe5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintpt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vrndpq_x_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintpt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintpt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, mve_pred16_t p)
{
return vrndpq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c
index 6fe3b2eae48..4b2ee2c3da2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintz.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a)
{
return vrndq_f16 (a);
}
-/* { dg-final { scan-assembler "vrintz.f16" } } */
+
+/*
+**foo1:
+** ...
+** vrintz.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+ return vrndq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c
index a27b5c99b3a..301e9e4c25e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintz.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a)
{
return vrndq_f32 (a);
}
-/* { dg-final { scan-assembler "vrintz.f32" } } */
+
+/*
+**foo1:
+** ...
+** vrintz.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+ return vrndq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c
index 3a9edafc772..d7ba6d4f11f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintzt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndq_m_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintzt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintzt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c
index 0ae4b92d235..6bfe1d49941 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintzt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndq_m_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintzt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintzt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c
index eb6c3c37876..13ba05011e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintzt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vrndq_x_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintzt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintzt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, mve_pred16_t p)
{
return vrndq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c
index 8b4c8c1e289..162d199420d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintzt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vrndq_x_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintzt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintzt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, mve_pred16_t p)
{
return vrndq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c
index e6f2028de30..9df65c5473d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintx.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a)
{
return vrndxq_f16 (a);
}
-/* { dg-final { scan-assembler "vrintx.f16" } } */
+
+/*
+**foo1:
+** ...
+** vrintx.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+ return vrndxq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c
index 32e6c90e60e..92bc6df1361 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintx.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a)
{
return vrndxq_f32 (a);
}
-/* { dg-final { scan-assembler "vrintx.f32" } } */
+
+/*
+**foo1:
+** ...
+** vrintx.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+ return vrndxq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c
index 0e6a6119f08..9d92566b08d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintxt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndxq_m_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintxt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintxt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndxq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c
index 3b09769814b..7a216050fb1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintxt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndxq_m_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintxt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintxt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndxq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c
index c160800023f..537506cd5be 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintxt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vrndxq_x_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintxt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintxt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, mve_pred16_t p)
{
return vrndxq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c
index 48b76161032..e19ba0c0a3c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintxt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vrndxq_x_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintxt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintxt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, mve_pred16_t p)
{
return vrndxq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c
index 9e7f22ccad9..e30cfe16fdf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vrshrnbq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vrshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c
index 6b6a98c3da4..acb89bd462a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vrshrnbq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vrshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c
index e54893d2abc..4d0c6048971 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vrshrnbq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vrshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c
index ecb41a2c444..1b768a13061 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vrshrnbq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vrshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c
index f09db27adee..6350e3c4cca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vrshrnbq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnb.i16" } } */
+/*
+**foo1:
+** ...
+** vrshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vrshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnb.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c
index 2bc4170b07f..8ae96d8a2b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vrshrnbq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnb.i32" } } */
+/*
+**foo1:
+** ...
+** vrshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vrshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnb.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c
index 990871f5b9e..2918cb05e43 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vrshrnbq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnb.i16" } } */
+/*
+**foo1:
+** ...
+** vrshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vrshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnb.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c
index 875fed28fe7..c615d8083d7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vrshrnbq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnb.i32" } } */
+/*
+**foo1:
+** ...
+** vrshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vrshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnb.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c
index 72206c36fda..639f25ed719 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vrshrntq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vrshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c
index e964af2e8b5..07a53e364f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vrshrntq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vrshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c
index ad98b7677f0..f00d62bcb7a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vrshrntq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vrshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c
index adee8b28b88..bb809acfe6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vrshrntq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vrshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c
index 4c2f133b605..926a897d50e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vrshrntq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnt.i16" } } */
+/*
+**foo1:
+** ...
+** vrshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vrshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnt.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c
index 26508ba7961..7e931355751 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vrshrntq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnt.i32" } } */
+/*
+**foo1:
+** ...
+** vrshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vrshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnt.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c
index eea3d4974db..61636d301f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vrshrntq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnt.i16" } } */
+/*
+**foo1:
+** ...
+** vrshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vrshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnt.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c
index 49afdf0c61e..b82dad525f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vrshrntq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnt.i32" } } */
+/*
+**foo1:
+** ...
+** vrshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vrshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnt.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c
index ee48f8c2733..b1a2f813320 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
- return vrshrq_m_n_s16 (inactive, a, 16, p);
+ return vrshrq_m_n_s16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
- return vrshrq_m (inactive, a, 16, p);
+ return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c
index 4330dcfaaa6..fb229273b86 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
- return vrshrq_m_n_s32 (inactive, a, 32, p);
+ return vrshrq_m_n_s32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
- return vrshrq_m (inactive, a, 32, p);
+ return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c
index 4b35c597a13..b9136b8dd69 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
- return vrshrq_m_n_s8 (inactive, a, 8, p);
+ return vrshrq_m_n_s8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
- return vrshrq_m (inactive, a, 8, p);
+ return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c
index 2e83c60ad95..9dbc3fed62a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
- return vrshrq_m_n_u16 (inactive, a, 16, p);
+ return vrshrq_m_n_u16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
- return vrshrq_m (inactive, a, 16, p);
+ return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c
index 5d2a9d8f4f4..0e0cb10b476 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
- return vrshrq_m_n_u32 (inactive, a, 32, p);
+ return vrshrq_m_n_u32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
- return vrshrq_m (inactive, a, 32, p);
+ return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c
index f5b43708689..010a7915c56 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
- return vrshrq_m_n_u8 (inactive, a, 8, p);
+ return vrshrq_m_n_u8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
- return vrshrq_m (inactive, a, 8, p);
+ return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c
index 2cd934774ce..ff3d552bd78 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshr.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a)
{
- return vrshrq_n_s16 (a, 16);
+ return vrshrq_n_s16 (a, 1);
}
-/* { dg-final { scan-assembler "vrshr.s16" } } */
+/*
+**foo1:
+** ...
+** vrshr.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a)
{
- return vrshrq (a, 16);
+ return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrshr.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c
index 3cc21f2b277..db161f7d009 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshr.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a)
{
- return vrshrq_n_s32 (a, 32);
+ return vrshrq_n_s32 (a, 1);
}
-/* { dg-final { scan-assembler "vrshr.s32" } } */
+/*
+**foo1:
+** ...
+** vrshr.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a)
{
- return vrshrq (a, 32);
+ return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrshr.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c
index 251d5324f5c..86a0294f8a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshr.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a)
{
- return vrshrq_n_s8 (a, 8);
+ return vrshrq_n_s8 (a, 1);
}
-/* { dg-final { scan-assembler "vrshr.s8" } } */
+/*
+**foo1:
+** ...
+** vrshr.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a)
{
- return vrshrq (a, 8);
+ return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrshr.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c
index 6934597f844..897247fce6c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshr.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a)
{
- return vrshrq_n_u16 (a, 16);
+ return vrshrq_n_u16 (a, 1);
}
-/* { dg-final { scan-assembler "vrshr.u16" } } */
+/*
+**foo1:
+** ...
+** vrshr.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a)
{
- return vrshrq (a, 16);
+ return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrshr.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c
index 52b287b8f3b..e8f7f1c33e0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshr.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a)
{
- return vrshrq_n_u32 (a, 32);
+ return vrshrq_n_u32 (a, 1);
}
-/* { dg-final { scan-assembler "vrshr.u32" } } */
+/*
+**foo1:
+** ...
+** vrshr.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a)
{
- return vrshrq (a, 32);
+ return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrshr.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c
index ac595a9ac95..a22521b14ae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshr.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a)
{
- return vrshrq_n_u8 (a, 8);
+ return vrshrq_n_u8 (a, 1);
}
-/* { dg-final { scan-assembler "vrshr.u8" } } */
+/*
+**foo1:
+** ...
+** vrshr.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a)
{
- return vrshrq (a, 8);
+ return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrshr.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c
index 14b5c1884f4..37f364cfc39 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
- return vrshrq_x_n_s16 (a, 16, p);
+ return vrshrq_x_n_s16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, mve_pred16_t p)
{
- return vrshrq_x (a, 16, p);
+ return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c
index 846ddb96782..0da2fd75056 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
- return vrshrq_x_n_s32 (a, 32, p);
+ return vrshrq_x_n_s32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, mve_pred16_t p)
{
- return vrshrq_x (a, 32, p);
+ return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c
index 06f75e56db6..90c814b20c5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, mve_pred16_t p)
{
- return vrshrq_x_n_s8 (a, 8, p);
+ return vrshrq_x_n_s8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, mve_pred16_t p)
{
- return vrshrq_x (a, 8, p);
+ return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c
index bc946497cfc..135b9e7e90f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
- return vrshrq_x_n_u16 (a, 16, p);
+ return vrshrq_x_n_u16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
- return vrshrq_x (a, 16, p);
+ return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c
index 55002cd196d..dd656f49aa7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, mve_pred16_t p)
{
- return vrshrq_x_n_u32 (a, 32, p);
+ return vrshrq_x_n_u32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, mve_pred16_t p)
{
- return vrshrq_x (a, 32, p);
+ return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c
index e3130657711..e41abc450a0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, mve_pred16_t p)
{
- return vrshrq_x_n_u8 (a, 8, p);
+ return vrshrq_x_n_u8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, mve_pred16_t p)
{
- return vrshrq_x (a, 8, p);
+ return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
index 21f4219faa3..66a5c4c9da3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
@@ -1,23 +1,61 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsbcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p)
{
return vsbciq_m_s32 (inactive, a, b, carry_out, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbcit.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsbcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p)
{
return vsbciq_m (inactive, a, b, carry_out, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbcit.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
index ef9eed92d33..9306f152cde 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
@@ -1,23 +1,61 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsbcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p)
{
return vsbciq_m_u32 (inactive, a, b, carry_out, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbcit.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsbcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p)
{
return vsbciq_m (inactive, a, b, carry_out, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbcit.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
index 2181a3a2879..0b5040f0b2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsbci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t a, int32x4_t b, unsigned * carry_out)
+foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
{
return vsbciq_s32 (a, b, carry_out);
}
-/* { dg-final { scan-assembler "vsbci.i32" } } */
+/*
+**foo1:
+** ...
+** vsbci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t a, int32x4_t b, unsigned * carry_out)
+foo1 (int32x4_t a, int32x4_t b, unsigned *carry_out)
{
- return vsbciq_s32 (a, b, carry_out);
+ return vsbciq (a, b, carry_out);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsbci.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
index df0487f3b88..df211a64daa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsbci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, unsigned * carry_out)
+foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
{
return vsbciq_u32 (a, b, carry_out);
}
-/* { dg-final { scan-assembler "vsbci.i32" } } */
+/*
+**foo1:
+** ...
+** vsbci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry_out)
+foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
{
- return vsbciq_u32 (a, b, carry_out);
+ return vsbciq (a, b, carry_out);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsbci.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
index 73be46a8459..217cfa7ac21 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
@@ -1,23 +1,73 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p)
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p)
{
- return vsbcq_m_s32 (inactive, a, b, carry, p);
+ return vsbcq_m_s32 (inactive, a, b, carry, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbct.i32" } } */
+/*
+**foo1:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo1(int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p)
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p)
{
- return vsbcq_m (inactive, a, b, carry, p);
+ return vsbcq_m (inactive, a, b, carry, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbct.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
index 80cf70584e5..dad04d05d68 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
@@ -1,22 +1,73 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p)
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p)
{
- return vsbcq_m_u32 (inactive, a, b, carry, p);
+ return vsbcq_m_u32 (inactive, a, b, carry, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbct.i32" } } */
+
+/*
+**foo1:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p)
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p)
{
- return vsbcq_m (inactive, a, b, carry, p);
+ return vsbcq_m (inactive, a, b, carry, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbct.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
index 23e42575bd7..cd033640bcc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
@@ -1,21 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vsbc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t a, int32x4_t b, unsigned * carry)
+foo (int32x4_t a, int32x4_t b, unsigned *carry)
{
return vsbcq_s32 (a, b, carry);
}
-/* { dg-final { scan-assembler "vsbc.i32" } } */
+/*
+**foo1:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vsbc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t a, int32x4_t b, unsigned * carry)
+foo1 (int32x4_t a, int32x4_t b, unsigned *carry)
{
return vsbcq (a, b, carry);
}
-/* { dg-final { scan-assembler "vsbc.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
index d3aa66f6134..6ca0c753b5e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
@@ -1,21 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vsbc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, unsigned * carry)
+foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
{
return vsbcq_u32 (a, b, carry);
}
-/* { dg-final { scan-assembler "vsbc.i32" } } */
+/*
+**foo1:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vsbc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry)
+foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry)
{
return vsbcq (a, b, carry);
}
-/* { dg-final { scan-assembler "vsbc.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c
index c4c77f2559c..c603a89117f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
-foo (int16x8_t a, uint32_t * b, mve_pred16_t p)
+foo (int16x8_t a, uint32_t *b, mve_pred16_t p)
{
- return vshlcq_m_s16 (a, b, 32, p);
+ return vshlcq_m_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
-foo1 (int16x8_t a, uint32_t * b, mve_pred16_t p)
+foo1 (int16x8_t a, uint32_t *b, mve_pred16_t p)
{
- return vshlcq_m (a, b, 32, p);
+ return vshlcq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c
index 20cfd09c82d..46e75033ae6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t a, uint32_t * b, mve_pred16_t p)
+foo (int32x4_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t a, uint32_t * b, mve_pred16_t p)
+foo1 (int32x4_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c
index 33dde10e4a8..868de5df80b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
-foo (int8x16_t a, uint32_t * b, mve_pred16_t p)
+foo (int8x16_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m_s8 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
-foo1 (int8x16_t a, uint32_t * b, mve_pred16_t p)
+foo1 (int8x16_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c
index 2bf69f0c465..a1e1c3f9bc4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint16x8_t a, uint32_t * b, mve_pred16_t p)
+foo (uint16x8_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
-foo1 (uint16x8_t a, uint32_t * b, mve_pred16_t p)
+foo1 (uint16x8_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c
index e6650302ea7..bcb0bebd969 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t a, uint32_t * b, mve_pred16_t p)
+foo (uint32x4_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t a, uint32_t * b, mve_pred16_t p)
+foo1 (uint32x4_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c
index 95857f09371..98936447451 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
-foo (uint8x16_t a, uint32_t * b, mve_pred16_t p)
+foo (uint8x16_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m_u8 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
-foo1 (uint8x16_t a, uint32_t * b, mve_pred16_t p)
+foo1 (uint8x16_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c
index ecd4fce5de3..e6c5069af21 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
-foo (int16x8_t a, uint32_t * b)
+foo (int16x8_t a, uint32_t *b)
{
return vshlcq_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+/*
+**foo1:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
-foo1 (int16x8_t a, uint32_t * b)
+foo1 (int16x8_t a, uint32_t *b)
{
return vshlcq (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c
index 2956b93138e..2c17845fd7e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t a, uint32_t * b)
+foo (int32x4_t a, uint32_t *b)
{
return vshlcq_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+/*
+**foo1:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t a, uint32_t * b)
+foo1 (int32x4_t a, uint32_t *b)
{
return vshlcq (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c
index cc22b1b1bd9..ab55f3a29ba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
-foo (int8x16_t a, uint32_t * b)
+foo (int8x16_t a, uint32_t *b)
{
return vshlcq_s8 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+/*
+**foo1:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
-foo1 (int8x16_t a, uint32_t * b)
+foo1 (int8x16_t a, uint32_t *b)
{
return vshlcq (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c
index bbf6c531573..e1862be0249 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint16x8_t a, uint32_t * b)
+foo (uint16x8_t a, uint32_t *b)
{
return vshlcq_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+/*
+**foo1:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
-foo1 (uint16x8_t a, uint32_t * b)
+foo1 (uint16x8_t a, uint32_t *b)
{
return vshlcq (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c
index c42d9c10afe..dc1030fbedf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t a, uint32_t * b)
+foo (uint32x4_t a, uint32_t *b)
{
return vshlcq_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+/*
+**foo1:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t a, uint32_t * b)
+foo1 (uint32x4_t a, uint32_t *b)
{
return vshlcq (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c
index f24b22797c2..cb24651a294 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
-foo (uint8x16_t a, uint32_t * b)
+foo (uint8x16_t a, uint32_t *b)
{
return vshlcq_u8 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+/*
+**foo1:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
-foo1 (uint8x16_t a, uint32_t * b)
+foo1 (uint8x16_t a, uint32_t *b)
{
return vshlcq (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c
index 6d6c4b2d737..1ee641d8d68 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
{
return vshllbq_m_n_s16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
{
return vshllbq_m (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c
index 5d7b9623f1a..93a06cb2676 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
{
return vshllbq_m_n_s8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
{
return vshllbq_m (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c
index 3697775ea0f..67039260cd5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vshllbq_m_n_u16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vshllbq_m (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c
index 39a10e21b0b..f02293bb874 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vshllbq_m_n_u8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vshllbq_m (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c
index 7d3a4d811cb..906f7fb75d1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshllb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int16x8_t a)
{
return vshllbq_n_s16 (a, 1);
}
-/* { dg-final { scan-assembler "vshllb.s16" } } */
+/*
+**foo1:
+** ...
+** vshllb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int16x8_t a)
{
return vshllbq (a, 1);
}
-/* { dg-final { scan-assembler "vshllb.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c
index 63b406978c1..f63ff4b7556 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshllb.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int8x16_t a)
{
return vshllbq_n_s8 (a, 1);
}
-/* { dg-final { scan-assembler "vshllb.s8" } } */
+/*
+**foo1:
+** ...
+** vshllb.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int8x16_t a)
{
return vshllbq (a, 1);
}
-/* { dg-final { scan-assembler "vshllb.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c
index 9306d244645..883d2979f32 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshllb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint16x8_t a)
{
return vshllbq_n_u16 (a, 1);
}
-/* { dg-final { scan-assembler "vshllb.u16" } } */
+/*
+**foo1:
+** ...
+** vshllb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint16x8_t a)
{
return vshllbq (a, 1);
}
-/* { dg-final { scan-assembler "vshllb.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c
index 0b24160216e..bbdec7ba321 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshllb.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint8x16_t a)
{
return vshllbq_n_u8 (a, 1);
}
-/* { dg-final { scan-assembler "vshllb.u8" } } */
+/*
+**foo1:
+** ...
+** vshllb.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint8x16_t a)
{
return vshllbq (a, 1);
}
-/* { dg-final { scan-assembler "vshllb.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c
index 689fc749b00..239c536f4a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int16x8_t a, mve_pred16_t p)
{
- return vshllbq_x_n_s16 (a, 1, p);
+ return vshllbq_x_n_s16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int32x4_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+ return vshllbq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c
index 82f684d1cd5..9371b523c3f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int8x16_t a, mve_pred16_t p)
{
- return vshllbq_x_n_s8 (a, 1, p);
+ return vshllbq_x_n_s8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int16x8_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+ return vshllbq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c
index 5c51a4e4011..72f9aed343e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint16x8_t a, mve_pred16_t p)
{
- return vshllbq_x_n_u16 (a, 1, p);
+ return vshllbq_x_n_u16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint32x4_t
+foo1 (uint16x8_t a, mve_pred16_t p)
+{
+ return vshllbq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c
index 5a713befb27..bd209428300 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint8x16_t a, mve_pred16_t p)
{
- return vshllbq_x_n_u8 (a, 1, p);
+ return vshllbq_x_n_u8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo1 (uint8x16_t a, mve_pred16_t p)
+{
+ return vshllbq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c
index 8153a570a9a..80035011527 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
{
return vshlltq_m_n_s16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
{
return vshlltq_m (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c
index 3f47337c9b6..19e2f3c7469 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
{
return vshlltq_m_n_s8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
{
return vshlltq_m (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c
index f5af1b31087..46af8731146 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vshlltq_m_n_u16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vshlltq_m (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c
index 92154d25387..ed7814c39dc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vshlltq_m_n_u8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vshlltq_m (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c
index ced2aa64217..b2987300406 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshllt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int16x8_t a)
{
return vshlltq_n_s16 (a, 1);
}
-/* { dg-final { scan-assembler "vshllt.s16" } } */
+/*
+**foo1:
+** ...
+** vshllt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int16x8_t a)
{
return vshlltq (a, 1);
}
-/* { dg-final { scan-assembler "vshllt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c
index 9fc0cd7ced9..c5b84aa5e2e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshllt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int8x16_t a)
{
return vshlltq_n_s8 (a, 1);
}
-/* { dg-final { scan-assembler "vshllt.s8" } } */
+/*
+**foo1:
+** ...
+** vshllt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int8x16_t a)
{
return vshlltq (a, 1);
}
-/* { dg-final { scan-assembler "vshllt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c
index 47b948e2468..358a5b4a3e7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshllt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint16x8_t a)
{
return vshlltq_n_u16 (a, 1);
}
-/* { dg-final { scan-assembler "vshllt.u16" } } */
+/*
+**foo1:
+** ...
+** vshllt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint16x8_t a)
{
return vshlltq (a, 1);
}
-/* { dg-final { scan-assembler "vshllt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c
index eac7422a1f1..223649215a6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshllt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint8x16_t a)
{
return vshlltq_n_u8 (a, 1);
}
-/* { dg-final { scan-assembler "vshllt.u8" } } */
+/*
+**foo1:
+** ...
+** vshllt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint8x16_t a)
{
return vshlltq (a, 1);
}
-/* { dg-final { scan-assembler "vshllt.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c
index 0e9e789c1e0..12d55e49aed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int16x8_t a, mve_pred16_t p)
{
- return vshlltq_x_n_s16 (a, 1, p);
+ return vshlltq_x_n_s16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int32x4_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+ return vshlltq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c
index 67966bed12c..dfad54a5eae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int8x16_t a, mve_pred16_t p)
{
- return vshlltq_x_n_s8 (a, 1, p);
+ return vshlltq_x_n_s8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int16x8_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+ return vshlltq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c
index dedc795797e..e9077d26918 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint16x8_t a, mve_pred16_t p)
{
- return vshlltq_x_n_u16 (a, 1, p);
+ return vshlltq_x_n_u16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint32x4_t
+foo1 (uint16x8_t a, mve_pred16_t p)
+{
+ return vshlltq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c
index a93c69d8d98..1d4d2795fa9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint8x16_t a, mve_pred16_t p)
{
- return vshlltq_x_n_u8 (a, 1, p);
+ return vshlltq_x_n_u8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo1 (uint8x16_t a, mve_pred16_t p)
+{
+ return vshlltq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c
index 6c0342da0cc..754d412c81d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vshlq_m_n_s16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c
index 0e472801de5..5805f90a105 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vshlq_m_n_s32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c
index 0f9efacc749..b69b52cf099 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vshlq_m_n_s8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c
index 0c4d9e9b7b5..152844bf318 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vshlq_m_n_u16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c
index cf247f879aa..9acfd9b8c6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vshlq_m_n_u32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c
index 64bda13216d..d2e7fe59f3f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vshlq_m_n_u8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c
index abd747e9008..ce72e8c408b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c
index 001a8d170fc..219c7d2ca73 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c
index 890dd359e65..22fdee6bd6c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c
index 91574c5db26..25eca63907d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c
index f6ec8797a83..9d24eda6e60 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c
index 37f0f488801..2421e0b72ec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c
index 759379c9fc5..c28996ad2cc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vshlq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c
index 4878f0b0e4f..ca4801df9ba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vshlq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c
index f4ed7f5aaeb..782eedbc774 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vshlq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c
index 99ae7ed9a53..941a6cc3578 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vshlq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c
index 7094ba2ccd7..75e10801ae7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vshlq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c
index e7c481a3b8c..dbabcd55900 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vshlq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c
index e24bb9acd75..83dee27238a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a)
{
return vshlq_n_s16 (a, 1);
}
-/* { dg-final { scan-assembler "vshl.s16" } } */
+/*
+**foo1:
+** ...
+** vshl.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a)
{
return vshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vshl.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c
index f537879249f..6b390c8b333 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a)
{
- return vshlq_n_s32 (a, 16);
+ return vshlq_n_s32 (a, 1);
}
-/* { dg-final { scan-assembler "vshl.s32" } } */
+/*
+**foo1:
+** ...
+** vshl.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a)
{
- return vshlq_n (a, 16);
+ return vshlq_n (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshl.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c
index ba6ddf3f8a1..e4fd7121bff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a)
{
return vshlq_n_s8 (a, 1);
}
-/* { dg-final { scan-assembler "vshl.s8" } } */
+/*
+**foo1:
+** ...
+** vshl.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a)
{
return vshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vshl.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c
index 730c7af40c6..6c37303a9fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a)
{
- return vshlq_n_u16 (a, 11);
+ return vshlq_n_u16 (a, 1);
}
-/* { dg-final { scan-assembler "vshl.u16" } } */
+/*
+**foo1:
+** ...
+** vshl.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a)
{
- return vshlq_n (a, 11);
+ return vshlq_n (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshl.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c
index 36caf5a9032..408f756408f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a)
{
return vshlq_n_u32 (a, 1);
}
-/* { dg-final { scan-assembler "vshl.u32" } } */
+/*
+**foo1:
+** ...
+** vshl.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a)
{
return vshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vshl.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c
index a5ba9805d9b..5ecdddccadf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a)
{
return vshlq_n_u8 (a, 1);
}
-/* { dg-final { scan-assembler "vshl.u8" } } */
+/*
+**foo1:
+** ...
+** vshl.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a)
{
return vshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vshl.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c
index b6d3e858d7c..f9a8257729e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32_t b)
{
return vshlq_r_s16 (a, b);
}
-/* { dg-final { scan-assembler "vshl.s16" } } */
+/*
+**foo1:
+** ...
+** vshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32_t b)
{
return vshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vshl.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c
index e04e2a7bcf3..f4f8e363059 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32_t b)
{
return vshlq_r_s32 (a, b);
}
-/* { dg-final { scan-assembler "vshl.s32" } } */
+/*
+**foo1:
+** ...
+** vshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32_t b)
{
return vshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vshl.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c
index d5e54c0a79a..c14d012a1e2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int32_t b)
{
return vshlq_r_s8 (a, b);
}
-/* { dg-final { scan-assembler "vshl.s8" } } */
+/*
+**foo1:
+** ...
+** vshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int32_t b)
{
return vshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vshl.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c
index 813bea0575d..71634680deb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32_t b)
{
return vshlq_r_u16 (a, b);
}
-/* { dg-final { scan-assembler "vshl.u16" } } */
+/*
+**foo1:
+** ...
+** vshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32_t b)
{
return vshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vshl.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c
index 84a61e47ca7..0d47f85bc82 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32_t b)
{
return vshlq_r_u32 (a, b);
}
-/* { dg-final { scan-assembler "vshl.u32" } } */
+/*
+**foo1:
+** ...
+** vshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32_t b)
{
return vshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vshl.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c
index 01f9a7d8f19..2d64908eeca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int32_t b)
{
return vshlq_r_u8 (a, b);
}
-/* { dg-final { scan-assembler "vshl.u8" } } */
+/*
+**foo1:
+** ...
+** vshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int32_t b)
{
return vshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vshl.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c
index 5d3e1e5fdf9..6158fafcdb5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vshlq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vshl.s16" } } */
+/*
+**foo1:
+** ...
+** vshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vshlq (a, b);
}
-/* { dg-final { scan-assembler "vshl.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c
index cecd050888f..b0b18470dea 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vshlq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vshl.s32" } } */
+/*
+**foo1:
+** ...
+** vshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vshlq (a, b);
}
-/* { dg-final { scan-assembler "vshl.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c
index d44610f4f5b..70b2d806131 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vshlq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vshl.s8" } } */
+/*
+**foo1:
+** ...
+** vshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vshlq (a, b);
}
-/* { dg-final { scan-assembler "vshl.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c
index 210fa905d3d..3ab782fa734 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int16x8_t b)
{
return vshlq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vshl.u16" } } */
+/*
+**foo1:
+** ...
+** vshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int16x8_t b)
{
return vshlq (a, b);
}
-/* { dg-final { scan-assembler "vshl.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c
index 8fc59620016..f104235caee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32x4_t b)
{
return vshlq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vshl.u32" } } */
+/*
+**foo1:
+** ...
+** vshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32x4_t b)
{
return vshlq (a, b);
}
-/* { dg-final { scan-assembler "vshl.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c
index 8332d501640..1a93abfefb1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int8x16_t b)
{
return vshlq_u8 (a, b);
}
-/* { dg-final { scan-assembler "vshl.u8" } } */
+/*
+**foo1:
+** ...
+** vshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int8x16_t b)
{
return vshlq (a, b);
}
-/* { dg-final { scan-assembler "vshl.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c
index 4bdbc848bb7..5ac725187e8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
- return vshlq_x_n_s16 (a, 1, p);
+ return vshlq_x_n_s16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int16x8_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+ return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c
index 7648d2e2c66..e5e3ab03f01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
- return vshlq_x_n_s32 (a, 1, p);
+ return vshlq_x_n_s32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int32x4_t
+foo1 (int32x4_t a, mve_pred16_t p)
+{
+ return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c
index 4b303e92e81..7618d83b85b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, mve_pred16_t p)
{
- return vshlq_x_n_s8 (a, 1, p);
+ return vshlq_x_n_s8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int8x16_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+ return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c
index a2b6ac2d4c0..b4f937ae8f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
- return vshlq_x_n_u16 (a, 1, p);
+ return vshlq_x_n_u16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo1 (uint16x8_t a, mve_pred16_t p)
+{
+ return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c
index 59aa9dbe182..e42270ba293 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, mve_pred16_t p)
{
- return vshlq_x_n_u32 (a, 1, p);
+ return vshlq_x_n_u32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint32x4_t
+foo1 (uint32x4_t a, mve_pred16_t p)
+{
+ return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c
index 64069bb1728..7e01f8b2ab5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, mve_pred16_t p)
{
- return vshlq_x_n_u8 (a, 1, p);
+ return vshlq_x_n_u8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint8x16_t
+foo1 (uint8x16_t a, mve_pred16_t p)
+{
+ return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c
index 61a643d64bd..a6eeff654e3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
- return vshlq_x_s16 (a, b, p);
+ return vshlq_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+int16x8_t
+foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c
index 71424456f7d..cc3c434708a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
- return vshlq_x_s32 (a, b, p);
+ return vshlq_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+int32x4_t
+foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c
index 0d4825a03ad..430a3ab43ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
- return vshlq_x_s8 (a, b, p);
+ return vshlq_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+int8x16_t
+foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c
index 7ce18722444..9f5d0903588 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int16x8_t b, mve_pred16_t p)
{
- return vshlq_x_u16 (a, b, p);
+ return vshlq_x_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c
index fe02cc694a2..32d729f6954 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32x4_t b, mve_pred16_t p)
{
- return vshlq_x_u32 (a, b, p);
+ return vshlq_x_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+uint32x4_t
+foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c
index 9611b268ca5..45e72c9dffa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int8x16_t b, mve_pred16_t p)
{
- return vshlq_x_u8 (a, b, p);
+ return vshlq_x_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+uint8x16_t
+foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c
index d069cb0db44..ab37f2605e0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
- return vshrnbq_m_n_s16 (a, b, 8, p);
+ return vshrnbq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
- return vshrnbq_m (a, b, 8, p);
+ return vshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c
index 50a450f5b52..9fd9f8a7804 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
- return vshrnbq_m_n_s32 (a, b, 16, p);
+ return vshrnbq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
- return vshrnbq_m (a, b, 16, p);
+ return vshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c
index e5762145e64..e9408eeb1bf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
- return vshrnbq_m_n_u16 (a, b, 8, p);
+ return vshrnbq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
- return vshrnbq_m (a, b, 8, p);
+ return vshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c
index 88da8e6f341..69699fd15ab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
- return vshrnbq_m_n_u32 (a, b, 16, p);
+ return vshrnbq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
- return vshrnbq_m (a, b, 16, p);
+ return vshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c
index 7fcd9e479dc..0320d690627 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
- return vshrnbq_n_s16 (a, b, 8);
+ return vshrnbq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshrnb.i16" } } */
+/*
+**foo1:
+** ...
+** vshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
- return vshrnbq (a, b, 8);
+ return vshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshrnb.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c
index 38d4fdfc05f..aa7b107f7f9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
- return vshrnbq_n_s32 (a, b, 16);
+ return vshrnbq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshrnb.i32" } } */
+/*
+**foo1:
+** ...
+** vshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
- return vshrnbq (a, b, 16);
+ return vshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshrnb.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c
index ff341a9f202..4f896469eb4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
- return vshrnbq_n_u16 (a, b, 8);
+ return vshrnbq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshrnb.i16" } } */
+/*
+**foo1:
+** ...
+** vshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
- return vshrnbq (a, b, 8);
+ return vshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshrnb.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c
index b891c036d36..d3d22978542 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
- return vshrnbq_n_u32 (a, b, 16);
+ return vshrnbq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshrnb.i32" } } */
+/*
+**foo1:
+** ...
+** vshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
- return vshrnbq (a, b, 16);
+ return vshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshrnb.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c
index 30535470961..77f39ac10c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
- return vshrntq_m_n_s16 (a, b, 8, p);
+ return vshrntq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
- return vshrntq_m (a, b, 8, p);
+ return vshrntq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c
index 2d52f5b6bb1..462d5f446f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
- return vshrntq_m_n_s32 (a, b, 16, p);
+ return vshrntq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
- return vshrntq_m (a, b, 16, p);
+ return vshrntq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c
index ed774e0b31a..0328cc3ef93 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
- return vshrntq_m_n_u16 (a, b, 8, p);
+ return vshrntq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
- return vshrntq_m (a, b, 8, p);
+ return vshrntq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c
index e592e96a5f9..d4882dc2d6d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
- return vshrntq_m_n_u32 (a, b, 16, p);
+ return vshrntq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
- return vshrntq_m (a, b, 16, p);
+ return vshrntq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c
index ddd9d5c0507..c9016ac124f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
- return vshrntq_n_s16 (a, b, 8);
+ return vshrntq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshrnt.i16" } } */
+/*
+**foo1:
+** ...
+** vshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
- return vshrntq (a, b, 8);
+ return vshrntq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshrnt.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c
index e35dbf07fac..6150f28d872 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
- return vshrntq_n_s32 (a, b, 16);
+ return vshrntq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshrnt.i32" } } */
+/*
+**foo1:
+** ...
+** vshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
- return vshrntq (a, b, 16);
+ return vshrntq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshrnt.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c
index 58a6eea561a..75be307feaa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
- return vshrntq_n_u16 (a, b, 8);
+ return vshrntq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshrnt.i16" } } */
+/*
+**foo1:
+** ...
+** vshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
- return vshrntq (a, b, 8);
+ return vshrntq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshrnt.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c
index ec0c10007ff..9b9e534e3d2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
- return vshrntq_n_u32 (a, b, 16);
+ return vshrntq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshrnt.i32" } } */
+/*
+**foo1:
+** ...
+** vshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
- return vshrntq (a, b, 16);
+ return vshrntq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshrnt.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c
index 00f236c6d74..ed1833b8673 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
- return vshrq_m_n_s16 (inactive, a, 16, p);
+ return vshrq_m_n_s16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
- return vshrq_m (inactive, a, 16, p);
+ return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c
index 1d1be501e16..880cd9e3545 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
- return vshrq_m_n_s32 (inactive, a, 32, p);
+ return vshrq_m_n_s32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
- return vshrq_m (inactive, a, 32, p);
+ return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c
index 7410ba9c8e9..53fc84857b7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
- return vshrq_m_n_s8 (inactive, a, 8, p);
+ return vshrq_m_n_s8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
- return vshrq_m (inactive, a, 8, p);
+ return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c
index 4b0dd59eefa..c3e311454b6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
- return vshrq_m_n_u16 (inactive, a, 16, p);
+ return vshrq_m_n_u16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
- return vshrq_m (inactive, a, 16, p);
+ return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c
index 47ccc1b7499..6c0471f0120 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
- return vshrq_m_n_u32 (inactive, a, 32, p);
+ return vshrq_m_n_u32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
- return vshrq_m (inactive, a, 32, p);
+ return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c
index 44f96027a04..5621608a2eb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
- return vshrq_m_n_u8 (inactive, a, 8, p);
+ return vshrq_m_n_u8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
- return vshrq_m (inactive, a, 8, p);
+ return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c
index 051fa4a14a1..59a589b21a1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshr.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a)
{
- return vshrq_n_s16 (a, 16);
+ return vshrq_n_s16 (a, 1);
}
-/* { dg-final { scan-assembler "vshr.s16" } } */
+/*
+**foo1:
+** ...
+** vshr.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a)
{
- return vshrq (a, 16);
+ return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshr.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c
index 65a0b2e6224..1666b6657f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshr.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a)
{
- return vshrq_n_s32 (a, 32);
+ return vshrq_n_s32 (a, 1);
}
-/* { dg-final { scan-assembler "vshr.s32" } } */
+/*
+**foo1:
+** ...
+** vshr.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a)
{
- return vshrq (a, 32);
+ return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshr.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c
index c5adcc1a465..1ce29185bcf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshr.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a)
{
- return vshrq_n_s8 (a, 8);
+ return vshrq_n_s8 (a, 1);
}
-/* { dg-final { scan-assembler "vshr.s8" } } */
+/*
+**foo1:
+** ...
+** vshr.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a)
{
- return vshrq (a, 8);
+ return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshr.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c
index 1b68fafea8a..c2dbe6e5041 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshr.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a)
{
- return vshrq_n_u16 (a, 16);
+ return vshrq_n_u16 (a, 1);
}
-/* { dg-final { scan-assembler "vshr.u16" } } */
+/*
+**foo1:
+** ...
+** vshr.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a)
{
- return vshrq (a, 16);
+ return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshr.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c
index 8b798b793c0..15d231c217f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshr.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a)
{
- return vshrq_n_u32 (a, 32);
+ return vshrq_n_u32 (a, 1);
}
-/* { dg-final { scan-assembler "vshr.u32" } } */
+/*
+**foo1:
+** ...
+** vshr.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a)
{
- return vshrq (a, 32);
+ return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshr.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c
index 14cdf5917e2..19924e0fcdb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshr.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a)
{
- return vshrq_n_u8 (a, 8);
+ return vshrq_n_u8 (a, 1);
}
-/* { dg-final { scan-assembler "vshr.u8" } } */
+/*
+**foo1:
+** ...
+** vshr.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a)
{
- return vshrq (a, 8);
+ return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshr.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c
index 4652693d75c..fc26fd8fd3b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
- return vshrq_x_n_s16 (a, 16, p);
+ return vshrq_x_n_s16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int16x8_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+ return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c
index 43fa28a1f8d..bc9ae54faad 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
- return vshrq_x_n_s32 (a, 32, p);
+ return vshrq_x_n_s32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int32x4_t
+foo1 (int32x4_t a, mve_pred16_t p)
+{
+ return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c
index 042bf488284..391ced24079 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, mve_pred16_t p)
{
- return vshrq_x_n_s8 (a, 8, p);
+ return vshrq_x_n_s8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int8x16_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+ return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c
index d627565fe84..eddb977fa83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
- return vshrq_x_n_u16 (a, 16, p);
+ return vshrq_x_n_u16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo1 (uint16x8_t a, mve_pred16_t p)
+{
+ return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c
index 0f26e7b9efc..6867668d1ce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, mve_pred16_t p)
{
- return vshrq_x_n_u8 (a, 8, p);
+ return vshrq_x_n_u8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint8x16_t
+foo1 (uint8x16_t a, mve_pred16_t p)
+{
+ return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c
index 49d342e7c17..23b346b1cab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
- return vsliq_m_n_s16 (a, b, 15, p);
+ return vsliq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
- return vsliq_m (a, b, 15, p);
+ return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c
index f0f7619dd0a..d640e1f8df4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
- return vsliq_m_n_s32 (a, b, 31, p);
+ return vsliq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
- return vsliq_m (a, b, 31, p);
+ return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c
index 12d295e70f6..14b1afa1d01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
- return vsliq_m_n_s8 (a, b, 7, p);
+ return vsliq_m_n_s8 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
- return vsliq_m (a, b, 7, p);
+ return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c
index 78cdbdf3950..521abbf4694 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
- return vsliq_m_n_u16 (a, b, 15, p);
+ return vsliq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
- return vsliq_m (a, b, 15, p);
+ return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c
index 62e9cfd9f31..951204a31a0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
- return vsliq_m_n_u32 (a, b, 31, p);
+ return vsliq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
- return vsliq_m (a, b, 31, p);
+ return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c
index f86fea32a90..8b893a8c4d2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
- return vsliq_m_n_u8 (a, b, 7, p);
+ return vsliq_m_n_u8 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
- return vsliq_m (a, b, 7, p);
+ return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c
index 2c5f82bb317..a6c86764eab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsli.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
- return vsliq_n_s16 (a, b, 15);
+ return vsliq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsli.16" } } */
+/*
+**foo1:
+** ...
+** vsli.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
- return vsliq (a, b, 15);
+ return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsli.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c
index 0738fd61203..301cdd463b5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsli.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
- return vsliq_n_s32 (a, b, 31);
+ return vsliq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsli.32" } } */
+/*
+**foo1:
+** ...
+** vsli.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
- return vsliq (a, b, 31);
+ return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsli.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c
index 25f2f761c3c..2a26f7f444b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsli.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
- return vsliq_n_s8 (a, b, 7);
+ return vsliq_n_s8 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsli.8" } } */
+/*
+**foo1:
+** ...
+** vsli.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
- return vsliq (a, b, 7);
+ return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsli.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c
index 25bbcd8f3fa..b71572a232e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsli.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b)
{
- return vsliq_n_u16 (a, b, 15);
+ return vsliq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsli.16" } } */
+/*
+**foo1:
+** ...
+** vsli.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b)
{
- return vsliq (a, b, 15);
+ return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsli.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c
index 970e069cabf..ecafb61b487 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsli.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b)
{
- return vsliq_n_u32 (a, b, 31);
+ return vsliq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsli.32" } } */
+/*
+**foo1:
+** ...
+** vsli.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b)
{
- return vsliq (a, b, 31);
+ return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsli.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c
index c24e354a957..e20ec7e030e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsli.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b)
{
- return vsliq_n_u8 (a, b, 7);
+ return vsliq_n_u8 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsli.8" } } */
+/*
+**foo1:
+** ...
+** vsli.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b)
{
- return vsliq (a, b, 7);
+ return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsli.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c
index 799232a8dc1..086f5f86fc1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
- return vsriq_m_n_s16 (a, b, 4, p);
+ return vsriq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
- return vsriq_m (a, b, 4, p);
+ return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c
index 7e019782c88..90267f67e54 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
- return vsriq_m_n_s32 (a, b, 2, p);
+ return vsriq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
- return vsriq_m (a, b, 2, p);
+ return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c
index 8fa3e757f6d..6c7552905b4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
- return vsriq_m_n_s8 (a, b, 4, p);
+ return vsriq_m_n_s8 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
- return vsriq_m (a, b, 4, p);
+ return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c
index 5e2c4a3deb3..624732b0c91 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
- return vsriq_m_n_u16 (a, b, 4, p);
+ return vsriq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
- return vsriq_m (a, b, 4, p);
+ return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c
index 368115e27b2..48abe8b9c0d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
- return vsriq_m_n_u32 (a, b, 4, p);
+ return vsriq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
- return vsriq_m (a, b, 4, p);
+ return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c
index 54db7d78836..b1f9ecd0c9f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
- return vsriq_m_n_u8 (a, b, 4, p);
+ return vsriq_m_n_u8 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
- return vsriq_m (a, b, 4, p);
+ return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c
index 75f57ae76a7..2f8bde64ff5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsri.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
- return vsriq_n_s16 (a, b, 4);
+ return vsriq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsri.16" } } */
+/*
+**foo1:
+** ...
+** vsri.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
- return vsriq (a, b, 4);
+ return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsri.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c
index 46d9ead1e9a..a95e6dae8f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsri.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
- return vsriq_n_s32 (a, b, 4);
+ return vsriq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsri.32" } } */
+/*
+**foo1:
+** ...
+** vsri.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
- return vsriq (a, b, 4);
+ return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsri.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c
index 3dcc5a34f90..7726a7ed934 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsri.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
- return vsriq_n_s8 (a, b, 4);
+ return vsriq_n_s8 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsri.8" } } */
+/*
+**foo1:
+** ...
+** vsri.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
- return vsriq (a, b, 4);
+ return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsri.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c
index ff6c4f0c277..4d8d5930b49 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsri.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b)
{
- return vsriq_n_u16 (a, b, 4);
+ return vsriq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsri.16" } } */
+/*
+**foo1:
+** ...
+** vsri.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b)
{
- return vsriq (a, b, 4);
+ return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsri.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c
index f6b79b26235..83a6b13ef40 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsri.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b)
{
- return vsriq_n_u32 (a, b, 4);
+ return vsriq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsri.32" } } */
+/*
+**foo1:
+** ...
+** vsri.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b)
{
- return vsriq (a, b, 4);
+ return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsri.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c
index 4c56b3ab00d..0bd9ac5ddfd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsri.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b)
{
- return vsriq_n_u8 (a, b, 4);
+ return vsriq_n_u8 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsri.8" } } */
+/*
+**foo1:
+** ...
+** vsri.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b)
{
- return vsriq (a, b, 4);
+ return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsri.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c
index 312b7464f17..1fa02f00f53 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c
@@ -1,25 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
-void
-foo (float16_t * addr, float16x8_t value)
-{
- vst1q_f16 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+**foo:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (float16_t * addr, float16x8_t value)
+foo (float16_t *base, float16x8_t value)
{
- vst1q (addr, value);
+ return vst1q_f16 (base, value);
}
-/* { dg-final { scan-assembler-times "vstrh.16" 2 } } */
+/*
+**foo1:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo2 (float16_t a, float16x8_t x)
+foo1 (float16_t *base, float16x8_t value)
{
- vst1q (&a, x);
+ return vst1q (base, value);
}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c
index a6ae1cef2d4..67cc3ae3b47 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (float32_t * addr, float32x4_t value)
+foo (float32_t *base, float32x4_t value)
{
- vst1q_f32 (addr, value);
+ return vst1q_f32 (base, value);
}
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/*
+**foo1:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (float32_t * addr, float32x4_t value)
+foo1 (float32_t *base, float32x4_t value)
{
- vst1q (addr, value);
+ return vst1q (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c
index f6db22d481a..06b2bd3910d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (float16_t * addr, float16x8_t value, mve_pred16_t p)
+foo (float16_t *base, float16x8_t value, mve_pred16_t p)
{
- vst1q_p_f16 (addr, value, p);
+ return vst1q_p_f16 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (float16_t * addr, float16x8_t value, mve_pred16_t p)
+foo1 (float16_t *base, float16x8_t value, mve_pred16_t p)
{
- vst1q_p (addr, value, p);
+ return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c
index 17e7f9c5dfd..e492a705ea0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (float32_t * addr, float32x4_t value, mve_pred16_t p)
+foo (float32_t *base, float32x4_t value, mve_pred16_t p)
{
- vst1q_p_f32 (addr, value, p);
+ return vst1q_p_f32 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p)
+foo1 (float32_t *base, float32x4_t value, mve_pred16_t p)
{
- vst1q_p (addr, value, p);
+ return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c
index b142fc3b021..7b76d1d7687 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int16_t * addr, int16x8_t value, mve_pred16_t p)
+foo (int16_t *base, int16x8_t value, mve_pred16_t p)
{
- vst1q_p_s16 (addr, value, p);
+ return vst1q_p_s16 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int16_t * addr, int16x8_t value, mve_pred16_t p)
+foo1 (int16_t *base, int16x8_t value, mve_pred16_t p)
{
- vst1q_p (addr, value, p);
+ return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c
index 6334462e230..4ad32a68a96 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int32_t * addr, int32x4_t value, mve_pred16_t p)
+foo (int32_t *base, int32x4_t value, mve_pred16_t p)
{
- vst1q_p_s32 (addr, value, p);
+ return vst1q_p_s32 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p)
+foo1 (int32_t *base, int32x4_t value, mve_pred16_t p)
{
- vst1q_p (addr, value, p);
+ return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c
index 1f3f0343820..2425b9cec00 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int8_t * addr, int8x16_t value, mve_pred16_t p)
+foo (int8_t *base, int8x16_t value, mve_pred16_t p)
{
- vst1q_p_s8 (addr, value, p);
+ return vst1q_p_s8 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrbt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int8_t * addr, int8x16_t value, mve_pred16_t p)
+foo1 (int8_t *base, int8x16_t value, mve_pred16_t p)
{
- vst1q_p (addr, value, p);
+ return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrbt.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c
index 331cd34cdce..c0065ef6ff5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint16_t * addr, uint16x8_t value, mve_pred16_t p)
+foo (uint16_t *base, uint16x8_t value, mve_pred16_t p)
{
- vst1q_p_u16 (addr, value, p);
+ return vst1q_p_u16 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint16_t * addr, uint16x8_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint16x8_t value, mve_pred16_t p)
{
- vst1q_p (addr, value, p);
+ return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c
index 27836c32451..c41c4184b9b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
+foo (uint32_t *base, uint32x4_t value, mve_pred16_t p)
{
- vst1q_p_u32 (addr, value, p);
+ return vst1q_p_u32 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
+foo1 (uint32_t *base, uint32x4_t value, mve_pred16_t p)
{
- vst1q_p (addr, value, p);
+ return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c
index bfbc542dc35..1cd3a781357 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint8_t * addr, uint8x16_t value, mve_pred16_t p)
+foo (uint8_t *base, uint8x16_t value, mve_pred16_t p)
{
- vst1q_p_u8 (addr, value, p);
+ return vst1q_p_u8 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrbt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint8_t * addr, uint8x16_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint8x16_t value, mve_pred16_t p)
{
- vst1q_p (addr, value, p);
+ return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrbt.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c
index cd14e2c408f..052959b2083 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c
@@ -1,25 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
-void
-foo (int16_t * addr, int16x8_t value)
-{
- vst1q_s16 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+**foo:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int16_t * addr, int16x8_t value)
+foo (int16_t *base, int16x8_t value)
{
- vst1q (addr, value);
+ return vst1q_s16 (base, value);
}
-/* { dg-final { scan-assembler-times "vstrh.16" 2 } } */
+/*
+**foo1:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo2 (int16_t a, int16x8_t x)
+foo1 (int16_t *base, int16x8_t value)
{
- vst1q (&a, x);
+ return vst1q (base, value);
}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c
index e07e8a30f9d..444ad07f4ef 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int32_t * addr, int32x4_t value)
+foo (int32_t *base, int32x4_t value)
{
- vst1q_s32 (addr, value);
+ return vst1q_s32 (base, value);
}
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/*
+**foo1:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int32_t * addr, int32x4_t value)
+foo1 (int32_t *base, int32x4_t value)
{
- vst1q (addr, value);
+ return vst1q (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c
index 0004c80963e..684ff0aca5b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c
@@ -1,25 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
-void
-foo (int8_t * addr, int8x16_t value)
-{
- vst1q_s8 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+**foo:
+** ...
+** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int8_t * addr, int8x16_t value)
+foo (int8_t *base, int8x16_t value)
{
- vst1q (addr, value);
+ return vst1q_s8 (base, value);
}
-/* { dg-final { scan-assembler-times "vstrb.8" 2 } } */
+/*
+**foo1:
+** ...
+** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo2 (int8_t a, int8x16_t x)
+foo1 (int8_t *base, int8x16_t value)
{
- vst1q (&a, x);
+ return vst1q (base, value);
}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c
index 248e7ce82b0..1fea2de1e76 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c
@@ -1,25 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
-void
-foo (uint16_t * addr, uint16x8_t value)
-{
- vst1q_u16 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+**foo:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint16_t * addr, uint16x8_t value)
+foo (uint16_t *base, uint16x8_t value)
{
- vst1q (addr, value);
+ return vst1q_u16 (base, value);
}
-/* { dg-final { scan-assembler-times "vstrh.16" 2 } } */
+/*
+**foo1:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo2 (uint16_t a, uint16x8_t x)
+foo1 (uint16_t *base, uint16x8_t value)
{
- vst1q (&a, x);
+ return vst1q (base, value);
}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c
index d1fdf8897b5..64c43c59d47 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint32_t * addr, uint32x4_t value)
+foo (uint32_t *base, uint32x4_t value)
{
- vst1q_u32 (addr, value);
+ return vst1q_u32 (base, value);
}
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/*
+**foo1:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint32_t * addr, uint32x4_t value)
+foo1 (uint32_t *base, uint32x4_t value)
{
- vst1q (addr, value);
+ return vst1q (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c
index f8b48a69903..5517611bba6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c
@@ -1,25 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
-void
-foo (uint8_t * addr, uint8x16_t value)
-{
- vst1q_u8 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+**foo:
+** ...
+** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint8_t * addr, uint8x16_t value)
+foo (uint8_t *base, uint8x16_t value)
{
- vst1q (addr, value);
+ return vst1q_u8 (base, value);
}
-/* { dg-final { scan-assembler-times "vstrb.8" 2 } } */
+/*
+**foo1:
+** ...
+** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo2 (uint8_t a, uint8x16_t x)
+foo1 (uint8_t *base, uint8x16_t value)
{
- vst1q (&a, x);
+ return vst1q (base, value);
}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c
index c694e2b6ad3..25a889dd1f0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint64x2_t addr, const int offset, int64x2_t value, mve_pred16_t p)
+foo (uint64x2_t addr, int64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_base_p_s64 (addr, 8, value, p);
+ return vstrdq_scatter_base_p_s64 (addr, 0, value, p);
}
-/* { dg-final { scan-assembler "vstrdt.u64" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint64x2_t addr, const int offset, int64x2_t value, mve_pred16_t p)
+foo1 (uint64x2_t addr, int64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_base_p (addr, 8, value, p);
+ return vstrdq_scatter_base_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrdt.u64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c
index 6e8507c81d9..f0731f69a09 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint64x2_t addr, const int offset, uint64x2_t value, mve_pred16_t p)
+foo (uint64x2_t addr, uint64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_base_p_u64 (addr, 8, value, p);
+ return vstrdq_scatter_base_p_u64 (addr, 0, value, p);
}
-/* { dg-final { scan-assembler "vstrdt.u64" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint64x2_t addr, const int offset, uint64x2_t value, mve_pred16_t p)
+foo1 (uint64x2_t addr, uint64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_base_p (addr, 8, value, p);
+ return vstrdq_scatter_base_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrdt.u64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c
index b9aac8036d4..31cdec9ba0a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint64x2_t addr, const int offset, int64x2_t value)
+foo (uint64x2_t addr, int64x2_t value)
{
- vstrdq_scatter_base_s64 (addr, 1016, value);
+ return vstrdq_scatter_base_s64 (addr, 0, value);
}
-/* { dg-final { scan-assembler "vstrd.u64" } } */
+/*
+**foo1:
+** ...
+** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint64x2_t addr, const int offset, int64x2_t value)
+foo1 (uint64x2_t addr, int64x2_t value)
{
- vstrdq_scatter_base (addr, 1016, value);
+ return vstrdq_scatter_base (addr, 0, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrd.u64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c
index 888d4e0c031..8f0195c9e8f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint64x2_t addr, const int offset, uint64x2_t value)
+foo (uint64x2_t addr, uint64x2_t value)
{
- vstrdq_scatter_base_u64 (addr, 8, value);
+ return vstrdq_scatter_base_u64 (addr, 0, value);
}
-/* { dg-final { scan-assembler "vstrd.u64" } } */
+/*
+**foo1:
+** ...
+** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint64x2_t addr, const int offset, uint64x2_t value)
+foo1 (uint64x2_t addr, uint64x2_t value)
{
- vstrdq_scatter_base (addr, 8, value);
+ return vstrdq_scatter_base (addr, 0, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrd.u64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c
index 319188b706f..8f19ede4e1a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c
@@ -1,19 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo (uint64x2_t * addr, const int offset, int64x2_t value, mve_pred16_t p)
+foo (uint64x2_t *addr, int64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_base_wb_p_s64 (addr, 8, value, p);
+ return vstrdq_scatter_base_wb_p_s64 (addr, 0, value, p);
}
+
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo1 (uint64x2_t * addr, const int offset, int64x2_t value, mve_pred16_t p)
+foo1 (uint64x2_t *addr, int64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_base_wb_p (addr, 8, value, p);
+ return vstrdq_scatter_base_wb_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler-times "vstrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c
index 940b5421c84..41958c961f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c
@@ -1,19 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo (uint64x2_t * addr, const int offset, uint64x2_t value, mve_pred16_t p)
+foo (uint64x2_t *addr, uint64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_base_wb_p_u64 (addr, 8, value, p);
+ return vstrdq_scatter_base_wb_p_u64 (addr, 0, value, p);
}
+
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo1 (uint64x2_t * addr, const int offset, uint64x2_t value, mve_pred16_t p)
+foo1 (uint64x2_t *addr, uint64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_base_wb_p (addr, 8, value, p);
+ return vstrdq_scatter_base_wb_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler-times "vstrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c
index 33926d5c9e2..fc06db1c202 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c
@@ -1,19 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo (uint64x2_t * addr, const int offset, int64x2_t value)
+foo (uint64x2_t *addr, int64x2_t value)
{
- vstrdq_scatter_base_wb_s64 (addr, 8, value);
+ return vstrdq_scatter_base_wb_s64 (addr, 0, value);
}
+
+/*
+**foo1:
+** ...
+** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo1 (uint64x2_t * addr, const int offset, int64x2_t value)
+foo1 (uint64x2_t *addr, int64x2_t value)
{
- vstrdq_scatter_base_wb (addr, 8, value);
+ return vstrdq_scatter_base_wb (addr, 0, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler-times "vstrd.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c
index b7ffcf9b5dd..c6529e617e3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c
@@ -1,19 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo (uint64x2_t * addr, const int offset, uint64x2_t value)
+foo (uint64x2_t *addr, uint64x2_t value)
{
- vstrdq_scatter_base_wb_u64 (addr, 8, value);
+ return vstrdq_scatter_base_wb_u64 (addr, 0, value);
}
+
+/*
+**foo1:
+** ...
+** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo1 (uint64x2_t * addr, const int offset, uint64x2_t value)
+foo1 (uint64x2_t *addr, uint64x2_t value)
{
- vstrdq_scatter_base_wb (addr, 8, value);
+ return vstrdq_scatter_base_wb (addr, 0, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler-times "vstrd.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c
index 7ebf858f816..754fb59df4c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
+foo (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_offset_p_s64 (base, offset, value, p);
+ return vstrdq_scatter_offset_p_s64 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrdt.64" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
+foo1 (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_offset_p (base, offset, value, p);
+ return vstrdq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrdt.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c
index 4829bada1a9..046f29a6621 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
+foo (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_offset_p_u64 (base, offset, value, p);
+ return vstrdq_scatter_offset_p_u64 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrdt.64" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
+foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_offset_p (base, offset, value, p);
+ return vstrdq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrdt.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c
index fb7317bc4d7..73e25cdf0ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (int64_t * base, uint64x2_t offset, int64x2_t value)
+foo (int64_t *base, uint64x2_t offset, int64x2_t value)
{
- vstrdq_scatter_offset_s64 (base, offset, value);
+ return vstrdq_scatter_offset_s64 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrd.64" } } */
+/*
+**foo1:
+** ...
+** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value)
+foo1 (int64_t *base, uint64x2_t offset, int64x2_t value)
{
- vstrdq_scatter_offset (base, offset, value);
+ return vstrdq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrd.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c
index e8b3a0210b4..d49adde0b94 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value)
+foo (uint64_t *base, uint64x2_t offset, uint64x2_t value)
{
- vstrdq_scatter_offset_u64 (base, offset, value);
+ return vstrdq_scatter_offset_u64 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrd.64" } } */
+/*
+**foo1:
+** ...
+** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value)
+foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value)
{
- vstrdq_scatter_offset (base, offset, value);
+ return vstrdq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrd.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c
index 9ca83e0f3fd..8acfba1f55e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
void
-foo (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
+foo (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_shifted_offset_p_s64 (base, offset, value, p);
+ return vstrdq_scatter_shifted_offset_p_s64 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrdt.64" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
void
-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
+foo1 (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_shifted_offset_p (base, offset, value, p);
+ return vstrdq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrdt.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c
index 1c33df18e84..630c627d604 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
void
-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
+foo (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_shifted_offset_p_u64 (base, offset, value, p);
+ return vstrdq_scatter_shifted_offset_p_u64 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrdt.64" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
void
-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
+foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_shifted_offset_p (base, offset, value, p);
+ return vstrdq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrdt.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c
index 8af348ddbe2..ec73bca4869 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
void
-foo (int64_t * base, uint64x2_t offset, int64x2_t value)
+foo (int64_t *base, uint64x2_t offset, int64x2_t value)
{
- vstrdq_scatter_shifted_offset_s64 (base, offset, value);
+ return vstrdq_scatter_shifted_offset_s64 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrd.64" } } */
+/*
+**foo1:
+** ...
+** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
void
-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value)
+foo1 (int64_t *base, uint64x2_t offset, int64x2_t value)
{
- vstrdq_scatter_shifted_offset (base, offset, value);
+ return vstrdq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrd.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c
index bc153a07192..9bdf8003961 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
void
-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value)
+foo (uint64_t *base, uint64x2_t offset, uint64x2_t value)
{
- vstrdq_scatter_shifted_offset_u64 (base, offset, value);
+ return vstrdq_scatter_shifted_offset_u64 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrd.64" } } */
+/*
+**foo1:
+** ...
+** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
void
-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value)
+foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value)
{
- vstrdq_scatter_shifted_offset (base, offset, value);
+ return vstrdq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrd.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--
2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 04/10] arm: Stop vadcq, vsbcq intrinsics from overwriting the FPSCR NZ flags
2023-04-28 11:29 [PATCH 01/10] arm: Mve testsuite improvements Andrea Corallo
2023-04-28 11:29 ` [PATCH 02/10] arm: Fix vstrwq* backend + testsuite Andrea Corallo
2023-04-28 11:29 ` [PATCH 03/10] arm: Mve backend + testsuite fixes 2 Andrea Corallo
@ 2023-04-28 11:29 ` Andrea Corallo
2023-04-28 16:45 ` Kyrylo Tkachov
2023-04-28 11:29 ` [PATCH 05/10] arm: Add vorrq_n overloading into vorrq _Generic Andrea Corallo
` (6 subsequent siblings)
9 siblings, 1 reply; 31+ messages in thread
From: Andrea Corallo @ 2023-04-28 11:29 UTC (permalink / raw)
To: gcc-patches; +Cc: kyrylo.tkachov, Richard.Earnshaw, Stam Markianos-Wright
From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Hi all,
We noticed that calls to the vadcq and vsbcq intrinsics, both of
which use __builtin_arm_set_fpscr_nzcvqc to set the Carry flag in
the FPSCR, would produce the following code:
```
< r2 is the *carry input >
vmrs r3, FPSCR_nzcvqc
bic r3, r3, #536870912
orr r3, r3, r2, lsl #29
vmsr FPSCR_nzcvqc, r3
```
when the MVE ACLE instead gives a different instruction sequence of:
```
< Rt is the *carry input >
VMRS Rs,FPSCR_nzcvqc
BFI Rs,Rt,#29,#1
VMSR FPSCR_nzcvqc,Rs
```
the bic + orr pair is slower and it's also wrong, because, if the
*carry input is greater than 1, then we risk overwriting the top two
bits of the FPSCR register (the N and Z flags).
This turned out to be a problem in the header file and the solution was
to simply add a `& 1x0u` to the `*carry` input: then the compiler knows
that we only care about the lowest bit and can optimise to a BFI.
Ok for trunk?
Thanks,
Stam Markianos-Wright
gcc/ChangeLog:
* config/arm/arm_mve.h (__arm_vadcq_s32): Fix arithmetic.
(__arm_vadcq_u32): Likewise.
(__arm_vadcq_m_s32): Likewise.
(__arm_vadcq_m_u32): Likewise.
(__arm_vsbcq_s32): Likewise.
(__arm_vsbcq_u32): Likewise.
(__arm_vsbcq_m_s32): Likewise.
(__arm_vsbcq_m_u32): Likewise.
---
gcc/config/arm/arm_mve.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 1262d668121..8778216304b 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -16055,7 +16055,7 @@ __extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vadcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry)
{
- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
int32x4_t __res = __builtin_mve_vadcq_sv4si (__a, __b);
*__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
return __res;
@@ -16065,7 +16065,7 @@ __extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vadcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry)
{
- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
uint32x4_t __res = __builtin_mve_vadcq_uv4si (__a, __b);
*__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
return __res;
@@ -16075,7 +16075,7 @@ __extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vadcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry, mve_pred16_t __p)
{
- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
int32x4_t __res = __builtin_mve_vadcq_m_sv4si (__inactive, __a, __b, __p);
*__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
return __res;
@@ -16085,7 +16085,7 @@ __extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vadcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry, mve_pred16_t __p)
{
- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
uint32x4_t __res = __builtin_mve_vadcq_m_uv4si (__inactive, __a, __b, __p);
*__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
return __res;
@@ -16131,7 +16131,7 @@ __extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vsbcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry)
{
- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
int32x4_t __res = __builtin_mve_vsbcq_sv4si (__a, __b);
*__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
return __res;
@@ -16141,7 +16141,7 @@ __extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vsbcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry)
{
- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
uint32x4_t __res = __builtin_mve_vsbcq_uv4si (__a, __b);
*__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
return __res;
@@ -16151,7 +16151,7 @@ __extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vsbcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry, mve_pred16_t __p)
{
- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
int32x4_t __res = __builtin_mve_vsbcq_m_sv4si (__inactive, __a, __b, __p);
*__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
return __res;
@@ -16161,7 +16161,7 @@ __extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vsbcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry, mve_pred16_t __p)
{
- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
uint32x4_t __res = __builtin_mve_vsbcq_m_uv4si (__inactive, __a, __b, __p);
*__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
return __res;
--
2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 05/10] arm: Add vorrq_n overloading into vorrq _Generic
2023-04-28 11:29 [PATCH 01/10] arm: Mve testsuite improvements Andrea Corallo
` (2 preceding siblings ...)
2023-04-28 11:29 ` [PATCH 04/10] arm: Stop vadcq, vsbcq intrinsics from overwriting the FPSCR NZ flags Andrea Corallo
@ 2023-04-28 11:29 ` Andrea Corallo
2023-04-28 16:47 ` Kyrylo Tkachov
2023-04-28 11:29 ` [PATCH 06/10] arm: Fix overloading of MVE scalar constant parameters on vbicq, vmvnq_m Andrea Corallo
` (5 subsequent siblings)
9 siblings, 1 reply; 31+ messages in thread
From: Andrea Corallo @ 2023-04-28 11:29 UTC (permalink / raw)
To: gcc-patches; +Cc: kyrylo.tkachov, Richard.Earnshaw, Stam Markianos-Wright
From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
We found this as part of the wider testsuite updates.
The applicable tests are authored by Andrea earlier in this patch series
Ok for trunk?
gcc/ChangeLog:
* config/arm/arm_mve.h (__arm_vorrq): Add _n variant.
---
gcc/config/arm/arm_mve.h | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 8778216304b..3d386f320c3 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -35852,6 +35852,10 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vorrq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vorrq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));})
@@ -38637,7 +38641,11 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vorrq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));})
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
#define __arm_vornq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
--
2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 06/10] arm: Fix overloading of MVE scalar constant parameters on vbicq, vmvnq_m
2023-04-28 11:29 [PATCH 01/10] arm: Mve testsuite improvements Andrea Corallo
` (3 preceding siblings ...)
2023-04-28 11:29 ` [PATCH 05/10] arm: Add vorrq_n overloading into vorrq _Generic Andrea Corallo
@ 2023-04-28 11:29 ` Andrea Corallo
2023-04-28 16:47 ` Kyrylo Tkachov
2023-04-28 11:29 ` [PATCH 07/10] arm: Fix MVE header pointer overloads this time (and a bit more tidying) Andrea Corallo
` (4 subsequent siblings)
9 siblings, 1 reply; 31+ messages in thread
From: Andrea Corallo @ 2023-04-28 11:29 UTC (permalink / raw)
To: gcc-patches; +Cc: kyrylo.tkachov, Richard.Earnshaw, Stam Markianos-Wright
From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
We found this as part of the wider testsuite updates.
The applicable tests are authored by Andrea earlier in this patch series
Ok for trunk?
gcc/ChangeLog:
* config/arm/arm_mve.h (__arm_vbicq): Change coerce on
scalar constant.
(__arm_vmvnq_m): Likewise.
---
gcc/config/arm/arm_mve.h | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 3d386f320c3..3a1cffb4063 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -35906,10 +35906,10 @@ extern void *__ARM_undef;
#define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1 (__p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1 (__p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1 (__p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1 (__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3 (p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3 (p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3 (p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3 (p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38825,10 +38825,10 @@ extern void *__ARM_undef;
#define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1 (__p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1 (__p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1 (__p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1 (__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3 (p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3 (p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3 (p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3 (p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -40962,10 +40962,10 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmvnq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmvnq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmvnq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1(__p1, int) , p2), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1(__p1, int) , p2));})
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int) , p2), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int) , p2), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int) , p2), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int) , p2));})
#define __arm_vorrq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
--
2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 07/10] arm: Fix MVE header pointer overloads this time (and a bit more tidying)
2023-04-28 11:29 [PATCH 01/10] arm: Mve testsuite improvements Andrea Corallo
` (4 preceding siblings ...)
2023-04-28 11:29 ` [PATCH 06/10] arm: Fix overloading of MVE scalar constant parameters on vbicq, vmvnq_m Andrea Corallo
@ 2023-04-28 11:29 ` Andrea Corallo
2023-04-28 16:51 ` Kyrylo Tkachov
2023-04-28 11:30 ` [PATCH 08/10] arm testsuite: Remove reduntant tests Andrea Corallo
` (3 subsequent siblings)
9 siblings, 1 reply; 31+ messages in thread
From: Andrea Corallo @ 2023-04-28 11:29 UTC (permalink / raw)
To: gcc-patches; +Cc: kyrylo.tkachov, Richard.Earnshaw, Stam Markianos-Wright
From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Hi all,
Previously we had fixed the overloading of scalar arguments to intrinsics
with the introduction of a new `__ARM_mve_coerce3` _ Generic association.
This allowed users to give types other than int32_t, e.g. int, short, long,
etc., which previously would emit a nonsensical error message from the
_Generic.
Here I adjust that handling slightly and I am also doing the same thing, but
for pointer types:
(un)signed char* can be now used instead of (u)int8_t*
(un)signed short* can be now used instead of (u)int16_t*
(un)signed int* and long* can be now used instead of (u)int32_t*
(un)signed long long* can be now used instead of (u)int64_t*
__fp16* and _Float16* can be now used instead of float16_t*
float* can be now used instead of float32_t*
This required me to break down the _coerce_ generics for the specific
pointer types.
On the scalar types, the change in this patch is minor, renaming the
_coerce_ generics and passing all scalars through the `__typeof` for
consistency with each-other.
No test regressions in the GCC testsuite or CMSIS-NN.
* config/arm/arm_mve.h: (__ARM_mve_typeid): Add more pointer types.
(__ARM_mve_coerce1): Remove.
(__ARM_mve_coerce2): Remove.
(__ARM_mve_coerce3): Remove.
(__ARM_mve_coerce_i_scalar): New.
(__ARM_mve_coerce_s8_ptr): New.
(__ARM_mve_coerce_u8_ptr): New.
(__ARM_mve_coerce_s16_ptr): New.
(__ARM_mve_coerce_u16_ptr): New.
(__ARM_mve_coerce_s32_ptr): New.
(__ARM_mve_coerce_u32_ptr): New.
(__ARM_mve_coerce_s64_ptr): New.
(__ARM_mve_coerce_u64_ptr): New.
(__ARM_mve_coerce_f_scalar): New.
(__ARM_mve_coerce_f16_ptr): New.
(__ARM_mve_coerce_f32_ptr): New.
(__arm_vst4q): Change _coerce_ overloads.
(__arm_vbicq): Change _coerce_ overloads.
(__arm_vmulq): Change _coerce_ overloads.
(__arm_vcmpeqq): Change _coerce_ overloads.
(__arm_vcmpneq): Change _coerce_ overloads.
(__arm_vmaxnmavq): Change _coerce_ overloads.
(__arm_vmaxnmvq): Change _coerce_ overloads.
(__arm_vminnmavq): Change _coerce_ overloads.
(__arm_vsubq): Change _coerce_ overloads.
(__arm_vminnmvq): Change _coerce_ overloads.
(__arm_vrshlq): Change _coerce_ overloads.
(__arm_vqsubq): Change _coerce_ overloads.
(__arm_vqdmulltq): Change _coerce_ overloads.
(__arm_vqdmullbq): Change _coerce_ overloads.
(__arm_vqdmulhq): Change _coerce_ overloads.
(__arm_vqaddq): Change _coerce_ overloads.
(__arm_vhaddq): Change _coerce_ overloads.
(__arm_vhsubq): Change _coerce_ overloads.
(__arm_vqdmlashq): Change _coerce_ overloads.
(__arm_vqrdmlahq): Change _coerce_ overloads.
(__arm_vmlasq): Change _coerce_ overloads.
(__arm_vqdmlahq): Change _coerce_ overloads.
(__arm_vmaxnmavq_p): Change _coerce_ overloads.
(__arm_vmaxnmvq_p): Change _coerce_ overloads.
(__arm_vminnmavq_p): Change _coerce_ overloads.
(__arm_vminnmvq_p): Change _coerce_ overloads.
(__arm_vfmasq_m): Change _coerce_ overloads.
(__arm_vld1q): Change _coerce_ overloads.
(__arm_vld1q_z): Change _coerce_ overloads.
(__arm_vld2q): Change _coerce_ overloads.
(__arm_vld4q): Change _coerce_ overloads.
(__arm_vldrhq_gather_offset): Change _coerce_ overloads.
(__arm_vldrhq_gather_offset_z): Change _coerce_ overloads.
(__arm_vldrhq_gather_shifted_offset): Change _coerce_ overloads.
(__arm_vldrhq_gather_shifted_offset_z): Change _coerce_ overloads.
(__arm_vldrwq_gather_offset): Change _coerce_ overloads.
(__arm_vldrwq_gather_offset_z): Change _coerce_ overloads.
(__arm_vldrwq_gather_shifted_offset): Change _coerce_ overloads.
(__arm_vldrwq_gather_shifted_offset_z): Change _coerce_ overloads.
(__arm_vst1q_p): Change _coerce_ overloads.
(__arm_vst2q): Change _coerce_ overloads.
(__arm_vst1q): Change _coerce_ overloads.
(__arm_vstrhq): Change _coerce_ overloads.
(__arm_vstrhq_p): Change _coerce_ overloads.
(__arm_vstrhq_scatter_offset_p): Change _coerce_ overloads.
(__arm_vstrhq_scatter_offset): Change _coerce_ overloads.
(__arm_vstrhq_scatter_shifted_offset_p): Change _coerce_ overloads.
(__arm_vstrhq_scatter_shifted_offset): Change _coerce_ overloads.
(__arm_vstrwq_p): Change _coerce_ overloads.
(__arm_vstrwq): Change _coerce_ overloads.
(__arm_vstrwq_scatter_offset): Change _coerce_ overloads.
(__arm_vstrwq_scatter_offset_p): Change _coerce_ overloads.
(__arm_vstrwq_scatter_shifted_offset): Change _coerce_ overloads.
(__arm_vstrwq_scatter_shifted_offset_p): Change _coerce_ overloads.
(__arm_vsetq_lane): Change _coerce_ overloads.
(__arm_vcmpneq_m): Change _coerce_ overloads.
(__arm_vldrbq_gather_offset): Change _coerce_ overloads.
(__arm_vdwdupq_x_u8): Change _coerce_ overloads.
(__arm_vdwdupq_x_u16): Change _coerce_ overloads.
(__arm_vdwdupq_x_u32): Change _coerce_ overloads.
(__arm_viwdupq_x_u8): Change _coerce_ overloads.
(__arm_viwdupq_x_u16): Change _coerce_ overloads.
(__arm_viwdupq_x_u32): Change _coerce_ overloads.
(__arm_vidupq_x_u8): Change _coerce_ overloads.
(__arm_vddupq_x_u8): Change _coerce_ overloads.
(__arm_vidupq_x_u16): Change _coerce_ overloads.
(__arm_vddupq_x_u16): Change _coerce_ overloads.
(__arm_vidupq_x_u32): Change _coerce_ overloads.
(__arm_vddupq_x_u32): Change _coerce_ overloads.
(__arm_vhaddq_x): Change _coerce_ overloads.
(__arm_vhsubq_x): Change _coerce_ overloads.
(__arm_vldrdq_gather_offset): Change _coerce_ overloads.
(__arm_vldrdq_gather_offset_z): Change _coerce_ overloads.
(__arm_vldrdq_gather_shifted_offset): Change _coerce_ overloads.
(__arm_vldrdq_gather_shifted_offset_z): Change _coerce_ overloads.
(__arm_vldrbq_gather_offset_z): Change _coerce_ overloads.
(__arm_vqrdmlahq_m): Change _coerce_ overloads.
(__arm_vqrdmlashq_m): Change _coerce_ overloads.
(__arm_vqdmlashq_m): Change _coerce_ overloads.
(__arm_vmlaldavaxq_p): Change _coerce_ overloads.
(__arm_vmlasq_m): Change _coerce_ overloads.
(__arm_vqdmulhq_m): Change _coerce_ overloads.
(__arm_vqdmulltq_m): Change _coerce_ overloads.
(__arm_vidupq_u16): Change _coerce_ overloads.
(__arm_vidupq_u32): Change _coerce_ overloads.
(__arm_vidupq_u8): Change _coerce_ overloads.
(__arm_vddupq_u16): Change _coerce_ overloads.
(__arm_vddupq_u32): Change _coerce_ overloads.
(__arm_vddupq_u8): Change _coerce_ overloads.
(__arm_viwdupq_m): Change _coerce_ overloads.
(__arm_viwdupq_u16): Change _coerce_ overloads.
(__arm_viwdupq_u32): Change _coerce_ overloads.
(__arm_viwdupq_u8): Change _coerce_ overloads.
(__arm_vdwdupq_m): Change _coerce_ overloads.
(__arm_vdwdupq_u16): Change _coerce_ overloads.
(__arm_vdwdupq_u32): Change _coerce_ overloads.
(__arm_vdwdupq_u8): Change _coerce_ overloads.
(__arm_vaddlvaq): Change _coerce_ overloads.
(__arm_vaddlvaq_p): Change _coerce_ overloads.
(__arm_vaddvaq): Change _coerce_ overloads.
(__arm_vaddvaq_p): Change _coerce_ overloads.
(__arm_vcmphiq_m): Change _coerce_ overloads.
(__arm_vmladavaq_p): Change _coerce_ overloads.
(__arm_vmladavaxq): Change _coerce_ overloads.
(__arm_vmlaldavaxq): Change _coerce_ overloads.
(__arm_vstrbq): Change _coerce_ overloads.
(__arm_vstrbq_p): Change _coerce_ overloads.
(__arm_vrmlaldavhaq_p): Change _coerce_ overloads.
(__arm_vstrbq_scatter_offset): Change _coerce_ overloads.
(__arm_vstrbq_scatter_offset_p): Change _coerce_ overloads.
(__arm_vstrdq_scatter_offset_p): Change _coerce_ overloads.
(__arm_vstrdq_scatter_offset): Change _coerce_ overloads.
(__arm_vstrdq_scatter_shifted_offset_p): Change _coerce_ overloads.
(__arm_vstrdq_scatter_shifted_offset): Change _coerce_ overloads.
gcc/testsuite/ChangeLog:
* gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c: Add testcases.
* gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: Add testcases.
---
gcc/config/arm/arm_mve.h | 2056 +++++++++--------
.../mve_intrinsic_type_overloads-fp.c | 55 +-
.../mve_intrinsic_type_overloads-int.c | 74 +-
3 files changed, 1148 insertions(+), 1037 deletions(-)
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 3a1cffb4063..71ea3ee275e 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -35582,16 +35582,29 @@ enum {
short: __ARM_mve_type_int_n, \
int: __ARM_mve_type_int_n, \
long: __ARM_mve_type_int_n, \
+ long long: __ARM_mve_type_int_n, \
_Float16: __ARM_mve_type_fp_n, \
__fp16: __ARM_mve_type_fp_n, \
float: __ARM_mve_type_fp_n, \
double: __ARM_mve_type_fp_n, \
- long long: __ARM_mve_type_int_n, \
unsigned char: __ARM_mve_type_int_n, \
unsigned short: __ARM_mve_type_int_n, \
unsigned int: __ARM_mve_type_int_n, \
unsigned long: __ARM_mve_type_int_n, \
unsigned long long: __ARM_mve_type_int_n, \
+ signed char*: __ARM_mve_type_int8_t_ptr, \
+ short*: __ARM_mve_type_int16_t_ptr, \
+ int*: __ARM_mve_type_int32_t_ptr, \
+ long*: __ARM_mve_type_int32_t_ptr, \
+ long long*: __ARM_mve_type_int64_t_ptr, \
+ _Float16*: __ARM_mve_type_float16_t_ptr, \
+ __fp16*: __ARM_mve_type_float16_t_ptr, \
+ float*: __ARM_mve_type_float32_t_ptr, \
+ unsigned char*: __ARM_mve_type_uint8_t_ptr, \
+ unsigned short*: __ARM_mve_type_uint16_t_ptr, \
+ unsigned int*: __ARM_mve_type_uint32_t_ptr, \
+ unsigned long*: __ARM_mve_type_uint32_t_ptr, \
+ unsigned long long*: __ARM_mve_type_uint64_t_ptr, \
default: __ARM_mve_unsupported_type))
#else
#define __ARM_mve_typeid(x) _Generic(x, \
@@ -35650,32 +35663,67 @@ enum {
unsigned int: __ARM_mve_type_int_n, \
unsigned long: __ARM_mve_type_int_n, \
unsigned long long: __ARM_mve_type_int_n, \
+ signed char*: __ARM_mve_type_int8_t_ptr, \
+ short*: __ARM_mve_type_int16_t_ptr, \
+ int*: __ARM_mve_type_int32_t_ptr, \
+ long*: __ARM_mve_type_int32_t_ptr, \
+ long long*: __ARM_mve_type_int64_t_ptr, \
+ unsigned char*: __ARM_mve_type_uint8_t_ptr, \
+ unsigned short*: __ARM_mve_type_uint16_t_ptr, \
+ unsigned int*: __ARM_mve_type_uint32_t_ptr, \
+ unsigned long*: __ARM_mve_type_uint32_t_ptr, \
+ unsigned long long*: __ARM_mve_type_uint64_t_ptr, \
default: __ARM_mve_unsupported_type))
#endif /* MVE Floating point. */
extern void *__ARM_undef;
#define __ARM_mve_coerce(param, type) \
_Generic(param, type: param, default: *(type *)__ARM_undef)
-#define __ARM_mve_coerce1(param, type) \
- _Generic(param, type: param, const type: param, default: *(type *)__ARM_undef)
-#define __ARM_mve_coerce2(param, type) \
- _Generic(param, type: param, __fp16: param, default: _Generic (param, _Float16: param, float16_t: param, float32_t: param, default: *(type *)__ARM_undef))
-#define __ARM_mve_coerce3(param, type) \
- _Generic(param, type: param, default: _Generic (param, int8_t: param, int16_t: param, int32_t: param, int64_t: param, uint8_t: param, uint16_t: param, uint32_t: param, uint64_t: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_i_scalar(param, type) \
+ _Generic(param, type: param, const type: param, default: _Generic (param, int8_t: param, int16_t: param, int32_t: param, int64_t: param, uint8_t: param, uint16_t: param, uint32_t: param, uint64_t: param, default: *(type *)__ARM_undef))
+
+#define __ARM_mve_coerce_s8_ptr(param, type) \
+ _Generic(param, type: param, const type: param, default: _Generic (param, signed char*: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_u8_ptr(param, type) \
+ _Generic(param, type: param, const type: param, default: _Generic (param, unsigned char*: param, default: *(type *)__ARM_undef))
+
+#define __ARM_mve_coerce_s16_ptr(param, type) \
+ _Generic(param, type: param, const type: param, default: _Generic (param, short*: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_u16_ptr(param, type) \
+ _Generic(param, type: param, const type: param, default: _Generic (param, unsigned short*: param, default: *(type *)__ARM_undef))
+
+#define __ARM_mve_coerce_s32_ptr(param, type) \
+ _Generic(param, type: param, const type: param, default: _Generic (param, int*: param, long*: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_u32_ptr(param, type) \
+ _Generic(param, type: param, const type: param, default: _Generic (param, unsigned int*: param, unsigned long*: param, default: *(type *)__ARM_undef))
+
+#define __ARM_mve_coerce_s64_ptr(param, type) \
+ _Generic(param, type: param, const type: param, default: _Generic (param, long long*: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_u64_ptr(param, type) \
+ _Generic(param, type: param, const type: param, default: _Generic (param, unsigned long long*: param, default: *(type *)__ARM_undef))
+
+#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */
+#define __ARM_mve_coerce_f_scalar(param, type) \
+ _Generic(param, type: param, const type: param, __fp16: param, default: _Generic (param, _Float16: param, float16_t: param, float32_t: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_f16_ptr(param, type) \
+ _Generic(param, type: param, const type: param, default: _Generic (param, __fp16*: param, _Float16*: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_f32_ptr(param, type) \
+ _Generic(param, type: param, const type: param, default: _Generic (param, float*: param, default: *(type *)__ARM_undef))
+#endif
#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */
#define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)), \
- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));})
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce_s16_ptr(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce_u16_ptr(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)), \
+ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce_f16_ptr(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \
+ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));})
#define __arm_vrndxq(p0) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -35852,10 +35900,10 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vorrq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vorrq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));})
@@ -35882,14 +35930,14 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));})
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));})
#define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -35906,10 +35954,10 @@ extern void *__ARM_undef;
#define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3 (p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3 (p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3 (p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3 (p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -35934,14 +35982,14 @@ extern void *__ARM_undef;
#define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -35966,14 +36014,14 @@ extern void *__ARM_undef;
#define __arm_vcmpeqq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpeqq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpeqq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpeqq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36004,16 +36052,16 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpeqq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpeqq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));})
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));})
#define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -36021,13 +36069,13 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));})
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));})
#define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -36037,11 +36085,11 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpleq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpleq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));})
#define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -36049,25 +36097,25 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));})
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));})
#define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36122,8 +36170,8 @@ extern void *__ARM_undef;
#define __arm_vmaxnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
#define __arm_vmaxnmq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -36134,14 +36182,14 @@ extern void *__ARM_undef;
#define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
#define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
#define __arm_vminnmaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -36152,8 +36200,8 @@ extern void *__ARM_undef;
#define __arm_vminnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
#define __arm_vbrsrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -36175,14 +36223,14 @@ extern void *__ARM_undef;
#define __arm_vsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36195,8 +36243,8 @@ extern void *__ARM_undef;
#define __arm_vminnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
#define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -36251,12 +36299,12 @@ extern void *__ARM_undef;
#define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36287,12 +36335,12 @@ extern void *__ARM_undef;
#define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36343,12 +36391,12 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
#define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -36356,9 +36404,9 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
#define __arm_vmlaldavxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -36391,8 +36439,8 @@ extern void *__ARM_undef;
#define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
@@ -36405,17 +36453,17 @@ extern void *__ARM_undef;
#define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
#define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
@@ -36423,12 +36471,12 @@ extern void *__ARM_undef;
#define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36461,12 +36509,12 @@ extern void *__ARM_undef;
#define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36491,12 +36539,12 @@ extern void *__ARM_undef;
#define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36639,12 +36687,12 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
#define __arm_vsriq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -36723,44 +36771,44 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
#define __arm_vqdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
#define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
#define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
#define __arm_vqdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
#define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -36950,11 +36998,11 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));})
@@ -36966,11 +37014,11 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpleq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpleq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));})
#define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -36980,11 +37028,11 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));})
#define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -36997,14 +37045,14 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpneq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpneq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));})
#define __arm_vcvtbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -37058,8 +37106,8 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double)), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double)), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double)), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double)), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));})
@@ -37074,8 +37122,8 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double)), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double)));})
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double)), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double)));})
#define __arm_vmaxnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -37098,14 +37146,14 @@ extern void *__ARM_undef;
#define __arm_vmaxnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
#define __arm_vmaxnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
#define __arm_vminnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -37116,14 +37164,14 @@ extern void *__ARM_undef;
#define __arm_vminnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
#define __arm_vminnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
#define __arm_vrndnq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -37185,13 +37233,13 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));})
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));})
#define __arm_vrshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -37292,11 +37340,11 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));})
@@ -37325,14 +37373,14 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
#define __arm_vandq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -37473,15 +37521,15 @@ extern void *__ARM_undef;
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmaq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmaq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
#define __arm_vfmasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
#define __arm_vfmsq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -37516,14 +37564,14 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
#define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -37550,14 +37598,14 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
#define __arm_vorrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -37574,236 +37622,236 @@ extern void *__ARM_undef;
#define __arm_vld1q(p0) (\
_Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \
- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \
- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \
- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \
- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \
- int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \
- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce1(p0, float32_t *))))
+ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
+ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
+ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \
+ int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \
+ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *))))
#define __arm_vld1q_z(p0,p1) ( \
_Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce1(p0, int8_t *), p1), \
- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce1(p0, int16_t *), p1), \
- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \
- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), p1), \
- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), p1), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \
- int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce1(p0, float16_t *), p1), \
- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1)))
+ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), p1), \
+ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), p1), \
+ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \
+ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), p1), \
+ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), p1), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \
+ int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), p1), \
+ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1)))
#define __arm_vld2q(p0) ( \
_Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \
- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \
- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \
- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \
- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \
- int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld2q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \
- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld2q_f32 (__ARM_mve_coerce1(p0, float32_t *))))
+ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
+ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
+ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \
+ int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld2q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \
+ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld2q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *))))
#define __arm_vld4q(p0) ( \
_Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \
- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \
- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \
- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \
- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \
- int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld4q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \
- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld4q_f32 (__ARM_mve_coerce1(p0, float32_t *))))
+ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
+ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
+ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \
+ int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld4q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \
+ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld4q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *))))
#define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));})
#define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));})
#define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));})
#define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));})
#define __arm_vldrwq_gather_offset(p0,p1) ( \
_Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \
- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_f32 (__ARM_mve_coerce1(p0, float32_t *), p1)))
+ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \
+ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1)))
#define __arm_vldrwq_gather_offset_z(p0,p1,p2) ( \
_Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1, p2), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1, p2), \
- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1, p2)))
+ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1, p2), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1, p2), \
+ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_z_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1, p2)))
#define __arm_vldrwq_gather_shifted_offset(p0,p1) ( \
_Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \
- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_f32 (__ARM_mve_coerce1(p0, float32_t *), p1)))
+ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \
+ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1)))
#define __arm_vldrwq_gather_shifted_offset_z(p0,p1,p2) ( \
_Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1, p2), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1, p2), \
- int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1, p2)))
+ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1, p2), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1, p2), \
+ int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1, p2)))
#define __arm_vst1q_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_p_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));})
#define __arm_vst2q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)), \
- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x2_t]: __arm_vst2q_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x2_t)), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x2_t]: __arm_vst2q_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x2_t)));})
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)), \
+ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x2_t]: __arm_vst2q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x2_t)), \
+ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x2_t]: __arm_vst2q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x2_t)));})
#define __arm_vst1q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));})
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));})
#define __arm_vstrhq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)));})
#define __arm_vstrhq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2));})
#define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
#define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
+ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
#define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
#define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
+ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
#define __arm_vstrwq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_p_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));})
#define __arm_vstrwq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));})
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));})
#define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
+ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
#define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
#define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
+ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
#define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
#define __arm_vstrwq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
@@ -37820,44 +37868,44 @@ extern void *__ARM_undef;
#define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t)));})
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
+ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t)));})
#define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
#define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));})
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
+ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));})
#define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
#define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
#define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));})
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
+ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));})
#define __arm_vuninitializedq(p0) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -38030,19 +38078,19 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
#define __arm_vandq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
@@ -38165,19 +38213,19 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
#define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
@@ -38266,19 +38314,19 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));})
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
#define __arm_vcmulq_rot90_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
@@ -38302,16 +38350,16 @@ extern void *__ARM_undef;
#define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2), \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vsetq_lane_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
- int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vsetq_lane_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2), \
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vsetq_lane_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+ int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vsetq_lane_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
#else /* MVE Integer. */
@@ -38327,12 +38375,12 @@ extern void *__ARM_undef;
#define __arm_vst4q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)));})
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)));})
#define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -38429,12 +38477,12 @@ extern void *__ARM_undef;
#define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38461,12 +38509,12 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
#define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -38480,12 +38528,12 @@ extern void *__ARM_undef;
#define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38516,12 +38564,12 @@ extern void *__ARM_undef;
#define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38590,12 +38638,12 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
#define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -38603,16 +38651,16 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
#define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
@@ -38620,12 +38668,12 @@ extern void *__ARM_undef;
#define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38642,10 +38690,10 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
#define __arm_vornq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -38660,12 +38708,12 @@ extern void *__ARM_undef;
#define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38740,12 +38788,12 @@ extern void *__ARM_undef;
#define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38770,12 +38818,12 @@ extern void *__ARM_undef;
#define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38825,10 +38873,10 @@ extern void *__ARM_undef;
#define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3 (p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3 (p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3 (p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3 (p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38845,12 +38893,12 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
#define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -38881,12 +38929,12 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
#define __arm_vqmovntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -38967,16 +39015,16 @@ extern void *__ARM_undef;
#define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
#define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
@@ -38986,9 +39034,9 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
#define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -38996,9 +39044,9 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
#define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -39006,9 +39054,9 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
#define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -39016,20 +39064,20 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
#define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
@@ -39054,12 +39102,12 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
#define __arm_vbicq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -39169,25 +39217,25 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
#define __arm_vqdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
#define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
#define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -39250,9 +39298,9 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
#define __arm_vcmpgtq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
@@ -39261,9 +39309,9 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
#define __arm_vcmpleq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -39271,9 +39319,9 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
#define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -39281,9 +39329,9 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
#define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -39294,12 +39342,12 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpneq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
#define __arm_vdupq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -39322,23 +39370,23 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
#define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
#define __arm_vnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -39363,9 +39411,9 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
#define __arm_vqdmlsdhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -39528,12 +39576,12 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -39633,12 +39681,12 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
#define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -39666,12 +39714,12 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -39683,12 +39731,12 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -39703,12 +39751,12 @@ extern void *__ARM_undef;
#define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
#define __arm_vstrwq_scatter_base_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
@@ -39717,144 +39765,144 @@ extern void *__ARM_undef;
#define __arm_vld1q(p0) (\
_Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \
- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \
- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \
- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \
- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce1(p0, uint32_t *))))
+ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
+ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
+ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *))))
#define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
#define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
#define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
#define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
#define __arm_vldrwq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1));})
+ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
#define __arm_vldrwq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1, p2), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1, p2));})
+ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, p2), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
#define __arm_vldrwq_gather_shifted_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1));})
+ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
#define __arm_vldrwq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1, p2), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1, p2));})
+ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, p2), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
#define __arm_vst1q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
#define __arm_vst1q_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
#define __arm_vst2q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)));})
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)));})
#define __arm_vstrhq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
#define __arm_vstrhq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
#define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
#define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
#define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
#define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
#define __arm_vstrwq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
#define __arm_vstrwq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
#define __arm_vstrdq_scatter_base_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
@@ -39869,58 +39917,58 @@ extern void *__ARM_undef;
#define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
#define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
#define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
#define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
- int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
- int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
#define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)));})
#define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
#define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)));})
#define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
#define __arm_vuninitializedq(p0) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -40025,15 +40073,15 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
#define __arm_vcaddq_rot270_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
@@ -40127,15 +40175,15 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
#define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
@@ -40219,29 +40267,29 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3));})
#define __arm_vld1q_z(p0,p1) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce1(p0, int8_t *), p1), \
- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce1(p0, int16_t *), p1), \
- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \
- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), p1), \
- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), p1), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1)))
+ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), p1), \
+ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), p1), \
+ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \
+ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), p1), \
+ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), p1), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1)))
#define __arm_vld2q(p0) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \
- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \
- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \
- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \
- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce1(p0, uint32_t *))))
+ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
+ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
+ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *))))
#define __arm_vld4q(p0) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \
- int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \
- int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \
- int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \
- int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce1(p0, uint32_t *))))
+ int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
+ int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
+ int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
+ int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *))))
#define __arm_vsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
@@ -40249,15 +40297,15 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
#define __arm_vgetq_lane(p0,p1) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -40273,14 +40321,14 @@ extern void *__ARM_undef;
#define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2));})
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2));})
#endif /* MVE Integer. */
@@ -40391,62 +40439,62 @@ extern void *__ARM_undef;
#define __arm_vdwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u8 ((uint32_t) __p1, p2, p3, p4), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
#define __arm_vdwdupq_x_u16(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u16 ((uint32_t) __p1, p2, p3, p4), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
#define __arm_vdwdupq_x_u32(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u32 ((uint32_t) __p1, p2, p3, p4), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
#define __arm_viwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u8 ((uint32_t) __p1, p2, p3, p4), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
#define __arm_viwdupq_x_u16(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u16 ((uint32_t) __p1, p2, p3, p4), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
#define __arm_viwdupq_x_u32(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u32 ((uint32_t) __p1, p2, p3, p4), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
#define __arm_vidupq_x_u8(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u8 ((uint32_t) __p1, p2, p3), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
#define __arm_vddupq_x_u8(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u8 ((uint32_t) __p1, p2, p3), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
#define __arm_vidupq_x_u16(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u16 ((uint32_t) __p1, p2, p3), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
#define __arm_vddupq_x_u16(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u16 ((uint32_t) __p1, p2, p3), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
#define __arm_vidupq_x_u32(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u32 ((uint32_t) __p1, p2, p3), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
#define __arm_vddupq_x_u32(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u32 ((uint32_t) __p1, p2, p3), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
#define __arm_vshrq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
@@ -40460,12 +40508,12 @@ extern void *__ARM_undef;
#define __arm_vhaddq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -40490,12 +40538,12 @@ extern void *__ARM_undef;
#define __arm_vhsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -40535,20 +40583,20 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_base_wb_u64 (p0, p1, __ARM_mve_coerce(__p2, uint64x2_t)));})
#define __arm_vldrdq_gather_offset(p0,p1) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
- int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_s64 (__ARM_mve_coerce1(p0, int64_t *), p1), \
- int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1)))
+ int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1), \
+ int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1)))
#define __arm_vldrdq_gather_offset_z(p0,p1,p2) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
- int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_z_s64 (__ARM_mve_coerce1(p0, int64_t *), p1, p2), \
- int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_z_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1, p2)))
+ int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_z_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1, p2), \
+ int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_z_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1, p2)))
#define __arm_vldrdq_gather_shifted_offset(p0,p1) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
- int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_s64 (__ARM_mve_coerce1(p0, int64_t *), p1), \
- int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1)))
+ int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1), \
+ int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1)))
#define __arm_vldrdq_gather_shifted_offset_z(p0,p1,p2) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
- int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_s64 (__ARM_mve_coerce1(p0, int64_t *), p1, p2), \
- int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1, p2)))
+ int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1, p2), \
+ int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1, p2)))
#define __arm_vadciq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -40604,36 +40652,36 @@ extern void *__ARM_undef;
#define __arm_vldrbq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_s8 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
#define __arm_vqrdmlahq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
#define __arm_vqrdmlashq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
#define __arm_vqdmlashq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
#define __arm_vqrshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -40734,12 +40782,12 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -40754,9 +40802,9 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
#define __arm_vqrdmlsdhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -40882,17 +40930,17 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_p_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
#define __arm_vmlaldavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
#define __arm_vmlsldavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -40962,10 +41010,10 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmvnq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmvnq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmvnq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int) , p2), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int) , p2), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int) , p2), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int) , p2));})
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2));})
#define __arm_vorrq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -41031,12 +41079,12 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -41070,12 +41118,12 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhsubq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhsubq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
#define __arm_vmaxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -41103,23 +41151,23 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
#define __arm_vmlasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
#define __arm_vmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -41165,12 +41213,12 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -41182,17 +41230,17 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
#define __arm_vqdmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
@@ -41203,15 +41251,15 @@ extern void *__ARM_undef;
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));})
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
#define __arm_vqdmulltq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
- int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+ int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
@@ -41277,9 +41325,9 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_p_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
#define __arm_vmullbq_poly_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -41290,12 +41338,12 @@ extern void *__ARM_undef;
#define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8(__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16(__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32(__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8(__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16(__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32(__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8(__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16(__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32(__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8(__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16(__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32(__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
#define __arm_vidupq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -41303,9 +41351,9 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vidupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), (uint32_t) __p1, p2, p3), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vidupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), (uint32_t) __p1, p2, p3), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vidupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), (uint32_t) __p1, p2, p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
#define __arm_vddupq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -41313,89 +41361,89 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vddupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), (uint32_t) __p1, p2, p3), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vddupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), (uint32_t) __p1, p2, p3), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vddupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), (uint32_t) __p1, p2, p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
#define __arm_vidupq_u16(p0,p1) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u16 ((uint32_t) __p0, p1), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1));})
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
#define __arm_vidupq_u32(p0,p1) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u32 ((uint32_t) __p0, p1), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1));})
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
#define __arm_vidupq_u8(p0,p1) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u8 ((uint32_t) __p0, p1), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1));})
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
#define __arm_vddupq_u16(p0,p1) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u16 ((uint32_t) __p0, p1), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1));})
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
#define __arm_vddupq_u32(p0,p1) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u32 ((uint32_t) __p0, p1), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1));})
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
#define __arm_vddupq_u8(p0,p1) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u8 ((uint32_t) __p0, p1), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1));})
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
#define __arm_viwdupq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
#define __arm_viwdupq_u16(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
- int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u16 (__ARM_mve_coerce3(p0, int), p1, (const int) p2), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1, (const int) p2));})
+ int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u16 (__ARM_mve_coerce_i_scalar(__p0, int), p1, (const int) p2), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, (const int) p2));})
#define __arm_viwdupq_u32(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
- int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u32 (__ARM_mve_coerce3(p0, int), p1, p2), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
+ int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u32 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
#define __arm_viwdupq_u8(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
- int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u8 (__ARM_mve_coerce3(p0, int), p1, p2), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
+ int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u8 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
#define __arm_vdwdupq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2, p3, p4), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
#define __arm_vdwdupq_u16(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
- int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u16 (__ARM_mve_coerce3(p0, int), p1, p2), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
+ int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u16 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
#define __arm_vdwdupq_u32(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
- int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u32 (__ARM_mve_coerce3(p0, int), p1, p2), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
+ int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u32 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
#define __arm_vdwdupq_u8(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
- int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u8 (__ARM_mve_coerce3(p0, int), p1, p2), \
- int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
+ int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u8 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
#define __arm_vshlcq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -41431,14 +41479,14 @@ extern void *__ARM_undef;
#define __arm_vaddlvaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t)));})
#define __arm_vaddlvaq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
#define __arm_vaddlvq(p0) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -41453,22 +41501,22 @@ extern void *__ARM_undef;
#define __arm_vaddvaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t)));})
#define __arm_vaddvaq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_p_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_p_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_p_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_p_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
#define __arm_vaddvq(p0) ({ __typeof(p0) __p0 = (p0); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -41494,9 +41542,9 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpcsq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpcsq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpcsq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));})
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
#define __arm_vcmpcsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -41504,9 +41552,9 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpcsq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpcsq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpcsq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2));})
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
#define __arm_vcmphiq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -41514,16 +41562,16 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmphiq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmphiq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmphiq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));})
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
#define __arm_vcmphiq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmphiq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmphiq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmphiq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
@@ -41620,34 +41668,34 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
#define __arm_vmladavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
#define __arm_vmladavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaxq_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaxq_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaxq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaxq_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaxq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaxq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
#define __arm_vmladavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -41690,17 +41738,17 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
#define __arm_vmlaldavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));})
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));})
#define __arm_vmlaldavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -41864,22 +41912,22 @@ extern void *__ARM_undef;
#define __arm_vstrbq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_s16 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_s32 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_u16 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_u32 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
#define __arm_vstrbq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_p_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_p_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_p_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_p_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_p_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_p_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_p_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_p_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_p_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_p_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_p_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_p_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
#define __arm_vstrdq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
@@ -41895,61 +41943,61 @@ extern void *__ARM_undef;
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
#define __arm_vrmlaldavhaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
#define __arm_vstrbq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
#define __arm_vstrbq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_p_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_p_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
- int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_p_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_p_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
- int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_p_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_p_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_p_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_p_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_p_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_p_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
#define __arm_vstrdq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_p_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \
- int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_p_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));})
+ int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_p_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \
+ int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_p_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));})
#define __arm_vstrdq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \
- int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));})
+ int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \
+ int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));})
#define __arm_vstrdq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \
- int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));})
+ int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \
+ int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));})
#define __arm_vstrdq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \
- int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));})
+ int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \
+ int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));})
#endif /* __cplusplus */
#endif /* __ARM_FEATURE_MVE */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c
index a2787a47859..a1e786ecd9f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c
@@ -1,6 +1,7 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long" } */
+/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -Wno-incompatible-pointer-types" { target c } } */
+/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -fpermissive" { target c++ } } */
#include "arm_mve.h"
float f1;
@@ -10,35 +11,14 @@ float32_t f4;
__fp16 f5;
_Float16 f6;
-int i1;
-short i2;
-long i3;
-long long i4;
-int8_t i5;
-int16_t i6;
-int32_t i7;
-int64_t i8;
-
float16x8_t floatvec;
-int16x8_t intvec;
-void test(void)
+/* Test a few different supported ways of passing a scalar int value.
+The intrinsic vmulq was chosen arbitrarily, but it is representative of
+all intrinsics that take a non-const scalar value. */
+void
+test_scalars (void)
{
- /* Test a few different supported ways of passing an int value. The
- intrinsic vmulq was chosen arbitrarily, but it is representative of
- all intrinsics that take a non-const scalar value. */
- intvec = vmulq(intvec, 2);
- intvec = vmulq(intvec, (int32_t) 2);
- intvec = vmulq(intvec, (short) 2);
- intvec = vmulq(intvec, i1);
- intvec = vmulq(intvec, i2);
- intvec = vmulq(intvec, i3);
- intvec = vmulq(intvec, i4);
- intvec = vmulq(intvec, i5);
- intvec = vmulq(intvec, i6);
- intvec = vmulq(intvec, i7);
- intvec = vmulq(intvec, i8);
-
/* Test a few different supported ways of passing a float value. */
floatvec = vmulq(floatvec, 0.5);
floatvec = vmulq(floatvec, 0.5f);
@@ -53,4 +33,25 @@ void test(void)
floatvec = vmulq(floatvec, (_Float16) 0.15);
}
+/* Next, test a number of valid pointer overloads. */
+void
+foo11 (__fp16 * addr, float16x8_t value)
+{
+ vst1q (addr, value);
+}
+
+#ifndef __cplusplus
+void
+foo12 (_Float16 * addr, float16x8_t value)
+{
+ vst1q (addr, value);
+}
+#endif
+
+void
+foo13 (float * addr, float32x4_t value)
+{
+ vst1q (addr, value);
+}
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c
index 7b88f462e17..7947dc024bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c
@@ -1,7 +1,7 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long" } */
-
+/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -Wno-incompatible-pointer-types" { target c } } */
+/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -fpermissive" { target c++ } } */
#include "arm_mve.h"
int i1;
@@ -15,11 +15,12 @@ int64_t i8;
int16x8_t intvec;
-void test(void)
+/* Test a few different supported ways of passing a scalar int value.
+The intrinsic vmulq was chosen arbitrarily, but it is representative of
+all intrinsics that take a non-const scalar value. */
+void
+test_scalars (void)
{
- /* Test a few different supported ways of passing an int value. The
- intrinsic vmulq was chosen arbitrarily, but it is representative of
- all intrinsics that take a non-const scalar value. */
intvec = vmulq(intvec, 2);
intvec = vmulq(intvec, (int32_t) 2);
intvec = vmulq(intvec, (short) 2);
@@ -33,4 +34,65 @@ void test(void)
intvec = vmulq(intvec, i8);
}
+/* Next, test a number of valid pointer overloads. */
+void
+foo1 (signed char * addr, int8x16_t value)
+{
+ vst1q (addr, value);
+}
+
+void
+foo2 (short * addr, int16x8_t value)
+{
+ vst1q (addr, value);
+}
+
+void
+foo3 (int * addr, int32x4_t value)
+{
+ vst1q (addr, value); /* { dg-warning "invalid conversion" "" { target c++ } } */
+}
+
+void
+foo4 (long * addr, int32x4_t value)
+{
+ vst1q (addr, value);
+}
+
+void
+foo5 (long long * addr, uint64x2_t value)
+{
+ vldrdq_gather_offset (addr, value);
+}
+
+void
+foo6 (unsigned char * addr, uint8x16_t value)
+{
+ vst1q (addr, value);
+}
+
+void
+foo7 (unsigned short * addr, uint16x8_t value)
+{
+ vst1q (addr, value);
+}
+
+void
+foo8 (unsigned int * addr, uint32x4_t value)
+{
+ vst1q (addr, value); /* { dg-warning "invalid conversion" "" { target c++ } } */
+}
+
+void
+foo9 (unsigned long * addr, uint32x4_t value)
+{
+ vst1q (addr, value);
+}
+
+void
+foo10 (unsigned long long * addr, uint64x2_t value)
+{
+ vldrdq_gather_offset (addr, value);
+}
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--
2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 08/10] arm testsuite: Remove reduntant tests
2023-04-28 11:29 [PATCH 01/10] arm: Mve testsuite improvements Andrea Corallo
` (5 preceding siblings ...)
2023-04-28 11:29 ` [PATCH 07/10] arm: Fix MVE header pointer overloads this time (and a bit more tidying) Andrea Corallo
@ 2023-04-28 11:30 ` Andrea Corallo
2023-04-28 16:52 ` Kyrylo Tkachov
2023-04-28 11:30 ` [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests Andrea Corallo
` (2 subsequent siblings)
9 siblings, 1 reply; 31+ messages in thread
From: Andrea Corallo @ 2023-04-28 11:30 UTC (permalink / raw)
To: gcc-patches; +Cc: kyrylo.tkachov, Richard.Earnshaw, Stam Markianos-Wright
From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Following Andrea's overhaul of the MVE testsuite, these tests are now
reduntant, as equivalent checks have been added to the each intrinsic's
<intrinsic name>.c test.
gcc/testsuite/ChangeLog:
* gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vaddq_m.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vaddq_n.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c: Removed.
* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c: Removed.
* gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c: Removed.
* gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c: Removed.
---
.../arm/mve/intrinsics/mve_fp_vaddq_n.c | 47 ------
.../arm/mve/intrinsics/mve_vaddq_m.c | 48 ------
.../arm/mve/intrinsics/mve_vaddq_n.c | 31 ----
.../arm/mve/intrinsics/mve_vddupq_m_n_u16.c | 13 --
.../arm/mve/intrinsics/mve_vddupq_m_n_u32.c | 13 --
.../arm/mve/intrinsics/mve_vddupq_m_n_u8.c | 13 --
.../arm/mve/intrinsics/mve_vddupq_n_u16.c | 13 --
.../arm/mve/intrinsics/mve_vddupq_n_u32.c | 13 --
.../arm/mve/intrinsics/mve_vddupq_n_u8.c | 13 --
.../arm/mve/intrinsics/mve_vddupq_x_n_u16.c | 12 --
.../arm/mve/intrinsics/mve_vddupq_x_n_u32.c | 12 --
.../arm/mve/intrinsics/mve_vddupq_x_n_u8.c | 12 --
.../arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c | 13 --
.../arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c | 13 --
.../arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c | 13 --
.../arm/mve/intrinsics/mve_vidupq_m_n_u16.c | 13 --
.../arm/mve/intrinsics/mve_vidupq_m_n_u32.c | 12 --
.../arm/mve/intrinsics/mve_vidupq_m_n_u8.c | 13 --
.../arm/mve/intrinsics/mve_vidupq_n_u16.c | 13 --
.../arm/mve/intrinsics/mve_vidupq_n_u32.c | 12 --
.../arm/mve/intrinsics/mve_vidupq_n_u8.c | 13 --
.../arm/mve/intrinsics/mve_vidupq_x_n_u16.c | 12 --
.../arm/mve/intrinsics/mve_vidupq_x_n_u32.c | 12 --
.../arm/mve/intrinsics/mve_vidupq_x_n_u8.c | 12 --
.../arm/mve/intrinsics/mve_viwdupq_x_n_u16.c | 13 --
.../arm/mve/intrinsics/mve_viwdupq_x_n_u32.c | 13 --
.../arm/mve/intrinsics/mve_viwdupq_x_n_u8.c | 13 --
.../intrinsics/mve_vldrdq_gather_offset_s64.c | 12 --
.../intrinsics/mve_vldrdq_gather_offset_u64.c | 12 --
.../mve_vldrdq_gather_offset_z_s64.c | 12 --
.../mve_vldrdq_gather_offset_z_u64.c | 12 --
.../mve_vldrdq_gather_shifted_offset_s64.c | 12 --
.../mve_vldrdq_gather_shifted_offset_u64.c | 12 --
.../mve_vldrdq_gather_shifted_offset_z_s64.c | 12 --
.../mve_vldrdq_gather_shifted_offset_z_u64.c | 12 --
.../intrinsics/mve_vldrhq_gather_offset_f16.c | 12 --
.../intrinsics/mve_vldrhq_gather_offset_s16.c | 12 --
.../intrinsics/mve_vldrhq_gather_offset_s32.c | 12 --
.../intrinsics/mve_vldrhq_gather_offset_u16.c | 12 --
.../intrinsics/mve_vldrhq_gather_offset_u32.c | 13 --
.../mve_vldrhq_gather_offset_z_f16.c | 12 --
.../mve_vldrhq_gather_offset_z_s16.c | 12 --
.../mve_vldrhq_gather_offset_z_s32.c | 12 --
.../mve_vldrhq_gather_offset_z_u16.c | 13 --
.../mve_vldrhq_gather_offset_z_u32.c | 13 --
.../mve_vldrhq_gather_shifted_offset_f16.c | 12 --
.../mve_vldrhq_gather_shifted_offset_s16.c | 13 --
.../mve_vldrhq_gather_shifted_offset_s32.c | 13 --
.../mve_vldrhq_gather_shifted_offset_u16.c | 13 --
.../mve_vldrhq_gather_shifted_offset_u32.c | 13 --
.../mve_vldrhq_gather_shifted_offset_z_f16.c | 13 --
.../mve_vldrhq_gather_shifted_offset_z_s16.c | 13 --
.../mve_vldrhq_gather_shifted_offset_z_s32.c | 12 --
.../mve_vldrhq_gather_shifted_offset_z_u16.c | 12 --
.../mve_vldrhq_gather_shifted_offset_z_u32.c | 12 --
.../intrinsics/mve_vldrwq_gather_offset_f32.c | 12 --
.../intrinsics/mve_vldrwq_gather_offset_s32.c | 13 --
.../intrinsics/mve_vldrwq_gather_offset_u32.c | 13 --
.../mve_vldrwq_gather_offset_z_f32.c | 12 --
.../mve_vldrwq_gather_offset_z_s32.c | 13 --
.../mve_vldrwq_gather_offset_z_u32.c | 13 --
.../mve_vldrwq_gather_shifted_offset_f32.c | 12 --
.../mve_vldrwq_gather_shifted_offset_s32.c | 13 --
.../mve_vldrwq_gather_shifted_offset_u32.c | 13 --
.../mve_vldrwq_gather_shifted_offset_z_f32.c | 12 --
.../mve_vldrwq_gather_shifted_offset_z_s32.c | 13 --
.../mve_vldrwq_gather_shifted_offset_z_u32.c | 13 --
.../mve_vstore_scatter_shifted_offset.c | 141 -----------------
.../mve_vstore_scatter_shifted_offset_p.c | 142 ------------------
.../arm/mve/intrinsics/vaddq_m_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vaddq_m_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vaddq_x_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vaddq_x_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vcmpeqq_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vcmpeqq_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vcmpgeq_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vcmpgeq_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vcmpgtq_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vcmpgtq_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vcmpleq_m_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vcmpleq_m_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vcmpleq_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vcmpleq_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vcmpltq_m_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vcmpltq_m_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vcmpltq_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vcmpltq_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vcmpneq_m_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vcmpneq_m_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vcmpneq_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vcmpneq_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vfmaq_m_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vfmaq_m_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vfmaq_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vfmaq_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vfmasq_m_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vfmasq_m_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vfmasq_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vfmasq_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vmaxnmavq_f16-1.c | 12 --
.../arm/mve/intrinsics/vmaxnmavq_f32-1.c | 12 --
.../arm/mve/intrinsics/vmaxnmavq_p_f16-1.c | 12 --
.../arm/mve/intrinsics/vmaxnmavq_p_f32-1.c | 12 --
.../arm/mve/intrinsics/vmaxnmvq_f16-1.c | 12 --
.../arm/mve/intrinsics/vmaxnmvq_f32-1.c | 12 --
.../arm/mve/intrinsics/vmaxnmvq_p_f16-1.c | 12 --
.../arm/mve/intrinsics/vmaxnmvq_p_f32-1.c | 12 --
.../arm/mve/intrinsics/vminnmavq_f16-1.c | 12 --
.../arm/mve/intrinsics/vminnmavq_f32-1.c | 12 --
.../arm/mve/intrinsics/vminnmavq_p_f16-1.c | 12 --
.../arm/mve/intrinsics/vminnmavq_p_f32-1.c | 12 --
.../arm/mve/intrinsics/vminnmvq_f16-1.c | 12 --
.../arm/mve/intrinsics/vminnmvq_f32-1.c | 12 --
.../arm/mve/intrinsics/vminnmvq_p_f16-1.c | 12 --
.../arm/mve/intrinsics/vminnmvq_p_f32-1.c | 12 --
.../arm/mve/intrinsics/vmulq_m_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vmulq_m_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vmulq_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vmulq_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vmulq_x_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vmulq_x_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vsetq_lane_f16-1.c | 13 --
.../arm/mve/intrinsics/vsetq_lane_f32-1.c | 13 --
.../arm/mve/intrinsics/vsubq_m_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vsubq_m_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vsubq_n_f16-1.c | 12 --
.../arm/mve/intrinsics/vsubq_n_f32-1.c | 12 --
.../arm/mve/intrinsics/vsubq_x_n_f16-1.c | 13 --
.../arm/mve/intrinsics/vsubq_x_n_f32-1.c | 13 --
135 files changed, 2006 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c
delete mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c
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delete mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c
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delete mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c
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diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c
deleted file mode 100644
index 714fbf9bfe7..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include <arm_mve.h>
-int8x16_t foo (int8x16_t a, int16_t b)
-{
- return vaddq (a, (b<<3));
-}
-int16x8_t foo1 (int16x8_t a, int16_t b)
-{
- return vaddq (a, (b<<3));
-}
-int32x4_t foo2 (int32x4_t a, int16_t b)
-{
- return vaddq (a, (b<<3));
-}
-uint8x16_t foo3 (uint8x16_t a, int16_t b)
-{
- return vaddq (a, (b<<3));
-}
-uint16x8_t foo4 (uint16x8_t a, int16_t b)
-{
- return vaddq (a, (b<<3));
-}
-uint32x4_t foo5 (uint32x4_t a, int16_t b)
-{
- return vaddq (a, (b<<3));
-}
-float16x8_t foo6 (float16x8_t a)
-{
- return vaddq (a, (float16_t)23.6);
-}
-float32x4_t foo7 (float32x4_t a)
-{
- return vaddq (a, (float32_t)23.46);
-}
-float16x8_t foo8 (float16x8_t a)
-{
- return vaddq (a, 23.6);
-}
-float32x4_t foo9 (float32x4_t a)
-{
- return vaddq (a, 23.46);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c
deleted file mode 100644
index 719b95d9020..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include <arm_mve.h>
-mve_pred16_t p;
-
-int32x4_t fn1 (int32x4_t vecIdx)
-{
- return vaddq_m(vuninitializedq_s32(), vecIdx, 1, p);
-}
-
-int16x8_t fn2 (int16x8_t vecIdx)
-{
- return vaddq_m(vuninitializedq_s16(), vecIdx, 1, p);
-}
-
-int8x16_t fn3 (int8x16_t vecIdx)
-{
- return vaddq_m(vuninitializedq_s8(), vecIdx, 1, p);
-}
-
-uint32x4_t fn4 (uint32x4_t vecIdx)
-{
- return vaddq_m(vuninitializedq_u32(), vecIdx, 1, p);
-}
-
-uint16x8_t fn5 (uint16x8_t vecIdx)
-{
- return vaddq_m(vuninitializedq_u16(), vecIdx, 1, p);
-}
-
-uint8x16_t fn6 (uint8x16_t vecIdx)
-{
- return vaddq_m(vuninitializedq_u8(), vecIdx, 1, p);
-}
-
-float32x4_t fn7 (float32x4_t vecIdx)
-{
- return vaddq_m(vuninitializedq_f32(), vecIdx, (float32_t) 1.23, p);
-}
-
-float16x8_t fn8 (float16x8_t vecIdx)
-{
- return vaddq_m(vuninitializedq_f16(), vecIdx, (float16_t) 1.40, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c
deleted file mode 100644
index baa7fabe061..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include <arm_mve.h>
-int8x16_t foo (int8x16_t a, int16_t b)
-{
- return vaddq (a, (b<<3));
-}
-int16x8_t foo1 (int16x8_t a, int16_t b)
-{
- return vaddq (a, (b<<3));
-}
-int32x4_t foo2 (int32x4_t a, int16_t b)
-{
- return vaddq (a, (b<<3));
-}
-uint8x16_t foo3 (uint8x16_t a, int16_t b)
-{
- return vaddq (a, (b<<3));
-}
-uint16x8_t foo4 (uint16x8_t a, int16_t b)
-{
- return vaddq (a, (b<<3));
-}
-uint32x4_t foo5 (uint32x4_t a, int16_t b)
-{
- return vaddq (a, (b<<3));
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c
deleted file mode 100644
index 15587802925..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (uint16x8_t inactive, int32_t a, mve_pred16_t p)
-{
- return vddupq_m (inactive, a, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c
deleted file mode 100644
index 8a9ed6327d3..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint32x4_t inactive, int32_t a, mve_pred16_t p)
-{
- return vddupq_m (inactive, a, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c
deleted file mode 100644
index fe4aceeea97..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint8x16_t
-foo1 (uint8x16_t inactive, int32_t a, mve_pred16_t p)
-{
- return vddupq_m (inactive, a, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c
deleted file mode 100644
index 05a68cbe559..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (int32_t a)
-{
- return vddupq_u16 (a, 4);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c
deleted file mode 100644
index f702c4cdb0a..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (int32_t a)
-{
- return vddupq_u32 (a, 1);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c
deleted file mode 100644
index f272056c423..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint8x16_t
-foo1 (int32_t a)
-{
- return vddupq_u8 (a, 1);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c
deleted file mode 100644
index 31e37827e60..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint16x8_t
-foo1 (int32_t a, mve_pred16_t p)
-{
- return vddupq_x_u16 (a, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c
deleted file mode 100644
index 9989d0b0f00..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint32x4_t
-foo1 (int32_t a, mve_pred16_t p)
-{
- return vddupq_x_u32 (a, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c
deleted file mode 100644
index 19f1501fe4e..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint8x16_t
-foo1 (int32_t a, mve_pred16_t p)
-{
- return vddupq_x_u8 (a, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c
deleted file mode 100644
index 07ea2d7d14c..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (int32_t a, uint32_t b, mve_pred16_t p)
-{
- return vdwdupq_x_u16 (a, b, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c
deleted file mode 100644
index 9889b0b2b66..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (int32_t a, uint32_t b, mve_pred16_t p)
-{
- return vdwdupq_x_u32 (a, b, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c
deleted file mode 100644
index 13ad8d69e18..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint8x16_t
-foo1 (int32_t a, uint32_t b, mve_pred16_t p)
-{
- return vdwdupq_x_u8 (a, b, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c
deleted file mode 100644
index cbe998e2faa..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (uint16x8_t inactive, int32_t a, mve_pred16_t p)
-{
- return vidupq_m (inactive, a, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c
deleted file mode 100644
index c9aa5c661de..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint32x4_t
-foo1 (uint32x4_t inactive, int32_t a, mve_pred16_t p)
-{
- return vidupq_m (inactive, a, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c
deleted file mode 100644
index 7b075744d9a..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint8x16_t
-foo1 (uint8x16_t inactive, int32_t a, mve_pred16_t p)
-{
- return vidupq_m (inactive, a, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c
deleted file mode 100644
index a461a1e64b1..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (int32_t a)
-{
- return vidupq_u16 (a, 4);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c
deleted file mode 100644
index c5b01a7ac90..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint32x4_t
-foo1 (int32_t a)
-{
- return vidupq_u32 (a, 1);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c
deleted file mode 100644
index f963d51ac0f..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint8x16_t
-foo1 (int32_t a)
-{
- return vidupq_u8 (a, 1);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c
deleted file mode 100644
index aecd4be5e71..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint16x8_t
-foo1 (int32_t a, mve_pred16_t p)
-{
- return vidupq_x_u16 (a, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c
deleted file mode 100644
index d3d33053f92..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint32x4_t
-foo1 (int32_t a, mve_pred16_t p)
-{
- return vidupq_x_u32 (a, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c
deleted file mode 100644
index f71953aeef4..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint8x16_t
-foo1 (int32_t a, mve_pred16_t p)
-{
- return vidupq_x_u8 (a, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c
deleted file mode 100644
index 312966773e6..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (int32_t a, uint32_t b, mve_pred16_t p)
-{
- return viwdupq_x_u16 (a, b, 2, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c
deleted file mode 100644
index a5d758126d4..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (int32_t a, uint32_t b, mve_pred16_t p)
-{
- return viwdupq_x_u32 (a, b, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c
deleted file mode 100644
index aa4e7375d39..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint8x16_t
-foo1 (int32_t a, uint32_t b, mve_pred16_t p)
-{
- return viwdupq_x_u8 (a, b, 8, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c
deleted file mode 100644
index e5b635983bf..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int64x2_t
-foo1 (int64_t * base, uint64x2_t offset)
-{
- return vldrdq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c
deleted file mode 100644
index 8d96527c6df..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint64x2_t
-foo1 (uint64_t * base, uint64x2_t offset)
-{
- return vldrdq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c
deleted file mode 100644
index e66e4465b19..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int64x2_t
-foo1 (int64_t * base, uint64x2_t offset, mve_pred16_t p)
-{
- return vldrdq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c
deleted file mode 100644
index 7ca9590c12c..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint64x2_t
-foo1 (uint64_t * base, uint64x2_t offset, mve_pred16_t p)
-{
- return vldrdq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c
deleted file mode 100644
index b8491680536..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int64x2_t
-foo1 (int64_t * base, uint64x2_t offset)
-{
- return vldrdq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c
deleted file mode 100644
index 851d4a1f435..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint64x2_t
-foo1 (uint64_t * base, uint64x2_t offset)
-{
- return vldrdq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c
deleted file mode 100644
index 586e38cfe43..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int64x2_t
-foo1 (int64_t * base, uint64x2_t offset, mve_pred16_t p)
-{
- return vldrdq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c
deleted file mode 100644
index dd6f482422f..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint64x2_t
-foo1 (uint64_t * base, uint64x2_t offset, mve_pred16_t p)
-{
- return vldrdq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c
deleted file mode 100644
index 3c0ae4b4262..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16_t * base, uint16x8_t offset)
-{
- return vldrhq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c
deleted file mode 100644
index bc7a51b38a5..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int16x8_t
-foo1 (int16_t * base, uint16x8_t offset)
-{
- return vldrhq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c
deleted file mode 100644
index d6e83072995..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int32x4_t
-foo1 (int16_t * base, uint32x4_t offset)
-{
- return vldrhq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c
deleted file mode 100644
index 21b0b1cf52e..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint16x8_t
-foo1 (uint16_t * base, uint16x8_t offset)
-{
- return vldrhq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c
deleted file mode 100644
index 3a9c47e9c47..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint16_t * base, uint32x4_t offset)
-{
- return vldrhq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c
deleted file mode 100644
index e31d0bc05bb..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16_t * base, uint16x8_t offset, mve_pred16_t p)
-{
- return vldrhq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c
deleted file mode 100644
index 6a40159be42..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int16x8_t
-foo1 (int16_t * base, uint16x8_t offset, mve_pred16_t p)
-{
- return vldrhq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c
deleted file mode 100644
index 1d9a70db727..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int32x4_t
-foo1 (int16_t * base, uint32x4_t offset, mve_pred16_t p)
-{
- return vldrhq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c
deleted file mode 100644
index 8fedbef9aef..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (uint16_t * base, uint16x8_t offset, mve_pred16_t p)
-{
- return vldrhq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c
deleted file mode 100644
index db410437c02..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint16_t * base, uint32x4_t offset, mve_pred16_t p)
-{
- return vldrhq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c
deleted file mode 100644
index c12bd91a733..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16_t * base, uint16x8_t offset)
-{
- return vldrhq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c
deleted file mode 100644
index df291626299..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int16x8_t
-foo1 (int16_t * base, uint16x8_t offset)
-{
- return vldrhq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c
deleted file mode 100644
index 9bc6627accf..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int32x4_t
-foo1 (int16_t * base, uint32x4_t offset)
-{
- return vldrhq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c
deleted file mode 100644
index c470871617d..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (uint16_t * base, uint16x8_t offset)
-{
- return vldrhq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c
deleted file mode 100644
index 2d4fe4c1d25..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint16_t * base, uint32x4_t offset)
-{
- return vldrhq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c
deleted file mode 100644
index 755540d93b6..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16_t * base, uint16x8_t offset, mve_pred16_t p)
-{
- return vldrhq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler "vldrht.f16" } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c
deleted file mode 100644
index b9fc8d3242b..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int16x8_t
-foo1 (int16_t * base, uint16x8_t offset, mve_pred16_t p)
-{
- return vldrhq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler "vldrht.u16" } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c
deleted file mode 100644
index c65df114f15..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int32x4_t
-foo1 (int16_t * base, uint32x4_t offset, mve_pred16_t p)
-{
- return vldrhq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c
deleted file mode 100644
index 8bb493bc6c0..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint16x8_t
-foo1 (uint16_t * base, uint16x8_t offset, mve_pred16_t p)
-{
- return vldrhq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c
deleted file mode 100644
index cac933f0f36..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint32x4_t
-foo1 (uint16_t * base, uint32x4_t offset, mve_pred16_t p)
-{
- return vldrhq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c
deleted file mode 100644
index 6d10e1ce9e8..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32_t * base, uint32x4_t offset)
-{
- return vldrwq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c
deleted file mode 100644
index 0f29a6a8aa1..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int32x4_t
-foo1 (int32_t * base, uint32x4_t offset)
-{
- return vldrwq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c
deleted file mode 100644
index 29e231757ec..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint32_t * base, uint32x4_t offset)
-{
- return vldrwq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c
deleted file mode 100644
index 77a949fc1a6..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32_t * base, uint32x4_t offset, mve_pred16_t p)
-{
- return vldrwq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c
deleted file mode 100644
index 849783ab89f..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int32x4_t
-foo1 (int32_t * base, uint32x4_t offset, mve_pred16_t p)
-{
- return vldrwq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c
deleted file mode 100644
index 3fe47cbeab5..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint32_t * base, uint32x4_t offset, mve_pred16_t p)
-{
- return vldrwq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c
deleted file mode 100644
index 0d166348de5..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32_t * base, uint32x4_t offset)
-{
- return vldrwq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c
deleted file mode 100644
index 78e520b159e..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int32x4_t
-foo1 (int32_t * base, uint32x4_t offset)
-{
- return vldrwq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c
deleted file mode 100644
index 6b8b72818d9..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint32_t * base, uint32x4_t offset)
-{
- return vldrwq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c
deleted file mode 100644
index db79e57a2f5..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32_t * base, uint32x4_t offset, mve_pred16_t p)
-{
- return vldrwq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c
deleted file mode 100644
index e060fee10ca..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int32x4_t
-foo1 (int32_t * base, uint32x4_t offset, mve_pred16_t p)
-{
- return vldrwq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c
deleted file mode 100644
index 72446470ae3..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint32_t * base, uint32x4_t offset, mve_pred16_t p)
-{
- return vldrwq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c
deleted file mode 100644
index 62dfb450a6d..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int
-foowu32( uint32_t * pDataSrc, uint32_t * pDataDest)
-{
- const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
- const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
- uint32x4_t vecIn1 = vldrwq_u32 ((uint32_t const *) pDataSrc);
- uint32x4_t vecIn2 = vldrwq_u32 ((uint32_t const *) &pDataSrc[4]);
- vstrwq_scatter_shifted_offset_u32 (pDataDest, vecOffs1, vecIn1);
- vstrwq_scatter_shifted_offset_u32 (pDataDest, vecOffs2, vecIn2);
- pDataDest[8] = pDataSrc[8];
- return 0;
-}
-
-int
-foowf32( float32_t * pDataSrc, float32_t * pDataDest)
-{
- const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
- const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
- float32x4_t vecIn1 = vldrwq_f32 ((float32_t const *) pDataSrc);
- float32x4_t vecIn2 = vldrwq_f32 ((float32_t const *) &pDataSrc[4]);
- vstrwq_scatter_shifted_offset_f32 (pDataDest, vecOffs1, vecIn1);
- vstrwq_scatter_shifted_offset_f32 (pDataDest, vecOffs2, vecIn2);
- pDataDest[8] = pDataSrc[8];
- return 0;
-}
-
-int
-foohu16( uint16_t * pDataSrc, uint16_t * pDataDest)
-{
- const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
- const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
- uint16x8_t vecIn1 = vldrhq_u16 ((uint16_t const *) pDataSrc);
- uint16x8_t vecIn2 = vldrhq_u16 ((uint16_t const *) &pDataSrc[8]);
- vstrhq_scatter_shifted_offset_u16 (pDataDest, vecOffs1, vecIn1);
- vstrhq_scatter_shifted_offset_u16 (pDataDest, vecOffs2, vecIn2);
- pDataDest[16] = pDataSrc[16];
- return 0;
-}
-
-int
-foohu32( uint32_t * pDataSrc, uint32_t * pDataDest)
-{
- const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
- const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
- uint32x4_t vecIn1 = vldrhq_u32 ((uint16_t const *) pDataSrc);
- uint32x4_t vecIn2 = vldrhq_u32 ((uint16_t const *) &pDataSrc[4]);
- vstrhq_scatter_shifted_offset_u32 ((uint16_t *)pDataDest, vecOffs1, vecIn1);
- vstrhq_scatter_shifted_offset_u32 ((uint16_t *)pDataDest, vecOffs2, vecIn2);
- pDataDest[8] = pDataSrc[8];
- return 0;
-}
-
-int
-foohf16( float16_t * pDataSrc, float16_t * pDataDest)
-{
- const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
- const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
- float16x8_t vecIn1 = vldrhq_f16 ((float16_t const *) pDataSrc);
- float16x8_t vecIn2 = vldrhq_f16 ((float16_t const *) &pDataSrc[8]);
- vstrhq_scatter_shifted_offset_f16 (pDataDest, vecOffs1, vecIn1);
- vstrhq_scatter_shifted_offset_f16 (pDataDest, vecOffs2, vecIn2);
- pDataDest[16] = pDataSrc[16];
- return 0;
-}
-
-int
-foodu64( uint64_t * pDataSrc, uint64_t * pDataDest)
-{
- const uint64x2_t vecOffs1 = { 0, 1};
- const uint64x2_t vecOffs2 = { 2, 3};
- uint32x4_t vecIn1 = vldrwq_u32 ((uint32_t const *) pDataSrc);
- uint32x4_t vecIn2 = vldrwq_u32 ((uint32_t const *) &pDataSrc[2]);
-
- vstrdq_scatter_shifted_offset_u64 (pDataDest, vecOffs1, (uint64x2_t) vecIn1);
- vstrdq_scatter_shifted_offset_u64 (pDataDest, vecOffs2, (uint64x2_t) vecIn2);
-
- pDataDest[2] = pDataSrc[2];
- return 0;
-}
-
-int
-foows32( int32_t * pDataSrc, int32_t * pDataDest)
-{
- const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
- const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
- int32x4_t vecIn1 = vldrwq_s32 ((int32_t const *) pDataSrc);
- int32x4_t vecIn2 = vldrwq_s32 ((int32_t const *) &pDataSrc[4]);
- vstrwq_scatter_shifted_offset_s32 (pDataDest, vecOffs1, vecIn1);
- vstrwq_scatter_shifted_offset_s32 (pDataDest, vecOffs2, vecIn2);
- pDataDest[8] = pDataSrc[8];
- return 0;
-}
-
-int
-foohs16( int16_t * pDataSrc, int16_t * pDataDest)
-{
- const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
- const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
- int16x8_t vecIn1 = vldrhq_s16 ((int16_t const *) pDataSrc);
- int16x8_t vecIn2 = vldrhq_s16 ((int16_t const *) &pDataSrc[8]);
- vstrhq_scatter_shifted_offset_s16 (pDataDest, vecOffs1, vecIn1);
- vstrhq_scatter_shifted_offset_s16 (pDataDest, vecOffs2, vecIn2);
- pDataDest[16] = pDataSrc[16];
- return 0;
-}
-
-int
-foohs32( int32_t * pDataSrc, int32_t * pDataDest)
-{
- const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
- const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
- int32x4_t vecIn1 = vldrhq_s32 ((int16_t const *) pDataSrc);
- int32x4_t vecIn2 = vldrhq_s32 ((int16_t const *) &pDataSrc[4]);
- vstrhq_scatter_shifted_offset_s32 ((int16_t *)pDataDest, vecOffs1, vecIn1);
- vstrhq_scatter_shifted_offset_s32 ((int16_t *)pDataDest, vecOffs2, vecIn2);
- pDataDest[8] = pDataSrc[8];
- return 0;
-}
-
-int
-foods64( int64_t * pDataSrc, int64_t * pDataDest)
-{
- const uint64x2_t vecOffs1 = { 0, 1};
- const uint64x2_t vecOffs2 = { 2, 3};
- int32x4_t vecIn1 = vldrwq_s32 ((int32_t const *) pDataSrc);
- int32x4_t vecIn2 = vldrwq_s32 ((int32_t const *) &pDataSrc[2]);
-
- vstrdq_scatter_shifted_offset_s64 (pDataDest, vecOffs1, (int64x2_t) vecIn1);
- vstrdq_scatter_shifted_offset_s64 (pDataDest, vecOffs2, (int64x2_t) vecIn2);
-
- pDataDest[2] = pDataSrc[2];
- return 0;
-}
-
-/* { dg-final { scan-assembler-times "vstr\[a-z\]" 20 } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c
deleted file mode 100644
index a51d3a21167..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-mve_pred16_t __p;
-int
-foowu32( uint32_t * pDataSrc, uint32_t * pDataDest)
-{
- const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
- const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
- uint32x4_t vecIn1 = vldrwq_z_u32 ((uint32_t const *) pDataSrc, __p);
- uint32x4_t vecIn2 = vldrwq_z_u32 ((uint32_t const *) &pDataSrc[4], __p);
- vstrwq_scatter_shifted_offset_p_u32 (pDataDest, vecOffs1, vecIn1, __p);
- vstrwq_scatter_shifted_offset_p_u32 (pDataDest, vecOffs2, vecIn2, __p);
- pDataDest[8] = pDataSrc[8];
- return 0;
-}
-
-int
-foowf32( float32_t * pDataSrc, float32_t * pDataDest)
-{
- const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
- const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
- float32x4_t vecIn1 = vldrwq_z_f32 ((float32_t const *) pDataSrc, __p);
- float32x4_t vecIn2 = vldrwq_z_f32 ((float32_t const *) &pDataSrc[4], __p);
- vstrwq_scatter_shifted_offset_p_f32 (pDataDest, vecOffs1, vecIn1, __p);
- vstrwq_scatter_shifted_offset_p_f32 (pDataDest, vecOffs2, vecIn2, __p);
- pDataDest[8] = pDataSrc[8];
- return 0;
-}
-
-int
-foohu16( uint16_t * pDataSrc, uint16_t * pDataDest)
-{
- const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
- const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
- uint16x8_t vecIn1 = vldrhq_z_u16 ((uint16_t const *) pDataSrc, __p);
- uint16x8_t vecIn2 = vldrhq_z_u16 ((uint16_t const *) &pDataSrc[8], __p);
- vstrhq_scatter_shifted_offset_p_u16 (pDataDest, vecOffs1, vecIn1, __p);
- vstrhq_scatter_shifted_offset_p_u16 (pDataDest, vecOffs2, vecIn2, __p);
- pDataDest[16] = pDataSrc[16];
- return 0;
-}
-
-int
-foohu32( uint32_t * pDataSrc, uint32_t * pDataDest)
-{
- const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
- const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
- uint32x4_t vecIn1 = vldrhq_z_u32 ((uint16_t const *) pDataSrc, __p);
- uint32x4_t vecIn2 = vldrhq_z_u32 ((uint16_t const *) &pDataSrc[4], __p);
- vstrhq_scatter_shifted_offset_p_u32 ((uint16_t *)pDataDest, vecOffs1, vecIn1, __p);
- vstrhq_scatter_shifted_offset_p_u32 ((uint16_t *)pDataDest, vecOffs2, vecIn2, __p);
- pDataDest[8] = pDataSrc[8];
- return 0;
-}
-
-int
-foohf16( float16_t * pDataSrc, float16_t * pDataDest)
-{
- const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
- const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
- float16x8_t vecIn1 = vldrhq_z_f16 ((float16_t const *) pDataSrc, __p);
- float16x8_t vecIn2 = vldrhq_z_f16 ((float16_t const *) &pDataSrc[8], __p);
- vstrhq_scatter_shifted_offset_p_f16 (pDataDest, vecOffs1, vecIn1, __p);
- vstrhq_scatter_shifted_offset_p_f16 (pDataDest, vecOffs2, vecIn2, __p);
- pDataDest[16] = pDataSrc[16];
- return 0;
-}
-
-int
-foodu64( uint64_t * pDataSrc, uint64_t * pDataDest)
-{
- const uint64x2_t vecOffs1 = { 0, 1};
- const uint64x2_t vecOffs2 = { 2, 3};
- uint32x4_t vecIn1 = vldrwq_z_u32 ((uint32_t const *) pDataSrc, __p);
- uint32x4_t vecIn2 = vldrwq_z_u32 ((uint32_t const *) &pDataSrc[2], __p);
-
- vstrdq_scatter_shifted_offset_p_u64 (pDataDest, vecOffs1, (uint64x2_t) vecIn1, __p);
- vstrdq_scatter_shifted_offset_p_u64 (pDataDest, vecOffs2, (uint64x2_t) vecIn2, __p);
-
- pDataDest[2] = pDataSrc[2];
- return 0;
-}
-
-int
-foows32( int32_t * pDataSrc, int32_t * pDataDest)
-{
- const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
- const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
- int32x4_t vecIn1 = vldrwq_z_s32 ((int32_t const *) pDataSrc, __p);
- int32x4_t vecIn2 = vldrwq_z_s32 ((int32_t const *) &pDataSrc[4], __p);
- vstrwq_scatter_shifted_offset_p_s32 (pDataDest, vecOffs1, vecIn1, __p);
- vstrwq_scatter_shifted_offset_p_s32 (pDataDest, vecOffs2, vecIn2, __p);
- pDataDest[8] = pDataSrc[8];
- return 0;
-}
-
-int
-foohs16( int16_t * pDataSrc, int16_t * pDataDest)
-{
- const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
- const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
- int16x8_t vecIn1 = vldrhq_z_s16 ((int16_t const *) pDataSrc, __p);
- int16x8_t vecIn2 = vldrhq_z_s16 ((int16_t const *) &pDataSrc[8], __p);
- vstrhq_scatter_shifted_offset_p_s16 (pDataDest, vecOffs1, vecIn1, __p);
- vstrhq_scatter_shifted_offset_p_s16 (pDataDest, vecOffs2, vecIn2, __p);
- pDataDest[16] = pDataSrc[16];
- return 0;
-}
-
-int
-foohs32( int32_t * pDataSrc, int32_t * pDataDest)
-{
- const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
- const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
- int32x4_t vecIn1 = vldrhq_z_s32 ((int16_t const *) pDataSrc, __p);
- int32x4_t vecIn2 = vldrhq_z_s32 ((int16_t const *) &pDataSrc[4], __p);
- vstrhq_scatter_shifted_offset_p_s32 ((int16_t *)pDataDest, vecOffs1, vecIn1, __p);
- vstrhq_scatter_shifted_offset_p_s32 ((int16_t *)pDataDest, vecOffs2, vecIn2, __p);
- pDataDest[8] = pDataSrc[8];
- return 0;
-}
-
-int
-foods64( int64_t * pDataSrc, int64_t * pDataDest)
-{
- const uint64x2_t vecOffs1 = { 0, 1};
- const uint64x2_t vecOffs2 = { 2, 3};
- int32x4_t vecIn1 = vldrwq_z_s32 ((int32_t const *) pDataSrc, __p);
- int32x4_t vecIn2 = vldrwq_z_s32 ((int32_t const *) &pDataSrc[2], __p);
-
- vstrdq_scatter_shifted_offset_p_s64 (pDataDest, vecOffs1, (int64x2_t) vecIn1, __p);
- vstrdq_scatter_shifted_offset_p_s64 (pDataDest, vecOffs2, (int64x2_t) vecIn2, __p);
-
- pDataDest[2] = pDataSrc[2];
- return 0;
-}
-
-/* { dg-final { scan-assembler-times "vstr\[a-z\]t" 20 } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c
deleted file mode 100644
index 8348098f948..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
-{
- return vaddq_m (inactive, a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c
deleted file mode 100644
index c34cc98385f..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
-{
- return vaddq_m (inactive, a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c
deleted file mode 100644
index 3bb01676947..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
- return vaddq_x (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c
deleted file mode 100644
index 66dedc7d7e5..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
- return vaddq_x (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c
deleted file mode 100644
index 909ca936492..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
- return vcmpeqq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c
deleted file mode 100644
index 8f993af20af..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
- return vcmpeqq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c
deleted file mode 100644
index 223cffc17e5..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b)
-{
- return vcmpeqq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c
deleted file mode 100644
index 81669bd7c60..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b)
-{
- return vcmpeqq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c
deleted file mode 100644
index 4a4e4b34fde..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
- return vcmpgeq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c
deleted file mode 100644
index c406a63aae2..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
- return vcmpgeq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c
deleted file mode 100644
index a65ed4421a8..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b)
-{
- return vcmpgeq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c
deleted file mode 100644
index 2e2fc0170eb..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b)
-{
- return vcmpgeq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c
deleted file mode 100644
index 08c91a72e05..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
- return vcmpgtq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c
deleted file mode 100644
index 0b74482211d..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
- return vcmpgtq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c
deleted file mode 100644
index 3b2faeaf64f..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b)
-{
- return vcmpgtq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c
deleted file mode 100644
index 16862e0209c..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b)
-{
- return vcmpgtq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c
deleted file mode 100644
index 50e53bdac47..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
- return vcmpleq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c
deleted file mode 100644
index b16da273a91..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
- return vcmpleq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c
deleted file mode 100644
index 4a4b97312b0..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b)
-{
- return vcmpleq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c
deleted file mode 100644
index 8d8f1051933..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b)
-{
- return vcmpleq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c
deleted file mode 100644
index 62ab53fb2ef..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
- return vcmpltq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c
deleted file mode 100644
index 55886fccff1..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
- return vcmpltq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c
deleted file mode 100644
index cd95daea48c..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b)
-{
- return vcmpltq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c
deleted file mode 100644
index db76687d53e..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b)
-{
- return vcmpltq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c
deleted file mode 100644
index 30618e87101..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
- return vcmpneq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c
deleted file mode 100644
index 4ecfda6d75c..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
- return vcmpneq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c
deleted file mode 100644
index 75a0090fcdc..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b)
-{
- return vcmpneq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c
deleted file mode 100644
index 11ae14cff56..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b)
-{
- return vcmpneq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c
deleted file mode 100644
index e47ae6d8e3b..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
-{
- return vfmaq_m (a, b, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c
deleted file mode 100644
index 78c39f0b2c9..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
-{
- return vfmaq_m (a, b, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c
deleted file mode 100644
index f7867f2c0c3..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c)
-{
- return vfmaq (a, b, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c
deleted file mode 100644
index f0bc45bfed9..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c)
-{
- return vfmaq (a, b, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c
deleted file mode 100644
index 4750e108b6d..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
-{
- return vfmasq_m (a, b, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c
deleted file mode 100644
index 4a379711386..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
-{
- return vfmasq_m (a, b, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c
deleted file mode 100644
index db824512b2b..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c)
-{
- return vfmasq (a, b, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c
deleted file mode 100644
index 12b1410c008..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c)
-{
- return vfmasq (a, b, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c
deleted file mode 100644
index 7c2349d1ee4..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b)
-{
- return vmaxnmavq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c
deleted file mode 100644
index 0deef79487a..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b)
-{
- return vmaxnmavq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c
deleted file mode 100644
index 56a7ac001f9..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
-{
- return vmaxnmavq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c
deleted file mode 100644
index 36c10a90633..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
-{
- return vmaxnmavq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c
deleted file mode 100644
index f60641f5de0..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b)
-{
- return vmaxnmvq (23.35, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c
deleted file mode 100644
index f8c9f44ac78..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b)
-{
- return vmaxnmvq (34.56, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c
deleted file mode 100644
index 96820ecab91..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
-{
- return vmaxnmvq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c
deleted file mode 100644
index 826ee8f900a..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
-{
- return vmaxnmvq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c
deleted file mode 100644
index 37d5136edca..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b)
-{
- return vminnmavq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c
deleted file mode 100644
index 78978d05054..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b)
-{
- return vminnmavq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c
deleted file mode 100644
index 7170b747a40..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
-{
- return vminnmavq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c
deleted file mode 100644
index 09559053852..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
-{
- return vminnmavq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c
deleted file mode 100644
index 132d1a123f8..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b)
-{
- return vminnmvq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c
deleted file mode 100644
index 74909075b09..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b)
-{
- return vminnmvq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c
deleted file mode 100644
index c88c3b74a50..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
-{
- return vminnmvq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c
deleted file mode 100644
index e4db972fc70..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
-{
- return vminnmvq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c
deleted file mode 100644
index c8222c5c7b9..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
-{
- return vmulq_m (inactive, a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c
deleted file mode 100644
index 2fae3a7f8fa..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
-{
- return vmulq_m (inactive, a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c
deleted file mode 100644
index cef311d981d..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16_t b)
-{
- return vmulq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c
deleted file mode 100644
index d6d4b9a0a7c..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32_t b)
-{
- return vmulq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c
deleted file mode 100644
index ea4cab03490..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
- return vmulq_x (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c
deleted file mode 100644
index a7a54c7c92c..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
- return vmulq_x (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c
deleted file mode 100644
index 608dd30788e..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo (float16_t a, float16x8_t b)
-{
- return vsetq_lane (23.26, b, 0);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c
deleted file mode 100644
index c5f5db7f28d..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo (float32_t a, float32x4_t b)
-{
- return vsetq_lane (23.34, b, 0);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c
deleted file mode 100644
index f3e19613e7e..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
-{
- return vsubq_m (inactive, a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c
deleted file mode 100644
index 4b5cd90c9ed..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
-{
- return vsubq_m (inactive, a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c
deleted file mode 100644
index f8832546f54..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16_t b)
-{
- return vsubq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c
deleted file mode 100644
index 88d9675540d..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32_t b)
-{
- return vsubq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c
deleted file mode 100644
index b3a67bb43eb..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo (float16x8_t a, float16_t b, mve_pred16_t p)
-{
- return vsubq_x_n_f16 (a, 23.23, p);
-}
-
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c
deleted file mode 100644
index dcb2425397b..00000000000
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo (float32x4_t a, float32_t b, mve_pred16_t p)
-{
- return vsubq_x_n_f32 (a, 23.23, p);
-}
-
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--
2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests
2023-04-28 11:29 [PATCH 01/10] arm: Mve testsuite improvements Andrea Corallo
` (6 preceding siblings ...)
2023-04-28 11:30 ` [PATCH 08/10] arm testsuite: Remove reduntant tests Andrea Corallo
@ 2023-04-28 11:30 ` Andrea Corallo
2023-04-28 16:54 ` Kyrylo Tkachov
2023-05-02 8:28 ` Christophe Lyon
2023-04-28 11:30 ` [PATCH 10/10] arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes Andrea Corallo
2023-04-28 16:27 ` [PATCH 01/10] arm: Mve testsuite improvements Kyrylo Tkachov
9 siblings, 2 replies; 31+ messages in thread
From: Andrea Corallo @ 2023-04-28 11:30 UTC (permalink / raw)
To: gcc-patches; +Cc: kyrylo.tkachov, Richard.Earnshaw, Stam Markianos-Wright
From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Hi all,
This is a simple testsuite tidy-up patch, addressing to types of errors:
* The vcmp vector-scalar tests failing due to the compiler's preference
of vector-vector comparisons, over vector-scalar comparisons. This is
due to the lack of cost model for MVE and the compiler not knowing that
the RTL vec_duplicate is free in those instructions. For now, we simply
XFAIL these checks.
* The tests for pr108177 had strict usage of q0 and r0 registers,
meaning that they would FAIL with -mfloat-abi=softf. The register checks
have now been relaxed.
gcc/testsuite/ChangeLog:
* gcc.target/arm/mve/intrinsics/srshr.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/srshrl.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/uqshl.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/uqshll.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/urshr.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/urshrl.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/vadciq_s32.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/vadciq_u32.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/vadcq_s32.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/vadcq_u32.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/vsbciq_s32.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/vsbciq_u32.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/vsbcq_s32.c: XFAIL check.
* gcc.target/arm/mve/intrinsics/vsbcq_u32.c: XFAIL check.
* gcc.target/arm/mve/pr108177-1.c: Relax registers.
* gcc.target/arm/mve/pr108177-10.c: Relax registers.
* gcc.target/arm/mve/pr108177-11.c: Relax registers.
* gcc.target/arm/mve/pr108177-12.c: Relax registers.
* gcc.target/arm/mve/pr108177-13.c: Relax registers.
* gcc.target/arm/mve/pr108177-14.c: Relax registers.
* gcc.target/arm/mve/pr108177-2.c: Relax registers.
* gcc.target/arm/mve/pr108177-3.c: Relax registers.
* gcc.target/arm/mve/pr108177-4.c: Relax registers.
* gcc.target/arm/mve/pr108177-5.c: Relax registers.
* gcc.target/arm/mve/pr108177-6.c: Relax registers.
* gcc.target/arm/mve/pr108177-7.c: Relax registers.
* gcc.target/arm/mve/pr108177-8.c: Relax registers.
* gcc.target/arm/mve/pr108177-9.c: Relax registers.
---
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/pr108177-1.c | 4 ++--
gcc/testsuite/gcc.target/arm/mve/pr108177-10.c | 4 ++--
gcc/testsuite/gcc.target/arm/mve/pr108177-11.c | 4 ++--
gcc/testsuite/gcc.target/arm/mve/pr108177-12.c | 4 ++--
gcc/testsuite/gcc.target/arm/mve/pr108177-13.c | 4 ++--
gcc/testsuite/gcc.target/arm/mve/pr108177-14.c | 4 ++--
gcc/testsuite/gcc.target/arm/mve/pr108177-2.c | 4 ++--
gcc/testsuite/gcc.target/arm/mve/pr108177-3.c | 4 ++--
gcc/testsuite/gcc.target/arm/mve/pr108177-4.c | 4 ++--
gcc/testsuite/gcc.target/arm/mve/pr108177-5.c | 4 ++--
gcc/testsuite/gcc.target/arm/mve/pr108177-6.c | 4 ++--
gcc/testsuite/gcc.target/arm/mve/pr108177-7.c | 4 ++--
gcc/testsuite/gcc.target/arm/mve/pr108177-8.c | 4 ++--
gcc/testsuite/gcc.target/arm/mve/pr108177-9.c | 4 ++--
38 files changed, 52 insertions(+), 52 deletions(-)
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
index dc63c527743..9f8111438a1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
@@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
index 8c5d185ca22..799d3bcdab1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
@@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
index 2296f3e1655..16c3617c104 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
@@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
index 1d870428c55..2f84d751c53 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
@@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
index 8b8610b0617..6cfe7338fce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
@@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
index 409c9de58ba..362e830c908 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
@@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
index c3b1736bfa1..583beb97849 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
@@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
index 3728c738b54..db7f1877d73 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
@@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
index 4e9a346ab14..978bd7d4b52 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
@@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
index 2cf1d1ab0b6..66b6d8b0056 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
@@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
index 89d8e2b9109..9c5f1f2f5c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
@@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
index 482ac094cf3..2723aa7f98f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
@@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
index 085b8277736..5712db2ceef 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
@@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
index a62a73ff24c..f7a25af8574 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
@@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
index f05c9d24643..8cd28fb1681 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
@@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
index 4f6276484ba..1d1f4bf0e58 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
@@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
index e71dcb8f174..bf77a808064 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
@@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
index c6fdb08d8ae..f9f091cd9b3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
@@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
index 4f1ac3c0977..d22ea1aca30 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
@@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
index e36d8a95a85..83beca964d6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
@@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
index 7262503eee6..abe1abfed2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
@@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
index 71d878dff9f..ca55fe2f76c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
@@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
index 3f997e8e487..77bac757d68 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
@@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
index 9917a95ffb7..352afa798d1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
@@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
}
/*
-**foo2:
+**foo2: { xfail *-*-* }
** ...
** vcmp.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
index 2d42062bc8e..8383b4d9e3a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
@@ -7,9 +7,9 @@
/*
** test:
**...
-** vstrbt.8 q0, \[r0\]
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
-** vstrbt.8 q0, \[r0\]
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
*/
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
index 4db594f588f..7b1cd3711d8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
@@ -7,9 +7,9 @@
/*
** test:
**...
-** vstrht.32 q0, \[r0\]
+** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
-** vstrht.32 q0, \[r0\]
+** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
*/
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
index 329fcb33eeb..e6ae8524052 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
@@ -7,9 +7,9 @@
/*
** test:
**...
-** vstrwt.32 q0, \[r0\]
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
-** vstrwt.32 q0, \[r0\]
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
*/
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
index 3f7c5b2a4c1..e352508e07e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
@@ -7,9 +7,9 @@
/*
** test:
**...
-** vstrwt.32 q0, \[r0\]
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
-** vstrwt.32 q0, \[r0\]
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
*/
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
index 2f82228d8f6..13afa92771d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
@@ -7,9 +7,9 @@
/*
** test:
**...
-** vstrht.16 q0, \[r0\]
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
-** vstrht.16 q0, \[r0\]
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
*/
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
index ba6196b7994..a093cd4b708 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
@@ -7,9 +7,9 @@
/*
** test:
**...
-** vstrwt.32 q0, \[r0\]
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
-** vstrwt.32 q0, \[r0\]
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
*/
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
index 52c8d87ccc8..da4181ff0b7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
@@ -7,9 +7,9 @@
/*
** test:
**...
-** vstrbt.8 q0, \[r0\]
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
-** vstrbt.8 q0, \[r0\]
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
*/
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
index ac89e7ea883..9604fd100e6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
@@ -7,9 +7,9 @@
/*
** test:
**...
-** vstrbt.16 q0, \[r0\]
+** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
-** vstrbt.16 q0, \[r0\]
+** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
*/
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
index dc4f7ddab07..07ba37b466c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
@@ -7,9 +7,9 @@
/*
** test:
**...
-** vstrbt.16 q0, \[r0\]
+** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
-** vstrbt.16 q0, \[r0\]
+** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
*/
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
index d1dfd328d66..72c1dd5a4d6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
@@ -7,9 +7,9 @@
/*
** test:
**...
-** vstrbt.32 q0, \[r0\]
+** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
-** vstrbt.32 q0, \[r0\]
+** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
*/
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
index fa70dde9eeb..3fedc9b98c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
@@ -7,9 +7,9 @@
/*
** test:
**...
-** vstrbt.32 q0, \[r0\]
+** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
-** vstrbt.32 q0, \[r0\]
+** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
*/
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
index 73cd8605171..c3b440c3b6c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
@@ -7,9 +7,9 @@
/*
** test:
**...
-** vstrht.16 q0, \[r0\]
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
-** vstrht.16 q0, \[r0\]
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
*/
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
index 187c2b3f4ce..5c450b81d1c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
@@ -7,9 +7,9 @@
/*
** test:
**...
-** vstrht.16 q0, \[r0\]
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
-** vstrht.16 q0, \[r0\]
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
*/
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
index caecd18a881..b5084efcc00 100644
--- a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
@@ -7,9 +7,9 @@
/*
** test:
**...
-** vstrht.32 q0, \[r0\]
+** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
-** vstrht.32 q0, \[r0\]
+** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
**...
*/
--
2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 10/10] arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes
2023-04-28 11:29 [PATCH 01/10] arm: Mve testsuite improvements Andrea Corallo
` (7 preceding siblings ...)
2023-04-28 11:30 ` [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests Andrea Corallo
@ 2023-04-28 11:30 ` Andrea Corallo
2023-04-28 16:58 ` Kyrylo Tkachov
2023-04-28 16:27 ` [PATCH 01/10] arm: Mve testsuite improvements Kyrylo Tkachov
9 siblings, 1 reply; 31+ messages in thread
From: Andrea Corallo @ 2023-04-28 11:30 UTC (permalink / raw)
To: gcc-patches; +Cc: kyrylo.tkachov, Richard.Earnshaw, Stam Markianos-Wright
From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
These newly updated tests were rewritten by Andrea. Some of them
needed further manual fixing as follows:
* The #shift immediate value not in the check-function-bodies as expected
* Some shifts getting optimised to mov immediates, e.g.
`uqshll (1, 1);` -> movs r0, #2; movs r1, #0
* The ACLE was specifying sub-optimal code: lsr+and instead of ubfx. In
this case the test rewritten from the ACLE had the lsr+and pattern,
but the compiler was able to optimise to ubfx. Hence I've changed the
test to now match on ubfx.
gcc/testsuite/ChangeLog:
* gcc.target/arm/mve/intrinsics/srshr.c: Update shift value.
* gcc.target/arm/mve/intrinsics/srshrl.c: Update shift value.
* gcc.target/arm/mve/intrinsics/uqshl.c: Update shift value and mov imm.
* gcc.target/arm/mve/intrinsics/uqshll.c: Update shift value and mov imm.
* gcc.target/arm/mve/intrinsics/urshr.c: Update shift value.
* gcc.target/arm/mve/intrinsics/urshrl.c: Update shift value.
* gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadciq_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadciq_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadcq_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadcq_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Update to ubfx.
---
gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c | 4 ++--
gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c | 5 +++--
gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c | 4 ++--
gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c | 4 ++--
.../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 8 ++------
.../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c | 8 ++------
.../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 8 ++------
.../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 8 ++------
22 files changed, 43 insertions(+), 106 deletions(-)
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
index 94e3f42fd33..734375d58c0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
@@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
-** srshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** srshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
int32_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
index 65f28ccbfde..a91943c38a0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
@@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
-** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
int64_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
index b23c9d97ba6..58aa7a61e42 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
@@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
-** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** uqshl (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint32_t
@@ -24,7 +24,7 @@ foo (uint32_t value)
/*
**foo1:
** ...
-** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** movs r0, #2
** ...
*/
uint32_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
index 6a3d08eea75..5584544aaf7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
@@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
-** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint64_t
@@ -24,7 +24,8 @@ foo (uint64_t value)
/*
**foo1:
** ...
-** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** movs r0, #2
+** movs r1, #0
** ...
*/
uint64_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
index 23afcb8da4c..ff97bf5c473 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
@@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
-** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint32_t
@@ -24,7 +24,7 @@ foo (uint32_t value)
/*
**foo1:
** ...
-** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint32_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
index 8014371f47f..ff6a69d300f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
@@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
-** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint64_t
@@ -24,7 +24,7 @@ foo (uint64_t value)
/*
**foo1:
** ...
-** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint64_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
index b262bf94d39..a6a059a19e9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
@@ -20,9 +20,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
index d349caed36a..942111339f0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
@@ -20,9 +20,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_p
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
index 5166993a355..3b68bb6ac33 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
@@ -16,9 +16,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
index 080bd61d238..82228491043 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
@@ -16,9 +16,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
index 45e6ff03623..0d4cb779254 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
@@ -26,9 +26,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
index 54f141b2093..a0ba6825d8c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
@@ -26,9 +26,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
index 06d5bae09da..47f5f22dde9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
@@ -22,9 +22,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
index e2111cfd16a..55a961be217 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
@@ -22,9 +22,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
index 66a5c4c9da3..dcbaef1a571 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
@@ -20,9 +20,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
index 9306f152cde..08f67f665c1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
@@ -20,9 +20,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_p
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
index 0b5040f0b2a..803246c3235 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
@@ -16,9 +16,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
index df211a64daa..22d2b4355bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
@@ -16,9 +16,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
index 217cfa7ac21..7a332610c69 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
@@ -26,9 +26,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
index dad04d05d68..60902196502 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
@@ -26,9 +26,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
index cd033640bcc..523fa32ee0d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
@@ -22,9 +22,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
index 6ca0c753b5e..ff720fd2df5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
@@ -22,9 +22,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
--
2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH 01/10] arm: Mve testsuite improvements
2023-04-28 11:29 [PATCH 01/10] arm: Mve testsuite improvements Andrea Corallo
` (8 preceding siblings ...)
2023-04-28 11:30 ` [PATCH 10/10] arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes Andrea Corallo
@ 2023-04-28 16:27 ` Kyrylo Tkachov
9 siblings, 0 replies; 31+ messages in thread
From: Kyrylo Tkachov @ 2023-04-28 16:27 UTC (permalink / raw)
To: Andrea Corallo, gcc-patches; +Cc: Richard Earnshaw, Andrea Corallo
Hi Andrea,
> -----Original Message-----
> From: Andrea Corallo <andrea.corallo@arm.com>
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; Andrea Corallo <Andrea.Corallo@arm.com>
> Subject: [PATCH 01/10] arm: Mve testsuite improvements
>
> Hello all,
>
> this patch improves a number of MVE tests in the testsuite for more
> precise and better coverage using check-function-bodies instead of
> scan-assembler checks. Also all intrusctions prescribed in the ACLE[1]
> are now checked.
>
Thanks. This is ok.
Kyrill
> Best Regards
>
> Andrea
>
> [1] <https://github.com/ARM-software/acle>
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arm/mve/intrinsics/vld1q_f16.c: Use
> check-function-bodies instead of scan-assembler checks. Use
> extern "C" for C++ testing.
> * gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld1q_z_f16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld1q_z_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld1q_z_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld1q_z_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld1q_z_s8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld1q_z_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld1q_z_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld1q_z_u8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld4q_f16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld4q_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld4q_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld4q_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld4q_s8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld4q_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld4q_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vld4q_u8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_s8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_u8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c: Likewise.
> *
> gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c: Likewise.
> *
> gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vst2q_f16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vst2q_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vst2q_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vst2q_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vst2q_s8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vst2q_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vst2q_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vst2q_u8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vst4q_f16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vst4q_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vst4q_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vst4q_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vst4q_s8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vst4q_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vst4q_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vst4q_u8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_s8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_u8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_f16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrhq_u32.c: Likewise.
> ---
> .../gcc.target/arm/mve/intrinsics/vld1q_f16.c | 29 +++++++++--
> .../gcc.target/arm/mve/intrinsics/vld1q_f32.c | 29 +++++++++--
> .../gcc.target/arm/mve/intrinsics/vld1q_s16.c | 29 +++++++++--
> .../gcc.target/arm/mve/intrinsics/vld1q_s32.c | 29 +++++++++--
> .../gcc.target/arm/mve/intrinsics/vld1q_s8.c | 29 +++++++++--
> .../gcc.target/arm/mve/intrinsics/vld1q_u16.c | 29 +++++++++--
> .../gcc.target/arm/mve/intrinsics/vld1q_u32.c | 29 +++++++++--
> .../gcc.target/arm/mve/intrinsics/vld1q_u8.c | 29 +++++++++--
> .../arm/mve/intrinsics/vld1q_z_f16.c | 38 ++++++++++++--
> .../arm/mve/intrinsics/vld1q_z_f32.c | 38 ++++++++++++--
> .../arm/mve/intrinsics/vld1q_z_s16.c | 38 ++++++++++++--
> .../arm/mve/intrinsics/vld1q_z_s32.c | 38 ++++++++++++--
> .../arm/mve/intrinsics/vld1q_z_s8.c | 38 ++++++++++++--
> .../arm/mve/intrinsics/vld1q_z_u16.c | 38 ++++++++++++--
> .../arm/mve/intrinsics/vld1q_z_u32.c | 38 ++++++++++++--
> .../arm/mve/intrinsics/vld1q_z_u8.c | 38 ++++++++++++--
> .../gcc.target/arm/mve/intrinsics/vld4q_f16.c | 37 +++++++++++---
> .../gcc.target/arm/mve/intrinsics/vld4q_f32.c | 37 +++++++++++---
> .../gcc.target/arm/mve/intrinsics/vld4q_s16.c | 37 +++++++++++---
> .../gcc.target/arm/mve/intrinsics/vld4q_s32.c | 37 +++++++++++---
> .../gcc.target/arm/mve/intrinsics/vld4q_s8.c | 37 +++++++++++---
> .../gcc.target/arm/mve/intrinsics/vld4q_u16.c | 37 +++++++++++---
> .../gcc.target/arm/mve/intrinsics/vld4q_u32.c | 37 +++++++++++---
> .../gcc.target/arm/mve/intrinsics/vld4q_u8.c | 37 +++++++++++---
> .../mve/intrinsics/vldrbq_gather_offset_s16.c | 28 +++++++++--
> .../mve/intrinsics/vldrbq_gather_offset_s32.c | 28 +++++++++--
> .../mve/intrinsics/vldrbq_gather_offset_s8.c | 28 +++++++++--
> .../mve/intrinsics/vldrbq_gather_offset_u16.c | 28 +++++++++--
> .../mve/intrinsics/vldrbq_gather_offset_u32.c | 28 +++++++++--
> .../mve/intrinsics/vldrbq_gather_offset_u8.c | 28 +++++++++--
> .../intrinsics/vldrbq_gather_offset_z_s16.c | 36 +++++++++++--
> .../intrinsics/vldrbq_gather_offset_z_s32.c | 36 +++++++++++--
> .../intrinsics/vldrbq_gather_offset_z_s8.c | 36 +++++++++++--
> .../intrinsics/vldrbq_gather_offset_z_u16.c | 36 +++++++++++--
> .../intrinsics/vldrbq_gather_offset_z_u32.c | 36 +++++++++++--
> .../intrinsics/vldrbq_gather_offset_z_u8.c | 36 +++++++++++--
> .../arm/mve/intrinsics/vldrbq_s16.c | 19 ++++++-
> .../arm/mve/intrinsics/vldrbq_s32.c | 19 ++++++-
> .../gcc.target/arm/mve/intrinsics/vldrbq_s8.c | 20 ++++++--
> .../arm/mve/intrinsics/vldrbq_u16.c | 19 ++++++-
> .../arm/mve/intrinsics/vldrbq_u32.c | 19 ++++++-
> .../gcc.target/arm/mve/intrinsics/vldrbq_u8.c | 20 ++++++--
> .../arm/mve/intrinsics/vldrbq_z_s16.c | 23 ++++++++-
> .../arm/mve/intrinsics/vldrbq_z_s32.c | 23 ++++++++-
> .../arm/mve/intrinsics/vldrbq_z_s8.c | 25 ++++++++--
> .../arm/mve/intrinsics/vldrbq_z_u16.c | 23 ++++++++-
> .../arm/mve/intrinsics/vldrbq_z_u32.c | 23 ++++++++-
> .../arm/mve/intrinsics/vldrbq_z_u8.c | 25 ++++++++--
> .../mve/intrinsics/vldrdq_gather_base_s64.c | 19 ++++++-
> .../mve/intrinsics/vldrdq_gather_base_u64.c | 19 ++++++-
> .../intrinsics/vldrdq_gather_base_wb_s64.c | 24 ++++++---
> .../intrinsics/vldrdq_gather_base_wb_u64.c | 24 ++++++---
> .../intrinsics/vldrdq_gather_base_wb_z_s64.c | 31 +++++++++---
> .../intrinsics/vldrdq_gather_base_wb_z_u64.c | 31 +++++++++---
> .../mve/intrinsics/vldrdq_gather_base_z_s64.c | 23 ++++++++-
> .../mve/intrinsics/vldrdq_gather_base_z_u64.c | 23 ++++++++-
> .../mve/intrinsics/vldrdq_gather_offset_s64.c | 28 +++++++++--
> .../mve/intrinsics/vldrdq_gather_offset_u64.c | 28 +++++++++--
> .../intrinsics/vldrdq_gather_offset_z_s64.c | 36 +++++++++++--
> .../intrinsics/vldrdq_gather_offset_z_u64.c | 36 +++++++++++--
> .../vldrdq_gather_shifted_offset_s64.c | 28 +++++++++--
> .../vldrdq_gather_shifted_offset_u64.c | 28 +++++++++--
> .../vldrdq_gather_shifted_offset_z_s64.c | 36 +++++++++++--
> .../vldrdq_gather_shifted_offset_z_u64.c | 36 +++++++++++--
> .../arm/mve/intrinsics/vldrhq_f16.c | 20 ++++++--
> .../mve/intrinsics/vldrhq_gather_offset_f16.c | 28 +++++++++--
> .../mve/intrinsics/vldrhq_gather_offset_s16.c | 28 +++++++++--
> .../mve/intrinsics/vldrhq_gather_offset_s32.c | 28 +++++++++--
> .../mve/intrinsics/vldrhq_gather_offset_u16.c | 28 +++++++++--
> .../mve/intrinsics/vldrhq_gather_offset_u32.c | 28 +++++++++--
> .../intrinsics/vldrhq_gather_offset_z_f16.c | 36 +++++++++++--
> .../intrinsics/vldrhq_gather_offset_z_s16.c | 36 +++++++++++--
> .../intrinsics/vldrhq_gather_offset_z_s32.c | 36 +++++++++++--
> .../intrinsics/vldrhq_gather_offset_z_u16.c | 36 +++++++++++--
> .../intrinsics/vldrhq_gather_offset_z_u32.c | 36 +++++++++++--
> .../vldrhq_gather_shifted_offset_f16.c | 28 +++++++++--
> .../vldrhq_gather_shifted_offset_s16.c | 28 +++++++++--
> .../vldrhq_gather_shifted_offset_s32.c | 28 +++++++++--
> .../vldrhq_gather_shifted_offset_u16.c | 28 +++++++++--
> .../vldrhq_gather_shifted_offset_u32.c | 28 +++++++++--
> .../vldrhq_gather_shifted_offset_z_f16.c | 36 +++++++++++--
> .../vldrhq_gather_shifted_offset_z_s16.c | 36 +++++++++++--
> .../vldrhq_gather_shifted_offset_z_s32.c | 36 +++++++++++--
> .../vldrhq_gather_shifted_offset_z_u16.c | 36 +++++++++++--
> .../vldrhq_gather_shifted_offset_z_u32.c | 36 +++++++++++--
> .../arm/mve/intrinsics/vldrhq_s16.c | 20 ++++++--
> .../arm/mve/intrinsics/vldrhq_s32.c | 20 ++++++--
> .../arm/mve/intrinsics/vldrhq_u16.c | 20 ++++++--
> .../arm/mve/intrinsics/vldrhq_u32.c | 20 ++++++--
> .../arm/mve/intrinsics/vldrhq_z_f16.c | 23 +++++++--
> .../arm/mve/intrinsics/vldrhq_z_s16.c | 23 +++++++--
> .../arm/mve/intrinsics/vldrhq_z_s32.c | 25 ++++++++--
> .../arm/mve/intrinsics/vldrhq_z_u16.c | 23 +++++++--
> .../arm/mve/intrinsics/vldrhq_z_u32.c | 25 ++++++++--
> .../arm/mve/intrinsics/vldrwq_f32.c | 18 ++++++-
> .../mve/intrinsics/vldrwq_gather_base_f32.c | 19 ++++++-
> .../mve/intrinsics/vldrwq_gather_base_s32.c | 19 ++++++-
> .../mve/intrinsics/vldrwq_gather_base_u32.c | 19 ++++++-
> .../intrinsics/vldrwq_gather_base_wb_f32.c | 22 ++++++--
> .../intrinsics/vldrwq_gather_base_wb_s32.c | 22 ++++++--
> .../intrinsics/vldrwq_gather_base_wb_u32.c | 22 ++++++--
> .../intrinsics/vldrwq_gather_base_wb_z_f32.c | 28 ++++++++---
> .../intrinsics/vldrwq_gather_base_wb_z_s32.c | 28 ++++++++---
> .../intrinsics/vldrwq_gather_base_wb_z_u32.c | 28 ++++++++---
> .../mve/intrinsics/vldrwq_gather_base_z_f32.c | 23 ++++++++-
> .../mve/intrinsics/vldrwq_gather_base_z_s32.c | 23 ++++++++-
> .../mve/intrinsics/vldrwq_gather_base_z_u32.c | 23 ++++++++-
> .../mve/intrinsics/vldrwq_gather_offset_f32.c | 28 +++++++++--
> .../mve/intrinsics/vldrwq_gather_offset_s32.c | 28 +++++++++--
> .../mve/intrinsics/vldrwq_gather_offset_u32.c | 28 +++++++++--
> .../intrinsics/vldrwq_gather_offset_z_f32.c | 36 +++++++++++--
> .../intrinsics/vldrwq_gather_offset_z_s32.c | 36 +++++++++++--
> .../intrinsics/vldrwq_gather_offset_z_u32.c | 36 +++++++++++--
> .../vldrwq_gather_shifted_offset_f32.c | 28 +++++++++--
> .../vldrwq_gather_shifted_offset_s32.c | 28 +++++++++--
> .../vldrwq_gather_shifted_offset_u32.c | 28 +++++++++--
> .../vldrwq_gather_shifted_offset_z_f32.c | 36 +++++++++++--
> .../vldrwq_gather_shifted_offset_z_s32.c | 36 +++++++++++--
> .../vldrwq_gather_shifted_offset_z_u32.c | 36 +++++++++++--
> .../arm/mve/intrinsics/vldrwq_s32.c | 18 ++++++-
> .../arm/mve/intrinsics/vldrwq_u32.c | 18 ++++++-
> .../arm/mve/intrinsics/vldrwq_z_f32.c | 23 +++++++--
> .../arm/mve/intrinsics/vldrwq_z_s32.c | 23 +++++++--
> .../arm/mve/intrinsics/vldrwq_z_u32.c | 23 +++++++--
> .../gcc.target/arm/mve/intrinsics/vst2q_f16.c | 37 +++++++++++---
> .../gcc.target/arm/mve/intrinsics/vst2q_f32.c | 37 +++++++++++---
> .../gcc.target/arm/mve/intrinsics/vst2q_s16.c | 37 +++++++++++---
> .../gcc.target/arm/mve/intrinsics/vst2q_s32.c | 37 +++++++++++---
> .../gcc.target/arm/mve/intrinsics/vst2q_s8.c | 37 +++++++++++---
> .../gcc.target/arm/mve/intrinsics/vst2q_u16.c | 37 +++++++++++---
> .../gcc.target/arm/mve/intrinsics/vst2q_u32.c | 37 +++++++++++---
> .../gcc.target/arm/mve/intrinsics/vst2q_u8.c | 37 +++++++++++---
> .../gcc.target/arm/mve/intrinsics/vst4q_f16.c | 50 +++++++++++--------
> .../gcc.target/arm/mve/intrinsics/vst4q_f32.c | 50 +++++++++++--------
> .../gcc.target/arm/mve/intrinsics/vst4q_s16.c | 50 +++++++++++--------
> .../gcc.target/arm/mve/intrinsics/vst4q_s32.c | 50 +++++++++++--------
> .../gcc.target/arm/mve/intrinsics/vst4q_s8.c | 50 +++++++++++--------
> .../gcc.target/arm/mve/intrinsics/vst4q_u16.c | 50 +++++++++++--------
> .../gcc.target/arm/mve/intrinsics/vst4q_u32.c | 50 +++++++++++--------
> .../gcc.target/arm/mve/intrinsics/vst4q_u8.c | 50 +++++++++++--------
> .../arm/mve/intrinsics/vstrbq_p_s16.c | 40 ++++++++++++---
> .../arm/mve/intrinsics/vstrbq_p_s32.c | 40 ++++++++++++---
> .../arm/mve/intrinsics/vstrbq_p_s8.c | 40 ++++++++++++---
> .../arm/mve/intrinsics/vstrbq_p_u16.c | 40 ++++++++++++---
> .../arm/mve/intrinsics/vstrbq_p_u32.c | 40 ++++++++++++---
> .../arm/mve/intrinsics/vstrbq_p_u8.c | 40 ++++++++++++---
> .../arm/mve/intrinsics/vstrbq_s16.c | 32 +++++++++---
> .../arm/mve/intrinsics/vstrbq_s32.c | 32 +++++++++---
> .../gcc.target/arm/mve/intrinsics/vstrbq_s8.c | 32 +++++++++---
> .../intrinsics/vstrbq_scatter_offset_p_s16.c | 40 ++++++++++++---
> .../intrinsics/vstrbq_scatter_offset_p_s32.c | 40 ++++++++++++---
> .../intrinsics/vstrbq_scatter_offset_p_s8.c | 40 ++++++++++++---
> .../intrinsics/vstrbq_scatter_offset_p_u16.c | 40 ++++++++++++---
> .../intrinsics/vstrbq_scatter_offset_p_u32.c | 40 ++++++++++++---
> .../intrinsics/vstrbq_scatter_offset_p_u8.c | 40 ++++++++++++---
> .../intrinsics/vstrbq_scatter_offset_s16.c | 32 +++++++++---
> .../intrinsics/vstrbq_scatter_offset_s32.c | 32 +++++++++---
> .../mve/intrinsics/vstrbq_scatter_offset_s8.c | 32 +++++++++---
> .../intrinsics/vstrbq_scatter_offset_u16.c | 32 +++++++++---
> .../intrinsics/vstrbq_scatter_offset_u32.c | 32 +++++++++---
> .../mve/intrinsics/vstrbq_scatter_offset_u8.c | 32 +++++++++---
> .../arm/mve/intrinsics/vstrbq_u16.c | 32 +++++++++---
> .../arm/mve/intrinsics/vstrbq_u32.c | 32 +++++++++---
> .../gcc.target/arm/mve/intrinsics/vstrbq_u8.c | 32 +++++++++---
> .../arm/mve/intrinsics/vstrhq_f16.c | 32 +++++++++---
> .../arm/mve/intrinsics/vstrhq_p_f16.c | 40 ++++++++++++---
> .../arm/mve/intrinsics/vstrhq_p_s16.c | 40 ++++++++++++---
> .../arm/mve/intrinsics/vstrhq_p_s32.c | 40 ++++++++++++---
> .../arm/mve/intrinsics/vstrhq_p_u16.c | 40 ++++++++++++---
> .../arm/mve/intrinsics/vstrhq_p_u32.c | 40 ++++++++++++---
> .../arm/mve/intrinsics/vstrhq_s16.c | 32 +++++++++---
> .../arm/mve/intrinsics/vstrhq_s32.c | 32 +++++++++---
> .../intrinsics/vstrhq_scatter_offset_f16.c | 32 +++++++++---
> .../intrinsics/vstrhq_scatter_offset_p_f16.c | 40 ++++++++++++---
> .../intrinsics/vstrhq_scatter_offset_p_s16.c | 40 ++++++++++++---
> .../intrinsics/vstrhq_scatter_offset_p_s32.c | 40 ++++++++++++---
> .../intrinsics/vstrhq_scatter_offset_p_u16.c | 40 ++++++++++++---
> .../intrinsics/vstrhq_scatter_offset_p_u32.c | 40 ++++++++++++---
> .../intrinsics/vstrhq_scatter_offset_s16.c | 32 +++++++++---
> .../intrinsics/vstrhq_scatter_offset_s32.c | 32 +++++++++---
> .../intrinsics/vstrhq_scatter_offset_u16.c | 32 +++++++++---
> .../intrinsics/vstrhq_scatter_offset_u32.c | 32 +++++++++---
> .../vstrhq_scatter_shifted_offset_f16.c | 32 +++++++++---
> .../vstrhq_scatter_shifted_offset_p_f16.c | 40 ++++++++++++---
> .../vstrhq_scatter_shifted_offset_p_s16.c | 40 ++++++++++++---
> .../vstrhq_scatter_shifted_offset_p_s32.c | 40 ++++++++++++---
> .../vstrhq_scatter_shifted_offset_p_u16.c | 40 ++++++++++++---
> .../vstrhq_scatter_shifted_offset_p_u32.c | 40 ++++++++++++---
> .../vstrhq_scatter_shifted_offset_s16.c | 32 +++++++++---
> .../vstrhq_scatter_shifted_offset_s32.c | 32 +++++++++---
> .../vstrhq_scatter_shifted_offset_u16.c | 32 +++++++++---
> .../vstrhq_scatter_shifted_offset_u32.c | 32 +++++++++---
> .../arm/mve/intrinsics/vstrhq_u16.c | 32 +++++++++---
> .../arm/mve/intrinsics/vstrhq_u32.c | 32 +++++++++---
> 194 files changed, 5171 insertions(+), 1035 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c
> index 699e40d0e3b..f0a9243a6d5 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c
> @@ -1,20 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> float16x8_t
> -foo (float16_t const * base)
> +foo (float16_t const *base)
> {
> return vld1q_f16 (base);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> float16x8_t
> -foo1 (float16_t const * base)
> +foo1 (float16_t const *base)
> {
> return vld1q (base);
> }
>
> -/* { dg-final { scan-assembler-times "vldrh.16" 2 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c
> index 86592303362..129d256dd86 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c
> @@ -1,20 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> float32x4_t
> -foo (float32_t const * base)
> +foo (float32_t const *base)
> {
> return vld1q_f32 (base);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> float32x4_t
> -foo1 (float32_t const * base)
> +foo1 (float32_t const *base)
> {
> return vld1q (base);
> }
>
> -/* { dg-final { scan-assembler-times "vldrw.32" 2 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c
> index f4f04f534db..a95bf6c4260 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c
> @@ -1,20 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int16x8_t
> -foo (int16_t const * base)
> +foo (int16_t const *base)
> {
> return vld1q_s16 (base);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int16x8_t
> -foo1 (int16_t const * base)
> +foo1 (int16_t const *base)
> {
> return vld1q (base);
> }
>
> -/* { dg-final { scan-assembler-times "vldrh.16" 2 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c
> index e0f66166751..bb24e52d164 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c
> @@ -1,20 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (int32_t const * base)
> +foo (int32_t const *base)
> {
> return vld1q_s32 (base);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo1 (int32_t const * base)
> +foo1 (int32_t const *base)
> {
> return vld1q (base);
> }
>
> -/* { dg-final { scan-assembler-times "vldrw.32" 2 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c
> index 1b7edead6b1..0d89c2f19cd 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c
> @@ -1,20 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int8x16_t
> -foo (int8_t const * base)
> +foo (int8_t const *base)
> {
> return vld1q_s8 (base);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int8x16_t
> -foo1 (int8_t const * base)
> +foo1 (int8_t const *base)
> {
> return vld1q (base);
> }
>
> -/* { dg-final { scan-assembler-times "vldrb.8" 2 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c
> index 50e1f5cedcb..a31baf75fed 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c
> @@ -1,20 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo (uint16_t const * base)
> +foo (uint16_t const *base)
> {
> return vld1q_u16 (base);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo1 (uint16_t const * base)
> +foo1 (uint16_t const *base)
> {
> return vld1q (base);
> }
>
> -/* { dg-final { scan-assembler-times "vldrh.16" 2 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c
> index a13fe824382..7d4f858c784 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c
> @@ -1,20 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint32_t const * base)
> +foo (uint32_t const *base)
> {
> return vld1q_u32 (base);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo1 (uint32_t const * base)
> +foo1 (uint32_t const *base)
> {
> return vld1q (base);
> }
>
> -/* { dg-final { scan-assembler-times "vldrw.32" 2 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c
> index dfd1deb93f0..455ec5ce105 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c
> @@ -1,20 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint8x16_t
> -foo (uint8_t const * base)
> +foo (uint8_t const *base)
> {
> return vld1q_u8 (base);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint8x16_t
> -foo1 (uint8_t const * base)
> +foo1 (uint8_t const *base)
> {
> return vld1q (base);
> }
>
> -/* { dg-final { scan-assembler-times "vldrb.8" 2 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c
> index 3c32e408e42..951b795fd59 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> float16x8_t
> -foo (float16_t const * base, mve_pred16_t p)
> +foo (float16_t const *base, mve_pred16_t p)
> {
> return vld1q_z_f16 (base, p);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> float16x8_t
> -foo1 (float16_t const * base, mve_pred16_t p)
> +foo1 (float16_t const *base, mve_pred16_t p)
> {
> return vld1q_z (base, p);
> }
>
> -/* { dg-final { scan-assembler-times "vpst" 2 } } */
> -/* { dg-final { scan-assembler-times "vldrht.16" 2 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c
> index 3fc935c889b..4b43f0f4be3 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> float32x4_t
> -foo (float32_t const * base, mve_pred16_t p)
> +foo (float32_t const *base, mve_pred16_t p)
> {
> return vld1q_z_f32 (base, p);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> float32x4_t
> -foo1 (float32_t const * base, mve_pred16_t p)
> +foo1 (float32_t const *base, mve_pred16_t p)
> {
> return vld1q_z (base, p);
> }
>
> -/* { dg-final { scan-assembler-times "vpst" 2 } } */
> -/* { dg-final { scan-assembler-times "vldrwt.32" 2 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c
> index 49cc81092f3..a65c10c5fc1 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int16x8_t
> -foo (int16_t const * base, mve_pred16_t p)
> +foo (int16_t const *base, mve_pred16_t p)
> {
> return vld1q_z_s16 (base, p);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int16x8_t
> -foo1 (int16_t const * base, mve_pred16_t p)
> +foo1 (int16_t const *base, mve_pred16_t p)
> {
> return vld1q_z (base, p);
> }
>
> -/* { dg-final { scan-assembler-times "vpst" 2 } } */
> -/* { dg-final { scan-assembler-times "vldrht.16" 2 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c
> index ec317cd70e8..31749046fc6 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (int32_t const * base, mve_pred16_t p)
> +foo (int32_t const *base, mve_pred16_t p)
> {
> return vld1q_z_s32 (base, p);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo1 (int32_t const * base, mve_pred16_t p)
> +foo1 (int32_t const *base, mve_pred16_t p)
> {
> return vld1q_z (base, p);
> }
>
> -/* { dg-final { scan-assembler-times "vpst" 2 } } */
> -/* { dg-final { scan-assembler-times "vldrwt.32" 2 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c
> index 538c140e78e..990522faee8 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int8x16_t
> -foo (int8_t const * base, mve_pred16_t p)
> +foo (int8_t const *base, mve_pred16_t p)
> {
> return vld1q_z_s8 (base, p);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int8x16_t
> -foo1 (int8_t const * base, mve_pred16_t p)
> +foo1 (int8_t const *base, mve_pred16_t p)
> {
> return vld1q_z (base, p);
> }
>
> -/* { dg-final { scan-assembler-times "vpst" 2 } } */
> -/* { dg-final { scan-assembler-times "vldrbt.8" 2 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c
> index e5e588a187e..8a41b42306c 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo (uint16_t const * base, mve_pred16_t p)
> +foo (uint16_t const *base, mve_pred16_t p)
> {
> return vld1q_z_u16 (base, p);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo1 (uint16_t const * base, mve_pred16_t p)
> +foo1 (uint16_t const *base, mve_pred16_t p)
> {
> return vld1q_z (base, p);
> }
>
> -/* { dg-final { scan-assembler-times "vpst" 2 } } */
> -/* { dg-final { scan-assembler-times "vldrht.16" 2 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c
> index 999beefa7e8..67b200f6028 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint32_t const * base, mve_pred16_t p)
> +foo (uint32_t const *base, mve_pred16_t p)
> {
> return vld1q_z_u32 (base, p);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo1 (uint32_t const * base, mve_pred16_t p)
> +foo1 (uint32_t const *base, mve_pred16_t p)
> {
> return vld1q_z (base, p);
> }
>
> -/* { dg-final { scan-assembler-times "vpst" 2 } } */
> -/* { dg-final { scan-assembler-times "vldrwt.32" 2 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c
> index 172053c7142..c113a0db3e1 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint8x16_t
> -foo (uint8_t const * base, mve_pred16_t p)
> +foo (uint8_t const *base, mve_pred16_t p)
> {
> return vld1q_z_u8 (base, p);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint8x16_t
> -foo1 (uint8_t const * base, mve_pred16_t p)
> +foo1 (uint8_t const *base, mve_pred16_t p)
> {
> return vld1q_z (base, p);
> }
>
> -/* { dg-final { scan-assembler-times "vpst" 2 } } */
> -/* { dg-final { scan-assembler-times "vldrbt.8" 2 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c
> index db50f27bb60..e554cdab33d 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c
> @@ -1,24 +1,47 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> float16x8x4_t
> -foo (float16_t const * addr)
> +foo (float16_t const *addr)
> {
> return vld4q_f16 (addr);
> }
>
> -/* { dg-final { scan-assembler "vld40.16" } } */
> -/* { dg-final { scan-assembler "vld41.16" } } */
> -/* { dg-final { scan-assembler "vld42.16" } } */
> -/* { dg-final { scan-assembler "vld43.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> float16x8x4_t
> -foo1 (float16_t const * addr)
> +foo1 (float16_t const *addr)
> {
> return vld4q (addr);
> }
>
> -/* { dg-final { scan-assembler "vld40.16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c
> index de3fe0e79fc..be61054d331 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c
> @@ -1,24 +1,47 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> float32x4x4_t
> -foo (float32_t const * addr)
> +foo (float32_t const *addr)
> {
> return vld4q_f32 (addr);
> }
>
> -/* { dg-final { scan-assembler "vld40.32" } } */
> -/* { dg-final { scan-assembler "vld41.32" } } */
> -/* { dg-final { scan-assembler "vld42.32" } } */
> -/* { dg-final { scan-assembler "vld43.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> float32x4x4_t
> -foo1 (float32_t const * addr)
> +foo1 (float32_t const *addr)
> {
> return vld4q (addr);
> }
>
> -/* { dg-final { scan-assembler "vld40.32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c
> index 41a9dd86a4f..f9cbc17da61 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c
> @@ -1,24 +1,47 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> int16x8x4_t
> -foo (int16_t const * addr)
> +foo (int16_t const *addr)
> {
> return vld4q_s16 (addr);
> }
>
> -/* { dg-final { scan-assembler "vld40.16" } } */
> -/* { dg-final { scan-assembler "vld41.16" } } */
> -/* { dg-final { scan-assembler "vld42.16" } } */
> -/* { dg-final { scan-assembler "vld43.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> int16x8x4_t
> -foo1 (int16_t const * addr)
> +foo1 (int16_t const *addr)
> {
> return vld4q (addr);
> }
>
> -/* { dg-final { scan-assembler "vld40.16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c
> index 6f29c1b28c0..056e26023a9 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c
> @@ -1,24 +1,47 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> int32x4x4_t
> -foo (int32_t const * addr)
> +foo (int32_t const *addr)
> {
> return vld4q_s32 (addr);
> }
>
> -/* { dg-final { scan-assembler "vld40.32" } } */
> -/* { dg-final { scan-assembler "vld41.32" } } */
> -/* { dg-final { scan-assembler "vld42.32" } } */
> -/* { dg-final { scan-assembler "vld43.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> int32x4x4_t
> -foo1 (int32_t const * addr)
> +foo1 (int32_t const *addr)
> {
> return vld4q (addr);
> }
>
> -/* { dg-final { scan-assembler "vld40.32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c
> index 7701facb55c..2bec51ab4f6 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c
> @@ -1,24 +1,47 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> int8x16x4_t
> -foo (int8_t const * addr)
> +foo (int8_t const *addr)
> {
> return vld4q_s8 (addr);
> }
>
> -/* { dg-final { scan-assembler "vld40.8" } } */
> -/* { dg-final { scan-assembler "vld41.8" } } */
> -/* { dg-final { scan-assembler "vld42.8" } } */
> -/* { dg-final { scan-assembler "vld43.8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> int8x16x4_t
> -foo1 (int8_t const * addr)
> +foo1 (int8_t const *addr)
> {
> return vld4q (addr);
> }
>
> -/* { dg-final { scan-assembler "vld40.8" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c
> index 5a5e22d36d0..a2c98670174 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c
> @@ -1,24 +1,47 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> uint16x8x4_t
> -foo (uint16_t const * addr)
> +foo (uint16_t const *addr)
> {
> return vld4q_u16 (addr);
> }
>
> -/* { dg-final { scan-assembler "vld40.16" } } */
> -/* { dg-final { scan-assembler "vld41.16" } } */
> -/* { dg-final { scan-assembler "vld42.16" } } */
> -/* { dg-final { scan-assembler "vld43.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vld40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> uint16x8x4_t
> -foo1 (uint16_t const * addr)
> +foo1 (uint16_t const *addr)
> {
> return vld4q (addr);
> }
>
> -/* { dg-final { scan-assembler "vld40.16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c
> index e40d9b24fb4..4bbe56db205 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c
> @@ -1,24 +1,47 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> uint32x4x4_t
> -foo (uint32_t const * addr)
> +foo (uint32_t const *addr)
> {
> return vld4q_u32 (addr);
> }
>
> -/* { dg-final { scan-assembler "vld40.32" } } */
> -/* { dg-final { scan-assembler "vld41.32" } } */
> -/* { dg-final { scan-assembler "vld42.32" } } */
> -/* { dg-final { scan-assembler "vld43.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vld40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> uint32x4x4_t
> -foo1 (uint32_t const * addr)
> +foo1 (uint32_t const *addr)
> {
> return vld4q (addr);
> }
>
> -/* { dg-final { scan-assembler "vld40.32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c
> index 0d9abc36190..63353dba4b6 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c
> @@ -1,24 +1,47 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> uint8x16x4_t
> -foo (uint8_t const * addr)
> +foo (uint8_t const *addr)
> {
> return vld4q_u8 (addr);
> }
>
> -/* { dg-final { scan-assembler "vld40.8" } } */
> -/* { dg-final { scan-assembler "vld41.8" } } */
> -/* { dg-final { scan-assembler "vld42.8" } } */
> -/* { dg-final { scan-assembler "vld43.8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vld40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vld43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> uint8x16x4_t
> -foo1 (uint8_t const * addr)
> +foo1 (uint8_t const *addr)
> {
> return vld4q (addr);
> }
>
> -/* { dg-final { scan-assembler "vld40.8" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c
> index 0f6c24dde0a..ce4255b8430 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrb.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int16x8_t
> -foo (int8_t const * base, uint16x8_t offset)
> +foo (int8_t const *base, uint16x8_t offset)
> {
> return vldrbq_gather_offset_s16 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrb.s16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrb.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int16x8_t
> -foo1 (int8_t const * base, uint16x8_t offset)
> +foo1 (int8_t const *base, uint16x8_t offset)
> {
> return vldrbq_gather_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrb.s16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c
> index 4c1415d2c5f..cd5eb6b9e66 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrb.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (int8_t const * base, uint32x4_t offset)
> +foo (int8_t const *base, uint32x4_t offset)
> {
> return vldrbq_gather_offset_s32 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrb.s32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrb.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo1 (int8_t const * base, uint32x4_t offset)
> +foo1 (int8_t const *base, uint32x4_t offset)
> {
> return vldrbq_gather_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrb.s32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c
> index 4108bbae3e2..5ef4a895082 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int8x16_t
> -foo (int8_t const * base, uint8x16_t offset)
> +foo (int8_t const *base, uint8x16_t offset)
> {
> return vldrbq_gather_offset_s8 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrb.u8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int8x16_t
> -foo1 (int8_t const * base, uint8x16_t offset)
> +foo1 (int8_t const *base, uint8x16_t offset)
> {
> return vldrbq_gather_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrb.u8" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c
> index 5d5b005a8f4..cfec3c66a54 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrb.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo (uint8_t const * base, uint16x8_t offset)
> +foo (uint8_t const *base, uint16x8_t offset)
> {
> return vldrbq_gather_offset_u16 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrb.u16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrb.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo1 (uint8_t const * base, uint16x8_t offset)
> +foo1 (uint8_t const *base, uint16x8_t offset)
> {
> return vldrbq_gather_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrb.u16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c
> index 7c2d92b7c58..f416a03c325 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrb.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint8_t const * base, uint32x4_t offset)
> +foo (uint8_t const *base, uint32x4_t offset)
> {
> return vldrbq_gather_offset_u32 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrb.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrb.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo1 (uint8_t const * base, uint32x4_t offset)
> +foo1 (uint8_t const *base, uint32x4_t offset)
> {
> return vldrbq_gather_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrb.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c
> index 110f9db0296..e8bdd1eabb6 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint8x16_t
> -foo (uint8_t const * base, uint8x16_t offset)
> +foo (uint8_t const *base, uint8x16_t offset)
> {
> return vldrbq_gather_offset_u8 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrb.u8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrb.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint8x16_t
> -foo1 (uint8_t const * base, uint8x16_t offset)
> +foo1 (uint8_t const *base, uint8x16_t offset)
> {
> return vldrbq_gather_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrb.u8" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c
> index f0616b5ab8d..9a134609780 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int16x8_t
> -foo (int8_t const * base, uint16x8_t offset, mve_pred16_t p)
> +foo (int8_t const *base, uint16x8_t offset, mve_pred16_t p)
> {
> return vldrbq_gather_offset_z_s16 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrbt.s16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int16x8_t
> -foo1 (int8_t const * base, uint16x8_t offset, mve_pred16_t p)
> +foo1 (int8_t const *base, uint16x8_t offset, mve_pred16_t p)
> {
> return vldrbq_gather_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrbt.s16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c
> index 5bf291d4ba5..f47e02076b2 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (int8_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo (int8_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrbq_gather_offset_z_s32 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrbt.s32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo1 (int8_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo1 (int8_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrbq_gather_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrbt.s32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c
> index a3798a01b5f..e2b58b47f1d 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int8x16_t
> -foo (int8_t const * base, uint8x16_t offset, mve_pred16_t p)
> +foo (int8_t const *base, uint8x16_t offset, mve_pred16_t p)
> {
> return vldrbq_gather_offset_z_s8 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrbt.u8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int8x16_t
> -foo1 (int8_t const * base, uint8x16_t offset, mve_pred16_t p)
> +foo1 (int8_t const *base, uint8x16_t offset, mve_pred16_t p)
> {
> return vldrbq_gather_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrbt.u8" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c
> index 578bd15c66e..2a1801fc941 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo (uint8_t const * base, uint16x8_t offset, mve_pred16_t p)
> +foo (uint8_t const *base, uint16x8_t offset, mve_pred16_t p)
> {
> return vldrbq_gather_offset_z_u16 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrbt.u16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo1 (uint8_t const * base, uint16x8_t offset, mve_pred16_t p)
> +foo1 (uint8_t const *base, uint16x8_t offset, mve_pred16_t p)
> {
> return vldrbq_gather_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrbt.u16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c
> index a58044af176..c415fe26ba8 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint8_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo (uint8_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrbq_gather_offset_z_u32 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrbt.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo1 (uint8_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo1 (uint8_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrbq_gather_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrbt.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c
> index 0e06833961b..90a19680999 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint8x16_t
> -foo (uint8_t const * base, uint8x16_t offset, mve_pred16_t p)
> +foo (uint8_t const *base, uint8x16_t offset, mve_pred16_t p)
> {
> return vldrbq_gather_offset_z_u8 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrbt.u8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.u8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint8x16_t
> -foo1 (uint8_t const * base, uint8x16_t offset, mve_pred16_t p)
> +foo1 (uint8_t const *base, uint8x16_t offset, mve_pred16_t p)
> {
> return vldrbq_gather_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrbt.u8" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c
> index 4403092b988..c54e04dbdda 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c
> @@ -1,13 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrb.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int16x8_t
> -foo (int8_t const * base)
> +foo (int8_t const *base)
> {
> return vldrbq_s16 (base);
> }
>
> -/* { dg-final { scan-assembler "vldrb.s16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c
> index 95ea9364ffc..1623f53d971 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c
> @@ -1,13 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrb.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (int8_t const * base)
> +foo (int8_t const *base)
> {
> return vldrbq_s32 (base);
> }
>
> -/* { dg-final { scan-assembler "vldrb.s32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c
> index ec2f2176ccf..b1c141ae287 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c
> @@ -1,14 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int8x16_t
> -foo (int8_t const * base)
> +foo (int8_t const *base)
> {
> return vldrbq_s8 (base);
> }
>
> -/* { dg-final { scan-assembler-times "vldrb.8" 1 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c
> index 2fb297f92ad..203e2e9de83 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c
> @@ -1,13 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrb.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo (uint8_t const * base)
> +foo (uint8_t const *base)
> {
> return vldrbq_u16 (base);
> }
>
> -/* { dg-final { scan-assembler "vldrb.u16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c
> index dc555c1be2d..2005c3a2bbf 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c
> @@ -1,13 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrb.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint8_t const * base)
> +foo (uint8_t const *base)
> {
> return vldrbq_u32 (base);
> }
>
> -/* { dg-final { scan-assembler "vldrb.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c
> index d07b472a4ff..b4c109eb147 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c
> @@ -1,14 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint8x16_t
> -foo (uint8_t const * base)
> +foo (uint8_t const *base)
> {
> return vldrbq_u8 (base);
> }
>
> -/* { dg-final { scan-assembler-times "vldrb.8" 1 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c
> index 8bd08ab5cff..813f6a31a25 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c
> @@ -1,13 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.s16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int16x8_t
> -foo (int8_t const * base, mve_pred16_t p)
> +foo (int8_t const *base, mve_pred16_t p)
> {
> return vldrbq_z_s16 (base, p);
> }
>
> -/* { dg-final { scan-assembler "vldrbt.s16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c
> index 0309ff4111b..10e1dbf6ad9 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c
> @@ -1,13 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (int8_t const * base, mve_pred16_t p)
> +foo (int8_t const *base, mve_pred16_t p)
> {
> return vldrbq_z_s32 (base, p);
> }
>
> -/* { dg-final { scan-assembler "vldrbt.s32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c
> index aed3c910063..de361d4c9a0 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c
> @@ -1,15 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int8x16_t
> -foo (int8_t const * base, mve_pred16_t p)
> +foo (int8_t const *base, mve_pred16_t p)
> {
> return vldrbq_z_s8 (base, p);
> }
>
> -/* { dg-final { scan-assembler-times "vpst" 1 } } */
> -/* { dg-final { scan-assembler-times "vldrbt.8" 1 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c
> index adcb0cfa2ae..ba4401045e7 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c
> @@ -1,13 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo (uint8_t const * base, mve_pred16_t p)
> +foo (uint8_t const *base, mve_pred16_t p)
> {
> return vldrbq_z_u16 (base, p);
> }
>
> -/* { dg-final { scan-assembler "vldrbt.u16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c
> index 6b7bce60d62..adc88a59a71 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c
> @@ -1,13 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint8_t const * base, mve_pred16_t p)
> +foo (uint8_t const *base, mve_pred16_t p)
> {
> return vldrbq_z_u32 (base, p);
> }
>
> -/* { dg-final { scan-assembler "vldrbt.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c
> index 54c61e74454..b13d9fb426f 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c
> @@ -1,15 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint8x16_t
> -foo (uint8_t const * base, mve_pred16_t p)
> +foo (uint8_t const *base, mve_pred16_t p)
> {
> return vldrbq_z_u8 (base, p);
> }
>
> -/* { dg-final { scan-assembler-times "vpst" 1 } } */
> -/* { dg-final { scan-assembler-times "vldrbt.8" 1 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c
> index 6499f930c40..3539c1e40ba 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c
> @@ -1,13 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> int64x2_t
> foo (uint64x2_t addr)
> {
> - return vldrdq_gather_base_s64 (addr, 8);
> + return vldrdq_gather_base_s64 (addr, 0);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vldrd.64" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c
> index 9a11638a261..2245df61a4e 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c
> @@ -1,13 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint64x2_t
> foo (uint64x2_t addr)
> {
> - return vldrdq_gather_base_u64 (addr, 8);
> + return vldrdq_gather_base_u64 (addr, 0);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vldrd.64" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c
> index a9b1f81b62d..e3fd7f16a31 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c
> @@ -1,16 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> int64x2_t
> -foo (uint64x2_t * addr)
> +foo (uint64x2_t *addr)
> {
> - return vldrdq_gather_base_wb_s64 (addr, 8);
> + return vldrdq_gather_base_wb_s64 (addr, 0);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-
> 9\]+\\\]!" } } */
> -/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
> -/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c
> index e32a06695ae..161cf00b65e 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c
> @@ -1,16 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrd.64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> uint64x2_t
> -foo (uint64x2_t * addr)
> +foo (uint64x2_t *addr)
> {
> - return vldrdq_gather_base_wb_u64 (addr, 8);
> + return vldrdq_gather_base_wb_u64 (addr, 0);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-
> 9\]+\\\]!" } } */
> -/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
> -/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.
> c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.
> c
> index bb06cf88e32..0716baa635a 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.
> c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.
> c
> @@ -1,15 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> #include "arm_mve.h"
>
> -int64x2_t foo (uint64x2_t * addr, mve_pred16_t p)
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> +int64x2_t
> +foo (uint64x2_t *addr, mve_pred16_t p)
> {
> - return vldrdq_gather_base_wb_z_s64 (addr, 1016, p);
> + return vldrdq_gather_base_wb_z_s64 (addr, 0, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vpst" } } */
> -/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-
> 9\]+\\\]!" } } */
> -/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
> -/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.
> c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.
> c
> index 558115d49ef..242c7c06e27 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.
> c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.
> c
> @@ -1,15 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> #include "arm_mve.h"
>
> -uint64x2_t foo (uint64x2_t * addr, mve_pred16_t p)
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> +uint64x2_t
> +foo (uint64x2_t *addr, mve_pred16_t p)
> {
> - return vldrdq_gather_base_wb_z_u64 (addr, 8, p);
> + return vldrdq_gather_base_wb_z_u64 (addr, 0, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vpst" } } */
> -/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-
> 9\]+\\\]!" } } */
> -/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
> -/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c
> index d7455b49206..d451f4e693f 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c
> @@ -1,13 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> int64x2_t
> foo (uint64x2_t addr, mve_pred16_t p)
> {
> - return vldrdq_gather_base_z_s64 (addr, 8, p);
> + return vldrdq_gather_base_z_s64 (addr, 0, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vldrdt.u64" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c
> index 07f72d422b4..508db3ca538 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c
> @@ -1,13 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint64x2_t
> foo (uint64x2_t addr, mve_pred16_t p)
> {
> - return vldrdq_gather_base_z_u64 (addr, 8, p);
> + return vldrdq_gather_base_z_u64 (addr, 0, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vldrdt.u64" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c
> index 1d2d904efc4..9431491f3fd 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int64x2_t
> -foo (int64_t const * base, uint64x2_t offset)
> +foo (int64_t const *base, uint64x2_t offset)
> {
> return vldrdq_gather_offset_s64 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrd.u64" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int64x2_t
> -foo1 (int64_t const * base, uint64x2_t offset)
> +foo1 (int64_t const *base, uint64x2_t offset)
> {
> return vldrdq_gather_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrd.u64" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c
> index 49a3b134d2f..11c0872f5a7 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint64x2_t
> -foo (uint64_t const * base, uint64x2_t offset)
> +foo (uint64_t const *base, uint64x2_t offset)
> {
> return vldrdq_gather_offset_u64 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrd.u64" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint64x2_t
> -foo1 (uint64_t const * base, uint64x2_t offset)
> +foo1 (uint64_t const *base, uint64x2_t offset)
> {
> return vldrdq_gather_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrd.u64" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c
> index 1ff5f2acd1b..f474cbef788 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int64x2_t
> -foo (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
> +foo (int64_t const *base, uint64x2_t offset, mve_pred16_t p)
> {
> return vldrdq_gather_offset_z_s64 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrdt.u64" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int64x2_t
> -foo1 (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
> +foo1 (int64_t const *base, uint64x2_t offset, mve_pred16_t p)
> {
> return vldrdq_gather_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrdt.u64" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c
> index 63b2254d171..19136d7f451 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint64x2_t
> -foo (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
> +foo (uint64_t const *base, uint64x2_t offset, mve_pred16_t p)
> {
> return vldrdq_gather_offset_z_u64 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrdt.u64" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint64x2_t
> -foo1 (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
> +foo1 (uint64_t const *base, uint64x2_t offset, mve_pred16_t p)
> {
> return vldrdq_gather_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrdt.u64" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s
> 64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s
> 64.c
> index 4feb9c06fcd..ad11d8fa5cb 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s
> 64.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s
> 64.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:
> @.*|)
> +** ...
> +*/
> int64x2_t
> -foo (int64_t const * base, uint64x2_t offset)
> +foo (int64_t const *base, uint64x2_t offset)
> {
> return vldrdq_gather_shifted_offset_s64 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrd.u64" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:
> @.*|)
> +** ...
> +*/
> int64x2_t
> -foo1 (int64_t const * base, uint64x2_t offset)
> +foo1 (int64_t const *base, uint64x2_t offset)
> {
> return vldrdq_gather_shifted_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrd.u64" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u
> 64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u
> 64.c
> index 999735039c8..a466494974b 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u
> 64.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u
> 64.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:
> @.*|)
> +** ...
> +*/
> uint64x2_t
> -foo (uint64_t const * base, uint64x2_t offset)
> +foo (uint64_t const *base, uint64x2_t offset)
> {
> return vldrdq_gather_shifted_offset_u64 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrd.u64" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrd.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:
> @.*|)
> +** ...
> +*/
> uint64x2_t
> -foo1 (uint64_t const * base, uint64x2_t offset)
> +foo1 (uint64_t const *base, uint64x2_t offset)
> {
> return vldrdq_gather_shifted_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrd.u64" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z
> _s64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z
> _s64.c
> index 77303a47a08..3555105d09e 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z
> _s64.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z
> _s64.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:
> @.*|)
> +** ...
> +*/
> int64x2_t
> -foo (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
> +foo (int64_t const *base, uint64x2_t offset, mve_pred16_t p)
> {
> return vldrdq_gather_shifted_offset_z_s64 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrdt.u64" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:
> @.*|)
> +** ...
> +*/
> int64x2_t
> -foo1 (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
> +foo1 (int64_t const *base, uint64x2_t offset, mve_pred16_t p)
> {
> return vldrdq_gather_shifted_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrdt.u64" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z
> _u64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z
> _u64.c
> index 0273b242031..f7cfbfcddb3 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z
> _u64.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z
> _u64.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:
> @.*|)
> +** ...
> +*/
> uint64x2_t
> -foo (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
> +foo (uint64_t const *base, uint64x2_t offset, mve_pred16_t p)
> {
> return vldrdq_gather_shifted_offset_z_u64 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrdt.u64" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrdt.u64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:
> @.*|)
> +** ...
> +*/
> uint64x2_t
> -foo1 (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
> +foo1 (uint64_t const *base, uint64x2_t offset, mve_pred16_t p)
> {
> return vldrdq_gather_shifted_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrdt.u64" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c
> index 05bef418d82..87c746f4ad7 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c
> @@ -1,14 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> float16x8_t
> -foo (float16_t const * base)
> +foo (float16_t const *base)
> {
> return vldrhq_f16 (base);
> }
>
> -/* { dg-final { scan-assembler-times "vldrh.16" 1 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c
> index 525e54c72f5..287276e41f9 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> float16x8_t
> -foo (float16_t const * base, uint16x8_t offset)
> +foo (float16_t const *base, uint16x8_t offset)
> {
> return vldrhq_gather_offset_f16 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.f16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> float16x8_t
> -foo1 (float16_t const * base, uint16x8_t offset)
> +foo1 (float16_t const *base, uint16x8_t offset)
> {
> return vldrhq_gather_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.f16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c
> index 47ef03445b4..e2493a62b3a 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int16x8_t
> -foo (int16_t const * base, uint16x8_t offset)
> +foo (int16_t const *base, uint16x8_t offset)
> {
> return vldrhq_gather_offset_s16 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.u16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int16x8_t
> -foo1 (int16_t const * base, uint16x8_t offset)
> +foo1 (int16_t const *base, uint16x8_t offset)
> {
> return vldrhq_gather_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.u16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c
> index 39379aaedd3..5d1e348cc86 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (int16_t const * base, uint32x4_t offset)
> +foo (int16_t const *base, uint32x4_t offset)
> {
> return vldrhq_gather_offset_s32 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.s32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo1 (int16_t const * base, uint32x4_t offset)
> +foo1 (int16_t const *base, uint32x4_t offset)
> {
> return vldrhq_gather_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.s32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c
> index fa345e24b48..6d5f6f877dc 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo (uint16_t const * base, uint16x8_t offset)
> +foo (uint16_t const *base, uint16x8_t offset)
> {
> return vldrhq_gather_offset_u16 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.u16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo1 (uint16_t const * base, uint16x8_t offset)
> +foo1 (uint16_t const *base, uint16x8_t offset)
> {
> return vldrhq_gather_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.u16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c
> index b888660dc37..c39afbe6119 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint16_t const * base, uint32x4_t offset)
> +foo (uint16_t const *base, uint32x4_t offset)
> {
> return vldrhq_gather_offset_u32 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo1 (uint16_t const * base, uint32x4_t offset)
> +foo1 (uint16_t const *base, uint32x4_t offset)
> {
> return vldrhq_gather_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c
> index 7ee84232f04..53c673e3644 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> float16x8_t
> -foo (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
> +foo (float16_t const *base, uint16x8_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_offset_z_f16 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.f16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> float16x8_t
> -foo1 (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
> +foo1 (float16_t const *base, uint16x8_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.f16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c
> index 9b354fad50d..1e68a77824e 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int16x8_t
> -foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
> +foo (int16_t const *base, uint16x8_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_offset_z_s16 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.u16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int16x8_t
> -foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
> +foo1 (int16_t const *base, uint16x8_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.u16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c
> index 0e252291944..06c208f31c5 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo (int16_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_offset_z_s32 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.s32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo1 (int16_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.s32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c
> index 763e33d90bb..f50f026b00e 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
> +foo (uint16_t const *base, uint16x8_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_offset_z_u16 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.u16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
> +foo1 (uint16_t const *base, uint16x8_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.u16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c
> index 36baa252aa4..eff32dc6718 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo (uint16_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_offset_z_u32 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo1 (uint16_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f
> 16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f
> 16.c
> index 843904a7041..f8468be41fa 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f
> 16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f
> 16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> float16x8_t
> -foo (float16_t const * base, uint16x8_t offset)
> +foo (float16_t const *base, uint16x8_t offset)
> {
> return vldrhq_gather_shifted_offset_f16 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.f16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrh.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> float16x8_t
> -foo1 (float16_t const * base, uint16x8_t offset)
> +foo1 (float16_t const *base, uint16x8_t offset)
> {
> return vldrhq_gather_shifted_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.f16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s
> 16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s
> 16.c
> index 6d013c835b5..ac2491ea143 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s
> 16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s
> 16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> int16x8_t
> -foo (int16_t const * base, uint16x8_t offset)
> +foo (int16_t const *base, uint16x8_t offset)
> {
> return vldrhq_gather_shifted_offset_s16 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.u16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> int16x8_t
> -foo1 (int16_t const * base, uint16x8_t offset)
> +foo1 (int16_t const *base, uint16x8_t offset)
> {
> return vldrhq_gather_shifted_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.u16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s
> 32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s
> 32.c
> index 5ec8e8c1dc8..6919b3a3cc2 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s
> 32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s
> 32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (int16_t const * base, uint32x4_t offset)
> +foo (int16_t const *base, uint32x4_t offset)
> {
> return vldrhq_gather_shifted_offset_s32 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.s32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> int32x4_t
> -foo1 (int16_t const * base, uint32x4_t offset)
> +foo1 (int16_t const *base, uint32x4_t offset)
> {
> return vldrhq_gather_shifted_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.s32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u
> 16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u
> 16.c
> index fa5f3d04548..7e8fdf3799d 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u
> 16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u
> 16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo (uint16_t const * base, uint16x8_t offset)
> +foo (uint16_t const *base, uint16x8_t offset)
> {
> return vldrhq_gather_shifted_offset_u16 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.u16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrh.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo1 (uint16_t const * base, uint16x8_t offset)
> +foo1 (uint16_t const *base, uint16x8_t offset)
> {
> return vldrhq_gather_shifted_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.u16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u
> 32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u
> 32.c
> index 227b18d7864..de2d22d985d 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u
> 32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u
> 32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint16_t const * base, uint32x4_t offset)
> +foo (uint16_t const *base, uint32x4_t offset)
> {
> return vldrhq_gather_shifted_offset_u32 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo1 (uint16_t const * base, uint32x4_t offset)
> +foo1 (uint16_t const *base, uint32x4_t offset)
> {
> return vldrhq_gather_shifted_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrh.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _f16.c
> index cae37837c7e..a55ada003ed 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _f16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _f16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> float16x8_t
> -foo (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
> +foo (float16_t const *base, uint16x8_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_shifted_offset_z_f16 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.f16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.f16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> float16x8_t
> -foo1 (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
> +foo1 (float16_t const *base, uint16x8_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_shifted_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.f16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _s16.c
> index 1aff290a6b0..ee57d77e3db 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _s16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _s16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> int16x8_t
> -foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
> +foo (int16_t const *base, uint16x8_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_shifted_offset_z_s16 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.u16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> int16x8_t
> -foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
> +foo1 (int16_t const *base, uint16x8_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_shifted_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.u16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _s32.c
> index 92ee073adf9..9f8963f56bc 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _s32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo (int16_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_shifted_offset_z_s32 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.s32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> int32x4_t
> -foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo1 (int16_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_shifted_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.s32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _u16.c
> index 792510d3639..90be7020ac2 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _u16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _u16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
> +foo (uint16_t const *base, uint16x8_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_shifted_offset_z_u16 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.u16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.u16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
> +foo1 (uint16_t const *base, uint16x8_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_shifted_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.u16" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _u32.c
> index 8ae845418e8..0ff6d021b51 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z
> _u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo (uint16_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_shifted_offset_z_u32 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo1 (uint16_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrhq_gather_shifted_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrht.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c
> index 7c977b6a699..107ce22856b 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c
> @@ -1,14 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int16x8_t
> -foo (int16_t const * base)
> +foo (int16_t const *base)
> {
> return vldrhq_s16 (base);
> }
>
> -/* { dg-final { scan-assembler-times "vldrh.16" 1 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c
> index 229b52163fa..5cc864c38e4 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c
> @@ -1,14 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrh.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (int16_t const * base)
> +foo (int16_t const *base)
> {
> return vldrhq_s32 (base);
> }
>
> -/* { dg-final { scan-assembler-times "vldrh.s32" 1 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c
> index 07f6d9e3944..12f807da03b 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c
> @@ -1,14 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo (uint16_t const * base)
> +foo (uint16_t const *base)
> {
> return vldrhq_u16 (base);
> }
>
> -/* { dg-final { scan-assembler-times "vldrh.16" 1 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c
> index cd24f01831f..5d4f34f9789 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c
> @@ -1,14 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrh.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint16_t const * base)
> +foo (uint16_t const *base)
> {
> return vldrhq_u32 (base);
> }
>
> -/* { dg-final { scan-assembler-times "vldrh.u32" 1 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c
> index dd0fc9c7b73..582061bbab3 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c
> @@ -1,15 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> float16x8_t
> -foo (float16_t const * base, mve_pred16_t p)
> +foo (float16_t const *base, mve_pred16_t p)
> {
> return vldrhq_z_f16 (base, p);
> }
>
> -/* { dg-final { scan-assembler-times "vpst" 1 } } */
> -/* { dg-final { scan-assembler-times "vldrht.16" 1 } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> /* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c
> index 36d3458d95c..dc32460ccdd 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c
> @@ -1,15 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int16x8_t
> -foo (int16_t const * base, mve_pred16_t p)
> +foo (int16_t const *base, mve_pred16_t p)
> {
> return vldrhq_z_s16 (base, p);
> }
>
> -/* { dg-final { scan-assembler-times "vpst" 1 } } */
> -/* { dg-final { scan-assembler-times "vldrht.16" 1 } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> /* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c
> index 9c67b479be7..15dd77cb36c 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c
> @@ -1,15 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.s32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (int16_t const * base, mve_pred16_t p)
> +foo (int16_t const *base, mve_pred16_t p)
> {
> return vldrhq_z_s32 (base, p);
> }
>
> -/* { dg-final { scan-assembler-times "vpst" 1 } } */
> -/* { dg-final { scan-assembler-times "vldrht.s32" 1 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c
> index 26354b5971a..91ab2caf1c6 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c
> @@ -1,15 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint16x8_t
> -foo (uint16_t const * base, mve_pred16_t p)
> +foo (uint16_t const *base, mve_pred16_t p)
> {
> return vldrhq_z_u16 (base, p);
> }
>
> -/* { dg-final { scan-assembler-times "vpst" 1 } } */
> -/* { dg-final { scan-assembler-times "vldrht.16" 1 } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> /* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c
> index 948fe5ee5b4..1682ec1987a 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c
> @@ -1,15 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrht.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint16_t const * base, mve_pred16_t p)
> +foo (uint16_t const *base, mve_pred16_t p)
> {
> return vldrhq_z_u32 (base, p);
> }
>
> -/* { dg-final { scan-assembler-times "vpst" 1 } } */
> -/* { dg-final { scan-assembler-times "vldrht.u32" 1 } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c
> index 143079aa23f..9cf47332b38 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c
> @@ -1,14 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> float32x4_t
> -foo (float32_t const * base)
> +foo (float32_t const *base)
> {
> return vldrwq_f32 (base);
> }
>
> -/* { dg-final { scan-assembler-times "vldrw.32" 1 } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> /* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c
> index 5e0faaad8dd..c3f052efbc6 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c
> @@ -1,13 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> float32x4_t
> foo (uint32x4_t addr)
> {
> - return vldrwq_gather_base_f32 (addr, 4);
> + return vldrwq_gather_base_f32 (addr, 0);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vldrw.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c
> index 8ca44199e3e..f2dbcfb9f6e 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c
> @@ -1,13 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> foo (uint32x4_t addr)
> {
> - return vldrwq_gather_base_s32 (addr, 4);
> + return vldrwq_gather_base_s32 (addr, 0);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vldrw.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c
> index 3c3e90f1c0a..0926689805f 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c
> @@ -1,13 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> foo (uint32x4_t addr)
> {
> - return vldrwq_gather_base_u32 (addr, 4);
> + return vldrwq_gather_base_u32 (addr, 0);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vldrw.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c
> index 8e2994f75d7..f9cd0a3ffe0 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c
> @@ -1,16 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> float32x4_t
> -foo (uint32x4_t * addr)
> +foo (uint32x4_t *addr)
> {
> - return vldrwq_gather_base_wb_f32 (addr, 8);
> + return vldrwq_gather_base_wb_f32 (addr, 0);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
> -/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-
> 9\]+\\\]!" } } */
> -/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
> /* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c
> index e5054738b75..b8f16969a31 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c
> @@ -1,16 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (uint32x4_t * addr)
> +foo (uint32x4_t *addr)
> {
> - return vldrwq_gather_base_wb_s32 (addr, 8);
> + return vldrwq_gather_base_wb_s32 (addr, 0);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
> -/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-
> 9\]+\\\]!" } } */
> -/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
> /* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c
> index 7f39414143b..387d0115f46 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c
> @@ -1,16 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint32x4_t * addr)
> +foo (uint32x4_t *addr)
> {
> - return vldrwq_gather_base_wb_u32 (addr, 8);
> + return vldrwq_gather_base_wb_u32 (addr, 0);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
> -/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-
> 9\]+\\\]!" } } */
> -/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
> /* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.
> c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.
> c
> index 1e57ca40739..bea7ecdee83 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.
> c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.
> c
> @@ -1,18 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> float32x4_t
> -foo (uint32x4_t * addr, mve_pred16_t p)
> +foo (uint32x4_t *addr, mve_pred16_t p)
> {
> - return vldrwq_gather_base_wb_z_f32 (addr, 8, p);
> + return vldrwq_gather_base_wb_z_f32 (addr, 0, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
> -/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */
> -/* { dg-final { scan-assembler "vpst" } } */
> -/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-
> 9\]+\\\]!" } } */
> -/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
> /* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32
> .c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32
> .c
> index f8d77fdfd5b..4469ac14a0a 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32
> .c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32
> .c
> @@ -1,18 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (uint32x4_t * addr, mve_pred16_t p)
> +foo (uint32x4_t *addr, mve_pred16_t p)
> {
> - return vldrwq_gather_base_wb_z_s32 (addr, 8, p);
> + return vldrwq_gather_base_wb_z_s32 (addr, 0, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
> -/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */
> -/* { dg-final { scan-assembler "vpst" } } */
> -/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-
> 9\]+\\\]!" } } */
> -/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
> /* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32
> .c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32
> .c
> index 8a0e109c70c..9d4d81b3afe 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32
> .c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32
> .c
> @@ -1,18 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint32x4_t * addr, mve_pred16_t p)
> +foo (uint32x4_t *addr, mve_pred16_t p)
> {
> - return vldrwq_gather_base_wb_z_u32 (addr, 8, p);
> + return vldrwq_gather_base_wb_z_u32 (addr, 0, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
> -/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */
> -/* { dg-final { scan-assembler "vpst" } } */
> -/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-
> 9\]+\\\]!" } } */
> -/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
> /* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c
> index 81aac523728..905000a31a8 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c
> @@ -1,13 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> float32x4_t
> foo (uint32x4_t addr, mve_pred16_t p)
> {
> - return vldrwq_gather_base_z_f32 (addr, 4, p);
> + return vldrwq_gather_base_z_f32 (addr, 0, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vldrwt.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c
> index fec49bbde06..3ee6a219b80 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c
> @@ -1,13 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> foo (uint32x4_t addr, mve_pred16_t p)
> {
> - return vldrwq_gather_base_z_s32 (addr, 4, p);
> + return vldrwq_gather_base_z_s32 (addr, 0, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vldrwt.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c
> index b64a11d6620..488adf58b78 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c
> @@ -1,13 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> foo (uint32x4_t addr, mve_pred16_t p)
> {
> - return vldrwq_gather_base_z_u32 (addr, 4, p);
> + return vldrwq_gather_base_z_u32 (addr, 0, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vldrwt.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c
> index 6a4ea041137..a513452a12d 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> float32x4_t
> -foo (float32_t const * base, uint32x4_t offset)
> +foo (float32_t const *base, uint32x4_t offset)
> {
> return vldrwq_gather_offset_f32 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrw.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> float32x4_t
> -foo1 (float32_t const * base, uint32x4_t offset)
> +foo1 (float32_t const *base, uint32x4_t offset)
> {
> return vldrwq_gather_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrw.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c
> index ee15fa4a0b0..57ad6583153 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (int32_t const * base, uint32x4_t offset)
> +foo (int32_t const *base, uint32x4_t offset)
> {
> return vldrwq_gather_offset_s32 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrw.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo1 (int32_t const * base, uint32x4_t offset)
> +foo1 (int32_t const *base, uint32x4_t offset)
> {
> return vldrwq_gather_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrw.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c
> index d344779058f..30fc36c6f97 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint32_t const * base, uint32x4_t offset)
> +foo (uint32_t const *base, uint32x4_t offset)
> {
> return vldrwq_gather_offset_u32 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrw.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo1 (uint32_t const * base, uint32x4_t offset)
> +foo1 (uint32_t const *base, uint32x4_t offset)
> {
> return vldrwq_gather_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrw.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c
> index 93253119418..1f84edcdb8e 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> float32x4_t
> -foo (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo (float32_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrwq_gather_offset_z_f32 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrwt.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> float32x4_t
> -foo1 (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo1 (float32_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrwq_gather_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrwt.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c
> index 4537427bef3..3fe5a986cc3 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo (int32_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrwq_gather_offset_z_s32 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrwt.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo1 (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo1 (int32_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrwq_gather_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrwt.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c
> index e59c4c996bf..087e5d0ce1e 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo (uint32_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrwq_gather_offset_z_u32 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrwt.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo1 (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo1 (uint32_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrwq_gather_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrwt.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f
> 32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f
> 32.c
> index 1ba2cb0ccde..bed16f5fa72 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f
> 32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f
> 32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> float32x4_t
> -foo (float32_t const * base, uint32x4_t offset)
> +foo (float32_t const *base, uint32x4_t offset)
> {
> return vldrwq_gather_shifted_offset_f32 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrw.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> float32x4_t
> -foo1 (float32_t const * base, uint32x4_t offset)
> +foo1 (float32_t const *base, uint32x4_t offset)
> {
> return vldrwq_gather_shifted_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrw.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s
> 32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s
> 32.c
> index 39d976bb676..e6c589020f3 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s
> 32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s
> 32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (int32_t const * base, uint32x4_t offset)
> +foo (int32_t const *base, uint32x4_t offset)
> {
> return vldrwq_gather_shifted_offset_s32 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrw.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> int32x4_t
> -foo1 (int32_t const * base, uint32x4_t offset)
> +foo1 (int32_t const *base, uint32x4_t offset)
> {
> return vldrwq_gather_shifted_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrw.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u
> 32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u
> 32.c
> index 971f482dfff..8e287da0dbf 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u
> 32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u
> 32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint32_t const * base, uint32x4_t offset)
> +foo (uint32_t const *base, uint32x4_t offset)
> {
> return vldrwq_gather_shifted_offset_u32 (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrw.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vldrw.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo1 (uint32_t const * base, uint32x4_t offset)
> +foo1 (uint32_t const *base, uint32x4_t offset)
> {
> return vldrwq_gather_shifted_offset (base, offset);
> }
>
> -/* { dg-final { scan-assembler "vldrw.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z
> _f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z
> _f32.c
> index e4110cd50aa..f69d67fd2aa 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z
> _f32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z
> _f32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> float32x4_t
> -foo (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo (float32_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrwq_gather_shifted_offset_z_f32 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrwt.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> float32x4_t
> -foo1 (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo1 (float32_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrwq_gather_shifted_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrwt.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z
> _s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z
> _s32.c
> index 71dd8a757ce..3aff6de03b6 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z
> _s32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z
> _s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo (int32_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrwq_gather_shifted_offset_z_s32 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrwt.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> int32x4_t
> -foo1 (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo1 (int32_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrwq_gather_shifted_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrwt.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z
> _u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z
> _u32.c
> index f95d6f0f708..ed8873d0c53 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z
> _u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z
> _u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo (uint32_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrwq_gather_shifted_offset_z_u32 (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrwt.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.u32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo1 (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
> +foo1 (uint32_t const *base, uint32x4_t offset, mve_pred16_t p)
> {
> return vldrwq_gather_shifted_offset_z (base, offset, p);
> }
>
> -/* { dg-final { scan-assembler "vldrwt.u32" } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c
> index 860dd324d25..87c3ac9f9d2 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c
> @@ -1,14 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (int32_t const * base)
> +foo (int32_t const *base)
> {
> return vldrwq_s32 (base);
> }
>
> -/* { dg-final { scan-assembler-times "vldrw.32" 1 } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> /* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c
> index 513ed49fb6e..5b560c534a1 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c
> @@ -1,14 +1,28 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vldrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint32_t const * base)
> +foo (uint32_t const *base)
> {
> return vldrwq_u32 (base);
> }
>
> -/* { dg-final { scan-assembler-times "vldrw.32" 1 } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> /* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c
> index 3e0a6a60bcf..14a61fcfbd4 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c
> @@ -1,15 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> float32x4_t
> -foo (float32_t const * base, mve_pred16_t p)
> +foo (float32_t const *base, mve_pred16_t p)
> {
> return vldrwq_z_f32 (base, p);
> }
>
> -/* { dg-final { scan-assembler-times "vpst" 1 } } */
> -/* { dg-final { scan-assembler-times "vldrwt.32" 1 } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> /* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c
> index 82b914885b5..5c90707becc 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c
> @@ -1,15 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> int32x4_t
> -foo (int32_t const * base, mve_pred16_t p)
> +foo (int32_t const *base, mve_pred16_t p)
> {
> return vldrwq_z_s32 (base, p);
> }
>
> -/* { dg-final { scan-assembler-times "vpst" 1 } } */
> -/* { dg-final { scan-assembler-times "vldrwt.32" 1 } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> /* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c
> index 6a66e167881..16b50335fe7 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c
> @@ -1,15 +1,32 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vldrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> uint32x4_t
> -foo (uint32_t const * base, mve_pred16_t p)
> +foo (uint32_t const *base, mve_pred16_t p)
> {
> return vldrwq_z_u32 (base, p);
> }
>
> -/* { dg-final { scan-assembler-times "vpst" 1 } } */
> -/* { dg-final { scan-assembler-times "vldrwt.32" 1 } } */
> +#ifdef __cplusplus
> +}
> +#endif
> +
> /* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c
> index 64650e26bcb..5180667658e 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c
> @@ -1,22 +1,45 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float16_t * addr, float16x8x2_t value)
> +foo (float16_t *addr, float16x8x2_t value)
> {
> - vst2q_f16 (addr, value);
> + return vst2q_f16 (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst20.16" } } */
> -/* { dg-final { scan-assembler "vst21.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float16_t * addr, float16x8x2_t value)
> +foo1 (float16_t *addr, float16x8x2_t value)
> {
> - vst2q (addr, value);
> + return vst2q (addr, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vst20.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c
> index 8840afb867d..3e6f5b0ed75 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c
> @@ -1,22 +1,45 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * addr, float32x4x2_t value)
> +foo (float32_t *addr, float32x4x2_t value)
> {
> - vst2q_f32 (addr, value);
> + return vst2q_f32 (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst20.32" } } */
> -/* { dg-final { scan-assembler "vst21.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * addr, float32x4x2_t value)
> +foo1 (float32_t *addr, float32x4x2_t value)
> {
> - vst2q (addr, value);
> + return vst2q (addr, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vst20.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c
> index 15182c5eee0..1c939317779 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c
> @@ -1,22 +1,45 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int16_t * addr, int16x8x2_t value)
> +foo (int16_t *addr, int16x8x2_t value)
> {
> - vst2q_s16 (addr, value);
> + return vst2q_s16 (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst20.16" } } */
> -/* { dg-final { scan-assembler "vst21.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int16_t * addr, int16x8x2_t value)
> +foo1 (int16_t *addr, int16x8x2_t value)
> {
> - vst2q (addr, value);
> + return vst2q (addr, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vst20.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c
> index 11c92463ae4..28c8e078942 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c
> @@ -1,22 +1,45 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * addr, int32x4x2_t value)
> +foo (int32_t *addr, int32x4x2_t value)
> {
> - vst2q_s32 (addr, value);
> + return vst2q_s32 (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst20.32" } } */
> -/* { dg-final { scan-assembler "vst21.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * addr, int32x4x2_t value)
> +foo1 (int32_t *addr, int32x4x2_t value)
> {
> - vst2q (addr, value);
> + return vst2q (addr, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vst20.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c
> index 90257ae5dae..e882c01bd63 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c
> @@ -1,22 +1,45 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int8_t * addr, int8x16x2_t value)
> +foo (int8_t *addr, int8x16x2_t value)
> {
> - vst2q_s8 (addr, value);
> + return vst2q_s8 (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst20.8" } } */
> -/* { dg-final { scan-assembler "vst21.8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int8_t * addr, int8x16x2_t value)
> +foo1 (int8_t *addr, int8x16x2_t value)
> {
> - vst2q (addr, value);
> + return vst2q (addr, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vst20.8" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c
> index a8a7c49757a..0cfbd6b9902 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c
> @@ -1,22 +1,45 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint16_t * addr, uint16x8x2_t value)
> +foo (uint16_t *addr, uint16x8x2_t value)
> {
> - vst2q_u16 (addr, value);
> + return vst2q_u16 (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst20.16" } } */
> -/* { dg-final { scan-assembler "vst21.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vst20.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +** vst21.16 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint16_t * addr, uint16x8x2_t value)
> +foo1 (uint16_t *addr, uint16x8x2_t value)
> {
> - vst2q (addr, value);
> + return vst2q (addr, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vst20.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c
> index b5d78180995..ea46a5969d0 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c
> @@ -1,22 +1,45 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * addr, uint32x4x2_t value)
> +foo (uint32_t *addr, uint32x4x2_t value)
> {
> - vst2q_u32 (addr, value);
> + return vst2q_u32 (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst20.32" } } */
> -/* { dg-final { scan-assembler "vst21.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vst20.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +** vst21.32 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * addr, uint32x4x2_t value)
> +foo1 (uint32_t *addr, uint32x4x2_t value)
> {
> - vst2q (addr, value);
> + return vst2q (addr, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vst20.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c
> index 4e7d6fea7ed..895c2ccf425 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c
> @@ -1,22 +1,45 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint8_t * addr, uint8x16x2_t value)
> +foo (uint8_t *addr, uint8x16x2_t value)
> {
> - vst2q_u8 (addr, value);
> + return vst2q_u8 (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst20.8" } } */
> -/* { dg-final { scan-assembler "vst21.8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint8_t * addr, uint8x16x2_t value)
> +foo1 (uint8_t *addr, uint8x16x2_t value)
> {
> - vst2q (addr, value);
> + return vst2q (addr, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vst20.8" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c
> index 0da66894e2c..94066089f58 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c
> @@ -1,37 +1,47 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> void
> -foo (float16_t * addr, float16x8x4_t value)
> +foo (float16_t *addr, float16x8x4_t value)
> {
> - vst4q_f16 (addr, value);
> + return vst4q_f16 (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst40.16" } } */
> -/* { dg-final { scan-assembler "vst41.16" } } */
> -/* { dg-final { scan-assembler "vst42.16" } } */
> -/* { dg-final { scan-assembler "vst43.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> void
> -foo1 (float16_t * addr, float16x8x4_t value)
> +foo1 (float16_t *addr, float16x8x4_t value)
> {
> - vst4q (addr, value);
> + return vst4q (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst40.16" } } */
> -/* { dg-final { scan-assembler "vst41.16" } } */
> -/* { dg-final { scan-assembler "vst42.16" } } */
> -/* { dg-final { scan-assembler "vst43.16" } } */
> -
> -void
> -foo2 (float16_t * addr, float16x8x4_t value)
> -{
> - vst4q_f16 (addr, value);
> - addr += 32;
> - vst4q_f16 (addr, value);
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c
> index c1614bd10fc..0150ba7ca56 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c
> @@ -1,37 +1,47 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> void
> -foo (float32_t * addr, float32x4x4_t value)
> +foo (float32_t *addr, float32x4x4_t value)
> {
> - vst4q_f32 (addr, value);
> + return vst4q_f32 (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst40.32" } } */
> -/* { dg-final { scan-assembler "vst41.32" } } */
> -/* { dg-final { scan-assembler "vst42.32" } } */
> -/* { dg-final { scan-assembler "vst43.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> void
> -foo1 (float32_t * addr, float32x4x4_t value)
> +foo1 (float32_t *addr, float32x4x4_t value)
> {
> - vst4q (addr, value);
> + return vst4q (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst40.32" } } */
> -/* { dg-final { scan-assembler "vst41.32" } } */
> -/* { dg-final { scan-assembler "vst42.32" } } */
> -/* { dg-final { scan-assembler "vst43.32" } } */
> -
> -void
> -foo2 (float32_t * addr, float32x4x4_t value)
> -{
> - vst4q_f32 (addr, value);
> - addr += 16;
> - vst4q_f32 (addr, value);
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c
> index e1250449bee..8c9df15b3c7 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c
> @@ -1,37 +1,47 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> void
> -foo (int16_t * addr, int16x8x4_t value)
> +foo (int16_t *addr, int16x8x4_t value)
> {
> - vst4q_s16 (addr, value);
> + return vst4q_s16 (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst40.16" } } */
> -/* { dg-final { scan-assembler "vst41.16" } } */
> -/* { dg-final { scan-assembler "vst42.16" } } */
> -/* { dg-final { scan-assembler "vst43.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> void
> -foo1 (int16_t * addr, int16x8x4_t value)
> +foo1 (int16_t *addr, int16x8x4_t value)
> {
> - vst4q (addr, value);
> + return vst4q (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst40.16" } } */
> -/* { dg-final { scan-assembler "vst41.16" } } */
> -/* { dg-final { scan-assembler "vst42.16" } } */
> -/* { dg-final { scan-assembler "vst43.16" } } */
> -
> -void
> -foo2 (int16_t * addr, int16x8x4_t value)
> -{
> - vst4q_s16 (addr, value);
> - addr += 32;
> - vst4q_s16 (addr, value);
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c
> index e6e1272744e..1a1a9797360 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c
> @@ -1,37 +1,47 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> void
> -foo (int32_t * addr, int32x4x4_t value)
> +foo (int32_t *addr, int32x4x4_t value)
> {
> - vst4q_s32 (addr, value);
> + return vst4q_s32 (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst40.32" } } */
> -/* { dg-final { scan-assembler "vst41.32" } } */
> -/* { dg-final { scan-assembler "vst42.32" } } */
> -/* { dg-final { scan-assembler "vst43.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> void
> -foo1 (int32_t * addr, int32x4x4_t value)
> +foo1 (int32_t *addr, int32x4x4_t value)
> {
> - vst4q (addr, value);
> + return vst4q (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst40.32" } } */
> -/* { dg-final { scan-assembler "vst41.32" } } */
> -/* { dg-final { scan-assembler "vst42.32" } } */
> -/* { dg-final { scan-assembler "vst43.32" } } */
> -
> -void
> -foo2 (int32_t * addr, int32x4x4_t value)
> -{
> - vst4q_s32 (addr, value);
> - addr += 16;
> - vst4q_s32 (addr, value);
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c
> index 16eb488ff99..d23032a73bc 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c
> @@ -1,37 +1,47 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> void
> -foo (int8_t * addr, int8x16x4_t value)
> +foo (int8_t *addr, int8x16x4_t value)
> {
> - vst4q_s8 (addr, value);
> + return vst4q_s8 (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst40.8" } } */
> -/* { dg-final { scan-assembler "vst41.8" } } */
> -/* { dg-final { scan-assembler "vst42.8" } } */
> -/* { dg-final { scan-assembler "vst43.8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> void
> -foo1 (int8_t * addr, int8x16x4_t value)
> +foo1 (int8_t *addr, int8x16x4_t value)
> {
> - vst4q (addr, value);
> + return vst4q (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst40.8" } } */
> -/* { dg-final { scan-assembler "vst41.8" } } */
> -/* { dg-final { scan-assembler "vst42.8" } } */
> -/* { dg-final { scan-assembler "vst43.8" } } */
> -
> -void
> -foo2 (int8_t * addr, int8x16x4_t value)
> -{
> - vst4q_s8 (addr, value);
> - addr += 16*4;
> - vst4q_s8 (addr, value);
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler {vst43.8\s\{.*\}, \[.*\]!} } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c
> index afd60306d0d..76cc4311e1b 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c
> @@ -1,37 +1,47 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> void
> -foo (uint16_t * addr, uint16x8x4_t value)
> +foo (uint16_t *addr, uint16x8x4_t value)
> {
> - vst4q_u16 (addr, value);
> + return vst4q_u16 (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst40.16" } } */
> -/* { dg-final { scan-assembler "vst41.16" } } */
> -/* { dg-final { scan-assembler "vst42.16" } } */
> -/* { dg-final { scan-assembler "vst43.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vst40.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst41.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst42.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst43.16 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> void
> -foo1 (uint16_t * addr, uint16x8x4_t value)
> +foo1 (uint16_t *addr, uint16x8x4_t value)
> {
> - vst4q (addr, value);
> + return vst4q (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst40.16" } } */
> -/* { dg-final { scan-assembler "vst41.16" } } */
> -/* { dg-final { scan-assembler "vst42.16" } } */
> -/* { dg-final { scan-assembler "vst43.16" } } */
> -
> -void
> -foo2 (uint16_t * addr, uint16x8x4_t value)
> -{
> - vst4q_u16 (addr, value);
> - addr += 32;
> - vst4q_u16 (addr, value);
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c
> index 755dd689dff..e5f62858eee 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c
> @@ -1,37 +1,47 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> void
> -foo (uint32_t * addr, uint32x4x4_t value)
> +foo (uint32_t *addr, uint32x4x4_t value)
> {
> - vst4q_u32 (addr, value);
> + return vst4q_u32 (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst40.32" } } */
> -/* { dg-final { scan-assembler "vst41.32" } } */
> -/* { dg-final { scan-assembler "vst42.32" } } */
> -/* { dg-final { scan-assembler "vst43.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vst40.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst41.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst42.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst43.32 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> void
> -foo1 (uint32_t * addr, uint32x4x4_t value)
> +foo1 (uint32_t *addr, uint32x4x4_t value)
> {
> - vst4q (addr, value);
> + return vst4q (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst40.32" } } */
> -/* { dg-final { scan-assembler "vst41.32" } } */
> -/* { dg-final { scan-assembler "vst42.32" } } */
> -/* { dg-final { scan-assembler "vst43.32" } } */
> -
> -void
> -foo2 (uint32_t * addr, uint32x4x4_t value)
> -{
> - vst4q_u32 (addr, value);
> - addr += 16;
> - vst4q_u32 (addr, value);
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c
> index 0b28451df55..923cd0d3b10 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c
> @@ -1,37 +1,47 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> void
> -foo (uint8_t * addr, uint8x16x4_t value)
> +foo (uint8_t *addr, uint8x16x4_t value)
> {
> - vst4q_u8 (addr, value);
> + return vst4q_u8 (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst40.8" } } */
> -/* { dg-final { scan-assembler "vst41.8" } } */
> -/* { dg-final { scan-assembler "vst42.8" } } */
> -/* { dg-final { scan-assembler "vst43.8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vst40.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst41.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst42.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** vst43.8 {q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
> +** ...
> +*/
> void
> -foo1 (uint8_t * addr, uint8x16x4_t value)
> +foo1 (uint8_t *addr, uint8x16x4_t value)
> {
> - vst4q (addr, value);
> + return vst4q (addr, value);
> }
>
> -/* { dg-final { scan-assembler "vst40.8" } } */
> -/* { dg-final { scan-assembler "vst41.8" } } */
> -/* { dg-final { scan-assembler "vst42.8" } } */
> -/* { dg-final { scan-assembler "vst43.8" } } */
> -
> -void
> -foo2 (uint8_t * addr, uint8x16x4_t value)
> -{
> - vst4q_u8 (addr, value);
> - addr += 16*4;
> - vst4q_u8 (addr, value);
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler {vst43.8\s\{.*\}, \[.*\]!} } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c
> index ad74d8aa2e9..19804443e01 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int8_t * addr, int16x8_t value, mve_pred16_t p)
> +foo (int8_t *base, int16x8_t value, mve_pred16_t p)
> {
> - vstrbq_p_s16 (addr, value, p);
> + return vstrbq_p_s16 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrbt.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int8_t * addr, int16x8_t value, mve_pred16_t p)
> +foo1 (int8_t *base, int16x8_t value, mve_pred16_t p)
> {
> - vstrbq_p (addr, value, p);
> + return vstrbq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrbt.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c
> index 46fd4549ffb..26be212770b 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int8_t * addr, int32x4_t value, mve_pred16_t p)
> +foo (int8_t *base, int32x4_t value, mve_pred16_t p)
> {
> - vstrbq_p_s32 (addr, value, p);
> + return vstrbq_p_s32 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrbt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int8_t * addr, int32x4_t value, mve_pred16_t p)
> +foo1 (int8_t *base, int32x4_t value, mve_pred16_t p)
> {
> - vstrbq_p (addr, value, p);
> + return vstrbq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrbt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c
> index 8e70b9eb098..a0d08772a50 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int8_t * addr, int8x16_t value, mve_pred16_t p)
> +foo (int8_t *base, int8x16_t value, mve_pred16_t p)
> {
> - vstrbq_p_s8 (addr, value, p);
> + return vstrbq_p_s8 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrbt.8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int8_t * addr, int8x16_t value, mve_pred16_t p)
> +foo1 (int8_t *base, int8x16_t value, mve_pred16_t p)
> {
> - vstrbq_p (addr, value, p);
> + return vstrbq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrbt.8" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c
> index 180f9033edd..bc02c59887a 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint8_t * addr, uint16x8_t value, mve_pred16_t p)
> +foo (uint8_t *base, uint16x8_t value, mve_pred16_t p)
> {
> - vstrbq_p_u16 (addr, value, p);
> + return vstrbq_p_u16 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrbt.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint8_t * addr, uint16x8_t value, mve_pred16_t p)
> +foo1 (uint8_t *base, uint16x8_t value, mve_pred16_t p)
> {
> - vstrbq_p (addr, value, p);
> + return vstrbq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrbt.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c
> index 1b944fc9ffc..1215d5f0978 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint8_t * addr, uint32x4_t value, mve_pred16_t p)
> +foo (uint8_t *base, uint32x4_t value, mve_pred16_t p)
> {
> - vstrbq_p_u32 (addr, value, p);
> + return vstrbq_p_u32 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrbt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint8_t * addr, uint32x4_t value, mve_pred16_t p)
> +foo1 (uint8_t *base, uint32x4_t value, mve_pred16_t p)
> {
> - vstrbq_p (addr, value, p);
> + return vstrbq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrbt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c
> index 7e73cbff84e..a88234e411d 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint8_t * addr, uint8x16_t value, mve_pred16_t p)
> +foo (uint8_t *base, uint8x16_t value, mve_pred16_t p)
> {
> - vstrbq_p_u8 (addr, value, p);
> + return vstrbq_p_u8 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrbt.8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint8_t * addr, uint8x16_t value, mve_pred16_t p)
> +foo1 (uint8_t *base, uint8x16_t value, mve_pred16_t p)
> {
> - vstrbq_p (addr, value, p);
> + return vstrbq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrbt.8" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c
> index 4d12bc2cd19..1e88d3aa600 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int8_t * addr, int16x8_t value)
> +foo (int8_t *base, int16x8_t value)
> {
> - vstrbq_s16 (addr, value);
> + return vstrbq_s16 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrb.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int8_t * addr, int16x8_t value)
> +foo1 (int8_t *base, int16x8_t value)
> {
> - vstrbq (addr, value);
> + return vstrbq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrb.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c
> index 750413f35ae..12764bf3041 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int8_t * addr, int32x4_t value)
> +foo (int8_t *base, int32x4_t value)
> {
> - vstrbq_s32 (addr, value);
> + return vstrbq_s32 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrb.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int8_t * addr, int32x4_t value)
> +foo1 (int8_t *base, int32x4_t value)
> {
> - vstrbq (addr, value);
> + return vstrbq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrb.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c
> index 7ffb2c51976..05a9e5c42ce 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int8_t * addr, int8x16_t value)
> +foo (int8_t *base, int8x16_t value)
> {
> - vstrbq_s8 (addr, value);
> + return vstrbq_s8 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrb.8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int8_t * addr, int8x16_t value)
> +foo1 (int8_t *base, int8x16_t value)
> {
> - vstrbq (addr, value);
> + return vstrbq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrb.8" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c
> index f59fa349cc0..052c3f85b75 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int8_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
> +foo (int8_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
> {
> - vstrbq_scatter_offset_p_s16 (base, offset, value, p);
> + return vstrbq_scatter_offset_p_s16 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrbt.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int8_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
> +foo1 (int8_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
> {
> - vstrbq_scatter_offset_p (base, offset, value, p);
> + return vstrbq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrbt.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c
> index 737c1008976..57410e46a8a 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int8_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> +foo (int8_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> {
> - vstrbq_scatter_offset_p_s32 (base, offset, value, p);
> + return vstrbq_scatter_offset_p_s32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrbt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int8_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> +foo1 (int8_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> {
> - vstrbq_scatter_offset_p (base, offset, value, p);
> + return vstrbq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrbt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c
> index 8b2d06807b4..c3cdefdf078 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int8_t * base, uint8x16_t offset, int8x16_t value, mve_pred16_t p)
> +foo (int8_t *base, uint8x16_t offset, int8x16_t value, mve_pred16_t p)
> {
> - vstrbq_scatter_offset_p_s8 (base, offset, value, p);
> + return vstrbq_scatter_offset_p_s8 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrbt.8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int8_t * base, uint8x16_t offset, int8x16_t value, mve_pred16_t p)
> +foo1 (int8_t *base, uint8x16_t offset, int8x16_t value, mve_pred16_t p)
> {
> - vstrbq_scatter_offset_p (base, offset, value, p);
> + return vstrbq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrbt.8" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c
> index 0adccaac39c..0868cc2248b 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint8_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
> +foo (uint8_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
> {
> - vstrbq_scatter_offset_p_u16 (base, offset, value, p);
> + return vstrbq_scatter_offset_p_u16 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrbt.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
> +foo1 (uint8_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
> {
> - vstrbq_scatter_offset_p (base, offset, value, p);
> + return vstrbq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrbt.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c
> index 308119294df..9d769941569 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint8_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> +foo (uint8_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> {
> - vstrbq_scatter_offset_p_u32 (base, offset, value, p);
> + return vstrbq_scatter_offset_p_u32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrbt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> +foo1 (uint8_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> {
> - vstrbq_scatter_offset_p (base, offset, value, p);
> + return vstrbq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrbt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c
> index 28b2ca4b83a..4586535d600 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint8_t * base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p)
> +foo (uint8_t *base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p)
> {
> - vstrbq_scatter_offset_p_u8 (base, offset, value, p);
> + return vstrbq_scatter_offset_p_u8 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrbt.8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p)
> +foo1 (uint8_t *base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p)
> {
> - vstrbq_scatter_offset_p (base, offset, value, p);
> + return vstrbq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrbt.8" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c
> index e6cf1828b33..179b96f4973 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int8_t * base, uint16x8_t offset, int16x8_t value)
> +foo (int8_t *base, uint16x8_t offset, int16x8_t value)
> {
> - vstrbq_scatter_offset_s16 (base, offset, value);
> + return vstrbq_scatter_offset_s16 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrb.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int8_t * base, uint16x8_t offset, int16x8_t value)
> +foo1 (int8_t *base, uint16x8_t offset, int16x8_t value)
> {
> - vstrbq_scatter_offset (base, offset, value);
> + return vstrbq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrb.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c
> index 052e02a7cf9..e7b7767c9f2 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int8_t * base, uint32x4_t offset, int32x4_t value)
> +foo (int8_t *base, uint32x4_t offset, int32x4_t value)
> {
> - vstrbq_scatter_offset_s32 (base, offset, value);
> + return vstrbq_scatter_offset_s32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrb.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int8_t * base, uint32x4_t offset, int32x4_t value)
> +foo1 (int8_t *base, uint32x4_t offset, int32x4_t value)
> {
> - vstrbq_scatter_offset (base, offset, value);
> + return vstrbq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrb.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c
> index 523f318e73c..f47bdd1a630 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int8_t * base, uint8x16_t offset, int8x16_t value)
> +foo (int8_t *base, uint8x16_t offset, int8x16_t value)
> {
> - vstrbq_scatter_offset_s8 (base, offset, value);
> + return vstrbq_scatter_offset_s8 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrb.8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int8_t * base, uint8x16_t offset, int8x16_t value)
> +foo1 (int8_t *base, uint8x16_t offset, int8x16_t value)
> {
> - vstrbq_scatter_offset (base, offset, value);
> + return vstrbq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrb.8" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c
> index 49d4d31ad21..90e8cf351f9 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint8_t * base, uint16x8_t offset, uint16x8_t value)
> +foo (uint8_t *base, uint16x8_t offset, uint16x8_t value)
> {
> - vstrbq_scatter_offset_u16 (base, offset, value);
> + return vstrbq_scatter_offset_u16 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrb.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value)
> +foo1 (uint8_t *base, uint16x8_t offset, uint16x8_t value)
> {
> - vstrbq_scatter_offset (base, offset, value);
> + return vstrbq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrb.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c
> index 0012852298c..e5449aa0942 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint8_t * base, uint32x4_t offset, uint32x4_t value)
> +foo (uint8_t *base, uint32x4_t offset, uint32x4_t value)
> {
> - vstrbq_scatter_offset_u32 (base, offset, value);
> + return vstrbq_scatter_offset_u32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrb.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value)
> +foo1 (uint8_t *base, uint32x4_t offset, uint32x4_t value)
> {
> - vstrbq_scatter_offset (base, offset, value);
> + return vstrbq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrb.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c
> index e54422a1afe..06c8c45e877 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint8_t * base, uint8x16_t offset, uint8x16_t value)
> +foo (uint8_t *base, uint8x16_t offset, uint8x16_t value)
> {
> - vstrbq_scatter_offset_u8 (base, offset, value);
> + return vstrbq_scatter_offset_u8 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrb.8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value)
> +foo1 (uint8_t *base, uint8x16_t offset, uint8x16_t value)
> {
> - vstrbq_scatter_offset (base, offset, value);
> + return vstrbq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrb.8" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c
> index 9fa9d18c6a1..0b350e2491b 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint8_t * addr, uint16x8_t value)
> +foo (uint8_t *base, uint16x8_t value)
> {
> - vstrbq_u16 (addr, value);
> + return vstrbq_u16 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrb.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrb.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint8_t * addr, uint16x8_t value)
> +foo1 (uint8_t *base, uint16x8_t value)
> {
> - vstrbq (addr, value);
> + return vstrbq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrb.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c
> index e535aa275ef..2f809356420 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint8_t * addr, uint32x4_t value)
> +foo (uint8_t *base, uint32x4_t value)
> {
> - vstrbq_u32 (addr, value);
> + return vstrbq_u32 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrb.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrb.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint8_t * addr, uint32x4_t value)
> +foo1 (uint8_t *base, uint32x4_t value)
> {
> - vstrbq (addr, value);
> + return vstrbq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrb.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c
> index 93771aabcbd..deeea98dda5 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint8_t * addr, uint8x16_t value)
> +foo (uint8_t *base, uint8x16_t value)
> {
> - vstrbq_u8 (addr, value);
> + return vstrbq_u8 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrb.8" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint8_t * addr, uint8x16_t value)
> +foo1 (uint8_t *base, uint8x16_t value)
> {
> - vstrbq (addr, value);
> + return vstrbq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrb.8" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c
> index 74e2617c380..a41217b24f2 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float16_t * addr, float16x8_t value)
> +foo (float16_t *base, float16x8_t value)
> {
> - vstrhq_f16 (addr, value);
> + return vstrhq_f16 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrh.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float16_t * addr, float16x8_t value)
> +foo1 (float16_t *base, float16x8_t value)
> {
> - vstrhq (addr, value);
> + return vstrhq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrh.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c
> index 227da4f10aa..8398a60023d 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float16_t * addr, float16x8_t value, mve_pred16_t p)
> +foo (float16_t *base, float16x8_t value, mve_pred16_t p)
> {
> - vstrhq_p_f16 (addr, value, p);
> + return vstrhq_p_f16 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrht.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float16_t * addr, float16x8_t value, mve_pred16_t p)
> +foo1 (float16_t *base, float16x8_t value, mve_pred16_t p)
> {
> - vstrhq_p (addr, value, p);
> + return vstrhq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrht.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c
> index f3ba71f0ce1..ee1026801be 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int16_t * addr, int16x8_t value, mve_pred16_t p)
> +foo (int16_t *base, int16x8_t value, mve_pred16_t p)
> {
> - vstrhq_p_s16 (addr, value, p);
> + return vstrhq_p_s16 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrht.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int16_t * addr, int16x8_t value, mve_pred16_t p)
> +foo1 (int16_t *base, int16x8_t value, mve_pred16_t p)
> {
> - vstrhq_p (addr, value, p);
> + return vstrhq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrht.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c
> index dab646706ce..b8490209644 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int16_t * addr, int32x4_t value, mve_pred16_t p)
> +foo (int16_t *base, int32x4_t value, mve_pred16_t p)
> {
> - vstrhq_p_s32 (addr, value, p);
> + return vstrhq_p_s32 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrht.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int16_t * addr, int32x4_t value, mve_pred16_t p)
> +foo1 (int16_t *base, int32x4_t value, mve_pred16_t p)
> {
> - vstrhq_p (addr, value, p);
> + return vstrhq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrht.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c
> index e575c70cc44..59fb73cef19 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint16_t * addr, uint16x8_t value, mve_pred16_t p)
> +foo (uint16_t *base, uint16x8_t value, mve_pred16_t p)
> {
> - vstrhq_p_u16 (addr, value, p);
> + return vstrhq_p_u16 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrht.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint16_t * addr, uint16x8_t value, mve_pred16_t p)
> +foo1 (uint16_t *base, uint16x8_t value, mve_pred16_t p)
> {
> - vstrhq_p (addr, value, p);
> + return vstrhq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrht.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c
> index e863e284c3c..ed66db7f8ce 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint16_t * addr, uint32x4_t value, mve_pred16_t p)
> +foo (uint16_t *base, uint32x4_t value, mve_pred16_t p)
> {
> - vstrhq_p_u32 (addr, value, p);
> + return vstrhq_p_u32 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrht.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint16_t * addr, uint32x4_t value, mve_pred16_t p)
> +foo1 (uint16_t *base, uint32x4_t value, mve_pred16_t p)
> {
> - vstrhq_p (addr, value, p);
> + return vstrhq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrht.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c
> index 5e47fb4e1a6..972d733c5bd 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int16_t * addr, int16x8_t value)
> +foo (int16_t *base, int16x8_t value)
> {
> - vstrhq_s16 (addr, value);
> + return vstrhq_s16 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrh.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int16_t * addr, int16x8_t value)
> +foo1 (int16_t *base, int16x8_t value)
> {
> - vstrhq (addr, value);
> + return vstrhq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrh.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c
> index 73e01c9acfb..f260c61c3a8 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int16_t * addr, int32x4_t value)
> +foo (int16_t *base, int32x4_t value)
> {
> - vstrhq_s32 (addr, value);
> + return vstrhq_s32 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrh.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int16_t * addr, int32x4_t value)
> +foo1 (int16_t *base, int32x4_t value)
> {
> - vstrhq (addr, value);
> + return vstrhq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrh.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c
> index d29bd08ad0a..794d75e76ac 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float16_t * base, uint16x8_t offset, float16x8_t value)
> +foo (float16_t *base, uint16x8_t offset, float16x8_t value)
> {
> - vstrhq_scatter_offset_f16 (base, offset, value);
> + return vstrhq_scatter_offset_f16 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrh.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float16_t * base, uint16x8_t offset, float16x8_t value)
> +foo1 (float16_t *base, uint16x8_t offset, float16x8_t value)
> {
> - vstrhq_scatter_offset (base, offset, value);
> + return vstrhq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrh.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c
> index 79d9827b378..1fd5a0773dc 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
> +foo (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_offset_p_f16 (base, offset, value, p);
> + return vstrhq_scatter_offset_p_f16 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrht.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
> +foo1 (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_offset_p (base, offset, value, p);
> + return vstrhq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrht.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c
> index 1b401d4c5b7..34c44a90541 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
> +foo (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_offset_p_s16 (base, offset, value, p);
> + return vstrhq_scatter_offset_p_s16 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrht.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
> +foo1 (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_offset_p (base, offset, value, p);
> + return vstrhq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrht.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c
> index afb325b9789..2a84b28a3f5 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> +foo (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_offset_p_s32 (base, offset, value, p);
> + return vstrhq_scatter_offset_p_s32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrht.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> +foo1 (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_offset_p (base, offset, value, p);
> + return vstrhq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrht.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c
> index 73bee831282..f1c875657ce 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
> +foo (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_offset_p_u16 (base, offset, value, p);
> + return vstrhq_scatter_offset_p_u16 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrht.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
> +foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_offset_p (base, offset, value, p);
> + return vstrhq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrht.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c
> index bae7c2d14c2..913fd8d5591 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> +foo (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_offset_p_u32 (base, offset, value, p);
> + return vstrhq_scatter_offset_p_u32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrht.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> +foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_offset_p (base, offset, value, p);
> + return vstrhq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrht.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c
> index bf3c03a85c6..b322d0fa02e 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int16_t * base, uint16x8_t offset, int16x8_t value)
> +foo (int16_t *base, uint16x8_t offset, int16x8_t value)
> {
> - vstrhq_scatter_offset_s16 (base, offset, value);
> + return vstrhq_scatter_offset_s16 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrh.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int16_t * base, uint16x8_t offset, int16x8_t value)
> +foo1 (int16_t *base, uint16x8_t offset, int16x8_t value)
> {
> - vstrhq_scatter_offset (base, offset, value);
> + return vstrhq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrh.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c
> index 0591ab55c07..49fcc3a382b 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int16_t * base, uint32x4_t offset, int32x4_t value)
> +foo (int16_t *base, uint32x4_t offset, int32x4_t value)
> {
> - vstrhq_scatter_offset_s32 (base, offset, value);
> + return vstrhq_scatter_offset_s32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrh.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int16_t * base, uint32x4_t offset, int32x4_t value)
> +foo1 (int16_t *base, uint32x4_t offset, int32x4_t value)
> {
> - vstrhq_scatter_offset (base, offset, value);
> + return vstrhq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrh.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c
> index 0a2fa1f410e..b5de540a74c 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint16_t * base, uint16x8_t offset, uint16x8_t value)
> +foo (uint16_t *base, uint16x8_t offset, uint16x8_t value)
> {
> - vstrhq_scatter_offset_u16 (base, offset, value);
> + return vstrhq_scatter_offset_u16 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrh.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value)
> +foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value)
> {
> - vstrhq_scatter_offset (base, offset, value);
> + return vstrhq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrh.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c
> index 809a44dee16..7808f25d4a4 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint16_t * base, uint32x4_t offset, uint32x4_t value)
> +foo (uint16_t *base, uint32x4_t offset, uint32x4_t value)
> {
> - vstrhq_scatter_offset_u32 (base, offset, value);
> + return vstrhq_scatter_offset_u32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrh.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value)
> +foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value)
> {
> - vstrhq_scatter_offset (base, offset, value);
> + return vstrhq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrh.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f
> 16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f
> 16.c
> index 1dcb1f7692d..6d57a22fe41 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f
> 16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f
> 16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (float16_t * base, uint16x8_t offset, float16x8_t value)
> +foo (float16_t *base, uint16x8_t offset, float16x8_t value)
> {
> - vstrhq_scatter_shifted_offset_f16 (base, offset, value);
> + return vstrhq_scatter_shifted_offset_f16 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrh.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (float16_t * base, uint16x8_t offset, float16x8_t value)
> +foo1 (float16_t *base, uint16x8_t offset, float16x8_t value)
> {
> - vstrhq_scatter_shifted_offset (base, offset, value);
> + return vstrhq_scatter_shifted_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrh.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _f16.c
> index c46eec95adf..2e77dd492a1 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _f16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _f16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
> +foo (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_shifted_offset_p_f16 (base, offset, value, p);
> + return vstrhq_scatter_shifted_offset_p_f16 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrht.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
> +foo1 (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_shifted_offset_p (base, offset, value, p);
> + return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrht.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _s16.c
> index 7e9a549e8c2..1c83a13ffdf 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _s16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _s16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
> +foo (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_shifted_offset_p_s16 (base, offset, value, p);
> + return vstrhq_scatter_shifted_offset_p_s16 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrht.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
> +foo1 (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_shifted_offset_p (base, offset, value, p);
> + return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrht.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _s32.c
> index 502b4b00e2a..6d786de4379 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _s32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> +foo (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_shifted_offset_p_s32 (base, offset, value, p);
> + return vstrhq_scatter_shifted_offset_p_s32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrht.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> +foo1 (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_shifted_offset_p (base, offset, value, p);
> + return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrht.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _u16.c
> index 151145ce174..fd73168ddbb 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _u16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _u16.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
> +foo (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_shifted_offset_p_u16 (base, offset, value, p);
> + return vstrhq_scatter_shifted_offset_p_u16 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrht.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
> +foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_shifted_offset_p (base, offset, value, p);
> + return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrht.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _u32.c
> index 14efd952593..689195ce603 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p
> _u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> +foo (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_shifted_offset_p_u32 (base, offset, value, p);
> + return vstrhq_scatter_shifted_offset_p_u32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrht.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> +foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> {
> - vstrhq_scatter_shifted_offset_p (base, offset, value, p);
> + return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrht.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s
> 16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s
> 16.c
> index e5142ed85f7..0edacd938f6 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s
> 16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s
> 16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (int16_t * base, uint16x8_t offset, int16x8_t value)
> +foo (int16_t *base, uint16x8_t offset, int16x8_t value)
> {
> - vstrhq_scatter_shifted_offset_s16 (base, offset, value);
> + return vstrhq_scatter_shifted_offset_s16 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrh.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (int16_t * base, uint16x8_t offset, int16x8_t value)
> +foo1 (int16_t *base, uint16x8_t offset, int16x8_t value)
> {
> - vstrhq_scatter_shifted_offset (base, offset, value);
> + return vstrhq_scatter_shifted_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrh.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s
> 32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s
> 32.c
> index 431808f9008..ebda2faec92 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s
> 32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s
> 32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (int16_t * base, uint32x4_t offset, int32x4_t value)
> +foo (int16_t *base, uint32x4_t offset, int32x4_t value)
> {
> - vstrhq_scatter_shifted_offset_s32 (base, offset, value);
> + return vstrhq_scatter_shifted_offset_s32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrh.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (int16_t * base, uint32x4_t offset, int32x4_t value)
> +foo1 (int16_t *base, uint32x4_t offset, int32x4_t value)
> {
> - vstrhq_scatter_shifted_offset (base, offset, value);
> + return vstrhq_scatter_shifted_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrh.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u
> 16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u
> 16.c
> index f93e5d51913..abe8bbf8045 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u
> 16.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u
> 16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (uint16_t * base, uint16x8_t offset, uint16x8_t value)
> +foo (uint16_t *base, uint16x8_t offset, uint16x8_t value)
> {
> - vstrhq_scatter_shifted_offset_u16 (base, offset, value);
> + return vstrhq_scatter_shifted_offset_u16 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrh.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value)
> +foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value)
> {
> - vstrhq_scatter_shifted_offset (base, offset, value);
> + return vstrhq_scatter_shifted_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrh.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u
> 32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u
> 32.c
> index fc250706fa8..a01b04bd940 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u
> 32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u
> 32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (uint16_t * base, uint32x4_t offset, uint32x4_t value)
> +foo (uint16_t *base, uint32x4_t offset, uint32x4_t value)
> {
> - vstrhq_scatter_shifted_offset_u32 (base, offset, value);
> + return vstrhq_scatter_shifted_offset_u32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrh.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value)
> +foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value)
> {
> - vstrhq_scatter_shifted_offset (base, offset, value);
> + return vstrhq_scatter_shifted_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrh.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c
> index f7b3ef1012b..85f5790ff49 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint16_t * addr, uint16x8_t value)
> +foo (uint16_t *base, uint16x8_t value)
> {
> - vstrhq_u16 (addr, value);
> + return vstrhq_u16 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrh.16" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint16_t * addr, uint16x8_t value)
> +foo1 (uint16_t *base, uint16x8_t value)
> {
> - vstrhq (addr, value);
> + return vstrhq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrh.16" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c
> index 8e01fd10032..d0958e22222 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint16_t * addr, uint32x4_t value)
> +foo (uint16_t *base, uint32x4_t value)
> {
> - vstrhq_u32 (addr, value);
> + return vstrhq_u32 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrh.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrh.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint16_t * addr, uint32x4_t value)
> +foo1 (uint16_t *base, uint32x4_t value)
> {
> - vstrhq (addr, value);
> + return vstrhq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrh.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> --
> 2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH 02/10] arm: Fix vstrwq* backend + testsuite
2023-04-28 11:29 ` [PATCH 02/10] arm: Fix vstrwq* backend + testsuite Andrea Corallo
@ 2023-04-28 16:27 ` Kyrylo Tkachov
2023-05-02 8:21 ` Christophe Lyon
1 sibling, 0 replies; 31+ messages in thread
From: Kyrylo Tkachov @ 2023-04-28 16:27 UTC (permalink / raw)
To: Andrea Corallo, gcc-patches; +Cc: Richard Earnshaw, Andrea Corallo
> -----Original Message-----
> From: Andrea Corallo <andrea.corallo@arm.com>
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; Andrea Corallo <Andrea.Corallo@arm.com>
> Subject: [PATCH 02/10] arm: Fix vstrwq* backend + testsuite
>
> Hi all,
>
> this patch fixes the vstrwq* MVE instrinsics failing to emit the
> correct sequence of instruction due to a missing predicates. Also the
> immediate range is fixed to be multiples of 2 up between [-252, 252].
>
Ok.
Thanks,
Kyrill
> Best Regards
>
> Andrea
>
> gcc/ChangeLog:
>
> * config/arm/constraints.md (mve_vldrd_immediate): Move it to
> predicates.md.
> (Ri): Move constraint definition from predicates.md.
> (Rl): Define new constraint.
> * config/arm/mve.md (mve_vstrwq_scatter_base_wb_p_<supf>v4si):
> Add
> missing constraint.
> (mve_vstrwq_scatter_base_wb_p_fv4sf): Add missing Up constraint
> for op 1, use mve_vstrw_immediate predicate and Rl constraint for
> op 2. Fix asm output spacing.
> (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Add missing
> constraint.
> * config/arm/predicates.md (Ri) Move constraint to constraints.md
> (mve_vldrd_immediate): Move it from
> constraints.md.
> (mve_vstrw_immediate): New predicate.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arm/mve/intrinsics/vstrwq_f32.c: Use
> check-function-bodies instead of scan-assembler checks. Use
> extern "C" for C++ testing.
> * gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_u32.c: Likewise.
> ---
> gcc/config/arm/constraints.md | 20 ++++++++--
> gcc/config/arm/mve.md | 10 ++---
> gcc/config/arm/predicates.md | 14 +++----
> .../arm/mve/intrinsics/vstrwq_f32.c | 32 ++++++++++++---
> .../arm/mve/intrinsics/vstrwq_p_f32.c | 40 ++++++++++++++++---
> .../arm/mve/intrinsics/vstrwq_p_s32.c | 40 ++++++++++++++++---
> .../arm/mve/intrinsics/vstrwq_p_u32.c | 40 ++++++++++++++++---
> .../arm/mve/intrinsics/vstrwq_s32.c | 32 ++++++++++++---
> .../mve/intrinsics/vstrwq_scatter_base_f32.c | 28 +++++++++++--
> .../intrinsics/vstrwq_scatter_base_p_f32.c | 36 +++++++++++++++--
> .../intrinsics/vstrwq_scatter_base_p_s32.c | 36 +++++++++++++++--
> .../intrinsics/vstrwq_scatter_base_p_u32.c | 36 +++++++++++++++--
> .../mve/intrinsics/vstrwq_scatter_base_s32.c | 28 +++++++++++--
> .../mve/intrinsics/vstrwq_scatter_base_u32.c | 28 +++++++++++--
> .../intrinsics/vstrwq_scatter_base_wb_f32.c | 32 ++++++++++++---
> .../intrinsics/vstrwq_scatter_base_wb_p_f32.c | 40 ++++++++++++++++---
> .../intrinsics/vstrwq_scatter_base_wb_p_s32.c | 40 ++++++++++++++++---
> .../intrinsics/vstrwq_scatter_base_wb_p_u32.c | 40 ++++++++++++++++---
> .../intrinsics/vstrwq_scatter_base_wb_s32.c | 32 ++++++++++++---
> .../intrinsics/vstrwq_scatter_base_wb_u32.c | 32 ++++++++++++---
> .../intrinsics/vstrwq_scatter_offset_f32.c | 32 ++++++++++++---
> .../intrinsics/vstrwq_scatter_offset_p_f32.c | 40 ++++++++++++++++---
> .../intrinsics/vstrwq_scatter_offset_p_s32.c | 40 ++++++++++++++++---
> .../intrinsics/vstrwq_scatter_offset_p_u32.c | 40 ++++++++++++++++---
> .../intrinsics/vstrwq_scatter_offset_s32.c | 32 ++++++++++++---
> .../intrinsics/vstrwq_scatter_offset_u32.c | 32 ++++++++++++---
> .../vstrwq_scatter_shifted_offset_f32.c | 32 ++++++++++++---
> .../vstrwq_scatter_shifted_offset_p_f32.c | 40 ++++++++++++++++---
> .../vstrwq_scatter_shifted_offset_p_s32.c | 40 ++++++++++++++++---
> .../vstrwq_scatter_shifted_offset_p_u32.c | 40 ++++++++++++++++---
> .../vstrwq_scatter_shifted_offset_s32.c | 32 ++++++++++++---
> .../vstrwq_scatter_shifted_offset_u32.c | 32 ++++++++++++---
> .../arm/mve/intrinsics/vstrwq_u32.c | 32 ++++++++++++---
> 33 files changed, 922 insertions(+), 178 deletions(-)
>
> diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md
> index 504cd938b26..05a4ebbdd67 100644
> --- a/gcc/config/arm/constraints.md
> +++ b/gcc/config/arm/constraints.md
> @@ -102,10 +102,6 @@ (define_constraint "Rg"
> (match_test "TARGET_HAVE_MVE && ((ival == 1) || (ival == 2)
> || (ival == 4) || (ival == 8))")))
>
> -;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE.
> -(define_predicate "mve_vldrd_immediate"
> - (match_test "satisfies_constraint_Ri (op)"))
> -
> (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
> "The VFP registers @code{s0}-@code{s31}.")
>
> @@ -574,6 +570,22 @@ (define_constraint "US"
> (match_code "symbol_ref")
> )
>
> +;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE.
> +(define_constraint "Ri"
> + "@internal In Thumb-2 state a constant is multiple of 8 and in range
> + of -/+ 1016 for MVE"
> + (and (match_code "const_int")
> + (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016)
> + && ((ival % 8) == 0)")))
> +
> +;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE.
> +(define_constraint "Rl"
> + "@internal In Thumb-2 state a constant is multiple of 2 and in range
> + of -/+ 252 for MVE"
> + (and (match_code "const_int")
> + (match_test "TARGET_HAVE_MVE && (-252 <= ival) && (ival <= 252)
> + && ((ival % 2) == 0)")))
> +
> (define_memory_constraint "Uz"
> "@internal
> A memory access that is accessible as an LDC/STC operand"
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> index 35eab6c94bf..161794e470c 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -9359,7 +9359,7 @@ (define_insn
> "mve_vstrwq_scatter_base_wb_p_<supf>v4si"
> [(match_operand:V4SI 1 "s_register_operand" "0")
> (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
> (match_operand:V4SI 3 "s_register_operand" "w")
> - (match_operand:V4BI 4 "vpr_register_operand")]
> + (match_operand:V4BI 4 "vpr_register_operand" "Up")]
> VSTRWSBWBQ))
> (set (match_operand:V4SI 0 "s_register_operand" "=w")
> (unspec:V4SI [(match_dup 1) (match_dup 2)]
> @@ -9408,9 +9408,9 @@ (define_insn
> "mve_vstrwq_scatter_base_wb_p_fv4sf"
> [(set (mem:BLK (scratch))
> (unspec:BLK
> [(match_operand:V4SI 1 "s_register_operand" "0")
> - (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
> + (match_operand:SI 2 "mve_vstrw_immediate" "Rl")
> (match_operand:V4SF 3 "s_register_operand" "w")
> - (match_operand:V4BI 4 "vpr_register_operand")]
> + (match_operand:V4BI 4 "vpr_register_operand" "Up")]
> VSTRWQSBWB_F))
> (set (match_operand:V4SI 0 "s_register_operand" "=w")
> (unspec:V4SI [(match_dup 1) (match_dup 2)]
> @@ -9422,7 +9422,7 @@ (define_insn
> "mve_vstrwq_scatter_base_wb_p_fv4sf"
> ops[0] = operands[1];
> ops[1] = operands[2];
> ops[2] = operands[3];
> - output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops);
> + output_asm_insn ("vpst\;vstrwt.u32\t%q2, [%q0, %1]!",ops);
> return "";
> }
> [(set_attr "length" "8")])
> @@ -9461,7 +9461,7 @@ (define_insn
> "mve_vstrdq_scatter_base_wb_p_<supf>v2di"
> [(match_operand:V2DI 1 "s_register_operand" "0")
> (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
> (match_operand:V2DI 3 "s_register_operand" "w")
> - (match_operand:V2QI 4 "vpr_register_operand")]
> + (match_operand:V2QI 4 "vpr_register_operand" "Up")]
> VSTRDSBWBQ))
> (set (match_operand:V2DI 0 "s_register_operand" "=w")
> (unspec:V2DI [(match_dup 1) (match_dup 2)]
> diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
> index 3139750c606..00995a590ab 100644
> --- a/gcc/config/arm/predicates.md
> +++ b/gcc/config/arm/predicates.md
> @@ -73,13 +73,13 @@ (define_predicate "mve_imm_32"
> (define_predicate "mve_imm_selective_upto_8"
> (match_test "satisfies_constraint_Rg (op)"))
>
> -;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE.
> -(define_constraint "Ri"
> - "@internal In Thumb-2 state a constant is multiple of 8 and in range
> - of -/+ 1016 for MVE"
> - (and (match_code "const_int")
> - (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016)
> - && ((ival % 8) == 0)")))
> +;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE.
> +(define_predicate "mve_vldrd_immediate"
> + (match_test "satisfies_constraint_Ri (op)"))
> +
> +;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE.
> +(define_predicate "mve_vstrw_immediate"
> + (match_test "satisfies_constraint_Rl (op)"))
>
> ; Predicate for stack protector guard's address in
> ; stack_protect_combined_set_insn and stack_protect_combined_test_insn
> patterns
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
> index 8aa04fcbdee..e92ecb0f6bc 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * addr, float32x4_t value)
> +foo (float32_t *base, float32x4_t value)
> {
> - vstrwq_f32 (addr, value);
> + return vstrwq_f32 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * addr, float32x4_t value)
> +foo1 (float32_t *base, float32x4_t value)
> {
> - vstrwq (addr, value);
> + return vstrwq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
> index 411de6414f7..f1992a67736 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * addr, float32x4_t value, mve_pred16_t p)
> +foo (float32_t *base, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_p_f32 (addr, value, p);
> + return vstrwq_p_f32 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p)
> +foo1 (float32_t *base, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_p (addr, value, p);
> + return vstrwq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
> index 3b042814d27..a00aeabb9fe 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * addr, int32x4_t value, mve_pred16_t p)
> +foo (int32_t *base, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_p_s32 (addr, value, p);
> + return vstrwq_p_s32 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p)
> +foo1 (int32_t *base, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_p (addr, value, p);
> + return vstrwq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
> index b9e92204c88..05fded8aac8 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
> +foo (uint32_t *base, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_p_u32 (addr, value, p);
> + return vstrwq_p_u32 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
> +foo1 (uint32_t *base, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_p (addr, value, p);
> + return vstrwq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
> index c7b3d91a972..b2a184f3c66 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * addr, int32x4_t value)
> +foo (int32_t *base, int32x4_t value)
> {
> - vstrwq_s32 (addr, value);
> + return vstrwq_s32 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * addr, int32x4_t value)
> +foo1 (int32_t *base, int32x4_t value)
> {
> - vstrwq (addr, value);
> + return vstrwq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
> index f8b56917295..c80e8d9cdc5 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo (uint32x4_t addr, float32x4_t value)
> {
> - vstrwq_scatter_base_f32 (addr, 8, value);
> + return vstrwq_scatter_base_f32 (addr, 0, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo1 (uint32x4_t addr, float32x4_t value)
> {
> - vstrwq_scatter_base (addr, 8, value);
> + return vstrwq_scatter_base (addr, 0, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
> index 4a75e6503e1..237843c0661 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo (uint32x4_t addr, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_p_f32 (addr, 8, value, p);
> + return vstrwq_scatter_base_p_f32 (addr, 0, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo1 (uint32x4_t addr, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_p (addr, 8, value, p);
> + return vstrwq_scatter_base_p (addr, 0, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
> index 5ac4f300a7d..5f4f4a09664 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo (uint32x4_t addr, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_p_s32 (addr, 8, value, p);
> + return vstrwq_scatter_base_p_s32 (addr, 0, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo1 (uint32x4_t addr, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_p (addr, 8, value, p);
> + return vstrwq_scatter_base_p (addr, 0, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
> index e564f26b9c7..8c5cf63f861 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo (uint32x4_t addr, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_p_u32 (addr, 8, value, p);
> + return vstrwq_scatter_base_p_u32 (addr, 0, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo1 (uint32x4_t addr, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_p (addr, 8, value, p);
> + return vstrwq_scatter_base_p (addr, 0, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
> index 5bba36db5cb..5208cf4f808 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo (uint32x4_t addr, int32x4_t value)
> {
> - vstrwq_scatter_base_s32 (addr, 8, value);
> + return vstrwq_scatter_base_s32 (addr, 0, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo1 (uint32x4_t addr, int32x4_t value)
> {
> - vstrwq_scatter_base (addr, 8, value);
> + return vstrwq_scatter_base (addr, 0, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
> index 1dcbb5a739c..e728db2b9f1 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo (uint32x4_t addr, uint32x4_t value)
> {
> - vstrwq_scatter_base_u32 (addr, 8, value);
> + return vstrwq_scatter_base_u32 (addr, 0, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo1 (uint32x4_t addr, uint32x4_t value)
> {
> - vstrwq_scatter_base (addr, 8, value);
> + return vstrwq_scatter_base (addr, 0, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
> index b2cc6e555ae..e481191aa57 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
> @@ -1,19 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32x4_t * addr, const int offset, float32x4_t value)
> +foo (uint32x4_t *addr, float32x4_t value)
> {
> - vstrwq_scatter_base_wb_f32 (addr, 8, value);
> + return vstrwq_scatter_base_wb_f32 (addr, 0, value);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32x4_t * addr, const int offset, float32x4_t value)
> +foo1 (uint32x4_t *addr, float32x4_t value)
> {
> - vstrwq_scatter_base_wb (addr, 8, value);
> + return vstrwq_scatter_base_wb (addr, 0, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-
> 9\]+\\\]!" 2 } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32
> .c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32
> .c
> index 4befd49d7b9..8d217d46230 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32
> .c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32
> .c
> @@ -1,19 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p)
> +foo (uint32x4_t *addr, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_wb_p_f32 (addr, 8, value, p);
> + return vstrwq_scatter_base_wb_p_f32 (addr, 0, value, p);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p)
> +foo1 (uint32x4_t *addr, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_wb_p (addr, 8, value, p);
> + return vstrwq_scatter_base_wb_p (addr, 0, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+,
> #\[0-9\]+\\\]!" 2 } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32
> .c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32
> .c
> index dfb1827c4f0..afc47adcd7f 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32
> .c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32
> .c
> @@ -1,19 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p)
> +foo (uint32x4_t *addr, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_wb_p_s32 (addr, 8, value, p);
> + return vstrwq_scatter_base_wb_p_s32 (addr, 0, value, p);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p)
> +foo1 (uint32x4_t *addr, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_wb_p (addr, 8, value, p);
> + return vstrwq_scatter_base_wb_p (addr, 0, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+,
> #\[0-9\]+\\\]!" 2 } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u3
> 2.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u3
> 2.c
> index 4eb78c600be..65191c2f1ed 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u3
> 2.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u3
> 2.c
> @@ -1,19 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p)
> +foo (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_wb_p_u32 (addr, 8, value, p);
> + return vstrwq_scatter_base_wb_p_u32 (addr, 0, value, p);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p)
> +foo1 (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_wb_p (addr, 8, value, p);
> + return vstrwq_scatter_base_wb_p (addr, 0, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+,
> #\[0-9\]+\\\]!" 2 } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
> index 618dbaf5aa6..b6a9f6cd1f4 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
> @@ -1,19 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32x4_t * addr, const int offset, int32x4_t value)
> +foo (uint32x4_t *addr, int32x4_t value)
> {
> - vstrwq_scatter_base_wb_s32 (addr, 8, value);
> + return vstrwq_scatter_base_wb_s32 (addr, 0, value);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32x4_t * addr, const int offset, int32x4_t value)
> +foo1 (uint32x4_t *addr, int32x4_t value)
> {
> - vstrwq_scatter_base_wb (addr, 8, value);
> + return vstrwq_scatter_base_wb (addr, 0, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-
> 9\]+\\\]!" 2 } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
> index 912a4590cf5..81a278f4e2b 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
> @@ -1,19 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32x4_t * addr, uint32x4_t value)
> +foo (uint32x4_t *addr, uint32x4_t value)
> {
> - vstrwq_scatter_base_wb_u32 (addr, 8, value);
> + return vstrwq_scatter_base_wb_u32 (addr, 0, value);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32x4_t * addr, uint32x4_t value)
> +foo1 (uint32x4_t *addr, uint32x4_t value)
> {
> - vstrwq_scatter_base_wb (addr, 8, value);
> + return vstrwq_scatter_base_wb (addr, 0, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-
> 9\]+\\\]!" 2 } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
> index c14d3ce607b..b81df68aa21 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * base, uint32x4_t offset, float32x4_t value)
> +foo (float32_t *base, uint32x4_t offset, float32x4_t value)
> {
> - vstrwq_scatter_offset_f32 (base, offset, value);
> + return vstrwq_scatter_offset_f32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value)
> +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value)
> {
> - vstrwq_scatter_offset (base, offset, value);
> + return vstrwq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
> index 115be56ec00..8aee42f76a3 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> +foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_offset_p_f32 (base, offset, value, p);
> + return vstrwq_scatter_offset_p_f32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_offset_p (base, offset, value, p);
> + return vstrwq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
> index 48652af3cff..9c74ae7a8d8 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> +foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_offset_p_s32 (base, offset, value, p);
> + return vstrwq_scatter_offset_p_s32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_offset_p (base, offset, value, p);
> + return vstrwq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
> index dcd42ec453f..015a202b548 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_offset_p_u32 (base, offset, value, p);
> + return vstrwq_scatter_offset_p_u32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_offset_p (base, offset, value, p);
> + return vstrwq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
> index 04672e5a4aa..df373111b78 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * base, uint32x4_t offset, int32x4_t value)
> +foo (int32_t *base, uint32x4_t offset, int32x4_t value)
> {
> - vstrwq_scatter_offset_s32 (base, offset, value);
> + return vstrwq_scatter_offset_s32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value)
> +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value)
> {
> - vstrwq_scatter_offset (base, offset, value);
> + return vstrwq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
> index e3d312550c6..a74696ca273 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value)
> +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value)
> {
> - vstrwq_scatter_offset_u32 (base, offset, value);
> + return vstrwq_scatter_offset_u32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value)
> +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value)
> {
> - vstrwq_scatter_offset (base, offset, value);
> + return vstrwq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f
> 32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f
> 32.c
> index b20c4c7ed3a..1c9b29a57b8 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f
> 32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f
> 32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * base, uint32x4_t offset, float32x4_t value)
> +foo (float32_t *base, uint32x4_t offset, float32x4_t value)
> {
> - vstrwq_scatter_shifted_offset_f32 (base, offset, value);
> + return vstrwq_scatter_shifted_offset_f32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value)
> +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value)
> {
> - vstrwq_scatter_shifted_offset (base, offset, value);
> + return vstrwq_scatter_shifted_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p
> _f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_
> p_f32.c
> index 1682f702dc6..08e1572854e 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p
> _f32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_
> p_f32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> +foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p);
> + return vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_shifted_offset_p (base, offset, value, p);
> + return vstrwq_scatter_shifted_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p
> _s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_
> p_s32.c
> index eef6ea6e196..2b8f8a7d61f 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p
> _s32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_
> p_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> +foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p);
> + return vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_shifted_offset_p (base, offset, value, p);
> + return vstrwq_scatter_shifted_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p
> _u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_
> p_u32.c
> index b11e7e04dc4..3e4e87bf79a 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p
> _u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_
> p_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p);
> + return vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_shifted_offset_p (base, offset, value, p);
> + return vstrwq_scatter_shifted_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s
> 32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s
> 32.c
> index 8ac25c47554..7f25490a69a 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s
> 32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s
> 32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * base, uint32x4_t offset, int32x4_t value)
> +foo (int32_t *base, uint32x4_t offset, int32x4_t value)
> {
> - vstrwq_scatter_shifted_offset_s32 (base, offset, value);
> + return vstrwq_scatter_shifted_offset_s32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value)
> +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value)
> {
> - vstrwq_scatter_shifted_offset (base, offset, value);
> + return vstrwq_scatter_shifted_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u
> 32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_
> u32.c
> index 1ce0ddacc7a..a96220c4f6e 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u
> 32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_
> u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value)
> +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value)
> {
> - vstrwq_scatter_shifted_offset_u32 (base, offset, value);
> + return vstrwq_scatter_shifted_offset_u32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value)
> +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value)
> {
> - vstrwq_scatter_shifted_offset (base, offset, value);
> + return vstrwq_scatter_shifted_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
> index 4aec9935b84..df554af79a6 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * addr, uint32x4_t value)
> +foo (uint32_t *base, uint32x4_t value)
> {
> - vstrwq_u32 (addr, value);
> + return vstrwq_u32 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * addr, uint32x4_t value)
> +foo1 (uint32_t *base, uint32x4_t value)
> {
> - vstrwq (addr, value);
> + return vstrwq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> --
> 2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH 03/10] arm: Mve backend + testsuite fixes 2
2023-04-28 11:29 ` [PATCH 03/10] arm: Mve backend + testsuite fixes 2 Andrea Corallo
@ 2023-04-28 16:40 ` Kyrylo Tkachov
2023-05-02 11:53 ` Andrea Corallo
0 siblings, 1 reply; 31+ messages in thread
From: Kyrylo Tkachov @ 2023-04-28 16:40 UTC (permalink / raw)
To: Andrea Corallo, gcc-patches; +Cc: Richard Earnshaw, Andrea Corallo
Hi Andrea,
> -----Original Message-----
> From: Andrea Corallo <andrea.corallo@arm.com>
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; Andrea Corallo <Andrea.Corallo@arm.com>
> Subject: [PATCH 03/10] arm: Mve backend + testsuite fixes 2
>
> Hi all,
>
> this patch improves a number of MVE tests in the testsuite for more
> precise and better coverage using check-function-bodies instead of
> scan-assembler checks. Also all intrusctions prescribed in the
> ACLE[1] are now checked.
>
> Also a number of simple fixes are done in the backend to fix
> capitalization and spacing.
Looks good, but I don't think the original patch made it to the list archives:
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/thread.html
You can commit this patch but please resend a compressed form of it to the list for archival.
Thanks,
Kyrill
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH 04/10] arm: Stop vadcq, vsbcq intrinsics from overwriting the FPSCR NZ flags
2023-04-28 11:29 ` [PATCH 04/10] arm: Stop vadcq, vsbcq intrinsics from overwriting the FPSCR NZ flags Andrea Corallo
@ 2023-04-28 16:45 ` Kyrylo Tkachov
2023-05-03 12:19 ` Stamatis Markianos-Wright
0 siblings, 1 reply; 31+ messages in thread
From: Kyrylo Tkachov @ 2023-04-28 16:45 UTC (permalink / raw)
To: Andrea Corallo, gcc-patches; +Cc: Richard Earnshaw, Stam Markianos-Wright
Hi Andrea, Stam,
> -----Original Message-----
> From: Andrea Corallo <andrea.corallo@arm.com>
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; Stam Markianos-Wright <Stam.Markianos-
> Wright@arm.com>
> Subject: [PATCH 04/10] arm: Stop vadcq, vsbcq intrinsics from overwriting the
> FPSCR NZ flags
>
> From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
>
> Hi all,
>
> We noticed that calls to the vadcq and vsbcq intrinsics, both of
> which use __builtin_arm_set_fpscr_nzcvqc to set the Carry flag in
> the FPSCR, would produce the following code:
>
> ```
> < r2 is the *carry input >
> vmrs r3, FPSCR_nzcvqc
> bic r3, r3, #536870912
> orr r3, r3, r2, lsl #29
> vmsr FPSCR_nzcvqc, r3
> ```
>
> when the MVE ACLE instead gives a different instruction sequence of:
> ```
> < Rt is the *carry input >
> VMRS Rs,FPSCR_nzcvqc
> BFI Rs,Rt,#29,#1
> VMSR FPSCR_nzcvqc,Rs
> ```
>
> the bic + orr pair is slower and it's also wrong, because, if the
> *carry input is greater than 1, then we risk overwriting the top two
> bits of the FPSCR register (the N and Z flags).
>
> This turned out to be a problem in the header file and the solution was
> to simply add a `& 1x0u` to the `*carry` input: then the compiler knows
> that we only care about the lowest bit and can optimise to a BFI.
>
> Ok for trunk?
Ok, but I think this needs testsuite coverage for the bug?
Thanks,
Kyrill
>
> Thanks,
> Stam Markianos-Wright
>
> gcc/ChangeLog:
>
> * config/arm/arm_mve.h (__arm_vadcq_s32): Fix arithmetic.
> (__arm_vadcq_u32): Likewise.
> (__arm_vadcq_m_s32): Likewise.
> (__arm_vadcq_m_u32): Likewise.
> (__arm_vsbcq_s32): Likewise.
> (__arm_vsbcq_u32): Likewise.
> (__arm_vsbcq_m_s32): Likewise.
> (__arm_vsbcq_m_u32): Likewise.
> ---
> gcc/config/arm/arm_mve.h | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
> index 1262d668121..8778216304b 100644
> --- a/gcc/config/arm/arm_mve.h
> +++ b/gcc/config/arm/arm_mve.h
> @@ -16055,7 +16055,7 @@ __extension__ extern __inline int32x4_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> __arm_vadcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry)
> {
> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> ~0x20000000u) | (*__carry << 29));
> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> ~0x20000000u) | ((*__carry & 0x1u) << 29));
> int32x4_t __res = __builtin_mve_vadcq_sv4si (__a, __b);
> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
> return __res;
> @@ -16065,7 +16065,7 @@ __extension__ extern __inline uint32x4_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> __arm_vadcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry)
> {
> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> ~0x20000000u) | (*__carry << 29));
> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> ~0x20000000u) | ((*__carry & 0x1u) << 29));
> uint32x4_t __res = __builtin_mve_vadcq_uv4si (__a, __b);
> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
> return __res;
> @@ -16075,7 +16075,7 @@ __extension__ extern __inline int32x4_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> __arm_vadcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b,
> unsigned * __carry, mve_pred16_t __p)
> {
> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> ~0x20000000u) | (*__carry << 29));
> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> ~0x20000000u) | ((*__carry & 0x1u) << 29));
> int32x4_t __res = __builtin_mve_vadcq_m_sv4si (__inactive, __a, __b, __p);
> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
> return __res;
> @@ -16085,7 +16085,7 @@ __extension__ extern __inline uint32x4_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> __arm_vadcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b,
> unsigned * __carry, mve_pred16_t __p)
> {
> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> ~0x20000000u) | (*__carry << 29));
> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> ~0x20000000u) | ((*__carry & 0x1u) << 29));
> uint32x4_t __res = __builtin_mve_vadcq_m_uv4si (__inactive, __a, __b,
> __p);
> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
> return __res;
> @@ -16131,7 +16131,7 @@ __extension__ extern __inline int32x4_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> __arm_vsbcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry)
> {
> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> ~0x20000000u) | (*__carry << 29));
> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> ~0x20000000u) | ((*__carry & 0x1u) << 29));
> int32x4_t __res = __builtin_mve_vsbcq_sv4si (__a, __b);
> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
> return __res;
> @@ -16141,7 +16141,7 @@ __extension__ extern __inline uint32x4_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> __arm_vsbcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry)
> {
> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> ~0x20000000u) | (*__carry << 29));
> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> ~0x20000000u) | ((*__carry & 0x1u) << 29));
> uint32x4_t __res = __builtin_mve_vsbcq_uv4si (__a, __b);
> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
> return __res;
> @@ -16151,7 +16151,7 @@ __extension__ extern __inline int32x4_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> __arm_vsbcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b,
> unsigned * __carry, mve_pred16_t __p)
> {
> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> ~0x20000000u) | (*__carry << 29));
> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> ~0x20000000u) | ((*__carry & 0x1u) << 29));
> int32x4_t __res = __builtin_mve_vsbcq_m_sv4si (__inactive, __a, __b, __p);
> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
> return __res;
> @@ -16161,7 +16161,7 @@ __extension__ extern __inline uint32x4_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> __arm_vsbcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b,
> unsigned * __carry, mve_pred16_t __p)
> {
> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> ~0x20000000u) | (*__carry << 29));
> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> ~0x20000000u) | ((*__carry & 0x1u) << 29));
> uint32x4_t __res = __builtin_mve_vsbcq_m_uv4si (__inactive, __a, __b,
> __p);
> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
> return __res;
> --
> 2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH 05/10] arm: Add vorrq_n overloading into vorrq _Generic
2023-04-28 11:29 ` [PATCH 05/10] arm: Add vorrq_n overloading into vorrq _Generic Andrea Corallo
@ 2023-04-28 16:47 ` Kyrylo Tkachov
0 siblings, 0 replies; 31+ messages in thread
From: Kyrylo Tkachov @ 2023-04-28 16:47 UTC (permalink / raw)
To: Andrea Corallo, gcc-patches; +Cc: Richard Earnshaw, Stam Markianos-Wright
> -----Original Message-----
> From: Andrea Corallo <andrea.corallo@arm.com>
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; Stam Markianos-Wright <Stam.Markianos-
> Wright@arm.com>
> Subject: [PATCH 05/10] arm: Add vorrq_n overloading into vorrq _Generic
>
> From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
>
> We found this as part of the wider testsuite updates.
>
> The applicable tests are authored by Andrea earlier in this patch series
>
> Ok for trunk?
Ok as a stopgap measure. I'm looking forward to the work from Christophe overhauling this whole part.
Thanks,
Kyrill
>
> gcc/ChangeLog:
>
> * config/arm/arm_mve.h (__arm_vorrq): Add _n variant.
> ---
> gcc/config/arm/arm_mve.h | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
> index 8778216304b..3d386f320c3 100644
> --- a/gcc/config/arm/arm_mve.h
> +++ b/gcc/config/arm/arm_mve.h
> @@ -35852,6 +35852,10 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]:
> __arm_vorrq_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]:
> __arm_vorrq_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce(__p1, float32x4_t)));})
>
> @@ -38637,7 +38641,11 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vorrq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t)));})
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)));})
>
> #define __arm_vornq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> --
> 2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH 06/10] arm: Fix overloading of MVE scalar constant parameters on vbicq, vmvnq_m
2023-04-28 11:29 ` [PATCH 06/10] arm: Fix overloading of MVE scalar constant parameters on vbicq, vmvnq_m Andrea Corallo
@ 2023-04-28 16:47 ` Kyrylo Tkachov
0 siblings, 0 replies; 31+ messages in thread
From: Kyrylo Tkachov @ 2023-04-28 16:47 UTC (permalink / raw)
To: Andrea Corallo, gcc-patches; +Cc: Richard Earnshaw, Stam Markianos-Wright
> -----Original Message-----
> From: Andrea Corallo <andrea.corallo@arm.com>
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; Stam Markianos-Wright <Stam.Markianos-
> Wright@arm.com>
> Subject: [PATCH 06/10] arm: Fix overloading of MVE scalar constant
> parameters on vbicq, vmvnq_m
>
> From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
>
> We found this as part of the wider testsuite updates.
>
> The applicable tests are authored by Andrea earlier in this patch series
>
> Ok for trunk?
Ok.
Thanks,
Kyrill
>
> gcc/ChangeLog:
>
> * config/arm/arm_mve.h (__arm_vbicq): Change coerce on
> scalar constant.
> (__arm_vmvnq_m): Likewise.
> ---
> gcc/config/arm/arm_mve.h | 24 ++++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
> index 3d386f320c3..3a1cffb4063 100644
> --- a/gcc/config/arm/arm_mve.h
> +++ b/gcc/config/arm/arm_mve.h
> @@ -35906,10 +35906,10 @@ extern void *__ARM_undef;
> #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce1 (__p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce1 (__p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce1 (__p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce1 (__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3 (p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3 (p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3 (p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3 (p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -38825,10 +38825,10 @@ extern void *__ARM_undef;
> #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce1 (__p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce1 (__p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce1 (__p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce1 (__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3 (p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3 (p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3 (p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3 (p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -40962,10 +40962,10 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vmvnq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vmvnq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vmvnq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce1(__p1, int) , p2), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce1(__p1, int) , p2), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce1(__p1, int) , p2), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce1(__p1, int) , p2));})
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int) , p2), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int) , p2), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int) , p2), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int) , p2));})
>
> #define __arm_vorrq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> --
> 2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH 07/10] arm: Fix MVE header pointer overloads this time (and a bit more tidying)
2023-04-28 11:29 ` [PATCH 07/10] arm: Fix MVE header pointer overloads this time (and a bit more tidying) Andrea Corallo
@ 2023-04-28 16:51 ` Kyrylo Tkachov
0 siblings, 0 replies; 31+ messages in thread
From: Kyrylo Tkachov @ 2023-04-28 16:51 UTC (permalink / raw)
To: Andrea Corallo, gcc-patches; +Cc: Richard Earnshaw, Stam Markianos-Wright
> -----Original Message-----
> From: Andrea Corallo <andrea.corallo@arm.com>
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; Stam Markianos-Wright <Stam.Markianos-
> Wright@arm.com>
> Subject: [PATCH 07/10] arm: Fix MVE header pointer overloads this time (and
> a bit more tidying)
>
> From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
>
> Hi all,
>
> Previously we had fixed the overloading of scalar arguments to intrinsics
> with the introduction of a new `__ARM_mve_coerce3` _ Generic association.
> This allowed users to give types other than int32_t, e.g. int, short, long,
> etc., which previously would emit a nonsensical error message from the
> _Generic.
>
> Here I adjust that handling slightly and I am also doing the same thing, but
> for pointer types:
> (un)signed char* can be now used instead of (u)int8_t*
> (un)signed short* can be now used instead of (u)int16_t*
> (un)signed int* and long* can be now used instead of (u)int32_t*
> (un)signed long long* can be now used instead of (u)int64_t*
> __fp16* and _Float16* can be now used instead of float16_t*
> float* can be now used instead of float32_t*
>
> This required me to break down the _coerce_ generics for the specific
> pointer types.
> On the scalar types, the change in this patch is minor, renaming the
> _coerce_ generics and passing all scalars through the `__typeof` for
> consistency with each-other.
>
Ok.
Thanks,
Kyrill
> No test regressions in the GCC testsuite or CMSIS-NN.
>
> * config/arm/arm_mve.h: (__ARM_mve_typeid): Add more pointer
> types.
> (__ARM_mve_coerce1): Remove.
> (__ARM_mve_coerce2): Remove.
> (__ARM_mve_coerce3): Remove.
> (__ARM_mve_coerce_i_scalar): New.
> (__ARM_mve_coerce_s8_ptr): New.
> (__ARM_mve_coerce_u8_ptr): New.
> (__ARM_mve_coerce_s16_ptr): New.
> (__ARM_mve_coerce_u16_ptr): New.
> (__ARM_mve_coerce_s32_ptr): New.
> (__ARM_mve_coerce_u32_ptr): New.
> (__ARM_mve_coerce_s64_ptr): New.
> (__ARM_mve_coerce_u64_ptr): New.
> (__ARM_mve_coerce_f_scalar): New.
> (__ARM_mve_coerce_f16_ptr): New.
> (__ARM_mve_coerce_f32_ptr): New.
> (__arm_vst4q): Change _coerce_ overloads.
> (__arm_vbicq): Change _coerce_ overloads.
> (__arm_vmulq): Change _coerce_ overloads.
> (__arm_vcmpeqq): Change _coerce_ overloads.
> (__arm_vcmpneq): Change _coerce_ overloads.
> (__arm_vmaxnmavq): Change _coerce_ overloads.
> (__arm_vmaxnmvq): Change _coerce_ overloads.
> (__arm_vminnmavq): Change _coerce_ overloads.
> (__arm_vsubq): Change _coerce_ overloads.
> (__arm_vminnmvq): Change _coerce_ overloads.
> (__arm_vrshlq): Change _coerce_ overloads.
> (__arm_vqsubq): Change _coerce_ overloads.
> (__arm_vqdmulltq): Change _coerce_ overloads.
> (__arm_vqdmullbq): Change _coerce_ overloads.
> (__arm_vqdmulhq): Change _coerce_ overloads.
> (__arm_vqaddq): Change _coerce_ overloads.
> (__arm_vhaddq): Change _coerce_ overloads.
> (__arm_vhsubq): Change _coerce_ overloads.
> (__arm_vqdmlashq): Change _coerce_ overloads.
> (__arm_vqrdmlahq): Change _coerce_ overloads.
> (__arm_vmlasq): Change _coerce_ overloads.
> (__arm_vqdmlahq): Change _coerce_ overloads.
> (__arm_vmaxnmavq_p): Change _coerce_ overloads.
> (__arm_vmaxnmvq_p): Change _coerce_ overloads.
> (__arm_vminnmavq_p): Change _coerce_ overloads.
> (__arm_vminnmvq_p): Change _coerce_ overloads.
> (__arm_vfmasq_m): Change _coerce_ overloads.
> (__arm_vld1q): Change _coerce_ overloads.
> (__arm_vld1q_z): Change _coerce_ overloads.
> (__arm_vld2q): Change _coerce_ overloads.
> (__arm_vld4q): Change _coerce_ overloads.
> (__arm_vldrhq_gather_offset): Change _coerce_ overloads.
> (__arm_vldrhq_gather_offset_z): Change _coerce_ overloads.
> (__arm_vldrhq_gather_shifted_offset): Change _coerce_ overloads.
> (__arm_vldrhq_gather_shifted_offset_z): Change _coerce_
> overloads.
> (__arm_vldrwq_gather_offset): Change _coerce_ overloads.
> (__arm_vldrwq_gather_offset_z): Change _coerce_ overloads.
> (__arm_vldrwq_gather_shifted_offset): Change _coerce_ overloads.
> (__arm_vldrwq_gather_shifted_offset_z): Change _coerce_
> overloads.
> (__arm_vst1q_p): Change _coerce_ overloads.
> (__arm_vst2q): Change _coerce_ overloads.
> (__arm_vst1q): Change _coerce_ overloads.
> (__arm_vstrhq): Change _coerce_ overloads.
> (__arm_vstrhq_p): Change _coerce_ overloads.
> (__arm_vstrhq_scatter_offset_p): Change _coerce_ overloads.
> (__arm_vstrhq_scatter_offset): Change _coerce_ overloads.
> (__arm_vstrhq_scatter_shifted_offset_p): Change _coerce_
> overloads.
> (__arm_vstrhq_scatter_shifted_offset): Change _coerce_ overloads.
> (__arm_vstrwq_p): Change _coerce_ overloads.
> (__arm_vstrwq): Change _coerce_ overloads.
> (__arm_vstrwq_scatter_offset): Change _coerce_ overloads.
> (__arm_vstrwq_scatter_offset_p): Change _coerce_ overloads.
> (__arm_vstrwq_scatter_shifted_offset): Change _coerce_ overloads.
> (__arm_vstrwq_scatter_shifted_offset_p): Change _coerce_
> overloads.
> (__arm_vsetq_lane): Change _coerce_ overloads.
> (__arm_vcmpneq_m): Change _coerce_ overloads.
> (__arm_vldrbq_gather_offset): Change _coerce_ overloads.
> (__arm_vdwdupq_x_u8): Change _coerce_ overloads.
> (__arm_vdwdupq_x_u16): Change _coerce_ overloads.
> (__arm_vdwdupq_x_u32): Change _coerce_ overloads.
> (__arm_viwdupq_x_u8): Change _coerce_ overloads.
> (__arm_viwdupq_x_u16): Change _coerce_ overloads.
> (__arm_viwdupq_x_u32): Change _coerce_ overloads.
> (__arm_vidupq_x_u8): Change _coerce_ overloads.
> (__arm_vddupq_x_u8): Change _coerce_ overloads.
> (__arm_vidupq_x_u16): Change _coerce_ overloads.
> (__arm_vddupq_x_u16): Change _coerce_ overloads.
> (__arm_vidupq_x_u32): Change _coerce_ overloads.
> (__arm_vddupq_x_u32): Change _coerce_ overloads.
> (__arm_vhaddq_x): Change _coerce_ overloads.
> (__arm_vhsubq_x): Change _coerce_ overloads.
> (__arm_vldrdq_gather_offset): Change _coerce_ overloads.
> (__arm_vldrdq_gather_offset_z): Change _coerce_ overloads.
> (__arm_vldrdq_gather_shifted_offset): Change _coerce_ overloads.
> (__arm_vldrdq_gather_shifted_offset_z): Change _coerce_ overloads.
> (__arm_vldrbq_gather_offset_z): Change _coerce_ overloads.
> (__arm_vqrdmlahq_m): Change _coerce_ overloads.
> (__arm_vqrdmlashq_m): Change _coerce_ overloads.
> (__arm_vqdmlashq_m): Change _coerce_ overloads.
> (__arm_vmlaldavaxq_p): Change _coerce_ overloads.
> (__arm_vmlasq_m): Change _coerce_ overloads.
> (__arm_vqdmulhq_m): Change _coerce_ overloads.
> (__arm_vqdmulltq_m): Change _coerce_ overloads.
> (__arm_vidupq_u16): Change _coerce_ overloads.
> (__arm_vidupq_u32): Change _coerce_ overloads.
> (__arm_vidupq_u8): Change _coerce_ overloads.
> (__arm_vddupq_u16): Change _coerce_ overloads.
> (__arm_vddupq_u32): Change _coerce_ overloads.
> (__arm_vddupq_u8): Change _coerce_ overloads.
> (__arm_viwdupq_m): Change _coerce_ overloads.
> (__arm_viwdupq_u16): Change _coerce_ overloads.
> (__arm_viwdupq_u32): Change _coerce_ overloads.
> (__arm_viwdupq_u8): Change _coerce_ overloads.
> (__arm_vdwdupq_m): Change _coerce_ overloads.
> (__arm_vdwdupq_u16): Change _coerce_ overloads.
> (__arm_vdwdupq_u32): Change _coerce_ overloads.
> (__arm_vdwdupq_u8): Change _coerce_ overloads.
> (__arm_vaddlvaq): Change _coerce_ overloads.
> (__arm_vaddlvaq_p): Change _coerce_ overloads.
> (__arm_vaddvaq): Change _coerce_ overloads.
> (__arm_vaddvaq_p): Change _coerce_ overloads.
> (__arm_vcmphiq_m): Change _coerce_ overloads.
> (__arm_vmladavaq_p): Change _coerce_ overloads.
> (__arm_vmladavaxq): Change _coerce_ overloads.
> (__arm_vmlaldavaxq): Change _coerce_ overloads.
> (__arm_vstrbq): Change _coerce_ overloads.
> (__arm_vstrbq_p): Change _coerce_ overloads.
> (__arm_vrmlaldavhaq_p): Change _coerce_ overloads.
> (__arm_vstrbq_scatter_offset): Change _coerce_ overloads.
> (__arm_vstrbq_scatter_offset_p): Change _coerce_ overloads.
> (__arm_vstrdq_scatter_offset_p): Change _coerce_ overloads.
> (__arm_vstrdq_scatter_offset): Change _coerce_ overloads.
> (__arm_vstrdq_scatter_shifted_offset_p): Change _coerce_
> overloads.
> (__arm_vstrdq_scatter_shifted_offset): Change _coerce_ overloads.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c:
> Add testcases.
> * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c:
> Add testcases.
> ---
> gcc/config/arm/arm_mve.h | 2056 +++++++++--------
> .../mve_intrinsic_type_overloads-fp.c | 55 +-
> .../mve_intrinsic_type_overloads-int.c | 74 +-
> 3 files changed, 1148 insertions(+), 1037 deletions(-)
>
> diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
> index 3a1cffb4063..71ea3ee275e 100644
> --- a/gcc/config/arm/arm_mve.h
> +++ b/gcc/config/arm/arm_mve.h
> @@ -35582,16 +35582,29 @@ enum {
> short: __ARM_mve_type_int_n, \
> int: __ARM_mve_type_int_n, \
> long: __ARM_mve_type_int_n, \
> + long long: __ARM_mve_type_int_n, \
> _Float16: __ARM_mve_type_fp_n, \
> __fp16: __ARM_mve_type_fp_n, \
> float: __ARM_mve_type_fp_n, \
> double: __ARM_mve_type_fp_n, \
> - long long: __ARM_mve_type_int_n, \
> unsigned char: __ARM_mve_type_int_n, \
> unsigned short: __ARM_mve_type_int_n, \
> unsigned int: __ARM_mve_type_int_n, \
> unsigned long: __ARM_mve_type_int_n, \
> unsigned long long: __ARM_mve_type_int_n, \
> + signed char*: __ARM_mve_type_int8_t_ptr, \
> + short*: __ARM_mve_type_int16_t_ptr, \
> + int*: __ARM_mve_type_int32_t_ptr, \
> + long*: __ARM_mve_type_int32_t_ptr, \
> + long long*: __ARM_mve_type_int64_t_ptr, \
> + _Float16*: __ARM_mve_type_float16_t_ptr, \
> + __fp16*: __ARM_mve_type_float16_t_ptr, \
> + float*: __ARM_mve_type_float32_t_ptr, \
> + unsigned char*: __ARM_mve_type_uint8_t_ptr, \
> + unsigned short*: __ARM_mve_type_uint16_t_ptr, \
> + unsigned int*: __ARM_mve_type_uint32_t_ptr, \
> + unsigned long*: __ARM_mve_type_uint32_t_ptr, \
> + unsigned long long*: __ARM_mve_type_uint64_t_ptr, \
> default: __ARM_mve_unsupported_type))
> #else
> #define __ARM_mve_typeid(x) _Generic(x, \
> @@ -35650,32 +35663,67 @@ enum {
> unsigned int: __ARM_mve_type_int_n, \
> unsigned long: __ARM_mve_type_int_n, \
> unsigned long long: __ARM_mve_type_int_n, \
> + signed char*: __ARM_mve_type_int8_t_ptr, \
> + short*: __ARM_mve_type_int16_t_ptr, \
> + int*: __ARM_mve_type_int32_t_ptr, \
> + long*: __ARM_mve_type_int32_t_ptr, \
> + long long*: __ARM_mve_type_int64_t_ptr, \
> + unsigned char*: __ARM_mve_type_uint8_t_ptr, \
> + unsigned short*: __ARM_mve_type_uint16_t_ptr, \
> + unsigned int*: __ARM_mve_type_uint32_t_ptr, \
> + unsigned long*: __ARM_mve_type_uint32_t_ptr, \
> + unsigned long long*: __ARM_mve_type_uint64_t_ptr, \
> default: __ARM_mve_unsupported_type))
> #endif /* MVE Floating point. */
>
> extern void *__ARM_undef;
> #define __ARM_mve_coerce(param, type) \
> _Generic(param, type: param, default: *(type *)__ARM_undef)
> -#define __ARM_mve_coerce1(param, type) \
> - _Generic(param, type: param, const type: param, default: *(type
> *)__ARM_undef)
> -#define __ARM_mve_coerce2(param, type) \
> - _Generic(param, type: param, __fp16: param, default: _Generic (param,
> _Float16: param, float16_t: param, float32_t: param, default: *(type
> *)__ARM_undef))
> -#define __ARM_mve_coerce3(param, type) \
> - _Generic(param, type: param, default: _Generic (param, int8_t: param,
> int16_t: param, int32_t: param, int64_t: param, uint8_t: param, uint16_t:
> param, uint32_t: param, uint64_t: param, default: *(type *)__ARM_undef))
> +#define __ARM_mve_coerce_i_scalar(param, type) \
> + _Generic(param, type: param, const type: param, default: _Generic
> (param, int8_t: param, int16_t: param, int32_t: param, int64_t: param,
> uint8_t: param, uint16_t: param, uint32_t: param, uint64_t: param, default:
> *(type *)__ARM_undef))
> +
> +#define __ARM_mve_coerce_s8_ptr(param, type) \
> + _Generic(param, type: param, const type: param, default: _Generic
> (param, signed char*: param, default: *(type *)__ARM_undef))
> +#define __ARM_mve_coerce_u8_ptr(param, type) \
> + _Generic(param, type: param, const type: param, default: _Generic
> (param, unsigned char*: param, default: *(type *)__ARM_undef))
> +
> +#define __ARM_mve_coerce_s16_ptr(param, type) \
> + _Generic(param, type: param, const type: param, default: _Generic
> (param, short*: param, default: *(type *)__ARM_undef))
> +#define __ARM_mve_coerce_u16_ptr(param, type) \
> + _Generic(param, type: param, const type: param, default: _Generic
> (param, unsigned short*: param, default: *(type *)__ARM_undef))
> +
> +#define __ARM_mve_coerce_s32_ptr(param, type) \
> + _Generic(param, type: param, const type: param, default: _Generic
> (param, int*: param, long*: param, default: *(type *)__ARM_undef))
> +#define __ARM_mve_coerce_u32_ptr(param, type) \
> + _Generic(param, type: param, const type: param, default: _Generic
> (param, unsigned int*: param, unsigned long*: param, default: *(type
> *)__ARM_undef))
> +
> +#define __ARM_mve_coerce_s64_ptr(param, type) \
> + _Generic(param, type: param, const type: param, default: _Generic
> (param, long long*: param, default: *(type *)__ARM_undef))
> +#define __ARM_mve_coerce_u64_ptr(param, type) \
> + _Generic(param, type: param, const type: param, default: _Generic
> (param, unsigned long long*: param, default: *(type *)__ARM_undef))
> +
> +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */
> +#define __ARM_mve_coerce_f_scalar(param, type) \
> + _Generic(param, type: param, const type: param, __fp16: param, default:
> _Generic (param, _Float16: param, float16_t: param, float32_t: param,
> default: *(type *)__ARM_undef))
> +#define __ARM_mve_coerce_f16_ptr(param, type) \
> + _Generic(param, type: param, const type: param, default: _Generic
> (param, __fp16*: param, _Float16*: param, default: *(type *)__ARM_undef))
> +#define __ARM_mve_coerce_f32_ptr(param, type) \
> + _Generic(param, type: param, const type: param, default: _Generic
> (param, float*: param, default: *(type *)__ARM_undef))
> +#endif
>
> #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */
>
> #define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]:
> __arm_vst4q_s8 (__ARM_mve_coerce(__p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16x4_t)), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]:
> __arm_vst4q_s16 (__ARM_mve_coerce(__p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8x4_t)), \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]:
> __arm_vst4q_s32 (__ARM_mve_coerce(__p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4x4_t)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]:
> __arm_vst4q_u8 (__ARM_mve_coerce(__p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16x4_t)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]:
> __arm_vst4q_u16 (__ARM_mve_coerce(__p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8x4_t)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]:
> __arm_vst4q_u32 (__ARM_mve_coerce(__p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4x4_t)), \
> - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]:
> __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *),
> __ARM_mve_coerce(__p1, float16x8x4_t)), \
> - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]:
> __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *),
> __ARM_mve_coerce(__p1, float32x4x4_t)));})
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]:
> __arm_vst4q_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16x4_t)), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]:
> __arm_vst4q_s16 (__ARM_mve_coerce_s16_ptr(__p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8x4_t)), \
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]:
> __arm_vst4q_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4x4_t)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]:
> __arm_vst4q_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16x4_t)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]:
> __arm_vst4q_u16 (__ARM_mve_coerce_u16_ptr(__p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8x4_t)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]:
> __arm_vst4q_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4x4_t)), \
> + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]:
> __arm_vst4q_f16 (__ARM_mve_coerce_f16_ptr(__p0, float16_t *),
> __ARM_mve_coerce(__p1, float16x8x4_t)), \
> + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]:
> __arm_vst4q_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *),
> __ARM_mve_coerce(__p1, float32x4x4_t)));})
>
> #define __arm_vrndxq(p0) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> @@ -35852,10 +35900,10 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]:
> __arm_vorrq_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]:
> __arm_vorrq_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce(__p1, float32x4_t)));})
>
> @@ -35882,14 +35930,14 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]:
> __arm_vaddq_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]:
> __arm_vaddq_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce(__p1, float32x4_t)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce2(p1, double)), \
> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce2(p1, double)));})
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p1, double)), \
> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p1, double)));})
>
> #define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -35906,10 +35954,10 @@ extern void *__ARM_undef;
> #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3 (p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3 (p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3 (p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3 (p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar (__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar (__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar (__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar (__p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -35934,14 +35982,14 @@ extern void *__ARM_undef;
> #define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce2(p1, double)), \
> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce2(p1, double)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p1, double)), \
> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p1, double)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -35966,14 +36014,14 @@ extern void *__ARM_undef;
> #define __arm_vcmpeqq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce2(p1, double)), \
> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce2(p1, double)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p1, double)), \
> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p1, double)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vcmpeqq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vcmpeqq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpeqq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -36004,16 +36052,16 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int), p2), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]:
> __arm_vcmpeqq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce(__p1, float16x8_t), p2), \
> int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]:
> __arm_vcmpeqq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce(__p1, float32x4_t), p2), \
> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce2(p1, double), p2), \
> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce2(p1, double), p2));})
> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p1, double), p2), \
> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p1, double), p2));})
>
> #define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -36021,13 +36069,13 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]:
> __arm_vcmpgtq_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]:
> __arm_vcmpgtq_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce(__p1, float32x4_t)), \
> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce2(p1, double)), \
> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce2(p1, double)));})
> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p1, double)), \
> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p1, double)));})
>
> #define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -36037,11 +36085,11 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]:
> __arm_vcmpleq_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]:
> __arm_vcmpleq_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce(__p1, float32x4_t)), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce2(p1, double)), \
> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce2(p1, double)));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p1, double)), \
> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p1, double)));})
>
> #define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -36049,25 +36097,25 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]:
> __arm_vcmpltq_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]:
> __arm_vcmpltq_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce(__p1, float32x4_t)), \
> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce2(p1, double)), \
> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce2(p1, double)));})
> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p1, double)), \
> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p1, double)));})
>
> #define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce2(p1, double)), \
> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce2(p1, double)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p1, double)), \
> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p1, double)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -36122,8 +36170,8 @@ extern void *__ARM_undef;
> #define __arm_vmaxnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vmaxnmavq_f16 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vmaxnmavq_f32 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float32x4_t)));})
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vmaxnmavq_f16 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vmaxnmavq_f32 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float32x4_t)));})
>
> #define __arm_vmaxnmq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -36134,14 +36182,14 @@ extern void *__ARM_undef;
> #define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float32x4_t)));})
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vmaxnmvq_f16 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vmaxnmvq_f32 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float32x4_t)));})
>
> #define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float32x4_t)));})
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vmaxnmvq_f16 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vmaxnmvq_f32 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float32x4_t)));})
>
> #define __arm_vminnmaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -36152,8 +36200,8 @@ extern void *__ARM_undef;
> #define __arm_vminnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vminnmavq_f16 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vminnmavq_f32 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float32x4_t)));})
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vminnmavq_f16 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vminnmavq_f32 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float32x4_t)));})
>
> #define __arm_vbrsrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> @@ -36175,14 +36223,14 @@ extern void *__ARM_undef;
> #define __arm_vsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce2(p1, double)), \
> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce2(p1, double)), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p1, double)), \
> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p1, double)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -36195,8 +36243,8 @@ extern void *__ARM_undef;
> #define __arm_vminnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vminnmvq_f16 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vminnmvq_f32 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float32x4_t)));})
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vminnmvq_f16 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vminnmvq_f32 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float32x4_t)));})
>
> #define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> @@ -36251,12 +36299,12 @@ extern void *__ARM_undef;
> #define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -36287,12 +36335,12 @@ extern void *__ARM_undef;
> #define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -36343,12 +36391,12 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)));})
>
> #define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -36356,9 +36404,9 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)));})
>
> #define __arm_vmlaldavxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -36391,8 +36439,8 @@ extern void *__ARM_undef;
> #define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)));})
>
> @@ -36405,17 +36453,17 @@ extern void *__ARM_undef;
> #define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)));})
>
> #define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)));})
> @@ -36423,12 +36471,12 @@ extern void *__ARM_undef;
> #define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -36461,12 +36509,12 @@ extern void *__ARM_undef;
> #define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -36491,12 +36539,12 @@ extern void *__ARM_undef;
> #define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -36639,12 +36687,12 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \
> - int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \
> - int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2,
> int)), \
> - int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2,
> int)));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int)), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2,
> int)), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2,
> int)), \
> + int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int)), \
> + int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int)), \
> + int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int)));})
>
> #define __arm_vsriq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -36723,44 +36771,44 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2,
> int)), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int)), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int)));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int)), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int)), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int)));})
>
> #define __arm_vqdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2,
> int)), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int)), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int)));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int)), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int)), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int)));})
>
> #define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int)), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int)));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int)), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int)), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int)));})
>
> #define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \
> - int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2,
> int)), \
> - int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2,
> int)), \
> - int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2,
> int)));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int)), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2,
> int)), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2,
> int)), \
> + int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int)), \
> + int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int)), \
> + int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int)));})
>
> #define __arm_vqdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int)), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int)));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int)), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int)), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int)));})
>
> #define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -36950,11 +36998,11 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpgtq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce2(p1, double), p2), \
> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpgtq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce2(p1, double), p2), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpgtq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p1, double), p2), \
> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpgtq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p1, double), p2), \
> int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]:
> __arm_vcmpgtq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce(__p1, float16x8_t), p2), \
> int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]:
> __arm_vcmpgtq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce(__p1, float32x4_t), p2));})
>
> @@ -36966,11 +37014,11 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]:
> __arm_vcmpleq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce(__p1, float16x8_t), p2), \
> int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]:
> __arm_vcmpleq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce(__p1, float32x4_t), p2), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpleq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce2(p1, double), p2), \
> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpleq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce2(p1, double), p2));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpleq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p1, double), p2), \
> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpleq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p1, double), p2));})
>
> #define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -36980,11 +37028,11 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]:
> __arm_vcmpltq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce(__p1, float16x8_t), p2), \
> int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]:
> __arm_vcmpltq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce(__p1, float32x4_t), p2), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpltq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce2(p1, double), p2), \
> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpltq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce2(p1, double), p2));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpltq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p1, double), p2), \
> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpltq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p1, double), p2));})
>
> #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -36997,14 +37045,14 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]:
> __arm_vcmpneq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce(__p1, float16x8_t), p2), \
> int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]:
> __arm_vcmpneq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce(__p1, float32x4_t), p2), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpneq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce2(p1, double), p2), \
> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpneq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce2(p1, double), p2));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpneq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p1, double), p2), \
> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpneq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p1, double), p2));})
>
> #define __arm_vcvtbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -37058,8 +37106,8 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_fp_n]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce2(p2, double)), \
> - int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_fp_n]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce2(p2, double)), \
> + int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_fp_n]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p2, double)), \
> + int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_fp_n]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p2, double)), \
> int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vfmaq_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce(__p2, float16x8_t)), \
> int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_float32x4_t]: __arm_vfmaq_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce(__p2, float32x4_t)));})
>
> @@ -37074,8 +37122,8 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_fp_n]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce2(p2, double)), \
> - int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_fp_n]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce2(p2, double)));})
> + int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_fp_n]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p2, double)), \
> + int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_fp_n]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p2, double)));})
>
> #define __arm_vmaxnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -37098,14 +37146,14 @@ extern void *__ARM_undef;
> #define __arm_vmaxnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vmaxnmavq_p_f16 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float16x8_t), p2), \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vmaxnmavq_p_f32 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float32x4_t), p2));})
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vmaxnmavq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float16x8_t), p2), \
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vmaxnmavq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float32x4_t), p2));})
>
> #define __arm_vmaxnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vmaxnmvq_p_f16 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float16x8_t), p2), \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vmaxnmvq_p_f32 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float32x4_t), p2));})
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vmaxnmvq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float16x8_t), p2), \
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vmaxnmvq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float32x4_t), p2));})
>
> #define __arm_vminnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -37116,14 +37164,14 @@ extern void *__ARM_undef;
> #define __arm_vminnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vminnmavq_p_f16 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float16x8_t), p2), \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vminnmavq_p_f32 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float32x4_t), p2));})
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vminnmavq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float16x8_t), p2), \
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vminnmavq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float32x4_t), p2));})
>
> #define __arm_vminnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vminnmvq_p_f16 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float16x8_t), p2), \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vminnmvq_p_f32 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float32x4_t), p2));})
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vminnmvq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float16x8_t), p2), \
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vminnmvq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float32x4_t), p2));})
>
> #define __arm_vrndnq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -37185,13 +37233,13 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]:
> __arm_vcmpgeq_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]:
> __arm_vcmpgeq_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce(__p1, float32x4_t)), \
> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce2(p1, double)), \
> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce2(p1, double)));})
> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p1, double)), \
> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p1, double)));})
>
> #define __arm_vrshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -37292,11 +37340,11 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce2(p1, double), p2), \
> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce2(p1, double), p2), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p1, double), p2), \
> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p1, double), p2), \
> int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]:
> __arm_vcmpgeq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t),
> __ARM_mve_coerce(__p1, float16x8_t), p2), \
> int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]:
> __arm_vcmpgeq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t),
> __ARM_mve_coerce(__p1, float32x4_t), p2));})
>
> @@ -37325,14 +37373,14 @@ extern void *__ARM_undef;
> int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_uint32x4_t]: __arm_vaddq_m_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vaddq_m_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce(__p2, float16x8_t), p3), \
> int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_float32x4_t]: __arm_vaddq_m_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce(__p2, float32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce2(p2, double), p3), \
> - int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce2(p2, double), p3));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p2, double), p3), \
> + int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p2, double), p3));})
>
> #define __arm_vandq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -37473,15 +37521,15 @@ extern void *__ARM_undef;
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vfmaq_m_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce(__p2, float16x8_t), p3), \
> int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_float32x4_t]: __arm_vfmaq_m_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce(__p2, float32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_fp_n]: __arm_vfmaq_m_n_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce2(p2, double), p3), \
> - int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_fp_n]: __arm_vfmaq_m_n_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce2(p2, double), p3));})
> + int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_fp_n]: __arm_vfmaq_m_n_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p2, double), p3), \
> + int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_fp_n]: __arm_vfmaq_m_n_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p2, double), p3));})
>
> #define __arm_vfmasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_fp_n]: __arm_vfmasq_m_n_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce2(p2, double), p3), \
> - int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_fp_n]: __arm_vfmasq_m_n_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce2(p2, double), p3));})
> + int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_fp_n]: __arm_vfmasq_m_n_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p2, double), p3), \
> + int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_fp_n]: __arm_vfmasq_m_n_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p2, double), p3));})
>
> #define __arm_vfmsq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -37516,14 +37564,14 @@ extern void *__ARM_undef;
> int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_uint32x4_t]: __arm_vmulq_m_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vmulq_m_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce(__p2, float16x8_t), p3), \
> int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_float32x4_t]: __arm_vmulq_m_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce(__p2, float32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_fp_n]: __arm_vmulq_m_n_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce2(p2, double), p3), \
> - int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_fp_n]: __arm_vmulq_m_n_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce2(p2, double), p3));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_fp_n]: __arm_vmulq_m_n_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p2, double), p3), \
> + int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_fp_n]: __arm_vmulq_m_n_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p2, double), p3));})
>
> #define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -37550,14 +37598,14 @@ extern void *__ARM_undef;
> int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_uint32x4_t]: __arm_vsubq_m_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vsubq_m_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce(__p2, float16x8_t), p3), \
> int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_float32x4_t]: __arm_vsubq_m_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce(__p2, float32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_fp_n]: __arm_vsubq_m_n_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce2(p2, double), p3), \
> - int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_fp_n]: __arm_vsubq_m_n_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce2(p2, double), p3));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_
> mve_type_fp_n]: __arm_vsubq_m_n_f16 (__ARM_mve_coerce(__p0,
> float16x8_t), __ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p2, double), p3), \
> + int
> (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_
> mve_type_fp_n]: __arm_vsubq_m_n_f32 (__ARM_mve_coerce(__p0,
> float32x4_t), __ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p2, double), p3));})
>
> #define __arm_vorrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -37574,236 +37622,236 @@ extern void *__ARM_undef;
>
> #define __arm_vld1q(p0) (\
> _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8
> (__ARM_mve_coerce1(p0, int8_t *)), \
> - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16
> (__ARM_mve_coerce1(p0, int16_t *)), \
> - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32
> (__ARM_mve_coerce1(p0, int32_t *)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8
> (__ARM_mve_coerce1(p0, uint8_t *)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16
> (__ARM_mve_coerce1(p0, uint16_t *)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32
> (__ARM_mve_coerce1(p0, uint32_t *)), \
> - int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16
> (__ARM_mve_coerce1(p0, float16_t *)), \
> - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32
> (__ARM_mve_coerce1(p0, float32_t *))))
> + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8
> (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
> + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
> + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32
> (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8
> (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32
> (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \
> + int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16
> (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \
> + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32
> (__ARM_mve_coerce_f32_ptr(p0, float32_t *))))
>
> #define __arm_vld1q_z(p0,p1) ( \
> _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8
> (__ARM_mve_coerce1(p0, int8_t *), p1), \
> - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16
> (__ARM_mve_coerce1(p0, int16_t *), p1), \
> - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32
> (__ARM_mve_coerce1(p0, int32_t *), p1), \
> - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8
> (__ARM_mve_coerce1(p0, uint8_t *), p1), \
> - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16
> (__ARM_mve_coerce1(p0, uint16_t *), p1), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32
> (__ARM_mve_coerce1(p0, uint32_t *), p1), \
> - int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16
> (__ARM_mve_coerce1(p0, float16_t *), p1), \
> - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32
> (__ARM_mve_coerce1(p0, float32_t *), p1)))
> + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8
> (__ARM_mve_coerce_s8_ptr(p0, int8_t *), p1), \
> + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), p1), \
> + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32
> (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \
> + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8
> (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), p1), \
> + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), p1), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32
> (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \
> + int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16
> (__ARM_mve_coerce_f16_ptr(p0, float16_t *), p1), \
> + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32
> (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1)))
>
> #define __arm_vld2q(p0) ( \
> _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8
> (__ARM_mve_coerce1(p0, int8_t *)), \
> - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16
> (__ARM_mve_coerce1(p0, int16_t *)), \
> - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32
> (__ARM_mve_coerce1(p0, int32_t *)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8
> (__ARM_mve_coerce1(p0, uint8_t *)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16
> (__ARM_mve_coerce1(p0, uint16_t *)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32
> (__ARM_mve_coerce1(p0, uint32_t *)), \
> - int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld2q_f16
> (__ARM_mve_coerce1(p0, float16_t *)), \
> - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld2q_f32
> (__ARM_mve_coerce1(p0, float32_t *))))
> + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8
> (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
> + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
> + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32
> (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8
> (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32
> (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \
> + int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld2q_f16
> (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \
> + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld2q_f32
> (__ARM_mve_coerce_f32_ptr(p0, float32_t *))))
>
> #define __arm_vld4q(p0) ( \
> _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8
> (__ARM_mve_coerce1(p0, int8_t *)), \
> - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16
> (__ARM_mve_coerce1(p0, int16_t *)), \
> - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32
> (__ARM_mve_coerce1(p0, int32_t *)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8
> (__ARM_mve_coerce1(p0, uint8_t *)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16
> (__ARM_mve_coerce1(p0, uint16_t *)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32
> (__ARM_mve_coerce1(p0, uint32_t *)), \
> - int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld4q_f16
> (__ARM_mve_coerce1(p0, float16_t *)), \
> - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld4q_f32
> (__ARM_mve_coerce1(p0, float32_t *))))
> + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8
> (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
> + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
> + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32
> (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8
> (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32
> (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \
> + int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld4q_f16
> (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \
> + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld4q_f32
> (__ARM_mve_coerce_f32_ptr(p0, float32_t *))))
>
> #define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce1(p0, int16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce1(p0, int16_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_f16 (__ARM_mve_coerce1(p0, float16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)));})
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t
> *), __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t
> *), __ARM_mve_coerce(__p1, uint32x4_t)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t
> *), __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t
> *), __ARM_mve_coerce(__p1, uint32x4_t)), \
> + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t
> *), __ARM_mve_coerce(__p1, uint16x8_t)));})
>
> #define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 =
> (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_z_f16 (__ARM_mve_coerce1(p0, float16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t), p2));})
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t
> *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t
> *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0,
> uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0,
> uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_z_f16 (__ARM_mve_coerce_f16_ptr(p0,
> float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));})
>
> #define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p1) __p1 =
> (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce1(p0, int16_t
> *), __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int16_t
> *), __ARM_mve_coerce(__p1, uint32x4_t)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce1(p0, uint16_t
> *), __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint16_t
> *), __ARM_mve_coerce(__p1, uint32x4_t)), \
> - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_f16 (__ARM_mve_coerce1(p0, float16_t
> *), __ARM_mve_coerce(__p1, uint16x8_t)));})
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0,
> int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0,
> int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0,
> uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0,
> uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
> + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0,
> float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));})
>
> #define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p1)
> __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce1(p0,
> int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0,
> int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce1(p0,
> uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0,
> uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_z_f16 (__ARM_mve_coerce1(p0,
> float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));})
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_z_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_shifted_offset_z_s32
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), p2), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_z_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_shifted_offset_z_u32
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), p2), \
> + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_z_f16 (__ARM_mve_coerce_f16_ptr(p0,
> float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));})
>
> #define __arm_vldrwq_gather_offset(p0,p1) ( \
> _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32
> (__ARM_mve_coerce1(p0, int32_t *), p1), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32
> (__ARM_mve_coerce1(p0, uint32_t *), p1), \
> - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_f32
> (__ARM_mve_coerce1(p0, float32_t *), p1)))
> + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32
> (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32
> (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \
> + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_f32
> (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1)))
>
> #define __arm_vldrwq_gather_offset_z(p0,p1,p2) ( \
> _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32
> (__ARM_mve_coerce1(p0, int32_t *), p1, p2), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]:
> __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint32_t *),
> p1, p2), \
> - int (*)[__ARM_mve_type_float32_t_ptr]:
> __arm_vldrwq_gather_offset_z_f32 (__ARM_mve_coerce1(p0, float32_t *),
> p1, p2)))
> + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32
> (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1, p2), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]:
> __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce_u32_ptr(p0,
> uint32_t *), p1, p2), \
> + int (*)[__ARM_mve_type_float32_t_ptr]:
> __arm_vldrwq_gather_offset_z_f32 (__ARM_mve_coerce_f32_ptr(p0,
> float32_t *), p1, p2)))
>
> #define __arm_vldrwq_gather_shifted_offset(p0,p1) ( \
> _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int32_t
> *), p1), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0,
> uint32_t *), p1), \
> - int (*)[__ARM_mve_type_float32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_f32 (__ARM_mve_coerce1(p0,
> float32_t *), p1)))
> + int (*)[__ARM_mve_type_int32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0,
> int32_t *), p1), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0,
> uint32_t *), p1), \
> + int (*)[__ARM_mve_type_float32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0,
> float32_t *), p1)))
>
> #define __arm_vldrwq_gather_shifted_offset_z(p0,p1,p2) ( \
> _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0,
> int32_t *), p1, p2), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0,
> uint32_t *), p1, p2), \
> - int (*)[__ARM_mve_type_float32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_z_f32 (__ARM_mve_coerce1(p0,
> float32_t *), p1, p2)))
> + int (*)[__ARM_mve_type_int32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_z_s32
> (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1, p2), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_z_u32
> (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1, p2), \
> + int (*)[__ARM_mve_type_float32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_z_f32
> (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1, p2)))
>
> #define __arm_vst1q_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]:
> __arm_vst1q_p_s8 (__ARM_mve_coerce(p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vst1q_p_s16 (__ARM_mve_coerce(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vst1q_p_s32 (__ARM_mve_coerce(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vst1q_p_u8 (__ARM_mve_coerce(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vst1q_p_u16 (__ARM_mve_coerce(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vst1q_p_u32 (__ARM_mve_coerce(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]:
> __arm_vst1q_p_f16 (__ARM_mve_coerce(p0, float16_t *),
> __ARM_mve_coerce(__p1, float16x8_t), p2), \
> - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vst1q_p_f32 (__ARM_mve_coerce(p0, float32_t *),
> __ARM_mve_coerce(__p1, float32x4_t), p2));})
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]:
> __arm_vst1q_p_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vst1q_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vst1q_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vst1q_p_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vst1q_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vst1q_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]:
> __arm_vst1q_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *),
> __ARM_mve_coerce(__p1, float16x8_t), p2), \
> + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vst1q_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *),
> __ARM_mve_coerce(__p1, float32x4_t), p2));})
>
> #define __arm_vst2q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]:
> __arm_vst2q_s8 (__ARM_mve_coerce(p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16x2_t)), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]:
> __arm_vst2q_s16 (__ARM_mve_coerce(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8x2_t)), \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]:
> __arm_vst2q_s32 (__ARM_mve_coerce(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4x2_t)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]:
> __arm_vst2q_u8 (__ARM_mve_coerce(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16x2_t)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]:
> __arm_vst2q_u16 (__ARM_mve_coerce(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8x2_t)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]:
> __arm_vst2q_u32 (__ARM_mve_coerce(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4x2_t)), \
> - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x2_t]:
> __arm_vst2q_f16 (__ARM_mve_coerce(p0, float16_t *),
> __ARM_mve_coerce(__p1, float16x8x2_t)), \
> - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x2_t]:
> __arm_vst2q_f32 (__ARM_mve_coerce(p0, float32_t *),
> __ARM_mve_coerce(__p1, float32x4x2_t)));})
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]:
> __arm_vst2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16x2_t)), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]:
> __arm_vst2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8x2_t)), \
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]:
> __arm_vst2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4x2_t)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]:
> __arm_vst2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16x2_t)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]:
> __arm_vst2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8x2_t)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]:
> __arm_vst2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4x2_t)), \
> + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x2_t]:
> __arm_vst2q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *),
> __ARM_mve_coerce(__p1, float16x8x2_t)), \
> + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x2_t]:
> __arm_vst2q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *),
> __ARM_mve_coerce(__p1, float32x4x2_t)));})
>
> #define __arm_vst1q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]:
> __arm_vst1q_s8 (__ARM_mve_coerce(p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vst1q_s16 (__ARM_mve_coerce(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vst1q_s32 (__ARM_mve_coerce(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vst1q_u8 (__ARM_mve_coerce(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vst1q_u16 (__ARM_mve_coerce(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vst1q_u32 (__ARM_mve_coerce(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]:
> __arm_vst1q_f16 (__ARM_mve_coerce(p0, float16_t *),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vst1q_f32 (__ARM_mve_coerce(p0, float32_t *),
> __ARM_mve_coerce(__p1, float32x4_t)));})
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]:
> __arm_vst1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vst1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vst1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vst1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vst1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vst1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]:
> __arm_vst1q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *),
> __ARM_mve_coerce(__p1, float16x8_t)), \
> + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vst1q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *),
> __ARM_mve_coerce(__p1, float32x4_t)));})
>
> #define __arm_vstrhq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vstrhq_s16 (__ARM_mve_coerce(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrhq_s32 (__ARM_mve_coerce(p0, int16_t *),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vstrhq_u16 (__ARM_mve_coerce(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrhq_u32 (__ARM_mve_coerce(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]:
> __arm_vstrhq_f16 (__ARM_mve_coerce(p0, float16_t *),
> __ARM_mve_coerce(__p1, float16x8_t)));})
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vstrhq_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrhq_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vstrhq_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrhq_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]:
> __arm_vstrhq_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *),
> __ARM_mve_coerce(__p1, float16x8_t)));})
>
> #define __arm_vstrhq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vstrhq_p_s16 (__ARM_mve_coerce(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrhq_p_s32 (__ARM_mve_coerce(p0, int16_t *),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vstrhq_p_u16 (__ARM_mve_coerce(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrhq_p_u32 (__ARM_mve_coerce(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> - int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]:
> __arm_vstrhq_p_f16 (__ARM_mve_coerce(p0, float16_t *),
> __ARM_mve_coerce(__p1, float16x8_t), p2));})
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vstrhq_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrhq_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vstrhq_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrhq_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]:
> __arm_vstrhq_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *),
> __ARM_mve_coerce(__p1, float16x8_t), p2));})
>
> #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 =
> (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid
> (__p2)])0, \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16
> (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, float16x8_t), p3));})
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> + int
> (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16
> (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
>
> #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid
> (__p2)])0, \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t)), \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t)), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t)), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t)), \
> - int
> (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16
> (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, float16x8_t)));})
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
> + int
> (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16
> (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
>
> #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1)
> __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid
> (__p2)])0, \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16
> (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, float16x8_t), p3));})
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> + int
> (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16
> (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
>
> #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1
> = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid
> (__p2)])0, \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t)), \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t)), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t)), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t)), \
> - int
> (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16
> (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, float16x8_t)));})
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
> + int
> (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16
> (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
>
> #define __arm_vstrwq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_p_s32 (__ARM_mve_coerce(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_p_u32 (__ARM_mve_coerce(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vstrwq_p_f32 (__ARM_mve_coerce(p0, float32_t *),
> __ARM_mve_coerce(__p1, float32x4_t), p2));})
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vstrwq_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *),
> __ARM_mve_coerce(__p1, float32x4_t), p2));})
>
> #define __arm_vstrwq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_s32 (__ARM_mve_coerce(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_u32 (__ARM_mve_coerce(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vstrwq_f32 (__ARM_mve_coerce(p0, float32_t *),
> __ARM_mve_coerce(__p1, float32x4_t)));})
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vstrwq_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *),
> __ARM_mve_coerce(__p1, float32x4_t)));})
>
> #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid
> (__p2)])0, \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t)), \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t)), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t)), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t)), \
> - int
> (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16
> (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, float16x8_t)));})
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
> + int
> (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16
> (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
>
> #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 =
> (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid
> (__p2)])0, \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16
> (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, float16x8_t), p3));})
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> + int
> (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16
> (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
>
> #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1
> = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid
> (__p2)])0, \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t)), \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t)), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t)), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t)), \
> - int
> (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16
> (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, float16x8_t)));})
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
> + int
> (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16
> (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
>
> #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1)
> __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid
> (__p2)])0, \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16
> (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, float16x8_t), p3));})
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> + int
> (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16
> (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
>
> #define __arm_vstrwq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
> @@ -37820,44 +37868,44 @@ extern void *__ARM_undef;
> #define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0);
> \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0,
> \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), p1,
> __ARM_mve_coerce(__p2, int32x4_t)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *),
> p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
> - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce(__p0, float32_t *),
> p1, __ARM_mve_coerce(__p2, float32x4_t)));})
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0,
> int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0,
> uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
> + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce_f32_ptr(__p0,
> float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t)));})
>
> #define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 =
> (p0); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0,
> \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *),
> p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *),
> p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce(__p0, float32_t *),
> p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce_s32_ptr(__p0,
> int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce_u32_ptr(__p0,
> uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce_f32_ptr(__p0,
> float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
>
> #define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1
> = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t
> *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t
> *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
> - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce(p0, float32_t
> *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));})
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0,
> int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0,
> uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
> + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0,
> float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));})
>
> #define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1)
> __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t
> *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0,
> uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce(p0,
> float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_p_s32
> (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2,
> int32x4_t), p3), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_p_u32
> (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1,
> __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_p_f32
> (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1,
> __ARM_mve_coerce(__p2, float32x4_t), p3));})
>
> #define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1)
> __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t
> *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0,
> uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce(p0,
> float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_p_s32
> (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2,
> int32x4_t), p3), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_p_u32
> (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1,
> __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_p_f32
> (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1,
> __ARM_mve_coerce(__p2, float32x4_t), p3));})
>
> #define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1
> = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t
> *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t
> *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
> - int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce(p0, float32_t
> *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));})
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0,
> int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0,
> uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
> + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0,
> float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));})
>
> #define __arm_vuninitializedq(p0) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> @@ -38030,19 +38078,19 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce(__p2, int8x16_t), p3), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t), p3), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce3(p2, int), p3), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce(__p2, uint8x16_t), p3), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce3(p2, int), p3), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]:
> __arm_vaddq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce(__p2, float16x8_t), p3), \
> int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]:
> __arm_vaddq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce(__p2, float32x4_t), p3), \
> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vaddq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce2(p2, double), p3), \
> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vaddq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce2(p2, double), p3));})
> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vaddq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p2, double), p3), \
> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vaddq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p2, double), p3));})
>
> #define __arm_vandq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> @@ -38165,19 +38213,19 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce(__p2, int8x16_t), p3), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t), p3), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce3(p2, int), p3), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce(__p2, uint8x16_t), p3), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce3(p2, int), p3), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]:
> __arm_vmulq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce(__p2, float16x8_t), p3), \
> int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]:
> __arm_vmulq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce(__p2, float32x4_t), p3), \
> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vmulq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce2(p2, double), p3), \
> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vmulq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce2(p2, double), p3));})
> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vmulq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p2, double), p3), \
> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vmulq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p2, double), p3));})
>
> #define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
> @@ -38266,19 +38314,19 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce(__p2, int8x16_t), p3), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t), p3), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce3(p2, int), p3), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vsubq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce(__p2, uint8x16_t), p3), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vsubq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vsubq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce3(p2, int), p3), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]:
> __arm_vsubq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce(__p2, float16x8_t), p3), \
> int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]:
> __arm_vsubq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce(__p2, float32x4_t), p3), \
> - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce2(p2, double), p3), \
> - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vsubq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce2(p2, double), p3));})
> + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]:
> __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t),
> __ARM_mve_coerce_f_scalar(__p2, double), p3), \
> + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]:
> __arm_vsubq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t),
> __ARM_mve_coerce_f_scalar(__p2, double), p3));})
>
> #define __arm_vcmulq_rot90_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> @@ -38302,16 +38350,16 @@ extern void *__ARM_undef;
> #define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]:
> __arm_vsetq_lane_s8 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]:
> __arm_vsetq_lane_s16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]:
> __arm_vsetq_lane_s32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]:
> __arm_vsetq_lane_s64 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int64x2_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]:
> __arm_vsetq_lane_u8 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]:
> __arm_vsetq_lane_u16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]:
> __arm_vsetq_lane_u32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]:
> __arm_vsetq_lane_u64 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint64x2_t), p2), \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vsetq_lane_f16 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float16x8_t), p2), \
> - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vsetq_lane_f32 (__ARM_mve_coerce2(p0, double),
> __ARM_mve_coerce(__p1, float32x4_t), p2));})
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]:
> __arm_vsetq_lane_s8 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]:
> __arm_vsetq_lane_s16 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]:
> __arm_vsetq_lane_s32 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]:
> __arm_vsetq_lane_s64 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, int64x2_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]:
> __arm_vsetq_lane_u8 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]:
> __arm_vsetq_lane_u16 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]:
> __arm_vsetq_lane_u32 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]:
> __arm_vsetq_lane_u64 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, uint64x2_t), p2), \
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]:
> __arm_vsetq_lane_f16 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float16x8_t), p2), \
> + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]:
> __arm_vsetq_lane_f32 (__ARM_mve_coerce_f_scalar(__p0, double),
> __ARM_mve_coerce(__p1, float32x4_t), p2));})
>
> #else /* MVE Integer. */
>
> @@ -38327,12 +38375,12 @@ extern void *__ARM_undef;
>
> #define __arm_vst4q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]:
> __arm_vst4q_s8 (__ARM_mve_coerce(p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16x4_t)), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]:
> __arm_vst4q_s16 (__ARM_mve_coerce(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8x4_t)), \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]:
> __arm_vst4q_s32 (__ARM_mve_coerce(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4x4_t)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]:
> __arm_vst4q_u8 (__ARM_mve_coerce(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16x4_t)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]:
> __arm_vst4q_u16 (__ARM_mve_coerce(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8x4_t)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]:
> __arm_vst4q_u32 (__ARM_mve_coerce(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4x4_t)));})
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]:
> __arm_vst4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16x4_t)), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]:
> __arm_vst4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8x4_t)), \
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]:
> __arm_vst4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4x4_t)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]:
> __arm_vst4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16x4_t)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]:
> __arm_vst4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8x4_t)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]:
> __arm_vst4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4x4_t)));})
>
> #define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> @@ -38429,12 +38477,12 @@ extern void *__ARM_undef;
> #define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -38461,12 +38509,12 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)));})
>
> #define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> @@ -38480,12 +38528,12 @@ extern void *__ARM_undef;
> #define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -38516,12 +38564,12 @@ extern void *__ARM_undef;
> #define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -38590,12 +38638,12 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)));})
>
> #define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -38603,16 +38651,16 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)));})
>
> #define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)));})
> @@ -38620,12 +38668,12 @@ extern void *__ARM_undef;
> #define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -38642,10 +38690,10 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)));})
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)));})
>
> #define __arm_vornq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -38660,12 +38708,12 @@ extern void *__ARM_undef;
> #define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -38740,12 +38788,12 @@ extern void *__ARM_undef;
> #define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -38770,12 +38818,12 @@ extern void *__ARM_undef;
> #define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -38825,10 +38873,10 @@ extern void *__ARM_undef;
> #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3 (p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3 (p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3 (p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3 (p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar (__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar (__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar (__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar (__p1, int)), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> @@ -38845,12 +38893,12 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)));})
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)));})
>
> #define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -38881,12 +38929,12 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vcmpeqq_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vcmpeqq_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vcmpeqq_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)));})
>
> #define __arm_vqmovntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -38967,16 +39015,16 @@ extern void *__ARM_undef;
> #define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)));})
>
> #define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)));})
>
> @@ -38986,9 +39034,9 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)));})
>
> #define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -38996,9 +39044,9 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)));})
>
> #define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -39006,9 +39054,9 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vcmpleq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vcmpleq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)));})
>
> #define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -39016,20 +39064,20 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int)));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)));})
>
> #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vcmpneq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int), p2), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vcmpneq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpneq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> @@ -39054,12 +39102,12 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int), p2));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2));})
>
> #define __arm_vbicq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> @@ -39169,25 +39217,25 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2,
> int)), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int)), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int)));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int)), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int)), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int)));})
>
> #define __arm_vqdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2,
> int)), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int)), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int)));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int)), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int)), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int)));})
>
> #define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int)), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int)));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int)), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int)), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int)));})
>
> #define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -39250,9 +39298,9 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int), p2));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2));})
>
>
> #define __arm_vcmpgtq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> @@ -39261,9 +39309,9 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int), p2));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2));})
>
> #define __arm_vcmpleq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -39271,9 +39319,9 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vcmpleq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vcmpleq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int), p2));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2));})
>
> #define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -39281,9 +39329,9 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vcmpltq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vcmpltq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int), p2));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2));})
>
> #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -39294,12 +39342,12 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vcmpneq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int), p2));})
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2));})
>
> #define __arm_vdupq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -39322,23 +39370,23 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \
> - int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \
> - int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2,
> int)), \
> - int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2,
> int)));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int)), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2,
> int)), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2,
> int)), \
> + int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int)), \
> + int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int)), \
> + int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int)));})
>
> #define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \
> - int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2,
> int)), \
> - int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2,
> int)), \
> - int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2,
> int)));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int)), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2,
> int)), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2,
> int)), \
> + int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int)), \
> + int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int)), \
> + int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int)));})
>
> #define __arm_vnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -39363,9 +39411,9 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int)), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int)));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int)), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int)), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int)));})
>
> #define __arm_vqdmlsdhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -39528,12 +39576,12 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int8x16_t]: __arm_vsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t),
> p3), \
> int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int16x8_t]: __arm_vsubq_m_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t), p3), \
> int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int32x4_t]: __arm_vsubq_m_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t), p3), \
> @@ -39633,12 +39681,12 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_typ
> e_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t),
> p3), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_typ
> e_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t),
> p3), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t),
> p3), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_ty
> pe_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2,
> uint8x16_t), p3), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_ty
> pe_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2,
> uint16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_ty
> pe_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2,
> uint32x4_t), p3));})
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_typ
> e_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2,
> int8x16_t), p3), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_typ
> e_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t), p3), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_ty
> pe_uint8x16_t]: __arm_vmladavaq_p_u8
> (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1,
> uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_ty
> pe_uint16x8_t]: __arm_vmladavaq_p_u16
> (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_ty
> pe_uint32x4_t]: __arm_vmladavaq_p_u32
> (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
>
> #define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -39666,12 +39714,12 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int8x16_t]: __arm_vaddq_m_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2,
> int8x16_t), p3), \
> int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int16x8_t]: __arm_vaddq_m_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t), p3), \
> int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int32x4_t]: __arm_vaddq_m_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t), p3), \
> @@ -39683,12 +39731,12 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int8x16_t]: __arm_vmulq_m_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2,
> int8x16_t), p3), \
> int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int16x8_t]: __arm_vmulq_m_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t), p3), \
> int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int32x4_t]: __arm_vmulq_m_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t), p3), \
> @@ -39703,12 +39751,12 @@ extern void *__ARM_undef;
>
> #define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vldrbq_gather_offset_s8 (__ARM_mve_coerce1(p0, int8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrbq_gather_offset_s16 (__ARM_mve_coerce1(p0, int8_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrbq_gather_offset_s32 (__ARM_mve_coerce1(p0, int8_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce1(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)));})
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vldrbq_gather_offset_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrbq_gather_offset_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrbq_gather_offset_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t
> *), __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t
> *), __ARM_mve_coerce(__p1, uint32x4_t)));})
>
> #define __arm_vstrwq_scatter_base_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 =
> (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
> @@ -39717,144 +39765,144 @@ extern void *__ARM_undef;
>
> #define __arm_vld1q(p0) (\
> _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8
> (__ARM_mve_coerce1(p0, int8_t *)), \
> - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16
> (__ARM_mve_coerce1(p0, int16_t *)), \
> - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32
> (__ARM_mve_coerce1(p0, int32_t *)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8
> (__ARM_mve_coerce1(p0, uint8_t *)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16
> (__ARM_mve_coerce1(p0, uint16_t *)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32
> (__ARM_mve_coerce1(p0, uint32_t *))))
> + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8
> (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
> + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
> + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32
> (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8
> (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32
> (__ARM_mve_coerce_u32_ptr(p0, uint32_t *))))
>
> #define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce1(p0, int16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce1(p0, int16_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)));})
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t
> *), __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t
> *), __ARM_mve_coerce(__p1, uint32x4_t)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t
> *), __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t
> *), __ARM_mve_coerce(__p1, uint32x4_t)));})
>
> #define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 =
> (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2));})
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t
> *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t
> *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0,
> uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0,
> uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
>
> #define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p1) __p1 =
> (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce1(p0, int16_t
> *), __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int16_t
> *), __ARM_mve_coerce(__p1, uint32x4_t)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce1(p0, uint16_t
> *), __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint16_t
> *), __ARM_mve_coerce(__p1, uint32x4_t)));})
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0,
> int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0,
> int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0,
> uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0,
> uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
>
> #define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p1)
> __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce1(p0,
> int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0,
> int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce1(p0,
> uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0,
> uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_z_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_shifted_offset_z_s32
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), p2), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrhq_gather_shifted_offset_z_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrhq_gather_shifted_offset_z_u32
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), p2));})
>
> #define __arm_vldrwq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32
> (__ARM_mve_coerce1(__p0, int32_t *), p1), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32
> (__ARM_mve_coerce1(__p0, uint32_t *), p1));})
> + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32
> (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32
> (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
>
> #define __arm_vldrwq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 =
> (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32
> (__ARM_mve_coerce1(__p0, int32_t *), p1, p2), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]:
> __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce1(__p0, uint32_t *),
> p1, p2));})
> + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32
> (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, p2), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]:
> __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce_u32_ptr(__p0,
> uint32_t *), p1, p2));})
>
> #define __arm_vldrwq_gather_shifted_offset(p0,p1) ({ __typeof(p0) __p0 =
> (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce1(__p0,
> int32_t *), p1), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce1(__p0,
> uint32_t *), p1));})
> + int (*)[__ARM_mve_type_int32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_s32
> (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_u32
> (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
>
> #define __arm_vldrwq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p0)
> __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(__p0,
> int32_t *), p1, p2), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(__p0,
> uint32_t *), p1, p2));})
> + int (*)[__ARM_mve_type_int32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_z_s32
> (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, p2), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]:
> __arm_vldrwq_gather_shifted_offset_z_u32
> (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
>
> #define __arm_vst1q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]:
> __arm_vst1q_s8 (__ARM_mve_coerce(p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vst1q_s16 (__ARM_mve_coerce(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vst1q_s32 (__ARM_mve_coerce(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vst1q_u8 (__ARM_mve_coerce(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vst1q_u16 (__ARM_mve_coerce(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vst1q_u32 (__ARM_mve_coerce(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)));})
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]:
> __arm_vst1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vst1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vst1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vst1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vst1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vst1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)));})
>
> #define __arm_vst1q_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]:
> __arm_vst1q_p_s8 (__ARM_mve_coerce(p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vst1q_p_s16 (__ARM_mve_coerce(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vst1q_p_s32 (__ARM_mve_coerce(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vst1q_p_u8 (__ARM_mve_coerce(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vst1q_p_u16 (__ARM_mve_coerce(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vst1q_p_u32 (__ARM_mve_coerce(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2));})
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]:
> __arm_vst1q_p_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vst1q_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vst1q_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vst1q_p_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vst1q_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vst1q_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2));})
>
> #define __arm_vst2q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]:
> __arm_vst2q_s8 (__ARM_mve_coerce(p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16x2_t)), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]:
> __arm_vst2q_s16 (__ARM_mve_coerce(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8x2_t)), \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]:
> __arm_vst2q_s32 (__ARM_mve_coerce(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4x2_t)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]:
> __arm_vst2q_u8 (__ARM_mve_coerce(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16x2_t)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]:
> __arm_vst2q_u16 (__ARM_mve_coerce(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8x2_t)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]:
> __arm_vst2q_u32 (__ARM_mve_coerce(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4x2_t)));})
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]:
> __arm_vst2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16x2_t)), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]:
> __arm_vst2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8x2_t)), \
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]:
> __arm_vst2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4x2_t)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]:
> __arm_vst2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16x2_t)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]:
> __arm_vst2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8x2_t)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]:
> __arm_vst2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4x2_t)));})
>
> #define __arm_vstrhq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vstrhq_s16 (__ARM_mve_coerce(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrhq_s32 (__ARM_mve_coerce(p0, int16_t *),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vstrhq_u16 (__ARM_mve_coerce(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrhq_u32 (__ARM_mve_coerce(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)));})
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vstrhq_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrhq_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vstrhq_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrhq_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)));})
>
> #define __arm_vstrhq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vstrhq_p_s16 (__ARM_mve_coerce(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> - int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrhq_p_s32 (__ARM_mve_coerce(p0, int16_t *),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vstrhq_p_u16 (__ARM_mve_coerce(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> - int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrhq_p_u32 (__ARM_mve_coerce(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2));})
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vstrhq_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrhq_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vstrhq_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrhq_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2));})
>
> #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 =
> (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid
> (__p2)])0, \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3));})
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
>
> #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid
> (__p2)])0, \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t)), \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t)), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t)), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t)));})
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
>
> #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1)
> __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid
> (__p2)])0, \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3));})
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
>
> #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1
> = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid
> (__p2)])0, \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t)), \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t)), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t)), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t)));})
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
>
>
> #define __arm_vstrwq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_s32 (__ARM_mve_coerce(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_u32 (__ARM_mve_coerce(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)));})
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)));})
>
> #define __arm_vstrwq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_p_s32 (__ARM_mve_coerce(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_p_u32 (__ARM_mve_coerce(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2));})
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2));})
>
> #define __arm_vstrdq_scatter_base_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 =
> (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
> @@ -39869,58 +39917,58 @@ extern void *__ARM_undef;
> #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid
> (__p2)])0, \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t)), \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t)), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t)), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t)));})
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
>
> #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 =
> (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid
> (__p2)])0, \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3));})
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
>
> #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1
> = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid
> (__p2)])0, \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t)), \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t)), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t)), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t)));})
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
>
> #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1)
> __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid
> (__p2)])0, \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32
> (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32
> (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3));})
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
>
> #define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0);
> \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0,
> \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), p1,
> __ARM_mve_coerce(__p2, int32x4_t)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *),
> p1, __ARM_mve_coerce(__p2, uint32x4_t)));})
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0,
> int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0,
> uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)));})
>
> #define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 =
> (p0); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0,
> \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *),
> p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *),
> p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce_s32_ptr(__p0,
> int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce_u32_ptr(__p0,
> uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
>
> #define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1
> = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t
> *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t
> *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)));})
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0,
> int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0,
> uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)));})
>
> #define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1)
> __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t
> *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0,
> uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_p_s32
> (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2,
> int32x4_t), p3), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_shifted_offset_p_u32
> (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1,
> __ARM_mve_coerce(__p2, uint32x4_t), p3));})
>
> #define __arm_vuninitializedq(p0) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> @@ -40025,15 +40073,15 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce(__p2, int8x16_t), p3), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t), p3), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce3(p2, int), p3), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce(__p2, uint8x16_t), p3), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce3(p2, int), p3));})
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3));})
>
> #define __arm_vcaddq_rot270_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> @@ -40127,15 +40175,15 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce(__p2, int8x16_t), p3), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t), p3), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce3(p2, int), p3), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce(__p2, uint8x16_t), p3), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce3(p2, int), p3));})
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3));})
>
> #define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
> @@ -40219,29 +40267,29 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_x_n_u32
> (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3));})
>
> #define __arm_vld1q_z(p0,p1) ( _Generic( (int
> (*)[__ARM_mve_typeid(p0)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8
> (__ARM_mve_coerce1(p0, int8_t *), p1), \
> - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16
> (__ARM_mve_coerce1(p0, int16_t *), p1), \
> - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32
> (__ARM_mve_coerce1(p0, int32_t *), p1), \
> - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8
> (__ARM_mve_coerce1(p0, uint8_t *), p1), \
> - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16
> (__ARM_mve_coerce1(p0, uint16_t *), p1), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32
> (__ARM_mve_coerce1(p0, uint32_t *), p1)))
> + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8
> (__ARM_mve_coerce_s8_ptr(p0, int8_t *), p1), \
> + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *), p1), \
> + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32
> (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \
> + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8
> (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), p1), \
> + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), p1), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32
> (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1)))
>
> #define __arm_vld2q(p0) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8
> (__ARM_mve_coerce1(p0, int8_t *)), \
> - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16
> (__ARM_mve_coerce1(p0, int16_t *)), \
> - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32
> (__ARM_mve_coerce1(p0, int32_t *)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8
> (__ARM_mve_coerce1(p0, uint8_t *)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16
> (__ARM_mve_coerce1(p0, uint16_t *)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32
> (__ARM_mve_coerce1(p0, uint32_t *))))
> + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8
> (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
> + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
> + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32
> (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8
> (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32
> (__ARM_mve_coerce_u32_ptr(p0, uint32_t *))))
>
>
> #define __arm_vld4q(p0) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8
> (__ARM_mve_coerce1(p0, int8_t *)), \
> - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16
> (__ARM_mve_coerce1(p0, int16_t *)), \
> - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32
> (__ARM_mve_coerce1(p0, int32_t *)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8
> (__ARM_mve_coerce1(p0, uint8_t *)), \
> - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16
> (__ARM_mve_coerce1(p0, uint16_t *)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32
> (__ARM_mve_coerce1(p0, uint32_t *))))
> + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8
> (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
> + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16
> (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
> + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32
> (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8
> (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
> + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16
> (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32
> (__ARM_mve_coerce_u32_ptr(p0, uint32_t *))))
>
> #define __arm_vsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> @@ -40249,15 +40297,15 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce(__p2, int8x16_t), p3), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t), p3), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce3(p2, int), p3), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vsubq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce(__p2, uint8x16_t), p3), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vsubq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vsubq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce3(p2, int), p3));})
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3));})
>
> #define __arm_vgetq_lane(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> @@ -40273,14 +40321,14 @@ extern void *__ARM_undef;
> #define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]:
> __arm_vsetq_lane_s8 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]:
> __arm_vsetq_lane_s16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]:
> __arm_vsetq_lane_s32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]:
> __arm_vsetq_lane_s64 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int64x2_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]:
> __arm_vsetq_lane_u8 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]:
> __arm_vsetq_lane_u16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]:
> __arm_vsetq_lane_u32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]:
> __arm_vsetq_lane_u64 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint64x2_t), p2));})
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]:
> __arm_vsetq_lane_s8 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]:
> __arm_vsetq_lane_s16 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]:
> __arm_vsetq_lane_s32 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]:
> __arm_vsetq_lane_s64 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, int64x2_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]:
> __arm_vsetq_lane_u8 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]:
> __arm_vsetq_lane_u16 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]:
> __arm_vsetq_lane_u32 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]:
> __arm_vsetq_lane_u64 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, uint64x2_t), p2));})
>
> #endif /* MVE Integer. */
>
> @@ -40391,62 +40439,62 @@ extern void *__ARM_undef;
> #define __arm_vdwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
> int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u8 ((uint32_t)
> __p1, p2, p3, p4), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u8
> (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u8
> (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
>
> #define __arm_vdwdupq_x_u16(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
> int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u16 ((uint32_t)
> __p1, p2, p3, p4), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u16
> (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u16
> (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
>
> #define __arm_vdwdupq_x_u32(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
> int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u32 ((uint32_t)
> __p1, p2, p3, p4), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u32
> (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u32
> (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
>
> #define __arm_viwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
> int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u8 ((uint32_t) __p1,
> p2, p3, p4), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u8
> (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u8
> (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
>
> #define __arm_viwdupq_x_u16(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
> int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u16 ((uint32_t)
> __p1, p2, p3, p4), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u16
> (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u16
> (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
>
> #define __arm_viwdupq_x_u32(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
> int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u32 ((uint32_t)
> __p1, p2, p3, p4), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u32
> (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u32
> (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
>
> #define __arm_vidupq_x_u8(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
> int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u8 ((uint32_t) __p1,
> p2, p3), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u8
> (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u8
> (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
>
> #define __arm_vddupq_x_u8(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
> int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u8 ((uint32_t) __p1,
> p2, p3), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u8
> (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u8
> (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
>
> #define __arm_vidupq_x_u16(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
> int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u16 ((uint32_t) __p1,
> p2, p3), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u16
> (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u16
> (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
>
> #define __arm_vddupq_x_u16(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
> int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u16 ((uint32_t) __p1,
> p2, p3), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u16
> (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u16
> (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
>
> #define __arm_vidupq_x_u32(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
> int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u32 ((uint32_t) __p1,
> p2, p3), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u32
> (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u32
> (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
>
> #define __arm_vddupq_x_u32(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
> int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u32 ((uint32_t) __p1,
> p2, p3), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u32
> (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u32
> (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
>
> #define __arm_vshrq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
> @@ -40460,12 +40508,12 @@ extern void *__ARM_undef;
> #define __arm_vhaddq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_x_n_u8( __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_x_n_u16( __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_x_n_u32( __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce3(p2, int), p3), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_x_n_u8( __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_x_n_u16( __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vhaddq_x_n_u32( __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vhaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce(__p2, int8x16_t), p3), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vhaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t), p3), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vhaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t), p3), \
> @@ -40490,12 +40538,12 @@ extern void *__ARM_undef;
> #define __arm_vhsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0,
> \
> - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce3(p2, int), p3), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce3(p2, int), p3), \
> + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vhsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]:
> __arm_vhsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce(__p2, int8x16_t), p3), \
> int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]:
> __arm_vhsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t), p3), \
> int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]:
> __arm_vhsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t), p3), \
> @@ -40535,20 +40583,20 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_base_wb_u64
> (p0, p1, __ARM_mve_coerce(__p2, uint64x2_t)));})
>
> #define __arm_vldrdq_gather_offset(p0,p1) ( _Generic( (int
> (*)[__ARM_mve_typeid(p0)])0, \
> - int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_s64
> (__ARM_mve_coerce1(p0, int64_t *), p1), \
> - int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_u64
> (__ARM_mve_coerce1(p0, uint64_t *), p1)))
> + int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_s64
> (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1), \
> + int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_u64
> (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1)))
>
> #define __arm_vldrdq_gather_offset_z(p0,p1,p2) ( _Generic( (int
> (*)[__ARM_mve_typeid(p0)])0, \
> - int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_z_s64
> (__ARM_mve_coerce1(p0, int64_t *), p1, p2), \
> - int (*)[__ARM_mve_type_uint64_t_ptr]:
> __arm_vldrdq_gather_offset_z_u64 (__ARM_mve_coerce1(p0, uint64_t *),
> p1, p2)))
> + int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_z_s64
> (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1, p2), \
> + int (*)[__ARM_mve_type_uint64_t_ptr]:
> __arm_vldrdq_gather_offset_z_u64 (__ARM_mve_coerce_u64_ptr(p0,
> uint64_t *), p1, p2)))
>
> #define __arm_vldrdq_gather_shifted_offset(p0,p1) ( _Generic( (int
> (*)[__ARM_mve_typeid(p0)])0, \
> - int (*)[__ARM_mve_type_int64_t_ptr]:
> __arm_vldrdq_gather_shifted_offset_s64 (__ARM_mve_coerce1(p0, int64_t
> *), p1), \
> - int (*)[__ARM_mve_type_uint64_t_ptr]:
> __arm_vldrdq_gather_shifted_offset_u64 (__ARM_mve_coerce1(p0, uint64_t
> *), p1)))
> + int (*)[__ARM_mve_type_int64_t_ptr]:
> __arm_vldrdq_gather_shifted_offset_s64 (__ARM_mve_coerce_s64_ptr(p0,
> int64_t *), p1), \
> + int (*)[__ARM_mve_type_uint64_t_ptr]:
> __arm_vldrdq_gather_shifted_offset_u64 (__ARM_mve_coerce_u64_ptr(p0,
> uint64_t *), p1)))
>
> #define __arm_vldrdq_gather_shifted_offset_z(p0,p1,p2) ( _Generic( (int
> (*)[__ARM_mve_typeid(p0)])0, \
> - int (*)[__ARM_mve_type_int64_t_ptr]:
> __arm_vldrdq_gather_shifted_offset_z_s64 (__ARM_mve_coerce1(p0,
> int64_t *), p1, p2), \
> - int (*)[__ARM_mve_type_uint64_t_ptr]:
> __arm_vldrdq_gather_shifted_offset_z_u64 (__ARM_mve_coerce1(p0,
> uint64_t *), p1, p2)))
> + int (*)[__ARM_mve_type_int64_t_ptr]:
> __arm_vldrdq_gather_shifted_offset_z_s64
> (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1, p2), \
> + int (*)[__ARM_mve_type_uint64_t_ptr]:
> __arm_vldrdq_gather_shifted_offset_z_u64
> (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1, p2)))
>
> #define __arm_vadciq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -40604,36 +40652,36 @@ extern void *__ARM_undef;
>
> #define __arm_vldrbq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 =
> (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vldrbq_gather_offset_z_s8 (__ARM_mve_coerce1(p0, int8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrbq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int8_t *),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrbq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int8_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vldrbq_gather_offset_z_u8 (__ARM_mve_coerce1(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2));})
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vldrbq_gather_offset_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrbq_gather_offset_z_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t
> *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrbq_gather_offset_z_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t
> *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vldrbq_gather_offset_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t
> *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t
> *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t
> *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
>
> #define __arm_vqrdmlahq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlahq_m_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlahq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlahq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int), p3));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlahq_m_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlahq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlahq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3));})
>
> #define __arm_vqrdmlashq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlashq_m_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlashq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlashq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int), p3));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlashq_m_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlashq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqrdmlashq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3));})
>
> #define __arm_vqdmlashq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqdmlashq_m_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqdmlashq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqdmlashq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int), p3));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqdmlashq_m_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqdmlashq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqdmlashq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3));})
>
> #define __arm_vqrshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -40734,12 +40782,12 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqsubq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqsubq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vqsubq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vqsubq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vqsubq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqsubq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqsubq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vqsubq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vqsubq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vqsubq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int8x16_t]: __arm_vqsubq_m_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2,
> int8x16_t), p3), \
> int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int16x8_t]: __arm_vqsubq_m_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t), p3), \
> int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int32x4_t]: __arm_vqsubq_m_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t), p3), \
> @@ -40754,9 +40802,9 @@ extern void *__ARM_undef;
> int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int8x16_t]: __arm_vqrdmulhq_m_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2,
> int8x16_t), p3), \
> int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int16x8_t]: __arm_vqrdmulhq_m_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t), p3), \
> int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int32x4_t]: __arm_vqrdmulhq_m_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqrdmulhq_m_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int), p3));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqrdmulhq_m_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3));})
>
> #define __arm_vqrdmlsdhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -40882,17 +40930,17 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_typ
> e_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t),
> p3), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t),
> p3), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_ty
> pe_uint16x8_t]: __arm_vmlaldavaq_p_u16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2,
> uint16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_ty
> pe_uint32x4_t]: __arm_vmlaldavaq_p_u32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2,
> uint32x4_t), p3));})
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_typ
> e_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t), p3), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_ty
> pe_uint16x8_t]: __arm_vmlaldavaq_p_u16
> (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_ty
> pe_uint32x4_t]: __arm_vmlaldavaq_p_u32
> (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
>
> #define __arm_vmlaldavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_typ
> e_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t),
> p3), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t),
> p3));})
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_typ
> e_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t), p3));})
>
> #define __arm_vmlsldavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -40962,10 +41010,10 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vmvnq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vmvnq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vmvnq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce3(p1, int) , p2), \
> - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce3(p1, int) , p2), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int) , p2), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int) , p2));})
> + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]:
> __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int) , p2), \
> + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]:
> __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int) , p2), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int) , p2), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int) , p2));})
>
> #define __arm_vorrq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> @@ -41031,12 +41079,12 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int8x16_t]: __arm_vhaddq_m_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2,
> int8x16_t), p3), \
> int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int16x8_t]: __arm_vhaddq_m_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t), p3), \
> int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int32x4_t]: __arm_vhaddq_m_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t), p3), \
> @@ -41070,12 +41118,12 @@ extern void *__ARM_undef;
> int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_uint8x16_t]: __arm_vhsubq_m_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce(__p2, uint8x16_t), p3), \
> int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_uint16x8_t]: __arm_vhsubq_m_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_uint32x4_t]: __arm_vhsubq_m_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vhsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vhsubq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vhsubq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vhsubq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vhsubq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vhsubq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2,
> int), p3));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vhsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vhsubq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vhsubq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vhsubq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vhsubq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vhsubq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3));})
>
> #define __arm_vmaxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -41103,23 +41151,23 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vmlaq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vmlaq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vmlaq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vmlaq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vmlaq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vmlaq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2,
> int), p3));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vmlaq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vmlaq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vmlaq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vmlaq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vmlaq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vmlaq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3));})
>
> #define __arm_vmlasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vmlasq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vmlasq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vmlasq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vmlasq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vmlasq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vmlasq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2,
> int), p3));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vmlasq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vmlasq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vmlasq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vmlasq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vmlasq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vmlasq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3));})
>
> #define __arm_vmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -41165,12 +41213,12 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqaddq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqaddq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vqaddq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vqaddq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vqaddq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqaddq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqaddq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_int_n]: __arm_vqaddq_m_n_u8 (__ARM_mve_coerce(__p0,
> uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_int_n]: __arm_vqaddq_m_n_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_int_n]: __arm_vqaddq_m_n_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int8x16_t]: __arm_vqaddq_m_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2,
> int8x16_t), p3), \
> int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int16x8_t]: __arm_vqaddq_m_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t), p3), \
> int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int32x4_t]: __arm_vqaddq_m_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t), p3), \
> @@ -41182,17 +41230,17 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqdmlahq_m_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqdmlahq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqdmlahq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int), p3));})
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqdmlahq_m_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqdmlahq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqdmlahq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3));})
>
> #define __arm_vqdmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqdmulhq_m_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqdmulhq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqdmulhq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int_n]: __arm_vqdmulhq_m_n_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqdmulhq_m_n_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqdmulhq_m_n_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int
> (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve
> _type_int8x16_t]: __arm_vqdmulhq_m_s8 (__ARM_mve_coerce(__p0,
> int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2,
> int8x16_t), p3), \
> int
> (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int16x8_t]: __arm_vqdmulhq_m_s16 (__ARM_mve_coerce(__p0,
> int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t), p3), \
> int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int32x4_t]: __arm_vqdmulhq_m_s32 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t), p3));})
> @@ -41203,15 +41251,15 @@ extern void *__ARM_undef;
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int16x8_t]: __arm_vqdmullbq_m_s16 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t), p3), \
> int
> (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int32x4_t]: __arm_vqdmullbq_m_s32 (__ARM_mve_coerce(__p0,
> int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqdmullbq_m_n_s16 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqdmullbq_m_n_s32 (__ARM_mve_coerce(__p0,
> int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int), p3));})
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqdmullbq_m_n_s16 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqdmullbq_m_n_s32 (__ARM_mve_coerce(__p0,
> int64x2_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3));})
>
> #define __arm_vqdmulltq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqdmulltq_m_n_s16 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2,
> int), p3), \
> - int
> (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqdmulltq_m_n_s32 (__ARM_mve_coerce(__p0,
> int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2,
> int), p3), \
> + int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int_n]: __arm_vqdmulltq_m_n_s16 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int16x8_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> + int
> (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int_n]: __arm_vqdmulltq_m_n_s32 (__ARM_mve_coerce(__p0,
> int64x2_t), __ARM_mve_coerce(__p1, int32x4_t),
> __ARM_mve_coerce_i_scalar(__p2, int), p3), \
> int
> (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve
> _type_int16x8_t]: __arm_vqdmulltq_m_s16 (__ARM_mve_coerce(__p0,
> int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t), p3), \
> int
> (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve
> _type_int32x4_t]: __arm_vqdmulltq_m_s32 (__ARM_mve_coerce(__p0,
> int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t), p3));})
>
> @@ -41277,9 +41325,9 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_typ
> e_int8x16_t]: __arm_vmladavaxq_p_s8 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t),
> p3), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_typ
> e_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t),
> p3), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t),
> p3));})
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_typ
> e_int8x16_t]: __arm_vmladavaxq_p_s8 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2,
> int8x16_t), p3), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_typ
> e_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t), p3));})
>
> #define __arm_vmullbq_poly_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -41290,12 +41338,12 @@ extern void *__ARM_undef;
>
> #define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vldrbq_gather_offset_s8(__ARM_mve_coerce1(p0, int8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrbq_gather_offset_s16(__ARM_mve_coerce1(p0, int8_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrbq_gather_offset_s32(__ARM_mve_coerce1(p0, int8_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vldrbq_gather_offset_u8(__ARM_mve_coerce1(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrbq_gather_offset_u16(__ARM_mve_coerce1(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrbq_gather_offset_u32(__ARM_mve_coerce1(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)));})
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vldrbq_gather_offset_s8(__ARM_mve_coerce_s8_ptr(p0, int8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrbq_gather_offset_s16(__ARM_mve_coerce_s8_ptr(p0, int8_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrbq_gather_offset_s32(__ARM_mve_coerce_s8_ptr(p0, int8_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vldrbq_gather_offset_u8(__ARM_mve_coerce_u8_ptr(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vldrbq_gather_offset_u16(__ARM_mve_coerce_u8_ptr(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vldrbq_gather_offset_u32(__ARM_mve_coerce_u8_ptr(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)));})
>
> #define __arm_vidupq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -41303,9 +41351,9 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vidupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), (uint32_t)
> __p1, p2, p3), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vidupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), (uint32_t)
> __p1, p2, p3), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vidupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), (uint32_t)
> __p1, p2, p3), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_vidupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_vidupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_vidupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_vidupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_vidupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_vidupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
>
> #define __arm_vddupq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -41313,89 +41361,89 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vddupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), (uint32_t)
> __p1, p2, p3), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vddupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), (uint32_t)
> __p1, p2, p3), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vddupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), (uint32_t)
> __p1, p2, p3), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_vddupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_vddupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_vddupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_vddupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_vddupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_vddupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
>
> #define __arm_vidupq_u16(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u16 ((uint32_t) __p0,
> p1), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u16
> (__ARM_mve_coerce(__p0, uint32_t *), p1));})
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u16
> (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
>
> #define __arm_vidupq_u32(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u32 ((uint32_t) __p0,
> p1), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u32
> (__ARM_mve_coerce(__p0, uint32_t *), p1));})
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u32
> (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
>
> #define __arm_vidupq_u8(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u8 ((uint32_t) __p0, p1),
> \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u8
> (__ARM_mve_coerce(__p0, uint32_t *), p1));})
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u8
> (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
>
> #define __arm_vddupq_u16(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u16 ((uint32_t) __p0,
> p1), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u16
> (__ARM_mve_coerce(__p0, uint32_t *), p1));})
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u16
> (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
>
> #define __arm_vddupq_u32(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u32 ((uint32_t) __p0,
> p1), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u32
> (__ARM_mve_coerce(__p0, uint32_t *), p1));})
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u32
> (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
>
> #define __arm_vddupq_u8(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u8 ((uint32_t) __p0,
> p1), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u8
> (__ARM_mve_coerce(__p0, uint32_t *), p1));})
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u8
> (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
>
> #define __arm_viwdupq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_viwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int), p2, p3, p4), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_viwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int), p2, p3, p4), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_viwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int), p2, p3, p4), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_viwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_viwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_viwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_viwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_viwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_viwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_viwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_viwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_viwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
>
> #define __arm_viwdupq_u16(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> - int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u16
> (__ARM_mve_coerce3(p0, int), p1, (const int) p2), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u16
> (__ARM_mve_coerce(__p0, uint32_t *), p1, (const int) p2));})
> + int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u16
> (__ARM_mve_coerce_i_scalar(__p0, int), p1, (const int) p2), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u16
> (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, (const int) p2));})
>
> #define __arm_viwdupq_u32(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> - int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u32
> (__ARM_mve_coerce3(p0, int), p1, p2), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u32
> (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
> + int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u32
> (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u32
> (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
>
> #define __arm_viwdupq_u8(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> - int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u8
> (__ARM_mve_coerce3(p0, int), p1, p2), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u8
> (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
> + int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u8
> (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u8
> (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
>
> #define __arm_vdwdupq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vdwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int), p2, p3, p4), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vdwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int), p2, p3, p4), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vdwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int), p2, p3, p4), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_vdwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_vdwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_vdwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vdwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vdwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vdwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_vdwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_vdwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]:
> __arm_vdwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
>
> #define __arm_vdwdupq_u16(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> - int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u16
> (__ARM_mve_coerce3(p0, int), p1, p2), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u16
> (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
> + int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u16
> (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u16
> (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
>
> #define __arm_vdwdupq_u32(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> - int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u32
> (__ARM_mve_coerce3(p0, int), p1, p2), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u32
> (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
> + int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u32
> (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u32
> (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
>
> #define __arm_vdwdupq_u8(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> - int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u8
> (__ARM_mve_coerce3(p0, int), p1, p2), \
> - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u8
> (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
> + int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u8
> (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
> + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u8
> (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
>
> #define __arm_vshlcq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> @@ -41431,14 +41479,14 @@ extern void *__ARM_undef;
> #define __arm_vaddlvaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]:
> __arm_vaddlvaq_s32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]:
> __arm_vaddlvaq_u32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t)));})
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]:
> __arm_vaddlvaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]:
> __arm_vaddlvaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t)));})
>
> #define __arm_vaddlvaq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]:
> __arm_vaddlvaq_p_s32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]:
> __arm_vaddlvaq_p_u32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t), p2));})
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]:
> __arm_vaddlvaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]:
> __arm_vaddlvaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t), p2));})
>
> #define __arm_vaddlvq(p0) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> @@ -41453,22 +41501,22 @@ extern void *__ARM_undef;
> #define __arm_vaddvaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]:
> __arm_vaddvaq_s8 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]:
> __arm_vaddvaq_s16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]:
> __arm_vaddvaq_s32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]:
> __arm_vaddvaq_u8 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]:
> __arm_vaddvaq_u16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]:
> __arm_vaddvaq_u32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t)));})
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]:
> __arm_vaddvaq_s8 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]:
> __arm_vaddvaq_s16 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]:
> __arm_vaddvaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]:
> __arm_vaddvaq_u8 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]:
> __arm_vaddvaq_u16 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]:
> __arm_vaddvaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t)));})
>
> #define __arm_vaddvaq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]:
> __arm_vaddvaq_p_s8 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]:
> __arm_vaddvaq_p_s16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]:
> __arm_vaddvaq_p_s32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]:
> __arm_vaddvaq_p_u8 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]:
> __arm_vaddvaq_p_u16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]:
> __arm_vaddvaq_p_u32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t), p2));})
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]:
> __arm_vaddvaq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]:
> __arm_vaddvaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]:
> __arm_vaddvaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]:
> __arm_vaddvaq_p_u8 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]:
> __arm_vaddvaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]:
> __arm_vaddvaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t), p2));})
>
> #define __arm_vaddvq(p0) ({ __typeof(p0) __p0 = (p0); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> @@ -41494,9 +41542,9 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vcmpcsq_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vcmpcsq_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vcmpcsq_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpcsq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpcsq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpcsq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)));})
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpcsq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpcsq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpcsq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)));})
>
> #define __arm_vcmpcsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -41504,9 +41552,9 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vcmpcsq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vcmpcsq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vcmpcsq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpcsq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpcsq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpcsq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int), p2));})
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmpcsq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmpcsq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmpcsq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2));})
>
> #define __arm_vcmphiq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -41514,16 +41562,16 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vcmphiq_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vcmphiq_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vcmphiq_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t)), \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmphiq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmphiq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int)), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmphiq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int)));})
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmphiq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmphiq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int)), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmphiq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int)));})
>
> #define __arm_vcmphiq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmphiq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmphiq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce3(p1, int), p2), \
> - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmphiq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce3(p1, int), p2), \
> + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]:
> __arm_vcmphiq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]:
> __arm_vcmphiq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]:
> __arm_vcmphiq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce_i_scalar(__p1, int), p2), \
> int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]:
> __arm_vcmphiq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]:
> __arm_vcmphiq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]:
> __arm_vcmphiq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t),
> __ARM_mve_coerce(__p1, uint32x4_t), p2));})
> @@ -41620,34 +41668,34 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_typ
> e_int8x16_t]: __arm_vmladavaq_s8 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)),
> \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_typ
> e_int16x8_t]: __arm_vmladavaq_s16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)),
> \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vmladavaq_s32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)),
> \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_ty
> pe_uint8x16_t]: __arm_vmladavaq_u8 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2,
> uint8x16_t)), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_ty
> pe_uint16x8_t]: __arm_vmladavaq_u16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2,
> uint16x8_t)), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_ty
> pe_uint32x4_t]: __arm_vmladavaq_u32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2,
> uint32x4_t)));})
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_typ
> e_int8x16_t]: __arm_vmladavaq_s8 (__ARM_mve_coerce_i_scalar(__p0, int),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)),
> \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_typ
> e_int16x8_t]: __arm_vmladavaq_s16 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t)), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vmladavaq_s32 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t)), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_ty
> pe_uint8x16_t]: __arm_vmladavaq_u8 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2,
> uint8x16_t)), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_ty
> pe_uint16x8_t]: __arm_vmladavaq_u16 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2,
> uint16x8_t)), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_ty
> pe_uint32x4_t]: __arm_vmladavaq_u32 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2,
> uint32x4_t)));})
>
> #define __arm_vmladavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_typ
> e_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t),
> p3), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_typ
> e_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t),
> p3), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t),
> p3), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_ty
> pe_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2,
> uint8x16_t), p3), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_ty
> pe_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2,
> uint16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_ty
> pe_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2,
> uint32x4_t), p3));})
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_typ
> e_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2,
> int8x16_t), p3), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_typ
> e_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t), p3), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_ty
> pe_uint8x16_t]: __arm_vmladavaq_p_u8
> (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1,
> uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_ty
> pe_uint16x8_t]: __arm_vmladavaq_p_u16
> (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_ty
> pe_uint32x4_t]: __arm_vmladavaq_p_u32
> (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
>
> #define __arm_vmladavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_typ
> e_int8x16_t]: __arm_vmladavaxq_s8 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)),
> \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_typ
> e_int16x8_t]: __arm_vmladavaxq_s16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)),
> \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vmladavaxq_s32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)),
> \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_ty
> pe_uint8x16_t]: __arm_vmladavaxq_u8 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2,
> uint8x16_t)), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_ty
> pe_uint16x8_t]: __arm_vmladavaxq_u16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2,
> uint16x8_t)), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_ty
> pe_uint32x4_t]: __arm_vmladavaxq_u32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2,
> uint32x4_t)));})
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_typ
> e_int8x16_t]: __arm_vmladavaxq_s8 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2,
> int8x16_t)), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_typ
> e_int16x8_t]: __arm_vmladavaxq_s16 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t)), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vmladavaxq_s32 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t)), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_ty
> pe_uint8x16_t]: __arm_vmladavaxq_u8 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2,
> uint8x16_t)), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_ty
> pe_uint16x8_t]: __arm_vmladavaxq_u16 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2,
> uint16x8_t)), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_ty
> pe_uint32x4_t]: __arm_vmladavaxq_u32 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2,
> uint32x4_t)));})
>
> #define __arm_vmladavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -41690,17 +41738,17 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_typ
> e_int16x8_t]: __arm_vmlaldavaq_s16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)),
> \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vmlaldavaq_s32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)),
> \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_ty
> pe_uint16x8_t]: __arm_vmlaldavaq_u16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2,
> uint16x8_t)), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_ty
> pe_uint32x4_t]: __arm_vmlaldavaq_u32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2,
> uint32x4_t)));})
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_typ
> e_int16x8_t]: __arm_vmlaldavaq_s16 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t)), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vmlaldavaq_s32 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t)), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_ty
> pe_uint16x8_t]: __arm_vmlaldavaq_u16 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2,
> uint16x8_t)), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_ty
> pe_uint32x4_t]: __arm_vmlaldavaq_u32 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2,
> uint32x4_t)));})
>
> #define __arm_vmlaldavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_typ
> e_int16x8_t]: __arm_vmlaldavaxq_s16 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)),
> \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vmlaldavaxq_s32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t)));})
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_typ
> e_int16x8_t]: __arm_vmlaldavaxq_s16 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2,
> int16x8_t)), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vmlaldavaxq_s32 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t)));})
>
> #define __arm_vmlaldavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> @@ -41864,22 +41912,22 @@ extern void *__ARM_undef;
>
> #define __arm_vstrbq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]:
> __arm_vstrbq_s8 (__ARM_mve_coerce(p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vstrbq_s16 (__ARM_mve_coerce(p0, int8_t *),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrbq_s32 (__ARM_mve_coerce(p0, int8_t *),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vstrbq_u8 (__ARM_mve_coerce(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vstrbq_u16 (__ARM_mve_coerce(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrbq_u32 (__ARM_mve_coerce(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)));})
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]:
> __arm_vstrbq_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16_t)), \
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vstrbq_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *),
> __ARM_mve_coerce(__p1, int16x8_t)), \
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrbq_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *),
> __ARM_mve_coerce(__p1, int32x4_t)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vstrbq_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vstrbq_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrbq_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint32x4_t)));})
>
> #define __arm_vstrbq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]:
> __arm_vstrbq_p_s8 (__ARM_mve_coerce(__p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vstrbq_p_s16 (__ARM_mve_coerce(__p0, int8_t *),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> - int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrbq_p_s32 (__ARM_mve_coerce(__p0, int8_t *),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vstrbq_p_u8 (__ARM_mve_coerce(__p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vstrbq_p_u16 (__ARM_mve_coerce(__p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> - int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrbq_p_u32 (__ARM_mve_coerce(__p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2));})
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]:
> __arm_vstrbq_p_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *),
> __ARM_mve_coerce(__p1, int8x16_t), p2), \
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]:
> __arm_vstrbq_p_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *),
> __ARM_mve_coerce(__p1, int16x8_t), p2), \
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrbq_p_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *),
> __ARM_mve_coerce(__p1, int32x4_t), p2), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> __arm_vstrbq_p_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]:
> __arm_vstrbq_p_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrbq_p_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *),
> __ARM_mve_coerce(__p1, uint32x4_t), p2));})
>
> #define __arm_vstrdq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
> @@ -41895,61 +41943,61 @@ extern void *__ARM_undef;
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vrmlaldavhaq_s32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)),
> \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_ty
> pe_uint32x4_t]: __arm_vrmlaldavhaq_u32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2,
> uint32x4_t)));})
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vrmlaldavhaq_s32 (__ARM_mve_coerce_i_scalar(__p0,
> int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2,
> int32x4_t)), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_ty
> pe_uint32x4_t]: __arm_vrmlaldavhaq_u32
> (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
>
> #define __arm_vrmlaldavhaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vrmlaldavhaq_p_s32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t),
> p3), \
> - int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_ty
> pe_uint32x4_t]: __arm_vrmlaldavhaq_p_u32 (__ARM_mve_coerce3(p0, int),
> __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2,
> uint32x4_t), p3));})
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_typ
> e_int32x4_t]: __arm_vrmlaldavhaq_p_s32
> (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1,
> int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
> + int
> (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_ty
> pe_uint32x4_t]: __arm_vrmlaldavhaq_p_u32
> (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
>
> #define __arm_vstrbq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mv
> e_type_int8x16_t]: __arm_vstrbq_scatter_offset_s8
> (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce(__p2, int8x16_t)), \
> - int
> (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mv
> e_type_int16x8_t]: __arm_vstrbq_scatter_offset_s16
> (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t)), \
> - int
> (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mv
> e_type_int32x4_t]: __arm_vstrbq_scatter_offset_s32
> (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t)), \
> - int
> (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_u8
> (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1,
> uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
> - int
> (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_u16
> (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
> - int
> (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_u32
> (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
> + int
> (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mv
> e_type_int8x16_t]: __arm_vstrbq_scatter_offset_s8
> (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1,
> uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
> + int
> (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mv
> e_type_int16x8_t]: __arm_vstrbq_scatter_offset_s16
> (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
> + int
> (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mv
> e_type_int32x4_t]: __arm_vstrbq_scatter_offset_s32
> (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
> + int
> (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_u8
> (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1,
> uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
> + int
> (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_u16
> (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
> + int
> (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_u32
> (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
>
> #define __arm_vstrbq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 =
> (p0); \
> __typeof(p1) __p1 = (p1); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typ
> eid(__p2)])0, \
> - int
> (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mv
> e_type_int8x16_t]: __arm_vstrbq_scatter_offset_p_s8
> (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce(__p2, int8x16_t), p3), \
> - int
> (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mv
> e_type_int16x8_t]: __arm_vstrbq_scatter_offset_p_s16
> (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, int16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mv
> e_type_int32x4_t]: __arm_vstrbq_scatter_offset_p_s32
> (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, int32x4_t), p3), \
> - int
> (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_p_u8
> (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1,
> uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
> - int
> (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_p_u16
> (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> - int
> (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_p_u32
> (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
> + int
> (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mv
> e_type_int8x16_t]: __arm_vstrbq_scatter_offset_p_s8
> (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1,
> uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
> + int
> (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mv
> e_type_int16x8_t]: __arm_vstrbq_scatter_offset_p_s16
> (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mv
> e_type_int32x4_t]: __arm_vstrbq_scatter_offset_p_s32
> (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
> + int
> (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_p_u8
> (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1,
> uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
> + int
> (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_p_u16
> (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> + int
> (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_p_u32
> (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1,
> uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
>
> #define __arm_vstrdq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 =
> (p0); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0,
> \
> - int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]:
> __arm_vstrdq_scatter_offset_p_s64 (__ARM_mve_coerce(__p0, int64_t *),
> p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \
> - int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]:
> __arm_vstrdq_scatter_offset_p_u64 (__ARM_mve_coerce(__p0, uint64_t *),
> p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));})
> + int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]:
> __arm_vstrdq_scatter_offset_p_s64 (__ARM_mve_coerce_s64_ptr(__p0,
> int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \
> + int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]:
> __arm_vstrdq_scatter_offset_p_u64 (__ARM_mve_coerce_u64_ptr(__p0,
> uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));})
>
> #define __arm_vstrdq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0,
> \
> - int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]:
> __arm_vstrdq_scatter_offset_s64 (__ARM_mve_coerce(__p0, int64_t *), p1,
> __ARM_mve_coerce(__p2, int64x2_t)), \
> - int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]:
> __arm_vstrdq_scatter_offset_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1,
> __ARM_mve_coerce(__p2, uint64x2_t)));})
> + int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]:
> __arm_vstrdq_scatter_offset_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t
> *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \
> + int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]:
> __arm_vstrdq_scatter_offset_u64 (__ARM_mve_coerce_u64_ptr(__p0,
> uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));})
>
> #define __arm_vstrdq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p0)
> __p0 = (p0); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0,
> \
> - int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]:
> __arm_vstrdq_scatter_shifted_offset_p_s64 (__ARM_mve_coerce(__p0,
> int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \
> - int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]:
> __arm_vstrdq_scatter_shifted_offset_p_u64 (__ARM_mve_coerce(__p0,
> uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));})
> + int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]:
> __arm_vstrdq_scatter_shifted_offset_p_s64
> (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2,
> int64x2_t), p3), \
> + int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]:
> __arm_vstrdq_scatter_shifted_offset_p_u64
> (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1,
> __ARM_mve_coerce(__p2, uint64x2_t), p3));})
>
> #define __arm_vstrdq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p0) __p0
> = (p0); \
> __typeof(p2) __p2 = (p2); \
> _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0,
> \
> - int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]:
> __arm_vstrdq_scatter_shifted_offset_s64 (__ARM_mve_coerce(__p0, int64_t
> *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \
> - int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]:
> __arm_vstrdq_scatter_shifted_offset_u64 (__ARM_mve_coerce(__p0,
> uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));})
> + int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]:
> __arm_vstrdq_scatter_shifted_offset_s64
> (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2,
> int64x2_t)), \
> + int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]:
> __arm_vstrdq_scatter_shifted_offset_u64
> (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1,
> __ARM_mve_coerce(__p2, uint64x2_t)));})
>
> #endif /* __cplusplus */
> #endif /* __ARM_FEATURE_MVE */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-
> fp.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-
> fp.c
> index a2787a47859..a1e786ecd9f 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-
> fp.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-
> fp.c
> @@ -1,6 +1,7 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long" } */
> +/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -Wno-
> incompatible-pointer-types" { target c } } */
> +/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -fpermissive"
> { target c++ } } */
> #include "arm_mve.h"
>
> float f1;
> @@ -10,35 +11,14 @@ float32_t f4;
> __fp16 f5;
> _Float16 f6;
>
> -int i1;
> -short i2;
> -long i3;
> -long long i4;
> -int8_t i5;
> -int16_t i6;
> -int32_t i7;
> -int64_t i8;
> -
> float16x8_t floatvec;
> -int16x8_t intvec;
>
> -void test(void)
> +/* Test a few different supported ways of passing a scalar int value.
> +The intrinsic vmulq was chosen arbitrarily, but it is representative of
> +all intrinsics that take a non-const scalar value. */
> +void
> +test_scalars (void)
> {
> - /* Test a few different supported ways of passing an int value. The
> - intrinsic vmulq was chosen arbitrarily, but it is representative of
> - all intrinsics that take a non-const scalar value. */
> - intvec = vmulq(intvec, 2);
> - intvec = vmulq(intvec, (int32_t) 2);
> - intvec = vmulq(intvec, (short) 2);
> - intvec = vmulq(intvec, i1);
> - intvec = vmulq(intvec, i2);
> - intvec = vmulq(intvec, i3);
> - intvec = vmulq(intvec, i4);
> - intvec = vmulq(intvec, i5);
> - intvec = vmulq(intvec, i6);
> - intvec = vmulq(intvec, i7);
> - intvec = vmulq(intvec, i8);
> -
> /* Test a few different supported ways of passing a float value. */
> floatvec = vmulq(floatvec, 0.5);
> floatvec = vmulq(floatvec, 0.5f);
> @@ -53,4 +33,25 @@ void test(void)
> floatvec = vmulq(floatvec, (_Float16) 0.15);
> }
>
> +/* Next, test a number of valid pointer overloads. */
> +void
> +foo11 (__fp16 * addr, float16x8_t value)
> +{
> + vst1q (addr, value);
> +}
> +
> +#ifndef __cplusplus
> +void
> +foo12 (_Float16 * addr, float16x8_t value)
> +{
> + vst1q (addr, value);
> +}
> +#endif
> +
> +void
> +foo13 (float * addr, float32x4_t value)
> +{
> + vst1q (addr, value);
> +}
> +
> /* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-
> int.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-
> int.c
> index 7b88f462e17..7947dc024bc 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-
> int.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-
> int.c
> @@ -1,7 +1,7 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long" } */
> -
> +/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -Wno-
> incompatible-pointer-types" { target c } } */
> +/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -fpermissive"
> { target c++ } } */
> #include "arm_mve.h"
>
> int i1;
> @@ -15,11 +15,12 @@ int64_t i8;
>
> int16x8_t intvec;
>
> -void test(void)
> +/* Test a few different supported ways of passing a scalar int value.
> +The intrinsic vmulq was chosen arbitrarily, but it is representative of
> +all intrinsics that take a non-const scalar value. */
> +void
> +test_scalars (void)
> {
> - /* Test a few different supported ways of passing an int value. The
> - intrinsic vmulq was chosen arbitrarily, but it is representative of
> - all intrinsics that take a non-const scalar value. */
> intvec = vmulq(intvec, 2);
> intvec = vmulq(intvec, (int32_t) 2);
> intvec = vmulq(intvec, (short) 2);
> @@ -33,4 +34,65 @@ void test(void)
> intvec = vmulq(intvec, i8);
> }
>
> +/* Next, test a number of valid pointer overloads. */
> +void
> +foo1 (signed char * addr, int8x16_t value)
> +{
> + vst1q (addr, value);
> +}
> +
> +void
> +foo2 (short * addr, int16x8_t value)
> +{
> + vst1q (addr, value);
> +}
> +
> +void
> +foo3 (int * addr, int32x4_t value)
> +{
> + vst1q (addr, value); /* { dg-warning "invalid conversion" "" { target c++ } } */
> +}
> +
> +void
> +foo4 (long * addr, int32x4_t value)
> +{
> + vst1q (addr, value);
> +}
> +
> +void
> +foo5 (long long * addr, uint64x2_t value)
> +{
> + vldrdq_gather_offset (addr, value);
> +}
> +
> +void
> +foo6 (unsigned char * addr, uint8x16_t value)
> +{
> + vst1q (addr, value);
> +}
> +
> +void
> +foo7 (unsigned short * addr, uint16x8_t value)
> +{
> + vst1q (addr, value);
> +}
> +
> +void
> +foo8 (unsigned int * addr, uint32x4_t value)
> +{
> + vst1q (addr, value); /* { dg-warning "invalid conversion" "" { target c++ } } */
> +}
> +
> +void
> +foo9 (unsigned long * addr, uint32x4_t value)
> +{
> + vst1q (addr, value);
> +}
> +
> +void
> +foo10 (unsigned long long * addr, uint64x2_t value)
> +{
> + vldrdq_gather_offset (addr, value);
> +}
> +
> /* { dg-final { scan-assembler-not "__ARM_undef" } } */
> --
> 2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH 08/10] arm testsuite: Remove reduntant tests
2023-04-28 11:30 ` [PATCH 08/10] arm testsuite: Remove reduntant tests Andrea Corallo
@ 2023-04-28 16:52 ` Kyrylo Tkachov
0 siblings, 0 replies; 31+ messages in thread
From: Kyrylo Tkachov @ 2023-04-28 16:52 UTC (permalink / raw)
To: Andrea Corallo, gcc-patches; +Cc: Richard Earnshaw, Stam Markianos-Wright
> -----Original Message-----
> From: Andrea Corallo <andrea.corallo@arm.com>
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; Stam Markianos-Wright <Stam.Markianos-
> Wright@arm.com>
> Subject: [PATCH 08/10] arm testsuite: Remove reduntant tests
>
> From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
>
> Following Andrea's overhaul of the MVE testsuite, these tests are now
> reduntant, as equivalent checks have been added to the each intrinsic's
> <intrinsic name>.c test.
>
Ok.
Negative diffstat patches are always a pleasure to see 😊
Thanks,
Kyrill
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vaddq_m.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vaddq_n.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c: Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c:
> Removed.
> *
> gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c:
> Removed.
> * gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c: Removed.
> * gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c: Removed.
> ---
> .../arm/mve/intrinsics/mve_fp_vaddq_n.c | 47 ------
> .../arm/mve/intrinsics/mve_vaddq_m.c | 48 ------
> .../arm/mve/intrinsics/mve_vaddq_n.c | 31 ----
> .../arm/mve/intrinsics/mve_vddupq_m_n_u16.c | 13 --
> .../arm/mve/intrinsics/mve_vddupq_m_n_u32.c | 13 --
> .../arm/mve/intrinsics/mve_vddupq_m_n_u8.c | 13 --
> .../arm/mve/intrinsics/mve_vddupq_n_u16.c | 13 --
> .../arm/mve/intrinsics/mve_vddupq_n_u32.c | 13 --
> .../arm/mve/intrinsics/mve_vddupq_n_u8.c | 13 --
> .../arm/mve/intrinsics/mve_vddupq_x_n_u16.c | 12 --
> .../arm/mve/intrinsics/mve_vddupq_x_n_u32.c | 12 --
> .../arm/mve/intrinsics/mve_vddupq_x_n_u8.c | 12 --
> .../arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c | 13 --
> .../arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c | 13 --
> .../arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c | 13 --
> .../arm/mve/intrinsics/mve_vidupq_m_n_u16.c | 13 --
> .../arm/mve/intrinsics/mve_vidupq_m_n_u32.c | 12 --
> .../arm/mve/intrinsics/mve_vidupq_m_n_u8.c | 13 --
> .../arm/mve/intrinsics/mve_vidupq_n_u16.c | 13 --
> .../arm/mve/intrinsics/mve_vidupq_n_u32.c | 12 --
> .../arm/mve/intrinsics/mve_vidupq_n_u8.c | 13 --
> .../arm/mve/intrinsics/mve_vidupq_x_n_u16.c | 12 --
> .../arm/mve/intrinsics/mve_vidupq_x_n_u32.c | 12 --
> .../arm/mve/intrinsics/mve_vidupq_x_n_u8.c | 12 --
> .../arm/mve/intrinsics/mve_viwdupq_x_n_u16.c | 13 --
> .../arm/mve/intrinsics/mve_viwdupq_x_n_u32.c | 13 --
> .../arm/mve/intrinsics/mve_viwdupq_x_n_u8.c | 13 --
> .../intrinsics/mve_vldrdq_gather_offset_s64.c | 12 --
> .../intrinsics/mve_vldrdq_gather_offset_u64.c | 12 --
> .../mve_vldrdq_gather_offset_z_s64.c | 12 --
> .../mve_vldrdq_gather_offset_z_u64.c | 12 --
> .../mve_vldrdq_gather_shifted_offset_s64.c | 12 --
> .../mve_vldrdq_gather_shifted_offset_u64.c | 12 --
> .../mve_vldrdq_gather_shifted_offset_z_s64.c | 12 --
> .../mve_vldrdq_gather_shifted_offset_z_u64.c | 12 --
> .../intrinsics/mve_vldrhq_gather_offset_f16.c | 12 --
> .../intrinsics/mve_vldrhq_gather_offset_s16.c | 12 --
> .../intrinsics/mve_vldrhq_gather_offset_s32.c | 12 --
> .../intrinsics/mve_vldrhq_gather_offset_u16.c | 12 --
> .../intrinsics/mve_vldrhq_gather_offset_u32.c | 13 --
> .../mve_vldrhq_gather_offset_z_f16.c | 12 --
> .../mve_vldrhq_gather_offset_z_s16.c | 12 --
> .../mve_vldrhq_gather_offset_z_s32.c | 12 --
> .../mve_vldrhq_gather_offset_z_u16.c | 13 --
> .../mve_vldrhq_gather_offset_z_u32.c | 13 --
> .../mve_vldrhq_gather_shifted_offset_f16.c | 12 --
> .../mve_vldrhq_gather_shifted_offset_s16.c | 13 --
> .../mve_vldrhq_gather_shifted_offset_s32.c | 13 --
> .../mve_vldrhq_gather_shifted_offset_u16.c | 13 --
> .../mve_vldrhq_gather_shifted_offset_u32.c | 13 --
> .../mve_vldrhq_gather_shifted_offset_z_f16.c | 13 --
> .../mve_vldrhq_gather_shifted_offset_z_s16.c | 13 --
> .../mve_vldrhq_gather_shifted_offset_z_s32.c | 12 --
> .../mve_vldrhq_gather_shifted_offset_z_u16.c | 12 --
> .../mve_vldrhq_gather_shifted_offset_z_u32.c | 12 --
> .../intrinsics/mve_vldrwq_gather_offset_f32.c | 12 --
> .../intrinsics/mve_vldrwq_gather_offset_s32.c | 13 --
> .../intrinsics/mve_vldrwq_gather_offset_u32.c | 13 --
> .../mve_vldrwq_gather_offset_z_f32.c | 12 --
> .../mve_vldrwq_gather_offset_z_s32.c | 13 --
> .../mve_vldrwq_gather_offset_z_u32.c | 13 --
> .../mve_vldrwq_gather_shifted_offset_f32.c | 12 --
> .../mve_vldrwq_gather_shifted_offset_s32.c | 13 --
> .../mve_vldrwq_gather_shifted_offset_u32.c | 13 --
> .../mve_vldrwq_gather_shifted_offset_z_f32.c | 12 --
> .../mve_vldrwq_gather_shifted_offset_z_s32.c | 13 --
> .../mve_vldrwq_gather_shifted_offset_z_u32.c | 13 --
> .../mve_vstore_scatter_shifted_offset.c | 141 -----------------
> .../mve_vstore_scatter_shifted_offset_p.c | 142 ------------------
> .../arm/mve/intrinsics/vaddq_m_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vaddq_m_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vaddq_x_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vaddq_x_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vcmpeqq_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vcmpeqq_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vcmpgeq_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vcmpgeq_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vcmpgtq_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vcmpgtq_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vcmpleq_m_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vcmpleq_m_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vcmpleq_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vcmpleq_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vcmpltq_m_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vcmpltq_m_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vcmpltq_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vcmpltq_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vcmpneq_m_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vcmpneq_m_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vcmpneq_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vcmpneq_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vfmaq_m_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vfmaq_m_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vfmaq_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vfmaq_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vfmasq_m_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vfmasq_m_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vfmasq_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vfmasq_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vmaxnmavq_f16-1.c | 12 --
> .../arm/mve/intrinsics/vmaxnmavq_f32-1.c | 12 --
> .../arm/mve/intrinsics/vmaxnmavq_p_f16-1.c | 12 --
> .../arm/mve/intrinsics/vmaxnmavq_p_f32-1.c | 12 --
> .../arm/mve/intrinsics/vmaxnmvq_f16-1.c | 12 --
> .../arm/mve/intrinsics/vmaxnmvq_f32-1.c | 12 --
> .../arm/mve/intrinsics/vmaxnmvq_p_f16-1.c | 12 --
> .../arm/mve/intrinsics/vmaxnmvq_p_f32-1.c | 12 --
> .../arm/mve/intrinsics/vminnmavq_f16-1.c | 12 --
> .../arm/mve/intrinsics/vminnmavq_f32-1.c | 12 --
> .../arm/mve/intrinsics/vminnmavq_p_f16-1.c | 12 --
> .../arm/mve/intrinsics/vminnmavq_p_f32-1.c | 12 --
> .../arm/mve/intrinsics/vminnmvq_f16-1.c | 12 --
> .../arm/mve/intrinsics/vminnmvq_f32-1.c | 12 --
> .../arm/mve/intrinsics/vminnmvq_p_f16-1.c | 12 --
> .../arm/mve/intrinsics/vminnmvq_p_f32-1.c | 12 --
> .../arm/mve/intrinsics/vmulq_m_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vmulq_m_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vmulq_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vmulq_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vmulq_x_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vmulq_x_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vsetq_lane_f16-1.c | 13 --
> .../arm/mve/intrinsics/vsetq_lane_f32-1.c | 13 --
> .../arm/mve/intrinsics/vsubq_m_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vsubq_m_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vsubq_n_f16-1.c | 12 --
> .../arm/mve/intrinsics/vsubq_n_f32-1.c | 12 --
> .../arm/mve/intrinsics/vsubq_x_n_f16-1.c | 13 --
> .../arm/mve/intrinsics/vsubq_x_n_f32-1.c | 13 --
> 135 files changed, 2006 deletions(-)
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.
> c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.
> c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offse
> t_s64.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offse
> t_u64.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offse
> t_z_s64.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offse
> t_z_u64.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.
> c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.
> c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.
> c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.
> c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.
> c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offse
> t_f16.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offse
> t_s16.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offse
> t_s32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offse
> t_u16.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offse
> t_u32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offse
> t_z_f16.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offse
> t_z_s16.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offse
> t_z_s32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offse
> t_z_u16.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offse
> t_z_u32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.
> c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32
> .c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32
> .c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offse
> t_f32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offse
> t_s32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offse
> t_u32.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offse
> t_z_f32.c
> delete mode 100644
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> delete mode 100644
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> t_z_u32.c
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> gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offse
> t.c
> delete mode 100644
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> t_p.c
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> delete mode 100644
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> delete mode 100644
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> delete mode 100644
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> delete mode 100644
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> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c
> delete mode 100644
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c
> deleted file mode 100644
> index 714fbf9bfe7..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c
> +++ /dev/null
> @@ -1,47 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include <arm_mve.h>
> -int8x16_t foo (int8x16_t a, int16_t b)
> -{
> - return vaddq (a, (b<<3));
> -}
> -int16x8_t foo1 (int16x8_t a, int16_t b)
> -{
> - return vaddq (a, (b<<3));
> -}
> -int32x4_t foo2 (int32x4_t a, int16_t b)
> -{
> - return vaddq (a, (b<<3));
> -}
> -uint8x16_t foo3 (uint8x16_t a, int16_t b)
> -{
> - return vaddq (a, (b<<3));
> -}
> -uint16x8_t foo4 (uint16x8_t a, int16_t b)
> -{
> - return vaddq (a, (b<<3));
> -}
> -uint32x4_t foo5 (uint32x4_t a, int16_t b)
> -{
> - return vaddq (a, (b<<3));
> -}
> -float16x8_t foo6 (float16x8_t a)
> -{
> - return vaddq (a, (float16_t)23.6);
> -}
> -float32x4_t foo7 (float32x4_t a)
> -{
> - return vaddq (a, (float32_t)23.46);
> -}
> -float16x8_t foo8 (float16x8_t a)
> -{
> - return vaddq (a, 23.6);
> -}
> -float32x4_t foo9 (float32x4_t a)
> -{
> - return vaddq (a, 23.46);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c
> deleted file mode 100644
> index 719b95d9020..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c
> +++ /dev/null
> @@ -1,48 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include <arm_mve.h>
> -mve_pred16_t p;
> -
> -int32x4_t fn1 (int32x4_t vecIdx)
> -{
> - return vaddq_m(vuninitializedq_s32(), vecIdx, 1, p);
> -}
> -
> -int16x8_t fn2 (int16x8_t vecIdx)
> -{
> - return vaddq_m(vuninitializedq_s16(), vecIdx, 1, p);
> -}
> -
> -int8x16_t fn3 (int8x16_t vecIdx)
> -{
> - return vaddq_m(vuninitializedq_s8(), vecIdx, 1, p);
> -}
> -
> -uint32x4_t fn4 (uint32x4_t vecIdx)
> -{
> - return vaddq_m(vuninitializedq_u32(), vecIdx, 1, p);
> -}
> -
> -uint16x8_t fn5 (uint16x8_t vecIdx)
> -{
> - return vaddq_m(vuninitializedq_u16(), vecIdx, 1, p);
> -}
> -
> -uint8x16_t fn6 (uint8x16_t vecIdx)
> -{
> - return vaddq_m(vuninitializedq_u8(), vecIdx, 1, p);
> -}
> -
> -float32x4_t fn7 (float32x4_t vecIdx)
> -{
> - return vaddq_m(vuninitializedq_f32(), vecIdx, (float32_t) 1.23, p);
> -}
> -
> -float16x8_t fn8 (float16x8_t vecIdx)
> -{
> - return vaddq_m(vuninitializedq_f16(), vecIdx, (float16_t) 1.40, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c
> deleted file mode 100644
> index baa7fabe061..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c
> +++ /dev/null
> @@ -1,31 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include <arm_mve.h>
> -int8x16_t foo (int8x16_t a, int16_t b)
> -{
> - return vaddq (a, (b<<3));
> -}
> -int16x8_t foo1 (int16x8_t a, int16_t b)
> -{
> - return vaddq (a, (b<<3));
> -}
> -int32x4_t foo2 (int32x4_t a, int16_t b)
> -{
> - return vaddq (a, (b<<3));
> -}
> -uint8x16_t foo3 (uint8x16_t a, int16_t b)
> -{
> - return vaddq (a, (b<<3));
> -}
> -uint16x8_t foo4 (uint16x8_t a, int16_t b)
> -{
> - return vaddq (a, (b<<3));
> -}
> -uint32x4_t foo5 (uint32x4_t a, int16_t b)
> -{
> - return vaddq (a, (b<<3));
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c
> deleted file mode 100644
> index 15587802925..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint16x8_t
> -foo1 (uint16x8_t inactive, int32_t a, mve_pred16_t p)
> -{
> - return vddupq_m (inactive, a, 1, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c
> deleted file mode 100644
> index 8a9ed6327d3..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint32x4_t
> -foo1 (uint32x4_t inactive, int32_t a, mve_pred16_t p)
> -{
> - return vddupq_m (inactive, a, 4, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c
> deleted file mode 100644
> index fe4aceeea97..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint8x16_t
> -foo1 (uint8x16_t inactive, int32_t a, mve_pred16_t p)
> -{
> - return vddupq_m (inactive, a, 4, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c
> deleted file mode 100644
> index 05a68cbe559..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint16x8_t
> -foo1 (int32_t a)
> -{
> - return vddupq_u16 (a, 4);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c
> deleted file mode 100644
> index f702c4cdb0a..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint32x4_t
> -foo1 (int32_t a)
> -{
> - return vddupq_u32 (a, 1);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c
> deleted file mode 100644
> index f272056c423..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint8x16_t
> -foo1 (int32_t a)
> -{
> - return vddupq_u8 (a, 1);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c
> deleted file mode 100644
> index 31e37827e60..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -uint16x8_t
> -foo1 (int32_t a, mve_pred16_t p)
> -{
> - return vddupq_x_u16 (a, 1, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c
> deleted file mode 100644
> index 9989d0b0f00..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -uint32x4_t
> -foo1 (int32_t a, mve_pred16_t p)
> -{
> - return vddupq_x_u32 (a, 4, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c
> deleted file mode 100644
> index 19f1501fe4e..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -uint8x16_t
> -foo1 (int32_t a, mve_pred16_t p)
> -{
> - return vddupq_x_u8 (a, 4, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c
> deleted file mode 100644
> index 07ea2d7d14c..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint16x8_t
> -foo1 (int32_t a, uint32_t b, mve_pred16_t p)
> -{
> - return vdwdupq_x_u16 (a, b, 1, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c
> deleted file mode 100644
> index 9889b0b2b66..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint32x4_t
> -foo1 (int32_t a, uint32_t b, mve_pred16_t p)
> -{
> - return vdwdupq_x_u32 (a, b, 4, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c
> deleted file mode 100644
> index 13ad8d69e18..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint8x16_t
> -foo1 (int32_t a, uint32_t b, mve_pred16_t p)
> -{
> - return vdwdupq_x_u8 (a, b, 4, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c
> deleted file mode 100644
> index cbe998e2faa..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint16x8_t
> -foo1 (uint16x8_t inactive, int32_t a, mve_pred16_t p)
> -{
> - return vidupq_m (inactive, a, 4, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c
> deleted file mode 100644
> index c9aa5c661de..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -uint32x4_t
> -foo1 (uint32x4_t inactive, int32_t a, mve_pred16_t p)
> -{
> - return vidupq_m (inactive, a, 1, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c
> deleted file mode 100644
> index 7b075744d9a..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint8x16_t
> -foo1 (uint8x16_t inactive, int32_t a, mve_pred16_t p)
> -{
> - return vidupq_m (inactive, a, 1, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c
> deleted file mode 100644
> index a461a1e64b1..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint16x8_t
> -foo1 (int32_t a)
> -{
> - return vidupq_u16 (a, 4);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c
> deleted file mode 100644
> index c5b01a7ac90..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -uint32x4_t
> -foo1 (int32_t a)
> -{
> - return vidupq_u32 (a, 1);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c
> deleted file mode 100644
> index f963d51ac0f..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint8x16_t
> -foo1 (int32_t a)
> -{
> - return vidupq_u8 (a, 1);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c
> deleted file mode 100644
> index aecd4be5e71..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -uint16x8_t
> -foo1 (int32_t a, mve_pred16_t p)
> -{
> - return vidupq_x_u16 (a, 4, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c
> deleted file mode 100644
> index d3d33053f92..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -uint32x4_t
> -foo1 (int32_t a, mve_pred16_t p)
> -{
> - return vidupq_x_u32 (a, 1, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c
> deleted file mode 100644
> index f71953aeef4..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -uint8x16_t
> -foo1 (int32_t a, mve_pred16_t p)
> -{
> - return vidupq_x_u8 (a, 1, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c
> deleted file mode 100644
> index 312966773e6..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint16x8_t
> -foo1 (int32_t a, uint32_t b, mve_pred16_t p)
> -{
> - return viwdupq_x_u16 (a, b, 2, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c
> deleted file mode 100644
> index a5d758126d4..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint32x4_t
> -foo1 (int32_t a, uint32_t b, mve_pred16_t p)
> -{
> - return viwdupq_x_u32 (a, b, 4, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c
> deleted file mode 100644
> index aa4e7375d39..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint8x16_t
> -foo1 (int32_t a, uint32_t b, mve_pred16_t p)
> -{
> - return viwdupq_x_u8 (a, b, 8, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.
> c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.
> c
> deleted file mode 100644
> index e5b635983bf..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.
> c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -int64x2_t
> -foo1 (int64_t * base, uint64x2_t offset)
> -{
> - return vldrdq_gather_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.
> c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.
> c
> deleted file mode 100644
> index 8d96527c6df..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.
> c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -uint64x2_t
> -foo1 (uint64_t * base, uint64x2_t offset)
> -{
> - return vldrdq_gather_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s6
> 4.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s6
> 4.c
> deleted file mode 100644
> index e66e4465b19..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s6
> 4.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -int64x2_t
> -foo1 (int64_t * base, uint64x2_t offset, mve_pred16_t p)
> -{
> - return vldrdq_gather_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u
> 64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u
> 64.c
> deleted file mode 100644
> index 7ca9590c12c..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u
> 64.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -uint64x2_t
> -foo1 (uint64_t * base, uint64x2_t offset, mve_pred16_t p)
> -{
> - return vldrdq_gather_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_off
> set_s64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_off
> set_s64.c
> deleted file mode 100644
> index b8491680536..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_off
> set_s64.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -int64x2_t
> -foo1 (int64_t * base, uint64x2_t offset)
> -{
> - return vldrdq_gather_shifted_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_off
> set_u64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_off
> set_u64.c
> deleted file mode 100644
> index 851d4a1f435..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_off
> set_u64.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -uint64x2_t
> -foo1 (uint64_t * base, uint64x2_t offset)
> -{
> - return vldrdq_gather_shifted_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_off
> set_z_s64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_off
> set_z_s64.c
> deleted file mode 100644
> index 586e38cfe43..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_off
> set_z_s64.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -int64x2_t
> -foo1 (int64_t * base, uint64x2_t offset, mve_pred16_t p)
> -{
> - return vldrdq_gather_shifted_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_off
> set_z_u64.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_off
> set_z_u64.c
> deleted file mode 100644
> index dd6f482422f..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_off
> set_z_u64.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -uint64x2_t
> -foo1 (uint64_t * base, uint64x2_t offset, mve_pred16_t p)
> -{
> - return vldrdq_gather_shifted_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.
> c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.
> c
> deleted file mode 100644
> index 3c0ae4b4262..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.
> c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16x8_t
> -foo1 (float16_t * base, uint16x8_t offset)
> -{
> - return vldrhq_gather_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.
> c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.
> c
> deleted file mode 100644
> index bc7a51b38a5..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.
> c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -int16x8_t
> -foo1 (int16_t * base, uint16x8_t offset)
> -{
> - return vldrhq_gather_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.
> c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.
> c
> deleted file mode 100644
> index d6e83072995..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.
> c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -int32x4_t
> -foo1 (int16_t * base, uint32x4_t offset)
> -{
> - return vldrhq_gather_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.
> c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.
> c
> deleted file mode 100644
> index 21b0b1cf52e..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.
> c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -uint16x8_t
> -foo1 (uint16_t * base, uint16x8_t offset)
> -{
> - return vldrhq_gather_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.
> c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.
> c
> deleted file mode 100644
> index 3a9c47e9c47..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.
> c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint32x4_t
> -foo1 (uint16_t * base, uint32x4_t offset)
> -{
> - return vldrhq_gather_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f1
> 6.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f1
> 6.c
> deleted file mode 100644
> index e31d0bc05bb..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f1
> 6.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16x8_t
> -foo1 (float16_t * base, uint16x8_t offset, mve_pred16_t p)
> -{
> - return vldrhq_gather_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s1
> 6.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s1
> 6.c
> deleted file mode 100644
> index 6a40159be42..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s1
> 6.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -int16x8_t
> -foo1 (int16_t * base, uint16x8_t offset, mve_pred16_t p)
> -{
> - return vldrhq_gather_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s3
> 2.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s3
> 2.c
> deleted file mode 100644
> index 1d9a70db727..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s3
> 2.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -int32x4_t
> -foo1 (int16_t * base, uint32x4_t offset, mve_pred16_t p)
> -{
> - return vldrhq_gather_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u
> 16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u
> 16.c
> deleted file mode 100644
> index 8fedbef9aef..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u
> 16.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint16x8_t
> -foo1 (uint16_t * base, uint16x8_t offset, mve_pred16_t p)
> -{
> - return vldrhq_gather_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u
> 32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u
> 32.c
> deleted file mode 100644
> index db410437c02..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u
> 32.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint32x4_t
> -foo1 (uint16_t * base, uint32x4_t offset, mve_pred16_t p)
> -{
> - return vldrhq_gather_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_f16.c
> deleted file mode 100644
> index c12bd91a733..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_f16.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16x8_t
> -foo1 (float16_t * base, uint16x8_t offset)
> -{
> - return vldrhq_gather_shifted_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_s16.c
> deleted file mode 100644
> index df291626299..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_s16.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -int16x8_t
> -foo1 (int16_t * base, uint16x8_t offset)
> -{
> - return vldrhq_gather_shifted_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_s32.c
> deleted file mode 100644
> index 9bc6627accf..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_s32.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -int32x4_t
> -foo1 (int16_t * base, uint32x4_t offset)
> -{
> - return vldrhq_gather_shifted_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_u16.c
> deleted file mode 100644
> index c470871617d..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_u16.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint16x8_t
> -foo1 (uint16_t * base, uint16x8_t offset)
> -{
> - return vldrhq_gather_shifted_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_u32.c
> deleted file mode 100644
> index 2d4fe4c1d25..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_u32.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint32x4_t
> -foo1 (uint16_t * base, uint32x4_t offset)
> -{
> - return vldrhq_gather_shifted_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_z_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_z_f16.c
> deleted file mode 100644
> index 755540d93b6..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_z_f16.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16x8_t
> -foo1 (float16_t * base, uint16x8_t offset, mve_pred16_t p)
> -{
> - return vldrhq_gather_shifted_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler "vldrht.f16" } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_z_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_z_s16.c
> deleted file mode 100644
> index b9fc8d3242b..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_z_s16.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -int16x8_t
> -foo1 (int16_t * base, uint16x8_t offset, mve_pred16_t p)
> -{
> - return vldrhq_gather_shifted_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler "vldrht.u16" } } */
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_z_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_z_s32.c
> deleted file mode 100644
> index c65df114f15..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_z_s32.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -int32x4_t
> -foo1 (int16_t * base, uint32x4_t offset, mve_pred16_t p)
> -{
> - return vldrhq_gather_shifted_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_z_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_z_u16.c
> deleted file mode 100644
> index 8bb493bc6c0..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_z_u16.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -uint16x8_t
> -foo1 (uint16_t * base, uint16x8_t offset, mve_pred16_t p)
> -{
> - return vldrhq_gather_shifted_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_z_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_z_u32.c
> deleted file mode 100644
> index cac933f0f36..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_off
> set_z_u32.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -uint32x4_t
> -foo1 (uint16_t * base, uint32x4_t offset, mve_pred16_t p)
> -{
> - return vldrhq_gather_shifted_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.
> c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.
> c
> deleted file mode 100644
> index 6d10e1ce9e8..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.
> c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32x4_t
> -foo1 (float32_t * base, uint32x4_t offset)
> -{
> - return vldrwq_gather_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.
> c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32
> .c
> deleted file mode 100644
> index 0f29a6a8aa1..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.
> c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -int32x4_t
> -foo1 (int32_t * base, uint32x4_t offset)
> -{
> - return vldrwq_gather_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32
> .c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32
> .c
> deleted file mode 100644
> index 29e231757ec..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32
> .c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint32x4_t
> -foo1 (uint32_t * base, uint32x4_t offset)
> -{
> - return vldrwq_gather_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f
> 32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f
> 32.c
> deleted file mode 100644
> index 77a949fc1a6..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f
> 32.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32x4_t
> -foo1 (float32_t * base, uint32x4_t offset, mve_pred16_t p)
> -{
> - return vldrwq_gather_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s
> 32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s
> 32.c
> deleted file mode 100644
> index 849783ab89f..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s
> 32.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -int32x4_t
> -foo1 (int32_t * base, uint32x4_t offset, mve_pred16_t p)
> -{
> - return vldrwq_gather_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u
> 32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u
> 32.c
> deleted file mode 100644
> index 3fe47cbeab5..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u
> 32.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint32x4_t
> -foo1 (uint32_t * base, uint32x4_t offset, mve_pred16_t p)
> -{
> - return vldrwq_gather_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_off
> set_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_off
> set_f32.c
> deleted file mode 100644
> index 0d166348de5..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_off
> set_f32.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32x4_t
> -foo1 (float32_t * base, uint32x4_t offset)
> -{
> - return vldrwq_gather_shifted_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_off
> set_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_off
> set_s32.c
> deleted file mode 100644
> index 78e520b159e..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_off
> set_s32.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -int32x4_t
> -foo1 (int32_t * base, uint32x4_t offset)
> -{
> - return vldrwq_gather_shifted_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_off
> set_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_off
> set_u32.c
> deleted file mode 100644
> index 6b8b72818d9..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_off
> set_u32.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint32x4_t
> -foo1 (uint32_t * base, uint32x4_t offset)
> -{
> - return vldrwq_gather_shifted_offset (base, offset);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_off
> set_z_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_off
> set_z_f32.c
> deleted file mode 100644
> index db79e57a2f5..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_off
> set_z_f32.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32x4_t
> -foo1 (float32_t * base, uint32x4_t offset, mve_pred16_t p)
> -{
> - return vldrwq_gather_shifted_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_off
> set_z_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_off
> set_z_s32.c
> deleted file mode 100644
> index e060fee10ca..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_off
> set_z_s32.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -int32x4_t
> -foo1 (int32_t * base, uint32x4_t offset, mve_pred16_t p)
> -{
> - return vldrwq_gather_shifted_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_off
> set_z_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_off
> set_z_u32.c
> deleted file mode 100644
> index 72446470ae3..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_off
> set_z_u32.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> -/* { dg-add-options arm_v8_1m_mve } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -uint32x4_t
> -foo1 (uint32_t * base, uint32x4_t offset, mve_pred16_t p)
> -{
> - return vldrwq_gather_shifted_offset_z (base, offset, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_off
> set.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_off
> set.c
> deleted file mode 100644
> index 62dfb450a6d..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_off
> set.c
> +++ /dev/null
> @@ -1,141 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -int
> -foowu32( uint32_t * pDataSrc, uint32_t * pDataDest)
> -{
> - const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
> - const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
> - uint32x4_t vecIn1 = vldrwq_u32 ((uint32_t const *) pDataSrc);
> - uint32x4_t vecIn2 = vldrwq_u32 ((uint32_t const *) &pDataSrc[4]);
> - vstrwq_scatter_shifted_offset_u32 (pDataDest, vecOffs1, vecIn1);
> - vstrwq_scatter_shifted_offset_u32 (pDataDest, vecOffs2, vecIn2);
> - pDataDest[8] = pDataSrc[8];
> - return 0;
> -}
> -
> -int
> -foowf32( float32_t * pDataSrc, float32_t * pDataDest)
> -{
> - const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
> - const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
> - float32x4_t vecIn1 = vldrwq_f32 ((float32_t const *) pDataSrc);
> - float32x4_t vecIn2 = vldrwq_f32 ((float32_t const *) &pDataSrc[4]);
> - vstrwq_scatter_shifted_offset_f32 (pDataDest, vecOffs1, vecIn1);
> - vstrwq_scatter_shifted_offset_f32 (pDataDest, vecOffs2, vecIn2);
> - pDataDest[8] = pDataSrc[8];
> - return 0;
> -}
> -
> -int
> -foohu16( uint16_t * pDataSrc, uint16_t * pDataDest)
> -{
> - const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
> - const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
> - uint16x8_t vecIn1 = vldrhq_u16 ((uint16_t const *) pDataSrc);
> - uint16x8_t vecIn2 = vldrhq_u16 ((uint16_t const *) &pDataSrc[8]);
> - vstrhq_scatter_shifted_offset_u16 (pDataDest, vecOffs1, vecIn1);
> - vstrhq_scatter_shifted_offset_u16 (pDataDest, vecOffs2, vecIn2);
> - pDataDest[16] = pDataSrc[16];
> - return 0;
> -}
> -
> -int
> -foohu32( uint32_t * pDataSrc, uint32_t * pDataDest)
> -{
> - const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
> - const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
> - uint32x4_t vecIn1 = vldrhq_u32 ((uint16_t const *) pDataSrc);
> - uint32x4_t vecIn2 = vldrhq_u32 ((uint16_t const *) &pDataSrc[4]);
> - vstrhq_scatter_shifted_offset_u32 ((uint16_t *)pDataDest, vecOffs1,
> vecIn1);
> - vstrhq_scatter_shifted_offset_u32 ((uint16_t *)pDataDest, vecOffs2,
> vecIn2);
> - pDataDest[8] = pDataSrc[8];
> - return 0;
> -}
> -
> -int
> -foohf16( float16_t * pDataSrc, float16_t * pDataDest)
> -{
> - const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
> - const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
> - float16x8_t vecIn1 = vldrhq_f16 ((float16_t const *) pDataSrc);
> - float16x8_t vecIn2 = vldrhq_f16 ((float16_t const *) &pDataSrc[8]);
> - vstrhq_scatter_shifted_offset_f16 (pDataDest, vecOffs1, vecIn1);
> - vstrhq_scatter_shifted_offset_f16 (pDataDest, vecOffs2, vecIn2);
> - pDataDest[16] = pDataSrc[16];
> - return 0;
> -}
> -
> -int
> -foodu64( uint64_t * pDataSrc, uint64_t * pDataDest)
> -{
> - const uint64x2_t vecOffs1 = { 0, 1};
> - const uint64x2_t vecOffs2 = { 2, 3};
> - uint32x4_t vecIn1 = vldrwq_u32 ((uint32_t const *) pDataSrc);
> - uint32x4_t vecIn2 = vldrwq_u32 ((uint32_t const *) &pDataSrc[2]);
> -
> - vstrdq_scatter_shifted_offset_u64 (pDataDest, vecOffs1, (uint64x2_t)
> vecIn1);
> - vstrdq_scatter_shifted_offset_u64 (pDataDest, vecOffs2, (uint64x2_t)
> vecIn2);
> -
> - pDataDest[2] = pDataSrc[2];
> - return 0;
> -}
> -
> -int
> -foows32( int32_t * pDataSrc, int32_t * pDataDest)
> -{
> - const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
> - const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
> - int32x4_t vecIn1 = vldrwq_s32 ((int32_t const *) pDataSrc);
> - int32x4_t vecIn2 = vldrwq_s32 ((int32_t const *) &pDataSrc[4]);
> - vstrwq_scatter_shifted_offset_s32 (pDataDest, vecOffs1, vecIn1);
> - vstrwq_scatter_shifted_offset_s32 (pDataDest, vecOffs2, vecIn2);
> - pDataDest[8] = pDataSrc[8];
> - return 0;
> -}
> -
> -int
> -foohs16( int16_t * pDataSrc, int16_t * pDataDest)
> -{
> - const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
> - const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
> - int16x8_t vecIn1 = vldrhq_s16 ((int16_t const *) pDataSrc);
> - int16x8_t vecIn2 = vldrhq_s16 ((int16_t const *) &pDataSrc[8]);
> - vstrhq_scatter_shifted_offset_s16 (pDataDest, vecOffs1, vecIn1);
> - vstrhq_scatter_shifted_offset_s16 (pDataDest, vecOffs2, vecIn2);
> - pDataDest[16] = pDataSrc[16];
> - return 0;
> -}
> -
> -int
> -foohs32( int32_t * pDataSrc, int32_t * pDataDest)
> -{
> - const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
> - const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
> - int32x4_t vecIn1 = vldrhq_s32 ((int16_t const *) pDataSrc);
> - int32x4_t vecIn2 = vldrhq_s32 ((int16_t const *) &pDataSrc[4]);
> - vstrhq_scatter_shifted_offset_s32 ((int16_t *)pDataDest, vecOffs1, vecIn1);
> - vstrhq_scatter_shifted_offset_s32 ((int16_t *)pDataDest, vecOffs2, vecIn2);
> - pDataDest[8] = pDataSrc[8];
> - return 0;
> -}
> -
> -int
> -foods64( int64_t * pDataSrc, int64_t * pDataDest)
> -{
> - const uint64x2_t vecOffs1 = { 0, 1};
> - const uint64x2_t vecOffs2 = { 2, 3};
> - int32x4_t vecIn1 = vldrwq_s32 ((int32_t const *) pDataSrc);
> - int32x4_t vecIn2 = vldrwq_s32 ((int32_t const *) &pDataSrc[2]);
> -
> - vstrdq_scatter_shifted_offset_s64 (pDataDest, vecOffs1, (int64x2_t)
> vecIn1);
> - vstrdq_scatter_shifted_offset_s64 (pDataDest, vecOffs2, (int64x2_t)
> vecIn2);
> -
> - pDataDest[2] = pDataSrc[2];
> - return 0;
> -}
> -
> -/* { dg-final { scan-assembler-times "vstr\[a-z\]" 20 } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_off
> set_p.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_off
> set_p.c
> deleted file mode 100644
> index a51d3a21167..00000000000
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_off
> set_p.c
> +++ /dev/null
> @@ -1,142 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -
> -mve_pred16_t __p;
> -int
> -foowu32( uint32_t * pDataSrc, uint32_t * pDataDest)
> -{
> - const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
> - const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
> - uint32x4_t vecIn1 = vldrwq_z_u32 ((uint32_t const *) pDataSrc, __p);
> - uint32x4_t vecIn2 = vldrwq_z_u32 ((uint32_t const *) &pDataSrc[4], __p);
> - vstrwq_scatter_shifted_offset_p_u32 (pDataDest, vecOffs1, vecIn1, __p);
> - vstrwq_scatter_shifted_offset_p_u32 (pDataDest, vecOffs2, vecIn2, __p);
> - pDataDest[8] = pDataSrc[8];
> - return 0;
> -}
> -
> -int
> -foowf32( float32_t * pDataSrc, float32_t * pDataDest)
> -{
> - const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
> - const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
> - float32x4_t vecIn1 = vldrwq_z_f32 ((float32_t const *) pDataSrc, __p);
> - float32x4_t vecIn2 = vldrwq_z_f32 ((float32_t const *) &pDataSrc[4], __p);
> - vstrwq_scatter_shifted_offset_p_f32 (pDataDest, vecOffs1, vecIn1, __p);
> - vstrwq_scatter_shifted_offset_p_f32 (pDataDest, vecOffs2, vecIn2, __p);
> - pDataDest[8] = pDataSrc[8];
> - return 0;
> -}
> -
> -int
> -foohu16( uint16_t * pDataSrc, uint16_t * pDataDest)
> -{
> - const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
> - const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
> - uint16x8_t vecIn1 = vldrhq_z_u16 ((uint16_t const *) pDataSrc, __p);
> - uint16x8_t vecIn2 = vldrhq_z_u16 ((uint16_t const *) &pDataSrc[8], __p);
> - vstrhq_scatter_shifted_offset_p_u16 (pDataDest, vecOffs1, vecIn1, __p);
> - vstrhq_scatter_shifted_offset_p_u16 (pDataDest, vecOffs2, vecIn2, __p);
> - pDataDest[16] = pDataSrc[16];
> - return 0;
> -}
> -
> -int
> -foohu32( uint32_t * pDataSrc, uint32_t * pDataDest)
> -{
> - const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
> - const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
> - uint32x4_t vecIn1 = vldrhq_z_u32 ((uint16_t const *) pDataSrc, __p);
> - uint32x4_t vecIn2 = vldrhq_z_u32 ((uint16_t const *) &pDataSrc[4], __p);
> - vstrhq_scatter_shifted_offset_p_u32 ((uint16_t *)pDataDest, vecOffs1,
> vecIn1, __p);
> - vstrhq_scatter_shifted_offset_p_u32 ((uint16_t *)pDataDest, vecOffs2,
> vecIn2, __p);
> - pDataDest[8] = pDataSrc[8];
> - return 0;
> -}
> -
> -int
> -foohf16( float16_t * pDataSrc, float16_t * pDataDest)
> -{
> - const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
> - const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
> - float16x8_t vecIn1 = vldrhq_z_f16 ((float16_t const *) pDataSrc, __p);
> - float16x8_t vecIn2 = vldrhq_z_f16 ((float16_t const *) &pDataSrc[8], __p);
> - vstrhq_scatter_shifted_offset_p_f16 (pDataDest, vecOffs1, vecIn1, __p);
> - vstrhq_scatter_shifted_offset_p_f16 (pDataDest, vecOffs2, vecIn2, __p);
> - pDataDest[16] = pDataSrc[16];
> - return 0;
> -}
> -
> -int
> -foodu64( uint64_t * pDataSrc, uint64_t * pDataDest)
> -{
> - const uint64x2_t vecOffs1 = { 0, 1};
> - const uint64x2_t vecOffs2 = { 2, 3};
> - uint32x4_t vecIn1 = vldrwq_z_u32 ((uint32_t const *) pDataSrc, __p);
> - uint32x4_t vecIn2 = vldrwq_z_u32 ((uint32_t const *) &pDataSrc[2], __p);
> -
> - vstrdq_scatter_shifted_offset_p_u64 (pDataDest, vecOffs1, (uint64x2_t)
> vecIn1, __p);
> - vstrdq_scatter_shifted_offset_p_u64 (pDataDest, vecOffs2, (uint64x2_t)
> vecIn2, __p);
> -
> - pDataDest[2] = pDataSrc[2];
> - return 0;
> -}
> -
> -int
> -foows32( int32_t * pDataSrc, int32_t * pDataDest)
> -{
> - const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
> - const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
> - int32x4_t vecIn1 = vldrwq_z_s32 ((int32_t const *) pDataSrc, __p);
> - int32x4_t vecIn2 = vldrwq_z_s32 ((int32_t const *) &pDataSrc[4], __p);
> - vstrwq_scatter_shifted_offset_p_s32 (pDataDest, vecOffs1, vecIn1, __p);
> - vstrwq_scatter_shifted_offset_p_s32 (pDataDest, vecOffs2, vecIn2, __p);
> - pDataDest[8] = pDataSrc[8];
> - return 0;
> -}
> -
> -int
> -foohs16( int16_t * pDataSrc, int16_t * pDataDest)
> -{
> - const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
> - const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
> - int16x8_t vecIn1 = vldrhq_z_s16 ((int16_t const *) pDataSrc, __p);
> - int16x8_t vecIn2 = vldrhq_z_s16 ((int16_t const *) &pDataSrc[8], __p);
> - vstrhq_scatter_shifted_offset_p_s16 (pDataDest, vecOffs1, vecIn1, __p);
> - vstrhq_scatter_shifted_offset_p_s16 (pDataDest, vecOffs2, vecIn2, __p);
> - pDataDest[16] = pDataSrc[16];
> - return 0;
> -}
> -
> -int
> -foohs32( int32_t * pDataSrc, int32_t * pDataDest)
> -{
> - const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
> - const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
> - int32x4_t vecIn1 = vldrhq_z_s32 ((int16_t const *) pDataSrc, __p);
> - int32x4_t vecIn2 = vldrhq_z_s32 ((int16_t const *) &pDataSrc[4], __p);
> - vstrhq_scatter_shifted_offset_p_s32 ((int16_t *)pDataDest, vecOffs1,
> vecIn1, __p);
> - vstrhq_scatter_shifted_offset_p_s32 ((int16_t *)pDataDest, vecOffs2,
> vecIn2, __p);
> - pDataDest[8] = pDataSrc[8];
> - return 0;
> -}
> -
> -int
> -foods64( int64_t * pDataSrc, int64_t * pDataDest)
> -{
> - const uint64x2_t vecOffs1 = { 0, 1};
> - const uint64x2_t vecOffs2 = { 2, 3};
> - int32x4_t vecIn1 = vldrwq_z_s32 ((int32_t const *) pDataSrc, __p);
> - int32x4_t vecIn2 = vldrwq_z_s32 ((int32_t const *) &pDataSrc[2], __p);
> -
> - vstrdq_scatter_shifted_offset_p_s64 (pDataDest, vecOffs1, (int64x2_t)
> vecIn1, __p);
> - vstrdq_scatter_shifted_offset_p_s64 (pDataDest, vecOffs2, (int64x2_t)
> vecIn2, __p);
> -
> - pDataDest[2] = pDataSrc[2];
> - return 0;
> -}
> -
> -/* { dg-final { scan-assembler-times "vstr\[a-z\]t" 20 } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c
> deleted file mode 100644
> index 8348098f948..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16x8_t
> -foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
> -{
> - return vaddq_m (inactive, a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c
> deleted file mode 100644
> index c34cc98385f..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32x4_t
> -foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
> -{
> - return vaddq_m (inactive, a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c
> deleted file mode 100644
> index 3bb01676947..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16x8_t
> -foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
> -{
> - return vaddq_x (a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c
> deleted file mode 100644
> index 66dedc7d7e5..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32x4_t
> -foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
> -{
> - return vaddq_x (a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c
> deleted file mode 100644
> index 909ca936492..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
> -{
> - return vcmpeqq_m (a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c
> deleted file mode 100644
> index 8f993af20af..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
> -{
> - return vcmpeqq_m (a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c
> deleted file mode 100644
> index 223cffc17e5..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float16x8_t a, float16_t b)
> -{
> - return vcmpeqq (a, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c
> deleted file mode 100644
> index 81669bd7c60..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float32x4_t a, float32_t b)
> -{
> - return vcmpeqq (a, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c
> deleted file mode 100644
> index 4a4e4b34fde..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
> -{
> - return vcmpgeq_m (a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c
> deleted file mode 100644
> index c406a63aae2..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
> -{
> - return vcmpgeq_m (a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c
> deleted file mode 100644
> index a65ed4421a8..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float16x8_t a, float16_t b)
> -{
> - return vcmpgeq (a, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c
> deleted file mode 100644
> index 2e2fc0170eb..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float32x4_t a, float32_t b)
> -{
> - return vcmpgeq (a, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c
> deleted file mode 100644
> index 08c91a72e05..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
> -{
> - return vcmpgtq_m (a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c
> deleted file mode 100644
> index 0b74482211d..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
> -{
> - return vcmpgtq_m (a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c
> deleted file mode 100644
> index 3b2faeaf64f..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float16x8_t a, float16_t b)
> -{
> - return vcmpgtq (a, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c
> deleted file mode 100644
> index 16862e0209c..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float32x4_t a, float32_t b)
> -{
> - return vcmpgtq (a, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c
> deleted file mode 100644
> index 50e53bdac47..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
> -{
> - return vcmpleq_m (a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c
> deleted file mode 100644
> index b16da273a91..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
> -{
> - return vcmpleq_m (a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c
> deleted file mode 100644
> index 4a4b97312b0..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float16x8_t a, float16_t b)
> -{
> - return vcmpleq (a, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c
> deleted file mode 100644
> index 8d8f1051933..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float32x4_t a, float32_t b)
> -{
> - return vcmpleq (a, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c
> deleted file mode 100644
> index 62ab53fb2ef..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
> -{
> - return vcmpltq_m (a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c
> deleted file mode 100644
> index 55886fccff1..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
> -{
> - return vcmpltq_m (a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c
> deleted file mode 100644
> index cd95daea48c..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float16x8_t a, float16_t b)
> -{
> - return vcmpltq (a, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c
> deleted file mode 100644
> index db76687d53e..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float32x4_t a, float32_t b)
> -{
> - return vcmpltq (a, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c
> deleted file mode 100644
> index 30618e87101..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
> -{
> - return vcmpneq_m (a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c
> deleted file mode 100644
> index 4ecfda6d75c..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
> -{
> - return vcmpneq_m (a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c
> deleted file mode 100644
> index 75a0090fcdc..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float16x8_t a, float16_t b)
> -{
> - return vcmpneq (a, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c
> deleted file mode 100644
> index 11ae14cff56..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -mve_pred16_t
> -foo1 (float32x4_t a, float32_t b)
> -{
> - return vcmpneq (a, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c
> deleted file mode 100644
> index e47ae6d8e3b..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16x8_t
> -foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
> -{
> - return vfmaq_m (a, b, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c
> deleted file mode 100644
> index 78c39f0b2c9..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32x4_t
> -foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
> -{
> - return vfmaq_m (a, b, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c
> deleted file mode 100644
> index f7867f2c0c3..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16x8_t
> -foo1 (float16x8_t a, float16x8_t b, float16_t c)
> -{
> - return vfmaq (a, b, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c
> deleted file mode 100644
> index f0bc45bfed9..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32x4_t
> -foo1 (float32x4_t a, float32x4_t b, float32_t c)
> -{
> - return vfmaq (a, b, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c
> deleted file mode 100644
> index 4750e108b6d..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16x8_t
> -foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
> -{
> - return vfmasq_m (a, b, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c
> deleted file mode 100644
> index 4a379711386..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32x4_t
> -foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
> -{
> - return vfmasq_m (a, b, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c
> deleted file mode 100644
> index db824512b2b..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16x8_t
> -foo1 (float16x8_t a, float16x8_t b, float16_t c)
> -{
> - return vfmasq (a, b, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c
> deleted file mode 100644
> index 12b1410c008..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32x4_t
> -foo1 (float32x4_t a, float32x4_t b, float32_t c)
> -{
> - return vfmasq (a, b, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c
> deleted file mode 100644
> index 7c2349d1ee4..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16_t
> -foo1 (float16_t a, float16x8_t b)
> -{
> - return vmaxnmavq (a, b);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c
> deleted file mode 100644
> index 0deef79487a..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32_t
> -foo1 (float32_t a, float32x4_t b)
> -{
> - return vmaxnmavq (a, b);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c
> deleted file mode 100644
> index 56a7ac001f9..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16_t
> -foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
> -{
> - return vmaxnmavq_p (a, b, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c
> deleted file mode 100644
> index 36c10a90633..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32_t
> -foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
> -{
> - return vmaxnmavq_p (a, b, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c
> deleted file mode 100644
> index f60641f5de0..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16_t
> -foo1 (float16_t a, float16x8_t b)
> -{
> - return vmaxnmvq (23.35, b);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c
> deleted file mode 100644
> index f8c9f44ac78..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32_t
> -foo1 (float32_t a, float32x4_t b)
> -{
> - return vmaxnmvq (34.56, b);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c
> deleted file mode 100644
> index 96820ecab91..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16_t
> -foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
> -{
> - return vmaxnmvq_p (a, b, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c
> deleted file mode 100644
> index 826ee8f900a..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32_t
> -foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
> -{
> - return vmaxnmvq_p (a, b, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c
> deleted file mode 100644
> index 37d5136edca..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16_t
> -foo1 (float16_t a, float16x8_t b)
> -{
> - return vminnmavq (a, b);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c
> deleted file mode 100644
> index 78978d05054..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32_t
> -foo1 (float32_t a, float32x4_t b)
> -{
> - return vminnmavq (a, b);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c
> deleted file mode 100644
> index 7170b747a40..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16_t
> -foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
> -{
> - return vminnmavq_p (a, b, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c
> deleted file mode 100644
> index 09559053852..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32_t
> -foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
> -{
> - return vminnmavq_p (a, b, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c
> deleted file mode 100644
> index 132d1a123f8..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16_t
> -foo1 (float16_t a, float16x8_t b)
> -{
> - return vminnmvq (a, b);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c
> deleted file mode 100644
> index 74909075b09..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32_t
> -foo1 (float32_t a, float32x4_t b)
> -{
> - return vminnmvq (a, b);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c
> deleted file mode 100644
> index c88c3b74a50..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16_t
> -foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
> -{
> - return vminnmvq_p (a, b, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c
> deleted file mode 100644
> index e4db972fc70..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32_t
> -foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
> -{
> - return vminnmvq_p (a, b, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c
> deleted file mode 100644
> index c8222c5c7b9..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16x8_t
> -foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
> -{
> - return vmulq_m (inactive, a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c
> deleted file mode 100644
> index 2fae3a7f8fa..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32x4_t
> -foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
> -{
> - return vmulq_m (inactive, a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c
> deleted file mode 100644
> index cef311d981d..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16x8_t
> -foo1 (float16x8_t a, float16_t b)
> -{
> - return vmulq (a, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c
> deleted file mode 100644
> index d6d4b9a0a7c..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32x4_t
> -foo1 (float32x4_t a, float32_t b)
> -{
> - return vmulq (a, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c
> deleted file mode 100644
> index ea4cab03490..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16x8_t
> -foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
> -{
> - return vmulq_x (a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c
> deleted file mode 100644
> index a7a54c7c92c..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32x4_t
> -foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
> -{
> - return vmulq_x (a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c
> deleted file mode 100644
> index 608dd30788e..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16x8_t
> -foo (float16_t a, float16x8_t b)
> -{
> - return vsetq_lane (23.26, b, 0);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c
> deleted file mode 100644
> index c5f5db7f28d..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32x4_t
> -foo (float32_t a, float32x4_t b)
> -{
> - return vsetq_lane (23.34, b, 0);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c
> deleted file mode 100644
> index f3e19613e7e..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16x8_t
> -foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
> -{
> - return vsubq_m (inactive, a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c
> deleted file mode 100644
> index 4b5cd90c9ed..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32x4_t
> -foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
> -{
> - return vsubq_m (inactive, a, 23.23, p);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c
> deleted file mode 100644
> index f8832546f54..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16x8_t
> -foo1 (float16x8_t a, float16_t b)
> -{
> - return vsubq (a, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c
> deleted file mode 100644
> index 88d9675540d..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32x4_t
> -foo1 (float32x4_t a, float32_t b)
> -{
> - return vsubq (a, 23.23);
> -}
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c
> deleted file mode 100644
> index b3a67bb43eb..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float16x8_t
> -foo (float16x8_t a, float16_t b, mve_pred16_t p)
> -{
> - return vsubq_x_n_f16 (a, 23.23, p);
> -}
> -
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c
> deleted file mode 100644
> index dcb2425397b..00000000000
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> -/* { dg-add-options arm_v8_1m_mve_fp } */
> -/* { dg-additional-options "-O2" } */
> -
> -#include "arm_mve.h"
> -float32x4_t
> -foo (float32x4_t a, float32_t b, mve_pred16_t p)
> -{
> - return vsubq_x_n_f32 (a, 23.23, p);
> -}
> -
> -
> -/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> --
> 2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests
2023-04-28 11:30 ` [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests Andrea Corallo
@ 2023-04-28 16:54 ` Kyrylo Tkachov
2023-05-02 12:17 ` Stamatis Markianos-Wright
2023-05-02 8:28 ` Christophe Lyon
1 sibling, 1 reply; 31+ messages in thread
From: Kyrylo Tkachov @ 2023-04-28 16:54 UTC (permalink / raw)
To: Andrea Corallo, gcc-patches; +Cc: Richard Earnshaw, Stam Markianos-Wright
> -----Original Message-----
> From: Andrea Corallo <andrea.corallo@arm.com>
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; Stam Markianos-Wright <Stam.Markianos-
> Wright@arm.com>
> Subject: [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests
>
> From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
>
> Hi all,
>
> This is a simple testsuite tidy-up patch, addressing to types of errors:
>
> * The vcmp vector-scalar tests failing due to the compiler's preference
> of vector-vector comparisons, over vector-scalar comparisons. This is
> due to the lack of cost model for MVE and the compiler not knowing that
> the RTL vec_duplicate is free in those instructions. For now, we simply
> XFAIL these checks.
I'd like to see this deficiency tracked in Bugzilla before we mark these as XFAIL.
> * The tests for pr108177 had strict usage of q0 and r0 registers,
> meaning that they would FAIL with -mfloat-abi=softf. The register checks
> have now been relaxed.
This part is ok.
Thanks,
Kyrill
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arm/mve/intrinsics/srshr.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/srshrl.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/uqshl.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/uqshll.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/urshr.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/urshrl.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vadciq_s32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vadciq_u32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vadcq_s32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vadcq_u32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: XFAIL check.
> * gcc.target/arm/mve/pr108177-1.c: Relax registers.
> * gcc.target/arm/mve/pr108177-10.c: Relax registers.
> * gcc.target/arm/mve/pr108177-11.c: Relax registers.
> * gcc.target/arm/mve/pr108177-12.c: Relax registers.
> * gcc.target/arm/mve/pr108177-13.c: Relax registers.
> * gcc.target/arm/mve/pr108177-14.c: Relax registers.
> * gcc.target/arm/mve/pr108177-2.c: Relax registers.
> * gcc.target/arm/mve/pr108177-3.c: Relax registers.
> * gcc.target/arm/mve/pr108177-4.c: Relax registers.
> * gcc.target/arm/mve/pr108177-5.c: Relax registers.
> * gcc.target/arm/mve/pr108177-6.c: Relax registers.
> * gcc.target/arm/mve/pr108177-7.c: Relax registers.
> * gcc.target/arm/mve/pr108177-8.c: Relax registers.
> * gcc.target/arm/mve/pr108177-9.c: Relax registers.
> ---
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/pr108177-1.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-10.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-11.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-12.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-13.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-14.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-2.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-3.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-4.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-5.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-6.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-7.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-8.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-9.c | 4 ++--
> 38 files changed, 52 insertions(+), 52 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
> index dc63c527743..9f8111438a1 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
> @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
> index 8c5d185ca22..799d3bcdab1 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
> @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
> index 2296f3e1655..16c3617c104 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
> @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
> index 1d870428c55..2f84d751c53 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
> index 8b8610b0617..6cfe7338fce 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
> index 409c9de58ba..362e830c908 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
> @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
> index c3b1736bfa1..583beb97849 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
> @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
> index 3728c738b54..db7f1877d73 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
> @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
> index 4e9a346ab14..978bd7d4b52 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
> index 2cf1d1ab0b6..66b6d8b0056 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
> index 89d8e2b9109..9c5f1f2f5c8 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
> index 482ac094cf3..2723aa7f98f 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
> index 085b8277736..5712db2ceef 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
> @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
> index a62a73ff24c..f7a25af8574 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
> @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
> index f05c9d24643..8cd28fb1681 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
> @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
> index 4f6276484ba..1d1f4bf0e58 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
> index e71dcb8f174..bf77a808064 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
> index c6fdb08d8ae..f9f091cd9b3 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
> index 4f1ac3c0977..d22ea1aca30 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
> index e36d8a95a85..83beca964d6 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
> index 7262503eee6..abe1abfed2a 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
> index 71d878dff9f..ca55fe2f76c 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
> @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
> index 3f997e8e487..77bac757d68 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
> @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
> index 9917a95ffb7..352afa798d1 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
> @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
> b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
> index 2d42062bc8e..8383b4d9e3a 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrbt.8 q0, \[r0\]
> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrbt.8 q0, \[r0\]
> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
> b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
> index 4db594f588f..7b1cd3711d8 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrht.32 q0, \[r0\]
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrht.32 q0, \[r0\]
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
> b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
> index 329fcb33eeb..e6ae8524052 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrwt.32 q0, \[r0\]
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrwt.32 q0, \[r0\]
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
> b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
> index 3f7c5b2a4c1..e352508e07e 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrwt.32 q0, \[r0\]
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrwt.32 q0, \[r0\]
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
> b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
> index 2f82228d8f6..13afa92771d 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrht.16 q0, \[r0\]
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrht.16 q0, \[r0\]
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
> b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
> index ba6196b7994..a093cd4b708 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrwt.32 q0, \[r0\]
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrwt.32 q0, \[r0\]
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
> b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
> index 52c8d87ccc8..da4181ff0b7 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrbt.8 q0, \[r0\]
> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrbt.8 q0, \[r0\]
> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
> b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
> index ac89e7ea883..9604fd100e6 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrbt.16 q0, \[r0\]
> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrbt.16 q0, \[r0\]
> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
> b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
> index dc4f7ddab07..07ba37b466c 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrbt.16 q0, \[r0\]
> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrbt.16 q0, \[r0\]
> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
> b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
> index d1dfd328d66..72c1dd5a4d6 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrbt.32 q0, \[r0\]
> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrbt.32 q0, \[r0\]
> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
> b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
> index fa70dde9eeb..3fedc9b98c8 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrbt.32 q0, \[r0\]
> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrbt.32 q0, \[r0\]
> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
> b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
> index 73cd8605171..c3b440c3b6c 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrht.16 q0, \[r0\]
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrht.16 q0, \[r0\]
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
> b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
> index 187c2b3f4ce..5c450b81d1c 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrht.16 q0, \[r0\]
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrht.16 q0, \[r0\]
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
> b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
> index caecd18a881..b5084efcc00 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrht.32 q0, \[r0\]
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrht.32 q0, \[r0\]
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> --
> 2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH 10/10] arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes
2023-04-28 11:30 ` [PATCH 10/10] arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes Andrea Corallo
@ 2023-04-28 16:58 ` Kyrylo Tkachov
2023-05-03 12:34 ` Stamatis Markianos-Wright
0 siblings, 1 reply; 31+ messages in thread
From: Kyrylo Tkachov @ 2023-04-28 16:58 UTC (permalink / raw)
To: Andrea Corallo, gcc-patches; +Cc: Richard Earnshaw, Stam Markianos-Wright
> -----Original Message-----
> From: Andrea Corallo <andrea.corallo@arm.com>
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; Stam Markianos-Wright <Stam.Markianos-
> Wright@arm.com>
> Subject: [PATCH 10/10] arm testsuite: Shifts and get_FPSCR ACLE optimisation
> fixes
>
> From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
>
> These newly updated tests were rewritten by Andrea. Some of them
> needed further manual fixing as follows:
>
> * The #shift immediate value not in the check-function-bodies as expected
> * Some shifts getting optimised to mov immediates, e.g.
> `uqshll (1, 1);` -> movs r0, #2; movs r1, #0
Shouldn't this test be testing something that cannot be constant-folded away? i.e. have non-constant arguments?
I think we should have conformance tests first and foremost, and follow-up tests for such optimisations should be (welcome) added separately.
> * The ACLE was specifying sub-optimal code: lsr+and instead of ubfx. In
> this case the test rewritten from the ACLE had the lsr+and pattern,
> but the compiler was able to optimise to ubfx. Hence I've changed the
> test to now match on ubfx.
That looks ok.
Thanks,
Kyrill
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arm/mve/intrinsics/srshr.c: Update shift value.
> * gcc.target/arm/mve/intrinsics/srshrl.c: Update shift value.
> * gcc.target/arm/mve/intrinsics/uqshl.c: Update shift value and mov
> imm.
> * gcc.target/arm/mve/intrinsics/uqshll.c: Update shift value and mov
> imm.
> * gcc.target/arm/mve/intrinsics/urshr.c: Update shift value.
> * gcc.target/arm/mve/intrinsics/urshrl.c: Update shift value.
> * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Update to ubfx.
> * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Update to ubfx.
> * gcc.target/arm/mve/intrinsics/vadciq_s32.c: Update to ubfx.
> * gcc.target/arm/mve/intrinsics/vadciq_u32.c: Update to ubfx.
> * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Update to ubfx.
> * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Update to ubfx.
> * gcc.target/arm/mve/intrinsics/vadcq_s32.c: Update to ubfx.
> * gcc.target/arm/mve/intrinsics/vadcq_u32.c: Update to ubfx.
> * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Update to ubfx.
> * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Update to ubfx.
> * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Update to ubfx.
> * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Update to ubfx.
> * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Update to ubfx.
> * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Update to ubfx.
> * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Update to ubfx.
> * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Update to ubfx.
> ---
> gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c | 5 +++--
> gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c | 4 ++--
> .../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 8 ++------
> .../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 8 ++------
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c | 8 ++------
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c | 8 ++------
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c | 8 ++------
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c | 8 ++------
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c | 8 ++------
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c | 8 ++------
> .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 8 ++------
> .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 8 ++------
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 8 ++------
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 8 ++------
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 8 ++------
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 8 ++------
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 8 ++------
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 8 ++------
> 22 files changed, 43 insertions(+), 106 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
> index 94e3f42fd33..734375d58c0 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
> @@ -12,7 +12,7 @@ extern "C" {
> /*
> **foo:
> ** ...
> -** srshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> +** srshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
> ** ...
> */
> int32_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
> index 65f28ccbfde..a91943c38a0 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
> @@ -12,7 +12,7 @@ extern "C" {
> /*
> **foo:
> ** ...
> -** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> +** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
> ** ...
> */
> int64_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
> index b23c9d97ba6..58aa7a61e42 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
> @@ -12,7 +12,7 @@ extern "C" {
> /*
> **foo:
> ** ...
> -** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> +** uqshl (?:ip|fp|r[0-9]+), #1(?: @.*|)
> ** ...
> */
> uint32_t
> @@ -24,7 +24,7 @@ foo (uint32_t value)
> /*
> **foo1:
> ** ...
> -** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> +** movs r0, #2
> ** ...
> */
> uint32_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
> index 6a3d08eea75..5584544aaf7 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
> @@ -12,7 +12,7 @@ extern "C" {
> /*
> **foo:
> ** ...
> -** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> +** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
> ** ...
> */
> uint64_t
> @@ -24,7 +24,8 @@ foo (uint64_t value)
> /*
> **foo1:
> ** ...
> -** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> +** movs r0, #2
> +** movs r1, #0
> ** ...
> */
> uint64_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
> index 23afcb8da4c..ff97bf5c473 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
> @@ -12,7 +12,7 @@ extern "C" {
> /*
> **foo:
> ** ...
> -** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> +** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
> ** ...
> */
> uint32_t
> @@ -24,7 +24,7 @@ foo (uint32_t value)
> /*
> **foo1:
> ** ...
> -** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> +** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
> ** ...
> */
> uint32_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
> index 8014371f47f..ff6a69d300f 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
> @@ -12,7 +12,7 @@ extern "C" {
> /*
> **foo:
> ** ...
> -** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> +** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
> ** ...
> */
> uint64_t
> @@ -24,7 +24,7 @@ foo (uint64_t value)
> /*
> **foo1:
> ** ...
> -** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> +** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
> ** ...
> */
> uint64_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
> index b262bf94d39..a6a059a19e9 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
> @@ -20,9 +20,7 @@ extern "C" {
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> int32x4_t
> @@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b,
> unsigned *carry_out, mve_pred
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> int32x4_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
> index d349caed36a..942111339f0 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
> @@ -20,9 +20,7 @@ extern "C" {
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> uint32x4_t
> @@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b,
> unsigned *carry_out, mve_p
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> uint32x4_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
> index 5166993a355..3b68bb6ac33 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
> @@ -16,9 +16,7 @@ extern "C" {
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> int32x4_t
> @@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> int32x4_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
> index 080bd61d238..82228491043 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
> @@ -16,9 +16,7 @@ extern "C" {
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> uint32x4_t
> @@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> uint32x4_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
> index 45e6ff03623..0d4cb779254 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
> @@ -26,9 +26,7 @@ extern "C" {
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> int32x4_t
> @@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b,
> unsigned *carry, mve_pred16_t
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> int32x4_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
> index 54f141b2093..a0ba6825d8c 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
> @@ -26,9 +26,7 @@ extern "C" {
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> uint32x4_t
> @@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b,
> unsigned *carry, mve_pred1
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> uint32x4_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
> index 06d5bae09da..47f5f22dde9 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
> @@ -22,9 +22,7 @@ extern "C" {
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> int32x4_t
> @@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> int32x4_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
> index e2111cfd16a..55a961be217 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
> @@ -22,9 +22,7 @@ extern "C" {
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> uint32x4_t
> @@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> uint32x4_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
> index 66a5c4c9da3..dcbaef1a571 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
> @@ -20,9 +20,7 @@ extern "C" {
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> int32x4_t
> @@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b,
> unsigned *carry_out, mve_pred
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> int32x4_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
> index 9306f152cde..08f67f665c1 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
> @@ -20,9 +20,7 @@ extern "C" {
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> uint32x4_t
> @@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b,
> unsigned *carry_out, mve_p
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> uint32x4_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
> index 0b5040f0b2a..803246c3235 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
> @@ -16,9 +16,7 @@ extern "C" {
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> int32x4_t
> @@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> int32x4_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
> index df211a64daa..22d2b4355bc 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
> @@ -16,9 +16,7 @@ extern "C" {
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> uint32x4_t
> @@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> uint32x4_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
> index 217cfa7ac21..7a332610c69 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
> @@ -26,9 +26,7 @@ extern "C" {
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> int32x4_t
> @@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b,
> unsigned *carry, mve_pred16_t
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> int32x4_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
> index dad04d05d68..60902196502 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
> @@ -26,9 +26,7 @@ extern "C" {
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> uint32x4_t
> @@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b,
> unsigned *carry, mve_pred1
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> uint32x4_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
> index cd033640bcc..523fa32ee0d 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
> @@ -22,9 +22,7 @@ extern "C" {
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> int32x4_t
> @@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> int32x4_t
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
> index 6ca0c753b5e..ff720fd2df5 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
> @@ -22,9 +22,7 @@ extern "C" {
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> uint32x4_t
> @@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> -** ...
> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> */
> uint32x4_t
> --
> 2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 02/10] arm: Fix vstrwq* backend + testsuite
2023-04-28 11:29 ` [PATCH 02/10] arm: Fix vstrwq* backend + testsuite Andrea Corallo
2023-04-28 16:27 ` Kyrylo Tkachov
@ 2023-05-02 8:21 ` Christophe Lyon
2023-05-02 8:45 ` Andrea Corallo
2023-05-02 10:18 ` Andrea Corallo
1 sibling, 2 replies; 31+ messages in thread
From: Christophe Lyon @ 2023-05-02 8:21 UTC (permalink / raw)
To: Andrea Corallo, gcc-patches; +Cc: kyrylo.tkachov, Richard.Earnshaw
Hi Andrea,
Minor comments below:
On 4/28/23 13:29, Andrea Corallo via Gcc-patches wrote:
> Hi all,
>
> this patch fixes the vstrwq* MVE instrinsics failing to emit the
> correct sequence of instruction due to a missing predicates. Also the
nit: you have a typo, should be "predicate"
> immediate range is fixed to be multiples of 2 up between [-252, 252].
Out of curiosity, which tests were affected by this error in the
immediate range?
Thanks,
Christophe
>
> Best Regards
>
> Andrea
>
> gcc/ChangeLog:
>
> * config/arm/constraints.md (mve_vldrd_immediate): Move it to
> predicates.md.
> (Ri): Move constraint definition from predicates.md.
> (Rl): Define new constraint.
> * config/arm/mve.md (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Add
> missing constraint.
> (mve_vstrwq_scatter_base_wb_p_fv4sf): Add missing Up constraint
> for op 1, use mve_vstrw_immediate predicate and Rl constraint for
> op 2. Fix asm output spacing.
> (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Add missing constraint.
> * config/arm/predicates.md (Ri) Move constraint to constraints.md
> (mve_vldrd_immediate): Move it from
> constraints.md.
> (mve_vstrw_immediate): New predicate.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arm/mve/intrinsics/vstrwq_f32.c: Use
> check-function-bodies instead of scan-assembler checks. Use
> extern "C" for C++ testing.
> * gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_u32.c: Likewise.
> ---
> gcc/config/arm/constraints.md | 20 ++++++++--
> gcc/config/arm/mve.md | 10 ++---
> gcc/config/arm/predicates.md | 14 +++----
> .../arm/mve/intrinsics/vstrwq_f32.c | 32 ++++++++++++---
> .../arm/mve/intrinsics/vstrwq_p_f32.c | 40 ++++++++++++++++---
> .../arm/mve/intrinsics/vstrwq_p_s32.c | 40 ++++++++++++++++---
> .../arm/mve/intrinsics/vstrwq_p_u32.c | 40 ++++++++++++++++---
> .../arm/mve/intrinsics/vstrwq_s32.c | 32 ++++++++++++---
> .../mve/intrinsics/vstrwq_scatter_base_f32.c | 28 +++++++++++--
> .../intrinsics/vstrwq_scatter_base_p_f32.c | 36 +++++++++++++++--
> .../intrinsics/vstrwq_scatter_base_p_s32.c | 36 +++++++++++++++--
> .../intrinsics/vstrwq_scatter_base_p_u32.c | 36 +++++++++++++++--
> .../mve/intrinsics/vstrwq_scatter_base_s32.c | 28 +++++++++++--
> .../mve/intrinsics/vstrwq_scatter_base_u32.c | 28 +++++++++++--
> .../intrinsics/vstrwq_scatter_base_wb_f32.c | 32 ++++++++++++---
> .../intrinsics/vstrwq_scatter_base_wb_p_f32.c | 40 ++++++++++++++++---
> .../intrinsics/vstrwq_scatter_base_wb_p_s32.c | 40 ++++++++++++++++---
> .../intrinsics/vstrwq_scatter_base_wb_p_u32.c | 40 ++++++++++++++++---
> .../intrinsics/vstrwq_scatter_base_wb_s32.c | 32 ++++++++++++---
> .../intrinsics/vstrwq_scatter_base_wb_u32.c | 32 ++++++++++++---
> .../intrinsics/vstrwq_scatter_offset_f32.c | 32 ++++++++++++---
> .../intrinsics/vstrwq_scatter_offset_p_f32.c | 40 ++++++++++++++++---
> .../intrinsics/vstrwq_scatter_offset_p_s32.c | 40 ++++++++++++++++---
> .../intrinsics/vstrwq_scatter_offset_p_u32.c | 40 ++++++++++++++++---
> .../intrinsics/vstrwq_scatter_offset_s32.c | 32 ++++++++++++---
> .../intrinsics/vstrwq_scatter_offset_u32.c | 32 ++++++++++++---
> .../vstrwq_scatter_shifted_offset_f32.c | 32 ++++++++++++---
> .../vstrwq_scatter_shifted_offset_p_f32.c | 40 ++++++++++++++++---
> .../vstrwq_scatter_shifted_offset_p_s32.c | 40 ++++++++++++++++---
> .../vstrwq_scatter_shifted_offset_p_u32.c | 40 ++++++++++++++++---
> .../vstrwq_scatter_shifted_offset_s32.c | 32 ++++++++++++---
> .../vstrwq_scatter_shifted_offset_u32.c | 32 ++++++++++++---
> .../arm/mve/intrinsics/vstrwq_u32.c | 32 ++++++++++++---
> 33 files changed, 922 insertions(+), 178 deletions(-)
>
> diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md
> index 504cd938b26..05a4ebbdd67 100644
> --- a/gcc/config/arm/constraints.md
> +++ b/gcc/config/arm/constraints.md
> @@ -102,10 +102,6 @@ (define_constraint "Rg"
> (match_test "TARGET_HAVE_MVE && ((ival == 1) || (ival == 2)
> || (ival == 4) || (ival == 8))")))
>
> -;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE.
> -(define_predicate "mve_vldrd_immediate"
> - (match_test "satisfies_constraint_Ri (op)"))
> -
> (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
> "The VFP registers @code{s0}-@code{s31}.")
>
> @@ -574,6 +570,22 @@ (define_constraint "US"
> (match_code "symbol_ref")
> )
>
> +;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE.
> +(define_constraint "Ri"
> + "@internal In Thumb-2 state a constant is multiple of 8 and in range
> + of -/+ 1016 for MVE"
> + (and (match_code "const_int")
> + (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016)
> + && ((ival % 8) == 0)")))
> +
> +;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE.
> +(define_constraint "Rl"
> + "@internal In Thumb-2 state a constant is multiple of 2 and in range
> + of -/+ 252 for MVE"
> + (and (match_code "const_int")
> + (match_test "TARGET_HAVE_MVE && (-252 <= ival) && (ival <= 252)
> + && ((ival % 2) == 0)")))
> +
> (define_memory_constraint "Uz"
> "@internal
> A memory access that is accessible as an LDC/STC operand"
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> index 35eab6c94bf..161794e470c 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -9359,7 +9359,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_<supf>v4si"
> [(match_operand:V4SI 1 "s_register_operand" "0")
> (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
> (match_operand:V4SI 3 "s_register_operand" "w")
> - (match_operand:V4BI 4 "vpr_register_operand")]
> + (match_operand:V4BI 4 "vpr_register_operand" "Up")]
> VSTRWSBWBQ))
> (set (match_operand:V4SI 0 "s_register_operand" "=w")
> (unspec:V4SI [(match_dup 1) (match_dup 2)]
> @@ -9408,9 +9408,9 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf"
> [(set (mem:BLK (scratch))
> (unspec:BLK
> [(match_operand:V4SI 1 "s_register_operand" "0")
> - (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
> + (match_operand:SI 2 "mve_vstrw_immediate" "Rl")
> (match_operand:V4SF 3 "s_register_operand" "w")
> - (match_operand:V4BI 4 "vpr_register_operand")]
> + (match_operand:V4BI 4 "vpr_register_operand" "Up")]
> VSTRWQSBWB_F))
> (set (match_operand:V4SI 0 "s_register_operand" "=w")
> (unspec:V4SI [(match_dup 1) (match_dup 2)]
> @@ -9422,7 +9422,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf"
> ops[0] = operands[1];
> ops[1] = operands[2];
> ops[2] = operands[3];
> - output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops);
> + output_asm_insn ("vpst\;vstrwt.u32\t%q2, [%q0, %1]!",ops);
> return "";
> }
> [(set_attr "length" "8")])
> @@ -9461,7 +9461,7 @@ (define_insn "mve_vstrdq_scatter_base_wb_p_<supf>v2di"
> [(match_operand:V2DI 1 "s_register_operand" "0")
> (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
> (match_operand:V2DI 3 "s_register_operand" "w")
> - (match_operand:V2QI 4 "vpr_register_operand")]
> + (match_operand:V2QI 4 "vpr_register_operand" "Up")]
> VSTRDSBWBQ))
> (set (match_operand:V2DI 0 "s_register_operand" "=w")
> (unspec:V2DI [(match_dup 1) (match_dup 2)]
> diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
> index 3139750c606..00995a590ab 100644
> --- a/gcc/config/arm/predicates.md
> +++ b/gcc/config/arm/predicates.md
> @@ -73,13 +73,13 @@ (define_predicate "mve_imm_32"
> (define_predicate "mve_imm_selective_upto_8"
> (match_test "satisfies_constraint_Rg (op)"))
>
> -;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE.
> -(define_constraint "Ri"
> - "@internal In Thumb-2 state a constant is multiple of 8 and in range
> - of -/+ 1016 for MVE"
> - (and (match_code "const_int")
> - (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016)
> - && ((ival % 8) == 0)")))
> +;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE.
> +(define_predicate "mve_vldrd_immediate"
> + (match_test "satisfies_constraint_Ri (op)"))
> +
> +;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE.
> +(define_predicate "mve_vstrw_immediate"
> + (match_test "satisfies_constraint_Rl (op)"))
>
> ; Predicate for stack protector guard's address in
> ; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
> index 8aa04fcbdee..e92ecb0f6bc 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * addr, float32x4_t value)
> +foo (float32_t *base, float32x4_t value)
> {
> - vstrwq_f32 (addr, value);
> + return vstrwq_f32 (base, value);
Why do you add "return", since the function is "void" ?
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * addr, float32x4_t value)
> +foo1 (float32_t *base, float32x4_t value)
> {
> - vstrwq (addr, value);
> + return vstrwq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
> index 411de6414f7..f1992a67736 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * addr, float32x4_t value, mve_pred16_t p)
> +foo (float32_t *base, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_p_f32 (addr, value, p);
> + return vstrwq_p_f32 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p)
> +foo1 (float32_t *base, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_p (addr, value, p);
> + return vstrwq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
> index 3b042814d27..a00aeabb9fe 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * addr, int32x4_t value, mve_pred16_t p)
> +foo (int32_t *base, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_p_s32 (addr, value, p);
> + return vstrwq_p_s32 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p)
> +foo1 (int32_t *base, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_p (addr, value, p);
> + return vstrwq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
> index b9e92204c88..05fded8aac8 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
> +foo (uint32_t *base, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_p_u32 (addr, value, p);
> + return vstrwq_p_u32 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
> +foo1 (uint32_t *base, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_p (addr, value, p);
> + return vstrwq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
> index c7b3d91a972..b2a184f3c66 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * addr, int32x4_t value)
> +foo (int32_t *base, int32x4_t value)
> {
> - vstrwq_s32 (addr, value);
> + return vstrwq_s32 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * addr, int32x4_t value)
> +foo1 (int32_t *base, int32x4_t value)
> {
> - vstrwq (addr, value);
> + return vstrwq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
> index f8b56917295..c80e8d9cdc5 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo (uint32x4_t addr, float32x4_t value)
> {
> - vstrwq_scatter_base_f32 (addr, 8, value);
> + return vstrwq_scatter_base_f32 (addr, 0, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo1 (uint32x4_t addr, float32x4_t value)
> {
> - vstrwq_scatter_base (addr, 8, value);
> + return vstrwq_scatter_base (addr, 0, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
> index 4a75e6503e1..237843c0661 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo (uint32x4_t addr, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_p_f32 (addr, 8, value, p);
> + return vstrwq_scatter_base_p_f32 (addr, 0, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo1 (uint32x4_t addr, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_p (addr, 8, value, p);
> + return vstrwq_scatter_base_p (addr, 0, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
> index 5ac4f300a7d..5f4f4a09664 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo (uint32x4_t addr, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_p_s32 (addr, 8, value, p);
> + return vstrwq_scatter_base_p_s32 (addr, 0, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo1 (uint32x4_t addr, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_p (addr, 8, value, p);
> + return vstrwq_scatter_base_p (addr, 0, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
> index e564f26b9c7..8c5cf63f861 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo (uint32x4_t addr, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_p_u32 (addr, 8, value, p);
> + return vstrwq_scatter_base_p_u32 (addr, 0, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo1 (uint32x4_t addr, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_p (addr, 8, value, p);
> + return vstrwq_scatter_base_p (addr, 0, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
> index 5bba36db5cb..5208cf4f808 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo (uint32x4_t addr, int32x4_t value)
> {
> - vstrwq_scatter_base_s32 (addr, 8, value);
> + return vstrwq_scatter_base_s32 (addr, 0, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo1 (uint32x4_t addr, int32x4_t value)
> {
> - vstrwq_scatter_base (addr, 8, value);
> + return vstrwq_scatter_base (addr, 0, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
> index 1dcbb5a739c..e728db2b9f1 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo (uint32x4_t addr, uint32x4_t value)
> {
> - vstrwq_scatter_base_u32 (addr, 8, value);
> + return vstrwq_scatter_base_u32 (addr, 0, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo1 (uint32x4_t addr, uint32x4_t value)
> {
> - vstrwq_scatter_base (addr, 8, value);
> + return vstrwq_scatter_base (addr, 0, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
> index b2cc6e555ae..e481191aa57 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
> @@ -1,19 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32x4_t * addr, const int offset, float32x4_t value)
> +foo (uint32x4_t *addr, float32x4_t value)
> {
> - vstrwq_scatter_base_wb_f32 (addr, 8, value);
> + return vstrwq_scatter_base_wb_f32 (addr, 0, value);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32x4_t * addr, const int offset, float32x4_t value)
> +foo1 (uint32x4_t *addr, float32x4_t value)
> {
> - vstrwq_scatter_base_wb (addr, 8, value);
> + return vstrwq_scatter_base_wb (addr, 0, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c
> index 4befd49d7b9..8d217d46230 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c
> @@ -1,19 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p)
> +foo (uint32x4_t *addr, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_wb_p_f32 (addr, 8, value, p);
> + return vstrwq_scatter_base_wb_p_f32 (addr, 0, value, p);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p)
> +foo1 (uint32x4_t *addr, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_wb_p (addr, 8, value, p);
> + return vstrwq_scatter_base_wb_p (addr, 0, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c
> index dfb1827c4f0..afc47adcd7f 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c
> @@ -1,19 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p)
> +foo (uint32x4_t *addr, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_wb_p_s32 (addr, 8, value, p);
> + return vstrwq_scatter_base_wb_p_s32 (addr, 0, value, p);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p)
> +foo1 (uint32x4_t *addr, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_wb_p (addr, 8, value, p);
> + return vstrwq_scatter_base_wb_p (addr, 0, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c
> index 4eb78c600be..65191c2f1ed 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c
> @@ -1,19 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p)
> +foo (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_wb_p_u32 (addr, 8, value, p);
> + return vstrwq_scatter_base_wb_p_u32 (addr, 0, value, p);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p)
> +foo1 (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_wb_p (addr, 8, value, p);
> + return vstrwq_scatter_base_wb_p (addr, 0, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
> index 618dbaf5aa6..b6a9f6cd1f4 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
> @@ -1,19 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32x4_t * addr, const int offset, int32x4_t value)
> +foo (uint32x4_t *addr, int32x4_t value)
> {
> - vstrwq_scatter_base_wb_s32 (addr, 8, value);
> + return vstrwq_scatter_base_wb_s32 (addr, 0, value);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32x4_t * addr, const int offset, int32x4_t value)
> +foo1 (uint32x4_t *addr, int32x4_t value)
> {
> - vstrwq_scatter_base_wb (addr, 8, value);
> + return vstrwq_scatter_base_wb (addr, 0, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
> index 912a4590cf5..81a278f4e2b 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
> @@ -1,19 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32x4_t * addr, uint32x4_t value)
> +foo (uint32x4_t *addr, uint32x4_t value)
> {
> - vstrwq_scatter_base_wb_u32 (addr, 8, value);
> + return vstrwq_scatter_base_wb_u32 (addr, 0, value);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32x4_t * addr, uint32x4_t value)
> +foo1 (uint32x4_t *addr, uint32x4_t value)
> {
> - vstrwq_scatter_base_wb (addr, 8, value);
> + return vstrwq_scatter_base_wb (addr, 0, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
> index c14d3ce607b..b81df68aa21 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * base, uint32x4_t offset, float32x4_t value)
> +foo (float32_t *base, uint32x4_t offset, float32x4_t value)
> {
> - vstrwq_scatter_offset_f32 (base, offset, value);
> + return vstrwq_scatter_offset_f32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value)
> +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value)
> {
> - vstrwq_scatter_offset (base, offset, value);
> + return vstrwq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
> index 115be56ec00..8aee42f76a3 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> +foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_offset_p_f32 (base, offset, value, p);
> + return vstrwq_scatter_offset_p_f32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_offset_p (base, offset, value, p);
> + return vstrwq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
> index 48652af3cff..9c74ae7a8d8 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> +foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_offset_p_s32 (base, offset, value, p);
> + return vstrwq_scatter_offset_p_s32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_offset_p (base, offset, value, p);
> + return vstrwq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
> index dcd42ec453f..015a202b548 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_offset_p_u32 (base, offset, value, p);
> + return vstrwq_scatter_offset_p_u32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_offset_p (base, offset, value, p);
> + return vstrwq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
> index 04672e5a4aa..df373111b78 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * base, uint32x4_t offset, int32x4_t value)
> +foo (int32_t *base, uint32x4_t offset, int32x4_t value)
> {
> - vstrwq_scatter_offset_s32 (base, offset, value);
> + return vstrwq_scatter_offset_s32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value)
> +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value)
> {
> - vstrwq_scatter_offset (base, offset, value);
> + return vstrwq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
> index e3d312550c6..a74696ca273 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value)
> +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value)
> {
> - vstrwq_scatter_offset_u32 (base, offset, value);
> + return vstrwq_scatter_offset_u32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value)
> +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value)
> {
> - vstrwq_scatter_offset (base, offset, value);
> + return vstrwq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c
> index b20c4c7ed3a..1c9b29a57b8 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * base, uint32x4_t offset, float32x4_t value)
> +foo (float32_t *base, uint32x4_t offset, float32x4_t value)
> {
> - vstrwq_scatter_shifted_offset_f32 (base, offset, value);
> + return vstrwq_scatter_shifted_offset_f32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value)
> +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value)
> {
> - vstrwq_scatter_shifted_offset (base, offset, value);
> + return vstrwq_scatter_shifted_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c
> index 1682f702dc6..08e1572854e 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> +foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p);
> + return vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_shifted_offset_p (base, offset, value, p);
> + return vstrwq_scatter_shifted_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c
> index eef6ea6e196..2b8f8a7d61f 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> +foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p);
> + return vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_shifted_offset_p (base, offset, value, p);
> + return vstrwq_scatter_shifted_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c
> index b11e7e04dc4..3e4e87bf79a 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p);
> + return vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_shifted_offset_p (base, offset, value, p);
> + return vstrwq_scatter_shifted_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c
> index 8ac25c47554..7f25490a69a 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * base, uint32x4_t offset, int32x4_t value)
> +foo (int32_t *base, uint32x4_t offset, int32x4_t value)
> {
> - vstrwq_scatter_shifted_offset_s32 (base, offset, value);
> + return vstrwq_scatter_shifted_offset_s32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value)
> +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value)
> {
> - vstrwq_scatter_shifted_offset (base, offset, value);
> + return vstrwq_scatter_shifted_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c
> index 1ce0ddacc7a..a96220c4f6e 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value)
> +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value)
> {
> - vstrwq_scatter_shifted_offset_u32 (base, offset, value);
> + return vstrwq_scatter_shifted_offset_u32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value)
> +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value)
> {
> - vstrwq_scatter_shifted_offset (base, offset, value);
> + return vstrwq_scatter_shifted_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
> index 4aec9935b84..df554af79a6 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * addr, uint32x4_t value)
> +foo (uint32_t *base, uint32x4_t value)
> {
> - vstrwq_u32 (addr, value);
> + return vstrwq_u32 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * addr, uint32x4_t value)
> +foo1 (uint32_t *base, uint32x4_t value)
> {
> - vstrwq (addr, value);
> + return vstrwq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests
2023-04-28 11:30 ` [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests Andrea Corallo
2023-04-28 16:54 ` Kyrylo Tkachov
@ 2023-05-02 8:28 ` Christophe Lyon
2023-05-02 9:33 ` Stamatis Markianos-Wright
1 sibling, 1 reply; 31+ messages in thread
From: Christophe Lyon @ 2023-05-02 8:28 UTC (permalink / raw)
To: gcc-patches, Stam Markianos-Wright
Cc: kyrylo.tkachov, Richard.Earnshaw, Andrea Corallo
Hi Stam!
On 4/28/23 13:30, Andrea Corallo via Gcc-patches wrote:
> From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
>
> Hi all,
>
> This is a simple testsuite tidy-up patch, addressing to types of errors:
>
> * The vcmp vector-scalar tests failing due to the compiler's preference
> of vector-vector comparisons, over vector-scalar comparisons. This is
> due to the lack of cost model for MVE and the compiler not knowing that
> the RTL vec_duplicate is free in those instructions. For now, we simply
> XFAIL these checks.
> * The tests for pr108177 had strict usage of q0 and r0 registers,
> meaning that they would FAIL with -mfloat-abi=softf. The register checks
Very minor typo: should be "softfp" :-)
Thanks,
Christophe
> have now been relaxed.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arm/mve/intrinsics/srshr.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/srshrl.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/uqshl.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/uqshll.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/urshr.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/urshrl.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vadciq_s32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vadciq_u32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vadcq_s32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vadcq_u32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: XFAIL check.
> * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: XFAIL check.
> * gcc.target/arm/mve/pr108177-1.c: Relax registers.
> * gcc.target/arm/mve/pr108177-10.c: Relax registers.
> * gcc.target/arm/mve/pr108177-11.c: Relax registers.
> * gcc.target/arm/mve/pr108177-12.c: Relax registers.
> * gcc.target/arm/mve/pr108177-13.c: Relax registers.
> * gcc.target/arm/mve/pr108177-14.c: Relax registers.
> * gcc.target/arm/mve/pr108177-2.c: Relax registers.
> * gcc.target/arm/mve/pr108177-3.c: Relax registers.
> * gcc.target/arm/mve/pr108177-4.c: Relax registers.
> * gcc.target/arm/mve/pr108177-5.c: Relax registers.
> * gcc.target/arm/mve/pr108177-6.c: Relax registers.
> * gcc.target/arm/mve/pr108177-7.c: Relax registers.
> * gcc.target/arm/mve/pr108177-8.c: Relax registers.
> * gcc.target/arm/mve/pr108177-9.c: Relax registers.
> ---
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 2 +-
> gcc/testsuite/gcc.target/arm/mve/pr108177-1.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-10.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-11.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-12.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-13.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-14.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-2.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-3.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-4.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-5.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-6.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-7.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-8.c | 4 ++--
> gcc/testsuite/gcc.target/arm/mve/pr108177-9.c | 4 ++--
> 38 files changed, 52 insertions(+), 52 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
> index dc63c527743..9f8111438a1 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
> @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
> index 8c5d185ca22..799d3bcdab1 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
> @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
> index 2296f3e1655..16c3617c104 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
> @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
> index 1d870428c55..2f84d751c53 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
> index 8b8610b0617..6cfe7338fce 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
> index 409c9de58ba..362e830c908 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
> @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
> index c3b1736bfa1..583beb97849 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
> @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
> index 3728c738b54..db7f1877d73 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
> @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
> index 4e9a346ab14..978bd7d4b52 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
> index 2cf1d1ab0b6..66b6d8b0056 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
> index 89d8e2b9109..9c5f1f2f5c8 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
> index 482ac094cf3..2723aa7f98f 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
> index 085b8277736..5712db2ceef 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
> @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
> index a62a73ff24c..f7a25af8574 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
> @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
> index f05c9d24643..8cd28fb1681 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
> @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
> index 4f6276484ba..1d1f4bf0e58 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
> index e71dcb8f174..bf77a808064 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
> index c6fdb08d8ae..f9f091cd9b3 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
> index 4f1ac3c0977..d22ea1aca30 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
> index e36d8a95a85..83beca964d6 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
> index 7262503eee6..abe1abfed2a 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
> index 71d878dff9f..ca55fe2f76c 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
> @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
> index 3f997e8e487..77bac757d68 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
> @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
> index 9917a95ffb7..352afa798d1 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
> @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
> }
>
> /*
> -**foo2:
> +**foo2: { xfail *-*-* }
> ** ...
> ** vcmp.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
> index 2d42062bc8e..8383b4d9e3a 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrbt.8 q0, \[r0\]
> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrbt.8 q0, \[r0\]
> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
> index 4db594f588f..7b1cd3711d8 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrht.32 q0, \[r0\]
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrht.32 q0, \[r0\]
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
> index 329fcb33eeb..e6ae8524052 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrwt.32 q0, \[r0\]
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrwt.32 q0, \[r0\]
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
> index 3f7c5b2a4c1..e352508e07e 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrwt.32 q0, \[r0\]
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrwt.32 q0, \[r0\]
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
> index 2f82228d8f6..13afa92771d 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrht.16 q0, \[r0\]
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrht.16 q0, \[r0\]
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
> index ba6196b7994..a093cd4b708 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrwt.32 q0, \[r0\]
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrwt.32 q0, \[r0\]
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
> index 52c8d87ccc8..da4181ff0b7 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrbt.8 q0, \[r0\]
> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrbt.8 q0, \[r0\]
> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
> index ac89e7ea883..9604fd100e6 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrbt.16 q0, \[r0\]
> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrbt.16 q0, \[r0\]
> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
> index dc4f7ddab07..07ba37b466c 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrbt.16 q0, \[r0\]
> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrbt.16 q0, \[r0\]
> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
> index d1dfd328d66..72c1dd5a4d6 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrbt.32 q0, \[r0\]
> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrbt.32 q0, \[r0\]
> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
> index fa70dde9eeb..3fedc9b98c8 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrbt.32 q0, \[r0\]
> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrbt.32 q0, \[r0\]
> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
> index 73cd8605171..c3b440c3b6c 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrht.16 q0, \[r0\]
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrht.16 q0, \[r0\]
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
> index 187c2b3f4ce..5c450b81d1c 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrht.16 q0, \[r0\]
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrht.16 q0, \[r0\]
> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
> index caecd18a881..b5084efcc00 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
> @@ -7,9 +7,9 @@
> /*
> ** test:
> **...
> -** vstrht.32 q0, \[r0\]
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> -** vstrht.32 q0, \[r0\]
> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
> **...
> */
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 02/10] arm: Fix vstrwq* backend + testsuite
2023-05-02 8:21 ` Christophe Lyon
@ 2023-05-02 8:45 ` Andrea Corallo
2023-05-02 10:18 ` Andrea Corallo
1 sibling, 0 replies; 31+ messages in thread
From: Andrea Corallo @ 2023-05-02 8:45 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches, kyrylo.tkachov, Richard.Earnshaw
Christophe Lyon <christophe.lyon@arm.com> writes:
> Hi Andrea,
>
> Minor comments below:
>
> On 4/28/23 13:29, Andrea Corallo via Gcc-patches wrote:
>> Hi all,
>> this patch fixes the vstrwq* MVE instrinsics failing to emit the
>> correct sequence of instruction due to a missing predicates. Also the
> nit: you have a typo, should be "predicate"
>
>> immediate range is fixed to be multiples of 2 up between [-252, 252].
>
> Out of curiosity, which tests were affected by this error in the
> immediate range?
Hi Christophe,
no special reason, just because the test is autogenerated and we use
this same pattern for all the intrinsics (the vast majority of which do
return a non void type). The test indeed compiles fine so no problem
there.
BR
Andrea
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests
2023-05-02 8:28 ` Christophe Lyon
@ 2023-05-02 9:33 ` Stamatis Markianos-Wright
0 siblings, 0 replies; 31+ messages in thread
From: Stamatis Markianos-Wright @ 2023-05-02 9:33 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
Cc: kyrylo.tkachov, Richard.Earnshaw, Andrea Corallo
On 02/05/2023 09:28, Christophe Lyon wrote:
> Hi Stam!
>
>
> On 4/28/23 13:30, Andrea Corallo via Gcc-patches wrote:
>> From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
>>
>> Hi all,
>>
>> This is a simple testsuite tidy-up patch, addressing to types of errors:
>>
>> * The vcmp vector-scalar tests failing due to the compiler's preference
>> of vector-vector comparisons, over vector-scalar comparisons. This is
>> due to the lack of cost model for MVE and the compiler not knowing that
>> the RTL vec_duplicate is free in those instructions. For now, we simply
>> XFAIL these checks.
>> * The tests for pr108177 had strict usage of q0 and r0 registers,
>> meaning that they would FAIL with -mfloat-abi=softf. The register checks
> Very minor typo: should be "softfp" :-)
Ahh indeed, thanks! Will change this before pushing
>
> Thanks,
>
> Christophe
>
>> have now been relaxed.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/arm/mve/intrinsics/srshr.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/srshrl.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/uqshl.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/uqshll.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/urshr.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/urshrl.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vadciq_s32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vadciq_u32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vadcq_s32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vadcq_u32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: XFAIL check.
>> * gcc.target/arm/mve/pr108177-1.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-10.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-11.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-12.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-13.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-14.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-2.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-3.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-4.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-5.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-6.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-7.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-8.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-9.c: Relax registers.
>> ---
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/pr108177-1.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-10.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-11.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-12.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-13.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-14.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-2.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-3.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-4.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-5.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-6.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-7.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-8.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-9.c | 4 ++--
>> 38 files changed, 52 insertions(+), 52 deletions(-)
>>
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
>> index dc63c527743..9f8111438a1 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
>> @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
>> index 8c5d185ca22..799d3bcdab1 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
>> @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
>> index 2296f3e1655..16c3617c104 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
>> @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
>> index 1d870428c55..2f84d751c53 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
>> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
>> index 8b8610b0617..6cfe7338fce 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
>> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
>> index 409c9de58ba..362e830c908 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
>> @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
>> index c3b1736bfa1..583beb97849 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
>> @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
>> index 3728c738b54..db7f1877d73 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
>> @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
>> index 4e9a346ab14..978bd7d4b52 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
>> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
>> index 2cf1d1ab0b6..66b6d8b0056 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
>> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
>> index 89d8e2b9109..9c5f1f2f5c8 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
>> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
>> index 482ac094cf3..2723aa7f98f 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
>> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
>> index 085b8277736..5712db2ceef 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
>> @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
>> index a62a73ff24c..f7a25af8574 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
>> @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
>> index f05c9d24643..8cd28fb1681 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
>> @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
>> index 4f6276484ba..1d1f4bf0e58 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
>> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
>> index e71dcb8f174..bf77a808064 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
>> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
>> index c6fdb08d8ae..f9f091cd9b3 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
>> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
>> index 4f1ac3c0977..d22ea1aca30 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
>> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
>> index e36d8a95a85..83beca964d6 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
>> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
>> index 7262503eee6..abe1abfed2a 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
>> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
>> index 71d878dff9f..ca55fe2f76c 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
>> @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
>> index 3f997e8e487..77bac757d68 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
>> @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git
>> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
>> index 9917a95ffb7..352afa798d1 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
>> @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
>> }
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
>> index 2d42062bc8e..8383b4d9e3a 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrbt.8 q0, \[r0\]
>> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrbt.8 q0, \[r0\]
>> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
>> index 4db594f588f..7b1cd3711d8 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrht.32 q0, \[r0\]
>> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrht.32 q0, \[r0\]
>> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
>> index 329fcb33eeb..e6ae8524052 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrwt.32 q0, \[r0\]
>> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrwt.32 q0, \[r0\]
>> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
>> index 3f7c5b2a4c1..e352508e07e 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrwt.32 q0, \[r0\]
>> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrwt.32 q0, \[r0\]
>> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
>> index 2f82228d8f6..13afa92771d 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrht.16 q0, \[r0\]
>> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrht.16 q0, \[r0\]
>> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
>> index ba6196b7994..a093cd4b708 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrwt.32 q0, \[r0\]
>> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrwt.32 q0, \[r0\]
>> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
>> index 52c8d87ccc8..da4181ff0b7 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrbt.8 q0, \[r0\]
>> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrbt.8 q0, \[r0\]
>> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
>> index ac89e7ea883..9604fd100e6 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrbt.16 q0, \[r0\]
>> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrbt.16 q0, \[r0\]
>> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
>> index dc4f7ddab07..07ba37b466c 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrbt.16 q0, \[r0\]
>> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrbt.16 q0, \[r0\]
>> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
>> index d1dfd328d66..72c1dd5a4d6 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrbt.32 q0, \[r0\]
>> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrbt.32 q0, \[r0\]
>> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
>> index fa70dde9eeb..3fedc9b98c8 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrbt.32 q0, \[r0\]
>> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrbt.32 q0, \[r0\]
>> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
>> index 73cd8605171..c3b440c3b6c 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrht.16 q0, \[r0\]
>> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrht.16 q0, \[r0\]
>> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
>> index 187c2b3f4ce..5c450b81d1c 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrht.16 q0, \[r0\]
>> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrht.16 q0, \[r0\]
>> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
>> index caecd18a881..b5084efcc00 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrht.32 q0, \[r0\]
>> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrht.32 q0, \[r0\]
>> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 02/10] arm: Fix vstrwq* backend + testsuite
2023-05-02 8:21 ` Christophe Lyon
2023-05-02 8:45 ` Andrea Corallo
@ 2023-05-02 10:18 ` Andrea Corallo
1 sibling, 0 replies; 31+ messages in thread
From: Andrea Corallo @ 2023-05-02 10:18 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches, kyrylo.tkachov, Richard.Earnshaw
Christophe Lyon <christophe.lyon@arm.com> writes:
> Hi Andrea,
>
> Minor comments below:
>
> On 4/28/23 13:29, Andrea Corallo via Gcc-patches wrote:
>> Hi all,
>> this patch fixes the vstrwq* MVE instrinsics failing to emit the
>> correct sequence of instruction due to a missing predicates. Also the
> nit: you have a typo, should be "predicate"
Ack thanks.
>> immediate range is fixed to be multiples of 2 up between [-252, 252].
>
> Out of curiosity, which tests were affected by this error in the
> immediate range?
None I'd say, so far we have no extensive tests checking for immediate
range in the testsuite.
BR
Andrea
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 03/10] arm: Mve backend + testsuite fixes 2
2023-04-28 16:40 ` Kyrylo Tkachov
@ 2023-05-02 11:53 ` Andrea Corallo
0 siblings, 0 replies; 31+ messages in thread
From: Andrea Corallo @ 2023-05-02 11:53 UTC (permalink / raw)
To: Kyrylo Tkachov; +Cc: gcc-patches, Richard Earnshaw
[-- Attachment #1: Type: text/plain, Size: 1196 bytes --]
Kyrylo Tkachov <Kyrylo.Tkachov@arm.com> writes:
> Hi Andrea,
>
>> -----Original Message-----
>> From: Andrea Corallo <andrea.corallo@arm.com>
>> Sent: Friday, April 28, 2023 12:30 PM
>> To: gcc-patches@gcc.gnu.org
>> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
>> <Richard.Earnshaw@arm.com>; Andrea Corallo <Andrea.Corallo@arm.com>
>> Subject: [PATCH 03/10] arm: Mve backend + testsuite fixes 2
>>
>> Hi all,
>>
>> this patch improves a number of MVE tests in the testsuite for more
>> precise and better coverage using check-function-bodies instead of
>> scan-assembler checks. Also all intrusctions prescribed in the
>> ACLE[1] are now checked.
>>
>> Also a number of simple fixes are done in the backend to fix
>> capitalization and spacing.
>
> Looks good,
Hi,
thanks for reviewing.
> but I don't think the original patch made it to the list archives:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-April/thread.html
> You can commit this patch but please resend a compressed form of it to the list for archival.
> Thanks,
> Kyrill
Yes I think it's supposed to be pending for manual moderation.
Please find it attached now in compressed format.
BR
Andrea
[-- Attachment #2: 0003-arm-Mve-backend-testsuite-fixes-2.patch.gz --]
[-- Type: text/plain, Size: 1454437 bytes --]
From df37d75efc02ba3c586bf6f71d322cde3bb0b2c4 Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.corallo@arm.com>
Date: Wed, 19 Apr 2023 18:08:57 +0200
Subject: [PATCH 03/10] arm: Mve backend + testsuite fixes 2
Hi all,
this patch improves a number of MVE tests in the testsuite for more
precise and better coverage using check-function-bodies instead of
scan-assembler checks. Also all intrusctions prescribed in the
ACLE[1] are now checked.
Also a number of simple fixes are done in the backend to fix
capitalization and spacing.
Best Regards
Andrea
[1] <https://github.com/ARM-software/acle>
gcc/ChangeLog:
* config/arm/mve.md (mve_vrndq_m_f<mode>, mve_vrev64q_f<mode>)
(mve_vrev32q_fv8hf, mve_vcvttq_f32_f16v4sf)
(mve_vcvtbq_f32_f16v4sf, mve_vcvtq_to_f_<supf><mode>)
(mve_vrev64q_<supf><mode>, mve_vcvtq_from_f_<supf><mode>)
(mve_vmovltq_<supf><mode>, mve_vmovlbq_<supf><mode>)
(mve_vcvtpq_<supf><mode>, mve_vcvtnq_<supf><mode>)
(mve_vcvtmq_<supf><mode>, mve_vcvtaq_<supf><mode>)
(mve_vmvnq_n_<supf><mode>, mve_vrev16q_<supf>v16qi)
(mve_vctp<MVE_vctp>q<MVE_vpred>, mve_vbrsrq_n_f<mode>)
(mve_vbrsrq_n_<supf><mode>, mve_vandq_f<mode>, mve_vbicq_f<mode>)
(mve_vbicq_n_<supf><mode>, mve_vctp<MVE_vctp>q_m<MVE_vpred>)
(mve_vcvtbq_f16_f32v8hf, mve_vcvttq_f16_f32v8hf)
(mve_veorq_f<mode>, mve_vmlaldavxq_s<mode>, mve_vmlsldavq_s<mode>)
(mve_vmlsldavxq_s<mode>, mve_vornq_f<mode>, mve_vorrq_f<mode>)
(mve_vrmlaldavhxq_sv4si, mve_vbicq_m_n_<supf><mode>)
(mve_vcvtq_m_to_f_<supf><mode>, mve_vshlcq_<supf><mode>)
(mve_vmvnq_m_<supf><mode>, mve_vpselq_<supf><mode>)
(mve_vcvtbq_m_f16_f32v8hf, mve_vcvtbq_m_f32_f16v4sf)
(mve_vcvttq_m_f16_f32v8hf, mve_vcvttq_m_f32_f16v4sf)
(mve_vmlaldavq_p_<supf><mode>, mve_vmlsldavaq_s<mode>)
(mve_vmlsldavaxq_s<mode>, mve_vmlsldavq_p_s<mode>)
(mve_vmlsldavxq_p_s<mode>, mve_vmvnq_m_n_<supf><mode>)
(mve_vorrq_m_n_<supf><mode>, mve_vpselq_f<mode>)
(mve_vrev32q_m_fv8hf, mve_vrev32q_m_<supf><mode>)
(mve_vrev64q_m_f<mode>, mve_vrmlaldavhaxq_sv4si)
(mve_vrmlaldavhxq_p_sv4si, mve_vrmlsldavhaxq_sv4si)
(mve_vrmlsldavhq_p_sv4si, mve_vrmlsldavhxq_p_sv4si)
(mve_vrev16q_m_<supf>v16qi, mve_vrmlaldavhq_p_<supf>v4si)
(mve_vrmlsldavhaq_sv4si, mve_vandq_m_<supf><mode>)
(mve_vbicq_m_<supf><mode>, mve_veorq_m_<supf><mode>)
(mve_vornq_m_<supf><mode>, mve_vorrq_m_<supf><mode>)
(mve_vandq_m_f<mode>, mve_vbicq_m_f<mode>, mve_veorq_m_f<mode>)
(mve_vornq_m_f<mode>, mve_vorrq_m_f<mode>)
(mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn)
(mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn)
(mve_vstrdq_scatter_base_wb_p_<supf>v2di) : Fix spacing and
capitalization in the emitted asm.
gcc/testsuite/ChangeLog:
* gcc.target/arm/mve/intrinsics/asrl.c: Use
check-function-bodies instead of scan-assembler checks. Use
extern "C" for C++ testing.
* gcc.target/arm/mve/intrinsics/lsll.c: Likewise.
* gcc.target/arm/mve/intrinsics/sqrshr.c: Likewise.
* gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c: Likewise.
* gcc.target/arm/mve/intrinsics/sqshl.c: Likewise.
* gcc.target/arm/mve/intrinsics/sqshll.c: Likewise.
* gcc.target/arm/mve/intrinsics/srshr.c: Likewise.
* gcc.target/arm/mve/intrinsics/srshrl.c: Likewise.
* gcc.target/arm/mve/intrinsics/uqrshl.c: Likewise.
* gcc.target/arm/mve/intrinsics/uqrshll_sat48.c: Likewise.
* gcc.target/arm/mve/intrinsics/uqshl.c: Likewise.
* gcc.target/arm/mve/intrinsics/uqshll.c: Likewise.
* gcc.target/arm/mve/intrinsics/urshr.c: Likewise.
* gcc.target/arm/mve/intrinsics/urshrl.c: Likewise.
* gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vadciq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vadciq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vadcq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vadcq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp16q.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp16q_m.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp32q.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp32q_m.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp64q.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp64q_m.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp8q.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp8q_m.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmaq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmaq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmsq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmsq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmladavxq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovnbq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovntq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpnot.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpselq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovntq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshlq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshlq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqsubq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev16q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev16q_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndaq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndaq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndmq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndmq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndnq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndnq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndpq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndpq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndxq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndxq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_m_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_r_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_r_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_r_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_r_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_r_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_r_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsliq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsriq_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c: Likewise.
---
gcc/config/arm/mve.md | 146 +++++++++---------
.../gcc.target/arm/mve/intrinsics/asrl.c | 21 ++-
.../gcc.target/arm/mve/intrinsics/lsll.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/sqrshr.c | 21 ++-
.../arm/mve/intrinsics/sqrshrl_sat48.c | 21 ++-
.../gcc.target/arm/mve/intrinsics/sqshl.c | 21 ++-
.../gcc.target/arm/mve/intrinsics/sqshll.c | 21 ++-
.../gcc.target/arm/mve/intrinsics/srshr.c | 21 ++-
.../gcc.target/arm/mve/intrinsics/srshrl.c | 21 ++-
.../gcc.target/arm/mve/intrinsics/uqrshl.c | 33 +++-
.../arm/mve/intrinsics/uqrshll_sat48.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/uqshl.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/uqshll.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/urshr.c | 35 ++++-
.../gcc.target/arm/mve/intrinsics/urshrl.c | 33 +++-
.../arm/mve/intrinsics/vadciq_m_s32.c | 50 +++++-
.../arm/mve/intrinsics/vadciq_m_u32.c | 50 +++++-
.../arm/mve/intrinsics/vadciq_s32.c | 40 ++++-
.../arm/mve/intrinsics/vadciq_u32.c | 40 ++++-
.../arm/mve/intrinsics/vadcq_m_s32.c | 62 +++++++-
.../arm/mve/intrinsics/vadcq_m_u32.c | 62 +++++++-
.../gcc.target/arm/mve/intrinsics/vadcq_s32.c | 52 ++++++-
.../gcc.target/arm/mve/intrinsics/vadcq_u32.c | 52 ++++++-
.../gcc.target/arm/mve/intrinsics/vandq_f16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vandq_f32.c | 24 ++-
.../arm/mve/intrinsics/vandq_m_f16.c | 34 +++-
.../arm/mve/intrinsics/vandq_m_f32.c | 34 +++-
.../arm/mve/intrinsics/vandq_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vandq_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vandq_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vandq_m_u16.c | 34 +++-
.../arm/mve/intrinsics/vandq_m_u32.c | 34 +++-
.../arm/mve/intrinsics/vandq_m_u8.c | 34 +++-
.../gcc.target/arm/mve/intrinsics/vandq_s16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vandq_s32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vandq_s8.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vandq_u16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vandq_u32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vandq_u8.c | 24 ++-
.../arm/mve/intrinsics/vandq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vandq_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vandq_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vandq_x_s32.c | 33 +++-
.../arm/mve/intrinsics/vandq_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vandq_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vandq_x_u32.c | 33 +++-
.../arm/mve/intrinsics/vandq_x_u8.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/vbicq_f16.c | 23 ++-
.../gcc.target/arm/mve/intrinsics/vbicq_f32.c | 23 ++-
.../arm/mve/intrinsics/vbicq_m_f16.c | 34 +++-
.../arm/mve/intrinsics/vbicq_m_f32.c | 34 +++-
.../arm/mve/intrinsics/vbicq_m_n_s16.c | 37 ++++-
.../arm/mve/intrinsics/vbicq_m_n_s32.c | 33 +++-
.../arm/mve/intrinsics/vbicq_m_n_u16.c | 33 +++-
.../arm/mve/intrinsics/vbicq_m_n_u32.c | 33 +++-
.../arm/mve/intrinsics/vbicq_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vbicq_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vbicq_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vbicq_m_u16.c | 34 +++-
.../arm/mve/intrinsics/vbicq_m_u32.c | 34 +++-
.../arm/mve/intrinsics/vbicq_m_u8.c | 34 +++-
.../arm/mve/intrinsics/vbicq_n_s16.c | 23 ++-
.../arm/mve/intrinsics/vbicq_n_s32.c | 23 ++-
.../arm/mve/intrinsics/vbicq_n_u16.c | 23 ++-
.../arm/mve/intrinsics/vbicq_n_u32.c | 23 ++-
.../gcc.target/arm/mve/intrinsics/vbicq_s16.c | 23 ++-
.../gcc.target/arm/mve/intrinsics/vbicq_s32.c | 23 ++-
.../gcc.target/arm/mve/intrinsics/vbicq_s8.c | 23 ++-
.../gcc.target/arm/mve/intrinsics/vbicq_u16.c | 23 ++-
.../gcc.target/arm/mve/intrinsics/vbicq_u32.c | 23 ++-
.../gcc.target/arm/mve/intrinsics/vbicq_u8.c | 23 ++-
.../arm/mve/intrinsics/vbicq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vbicq_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vbicq_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vbicq_x_s32.c | 33 +++-
.../arm/mve/intrinsics/vbicq_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vbicq_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vbicq_x_u32.c | 33 +++-
.../arm/mve/intrinsics/vbicq_x_u8.c | 33 +++-
.../arm/mve/intrinsics/vbrsrq_m_n_f16.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_m_n_f32.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_m_n_s8.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_m_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_m_n_u8.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_n_f16.c | 24 ++-
.../arm/mve/intrinsics/vbrsrq_n_f32.c | 24 ++-
.../arm/mve/intrinsics/vbrsrq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vbrsrq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vbrsrq_n_s8.c | 24 ++-
.../arm/mve/intrinsics/vbrsrq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vbrsrq_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vbrsrq_n_u8.c | 24 ++-
.../arm/mve/intrinsics/vbrsrq_x_n_f16.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_x_n_f32.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_x_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_x_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_x_n_s8.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_x_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_x_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vbrsrq_x_n_u8.c | 34 +++-
.../arm/mve/intrinsics/vcmpgtq_n_f16.c | 2 +-
.../gcc.target/arm/mve/intrinsics/vctp16q.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/vctp16q_m.c | 42 ++++-
.../gcc.target/arm/mve/intrinsics/vctp32q.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/vctp32q_m.c | 42 ++++-
.../gcc.target/arm/mve/intrinsics/vctp64q.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/vctp64q_m.c | 42 ++++-
.../gcc.target/arm/mve/intrinsics/vctp8q.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/vctp8q_m.c | 42 ++++-
.../arm/mve/intrinsics/vcvtaq_m_s16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtaq_m_s32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtaq_m_u16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtaq_m_u32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtaq_s16_f16.c | 17 +-
.../arm/mve/intrinsics/vcvtaq_s32_f32.c | 17 +-
.../arm/mve/intrinsics/vcvtaq_u16_f16.c | 19 ++-
.../arm/mve/intrinsics/vcvtaq_u32_f32.c | 19 ++-
.../arm/mve/intrinsics/vcvtaq_x_s16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtaq_x_s32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtaq_x_u16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtaq_x_u32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtbq_f16_f32.c | 17 +-
.../arm/mve/intrinsics/vcvtbq_f32_f16.c | 17 +-
.../arm/mve/intrinsics/vcvtbq_m_f16_f32.c | 26 +++-
.../arm/mve/intrinsics/vcvtbq_m_f32_f16.c | 26 +++-
.../arm/mve/intrinsics/vcvtbq_x_f32_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtmq_m_s16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtmq_m_s32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtmq_m_u16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtmq_m_u32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtmq_s16_f16.c | 17 +-
.../arm/mve/intrinsics/vcvtmq_s32_f32.c | 17 +-
.../arm/mve/intrinsics/vcvtmq_u16_f16.c | 19 ++-
.../arm/mve/intrinsics/vcvtmq_u32_f32.c | 19 ++-
.../arm/mve/intrinsics/vcvtmq_x_s16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtmq_x_s32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtmq_x_u16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtmq_x_u32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtnq_m_s16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtnq_m_s32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtnq_m_u16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtnq_m_u32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtnq_s16_f16.c | 17 +-
.../arm/mve/intrinsics/vcvtnq_s32_f32.c | 17 +-
.../arm/mve/intrinsics/vcvtnq_u16_f16.c | 19 ++-
.../arm/mve/intrinsics/vcvtnq_u32_f32.c | 17 +-
.../arm/mve/intrinsics/vcvtnq_x_s16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtnq_x_s32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtnq_x_u16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtnq_x_u32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtpq_m_s16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtpq_m_s32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtpq_m_u16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtpq_m_u32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtpq_s16_f16.c | 17 +-
.../arm/mve/intrinsics/vcvtpq_s32_f32.c | 17 +-
.../arm/mve/intrinsics/vcvtpq_u16_f16.c | 19 ++-
.../arm/mve/intrinsics/vcvtpq_u32_f32.c | 19 ++-
.../arm/mve/intrinsics/vcvtpq_x_s16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtpq_x_s32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtpq_x_u16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtpq_x_u32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtq_f16_s16.c | 30 +++-
.../arm/mve/intrinsics/vcvtq_f16_u16.c | 30 +++-
.../arm/mve/intrinsics/vcvtq_f32_s32.c | 30 +++-
.../arm/mve/intrinsics/vcvtq_f32_u32.c | 30 +++-
.../arm/mve/intrinsics/vcvtq_m_f16_s16.c | 33 +++-
.../arm/mve/intrinsics/vcvtq_m_f16_u16.c | 33 +++-
.../arm/mve/intrinsics/vcvtq_m_f32_s32.c | 33 +++-
.../arm/mve/intrinsics/vcvtq_m_f32_u32.c | 33 +++-
.../arm/mve/intrinsics/vcvtq_m_n_f16_s16.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_m_n_f16_u16.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_m_n_f32_s32.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_m_n_f32_u32.c | 38 ++++-
.../arm/mve/intrinsics/vcvtq_m_n_s16_f16.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_m_n_s32_f32.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_m_n_u16_f16.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_m_n_u32_f32.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_m_s16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtq_m_s32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtq_m_u16_f16.c | 33 +++-
.../arm/mve/intrinsics/vcvtq_m_u32_f32.c | 33 +++-
.../arm/mve/intrinsics/vcvtq_n_f16_s16.c | 24 ++-
.../arm/mve/intrinsics/vcvtq_n_f16_u16.c | 24 ++-
.../arm/mve/intrinsics/vcvtq_n_f32_s32.c | 24 ++-
.../arm/mve/intrinsics/vcvtq_n_f32_u32.c | 24 ++-
.../arm/mve/intrinsics/vcvtq_n_s16_f16.c | 17 +-
.../arm/mve/intrinsics/vcvtq_n_s32_f32.c | 17 +-
.../arm/mve/intrinsics/vcvtq_n_u16_f16.c | 17 +-
.../arm/mve/intrinsics/vcvtq_n_u32_f32.c | 17 +-
.../arm/mve/intrinsics/vcvtq_s16_f16.c | 17 +-
.../arm/mve/intrinsics/vcvtq_s32_f32.c | 17 +-
.../arm/mve/intrinsics/vcvtq_u16_f16.c | 19 ++-
.../arm/mve/intrinsics/vcvtq_u32_f32.c | 19 ++-
.../arm/mve/intrinsics/vcvtq_x_f16_s16.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_x_f16_u16.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_x_f32_s32.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_x_f32_u32.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_x_n_f16_s16.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_x_n_f16_u16.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_x_n_f32_s32.c | 34 +++-
.../arm/mve/intrinsics/vcvtq_x_n_f32_u32.c | 38 ++++-
.../arm/mve/intrinsics/vcvtq_x_n_s16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtq_x_n_s32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtq_x_n_u16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtq_x_n_u32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtq_x_s16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtq_x_s32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvtq_x_u16_f16.c | 22 ++-
.../arm/mve/intrinsics/vcvtq_x_u32_f32.c | 22 ++-
.../arm/mve/intrinsics/vcvttq_f16_f32.c | 17 +-
.../arm/mve/intrinsics/vcvttq_f32_f16.c | 17 +-
.../arm/mve/intrinsics/vcvttq_m_f16_f32.c | 26 +++-
.../arm/mve/intrinsics/vcvttq_m_f32_f16.c | 26 +++-
.../arm/mve/intrinsics/vcvttq_x_f32_f16.c | 22 ++-
.../gcc.target/arm/mve/intrinsics/veorq_f16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/veorq_f32.c | 24 ++-
.../arm/mve/intrinsics/veorq_m_f16.c | 34 +++-
.../arm/mve/intrinsics/veorq_m_f32.c | 34 +++-
.../arm/mve/intrinsics/veorq_m_s16.c | 34 +++-
.../arm/mve/intrinsics/veorq_m_s32.c | 34 +++-
.../arm/mve/intrinsics/veorq_m_s8.c | 34 +++-
.../arm/mve/intrinsics/veorq_m_u16.c | 34 +++-
.../arm/mve/intrinsics/veorq_m_u32.c | 34 +++-
.../arm/mve/intrinsics/veorq_m_u8.c | 34 +++-
.../gcc.target/arm/mve/intrinsics/veorq_s16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/veorq_s32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/veorq_s8.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/veorq_u16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/veorq_u32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/veorq_u8.c | 24 ++-
.../arm/mve/intrinsics/veorq_x_f16.c | 34 +++-
.../arm/mve/intrinsics/veorq_x_f32.c | 34 +++-
.../arm/mve/intrinsics/veorq_x_s16.c | 34 +++-
.../arm/mve/intrinsics/veorq_x_s32.c | 34 +++-
.../arm/mve/intrinsics/veorq_x_s8.c | 34 +++-
.../arm/mve/intrinsics/veorq_x_u16.c | 34 +++-
.../arm/mve/intrinsics/veorq_x_u32.c | 34 +++-
.../arm/mve/intrinsics/veorq_x_u8.c | 34 +++-
.../gcc.target/arm/mve/intrinsics/vfmaq_f16.c | 32 +++-
.../gcc.target/arm/mve/intrinsics/vfmaq_f32.c | 32 +++-
.../arm/mve/intrinsics/vfmaq_m_f16.c | 42 ++++-
.../arm/mve/intrinsics/vfmaq_m_f32.c | 42 ++++-
.../arm/mve/intrinsics/vfmaq_m_n_f16.c | 58 ++++++-
.../arm/mve/intrinsics/vfmaq_m_n_f32.c | 58 ++++++-
.../arm/mve/intrinsics/vfmaq_n_f16.c | 44 +++++-
.../arm/mve/intrinsics/vfmaq_n_f32.c | 44 +++++-
.../arm/mve/intrinsics/vfmasq_m_n_f16.c | 2 +-
.../arm/mve/intrinsics/vfmasq_m_n_f32.c | 2 +-
.../arm/mve/intrinsics/vfmasq_n_f16.c | 44 +++++-
.../arm/mve/intrinsics/vfmasq_n_f32.c | 44 +++++-
.../gcc.target/arm/mve/intrinsics/vfmsq_f16.c | 32 +++-
.../gcc.target/arm/mve/intrinsics/vfmsq_f32.c | 32 +++-
.../arm/mve/intrinsics/vfmsq_m_f16.c | 42 ++++-
.../arm/mve/intrinsics/vfmsq_m_f32.c | 42 ++++-
.../arm/mve/intrinsics/vhcaddq_rot270_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vhcaddq_rot270_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vhcaddq_rot270_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vhcaddq_rot270_s16.c | 24 ++-
.../arm/mve/intrinsics/vhcaddq_rot270_s32.c | 24 ++-
.../arm/mve/intrinsics/vhcaddq_rot270_s8.c | 24 ++-
.../arm/mve/intrinsics/vhcaddq_rot270_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vhcaddq_rot270_x_s32.c | 33 +++-
.../arm/mve/intrinsics/vhcaddq_rot270_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vhcaddq_rot90_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vhcaddq_rot90_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vhcaddq_rot90_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vhcaddq_rot90_s16.c | 24 ++-
.../arm/mve/intrinsics/vhcaddq_rot90_s32.c | 24 ++-
.../arm/mve/intrinsics/vhcaddq_rot90_s8.c | 24 ++-
.../arm/mve/intrinsics/vhcaddq_rot90_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vhcaddq_rot90_x_s32.c | 33 +++-
.../arm/mve/intrinsics/vhcaddq_rot90_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vmladavq_p_s16.c | 40 ++++-
.../arm/mve/intrinsics/vmladavq_p_s32.c | 40 ++++-
.../arm/mve/intrinsics/vmladavq_p_s8.c | 40 ++++-
.../arm/mve/intrinsics/vmladavq_p_u16.c | 40 ++++-
.../arm/mve/intrinsics/vmladavq_p_u32.c | 40 ++++-
.../arm/mve/intrinsics/vmladavq_p_u8.c | 40 ++++-
.../arm/mve/intrinsics/vmladavq_s16.c | 32 +++-
.../arm/mve/intrinsics/vmladavq_s32.c | 32 +++-
.../arm/mve/intrinsics/vmladavq_s8.c | 32 +++-
.../arm/mve/intrinsics/vmladavq_u16.c | 32 +++-
.../arm/mve/intrinsics/vmladavq_u32.c | 32 +++-
.../arm/mve/intrinsics/vmladavq_u8.c | 32 +++-
.../arm/mve/intrinsics/vmladavxq_p_s16.c | 40 ++++-
.../arm/mve/intrinsics/vmladavxq_p_s32.c | 40 ++++-
.../arm/mve/intrinsics/vmladavxq_p_s8.c | 40 ++++-
.../arm/mve/intrinsics/vmladavxq_s16.c | 32 +++-
.../arm/mve/intrinsics/vmladavxq_s32.c | 32 +++-
.../arm/mve/intrinsics/vmladavxq_s8.c | 32 +++-
.../arm/mve/intrinsics/vmlaldavaq_p_s16.c | 40 ++++-
.../arm/mve/intrinsics/vmlaldavaq_p_s32.c | 40 ++++-
.../arm/mve/intrinsics/vmlaldavaq_p_u16.c | 56 ++++++-
.../arm/mve/intrinsics/vmlaldavaq_p_u32.c | 56 ++++++-
.../arm/mve/intrinsics/vmlaldavaq_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlaldavaq_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlaldavaq_u16.c | 44 +++++-
.../arm/mve/intrinsics/vmlaldavaq_u32.c | 44 +++++-
.../arm/mve/intrinsics/vmlaldavaxq_p_s16.c | 2 +-
.../arm/mve/intrinsics/vmlaldavaxq_p_s32.c | 2 +-
.../arm/mve/intrinsics/vmlaldavaxq_s16.c | 2 +-
.../arm/mve/intrinsics/vmlaldavaxq_s32.c | 2 +-
.../arm/mve/intrinsics/vmlaldavq_p_s16.c | 40 ++++-
.../arm/mve/intrinsics/vmlaldavq_p_s32.c | 40 ++++-
.../arm/mve/intrinsics/vmlaldavq_p_u16.c | 40 ++++-
.../arm/mve/intrinsics/vmlaldavq_p_u32.c | 40 ++++-
.../arm/mve/intrinsics/vmlaldavq_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlaldavq_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlaldavq_u16.c | 32 +++-
.../arm/mve/intrinsics/vmlaldavq_u32.c | 32 +++-
.../arm/mve/intrinsics/vmlaldavxq_p_s16.c | 40 ++++-
.../arm/mve/intrinsics/vmlaldavxq_p_s32.c | 40 ++++-
.../arm/mve/intrinsics/vmlaldavxq_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlaldavxq_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlaq_m_n_s16.c | 42 ++++-
.../arm/mve/intrinsics/vmlaq_m_n_s32.c | 42 ++++-
.../arm/mve/intrinsics/vmlaq_m_n_s8.c | 42 ++++-
.../arm/mve/intrinsics/vmlaq_m_n_u16.c | 58 ++++++-
.../arm/mve/intrinsics/vmlaq_m_n_u32.c | 58 ++++++-
.../arm/mve/intrinsics/vmlaq_m_n_u8.c | 58 ++++++-
.../arm/mve/intrinsics/vmlaq_n_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlaq_n_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlaq_n_s8.c | 32 +++-
.../arm/mve/intrinsics/vmlaq_n_u16.c | 44 +++++-
.../arm/mve/intrinsics/vmlaq_n_u32.c | 44 +++++-
.../arm/mve/intrinsics/vmlaq_n_u8.c | 44 +++++-
.../arm/mve/intrinsics/vmlsdavaq_p_s16.c | 33 +++-
.../arm/mve/intrinsics/vmlsdavaq_p_s32.c | 33 +++-
.../arm/mve/intrinsics/vmlsdavaq_p_s8.c | 33 +++-
.../arm/mve/intrinsics/vmlsdavaq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavaq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavaq_s8.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavaxq_p_s16.c | 33 +++-
.../arm/mve/intrinsics/vmlsdavaxq_p_s32.c | 33 +++-
.../arm/mve/intrinsics/vmlsdavaxq_p_s8.c | 33 +++-
.../arm/mve/intrinsics/vmlsdavaxq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavaxq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavaxq_s8.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavq_p_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlsdavq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlsdavq_p_s8.c | 32 +++-
.../arm/mve/intrinsics/vmlsdavq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavq_s8.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavxq_p_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlsdavxq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlsdavxq_p_s8.c | 32 +++-
.../arm/mve/intrinsics/vmlsdavxq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavxq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmlsdavxq_s8.c | 24 ++-
.../arm/mve/intrinsics/vmlsldavaq_p_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlsldavaq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlsldavaq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmlsldavaq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmlsldavaxq_p_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlsldavaxq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlsldavaxq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmlsldavaxq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmlsldavq_p_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlsldavq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlsldavq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmlsldavq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmlsldavxq_p_s16.c | 32 +++-
.../arm/mve/intrinsics/vmlsldavxq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vmlsldavxq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmlsldavxq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmovlbq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vmovlbq_m_s8.c | 33 +++-
.../arm/mve/intrinsics/vmovlbq_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vmovlbq_m_u8.c | 33 +++-
.../arm/mve/intrinsics/vmovlbq_s16.c | 28 +++-
.../arm/mve/intrinsics/vmovlbq_s8.c | 24 ++-
.../arm/mve/intrinsics/vmovlbq_u16.c | 28 +++-
.../arm/mve/intrinsics/vmovlbq_u8.c | 28 +++-
.../arm/mve/intrinsics/vmovlbq_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vmovlbq_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vmovlbq_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vmovlbq_x_u8.c | 33 +++-
.../arm/mve/intrinsics/vmovltq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vmovltq_m_s8.c | 33 +++-
.../arm/mve/intrinsics/vmovltq_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vmovltq_m_u8.c | 33 +++-
.../arm/mve/intrinsics/vmovltq_s16.c | 28 +++-
.../arm/mve/intrinsics/vmovltq_s8.c | 24 ++-
.../arm/mve/intrinsics/vmovltq_u16.c | 28 +++-
.../arm/mve/intrinsics/vmovltq_u8.c | 28 +++-
.../arm/mve/intrinsics/vmovltq_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vmovltq_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vmovltq_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vmovltq_x_u8.c | 33 +++-
.../arm/mve/intrinsics/vmovnbq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vmovnbq_m_s32.c | 33 +++-
.../arm/mve/intrinsics/vmovnbq_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vmovnbq_m_u32.c | 33 +++-
.../arm/mve/intrinsics/vmovnbq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmovnbq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmovnbq_u16.c | 24 ++-
.../arm/mve/intrinsics/vmovnbq_u32.c | 24 ++-
.../arm/mve/intrinsics/vmovntq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vmovntq_m_s32.c | 33 +++-
.../arm/mve/intrinsics/vmovntq_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vmovntq_m_u32.c | 33 +++-
.../arm/mve/intrinsics/vmovntq_s16.c | 24 ++-
.../arm/mve/intrinsics/vmovntq_s32.c | 24 ++-
.../arm/mve/intrinsics/vmovntq_u16.c | 24 ++-
.../arm/mve/intrinsics/vmovntq_u32.c | 24 ++-
.../arm/mve/intrinsics/vmvnq_m_n_s16.c | 37 ++++-
.../arm/mve/intrinsics/vmvnq_m_n_s32.c | 37 ++++-
.../arm/mve/intrinsics/vmvnq_m_n_u16.c | 37 ++++-
.../arm/mve/intrinsics/vmvnq_m_n_u32.c | 37 ++++-
.../arm/mve/intrinsics/vmvnq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vmvnq_m_s32.c | 33 +++-
.../arm/mve/intrinsics/vmvnq_m_s8.c | 33 +++-
.../arm/mve/intrinsics/vmvnq_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vmvnq_m_u32.c | 33 +++-
.../arm/mve/intrinsics/vmvnq_m_u8.c | 33 +++-
.../arm/mve/intrinsics/vmvnq_n_s16.c | 17 +-
.../arm/mve/intrinsics/vmvnq_n_s32.c | 19 ++-
.../arm/mve/intrinsics/vmvnq_n_u16.c | 19 ++-
.../arm/mve/intrinsics/vmvnq_n_u32.c | 19 ++-
.../gcc.target/arm/mve/intrinsics/vmvnq_s16.c | 28 +++-
.../gcc.target/arm/mve/intrinsics/vmvnq_s32.c | 28 +++-
.../gcc.target/arm/mve/intrinsics/vmvnq_s8.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vmvnq_u16.c | 28 +++-
.../gcc.target/arm/mve/intrinsics/vmvnq_u32.c | 28 +++-
.../gcc.target/arm/mve/intrinsics/vmvnq_u8.c | 28 +++-
.../arm/mve/intrinsics/vmvnq_x_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vmvnq_x_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vmvnq_x_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vmvnq_x_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vmvnq_x_s16.c | 34 +++-
.../arm/mve/intrinsics/vmvnq_x_s32.c | 34 +++-
.../arm/mve/intrinsics/vmvnq_x_s8.c | 34 +++-
.../arm/mve/intrinsics/vmvnq_x_u16.c | 34 +++-
.../arm/mve/intrinsics/vmvnq_x_u32.c | 34 +++-
.../arm/mve/intrinsics/vmvnq_x_u8.c | 34 +++-
.../gcc.target/arm/mve/intrinsics/vornq_f16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vornq_f32.c | 24 ++-
.../arm/mve/intrinsics/vornq_m_f16.c | 34 +++-
.../arm/mve/intrinsics/vornq_m_f32.c | 34 +++-
.../arm/mve/intrinsics/vornq_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vornq_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vornq_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vornq_m_u16.c | 34 +++-
.../arm/mve/intrinsics/vornq_m_u32.c | 34 +++-
.../arm/mve/intrinsics/vornq_m_u8.c | 34 +++-
.../gcc.target/arm/mve/intrinsics/vornq_s16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vornq_s32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vornq_s8.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vornq_u16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vornq_u32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vornq_u8.c | 24 ++-
.../arm/mve/intrinsics/vornq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vornq_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vornq_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vornq_x_s32.c | 33 +++-
.../arm/mve/intrinsics/vornq_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vornq_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vornq_x_u32.c | 33 +++-
.../arm/mve/intrinsics/vornq_x_u8.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/vorrq_f16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vorrq_f32.c | 24 ++-
.../arm/mve/intrinsics/vorrq_m_f16.c | 34 +++-
.../arm/mve/intrinsics/vorrq_m_f32.c | 34 +++-
.../arm/mve/intrinsics/vorrq_m_n_s16.c | 37 ++++-
.../arm/mve/intrinsics/vorrq_m_n_s32.c | 33 +++-
.../arm/mve/intrinsics/vorrq_m_n_u16.c | 33 +++-
.../arm/mve/intrinsics/vorrq_m_n_u32.c | 33 +++-
.../arm/mve/intrinsics/vorrq_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vorrq_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vorrq_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vorrq_m_u16.c | 34 +++-
.../arm/mve/intrinsics/vorrq_m_u32.c | 34 +++-
.../arm/mve/intrinsics/vorrq_m_u8.c | 34 +++-
.../arm/mve/intrinsics/vorrq_n_s16.c | 30 +++-
.../arm/mve/intrinsics/vorrq_n_s32.c | 30 +++-
.../arm/mve/intrinsics/vorrq_n_u16.c | 30 +++-
.../arm/mve/intrinsics/vorrq_n_u32.c | 32 +++-
.../gcc.target/arm/mve/intrinsics/vorrq_s16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vorrq_s32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vorrq_s8.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vorrq_u16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vorrq_u32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vorrq_u8.c | 24 ++-
.../arm/mve/intrinsics/vorrq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vorrq_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vorrq_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vorrq_x_s32.c | 33 +++-
.../arm/mve/intrinsics/vorrq_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vorrq_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vorrq_x_u32.c | 33 +++-
.../arm/mve/intrinsics/vorrq_x_u8.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/vpnot.c | 25 ++-
.../arm/mve/intrinsics/vpselq_f16.c | 28 +++-
.../arm/mve/intrinsics/vpselq_f32.c | 28 +++-
.../arm/mve/intrinsics/vpselq_s16.c | 28 +++-
.../arm/mve/intrinsics/vpselq_s32.c | 28 +++-
.../arm/mve/intrinsics/vpselq_s64.c | 28 +++-
.../gcc.target/arm/mve/intrinsics/vpselq_s8.c | 28 +++-
.../arm/mve/intrinsics/vpselq_u16.c | 28 +++-
.../arm/mve/intrinsics/vpselq_u32.c | 28 +++-
.../arm/mve/intrinsics/vpselq_u64.c | 28 +++-
.../gcc.target/arm/mve/intrinsics/vpselq_u8.c | 28 +++-
.../arm/mve/intrinsics/vqmovnbq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vqmovnbq_m_s32.c | 33 +++-
.../arm/mve/intrinsics/vqmovnbq_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vqmovnbq_m_u32.c | 33 +++-
.../arm/mve/intrinsics/vqmovnbq_s16.c | 24 ++-
.../arm/mve/intrinsics/vqmovnbq_s32.c | 24 ++-
.../arm/mve/intrinsics/vqmovnbq_u16.c | 24 ++-
.../arm/mve/intrinsics/vqmovnbq_u32.c | 24 ++-
.../arm/mve/intrinsics/vqmovntq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vqmovntq_m_s32.c | 33 +++-
.../arm/mve/intrinsics/vqmovntq_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vqmovntq_m_u32.c | 33 +++-
.../arm/mve/intrinsics/vqmovntq_s16.c | 24 ++-
.../arm/mve/intrinsics/vqmovntq_s32.c | 24 ++-
.../arm/mve/intrinsics/vqmovntq_u16.c | 24 ++-
.../arm/mve/intrinsics/vqmovntq_u32.c | 24 ++-
.../arm/mve/intrinsics/vqmovunbq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vqmovunbq_m_s32.c | 33 +++-
.../arm/mve/intrinsics/vqmovunbq_s16.c | 24 ++-
.../arm/mve/intrinsics/vqmovunbq_s32.c | 24 ++-
.../arm/mve/intrinsics/vqmovuntq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vqmovuntq_m_s32.c | 33 +++-
.../arm/mve/intrinsics/vqmovuntq_s16.c | 24 ++-
.../arm/mve/intrinsics/vqmovuntq_s32.c | 24 ++-
.../arm/mve/intrinsics/vqrdmladhq_m_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhq_m_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhq_m_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhq_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhq_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhq_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhxq_m_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhxq_m_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhxq_m_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhxq_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhxq_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmladhxq_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmlahq_m_n_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmlahq_m_n_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmlahq_m_n_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmlahq_n_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmlahq_n_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmlahq_n_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmlashq_m_n_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmlashq_m_n_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmlashq_m_n_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmlashq_n_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmlashq_n_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmlashq_n_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhq_m_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhq_m_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhq_m_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhq_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhq_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhq_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhxq_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhxq_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmlsdhxq_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_m_n_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_m_n_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_m_n_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_m_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_m_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_m_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_n_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_n_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_n_s8.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_s16.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_s32.c | 2 +-
.../arm/mve/intrinsics/vqrdmulhq_s8.c | 2 +-
.../arm/mve/intrinsics/vqrshlq_m_n_s16.c | 33 +++-
.../arm/mve/intrinsics/vqrshlq_m_n_s32.c | 33 +++-
.../arm/mve/intrinsics/vqrshlq_m_n_s8.c | 33 +++-
.../arm/mve/intrinsics/vqrshlq_m_n_u16.c | 33 +++-
.../arm/mve/intrinsics/vqrshlq_m_n_u32.c | 33 +++-
.../arm/mve/intrinsics/vqrshlq_m_n_u8.c | 33 +++-
.../arm/mve/intrinsics/vqrshlq_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vqrshlq_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vqrshlq_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vqrshlq_m_u16.c | 34 +++-
.../arm/mve/intrinsics/vqrshlq_m_u32.c | 34 +++-
.../arm/mve/intrinsics/vqrshlq_m_u8.c | 34 +++-
.../arm/mve/intrinsics/vqrshlq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_n_s8.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_n_u8.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_s16.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_s32.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_s8.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_u16.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_u32.c | 24 ++-
.../arm/mve/intrinsics/vqrshlq_u8.c | 24 ++-
.../arm/mve/intrinsics/vqrshrnbq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vqrshrnbq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vqrshrnbq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vqrshrnbq_m_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vqrshrnbq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqrshrnbq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vqrshrnbq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vqrshrnbq_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vqrshrntq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vqrshrntq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vqrshrntq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vqrshrntq_m_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vqrshrntq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqrshrntq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vqrshrntq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vqrshrntq_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vqrshrunbq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vqrshrunbq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vqrshrunbq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqrshrunbq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vqrshruntq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vqrshruntq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vqrshruntq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqrshruntq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_n_s8.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_n_u8.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_r_s16.c | 33 +++-
.../arm/mve/intrinsics/vqshlq_m_r_s32.c | 33 +++-
.../arm/mve/intrinsics/vqshlq_m_r_s8.c | 33 +++-
.../arm/mve/intrinsics/vqshlq_m_r_u16.c | 33 +++-
.../arm/mve/intrinsics/vqshlq_m_r_u32.c | 33 +++-
.../arm/mve/intrinsics/vqshlq_m_r_u8.c | 33 +++-
.../arm/mve/intrinsics/vqshlq_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_u16.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_u32.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_m_u8.c | 34 +++-
.../arm/mve/intrinsics/vqshlq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_n_s8.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_n_u8.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_r_s16.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_r_s32.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_r_s8.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_r_u16.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_r_u32.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_r_u8.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_s16.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_s32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vqshlq_s8.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_u16.c | 24 ++-
.../arm/mve/intrinsics/vqshlq_u32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vqshlq_u8.c | 24 ++-
.../arm/mve/intrinsics/vqshluq_m_n_s16.c | 37 ++++-
.../arm/mve/intrinsics/vqshluq_m_n_s32.c | 37 ++++-
.../arm/mve/intrinsics/vqshluq_m_n_s8.c | 37 ++++-
.../arm/mve/intrinsics/vqshluq_n_s16.c | 28 +++-
.../arm/mve/intrinsics/vqshluq_n_s32.c | 28 +++-
.../arm/mve/intrinsics/vqshluq_n_s8.c | 28 +++-
.../arm/mve/intrinsics/vqshrnbq_m_n_s16.c | 38 ++++-
.../arm/mve/intrinsics/vqshrnbq_m_n_s32.c | 38 ++++-
.../arm/mve/intrinsics/vqshrnbq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vqshrnbq_m_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vqshrnbq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqshrnbq_n_s32.c | 28 +++-
.../arm/mve/intrinsics/vqshrnbq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vqshrnbq_n_u32.c | 28 +++-
.../arm/mve/intrinsics/vqshrntq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vqshrntq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vqshrntq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vqshrntq_m_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vqshrntq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqshrntq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vqshrntq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vqshrntq_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vqshrunbq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vqshrunbq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vqshrunbq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqshrunbq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vqshruntq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vqshruntq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vqshruntq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vqshruntq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vqsubq_m_n_s16.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_n_s32.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_n_s8.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_n_u16.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_n_u32.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_n_u8.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_s16.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_s32.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_s8.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_u16.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_u32.c | 2 +-
.../arm/mve/intrinsics/vqsubq_m_u8.c | 2 +-
.../arm/mve/intrinsics/vqsubq_n_s16.c | 2 +-
.../arm/mve/intrinsics/vqsubq_n_s32.c | 2 +-
.../arm/mve/intrinsics/vqsubq_n_s8.c | 2 +-
.../arm/mve/intrinsics/vqsubq_n_u16.c | 2 +-
.../arm/mve/intrinsics/vqsubq_n_u32.c | 2 +-
.../arm/mve/intrinsics/vqsubq_n_u8.c | 2 +-
.../arm/mve/intrinsics/vqsubq_s16.c | 2 +-
.../arm/mve/intrinsics/vqsubq_s32.c | 2 +-
.../gcc.target/arm/mve/intrinsics/vqsubq_s8.c | 2 +-
.../arm/mve/intrinsics/vqsubq_u16.c | 2 +-
.../arm/mve/intrinsics/vqsubq_u32.c | 2 +-
.../gcc.target/arm/mve/intrinsics/vqsubq_u8.c | 2 +-
.../arm/mve/intrinsics/vrev16q_m_s8.c | 33 +++-
.../arm/mve/intrinsics/vrev16q_m_u8.c | 33 +++-
.../arm/mve/intrinsics/vrev16q_s8.c | 24 ++-
.../arm/mve/intrinsics/vrev16q_u8.c | 28 +++-
.../arm/mve/intrinsics/vrev16q_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vrev16q_x_u8.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_f16.c | 30 +++-
.../arm/mve/intrinsics/vrev32q_m_f16.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_m_s8.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_m_u8.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_s16.c | 28 +++-
.../arm/mve/intrinsics/vrev32q_s8.c | 24 ++-
.../arm/mve/intrinsics/vrev32q_u16.c | 28 +++-
.../arm/mve/intrinsics/vrev32q_u8.c | 28 +++-
.../arm/mve/intrinsics/vrev32q_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vrev32q_x_u8.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_f16.c | 30 +++-
.../arm/mve/intrinsics/vrev64q_f32.c | 30 +++-
.../arm/mve/intrinsics/vrev64q_m_f16.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_m_f32.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_m_s32.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_m_s8.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_m_u32.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_m_u8.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_s16.c | 24 ++-
.../arm/mve/intrinsics/vrev64q_s32.c | 24 ++-
.../arm/mve/intrinsics/vrev64q_s8.c | 24 ++-
.../arm/mve/intrinsics/vrev64q_u16.c | 28 +++-
.../arm/mve/intrinsics/vrev64q_u32.c | 28 +++-
.../arm/mve/intrinsics/vrev64q_u8.c | 28 +++-
.../arm/mve/intrinsics/vrev64q_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_x_s32.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_x_u32.c | 33 +++-
.../arm/mve/intrinsics/vrev64q_x_u8.c | 33 +++-
.../arm/mve/intrinsics/vrhaddq_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vrhaddq_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vrhaddq_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vrhaddq_m_u16.c | 34 +++-
.../arm/mve/intrinsics/vrhaddq_m_u32.c | 34 +++-
.../arm/mve/intrinsics/vrhaddq_m_u8.c | 34 +++-
.../arm/mve/intrinsics/vrhaddq_s16.c | 24 ++-
.../arm/mve/intrinsics/vrhaddq_s32.c | 24 ++-
.../arm/mve/intrinsics/vrhaddq_s8.c | 24 ++-
.../arm/mve/intrinsics/vrhaddq_u16.c | 24 ++-
.../arm/mve/intrinsics/vrhaddq_u32.c | 24 ++-
.../arm/mve/intrinsics/vrhaddq_u8.c | 24 ++-
.../arm/mve/intrinsics/vrhaddq_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vrhaddq_x_s32.c | 33 +++-
.../arm/mve/intrinsics/vrhaddq_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vrhaddq_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vrhaddq_x_u32.c | 33 +++-
.../arm/mve/intrinsics/vrhaddq_x_u8.c | 33 +++-
.../arm/mve/intrinsics/vrmlaldavhaq_p_s32.c | 2 +-
.../arm/mve/intrinsics/vrmlaldavhaq_p_u32.c | 2 +-
.../arm/mve/intrinsics/vrmlaldavhaq_s32.c | 2 +-
.../arm/mve/intrinsics/vrmlaldavhaq_u32.c | 2 +-
.../arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vrmlaldavhaxq_s32.c | 24 ++-
.../arm/mve/intrinsics/vrmlaldavhq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vrmlaldavhq_p_u32.c | 32 +++-
.../arm/mve/intrinsics/vrmlaldavhq_s32.c | 24 ++-
.../arm/mve/intrinsics/vrmlaldavhq_u32.c | 24 ++-
.../arm/mve/intrinsics/vrmlaldavhxq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vrmlaldavhxq_s32.c | 24 ++-
.../arm/mve/intrinsics/vrmlsldavhaq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vrmlsldavhaq_s32.c | 24 ++-
.../arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vrmlsldavhaxq_s32.c | 24 ++-
.../arm/mve/intrinsics/vrmlsldavhq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vrmlsldavhq_s32.c | 24 ++-
.../arm/mve/intrinsics/vrmlsldavhxq_p_s32.c | 32 +++-
.../arm/mve/intrinsics/vrmlsldavhxq_s32.c | 24 ++-
.../arm/mve/intrinsics/vrmulhq_m_s16.c | 34 +++-
.../arm/mve/intrinsics/vrmulhq_m_s32.c | 34 +++-
.../arm/mve/intrinsics/vrmulhq_m_s8.c | 34 +++-
.../arm/mve/intrinsics/vrmulhq_m_u16.c | 34 +++-
.../arm/mve/intrinsics/vrmulhq_m_u32.c | 34 +++-
.../arm/mve/intrinsics/vrmulhq_m_u8.c | 34 +++-
.../arm/mve/intrinsics/vrmulhq_s16.c | 24 ++-
.../arm/mve/intrinsics/vrmulhq_s32.c | 24 ++-
.../arm/mve/intrinsics/vrmulhq_s8.c | 24 ++-
.../arm/mve/intrinsics/vrmulhq_u16.c | 24 ++-
.../arm/mve/intrinsics/vrmulhq_u32.c | 24 ++-
.../arm/mve/intrinsics/vrmulhq_u8.c | 24 ++-
.../arm/mve/intrinsics/vrmulhq_x_s16.c | 33 +++-
.../arm/mve/intrinsics/vrmulhq_x_s32.c | 33 +++-
.../arm/mve/intrinsics/vrmulhq_x_s8.c | 33 +++-
.../arm/mve/intrinsics/vrmulhq_x_u16.c | 33 +++-
.../arm/mve/intrinsics/vrmulhq_x_u32.c | 33 +++-
.../arm/mve/intrinsics/vrmulhq_x_u8.c | 33 +++-
.../arm/mve/intrinsics/vrndaq_f16.c | 30 +++-
.../arm/mve/intrinsics/vrndaq_f32.c | 30 +++-
.../arm/mve/intrinsics/vrndaq_m_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndaq_m_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndaq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndaq_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndmq_f16.c | 30 +++-
.../arm/mve/intrinsics/vrndmq_f32.c | 30 +++-
.../arm/mve/intrinsics/vrndmq_m_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndmq_m_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndmq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndmq_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndnq_f16.c | 30 +++-
.../arm/mve/intrinsics/vrndnq_f32.c | 30 +++-
.../arm/mve/intrinsics/vrndnq_m_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndnq_m_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndnq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndnq_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndpq_f16.c | 30 +++-
.../arm/mve/intrinsics/vrndpq_f32.c | 30 +++-
.../arm/mve/intrinsics/vrndpq_m_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndpq_m_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndpq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndpq_x_f32.c | 33 +++-
.../gcc.target/arm/mve/intrinsics/vrndq_f16.c | 30 +++-
.../gcc.target/arm/mve/intrinsics/vrndq_f32.c | 30 +++-
.../arm/mve/intrinsics/vrndq_m_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndq_m_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndq_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndxq_f16.c | 30 +++-
.../arm/mve/intrinsics/vrndxq_f32.c | 30 +++-
.../arm/mve/intrinsics/vrndxq_m_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndxq_m_f32.c | 33 +++-
.../arm/mve/intrinsics/vrndxq_x_f16.c | 33 +++-
.../arm/mve/intrinsics/vrndxq_x_f32.c | 33 +++-
.../arm/mve/intrinsics/vrshrnbq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vrshrnbq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vrshrnbq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vrshrnbq_m_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vrshrnbq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vrshrnbq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vrshrnbq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vrshrnbq_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vrshrntq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vrshrntq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vrshrntq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vrshrntq_m_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vrshrntq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vrshrntq_n_s32.c | 24 ++-
.../arm/mve/intrinsics/vrshrntq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vrshrntq_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vrshrq_m_n_s16.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_m_n_s32.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_m_n_s8.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_m_n_u16.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_m_n_u32.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_m_n_u8.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_n_s16.c | 28 +++-
.../arm/mve/intrinsics/vrshrq_n_s32.c | 28 +++-
.../arm/mve/intrinsics/vrshrq_n_s8.c | 28 +++-
.../arm/mve/intrinsics/vrshrq_n_u16.c | 28 +++-
.../arm/mve/intrinsics/vrshrq_n_u32.c | 28 +++-
.../arm/mve/intrinsics/vrshrq_n_u8.c | 28 +++-
.../arm/mve/intrinsics/vrshrq_x_n_s16.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_x_n_s32.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_x_n_s8.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_x_n_u16.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_x_n_u32.c | 38 ++++-
.../arm/mve/intrinsics/vrshrq_x_n_u8.c | 38 ++++-
.../arm/mve/intrinsics/vsbciq_m_s32.c | 50 +++++-
.../arm/mve/intrinsics/vsbciq_m_u32.c | 50 +++++-
.../arm/mve/intrinsics/vsbciq_s32.c | 42 ++++-
.../arm/mve/intrinsics/vsbciq_u32.c | 42 ++++-
.../arm/mve/intrinsics/vsbcq_m_s32.c | 66 +++++++-
.../arm/mve/intrinsics/vsbcq_m_u32.c | 67 +++++++-
.../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 52 ++++++-
.../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 52 ++++++-
.../arm/mve/intrinsics/vshlcq_m_s16.c | 42 ++++-
.../arm/mve/intrinsics/vshlcq_m_s32.c | 38 ++++-
.../arm/mve/intrinsics/vshlcq_m_s8.c | 38 ++++-
.../arm/mve/intrinsics/vshlcq_m_u16.c | 38 ++++-
.../arm/mve/intrinsics/vshlcq_m_u32.c | 38 ++++-
.../arm/mve/intrinsics/vshlcq_m_u8.c | 38 ++++-
.../arm/mve/intrinsics/vshlcq_s16.c | 28 +++-
.../arm/mve/intrinsics/vshlcq_s32.c | 28 +++-
.../gcc.target/arm/mve/intrinsics/vshlcq_s8.c | 28 +++-
.../arm/mve/intrinsics/vshlcq_u16.c | 28 +++-
.../arm/mve/intrinsics/vshlcq_u32.c | 28 +++-
.../gcc.target/arm/mve/intrinsics/vshlcq_u8.c | 28 +++-
.../arm/mve/intrinsics/vshllbq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vshllbq_m_n_s8.c | 34 +++-
.../arm/mve/intrinsics/vshllbq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vshllbq_m_n_u8.c | 34 +++-
.../arm/mve/intrinsics/vshllbq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vshllbq_n_s8.c | 24 ++-
.../arm/mve/intrinsics/vshllbq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vshllbq_n_u8.c | 24 ++-
.../arm/mve/intrinsics/vshllbq_x_n_s16.c | 40 ++++-
.../arm/mve/intrinsics/vshllbq_x_n_s8.c | 40 ++++-
.../arm/mve/intrinsics/vshllbq_x_n_u16.c | 40 ++++-
.../arm/mve/intrinsics/vshllbq_x_n_u8.c | 40 ++++-
.../arm/mve/intrinsics/vshlltq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vshlltq_m_n_s8.c | 34 +++-
.../arm/mve/intrinsics/vshlltq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vshlltq_m_n_u8.c | 34 +++-
.../arm/mve/intrinsics/vshlltq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vshlltq_n_s8.c | 24 ++-
.../arm/mve/intrinsics/vshlltq_n_u16.c | 24 ++-
.../arm/mve/intrinsics/vshlltq_n_u8.c | 24 ++-
.../arm/mve/intrinsics/vshlltq_x_n_s16.c | 40 ++++-
.../arm/mve/intrinsics/vshlltq_x_n_s8.c | 40 ++++-
.../arm/mve/intrinsics/vshlltq_x_n_u16.c | 40 ++++-
.../arm/mve/intrinsics/vshlltq_x_n_u8.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_m_n_s16.c | 34 +++-
.../arm/mve/intrinsics/vshlq_m_n_s32.c | 34 +++-
.../arm/mve/intrinsics/vshlq_m_n_s8.c | 34 +++-
.../arm/mve/intrinsics/vshlq_m_n_u16.c | 34 +++-
.../arm/mve/intrinsics/vshlq_m_n_u32.c | 34 +++-
.../arm/mve/intrinsics/vshlq_m_n_u8.c | 34 +++-
.../arm/mve/intrinsics/vshlq_m_r_s16.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_r_s32.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_r_s8.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_r_u16.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_r_u32.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_r_u8.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_s16.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_s32.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_s8.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_u16.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_u32.c | 33 +++-
.../arm/mve/intrinsics/vshlq_m_u8.c | 33 +++-
.../arm/mve/intrinsics/vshlq_n_s16.c | 24 ++-
.../arm/mve/intrinsics/vshlq_n_s32.c | 28 +++-
.../arm/mve/intrinsics/vshlq_n_s8.c | 24 ++-
.../arm/mve/intrinsics/vshlq_n_u16.c | 28 +++-
.../arm/mve/intrinsics/vshlq_n_u32.c | 24 ++-
.../arm/mve/intrinsics/vshlq_n_u8.c | 24 ++-
.../arm/mve/intrinsics/vshlq_r_s16.c | 24 ++-
.../arm/mve/intrinsics/vshlq_r_s32.c | 24 ++-
.../arm/mve/intrinsics/vshlq_r_s8.c | 24 ++-
.../arm/mve/intrinsics/vshlq_r_u16.c | 24 ++-
.../arm/mve/intrinsics/vshlq_r_u32.c | 24 ++-
.../arm/mve/intrinsics/vshlq_r_u8.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vshlq_s16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vshlq_s32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vshlq_s8.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vshlq_u16.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vshlq_u32.c | 24 ++-
.../gcc.target/arm/mve/intrinsics/vshlq_u8.c | 24 ++-
.../arm/mve/intrinsics/vshlq_x_n_s16.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_n_s32.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_n_s8.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_n_u16.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_n_u32.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_n_u8.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_s16.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_s32.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_s8.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_u16.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_u32.c | 40 ++++-
.../arm/mve/intrinsics/vshlq_x_u8.c | 40 ++++-
.../arm/mve/intrinsics/vshrnbq_m_n_s16.c | 38 ++++-
.../arm/mve/intrinsics/vshrnbq_m_n_s32.c | 38 ++++-
.../arm/mve/intrinsics/vshrnbq_m_n_u16.c | 38 ++++-
.../arm/mve/intrinsics/vshrnbq_m_n_u32.c | 38 ++++-
.../arm/mve/intrinsics/vshrnbq_n_s16.c | 28 +++-
.../arm/mve/intrinsics/vshrnbq_n_s32.c | 28 +++-
.../arm/mve/intrinsics/vshrnbq_n_u16.c | 28 +++-
.../arm/mve/intrinsics/vshrnbq_n_u32.c | 28 +++-
.../arm/mve/intrinsics/vshrntq_m_n_s16.c | 38 ++++-
.../arm/mve/intrinsics/vshrntq_m_n_s32.c | 38 ++++-
.../arm/mve/intrinsics/vshrntq_m_n_u16.c | 38 ++++-
.../arm/mve/intrinsics/vshrntq_m_n_u32.c | 38 ++++-
.../arm/mve/intrinsics/vshrntq_n_s16.c | 28 +++-
.../arm/mve/intrinsics/vshrntq_n_s32.c | 28 +++-
.../arm/mve/intrinsics/vshrntq_n_u16.c | 28 +++-
.../arm/mve/intrinsics/vshrntq_n_u32.c | 28 +++-
.../arm/mve/intrinsics/vshrq_m_n_s16.c | 38 ++++-
.../arm/mve/intrinsics/vshrq_m_n_s32.c | 38 ++++-
.../arm/mve/intrinsics/vshrq_m_n_s8.c | 38 ++++-
.../arm/mve/intrinsics/vshrq_m_n_u16.c | 38 ++++-
.../arm/mve/intrinsics/vshrq_m_n_u32.c | 38 ++++-
.../arm/mve/intrinsics/vshrq_m_n_u8.c | 38 ++++-
.../arm/mve/intrinsics/vshrq_n_s16.c | 28 +++-
.../arm/mve/intrinsics/vshrq_n_s32.c | 28 +++-
.../arm/mve/intrinsics/vshrq_n_s8.c | 28 +++-
.../arm/mve/intrinsics/vshrq_n_u16.c | 28 +++-
.../arm/mve/intrinsics/vshrq_n_u32.c | 28 +++-
.../arm/mve/intrinsics/vshrq_n_u8.c | 28 +++-
.../arm/mve/intrinsics/vshrq_x_n_s16.c | 40 ++++-
.../arm/mve/intrinsics/vshrq_x_n_s32.c | 40 ++++-
.../arm/mve/intrinsics/vshrq_x_n_s8.c | 40 ++++-
.../arm/mve/intrinsics/vshrq_x_n_u16.c | 40 ++++-
.../arm/mve/intrinsics/vshrq_x_n_u8.c | 40 ++++-
.../arm/mve/intrinsics/vsliq_m_n_s16.c | 38 ++++-
.../arm/mve/intrinsics/vsliq_m_n_s32.c | 38 ++++-
.../arm/mve/intrinsics/vsliq_m_n_s8.c | 38 ++++-
.../arm/mve/intrinsics/vsliq_m_n_u16.c | 38 ++++-
.../arm/mve/intrinsics/vsliq_m_n_u32.c | 38 ++++-
.../arm/mve/intrinsics/vsliq_m_n_u8.c | 38 ++++-
.../arm/mve/intrinsics/vsliq_n_s16.c | 28 +++-
.../arm/mve/intrinsics/vsliq_n_s32.c | 28 +++-
.../arm/mve/intrinsics/vsliq_n_s8.c | 28 +++-
.../arm/mve/intrinsics/vsliq_n_u16.c | 28 +++-
.../arm/mve/intrinsics/vsliq_n_u32.c | 28 +++-
.../arm/mve/intrinsics/vsliq_n_u8.c | 28 +++-
.../arm/mve/intrinsics/vsriq_m_n_s16.c | 37 ++++-
.../arm/mve/intrinsics/vsriq_m_n_s32.c | 37 ++++-
.../arm/mve/intrinsics/vsriq_m_n_s8.c | 37 ++++-
.../arm/mve/intrinsics/vsriq_m_n_u16.c | 37 ++++-
.../arm/mve/intrinsics/vsriq_m_n_u32.c | 37 ++++-
.../arm/mve/intrinsics/vsriq_m_n_u8.c | 37 ++++-
.../arm/mve/intrinsics/vsriq_n_s16.c | 28 +++-
.../arm/mve/intrinsics/vsriq_n_s32.c | 28 +++-
.../arm/mve/intrinsics/vsriq_n_s8.c | 28 +++-
.../arm/mve/intrinsics/vsriq_n_u16.c | 28 +++-
.../arm/mve/intrinsics/vsriq_n_u32.c | 28 +++-
.../arm/mve/intrinsics/vsriq_n_u8.c | 28 +++-
.../gcc.target/arm/mve/intrinsics/vst1q_f16.c | 36 +++--
.../gcc.target/arm/mve/intrinsics/vst1q_f32.c | 32 +++-
.../arm/mve/intrinsics/vst1q_p_f16.c | 40 ++++-
.../arm/mve/intrinsics/vst1q_p_f32.c | 40 ++++-
.../arm/mve/intrinsics/vst1q_p_s16.c | 40 ++++-
.../arm/mve/intrinsics/vst1q_p_s32.c | 40 ++++-
.../arm/mve/intrinsics/vst1q_p_s8.c | 40 ++++-
.../arm/mve/intrinsics/vst1q_p_u16.c | 40 ++++-
.../arm/mve/intrinsics/vst1q_p_u32.c | 40 ++++-
.../arm/mve/intrinsics/vst1q_p_u8.c | 40 ++++-
.../gcc.target/arm/mve/intrinsics/vst1q_s16.c | 36 +++--
.../gcc.target/arm/mve/intrinsics/vst1q_s32.c | 32 +++-
.../gcc.target/arm/mve/intrinsics/vst1q_s8.c | 36 +++--
.../gcc.target/arm/mve/intrinsics/vst1q_u16.c | 36 +++--
.../gcc.target/arm/mve/intrinsics/vst1q_u32.c | 32 +++-
.../gcc.target/arm/mve/intrinsics/vst1q_u8.c | 36 +++--
.../intrinsics/vstrdq_scatter_base_p_s64.c | 40 ++++-
.../intrinsics/vstrdq_scatter_base_p_u64.c | 40 ++++-
.../mve/intrinsics/vstrdq_scatter_base_s64.c | 32 +++-
.../mve/intrinsics/vstrdq_scatter_base_u64.c | 32 +++-
.../intrinsics/vstrdq_scatter_base_wb_p_s64.c | 40 ++++-
.../intrinsics/vstrdq_scatter_base_wb_p_u64.c | 40 ++++-
.../intrinsics/vstrdq_scatter_base_wb_s64.c | 32 +++-
.../intrinsics/vstrdq_scatter_base_wb_u64.c | 32 +++-
.../intrinsics/vstrdq_scatter_offset_p_s64.c | 40 ++++-
.../intrinsics/vstrdq_scatter_offset_p_u64.c | 40 ++++-
.../intrinsics/vstrdq_scatter_offset_s64.c | 32 +++-
.../intrinsics/vstrdq_scatter_offset_u64.c | 32 +++-
.../vstrdq_scatter_shifted_offset_p_s64.c | 40 ++++-
.../vstrdq_scatter_shifted_offset_p_u64.c | 40 ++++-
.../vstrdq_scatter_shifted_offset_s64.c | 32 +++-
.../vstrdq_scatter_shifted_offset_u64.c | 32 +++-
1069 files changed, 27457 insertions(+), 3534 deletions(-)
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 161794e470c..5adbbb3bff6 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -141,7 +141,7 @@ (define_insn "mve_vrndq_m_f<mode>"
VRNDQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vrintzt.f%#<V_sz_elem> %q0, %q2"
+ "vpst\;vrintzt.f%#<V_sz_elem>\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -239,7 +239,7 @@ (define_insn "mve_vrev64q_f<mode>"
VREV64Q_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vrev64.%#<V_sz_elem> %q0, %q1"
+ "vrev64.%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -293,7 +293,7 @@ (define_insn "mve_vrev32q_fv8hf"
VREV32Q_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vrev32.16 %q0, %q1"
+ "vrev32.16\t%q0, %q1"
[(set_attr "type" "mve_move")
])
;;
@@ -306,7 +306,7 @@ (define_insn "mve_vcvttq_f32_f16v4sf"
VCVTTQ_F32_F16))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvtt.f32.f16 %q0, %q1"
+ "vcvtt.f32.f16\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -320,7 +320,7 @@ (define_insn "mve_vcvtbq_f32_f16v4sf"
VCVTBQ_F32_F16))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvtb.f32.f16 %q0, %q1"
+ "vcvtb.f32.f16\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -334,7 +334,7 @@ (define_insn "mve_vcvtq_to_f_<supf><mode>"
VCVTQ_TO_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q1"
+ "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -348,7 +348,7 @@ (define_insn "mve_vrev64q_<supf><mode>"
VREV64Q))
]
"TARGET_HAVE_MVE"
- "vrev64.%#<V_sz_elem> %q0, %q1"
+ "vrev64.%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -362,7 +362,7 @@ (define_insn "mve_vcvtq_from_f_<supf><mode>"
VCVTQ_FROM_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
+ "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
;; [vqnegq_s])
@@ -524,7 +524,7 @@ (define_insn "mve_vmovltq_<supf><mode>"
VMOVLTQ))
]
"TARGET_HAVE_MVE"
- "vmovlt.<supf>%#<V_sz_elem> %q0, %q1"
+ "vmovlt.<supf>%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -538,7 +538,7 @@ (define_insn "mve_vmovlbq_<supf><mode>"
VMOVLBQ))
]
"TARGET_HAVE_MVE"
- "vmovlb.<supf>%#<V_sz_elem> %q0, %q1"
+ "vmovlb.<supf>%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -552,7 +552,7 @@ (define_insn "mve_vcvtpq_<supf><mode>"
VCVTPQ))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
+ "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -566,7 +566,7 @@ (define_insn "mve_vcvtnq_<supf><mode>"
VCVTNQ))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
+ "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -580,7 +580,7 @@ (define_insn "mve_vcvtmq_<supf><mode>"
VCVTMQ))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
+ "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -594,7 +594,7 @@ (define_insn "mve_vcvtaq_<supf><mode>"
VCVTAQ))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem> %q0, %q1"
+ "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -608,7 +608,7 @@ (define_insn "mve_vmvnq_n_<supf><mode>"
VMVNQ_N))
]
"TARGET_HAVE_MVE"
- "vmvn.i%#<V_sz_elem> %q0, %1"
+ "vmvn.i%#<V_sz_elem>\t%q0, %1"
[(set_attr "type" "mve_move")
])
@@ -622,7 +622,7 @@ (define_insn "mve_vrev16q_<supf>v16qi"
VREV16Q))
]
"TARGET_HAVE_MVE"
- "vrev16.8 %q0, %q1"
+ "vrev16.8\t%q0, %q1"
[(set_attr "type" "mve_move")
])
@@ -650,7 +650,7 @@ (define_insn "mve_vctp<MVE_vctp>q<MVE_vpred>"
VCTP))
]
"TARGET_HAVE_MVE"
- "vctp.<MVE_vctp> %1"
+ "vctp.<MVE_vctp>\t%1"
[(set_attr "type" "mve_move")
])
@@ -694,7 +694,7 @@ (define_insn "mve_vbrsrq_n_f<mode>"
VBRSRQ_N_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vbrsr.<V_sz_elem> %q0, %q1, %2"
+ "vbrsr.<V_sz_elem>\t%q0, %q1, %2"
[(set_attr "type" "mve_move")
])
@@ -976,7 +976,7 @@ (define_insn "mve_vbrsrq_n_<supf><mode>"
VBRSRQ_N))
]
"TARGET_HAVE_MVE"
- "vbrsr.%#<V_sz_elem> %q0, %q1, %2"
+ "vbrsr.%#<V_sz_elem>\t%q0, %q1, %2"
[(set_attr "type" "mve_move")
])
@@ -1864,7 +1864,7 @@ (define_insn "mve_vandq_f<mode>"
(match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vand %q0, %q1, %q2"
+ "vand\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -1878,7 +1878,7 @@ (define_insn "mve_vbicq_f<mode>"
(match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vbic %q0, %q1, %q2"
+ "vbic\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -1893,7 +1893,7 @@ (define_insn "mve_vbicq_n_<supf><mode>"
VBICQ_N))
]
"TARGET_HAVE_MVE"
- "vbic.i%#<V_sz_elem> %q0, %2"
+ "vbic.i%#<V_sz_elem>\t%q0, %2"
[(set_attr "type" "mve_move")
])
@@ -1967,7 +1967,7 @@ (define_insn "mve_vctp<MVE_vctp>q_m<MVE_vpred>"
VCTP_M))
]
"TARGET_HAVE_MVE"
- "vpst\;vctpt.<MVE_vctp> %1"
+ "vpst\;vctpt.<MVE_vctp>\t%1"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -1982,7 +1982,7 @@ (define_insn "mve_vcvtbq_f16_f32v8hf"
VCVTBQ_F16_F32))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvtb.f16.f32 %q0, %q2"
+ "vcvtb.f16.f32\t%q0, %q2"
[(set_attr "type" "mve_move")
])
@@ -1997,7 +1997,7 @@ (define_insn "mve_vcvttq_f16_f32v8hf"
VCVTTQ_F16_F32))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvtt.f16.f32 %q0, %q2"
+ "vcvtt.f16.f32\t%q0, %q2"
[(set_attr "type" "mve_move")
])
@@ -2011,7 +2011,7 @@ (define_insn "mve_veorq_f<mode>"
(match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "veor %q0, %q1, %q2"
+ "veor\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -2159,7 +2159,7 @@ (define_insn "mve_vmlaldavxq_s<mode>"
VMLALDAVXQ_S))
]
"TARGET_HAVE_MVE"
- "vmlaldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+ "vmlaldavx.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -2174,7 +2174,7 @@ (define_insn "mve_vmlsldavq_s<mode>"
VMLSLDAVQ_S))
]
"TARGET_HAVE_MVE"
- "vmlsldav.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+ "vmlsldav.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -2189,7 +2189,7 @@ (define_insn "mve_vmlsldavxq_s<mode>"
VMLSLDAVXQ_S))
]
"TARGET_HAVE_MVE"
- "vmlsldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+ "vmlsldavx.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -2262,7 +2262,7 @@ (define_insn "mve_vornq_f<mode>"
(match_operand:MVE_0 1 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vorn %q0, %q1, %q2"
+ "vorn\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -2276,7 +2276,7 @@ (define_insn "mve_vorrq_f<mode>"
(match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vorr %q0, %q1, %q2"
+ "vorr\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -2426,7 +2426,7 @@ (define_insn "mve_vrmlaldavhxq_sv4si"
VRMLALDAVHXQ_S))
]
"TARGET_HAVE_MVE"
- "vrmlaldavhx.s32 %Q0, %R0, %q1, %q2"
+ "vrmlaldavhx.s32\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -2561,7 +2561,7 @@ (define_insn "mve_vbicq_m_n_<supf><mode>"
VBICQ_M_N))
]
"TARGET_HAVE_MVE"
- "vpst\;vbict.i%#<V_sz_elem> %q0, %2"
+ "vpst\;vbict.i%#<V_sz_elem>\t%q0, %2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
@@ -2606,7 +2606,7 @@ (define_insn "mve_vcvtq_m_to_f_<supf><mode>"
VCVTQ_M_TO_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q2"
+ "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
@@ -2714,7 +2714,7 @@ (define_insn "mve_vshlcq_<supf><mode>"
(match_dup 4)]
VSHLCQ))]
"TARGET_HAVE_MVE"
- "vshlc %q0, %1, %4")
+ "vshlc\t%q0, %1, %4")
;;
;; [vabsq_m_s])
@@ -3272,7 +3272,7 @@ (define_insn "mve_vmvnq_m_<supf><mode>"
VMVNQ_M))
]
"TARGET_HAVE_MVE"
- "vpst\;vmvnt %q0, %q2"
+ "vpst\;vmvnt\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -3304,7 +3304,7 @@ (define_insn "@mve_vpselq_<supf><mode>"
VPSELQ))
]
"TARGET_HAVE_MVE"
- "vpsel %q0, %q1, %q2"
+ "vpsel\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -3929,7 +3929,7 @@ (define_insn "mve_vcvtbq_m_f16_f32v8hf"
VCVTBQ_M_F16_F32))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcvtbt.f16.f32 %q0, %q2"
+ "vpst\;vcvtbt.f16.f32\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -3945,7 +3945,7 @@ (define_insn "mve_vcvtbq_m_f32_f16v4sf"
VCVTBQ_M_F32_F16))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcvtbt.f32.f16 %q0, %q2"
+ "vpst\;vcvtbt.f32.f16\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -3961,7 +3961,7 @@ (define_insn "mve_vcvttq_m_f16_f32v8hf"
VCVTTQ_M_F16_F32))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcvttt.f16.f32 %q0, %q2"
+ "vpst\;vcvttt.f16.f32\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -3977,7 +3977,7 @@ (define_insn "mve_vcvttq_m_f32_f16v4sf"
VCVTTQ_M_F32_F16))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcvttt.f32.f16 %q0, %q2"
+ "vpst\;vcvttt.f32.f16\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4197,7 +4197,7 @@ (define_insn "mve_vmlaldavq_p_<supf><mode>"
VMLALDAVQ_P))
]
"TARGET_HAVE_MVE"
- "vpst\;vmlaldavt.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+ "vpst\;vmlaldavt.<supf>%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4228,7 +4228,7 @@ (define_insn "mve_vmlsldavaq_s<mode>"
VMLSLDAVAQ_S))
]
"TARGET_HAVE_MVE"
- "vmlsldava.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
+ "vmlsldava.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
[(set_attr "type" "mve_move")
])
@@ -4244,7 +4244,7 @@ (define_insn "mve_vmlsldavaxq_s<mode>"
VMLSLDAVAXQ_S))
]
"TARGET_HAVE_MVE"
- "vmlsldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
+ "vmlsldavax.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
[(set_attr "type" "mve_move")
])
@@ -4260,7 +4260,7 @@ (define_insn "mve_vmlsldavq_p_s<mode>"
VMLSLDAVQ_P_S))
]
"TARGET_HAVE_MVE"
- "vpst\;vmlsldavt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+ "vpst\;vmlsldavt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4276,7 +4276,7 @@ (define_insn "mve_vmlsldavxq_p_s<mode>"
VMLSLDAVXQ_P_S))
]
"TARGET_HAVE_MVE"
- "vpst\;vmlsldavxt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+ "vpst\;vmlsldavxt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
@@ -4353,7 +4353,7 @@ (define_insn "mve_vmvnq_m_n_<supf><mode>"
VMVNQ_M_N))
]
"TARGET_HAVE_MVE"
- "vpst\;vmvnt.i%#<V_sz_elem> %q0, %2"
+ "vpst\;vmvnt.i%#<V_sz_elem>\t%q0, %2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
@@ -4384,7 +4384,7 @@ (define_insn "mve_vorrq_m_n_<supf><mode>"
VORRQ_M_N))
]
"TARGET_HAVE_MVE"
- "vpst\;vorrt.i%#<V_sz_elem> %q0, %2"
+ "vpst\;vorrt.i%#<V_sz_elem>\t%q0, %2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
@@ -4399,7 +4399,7 @@ (define_insn "@mve_vpselq_f<mode>"
VPSELQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpsel %q0, %q1, %q2"
+ "vpsel\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -4575,7 +4575,7 @@ (define_insn "mve_vrev32q_m_fv8hf"
VREV32Q_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vrev32t.16 %q0, %q2"
+ "vpst\;vrev32t.16\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4591,7 +4591,7 @@ (define_insn "mve_vrev32q_m_<supf><mode>"
VREV32Q_M))
]
"TARGET_HAVE_MVE"
- "vpst\;vrev32t.%#<V_sz_elem> %q0, %q2"
+ "vpst\;vrev32t.%#<V_sz_elem>\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4607,7 +4607,7 @@ (define_insn "mve_vrev64q_m_f<mode>"
VREV64Q_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vrev64t.%#<V_sz_elem> %q0, %q2"
+ "vpst\;vrev64t.%#<V_sz_elem>\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4623,7 +4623,7 @@ (define_insn "mve_vrmlaldavhaxq_sv4si"
VRMLALDAVHAXQ_S))
]
"TARGET_HAVE_MVE"
- "vrmlaldavhax.s32 %Q0, %R0, %q2, %q3"
+ "vrmlaldavhax.s32\t%Q0, %R0, %q2, %q3"
[(set_attr "type" "mve_move")
])
@@ -4639,7 +4639,7 @@ (define_insn "mve_vrmlaldavhxq_p_sv4si"
VRMLALDAVHXQ_P_S))
]
"TARGET_HAVE_MVE"
- "vpst\;vrmlaldavhxt.s32 %Q0, %R0, %q1, %q2"
+ "vpst\;vrmlaldavhxt.s32\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4655,7 +4655,7 @@ (define_insn "mve_vrmlsldavhaxq_sv4si"
VRMLSLDAVHAXQ_S))
]
"TARGET_HAVE_MVE"
- "vrmlsldavhax.s32 %Q0, %R0, %q2, %q3"
+ "vrmlsldavhax.s32\t%Q0, %R0, %q2, %q3"
[(set_attr "type" "mve_move")
])
@@ -4671,7 +4671,7 @@ (define_insn "mve_vrmlsldavhq_p_sv4si"
VRMLSLDAVHQ_P_S))
]
"TARGET_HAVE_MVE"
- "vpst\;vrmlsldavht.s32 %Q0, %R0, %q1, %q2"
+ "vpst\;vrmlsldavht.s32\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4687,7 +4687,7 @@ (define_insn "mve_vrmlsldavhxq_p_sv4si"
VRMLSLDAVHXQ_P_S))
]
"TARGET_HAVE_MVE"
- "vpst\;vrmlsldavhxt.s32 %Q0, %R0, %q1, %q2"
+ "vpst\;vrmlsldavhxt.s32\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4912,7 +4912,7 @@ (define_insn "mve_vrev16q_m_<supf>v16qi"
VREV16Q_M))
]
"TARGET_HAVE_MVE"
- "vpst\;vrev16t.8 %q0, %q2"
+ "vpst\;vrev16t.8\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4944,7 +4944,7 @@ (define_insn "mve_vrmlaldavhq_p_<supf>v4si"
VRMLALDAVHQ_P))
]
"TARGET_HAVE_MVE"
- "vpst\;vrmlaldavht.<supf>32 %Q0, %R0, %q1, %q2"
+ "vpst\;vrmlaldavht.<supf>32\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4960,7 +4960,7 @@ (define_insn "mve_vrmlsldavhaq_sv4si"
VRMLSLDAVHAQ_S))
]
"TARGET_HAVE_MVE"
- "vrmlsldavha.s32 %Q0, %R0, %q2, %q3"
+ "vrmlsldavha.s32\t%Q0, %R0, %q2, %q3"
[(set_attr "type" "mve_move")
])
@@ -5129,7 +5129,7 @@ (define_insn "mve_vandq_m_<supf><mode>"
VANDQ_M))
]
"TARGET_HAVE_MVE"
- "vpst\;vandt %q0, %q2, %q3"
+ "vpst\;vandt\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -5146,7 +5146,7 @@ (define_insn "mve_vbicq_m_<supf><mode>"
VBICQ_M))
]
"TARGET_HAVE_MVE"
- "vpst\;vbict %q0, %q2, %q3"
+ "vpst\;vbict\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -5214,7 +5214,7 @@ (define_insn "mve_veorq_m_<supf><mode>"
VEORQ_M))
]
"TARGET_HAVE_MVE"
- "vpst\;veort %q0, %q2, %q3"
+ "vpst\;veort\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -5469,7 +5469,7 @@ (define_insn "mve_vornq_m_<supf><mode>"
VORNQ_M))
]
"TARGET_HAVE_MVE"
- "vpst\;vornt %q0, %q2, %q3"
+ "vpst\;vornt\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -5486,7 +5486,7 @@ (define_insn "mve_vorrq_m_<supf><mode>"
VORRQ_M))
]
"TARGET_HAVE_MVE"
- "vpst\;vorrt %q0, %q2, %q3"
+ "vpst\;vorrt\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -6658,7 +6658,7 @@ (define_insn "mve_vandq_m_f<mode>"
VANDQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vandt %q0, %q2, %q3"
+ "vpst\;vandt\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -6675,7 +6675,7 @@ (define_insn "mve_vbicq_m_f<mode>"
VBICQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vbict %q0, %q2, %q3"
+ "vpst\;vbict\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -6879,7 +6879,7 @@ (define_insn "mve_veorq_m_f<mode>"
VEORQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;veort %q0, %q2, %q3"
+ "vpst\;veort\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -7032,7 +7032,7 @@ (define_insn "mve_vornq_m_f<mode>"
VORNQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vornt %q0, %q2, %q3"
+ "vpst\;vornt\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -7049,7 +7049,7 @@ (define_insn "mve_vorrq_m_f<mode>"
VORRQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vorrt %q0, %q2, %q3"
+ "vpst\;vorrt\t%q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -8492,7 +8492,7 @@ (define_insn "mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn"
(match_operand:V2QI 3 "vpr_register_operand" "Up")]
VSTRDSSOQ))]
"TARGET_HAVE_MVE"
- "vpst\;vstrdt.64\t%q2, [%0, %q1, UXTW #3]"
+ "vpst\;vstrdt.64\t%q2, [%0, %q1, uxtw #3]"
[(set_attr "length" "8")])
;;
@@ -8521,7 +8521,7 @@ (define_insn "mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn"
(match_operand:V2DI 2 "s_register_operand" "w")]
VSTRDSSOQ))]
"TARGET_HAVE_MVE"
- "vstrd.64\t%q2, [%0, %q1, UXTW #3]"
+ "vstrd.64\t%q2, [%0, %q1, uxtw #3]"
[(set_attr "length" "4")])
;;
@@ -9473,7 +9473,7 @@ (define_insn "mve_vstrdq_scatter_base_wb_p_<supf>v2di"
ops[0] = operands[1];
ops[1] = operands[2];
ops[2] = operands[3];
- output_asm_insn ("vpst;vstrdt.u64\t%q2, [%q0, %1]!",ops);
+ output_asm_insn ("vpst\;vstrdt.u64\t%q2, [%q0, %1]!",ops);
return "";
}
[(set_attr "length" "8")])
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c
index a2d5160e518..1aa576afae3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** asrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int64_t
-asrl_reg (int64_t longval3, int32_t x)
+foo (int64_t value, int32_t shift)
{
- return asrl (longval3, x);
+ return asrl (value, shift);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "asrl\\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c
index 9c1b62fb9f2..5542ac8c316 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c
@@ -1,13 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** lsll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint64_t
-lsll_reg (uint64_t longval3, int32_t x)
+foo (uint64_t value, int32_t shift)
{
- return lsll (longval3, x);
+ return lsll (value, shift);
+}
+
+/*
+**foo1:
+** ...
+** lsll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint64_t
+foo1 (int32_t shift)
+{
+ return lsll (1, shift);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "lsll\\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c
index 1f0a228e4b4..ea8c7a0ce4a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** sqrshr (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32_t
-sqrshr_reg (int32_t longval3, int32_t x)
+foo (int32_t value, int32_t shift)
{
- return sqrshr (longval3, x);
+ return sqrshr (value, shift);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "sqrshr\\tr\[0-9\]+, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c
index 2f1612cde77..affa12c526d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** sqrshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #48, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int64_t
-sqrshrl_reg (int64_t longval3, int32_t x)
+foo (int64_t value, int32_t shift)
{
- return sqrshrl_sat48 (longval3, x);
+ return sqrshrl_sat48 (value, shift);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "sqrshrl\\tr\[0-9\]+, r\[0-9\]+, #48, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c
index 8cb8c74b268..e8c9c441163 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** sqshl (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-sqshl_imm (int32_t longval3)
+foo (int32_t value)
{
- return sqshl (longval3, 25);
+ return sqshl (value, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "sqshl\\tr\[0-9\]+, #25" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c
index 016ef2a336e..03dc91f3758 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** sqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-sqshll_imm(int64_t value)
+foo (int64_t value)
{
- return sqshll (value, 21);
+ return sqshll (value, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "sqshll\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
index 264f0bf09ce..94e3f42fd33 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** srshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
int32_t
-srshr_imm (int32_t longval3)
+foo (int32_t value)
{
- return srshr (longval3, 25);
+ return srshr (value, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "srshr\\tr\[0-9\]+, #25" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
index ab12d0da635..65f28ccbfde 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
int64_t
-srshrl_imm(int64_t value)
+foo (int64_t value)
{
- return srshrl (value, 21);
+ return srshrl (value, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "srshrl\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c
index 0064aa19fbc..4b6fd041210 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c
@@ -1,13 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** uqrshl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32_t
-uqrshl_reg (uint32_t longval3, int32_t x)
+foo (uint32_t value, int32_t shift)
{
- return uqrshl (longval3, x);
+ return uqrshl (value, shift);
+}
+
+/*
+**foo1:
+** ...
+** uqrshl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint32_t
+foo1 (int32_t shift)
+{
+ return uqrshl (1, shift);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "uqrshl\\tr\[0-9\]+, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c
index 24cd2324413..eaf36911eb6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c
@@ -1,13 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** uqrshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #48, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint64_t
-uqrshll_reg (uint64_t longval3, int32_t x)
+foo (uint64_t value, int32_t shift)
{
- return uqrshll_sat48 (longval3, x);
+ return uqrshll_sat48 (value, shift);
+}
+
+/*
+**foo1:
+** ...
+** uqrshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #48, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint64_t
+foo1 (int32_t shift)
+{
+ return uqrshll_sat48 (1, shift);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "uqrshll\\tr\[0-9\]+, r\[0-9\]+, #48, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
index 9e6ff649805..b23c9d97ba6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
@@ -1,13 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
uint32_t
-uqshl_imm (uint32_t longval3)
+foo (uint32_t value)
{
- return uqshl (longval3, 21);
+ return uqshl (value, 1);
+}
+
+/*
+**foo1:
+** ...
+** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
+uint32_t
+foo1 ()
+{
+ return uqshl (1, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "uqshl\\tr\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
index 52560721d6f..6a3d08eea75 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
@@ -1,13 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
uint64_t
-uqshll_imm(uint64_t value)
+foo (uint64_t value)
{
- return uqshll (value, 21);
+ return uqshll (value, 1);
+}
+
+/*
+**foo1:
+** ...
+** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
+uint64_t
+foo1 ()
+{
+ return uqshll (1, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "uqshll\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
index ec5d84bb009..23afcb8da4c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
@@ -1,13 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
-uint64_t
-urshr_imm (uint32_t longval3)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
+uint32_t
+foo (uint32_t value)
+{
+ return urshr (value, 1);
+}
+
+/*
+**foo1:
+** ...
+** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
+uint32_t
+foo1 ()
{
- return urshr (longval3, 21);
+ return urshr (1, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "urshr\\tr\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
index ea29412ab7a..8014371f47f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
@@ -1,13 +1,40 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
uint64_t
-urshrl_imm(uint64_t value)
+foo (uint64_t value)
{
- return urshrl (value, 21);
+ return urshrl (value, 1);
+}
+
+/*
+**foo1:
+** ...
+** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** ...
+*/
+uint64_t
+foo1 ()
+{
+ return urshrl (1, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "urshrl\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
index 1bfc101d5e8..b262bf94d39 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
@@ -1,23 +1,61 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vadcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p)
{
return vadciq_m_s32 (inactive, a, b, carry_out, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadcit.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vadcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p)
{
return vadciq_m (inactive, a, b, carry_out, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadcit.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
index f72fe34c33b..d349caed36a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
@@ -1,23 +1,61 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vadcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p)
{
return vadciq_m_u32 (inactive, a, b, carry_out, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadcit.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vadcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p)
{
return vadciq_m (inactive, a, b, carry_out, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadcit.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
index ff13841c581..5166993a355 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vadci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t a, int32x4_t b, unsigned * carry_out)
+foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
{
return vadciq_s32 (a, b, carry_out);
}
-/* { dg-final { scan-assembler "vadci.i32" } } */
+/*
+**foo1:
+** ...
+** vadci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t a, int32x4_t b, unsigned * carry_out)
+foo1 (int32x4_t a, int32x4_t b, unsigned *carry_out)
{
return vadciq (a, b, carry_out);
}
-/* { dg-final { scan-assembler "vadci.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
index e3560362225..080bd61d238 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vadci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, unsigned * carry_out)
+foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
{
return vadciq_u32 (a, b, carry_out);
}
-/* { dg-final { scan-assembler "vadci.i32" } } */
+/*
+**foo1:
+** ...
+** vadci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry_out)
+foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
{
return vadciq (a, b, carry_out);
}
-/* { dg-final { scan-assembler "vadci.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
index 668c4fdc82c..45e6ff03623 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
@@ -1,23 +1,73 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p)
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p)
{
return vadcq_m_s32 (inactive, a, b, carry, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadct.i32" } } */
+/*
+**foo1:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p)
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p)
{
return vadcq_m (inactive, a, b, carry, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadct.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
index 368c7c5c5f2..54f141b2093 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
@@ -1,23 +1,73 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p)
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p)
{
return vadcq_m_u32 (inactive, a, b, carry, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadct.i32" } } */
+/*
+**foo1:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p)
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p)
{
return vadcq_m (inactive, a, b, carry, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadct.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
index 9c8777c45ee..06d5bae09da 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
@@ -1,21 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vadc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t a, int32x4_t b, unsigned * carry)
+foo (int32x4_t a, int32x4_t b, unsigned *carry)
{
return vadcq_s32 (a, b, carry);
}
-/* { dg-final { scan-assembler "vadc.i32" } } */
+/*
+**foo1:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vadc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t a, int32x4_t b, unsigned * carry)
+foo1 (int32x4_t a, int32x4_t b, unsigned *carry)
{
return vadcq (a, b, carry);
}
-/* { dg-final { scan-assembler "vadc.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
index 78f48da5107..e2111cfd16a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
@@ -1,21 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vadc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, unsigned * carry)
+foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
{
return vadcq_u32 (a, b, carry);
}
-/* { dg-final { scan-assembler "vadc.i32" } } */
+/*
+**foo1:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vadc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry)
+foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry)
{
return vadcq (a, b, carry);
}
-/* { dg-final { scan-assembler "vadc.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c
index 2303b598a28..cb1820347bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vandq_f16 (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+/*
+**foo1:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vandq (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c
index 905f2b410c0..1034bcbaa62 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vandq_f32 (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+/*
+**foo1:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vandq (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c
index d061dbc390b..d6752a6fdc4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vandq_m_f16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vandq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c
index 77b2813dfad..fb8410d0b71 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vandq_m_f32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vandq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c
index 2840a33b433..5797ffa9a16 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vandq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vandq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c
index 2e8ec7e14de..d2ede670e40 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vandq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vandq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c
index 36226f6d9ac..76ed60c64a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vandq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vandq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c
index 49f0502f607..b3f7833e546 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vandq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vandq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c
index 194c7800a05..7d761c86622 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vandq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vandq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c
index 9b27c44ee82..8fd17e4f258 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vandq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vandq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c
index 86aa64fec96..9f3e9b0c078 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vandq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+/*
+**foo1:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vandq (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c
index 907fe89ced8..ab0e9627fb9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vandq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+/*
+**foo1:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vandq (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c
index 783ad042c87..980ba6b5f7a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vandq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+/*
+**foo1:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vandq (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c
index ae483869f11..fdd18e92476 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b)
{
return vandq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+/*
+**foo1:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b)
{
return vandq (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c
index 532926d894a..01df1828788 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b)
{
return vandq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+/*
+**foo1:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b)
{
return vandq (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c
index 4018308f66d..a4f0cec4483 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b)
{
return vandq_u8 (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+/*
+**foo1:
+** ...
+** vand q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b)
{
return vandq (a, b);
}
-/* { dg-final { scan-assembler "vand" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c
index 6aa98910c7b..99c586d5604 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vandq_x_f16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vandq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c
index fd74ee6eee7..eda9d618409 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vandq_x_f32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vandq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c
index d8821d59be7..f0159ee7668 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vandq_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vandq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c
index 980b01436b6..09277b2d56b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vandq_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vandq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c
index 93dead71416..f1232168a7d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vandq_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vandq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c
index aa99c69bd84..836385f44f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vandq_x_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vandq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c
index 1178837d78a..06b5010738b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vandq_x_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vandq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c
index d46e2b235b9..37f4fc51f9a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vandq_x_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vandt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vandq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c
index c15f1f91d07..38a1a4adafa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vbicq_f16 (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+/*
+**foo1:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vbicq (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c
index c8659d460a0..224b535992b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vbicq_f32 (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+/*
+**foo1:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vbicq (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c
index 39a12a9fba3..e197a2aa1e3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vbicq_m_f16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vbicq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c
index 091027c4b19..b441e205a64 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vbicq_m_f32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vbicq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c
index 3d0d09859c1..4e2be3e4516 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
- return vbicq_m_n_s16 (a, 16, p);
+ return vbicq_m_n_s16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, mve_pred16_t p)
{
- return vbicq_m_n (a, 16, p);
+ return vbicq_m_n (a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c
index 47a9459580b..d8beab58024 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
return vbicq_m_n_s32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, mve_pred16_t p)
{
return vbicq_m_n (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c
index 7c0c691fd46..34b62aa557f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vbicq_m_n_u16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vbicq_m_n (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c
index e97b17aa27d..60681e3f045 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, mve_pred16_t p)
{
return vbicq_m_n_u32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, mve_pred16_t p)
{
return vbicq_m_n (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c
index 31a9e986b8d..c30658cf34c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vbicq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vbicq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c
index 9e7a2940b42..6a861cb80e5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vbicq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vbicq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c
index b5e3253384c..c19caf53658 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vbicq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vbicq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c
index 54370ab9548..443fcac6605 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vbicq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vbicq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c
index cfcae7c74a9..31b1e22ef7a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vbicq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vbicq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c
index cd9856f629e..6bddc5c2d30 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vbicq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vbicq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c
index 6258727d82f..8726b2c57a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c
@@ -1,20 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a)
{
return vbicq_n_s16 (a, 1);
}
+
+/*
+**foo1:
+** ...
+** vbic.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a)
{
return vbicq (a, 1);
}
-/* { dg-final { scan-assembler-times "vbic.i16" 2 } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c
index be641abf556..015af580ed0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c
@@ -1,20 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a)
{
return vbicq_n_s32 (a, 1);
}
+
+/*
+**foo1:
+** ...
+** vbic.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a)
{
return vbicq (a, 1);
}
-/* { dg-final { scan-assembler-times "vbic.i32" 2 } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c
index 0b26ffda0dc..1ad03b9d17f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c
@@ -1,20 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a)
{
return vbicq_n_u16 (a, 1);
}
+
+/*
+**foo1:
+** ...
+** vbic.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a)
{
return vbicq (a, 1);
}
-/* { dg-final { scan-assembler-times "vbic.i16" 2 } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c
index 47820bd184a..f3fe58fdf37 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c
@@ -1,20 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a)
{
return vbicq_n_u32 (a, 1);
}
+
+/*
+**foo1:
+** ...
+** vbic.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a)
{
return vbicq (a, 1);
}
-/* { dg-final { scan-assembler-times "vbic.i32" 2 } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c
index 4ffacdd9733..6fd2a9e5c0c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vbicq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+/*
+**foo1:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vbicq (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c
index 13fbff40746..37859e0dc6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vbicq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+/*
+**foo1:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vbicq (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c
index b9fba943a83..23db9afbcf1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vbicq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+/*
+**foo1:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vbicq (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c
index 5d94a6396c4..9ed4e533e52 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b)
{
return vbicq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+/*
+**foo1:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b)
{
return vbicq (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c
index 893dc3deefc..abaf2a9cf7b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b)
{
return vbicq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+/*
+**foo1:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b)
{
return vbicq (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c
index bd5e9bc0197..4a47bb9d0e7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c
@@ -1,22 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b)
{
return vbicq_u8 (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+/*
+**foo1:
+** ...
+** vbic q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b)
{
return vbicq (a, b);
}
-/* { dg-final { scan-assembler "vbic" } } */
+#ifdef __cplusplus
+}
+#endif
+
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c
index 975d60c713e..aa4812568d7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vbicq_x_f16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vbicq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c
index e779224b5d5..db295df1cd5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vbicq_x_f32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vbicq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c
index be554c4b2fb..2b7a3594dd7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vbicq_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vbicq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c
index e49aabf11d6..bf3b755f9ee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vbicq_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vbicq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c
index c36cd1e6dc5..30df0904539 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vbicq_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vbicq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c
index 3b611591deb..eaa50a84fd4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vbicq_x_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vbicq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c
index fce2fab3dd6..aea2592d9cf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vbicq_x_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vbicq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c
index 672b3fb1e39..4ffee473ea6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vbicq_x_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbict q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vbicq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c
index 8f8d1bffd73..5985b7fed01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m_n_f16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c
index 336c8194cd7..1fff5a8bf95 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m_n_f32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c
index f597d8ccb9d..a5221f8d864 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m_n_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c
index 76f0463af1e..99106e81a30 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m_n_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c
index 30c6519236c..6bd4c8f4455 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m_n_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c
index 7052b8b5ff5..03ad4896029 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m_n_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c
index e19e02fbbd8..e65077001ec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m_n_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c
index ce658432fd9..61ca255e431 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m_n_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c
index 9b8dea6e7e8..6dc4c657cbf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, int32_t b)
{
return vbrsrq_n_f16 (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.16" } } */
+/*
+**foo1:
+** ...
+** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, int32_t b)
{
return vbrsrq (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c
index cd335197c3b..810cd1b86ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, int32_t b)
{
return vbrsrq_n_f32 (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.32" } } */
+/*
+**foo1:
+** ...
+** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, int32_t b)
{
return vbrsrq (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c
index efb17dd5250..109ccd72f0a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32_t b)
{
return vbrsrq_n_s16 (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.16" } } */
+/*
+**foo1:
+** ...
+** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32_t b)
{
return vbrsrq (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c
index fda78e6aa4b..78b2db49c87 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32_t b)
{
return vbrsrq_n_s32 (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.32" } } */
+/*
+**foo1:
+** ...
+** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32_t b)
{
return vbrsrq (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c
index cd75a2b88fa..dfd485240ea 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbrsr.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int32_t b)
{
return vbrsrq_n_s8 (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.8" } } */
+/*
+**foo1:
+** ...
+** vbrsr.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int32_t b)
{
return vbrsrq (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c
index ef7708e33f8..59e1fcc0fd9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32_t b)
{
return vbrsrq_n_u16 (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.16" } } */
+/*
+**foo1:
+** ...
+** vbrsr.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32_t b)
{
return vbrsrq (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c
index b33c533aeda..2d7792dd1cb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32_t b)
{
return vbrsrq_n_u32 (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.32" } } */
+/*
+**foo1:
+** ...
+** vbrsr.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32_t b)
{
return vbrsrq (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c
index 91156bd4325..5f4398ddbe1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vbrsr.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int32_t b)
{
return vbrsrq_n_u8 (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.8" } } */
+/*
+**foo1:
+** ...
+** vbrsr.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int32_t b)
{
return vbrsrq (a, b);
}
-/* { dg-final { scan-assembler "vbrsr.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c
index 0710b59b1ab..d9d404ccf82 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x_n_f16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c
index 67ab8cf80c9..8b176fe701c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x_n_f32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c
index ac0c13c0b4d..77f4f1852a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x_n_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c
index 98c87f17588..fc4a1c9c7e0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x_n_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c
index 8159f5da999..10322ac328a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x_n_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c
index dbad2940616..72d8a9e23b0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x_n_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c
index 04c812a2747..535af3600c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x_n_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c
index b3836936750..5f8f8c928fd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x_n_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vbrsrt.8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vbrsrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
index 0339fbcafc6..89d8e2b9109 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
@@ -56,4 +56,4 @@ foo2 (float16x8_t a)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
index 2659f061cd9..1575966073d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
@@ -1,21 +1,44 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vctp.16 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
foo (uint32_t a)
{
return vctp16q (a);
}
-/* { dg-final { scan-assembler "vctp.16" } } */
-
+/*
+**foo1:
+** ...
+** vctp.16 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
-foo1 (uint32_t a)
+foo1 ()
{
- return vctp16q (a);
+ return vctp16q (1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vctp.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c
index d901c9ece0d..a14fbe97f86 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c
@@ -1,22 +1,52 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vctpt.16 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
foo (uint32_t a, mve_pred16_t p)
{
return vctp16q_m (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vctpt.16" } } */
-
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vctpt.16 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
-foo1 (uint32_t a, mve_pred16_t p)
+foo1 (mve_pred16_t p)
{
- return vctp16q_m (a, p);
+ return vctp16q_m (1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
index f54ecc33e4a..c53b6190019 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
@@ -1,21 +1,44 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vctp.32 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
foo (uint32_t a)
{
return vctp32q (a);
}
-/* { dg-final { scan-assembler "vctp.32" } } */
-
+/*
+**foo1:
+** ...
+** vctp.32 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
-foo1 (uint32_t a)
+foo1 ()
{
- return vctp32q (a);
+ return vctp32q (1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vctp.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c
index 3d2f101fb0c..6fa790d7039 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c
@@ -1,22 +1,52 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vctpt.32 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
foo (uint32_t a, mve_pred16_t p)
{
return vctp32q_m (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vctpt.32" } } */
-
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vctpt.32 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
-foo1 (uint32_t a, mve_pred16_t p)
+foo1 (mve_pred16_t p)
{
- return vctp32q_m (a, p);
+ return vctp32q_m (1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
index 8502ad3b600..dba63bae1a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
@@ -1,21 +1,44 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vctp.64 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
foo (uint32_t a)
{
return vctp64q (a);
}
-/* { dg-final { scan-assembler "vctp.64" } } */
-
+/*
+**foo1:
+** ...
+** vctp.64 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
-foo1 (uint32_t a)
+foo1 ()
{
- return vctp64q (a);
+ return vctp64q (1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vctp.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c
index 6f3d1c21d01..1faf8a0063c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c
@@ -1,22 +1,52 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vctpt.64 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
foo (uint32_t a, mve_pred16_t p)
{
return vctp64q_m (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vctpt.64" } } */
-
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vctpt.64 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
-foo1 (uint32_t a, mve_pred16_t p)
+foo1 (mve_pred16_t p)
{
- return vctp64q_m (a, p);
+ return vctp64q_m (1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
index 91283f82db1..56267fd861d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
@@ -1,21 +1,44 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vctp.8 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
foo (uint32_t a)
{
return vctp8q (a);
}
-/* { dg-final { scan-assembler "vctp.8" } } */
-
+/*
+**foo1:
+** ...
+** vctp.8 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
-foo1 (uint32_t a)
+foo1 ()
{
- return vctp8q (a);
+ return vctp8q (1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vctp.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c
index 2c640ba6801..937c33cbb83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c
@@ -1,22 +1,52 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vctpt.8 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
foo (uint32_t a, mve_pred16_t p)
{
return vctp8q_m (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vctpt.8" } } */
-
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vctpt.8 (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
-foo1 (uint32_t a, mve_pred16_t p)
+foo1 (mve_pred16_t p)
{
- return vctp8q_m (a, p);
+ return vctp8q_m (1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c
index ad8b7d9eb06..fcf4cf817ff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtaq_m_s16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.s16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtaq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c
index 5649e342d1a..8aa640de6ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtaq_m_s32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.s32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtaq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c
index b73c3418758..8fdd3c1b1b0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtaq_m_u16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.u16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtaq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c
index 56c04f9f782..246941e7523 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtaq_m_u32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.u32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtaq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c
index e2d70e8901f..c45ba6ccfbf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvta.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a)
{
return vcvtaq_s16_f16 (a);
}
-/* { dg-final { scan-assembler "vcvta.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c
index d6fd45ae01e..baa20cc5f9a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvta.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a)
{
return vcvtaq_s32_f32 (a);
}
-/* { dg-final { scan-assembler "vcvta.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c
index 8f3b12d9101..de4ea927385 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvta.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a)
{
- return vcvtaq_u16_f16 (a);
+ return vcvtaq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vcvta.u16.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c
index 45e2916e288..93bf292980e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvta.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a)
{
- return vcvtaq_u32_f32 (a);
+ return vcvtaq_u32_f32 (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vcvta.u32.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c
index 26ff128217e..b046b7ad94d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtaq_x_s16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c
index 3a79e3aecd4..77a740867be 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtaq_x_s32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c
index 1f26e7f52d4..b8a10822bdb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtaq_x_u16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.u16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c
index 987e524d789..51184231b7a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtat.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtaq_x_u32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.u32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c
index f45e07de375..76b76a2f66e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtb.f16.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float32x4_t b)
{
return vcvtbq_f16_f32 (a, b);
}
-/* { dg-final { scan-assembler "vcvtb.f16.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c
index 39471a0a43b..347d4129b99 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtb.f32.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float16x8_t a)
{
return vcvtbq_f32_f16 (a);
}
-/* { dg-final { scan-assembler "vcvtb.f32.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c
index 6c8d9192417..0545d1e8e27 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c
@@ -1,22 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtbt.f16.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float32x4_t b, mve_pred16_t p)
{
return vcvtbq_m_f16_f32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtbt.f16.f32" } } */
-
-float16x8_t
-foo1 (float16x8_t a, float32x4_t b, mve_pred16_t p)
-{
- return vcvtbq_m (a, b, p);
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c
index 91775436e67..1b220ddfa19 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c
@@ -1,22 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtbt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtbq_m_f32_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtbt.f32.f16" } } */
-
-float32x4_t
-foo1 (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
-{
- return vcvtbq_m (inactive, a, p);
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c
index 0dcdb19d1e4..2a3559d2522 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtbt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtbq_x_f32_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtbt.f32.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c
index 75ff107ab15..b8f6ed855d6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtmq_m_s16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.s16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtmq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c
index b364533e08d..61445594524 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtmq_m_s32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.s32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtmq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c
index 249ef0e92b1..3e57ba58d0f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtmq_m_u16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.u16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtmq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c
index 52ff77ca4c5..8b8a1565332 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtmq_m_u32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.u32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtmq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c
index 70f43ddc220..4eafb5783b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtm.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a)
{
return vcvtmq_s16_f16 (a);
}
-/* { dg-final { scan-assembler "vcvtm.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c
index c2f62cf0717..bd3bfc1b4bd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtm.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a)
{
return vcvtmq_s32_f32 (a);
}
-/* { dg-final { scan-assembler "vcvtm.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c
index 62e4acd73b5..a1917eaf11a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtm.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a)
{
- return vcvtmq_u16_f16 (a);
+ return vcvtmq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vcvtm.u16.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c
index f7f59df1be9..c9f62479e85 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtm.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a)
{
- return vcvtmq_u32_f32 (a);
+ return vcvtmq_u32_f32 (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vcvtm.u32.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c
index 22597fb9cb1..211c2d0df83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtmq_x_s16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c
index 17a583c2641..7ca2cb6eb15 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtmq_x_s32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c
index b6e296f29ea..df212089bf5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtmq_x_u16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.u16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c
index 5f9909b5adb..8b5818fd029 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtmt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtmq_x_u32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.u32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c
index a7c3b66a2eb..67fa9cb720d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtnq_m_s16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.s16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c
index 38913a9e26c..26c0b09f7b5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtnq_m_s32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.s32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c
index 42d9e5ea79c..ee2a64747a2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtnq_m_u16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.u16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c
index 321fa35ceb3..cc61951abf5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtnq_m_u32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.u32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c
index d66c058834e..39c00f6ed04 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtn.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a)
{
return vcvtnq_s16_f16 (a);
}
-/* { dg-final { scan-assembler "vcvtn.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c
index 3dec6661411..c371598db24 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtn.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a)
{
return vcvtnq_s32_f32 (a);
}
-/* { dg-final { scan-assembler "vcvtn.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c
index 07637e84bf7..17ae06a57be 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtn.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a)
{
- return vcvtnq_u16_f16 (a);
+ return vcvtnq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vcvtn.u16.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c
index b6d5eb90493..4777b1b205a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtn.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a)
{
return vcvtnq_u32_f32 (a);
}
-/* { dg-final { scan-assembler "vcvtn.u32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c
index f552d633231..a9c91831881 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtnq_x_s16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c
index c3aa2e3daed..2ffb1d98736 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtnq_x_s32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c
index 9d9d12f9f2c..ce2ceb108b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtnq_x_u16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.u16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c
index e7df48de88d..c2c48ef1558 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtnt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtnq_x_u32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.u32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c
index c613fc8883d..f09c78b77c2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtpq_m_s16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.s16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtpq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c
index 7f4c7f600e5..7a3d7763406 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtpq_m_s32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.s32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtpq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c
index 192891021f0..f82103ca831 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtpq_m_u16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.u16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtpq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c
index 61858f7844a..7c848aa5157 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtpq_m_u32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.u32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtpq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c
index 8615e50bbaa..87258346b53 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtp.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a)
{
return vcvtpq_s16_f16 (a);
}
-/* { dg-final { scan-assembler "vcvtp.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c
index fed7a4b83f7..e4a7d0baaf1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtp.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a)
{
return vcvtpq_s32_f32 (a);
}
-/* { dg-final { scan-assembler "vcvtp.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c
index 37d1411067f..94edfcb0244 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtp.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a)
{
- return vcvtpq_u16_f16 (a);
+ return vcvtpq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vcvtp.u16.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c
index fcea4c51885..b84501ca72c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtp.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a)
{
- return vcvtpq_u32_f32 (a);
+ return vcvtpq_u32_f32 (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vcvtp.u32.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c
index 5d550772bfc..2b51cc56867 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtpq_x_s16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c
index 31823ab9528..6c4d6655300 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtpq_x_s32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c
index 0d1808c0fe8..2e663c8a472 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtpq_x_u16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.u16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c
index d73df212942..2d32425fdbf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtpt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtpq_x_u32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.u32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c
index 560127b7c9f..9f1647c1ac8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (int16x8_t a)
{
return vcvtq_f16_s16 (a);
}
-/* { dg-final { scan-assembler "vcvt.f16.s16" } } */
+
+/*
+**foo1:
+** ...
+** vcvt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (int16x8_t a)
+{
+ return vcvtq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c
index f571c535778..6704626bd1e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (uint16x8_t a)
{
return vcvtq_f16_u16 (a);
}
-/* { dg-final { scan-assembler "vcvt.f16.u16" } } */
+
+/*
+**foo1:
+** ...
+** vcvt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (uint16x8_t a)
+{
+ return vcvtq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c
index 898c74bfba4..898126468d9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (int32x4_t a)
{
return vcvtq_f32_s32 (a);
}
-/* { dg-final { scan-assembler "vcvt.f32.s32" } } */
+
+/*
+**foo1:
+** ...
+** vcvt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (int32x4_t a)
+{
+ return vcvtq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c
index a44add5d178..9e9aa1d703e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (uint32x4_t a)
{
return vcvtq_f32_u32 (a);
}
-/* { dg-final { scan-assembler "vcvt.f32.u32" } } */
+
+/*
+**foo1:
+** ...
+** vcvt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (uint32x4_t a)
+{
+ return vcvtq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c
index 45e9b045af6..b01a9a148c6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vcvtq_m_f16_s16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c
index b50f57234c3..805e26e72fd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vcvtq_m_f16_u16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c
index 4c1af180b58..7faa130fa3f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vcvtq_m_f32_s32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c
index 49acef80489..589d4efa61b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vcvtq_m_f32_u32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c
index d5ba7a690a6..3e23f1d88d8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n_f16_s16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c
index e53d7fa6ef1..f6f309cba25 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n_f16_u16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c
index 58519c04ff4..e6ff2fd6f44 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vcvtq_m_n_f32_s32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vcvtq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c
index 782d1f9e259..7368f127aab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
- return vcvtq_m_n_f32_u32 (inactive, a, 16, p);
+ return vcvtq_m_n_f32_u32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
- return vcvtq_m_n (inactive, a, 16, p);
+ return vcvtq_m_n (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c
index cd3f373aa77..edfb01203dd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n_s16_f16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c
index d1ff5072223..8084160e7e9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtq_m_n_s32_f32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c
index 4bf12e8b64e..1d217387ac6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n_u16_f16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c
index 4d0b1bf7a7f..868a1bcc1b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtq_m_n_u32_f32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c
index 606e43614ea..a998cdcb11a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtq_m_s16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c
index 2204e7929ec..fdaeac453a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtq_m_s32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c
index 1f814251c4f..f168d371615 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtq_m_u16_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c
index 13cd6f28884..83e5ae38106 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtq_m_u32_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c
index 565012e4e93..5c017221889 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (int16x8_t a)
{
return vcvtq_n_f16_s16 (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.f16.s16" } } */
+/*
+**foo1:
+** ...
+** vcvt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (int16x8_t a)
{
return vcvtq_n (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.f16.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c
index 95acc29683f..1080a5a0309 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (uint16x8_t a)
{
return vcvtq_n_f16_u16 (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.f16.u16" } } */
+/*
+**foo1:
+** ...
+** vcvt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (uint16x8_t a)
{
return vcvtq_n (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.f16.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c
index 5285099bc2a..020138b0084 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (int32x4_t a)
{
return vcvtq_n_f32_s32 (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.f32.s32" } } */
+/*
+**foo1:
+** ...
+** vcvt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (int32x4_t a)
{
return vcvtq_n (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.f32.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c
index ad6335116bc..3f1c3c8c9e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (uint32x4_t a)
{
return vcvtq_n_f32_u32 (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.f32.u32" } } */
+/*
+**foo1:
+** ...
+** vcvt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (uint32x4_t a)
{
return vcvtq_n (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.f32.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c
index ed3dd1a87d6..d16c114e00b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.s16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a)
{
return vcvtq_n_s16_f16 (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c
index e7f63f8cdd2..9256cb48a26 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.s32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a)
{
return vcvtq_n_s32_f32 (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c
index ca2fdca9b49..1038af8f890 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.u16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a)
{
return vcvtq_n_u16_f16 (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.u16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c
index 2919ea5b364..5c06365b320 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.u32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a)
{
return vcvtq_n_u32_f32 (a, 1);
}
-/* { dg-final { scan-assembler "vcvt.u32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c
index 8269bf949bf..ecec3727529 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a)
{
return vcvtq_s16_f16 (a);
}
-/* { dg-final { scan-assembler "vcvt.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c
index 2af96d25917..9be17c0696c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a)
{
return vcvtq_s32_f32 (a);
}
-/* { dg-final { scan-assembler "vcvt.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c
index afac0f4d414..3c33f2ce5b1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a)
{
- return vcvtq_u16_f16 (a);
+ return vcvtq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vcvt.u16.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c
index 7380f73301a..8e70df955b9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a)
{
- return vcvtq_u32_f32 (a);
+ return vcvtq_u32_f32 (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vcvt.u32.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c
index c6b9c1005f5..73b368fdd4f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
return vcvtq_x_f16_s16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (int16x8_t a, mve_pred16_t p)
{
return vcvtq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c
index d3ef02c1931..13d7fed2f5b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vcvtq_x_f16_u16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vcvtq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c
index fa73ad69ce5..d14099c87a6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
return vcvtq_x_f32_s32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (int32x4_t a, mve_pred16_t p)
{
return vcvtq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c
index 99ca3881553..800d8aa8e8e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (uint32x4_t a, mve_pred16_t p)
{
return vcvtq_x_f32_u32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (uint32x4_t a, mve_pred16_t p)
{
return vcvtq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c
index 718c83e74df..f91021d5735 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
return vcvtq_x_n_f16_s16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (int16x8_t a, mve_pred16_t p)
{
return vcvtq_x_n (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c
index 510c29c383a..f4c444b5540 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vcvtq_x_n_f16_u16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f16.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vcvtq_x_n (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c
index 34f7cc1e061..7c11f1f0c34 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
return vcvtq_x_n_f32_s32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (int32x4_t a, mve_pred16_t p)
{
return vcvtq_x_n (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c
index b5b20efc1b8..96a1d2c8876 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (uint32x4_t a, mve_pred16_t p)
{
- return vcvtq_x_n_f32_u32 (a, 16, p);
+ return vcvtq_x_n_f32_u32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.f32.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (uint32x4_t a, mve_pred16_t p)
{
- return vcvtq_x_n (a, 16, p);
+ return vcvtq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c
index 3c3343ae4e1..7c0f551d66f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtq_x_n_s16_f16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c
index 17ef866af39..c22eeb75a17 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtq_x_n_s32_f32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c
index 62e6f1638d5..7f07b0fac53 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u16.f16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtq_x_n_u16_f16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c
index 306e32016ff..7531db7d575 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u32.f32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtq_x_n_u32_f32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c
index 56867da3bb0..fd90d67b46c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtq_x_s16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c
index 4449bd68c54..e6cbbeaca2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.s32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtq_x_s32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c
index 580bb775c59..29d1d9d5c56 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u16.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvtq_x_u16_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c
index 3722de632e5..0181850d857 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvtt.u32.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vcvtq_x_u32_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c
index 599e30e3d26..3c9a6844e01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtt.f16.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float32x4_t b)
{
return vcvttq_f16_f32 (a, b);
}
-/* { dg-final { scan-assembler "vcvtt.f16.f32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c
index a4a7997d2dd..9d389382ae9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vcvtt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float16x8_t a)
{
return vcvttq_f32_f16 (a);
}
-/* { dg-final { scan-assembler "vcvtt.f32.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c
index 065974d7e76..2eeb670a5a2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c
@@ -1,22 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvttt.f16.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float32x4_t b, mve_pred16_t p)
{
return vcvttq_m_f16_f32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvttt.f16.f32" } } */
-
-float16x8_t
-foo1 (float16x8_t a, float32x4_t b, mve_pred16_t p)
-{
- return vcvttq_m (a, b, p);
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c
index 1eb69e4fee9..ba309114dae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c
@@ -1,22 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvttt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvttq_m_f32_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvttt.f32.f16" } } */
-
-float32x4_t
-foo1 (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
-{
- return vcvttq_m (inactive, a, p);
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c
index 921caba0e1b..29688a939dd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vcvttt.f32.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float16x8_t a, mve_pred16_t p)
{
return vcvttq_x_f32_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvttt.f32.f16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c
index 90cd663c7f3..0c27a1c5664 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return veorq_f16 (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+/*
+**foo1:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return veorq (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c
index e9ad87a9796..cbf67e335ef 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return veorq_f32 (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+/*
+**foo1:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return veorq (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c
index a39d680e0cd..5d9831f8d34 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return veorq_m_f16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return veorq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c
index a5dbfc4725e..ea992de1fbc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return veorq_m_f32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return veorq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c
index 9ab271ac987..f2b8b91aa13 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return veorq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return veorq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c
index 45d5074e32b..c9573f732aa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return veorq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return veorq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c
index 5b8ac0a286e..86cb8ed31c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return veorq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return veorq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c
index e436a9e6536..7b2b1ea1596 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return veorq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return veorq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c
index 631abb515fd..3d3b2bbb4e6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return veorq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return veorq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c
index ba65042f986..7d2baba6e8e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return veorq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return veorq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c
index b49e35c887f..8275da1d7fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return veorq_s16 (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+/*
+**foo1:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return veorq (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c
index 9b6414b8458..ea111b4256d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return veorq_s32 (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+/*
+**foo1:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return veorq (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c
index 4a18bf5a165..f40dddcbb6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return veorq_s8 (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+/*
+**foo1:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return veorq (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c
index 90d5a5a6021..f16ddc14e09 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b)
{
return veorq_u16 (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+/*
+**foo1:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b)
{
return veorq (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c
index b6103d68638..33213c53aa7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b)
{
return veorq_u32 (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+/*
+**foo1:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b)
{
return veorq (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c
index 86fccc1bef0..aba155b1023 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b)
{
return veorq_u8 (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+/*
+**foo1:
+** ...
+** veor q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b)
{
return veorq (a, b);
}
-/* { dg-final { scan-assembler "veor" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c
index eb9e44cb777..8eac5ee6ae0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return veorq_x_f16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return veorq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c
index 3503250e5c3..3e71870daf0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return veorq_x_f32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return veorq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c
index 837210bb609..fd032647117 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return veorq_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return veorq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c
index 93796e333ab..ec67ddc761b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return veorq_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return veorq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c
index ed88d43834d..35a1dfdab8a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return veorq_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return veorq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c
index e6e82d8076d..7aad6d6f5c1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return veorq_x_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return veorq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c
index 17393d80233..315241581f8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return veorq_x_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return veorq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c
index 027968dab2d..615b1e645b1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return veorq_x_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** veort q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return veorq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c
index 8c926bdf1c3..18a184a0e98 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vfma.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16x8_t a, float16x8_t b, float16x8_t c)
+foo (float16x8_t add, float16x8_t m1, float16x8_t m2)
{
- return vfmaq_f16 (a, b, c);
+ return vfmaq_f16 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vfma.f16" } } */
+/*
+**foo1:
+** ...
+** vfma.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
+foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2)
{
- return vfmaq (a, b, c);
+ return vfmaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vfma.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c
index c2fff9a43ea..5d67439b11e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vfma.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32x4_t a, float32x4_t b, float32x4_t c)
+foo (float32x4_t add, float32x4_t m1, float32x4_t m2)
{
- return vfmaq_f32 (a, b, c);
+ return vfmaq_f32 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vfma.f32" } } */
+/*
+**foo1:
+** ...
+** vfma.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
+foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2)
{
- return vfmaq (a, b, c);
+ return vfmaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vfma.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c
index e8453e0cb41..e094cba8acb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+foo (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p)
{
- return vfmaq_m_f16 (a, b, c, p);
+ return vfmaq_m_f16 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p)
{
- return vfmaq_m (a, b, c, p);
+ return vfmaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c
index 9d1844eba5a..3003eff236a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+foo (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p)
{
- return vfmaq_m_f32 (a, b, c, p);
+ return vfmaq_m_f32 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p)
{
- return vfmaq_m (a, b, c, p);
+ return vfmaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c
index 888016e8164..4603f038467 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c
@@ -1,23 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
+foo (float16x8_t add, float16x8_t m1, float16_t m2, mve_pred16_t p)
{
- return vfmaq_m_n_f16 (a, b, c, p);
+ return vfmaq_m_n_f16 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
+foo1 (float16x8_t add, float16x8_t m1, float16_t m2, mve_pred16_t p)
{
- return vfmaq_m (a, b, c, p);
+ return vfmaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+float16x8_t
+foo2 (float16x8_t add, float16x8_t m1, mve_pred16_t p)
+{
+ return vfmaq_m (add, m1, 1.1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c
index f9afc8845b0..ad0ff907810 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c
@@ -1,23 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
+foo (float32x4_t add, float32x4_t m1, float32_t m2, mve_pred16_t p)
{
- return vfmaq_m_n_f32 (a, b, c, p);
+ return vfmaq_m_n_f32 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
+foo1 (float32x4_t add, float32x4_t m1, float32_t m2, mve_pred16_t p)
{
- return vfmaq_m (a, b, c, p);
+ return vfmaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmat.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+float32x4_t
+foo2 (float32x4_t add, float32x4_t m1, mve_pred16_t p)
+{
+ return vfmaq_m (add, m1, 1.1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c
index 208c46f5960..8e8738bc10a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vfma.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16x8_t a, float16x8_t b, float16_t c)
+foo (float16x8_t add, float16x8_t m1, float16_t m2)
{
- return vfmaq_n_f16 (a, b, c);
+ return vfmaq_n_f16 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vfma.f16" } } */
+/*
+**foo1:
+** ...
+** vfma.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c)
+foo1 (float16x8_t add, float16x8_t m1, float16_t m2)
{
- return vfmaq (a, b, c);
+ return vfmaq (add, m1, m2);
+}
+
+/*
+**foo2:
+** ...
+** vfma.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+float16x8_t
+foo2 (float16x8_t add, float16x8_t m1)
+{
+ return vfmaq (add, m1, 1.1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vfma.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c
index 664533239b7..4781e089ffb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vfma.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32x4_t a, float32x4_t b, float32_t c)
+foo (float32x4_t add, float32x4_t m1, float32_t m2)
{
- return vfmaq_n_f32 (a, b, c);
+ return vfmaq_n_f32 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vfma.f32" } } */
+/*
+**foo1:
+** ...
+** vfma.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c)
+foo1 (float32x4_t add, float32x4_t m1, float32_t m2)
{
- return vfmaq (a, b, c);
+ return vfmaq (add, m1, m2);
+}
+
+/*
+**foo2:
+** ...
+** vfma.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+float32x4_t
+foo2 (float32x4_t add, float32x4_t m1)
+{
+ return vfmaq (add, m1, 1.1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vfma.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
index 7f427bd6140..3f57b80874e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
@@ -62,4 +62,4 @@ foo2 (float16x8_t m1, float16x8_t m2, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
index 99a106982fa..728633f5c9e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
@@ -62,4 +62,4 @@ foo2 (float32x4_t m1, float32x4_t m2, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c
index ce9bf48d657..def309387fa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vfmas.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16x8_t a, float16x8_t b, float16_t c)
+foo (float16x8_t m1, float16x8_t m2, float16_t add)
{
- return vfmasq_n_f16 (a, b, c);
+ return vfmasq_n_f16 (m1, m2, add);
}
-/* { dg-final { scan-assembler "vfmas.f16" } } */
+/*
+**foo1:
+** ...
+** vfmas.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c)
+foo1 (float16x8_t m1, float16x8_t m2, float16_t add)
{
- return vfmasq (a, b, c);
+ return vfmasq (m1, m2, add);
+}
+
+/*
+**foo2:
+** ...
+** vfmas.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+float16x8_t
+foo2 (float16x8_t m1, float16x8_t m2)
+{
+ return vfmasq (m1, m2, 1.1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vfmas.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c
index 46c5a320644..c761bdcb109 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vfmas.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32x4_t a, float32x4_t b, float32_t c)
+foo (float32x4_t m1, float32x4_t m2, float32_t add)
{
- return vfmasq_n_f32 (a, b, c);
+ return vfmasq_n_f32 (m1, m2, add);
}
-/* { dg-final { scan-assembler "vfmas.f32" } } */
+/*
+**foo1:
+** ...
+** vfmas.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c)
+foo1 (float32x4_t m1, float32x4_t m2, float32_t add)
{
- return vfmasq (a, b, c);
+ return vfmasq (m1, m2, add);
+}
+
+/*
+**foo2:
+** ...
+** vfmas.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+float32x4_t
+foo2 (float32x4_t m1, float32x4_t m2)
+{
+ return vfmasq (m1, m2, 1.1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vfmas.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c
index 32475013fd4..607668ebc47 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vfms.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16x8_t a, float16x8_t b, float16x8_t c)
+foo (float16x8_t add, float16x8_t m1, float16x8_t m2)
{
- return vfmsq_f16 (a, b, c);
+ return vfmsq_f16 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vfms.f16" } } */
+/*
+**foo1:
+** ...
+** vfms.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
+foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2)
{
- return vfmsq (a, b, c);
+ return vfmsq (add, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vfms.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c
index fbdabd188d5..ac18e9e3d9c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vfms.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32x4_t a, float32x4_t b, float32x4_t c)
+foo (float32x4_t add, float32x4_t m1, float32x4_t m2)
{
- return vfmsq_f32 (a, b, c);
+ return vfmsq_f32 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vfms.f32" } } */
+/*
+**foo1:
+** ...
+** vfms.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
+foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2)
{
- return vfmsq (a, b, c);
+ return vfmsq (add, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vfms.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c
index ccbbfc1606c..f530e0b0614 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmst.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
-foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+foo (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p)
{
- return vfmsq_m_f16 (a, b, c, p);
+ return vfmsq_m_f16 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmst.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmst.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p)
{
- return vfmsq_m (a, b, c, p);
+ return vfmsq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmst.f16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c
index 219492a2ad9..6faca5a2e84 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmst.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
-foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+foo (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p)
{
- return vfmsq_m_f32 (a, b, c, p);
+ return vfmsq_m_f32 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmst.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vfmst.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p)
{
- return vfmsq_m (a, b, c, p);
+ return vfmsq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmst.f32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c
index f4a1311980a..7e39b75a7bf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vhcaddq_rot270_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vhcaddq_rot270_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c
index 4697eb25458..57096076913 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vhcaddq_rot270_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vhcaddq_rot270_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c
index ff547e83588..d47a99e29a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vhcaddq_rot270_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vhcaddq_rot270_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c
index 75346b2e349..01324c003c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vhcadd.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vhcaddq_rot270_s16 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s16" } } */
+/*
+**foo1:
+** ...
+** vhcadd.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vhcaddq_rot270 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c
index 0d458f100af..344d1ebf4a7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vhcadd.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vhcaddq_rot270_s32 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s32" } } */
+/*
+**foo1:
+** ...
+** vhcadd.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vhcaddq_rot270 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c
index 5106bb7d45b..0ee4cfb4095 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vhcadd.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vhcaddq_rot270_s8 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s8" } } */
+/*
+**foo1:
+** ...
+** vhcadd.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vhcaddq_rot270 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c
index 73f4784cd35..c3e70ad9e2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vhcaddq_rot270_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vhcaddq_rot270_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c
index 69c7cb7b0e6..6f14d2af44d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vhcaddq_rot270_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vhcaddq_rot270_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c
index df4aff74bff..32bfb6cf3bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vhcaddq_rot270_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vhcaddq_rot270_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c
index 5461fc26741..a7a870e78df 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vhcaddq_rot90_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vhcaddq_rot90_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c
index 20d2711aadb..1e6ef8f9aaa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vhcaddq_rot90_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vhcaddq_rot90_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c
index 55475753512..147d647d27f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vhcaddq_rot90_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vhcaddq_rot90_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c
index 539f9b00bd2..76747d669bb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vhcadd.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vhcaddq_rot90_s16 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s16" } } */
+/*
+**foo1:
+** ...
+** vhcadd.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vhcaddq_rot90 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c
index 841c5294253..8b9b8ad7aa9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vhcadd.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vhcaddq_rot90_s32 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s32" } } */
+/*
+**foo1:
+** ...
+** vhcadd.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vhcaddq_rot90 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c
index d2992c2f280..5e9b004f7cc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vhcadd.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vhcaddq_rot90_s8 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s8" } } */
+/*
+**foo1:
+** ...
+** vhcadd.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vhcaddq_rot90 (a, b);
}
-/* { dg-final { scan-assembler "vhcadd.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c
index 0d677f7f149..d3416d65658 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vhcaddq_rot90_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vhcaddq_rot90_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c
index a54af77440f..b0255e5141c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vhcaddq_rot90_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vhcaddq_rot90_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c
index 5205cd37deb..10f5f31f26e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vhcaddq_rot90_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vhcaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vhcaddq_rot90_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c
index 2a7a79e62ea..f05d04b1f3d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmladavq_p_s16 (a, b, p);
+ return vmladavq_p_s16 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmladavt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmladavq_p (a, b, p);
+ return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavt.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c
index 6b118144075..397bb9fb4ec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmladavq_p_s32 (a, b, p);
+ return vmladavq_p_s32 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmladavt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmladavq_p (a, b, p);
+ return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavt.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c
index b3a4e11fa24..25c11d200ad 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
+foo (int8x16_t m1, int8x16_t m2, mve_pred16_t p)
{
- return vmladavq_p_s8 (a, b, p);
+ return vmladavq_p_s8 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmladavt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+foo1 (int8x16_t m1, int8x16_t m2, mve_pred16_t p)
{
- return vmladavq_p (a, b, p);
+ return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavt.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c
index 0ff2ffdc5f2..064d2c22a23 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+foo (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
{
- return vmladavq_p_u16 (a, b, p);
+ return vmladavq_p_u16 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmladavt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+foo1 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
{
- return vmladavq_p (a, b, p);
+ return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavt.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c
index c5d213d4c0b..f5f3de9f0e8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+foo (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
{
- return vmladavq_p_u32 (a, b, p);
+ return vmladavq_p_u32 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmladavt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+foo1 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
{
- return vmladavq_p (a, b, p);
+ return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavt.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c
index 6fcc530c17c..243e61715e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+foo (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p)
{
- return vmladavq_p_u8 (a, b, p);
+ return vmladavq_p_u8 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmladavt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavt.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+foo1 (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p)
{
- return vmladavq_p (a, b, p);
+ return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavt.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c
index a140be6204d..b0ff042fc43 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmladav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int16x8_t a, int16x8_t b)
+foo (int16x8_t m1, int16x8_t m2)
{
- return vmladavq_s16 (a, b);
+ return vmladavq_s16 (m1, m2);
}
-/* { dg-final { scan-assembler "vmladav.s16" } } */
+/*
+**foo1:
+** ...
+** vmladav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int16x8_t a, int16x8_t b)
+foo1 (int16x8_t m1, int16x8_t m2)
{
- return vmladavq (a, b);
+ return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladav.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c
index 1413e480551..a2ef4b37e4d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmladav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int32x4_t a, int32x4_t b)
+foo (int32x4_t m1, int32x4_t m2)
{
- return vmladavq_s32 (a, b);
+ return vmladavq_s32 (m1, m2);
}
-/* { dg-final { scan-assembler "vmladav.s32" } } */
+/*
+**foo1:
+** ...
+** vmladav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int32x4_t a, int32x4_t b)
+foo1 (int32x4_t m1, int32x4_t m2)
{
- return vmladavq (a, b);
+ return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladav.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c
index d43dbb9fefc..e3e6e2982d7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmladav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int8x16_t a, int8x16_t b)
+foo (int8x16_t m1, int8x16_t m2)
{
- return vmladavq_s8 (a, b);
+ return vmladavq_s8 (m1, m2);
}
-/* { dg-final { scan-assembler "vmladav.s8" } } */
+/*
+**foo1:
+** ...
+** vmladav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int8x16_t a, int8x16_t b)
+foo1 (int8x16_t m1, int8x16_t m2)
{
- return vmladavq (a, b);
+ return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladav.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c
index e1c44d7b4ce..d021bc0e30d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmladav.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo (uint16x8_t a, uint16x8_t b)
+foo (uint16x8_t m1, uint16x8_t m2)
{
- return vmladavq_u16 (a, b);
+ return vmladavq_u16 (m1, m2);
}
-/* { dg-final { scan-assembler "vmladav.u16" } } */
+/*
+**foo1:
+** ...
+** vmladav.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo1 (uint16x8_t a, uint16x8_t b)
+foo1 (uint16x8_t m1, uint16x8_t m2)
{
- return vmladavq (a, b);
+ return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladav.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c
index 5e9bb56bae0..0848ca25b9f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmladav.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo (uint32x4_t a, uint32x4_t b)
+foo (uint32x4_t m1, uint32x4_t m2)
{
- return vmladavq_u32 (a, b);
+ return vmladavq_u32 (m1, m2);
}
-/* { dg-final { scan-assembler "vmladav.u32" } } */
+/*
+**foo1:
+** ...
+** vmladav.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo1 (uint32x4_t a, uint32x4_t b)
+foo1 (uint32x4_t m1, uint32x4_t m2)
{
- return vmladavq (a, b);
+ return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladav.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c
index f4223538170..2a735fbb654 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmladav.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo (uint8x16_t a, uint8x16_t b)
+foo (uint8x16_t m1, uint8x16_t m2)
{
- return vmladavq_u8 (a, b);
+ return vmladavq_u8 (m1, m2);
}
-/* { dg-final { scan-assembler "vmladav.u8" } } */
+/*
+**foo1:
+** ...
+** vmladav.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32_t
-foo1 (uint8x16_t a, uint8x16_t b)
+foo1 (uint8x16_t m1, uint8x16_t m2)
{
- return vmladavq (a, b);
+ return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladav.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c
index 7ee875eae6b..dc94ecada57 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmladavxq_p_s16 (a, b, p);
+ return vmladavxq_p_s16 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmladavxt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmladavxq_p (a, b, p);
+ return vmladavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavxt.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c
index d4f92ba9cf2..15a2abd7d13 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmladavxq_p_s32 (a, b, p);
+ return vmladavxq_p_s32 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmladavxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmladavxq_p (a, b, p);
+ return vmladavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavxt.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c
index d5f14c51ae8..e56874151a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
+foo (int8x16_t m1, int8x16_t m2, mve_pred16_t p)
{
- return vmladavxq_p_s8 (a, b, p);
+ return vmladavxq_p_s8 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmladavxt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmladavxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+foo1 (int8x16_t m1, int8x16_t m2, mve_pred16_t p)
{
- return vmladavxq_p (a, b, p);
+ return vmladavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavxt.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c
index deac58d768e..e7e3b571efb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmladavx.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int16x8_t a, int16x8_t b)
+foo (int16x8_t m1, int16x8_t m2)
{
- return vmladavxq_s16 (a, b);
+ return vmladavxq_s16 (m1, m2);
}
-/* { dg-final { scan-assembler "vmladavx.s16" } } */
+/*
+**foo1:
+** ...
+** vmladavx.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int16x8_t a, int16x8_t b)
+foo1 (int16x8_t m1, int16x8_t m2)
{
- return vmladavxq (a, b);
+ return vmladavxq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavx.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c
index 56516d74173..c3841f59d57 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmladavx.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int32x4_t a, int32x4_t b)
+foo (int32x4_t m1, int32x4_t m2)
{
- return vmladavxq_s32 (a, b);
+ return vmladavxq_s32 (m1, m2);
}
-/* { dg-final { scan-assembler "vmladavx.s32" } } */
+/*
+**foo1:
+** ...
+** vmladavx.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int32x4_t a, int32x4_t b)
+foo1 (int32x4_t m1, int32x4_t m2)
{
- return vmladavxq (a, b);
+ return vmladavxq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavx.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c
index 3b1e8cd67cd..59cdc346ee5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmladavx.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo (int8x16_t a, int8x16_t b)
+foo (int8x16_t m1, int8x16_t m2)
{
- return vmladavxq_s8 (a, b);
+ return vmladavxq_s8 (m1, m2);
}
-/* { dg-final { scan-assembler "vmladavx.s8" } } */
+/*
+**foo1:
+** ...
+** vmladavx.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
-foo1 (int8x16_t a, int8x16_t b)
+foo1 (int8x16_t m1, int8x16_t m2)
{
- return vmladavxq (a, b);
+ return vmladavxq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmladavx.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c
index 246b40fbe2c..fbdbb5c16a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmlaldavaq_p_s16 (a, b, c, p);
+ return vmlaldavaq_p_s16 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavat.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo1 (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmlaldavaq_p (a, b, c, p);
+ return vmlaldavaq_p (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavat.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c
index 6563af20061..9c59d0306a1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmlaldavaq_p_s32 (a, b, c, p);
+ return vmlaldavaq_p_s32 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavat.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo1 (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmlaldavaq_p (a, b, c, p);
+ return vmlaldavaq_p (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavat.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c
index 632e29f972d..b714b677339 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c
@@ -1,21 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+foo (uint64_t add, uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
{
- return vmlaldavaq_p_u16 (a, b, c, p);
+ return vmlaldavaq_p_u16 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavat.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo1 (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+foo1 (uint64_t add, uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
{
- return vmlaldavaq_p (a, b, c, p);
+ return vmlaldavaq_p (add, m1, m2, p);
+}
+
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+uint64_t
+foo2 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
+{
+ return vmlaldavaq_p (1, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavat.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c
index d2fcd5d14ed..29419a06458 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c
@@ -1,21 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+foo (uint64_t add, uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
{
- return vmlaldavaq_p_u32 (a, b, c, p);
+ return vmlaldavaq_p_u32 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavat.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo1 (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+foo1 (uint64_t add, uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
{
- return vmlaldavaq_p (a, b, c, p);
+ return vmlaldavaq_p (add, m1, m2, p);
+}
+
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavat.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+uint64_t
+foo2 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
+{
+ return vmlaldavaq_p (1, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavat.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c
index 1cb9b6ebc41..d1f049923c0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldava.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int64_t a, int16x8_t b, int16x8_t c)
+foo (int64_t add, int16x8_t m1, int16x8_t m2)
{
- return vmlaldavaq_s16 (a, b, c);
+ return vmlaldavaq_s16 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldava.s16" } } */
+/*
+**foo1:
+** ...
+** vmlaldava.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int64_t a, int16x8_t b, int16x8_t c)
+foo1 (int64_t add, int16x8_t m1, int16x8_t m2)
{
- return vmlaldavaq (a, b, c);
+ return vmlaldavaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldava.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c
index 56e59f5929d..dfce7d8f625 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldava.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int64_t a, int32x4_t b, int32x4_t c)
+foo (int64_t add, int32x4_t m1, int32x4_t m2)
{
- return vmlaldavaq_s32 (a, b, c);
+ return vmlaldavaq_s32 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldava.s32" } } */
+/*
+**foo1:
+** ...
+** vmlaldava.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int64_t a, int32x4_t b, int32x4_t c)
+foo1 (int64_t add, int32x4_t m1, int32x4_t m2)
{
- return vmlaldavaq (a, b, c);
+ return vmlaldavaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldava.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c
index 7c95abc271c..7e42054a4f3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldava.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo (uint64_t a, uint16x8_t b, uint16x8_t c)
+foo (uint64_t add, uint16x8_t m1, uint16x8_t m2)
{
- return vmlaldavaq_u16 (a, b, c);
+ return vmlaldavaq_u16 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldava.u16" } } */
+/*
+**foo1:
+** ...
+** vmlaldava.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo1 (uint64_t a, uint16x8_t b, uint16x8_t c)
+foo1 (uint64_t add, uint16x8_t m1, uint16x8_t m2)
{
- return vmlaldavaq (a, b, c);
+ return vmlaldavaq (add, m1, m2);
+}
+
+/*
+**foo2:
+** ...
+** vmlaldava.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+uint64_t
+foo2 (uint16x8_t m1, uint16x8_t m2)
+{
+ return vmlaldavaq (1, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldava.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c
index 239f5e32d8b..20ba6d377bf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldava.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo (uint64_t a, uint32x4_t b, uint32x4_t c)
+foo (uint64_t add, uint32x4_t m1, uint32x4_t m2)
{
- return vmlaldavaq_u32 (a, b, c);
+ return vmlaldavaq_u32 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldava.u32" } } */
+/*
+**foo1:
+** ...
+** vmlaldava.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo1 (uint64_t a, uint32x4_t b, uint32x4_t c)
+foo1 (uint64_t add, uint32x4_t m1, uint32x4_t m2)
{
- return vmlaldavaq (a, b, c);
+ return vmlaldavaq (add, m1, m2);
+}
+
+/*
+**foo2:
+** ...
+** vmlaldava.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+uint64_t
+foo2 (uint32x4_t m1, uint32x4_t m2)
+{
+ return vmlaldavaq (1, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldava.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c
index 11e32c76d5a..7c2f07f3495 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c
@@ -46,4 +46,4 @@ foo1 (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c
index 937fab4166c..6214235487b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c
@@ -46,4 +46,4 @@ foo1 (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c
index 4f10ec7d098..b5922b8c281 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c
@@ -38,4 +38,4 @@ foo1 (int64_t add, int16x8_t m1, int16x8_t m2)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c
index 1d78a7cd269..124125e2f29 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c
@@ -38,4 +38,4 @@ foo1 (int64_t add, int32x4_t m1, int32x4_t m2)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c
index 008efd95a35..de9cc0ed9c4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmlaldavq_p_s16 (a, b, p);
+ return vmlaldavq_p_s16 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmlaldavq_p (a, b, p);
+ return vmlaldavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavt.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c
index e824e6b7ce0..a2b1c59291b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmlaldavq_p_s32 (a, b, p);
+ return vmlaldavq_p_s32 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmlaldavq_p (a, b, p);
+ return vmlaldavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavt.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c
index 1fea6d5c117..6034b9b5454 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavt.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+foo (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
{
- return vmlaldavq_p_u16 (a, b, p);
+ return vmlaldavq_p_u16 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavt.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+foo1 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
{
- return vmlaldavq_p (a, b, p);
+ return vmlaldavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavt.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c
index 99300fcb6ec..a85d7de4dad 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavt.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+foo (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
{
- return vmlaldavq_p_u32 (a, b, p);
+ return vmlaldavq_p_u32 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavt.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+foo1 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
{
- return vmlaldavq_p (a, b, p);
+ return vmlaldavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavt.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c
index 1cdb44920e1..b18e8eb149e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldav.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int16x8_t a, int16x8_t b)
+foo (int16x8_t m1, int16x8_t m2)
{
- return vmlaldavq_s16 (a, b);
+ return vmlaldavq_s16 (m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldav.s16" } } */
+/*
+**foo1:
+** ...
+** vmlaldav.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int16x8_t a, int16x8_t b)
+foo1 (int16x8_t m1, int16x8_t m2)
{
- return vmlaldavq (a, b);
+ return vmlaldavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldav.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c
index 123ca0f4eeb..b0fe1c5132c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldav.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int32x4_t a, int32x4_t b)
+foo (int32x4_t m1, int32x4_t m2)
{
- return vmlaldavq_s32 (a, b);
+ return vmlaldavq_s32 (m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldav.s32" } } */
+/*
+**foo1:
+** ...
+** vmlaldav.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int32x4_t a, int32x4_t b)
+foo1 (int32x4_t m1, int32x4_t m2)
{
- return vmlaldavq (a, b);
+ return vmlaldavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldav.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c
index c9c40eeac0a..d1fcf715cb7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldav.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo (uint16x8_t a, uint16x8_t b)
+foo (uint16x8_t m1, uint16x8_t m2)
{
- return vmlaldavq_u16 (a, b);
+ return vmlaldavq_u16 (m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldav.u16" } } */
+/*
+**foo1:
+** ...
+** vmlaldav.u16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo1 (uint16x8_t a, uint16x8_t b)
+foo1 (uint16x8_t m1, uint16x8_t m2)
{
- return vmlaldavq (a, b);
+ return vmlaldavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldav.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c
index 4d1754697bf..76726e8255b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldav.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo (uint32x4_t a, uint32x4_t b)
+foo (uint32x4_t m1, uint32x4_t m2)
{
- return vmlaldavq_u32 (a, b);
+ return vmlaldavq_u32 (m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldav.u32" } } */
+/*
+**foo1:
+** ...
+** vmlaldav.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
-foo1 (uint32x4_t a, uint32x4_t b)
+foo1 (uint32x4_t m1, uint32x4_t m2)
{
- return vmlaldavq (a, b);
+ return vmlaldavq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldav.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c
index d41c2e16114..3b8392bcf7f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmlaldavxq_p_s16 (a, b, p);
+ return vmlaldavxq_p_s16 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavxt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
{
- return vmlaldavxq_p (a, b, p);
+ return vmlaldavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavxt.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c
index 8ad7b219a0f..578b7b68095 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmlaldavxq_p_s32 (a, b, p);
+ return vmlaldavxq_p_s32 (m1, m2, p);
}
-/* { dg-final { scan-assembler "vmlaldavxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlaldavxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
{
- return vmlaldavxq_p (a, b, p);
+ return vmlaldavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavxt.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c
index ebe999393e8..7061bd2c13d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldavx.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int16x8_t a, int16x8_t b)
+foo (int16x8_t m1, int16x8_t m2)
{
- return vmlaldavxq_s16 (a, b);
+ return vmlaldavxq_s16 (m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldavx.s16" } } */
+/*
+**foo1:
+** ...
+** vmlaldavx.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int16x8_t a, int16x8_t b)
+foo1 (int16x8_t m1, int16x8_t m2)
{
- return vmlaldavxq (a, b);
+ return vmlaldavxq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavx.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c
index 0417eb867de..957dc174a36 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlaldavx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo (int32x4_t a, int32x4_t b)
+foo (int32x4_t m1, int32x4_t m2)
{
- return vmlaldavxq_s32 (a, b);
+ return vmlaldavxq_s32 (m1, m2);
}
-/* { dg-final { scan-assembler "vmlaldavx.s32" } } */
+/*
+**foo1:
+** ...
+** vmlaldavx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
-foo1 (int32x4_t a, int32x4_t b)
+foo1 (int32x4_t m1, int32x4_t m2)
{
- return vmlaldavxq (a, b);
+ return vmlaldavxq (m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmlaldavx.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c
index d48b020d595..f68fe8e49a3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
{
- return vmlaq_m_n_s16 (a, b, c, p);
+ return vmlaq_m_n_s16 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo1 (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
{
- return vmlaq_m (a, b, c, p);
+ return vmlaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c
index 315c1afc2c7..d3c49553596 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
{
- return vmlaq_m_n_s32 (a, b, c, p);
+ return vmlaq_m_n_s32 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo1 (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
{
- return vmlaq_m (a, b, c, p);
+ return vmlaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c
index a452f5de5e6..44dc3b57cdd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
{
- return vmlaq_m_n_s8 (a, b, c, p);
+ return vmlaq_m_n_s8 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo1 (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
{
- return vmlaq_m (a, b, c, p);
+ return vmlaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c
index 6ecdc689a61..cbb92fb39b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c
@@ -1,23 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p)
+foo (uint16x8_t add, uint16x8_t m1, uint16_t m2, mve_pred16_t p)
{
- return vmlaq_m_n_u16 (a, b, c, p);
+ return vmlaq_m_n_u16 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
-foo1 (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p)
+foo1 (uint16x8_t add, uint16x8_t m1, uint16_t m2, mve_pred16_t p)
{
- return vmlaq_m (a, b, c, p);
+ return vmlaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo2 (uint16x8_t add, uint16x8_t m1, mve_pred16_t p)
+{
+ return vmlaq_m (add, m1, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c
index 2c584a635e7..569ea91af36 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c
@@ -1,23 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p)
+foo (uint32x4_t add, uint32x4_t m1, uint32_t m2, mve_pred16_t p)
{
- return vmlaq_m_n_u32 (a, b, c, p);
+ return vmlaq_m_n_u32 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p)
+foo1 (uint32x4_t add, uint32x4_t m1, uint32_t m2, mve_pred16_t p)
{
- return vmlaq_m (a, b, c, p);
+ return vmlaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint32x4_t
+foo2 (uint32x4_t add, uint32x4_t m1, mve_pred16_t p)
+{
+ return vmlaq_m (add, m1, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c
index b75b3c95916..592ad3e072a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c
@@ -1,23 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
-foo (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p)
+foo (uint8x16_t add, uint8x16_t m1, uint8_t m2, mve_pred16_t p)
{
- return vmlaq_m_n_u8 (a, b, c, p);
+ return vmlaq_m_n_u8 (add, m1, m2, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
-foo1 (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p)
+foo1 (uint8x16_t add, uint8x16_t m1, uint8_t m2, mve_pred16_t p)
{
- return vmlaq_m (a, b, c, p);
+ return vmlaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlat.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint8x16_t
+foo2 (uint8x16_t add, uint8x16_t m1, mve_pred16_t p)
+{
+ return vmlaq_m (add, m1, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c
index 29543c8f60d..d1fa73de1c9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmla.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c)
+foo (int16x8_t add, int16x8_t m1, int16_t m2)
{
- return vmlaq_n_s16 (a, b, c);
+ return vmlaq_n_s16 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmla.s16" } } */
+/*
+**foo1:
+** ...
+** vmla.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c)
+foo1 (int16x8_t add, int16x8_t m1, int16_t m2)
{
- return vmlaq (a, b, c);
+ return vmlaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmla.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c
index d74bacaffd7..c349c0c8d7f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmla.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c)
+foo (int32x4_t add, int32x4_t m1, int32_t m2)
{
- return vmlaq_n_s32 (a, b, c);
+ return vmlaq_n_s32 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmla.s32" } } */
+/*
+**foo1:
+** ...
+** vmla.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c)
+foo1 (int32x4_t add, int32x4_t m1, int32_t m2)
{
- return vmlaq (a, b, c);
+ return vmlaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmla.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c
index 38dd01a6580..c1cd39e5715 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmla.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c)
+foo (int8x16_t add, int8x16_t m1, int8_t m2)
{
- return vmlaq_n_s8 (a, b, c);
+ return vmlaq_n_s8 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmla.s8" } } */
+/*
+**foo1:
+** ...
+** vmla.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c)
+foo1 (int8x16_t add, int8x16_t m1, int8_t m2)
{
- return vmlaq (a, b, c);
+ return vmlaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmla.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c
index 55a5d0601d5..5eb201c05e8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmla.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint16x8_t a, uint16x8_t b, uint16_t c)
+foo (uint16x8_t add, uint16x8_t m1, uint16_t m2)
{
- return vmlaq_n_u16 (a, b, c);
+ return vmlaq_n_u16 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmla.u16" } } */
+/*
+**foo1:
+** ...
+** vmla.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
-foo1 (uint16x8_t a, uint16x8_t b, uint16_t c)
+foo1 (uint16x8_t add, uint16x8_t m1, uint16_t m2)
{
- return vmlaq (a, b, c);
+ return vmlaq (add, m1, m2);
+}
+
+/*
+**foo2:
+** ...
+** vmla.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo2 (uint16x8_t add, uint16x8_t m1)
+{
+ return vmlaq (add, m1, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmla.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c
index e160275a29b..d4820ea65d9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmla.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, uint32_t c)
+foo (uint32x4_t add, uint32x4_t m1, uint32_t m2)
{
- return vmlaq_n_u32 (a, b, c);
+ return vmlaq_n_u32 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmla.u32" } } */
+/*
+**foo1:
+** ...
+** vmla.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, uint32_t c)
+foo1 (uint32x4_t add, uint32x4_t m1, uint32_t m2)
{
- return vmlaq (a, b, c);
+ return vmlaq (add, m1, m2);
+}
+
+/*
+**foo2:
+** ...
+** vmla.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint32x4_t
+foo2 (uint32x4_t add, uint32x4_t m1)
+{
+ return vmlaq (add, m1, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmla.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c
index 5f0edef53d4..7f83f092b07 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmla.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
-foo (uint8x16_t a, uint8x16_t b, uint8_t c)
+foo (uint8x16_t add, uint8x16_t m1, uint8_t m2)
{
- return vmlaq_n_u8 (a, b, c);
+ return vmlaq_n_u8 (add, m1, m2);
}
-/* { dg-final { scan-assembler "vmla.u8" } } */
+/*
+**foo1:
+** ...
+** vmla.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
-foo1 (uint8x16_t a, uint8x16_t b, uint8_t c)
+foo1 (uint8x16_t add, uint8x16_t m1, uint8_t m2)
{
- return vmlaq (a, b, c);
+ return vmlaq (add, m1, m2);
+}
+
+/*
+**foo2:
+** ...
+** vmla.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
+uint8x16_t
+foo2 (uint8x16_t add, uint8x16_t m1)
+{
+ return vmlaq (add, m1, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmla.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c
index 3b250c1bf79..e8d1b5fd3d0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavat.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
{
return vmlsdavaq_p_s16 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavat.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavat.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
{
return vmlsdavaq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavat.s16" } } */
-/* { dg-final { scan-assembler "vmlsdavat.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c
index 077c5980e66..effbf24d997 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavat.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vmlsdavaq_p_s32 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavat.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavat.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vmlsdavaq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavat.s32" } } */
-/* { dg-final { scan-assembler "vmlsdavat.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c
index 2e53f5530b1..de04f9fd089 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavat.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
{
return vmlsdavaq_p_s8 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavat.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavat.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
{
return vmlsdavaq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavat.s8" } } */
-/* { dg-final { scan-assembler "vmlsdavat.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c
index e127be940b4..f66f652f6fd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdava.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int16x8_t b, int16x8_t c)
{
return vmlsdavaq_s16 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdava.s16" } } */
+/*
+**foo1:
+** ...
+** vmlsdava.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int16x8_t b, int16x8_t c)
{
return vmlsdavaq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdava.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c
index 20f879c6b69..79ba85ddb02 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdava.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int32x4_t b, int32x4_t c)
{
return vmlsdavaq_s32 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdava.s32" } } */
+/*
+**foo1:
+** ...
+** vmlsdava.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int32x4_t b, int32x4_t c)
{
return vmlsdavaq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdava.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c
index 3cbed73f660..3e0f9dc2649 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdava.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int8x16_t b, int8x16_t c)
{
return vmlsdavaq_s8 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdava.s8" } } */
+/*
+**foo1:
+** ...
+** vmlsdava.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int8x16_t b, int8x16_t c)
{
return vmlsdavaq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdava.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c
index 37aee878b97..61e88ce8fb8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavaxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
{
return vmlsdavaxq_p_s16 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavaxt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavaxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
{
return vmlsdavaxq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavaxt.s16" } } */
-/* { dg-final { scan-assembler "vmlsdavaxt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c
index 6a15d3cf97b..cbc2c71423e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavaxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vmlsdavaxq_p_s32 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavaxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavaxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vmlsdavaxq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavaxt.s32" } } */
-/* { dg-final { scan-assembler "vmlsdavaxt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c
index d090e625e1b..2b30e8a9c12 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavaxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
{
return vmlsdavaxq_p_s8 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavaxt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavaxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
{
return vmlsdavaxq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsdavaxt.s8" } } */
-/* { dg-final { scan-assembler "vmlsdavaxt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c
index 0ef5302ef80..90fd85a170e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdavax.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int16x8_t b, int16x8_t c)
{
return vmlsdavaxq_s16 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdavax.s16" } } */
+/*
+**foo1:
+** ...
+** vmlsdavax.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int16x8_t b, int16x8_t c)
{
return vmlsdavaxq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdavax.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c
index 71a5e1a987f..06fe27faf49 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdavax.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int32x4_t b, int32x4_t c)
{
return vmlsdavaxq_s32 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdavax.s32" } } */
+/*
+**foo1:
+** ...
+** vmlsdavax.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int32x4_t b, int32x4_t c)
{
return vmlsdavaxq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdavax.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c
index 7df6b9f7f32..70a44b49d8e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdavax.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32_t a, int8x16_t b, int8x16_t c)
{
return vmlsdavaxq_s8 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdavax.s8" } } */
+/*
+**foo1:
+** ...
+** vmlsdavax.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32_t a, int8x16_t b, int8x16_t c)
{
return vmlsdavaxq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsdavax.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c
index f71dda19c57..09db9a3a90a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vmlsdavq_p_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vmlsdavq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c
index 255235ba372..8eb9d24263a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vmlsdavq_p_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vmlsdavq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c
index 2fc892db2eb..166fedea45c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vmlsdavq_p_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vmlsdavq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c
index 7376b07865b..b97252f7225 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int16x8_t a, int16x8_t b)
{
return vmlsdavq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vmlsdav.s16" } } */
+/*
+**foo1:
+** ...
+** vmlsdav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int16x8_t a, int16x8_t b)
{
return vmlsdavq (a, b);
}
-/* { dg-final { scan-assembler "vmlsdav.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c
index a37042eab30..5473cfe22fc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32x4_t a, int32x4_t b)
{
return vmlsdavq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vmlsdav.s32" } } */
+/*
+**foo1:
+** ...
+** vmlsdav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32x4_t a, int32x4_t b)
{
return vmlsdavq (a, b);
}
-/* { dg-final { scan-assembler "vmlsdav.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c
index b44b98bc7e4..487097118fd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int8x16_t a, int8x16_t b)
{
return vmlsdavq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vmlsdav.s8" } } */
+/*
+**foo1:
+** ...
+** vmlsdav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int8x16_t a, int8x16_t b)
{
return vmlsdavq (a, b);
}
-/* { dg-final { scan-assembler "vmlsdav.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c
index aa4ac4e4f01..d1ff9a0fa1c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vmlsdavxq_p_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavxt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavxt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vmlsdavxq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavxt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c
index 0de81290d99..09c19c1f161 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vmlsdavxq_p_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavxt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vmlsdavxq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavxt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c
index 68588f6951a..1f364a3e846 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vmlsdavxq_p_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavxt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsdavxt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vmlsdavxq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsdavxt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c
index 8f49d6a6106..1c0675fb44b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdavx.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int16x8_t a, int16x8_t b)
{
return vmlsdavxq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vmlsdavx.s16" } } */
+/*
+**foo1:
+** ...
+** vmlsdavx.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int16x8_t a, int16x8_t b)
{
return vmlsdavxq (a, b);
}
-/* { dg-final { scan-assembler "vmlsdavx.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c
index 830cd4ca8b1..5986e130ec0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdavx.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int32x4_t a, int32x4_t b)
{
return vmlsdavxq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vmlsdavx.s32" } } */
+/*
+**foo1:
+** ...
+** vmlsdavx.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int32x4_t a, int32x4_t b)
{
return vmlsdavxq (a, b);
}
-/* { dg-final { scan-assembler "vmlsdavx.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c
index 74feb60b005..4f8aa44b57a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsdavx.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo (int8x16_t a, int8x16_t b)
{
return vmlsdavxq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vmlsdavx.s8" } } */
+/*
+**foo1:
+** ...
+** vmlsdavx.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32_t
foo1 (int8x16_t a, int8x16_t b)
{
return vmlsdavxq (a, b);
}
-/* { dg-final { scan-assembler "vmlsdavx.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c
index 78d29b058a3..8d0a03c0213 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavat.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
{
return vmlsldavaq_p_s16 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsldavat.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavat.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
{
return vmlsldavaq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsldavat.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c
index fca0ef1d3dc..fae2ad5c713 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vmlsldavaq_p_s32 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsldavat.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vmlsldavaq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsldavat.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c
index aecfcee4571..bfe4010df68 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsldava.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int16x8_t b, int16x8_t c)
{
return vmlsldavaq_s16 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsldava.s16" } } */
+/*
+**foo1:
+** ...
+** vmlsldava.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int16x8_t b, int16x8_t c)
{
return vmlsldavaq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsldava.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c
index 7344a50f02b..b023b1b67ee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsldava.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c)
{
return vmlsldavaq_s32 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsldava.s32" } } */
+/*
+**foo1:
+** ...
+** vmlsldava.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c)
{
return vmlsldavaq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsldava.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c
index 5278bd842cc..1ffa8c28ea9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavaxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
{
return vmlsldavaxq_p_s16 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsldavaxt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavaxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
{
return vmlsldavaxq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsldavaxt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c
index 07efdf96f10..aa5001705c1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vmlsldavaxq_p_s32 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsldavaxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vmlsldavaxq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vmlsldavaxt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c
index 6a51d9f3d93..7772b3da069 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsldavax.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int16x8_t b, int16x8_t c)
{
return vmlsldavaxq_s16 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsldavax.s16" } } */
+/*
+**foo1:
+** ...
+** vmlsldavax.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int16x8_t b, int16x8_t c)
{
return vmlsldavaxq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsldavax.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c
index 275776388d2..eba923f15d8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsldavax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c)
{
return vmlsldavaxq_s32 (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsldavax.s32" } } */
+/*
+**foo1:
+** ...
+** vmlsldavax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c)
{
return vmlsldavaxq (a, b, c);
}
-/* { dg-final { scan-assembler "vmlsldavax.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c
index 6eedf07efd6..79ed4c94b64 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vmlsldavq_p_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsldavt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vmlsldavq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsldavt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c
index b36ea49612c..44982f89edf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vmlsldavq_p_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsldavt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vmlsldavq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsldavt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c
index f05841798c9..dbdf1deae04 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsldav.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int16x8_t a, int16x8_t b)
{
return vmlsldavq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vmlsldav.s16" } } */
+/*
+**foo1:
+** ...
+** vmlsldav.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int16x8_t a, int16x8_t b)
{
return vmlsldavq (a, b);
}
-/* { dg-final { scan-assembler "vmlsldav.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c
index 45bee16ab79..458f14c446f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsldav.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b)
{
return vmlsldavq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vmlsldav.s32" } } */
+/*
+**foo1:
+** ...
+** vmlsldav.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b)
{
return vmlsldavq (a, b);
}
-/* { dg-final { scan-assembler "vmlsldav.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c
index 821f4eae90a..9481550f526 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vmlsldavxq_p_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsldavxt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavxt.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vmlsldavxq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsldavxt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c
index 77e84d07486..cc20e554932 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vmlsldavxq_p_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsldavxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmlsldavxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vmlsldavxq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vmlsldavxt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c
index dcd88f8db73..7a4d9365ed6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsldavx.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int16x8_t a, int16x8_t b)
{
return vmlsldavxq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vmlsldavx.s16" } } */
+/*
+**foo1:
+** ...
+** vmlsldavx.s16 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int16x8_t a, int16x8_t b)
{
return vmlsldavxq (a, b);
}
-/* { dg-final { scan-assembler "vmlsldavx.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c
index d59550ba69e..b241569d75c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmlsldavx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b)
{
return vmlsldavxq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vmlsldavx.s32" } } */
+/*
+**foo1:
+** ...
+** vmlsldavx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b)
{
return vmlsldavxq (a, b);
}
-/* { dg-final { scan-assembler "vmlsldavx.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c
index b7ce6ce9c2a..69c2f91b50e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
{
return vmovlbq_m_s16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
{
return vmovlbq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c
index d15df32831d..2b3cfacb5f3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
{
return vmovlbq_m_s8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
{
return vmovlbq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c
index dcd9dc43692..39398b2cde9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vmovlbq_m_u16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vmovlbq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c
index dbdeb263086..30ca18ad103 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vmovlbq_m_u8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vmovlbq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c
index a6b5cbb1527..8ce0da68113 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovlb.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int16x8_t a)
{
return vmovlbq_s16 (a);
}
-/* { dg-final { scan-assembler "vmovlb.s16" } } */
+/*
+**foo1:
+** ...
+** vmovlb.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int16x8_t a)
{
return vmovlbq (a);
}
-/* { dg-final { scan-assembler "vmovlb.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c
index 4ead765bb6e..36fbce37bf8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovlb.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int8x16_t a)
{
return vmovlbq_s8 (a);
}
-/* { dg-final { scan-assembler "vmovlb.s8" } } */
+/*
+**foo1:
+** ...
+** vmovlb.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int8x16_t a)
{
return vmovlbq (a);
}
-/* { dg-final { scan-assembler "vmovlb.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c
index fec88bb7f79..b90728e9956 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovlb.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint16x8_t a)
{
- return vmovlbq_u16 (a);
+ return vmovlbq_u16 (a);
}
-/* { dg-final { scan-assembler "vmovlb.u16" } } */
+/*
+**foo1:
+** ...
+** vmovlb.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint16x8_t a)
{
- return vmovlbq (a);
+ return vmovlbq (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmovlb.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c
index af6d804696a..5299f581329 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovlb.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint8x16_t a)
{
- return vmovlbq_u8 (a);
+ return vmovlbq_u8 (a);
}
-/* { dg-final { scan-assembler "vmovlb.u8" } } */
+/*
+**foo1:
+** ...
+** vmovlb.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint8x16_t a)
{
- return vmovlbq (a);
+ return vmovlbq (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmovlb.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c
index 393fc5523a7..63d2ddb9015 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int16x8_t a, mve_pred16_t p)
{
return vmovlbq_x_s16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int16x8_t a, mve_pred16_t p)
{
return vmovlbq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c
index 3773be0b621..b573f572012 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int8x16_t a, mve_pred16_t p)
{
return vmovlbq_x_s8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int8x16_t a, mve_pred16_t p)
{
return vmovlbq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c
index b668eeb6fcf..f039019f5b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vmovlbq_x_u16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vmovlbq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c
index 6019e2d09d7..7fb32ece22d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint8x16_t a, mve_pred16_t p)
{
return vmovlbq_x_u8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovlbt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint8x16_t a, mve_pred16_t p)
{
return vmovlbq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c
index 47897a3913f..72ca8c8bb9b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
{
return vmovltq_m_s16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
{
return vmovltq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c
index c87b263db51..7e3b4f40bc5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
{
return vmovltq_m_s8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
{
return vmovltq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c
index cfe7cd7a5d3..4320df794ab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vmovltq_m_u16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vmovltq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c
index a9119fbb940..c9a75a590b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vmovltq_m_u8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vmovltq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c
index a7fd325e330..f431cda53ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovlt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int16x8_t a)
{
return vmovltq_s16 (a);
}
-/* { dg-final { scan-assembler "vmovlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmovlt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int16x8_t a)
{
return vmovltq (a);
}
-/* { dg-final { scan-assembler "vmovlt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c
index c392e56b60b..d65f8066454 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovlt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int8x16_t a)
{
return vmovltq_s8 (a);
}
-/* { dg-final { scan-assembler "vmovlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmovlt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int8x16_t a)
{
return vmovltq (a);
}
-/* { dg-final { scan-assembler "vmovlt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c
index 7634af6f45a..5469671041b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovlt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint16x8_t a)
{
- return vmovltq_u16 (a);
+ return vmovltq_u16 (a);
}
-/* { dg-final { scan-assembler "vmovlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmovlt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint16x8_t a)
{
- return vmovltq (a);
+ return vmovltq (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmovlt.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c
index 2c0d1a7c69d..a14c71cdfbc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovlt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint8x16_t a)
{
- return vmovltq_u8 (a);
+ return vmovltq_u8 (a);
}
-/* { dg-final { scan-assembler "vmovlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmovlt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint8x16_t a)
{
- return vmovltq (a);
+ return vmovltq (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmovlt.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c
index ae6c8999835..f8e24c4e0d3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int16x8_t a, mve_pred16_t p)
{
return vmovltq_x_s16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int16x8_t a, mve_pred16_t p)
{
return vmovltq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c
index 1172643218a..b97de081858 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int8x16_t a, mve_pred16_t p)
{
return vmovltq_x_s8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.s8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int8x16_t a, mve_pred16_t p)
{
return vmovltq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c
index 64442dcf935..851264e45ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vmovltq_x_u16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vmovltq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c
index 33e571890c0..82219b670db 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint8x16_t a, mve_pred16_t p)
{
return vmovltq_x_u8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovltt.u8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint8x16_t a, mve_pred16_t p)
{
return vmovltq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c
index fdb392cbf81..3bd9b82cbb3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovnbt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vmovnbq_m_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovnbt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovnbt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vmovnbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c
index 9f32f49d24e..bc2f95c7d8a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovnbt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vmovnbq_m_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovnbt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovnbt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vmovnbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c
index ebc1599af54..1624237c67a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovnbt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vmovnbq_m_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovnbt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovnbt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vmovnbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c
index 502068713e9..1a2f1e8441e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovnbt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vmovnbq_m_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovnbt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovnbt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vmovnbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c
index a49943fd25a..d5286f11259 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovnb.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vmovnbq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vmovnb.i16" } } */
+/*
+**foo1:
+** ...
+** vmovnb.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vmovnbq (a, b);
}
-/* { dg-final { scan-assembler "vmovnb.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c
index 6dbce232399..b6b44837b8c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovnb.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vmovnbq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vmovnb.i32" } } */
+/*
+**foo1:
+** ...
+** vmovnb.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vmovnbq (a, b);
}
-/* { dg-final { scan-assembler "vmovnb.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c
index f3df71a43eb..1203ac5c7f5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovnb.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vmovnbq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vmovnb.i16" } } */
+/*
+**foo1:
+** ...
+** vmovnb.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vmovnbq (a, b);
}
-/* { dg-final { scan-assembler "vmovnb.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c
index e0369ed5fa2..de5bb111783 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovnb.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vmovnbq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vmovnb.i32" } } */
+/*
+**foo1:
+** ...
+** vmovnb.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vmovnbq (a, b);
}
-/* { dg-final { scan-assembler "vmovnb.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c
index f305ab30dc8..594f72c08f5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovntt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vmovntq_m_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovntt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovntt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vmovntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c
index 59820c610e6..b3e3e0442c5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovntt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vmovntq_m_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovntt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovntt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vmovntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c
index 079b162148e..a3e33db311e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovntt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vmovntq_m_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovntt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovntt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vmovntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c
index 7c09b2e4f9f..b5629493c72 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovntt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vmovntq_m_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovntt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmovntt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vmovntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c
index 229cd5809d9..d7e369d266e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovnt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vmovntq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vmovnt.i16" } } */
+/*
+**foo1:
+** ...
+** vmovnt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vmovntq (a, b);
}
-/* { dg-final { scan-assembler "vmovnt.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c
index 01921cbd66e..6d87cc21aaa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovnt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vmovntq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vmovnt.i32" } } */
+/*
+**foo1:
+** ...
+** vmovnt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vmovntq (a, b);
}
-/* { dg-final { scan-assembler "vmovnt.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c
index 30e75b2169d..f85e45a666a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovnt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vmovntq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vmovnt.i16" } } */
+/*
+**foo1:
+** ...
+** vmovnt.i16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vmovntq (a, b);
}
-/* { dg-final { scan-assembler "vmovnt.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c
index 9ed963dda70..05c4af3d614 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmovnt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vmovntq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vmovnt.i32" } } */
+/*
+**foo1:
+** ...
+** vmovnt.i32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vmovntq (a, b);
}
-/* { dg-final { scan-assembler "vmovnt.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c
index 1b6e683700c..9d4804a0057 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, mve_pred16_t p)
{
- return vmvnq_m_n_s16 (inactive, 2, p);
+ return vmvnq_m_n_s16 (inactive, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, mve_pred16_t p)
{
- return vmvnq_m (inactive, 2, p);
+ return vmvnq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c
index dcfd69fb7f1..607cdfca33e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, mve_pred16_t p)
{
- return vmvnq_m_n_s32 (inactive, 2, p);
+ return vmvnq_m_n_s32 (inactive, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, mve_pred16_t p)
{
- return vmvnq_m (inactive, 2, p);
+ return vmvnq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c
index bd86fa806b8..7b0b5a9ef83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, mve_pred16_t p)
{
- return vmvnq_m_n_u16 (inactive, 4, p);
+ return vmvnq_m_n_u16 (inactive, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, mve_pred16_t p)
{
- return vmvnq_m (inactive, 4, p);
+ return vmvnq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c
index 2ac6ef192d7..2217420081e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, mve_pred16_t p)
{
- return vmvnq_m_n_u32 (inactive, 4, p);
+ return vmvnq_m_n_u32 (inactive, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, mve_pred16_t p)
{
- return vmvnq_m (inactive, 4, p);
+ return vmvnq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c
index 5284b8fe054..e27d8111b54 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vmvnq_m_s16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vmvnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c
index da16a5d45d6..8a264a1e76f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vmvnq_m_s32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vmvnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c
index 206759247c5..c4374d0ffd4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vmvnq_m_s8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vmvnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c
index 9940cec4bfe..3d5d56eadfe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vmvnq_m_u16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vmvnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c
index 25179f13f95..fd1961e0673 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vmvnq_m_u32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vmvnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c
index 7237db35b33..037d1f4ce39 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vmvnq_m_u8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vmvnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c
index 336c6aa63c4..975639334d5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo ()
{
return vmvnq_n_s16 (1);
}
-/* { dg-final { scan-assembler "vmvn.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c
index 354c39c8f7b..0e09343e6c3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo ()
{
- return vmvnq_n_s32 (2);
+ return vmvnq_n_s32 (1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmvn.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c
index 178b003091b..84e158ade93 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo ()
{
- return vmvnq_n_u16 (1);
+ return vmvnq_n_u16 (1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmvn.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c
index 4819066bdbd..168b77a400a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c
@@ -1,13 +1,28 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo ()
{
- return vmvnq_n_u32 (2);
+ return vmvnq_n_u32 (1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmvn.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c
index 840d834ea9e..30ddcd9118e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a)
{
return vmvnq_s16 (a);
}
-/* { dg-final { scan-assembler "vmvn" } } */
+/*
+**foo1:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a)
{
return vmvnq (a);
}
-/* { dg-final { scan-assembler "vmvn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c
index cf73bc088c7..48d66753c0f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a)
{
return vmvnq_s32 (a);
}
-/* { dg-final { scan-assembler "vmvn" } } */
+/*
+**foo1:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a)
{
return vmvnq (a);
}
-/* { dg-final { scan-assembler "vmvn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c
index 6d239391cbb..199bb0f81c3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a)
{
return vmvnq_s8 (a);
}
-/* { dg-final { scan-assembler "vmvn" } } */
+/*
+**foo1:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a)
{
return vmvnq (a);
}
-/* { dg-final { scan-assembler "vmvn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c
index db348328513..c2d724f5375 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a)
{
- return vmvnq_u16 (a);
+ return vmvnq_u16 (a);
}
-/* { dg-final { scan-assembler "vmvn" } } */
+/*
+**foo1:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a)
{
- return vmvnq (a);
+ return vmvnq (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmvn" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c
index c007a959078..8bafe68f21c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a)
{
- return vmvnq_u32 (a);
+ return vmvnq_u32 (a);
}
-/* { dg-final { scan-assembler "vmvn" } } */
+/*
+**foo1:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a)
{
- return vmvnq (a);
+ return vmvnq (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmvn" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c
index 2288a283d60..684e5bc94f1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a)
{
- return vmvnq_u8 (a);
+ return vmvnq_u8 (a);
}
-/* { dg-final { scan-assembler "vmvn" } } */
+/*
+**foo1:
+** ...
+** vmvn q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a)
{
- return vmvnq (a);
+ return vmvnq (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vmvn" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c
index b00ccc3e672..a4d575e4aba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (mve_pred16_t p)
{
- return vmvnq_x_n_s16 (2, p);
+ return vmvnq_x_n_s16 (1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c
index ea65104b4b3..9ca5c90d80e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (mve_pred16_t p)
{
- return vmvnq_x_n_s32 (2, p);
+ return vmvnq_x_n_s32 (1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c
index 2fa4e40ad5d..9fbf2b978ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (mve_pred16_t p)
{
- return vmvnq_x_n_u16 (4, p);
+ return vmvnq_x_n_u16 (1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c
index b39e681c116..883e9af1609 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c
@@ -1,14 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (mve_pred16_t p)
{
- return vmvnq_x_n_u32 (4, p);
+ return vmvnq_x_n_u32 (1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c
index d4b87a795fc..6bd04f7dd38 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
return vmvnq_x_s16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, mve_pred16_t p)
{
return vmvnq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c
index 0bcdba0c1d6..6af90408e9c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
return vmvnq_x_s32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, mve_pred16_t p)
{
return vmvnq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c
index ffa7306ace6..8c6f118c36f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, mve_pred16_t p)
{
return vmvnq_x_s8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, mve_pred16_t p)
{
return vmvnq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c
index 29b5ad950ea..2e9902f3858 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vmvnq_x_u16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vmvnq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c
index b3d5f73cd92..53b2ebdd457 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, mve_pred16_t p)
{
return vmvnq_x_u32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, mve_pred16_t p)
{
return vmvnq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c
index f085aa83662..ad7a5a9398c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, mve_pred16_t p)
{
return vmvnq_x_u8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vmvnt q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, mve_pred16_t p)
{
return vmvnq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c
index 7cf00d94084..36543ee6bff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vornq_f16 (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+/*
+**foo1:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vornq (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c
index d187bde1dc2..c3d73059c31 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vornq_f32 (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+/*
+**foo1:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vornq (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c
index 081872bada1..7a5cabf4396 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vornq_m_f16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vornq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c
index fe92dae6ec6..8fb90212c88 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vornq_m_f32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vornq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c
index 56a2b64bc29..31123f853f8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vornq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vornq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c
index c2e4b1267b8..e5d6d63955b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vornq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vornq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c
index 6607808e96e..73bde2bcfde 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vornq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vornq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c
index 1905ed193ac..2872c0a7045 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vornq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vornq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c
index 6d6620c3e07..90e8df24b99 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vornq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vornq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c
index 23e8d046c73..eedbf3a1ae1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vornq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vornq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c
index 0f73ea28e0d..ac92a93f19c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vornq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+/*
+**foo1:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vornq (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c
index 7d9835fc1b8..38be3483872 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vornq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+/*
+**foo1:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vornq (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c
index f2ba62292f5..3d5e47fa1e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vornq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+/*
+**foo1:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vornq (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c
index baa3fd80813..e69212d59b0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b)
{
return vornq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+/*
+**foo1:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b)
{
return vornq (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c
index 481db437b77..c89622c830f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b)
{
return vornq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+/*
+**foo1:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b)
{
return vornq (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c
index 575a7365487..61ce5ad294a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b)
{
return vornq_u8 (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+/*
+**foo1:
+** ...
+** vorn q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b)
{
return vornq (a, b);
}
-/* { dg-final { scan-assembler "vorn" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c
index d776bff2416..2bc10776f6d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vornq_x_f16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vornq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c
index 939e8fafb83..7b733cf6a6b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vornq_x_f32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vornq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c
index 77569b42cc8..beba497bbf9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vornq_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vornq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c
index 29cfd020c30..60e6125ed6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vornq_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vornq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c
index fd10ff8e719..f62c9b2a111 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vornq_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vornq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c
index 473f22abd52..2ac693ca30f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vornq_x_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vornq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c
index 010ac07454d..1981c8ca408 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vornq_x_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vornq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c
index 126a6d236b3..171dc0f58b6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vornq_x_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vornt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vornq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c
index 1481c43ae5f..3d222d5679b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b)
{
return vorrq_f16 (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+/*
+**foo1:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b)
{
return vorrq (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c
index 257edd99b7b..140817ee919 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b)
{
return vorrq_f32 (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+/*
+**foo1:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b)
{
return vorrq (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c
index 641c8f0f3bd..dbfac724131 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vorrq_m_f16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vorrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c
index b537a7c74c3..e13a1df44e2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vorrq_m_f32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vorrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c
index 757482a3a95..b591bd6fc11 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
- return vorrq_m_n_s16 (a, 253, p);
+ return vorrq_m_n_s16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, mve_pred16_t p)
{
- return vorrq_m_n (a, 253, p);
+ return vorrq_m_n (a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c
index 967e49e7a26..ce4dd3ee7bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
return vorrq_m_n_s32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, mve_pred16_t p)
{
return vorrq_m_n (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c
index 01022c32a88..9e7788484ad 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vorrq_m_n_u16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vorrq_m_n (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c
index 809237d1cf6..613c0e2f889 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, mve_pred16_t p)
{
return vorrq_m_n_u32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, mve_pred16_t p)
{
return vorrq_m_n (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c
index 2714810d591..d475f1e939f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vorrq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vorrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c
index c960b18631a..e171e93e4eb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vorrq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vorrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c
index d1d4bc721b0..17043b26c2e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vorrq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vorrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c
index 01190ea4812..19a752ec3b7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vorrq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vorrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c
index 502ceab2fe4..7f3985d1508 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vorrq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vorrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c
index 44cf1413ca6..5a04ebdf1de 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vorrq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vorrq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c
index 63a369f9996..b95418d9668 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a)
{
return vorrq_n_s16 (a, 1);
}
-/* { dg-final { scan-assembler "vorr.i16" } } */
+
+/*
+**foo1:
+** ...
+** vorr.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int16x8_t
+foo1 (int16x8_t a)
+{
+ return vorrq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c
index cf7bbc8c46d..30248216012 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a)
{
return vorrq_n_s32 (a, 1);
}
-/* { dg-final { scan-assembler "vorr.i32" } } */
+
+/*
+**foo1:
+** ...
+** vorr.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int32x4_t
+foo1 (int32x4_t a)
+{
+ return vorrq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c
index 2d599e52f8d..1f131501aec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a)
{
return vorrq_n_u16 (a, 1);
}
-/* { dg-final { scan-assembler "vorr.i16" } } */
+
+/*
+**foo1:
+** ...
+** vorr.i16 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo1 (uint16x8_t a)
+{
+ return vorrq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c
index 5a873d0d1a3..5bfdb0b2e14 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a)
{
- return vorrq_n_u32 (a, 44);
+ return vorrq_n_u32 (a, 1);
+}
+
+
+/*
+**foo1:
+** ...
+** vorr.i32 q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint32x4_t
+foo1 (uint32x4_t a)
+{
+ return vorrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vorr.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c
index 2a56912ab31..658df6f422f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vorrq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+/*
+**foo1:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vorrq (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c
index e80b991c95a..a0a24b7fd45 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vorrq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+/*
+**foo1:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vorrq (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c
index 3456477c07c..645c6144f46 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vorrq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+/*
+**foo1:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vorrq (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c
index bb7699c1e3b..cb618a1f793 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b)
{
return vorrq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+/*
+**foo1:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b)
{
return vorrq (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c
index e01f5413dc3..937102ff962 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b)
{
return vorrq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+/*
+**foo1:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b)
{
return vorrq (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c
index c7ad98805c4..07121b5b1c9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b)
{
return vorrq_u8 (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+/*
+**foo1:
+** ...
+** vorr q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b)
{
return vorrq (a, b);
}
-/* { dg-final { scan-assembler "vorr" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c
index 2e678febb78..b34d102f470 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vorrq_x_f16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vorrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c
index 12acfb49773..d41a94e7a02 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vorrq_x_f32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vorrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c
index 75fe4541845..3e1d3e97d26 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vorrq_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vorrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c
index 37d17f046af..0982b3d2081 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vorrq_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vorrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c
index 3558db3b7b0..0a46246e124 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vorrq_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vorrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c
index 7c9a2559c87..ef83d9de2ee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vorrq_x_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vorrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c
index 13ff34d582a..b6abfd5b314 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vorrq_x_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vorrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c
index 781b2b59699..b724ed0562b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vorrq_x_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vorrt q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vorrq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
index a84f84446c0..2b894d1d938 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
@@ -1,21 +1,32 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpnot(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|)
+** ...
+*/
mve_pred16_t
foo (mve_pred16_t a)
{
return vpnot (a);
}
-/* { dg-final { scan-assembler "vpnot" } } */
-
-mve_pred16_t
-foo1 (mve_pred16_t a)
-{
- return vpnot (a);
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpnot" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c
index ff121b585ed..50127b4537d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vpselq_f16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c
index 35c84761f08..0733413f1ca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vpselq_f32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c
index 0e0c14ed49d..06ef70c4073 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vpselq_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c
index 0e746de6e07..87b4b2242eb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vpselq_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c
index f4bbb77e268..dedb812c11b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64x2_t
foo (int64x2_t a, int64x2_t b, mve_pred16_t p)
{
return vpselq_s64 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64x2_t
foo1 (int64x2_t a, int64x2_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c
index 65cd415c789..5050fc03556 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vpselq_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c
index 742ca17ac8e..055f3c00381 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vpselq_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c
index 9d2e01c31d4..11333822b19 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vpselq_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c
index 58c4169bc0a..c08e6c54d95 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64x2_t
foo (uint64x2_t a, uint64x2_t b, mve_pred16_t p)
{
return vpselq_u64 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64x2_t
foo1 (uint64x2_t a, uint64x2_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c
index 5f73ba44ea8..804aed384c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c
@@ -1,21 +1,45 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vpselq_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpsel q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vpselq (a, b, p);
}
-/* { dg-final { scan-assembler "vpsel" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c
index bf5520ed1ff..dd6c0300c32 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovnbt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqmovnbq_m_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovnbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovnbt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqmovnbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c
index f07612a47d5..eb340ebe520 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovnbt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqmovnbq_m_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovnbt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovnbt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqmovnbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c
index 79f082fefab..673f453e7af 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovnbt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqmovnbq_m_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovnbt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovnbt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqmovnbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c
index 5d242dc497f..84f7f9bf897 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovnbt.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqmovnbq_m_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovnbt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovnbt.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqmovnbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c
index 18df48f5084..ed17eb81884 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovnb.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vqmovnbq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vqmovnb.s16" } } */
+/*
+**foo1:
+** ...
+** vqmovnb.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vqmovnbq (a, b);
}
-/* { dg-final { scan-assembler "vqmovnb.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c
index 37f9e817805..065ce9b246c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovnb.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vqmovnbq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vqmovnb.s32" } } */
+/*
+**foo1:
+** ...
+** vqmovnb.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vqmovnbq (a, b);
}
-/* { dg-final { scan-assembler "vqmovnb.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c
index 130dcb06944..29df4636e3d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovnb.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vqmovnbq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vqmovnb.u16" } } */
+/*
+**foo1:
+** ...
+** vqmovnb.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vqmovnbq (a, b);
}
-/* { dg-final { scan-assembler "vqmovnb.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c
index 8bf735294e5..422c33560d3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovnb.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vqmovnbq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vqmovnb.u32" } } */
+/*
+**foo1:
+** ...
+** vqmovnb.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vqmovnbq (a, b);
}
-/* { dg-final { scan-assembler "vqmovnb.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c
index bc624bcd877..b50964bd4f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovntt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqmovntq_m_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovntt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovntt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqmovntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c
index 429f25cdb0f..5d4947abb9f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovntt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqmovntq_m_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovntt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovntt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqmovntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c
index a453a9fc36a..8cfd62831eb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovntt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqmovntq_m_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovntt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovntt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqmovntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c
index 3f9ae8a5ee4..b9d3b7e75ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovntt.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqmovntq_m_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovntt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovntt.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqmovntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c
index 5de956cbac4..8838a242fd9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovnt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vqmovntq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vqmovnt.s16" } } */
+/*
+**foo1:
+** ...
+** vqmovnt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vqmovntq (a, b);
}
-/* { dg-final { scan-assembler "vqmovnt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c
index 30db31c47ee..1d8b0dc17ef 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovnt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vqmovntq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vqmovnt.s32" } } */
+/*
+**foo1:
+** ...
+** vqmovnt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vqmovntq (a, b);
}
-/* { dg-final { scan-assembler "vqmovnt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c
index 312ce4f865f..10badd5feb4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovnt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vqmovntq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vqmovnt.u16" } } */
+/*
+**foo1:
+** ...
+** vqmovnt.u16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vqmovntq (a, b);
}
-/* { dg-final { scan-assembler "vqmovnt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c
index 20623384858..80460393001 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovnt.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vqmovntq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vqmovnt.u32" } } */
+/*
+**foo1:
+** ...
+** vqmovnt.u32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vqmovntq (a, b);
}
-/* { dg-final { scan-assembler "vqmovnt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c
index 8e46de63b84..d295b3f9155 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovunbt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqmovunbq_m_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovunbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovunbt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqmovunbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c
index d0ec95192f9..84b94db682f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovunbt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqmovunbq_m_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovunbt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovunbt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqmovunbq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c
index 9b3b80d024f..070bb90bf12 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovunb.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b)
{
return vqmovunbq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vqmovunb.s16" } } */
+/*
+**foo1:
+** ...
+** vqmovunb.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b)
{
return vqmovunbq (a, b);
}
-/* { dg-final { scan-assembler "vqmovunb.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c
index 9cc43d987de..659e703a558 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovunb.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b)
{
return vqmovunbq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vqmovunb.s32" } } */
+/*
+**foo1:
+** ...
+** vqmovunb.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b)
{
return vqmovunbq (a, b);
}
-/* { dg-final { scan-assembler "vqmovunb.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c
index a81fb8863af..fb3b36c451e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovuntt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqmovuntq_m_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovuntt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovuntt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqmovuntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c
index e76ca2b5f48..f6fce6d4473 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovuntt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqmovuntq_m_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovuntt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqmovuntt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqmovuntq_m (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c
index 324d2e56f3c..3230f25998b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovunt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b)
{
return vqmovuntq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vqmovunt.s16" } } */
+/*
+**foo1:
+** ...
+** vqmovunt.s16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b)
{
return vqmovuntq (a, b);
}
-/* { dg-final { scan-assembler "vqmovunt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c
index 80fee05b642..5333897a34a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqmovunt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b)
{
return vqmovuntq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vqmovunt.s32" } } */
+/*
+**foo1:
+** ...
+** vqmovunt.s32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b)
{
return vqmovuntq (a, b);
}
-/* { dg-final { scan-assembler "vqmovunt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c
index 5b0e134a0ff..1140c25c4a2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c
index 6fdf3879cc2..b3e6dac19a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c
index ef75f737161..5ae74e1dd2d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c
index cf7cdb202ce..f515c3926da 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c
index 5a022fe3009..4693d01eeb4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c
index 2cb27df16f6..cea58e4f80a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c
index 1f68671b3f9..3b8ea613f1d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c
index eaea6e1f482..6ef932672bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c
index 0f582a91f3a..5b9dc5cadac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c
index a26898ebdab..745c70b84f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c
index 572486ecf82..94e976f724c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c
index 00e478b9d3e..f8c9f487068 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
index 304f86c6e51..f8400ac63d7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
index 265fecaf806..fa1131de6b5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
index d1687f79311..a7ce97cc2f6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c
index 4595d55711e..175a2f74416 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t add, int16x8_t m1, int16_t m2)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c
index 22d9ce56a35..56d5423bd3f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t add, int32x4_t m1, int32_t m2)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c
index 36a23ad2078..992be758837 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t add, int8x16_t m1, int8_t m2)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
index 2995682f252..d713c224b30 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
index 7e637e6900f..8af4928f833 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
index d81472d933a..9f30b7d0e13 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c
index 2710f2f0442..83caaab8926 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t m1, int16x8_t m2, int16_t add)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c
index 5fefc3938c5..337f33c51c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t m1, int32x4_t m2, int32_t add)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c
index df96fe85213..df005ee9b03 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t m1, int8x16_t m2, int8_t add)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c
index 6a5776215ca..52c7f16df12 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c
index 9539e249d6a..574809dde9b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c
index 69e54f53a76..9b509687ed9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c
index 3eb957d6029..19fdc151550 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c
index 3a3fb506c01..d50bd8500bd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c
index 65ac15da9c7..c3f6b3e462b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c
index 3598f50ccba..35fc3bde975 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c
index 1ab22edf9ca..7b5ee71194c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c
index 01103e99b61..0ceb9c55aa3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c
index 522d0ba4a3a..b94e4cca8b2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c
index 5198dfa754e..0f508d9bca1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c
index b5baa3dea79..92607fe0265 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c
index fc3a33073aa..ae38058cc62 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c
index 897ad5bd28c..e923495f4b5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c
index 05ab0609af4..a6ce3b2ca01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c
index 1d9dc07787c..a8a749d07cb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c
index 76d7507e35a..ad6130dfbdc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c
index 7fd2119ea63..da29228e5f3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c
index 8a90a399858..342ef427bc9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t a, int16_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c
index 973464b3297..7ae72b75689 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t a, int32_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c
index 65aab964f4e..8acb72a2245 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t a, int8_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c
index f3153c86b4c..5e93d7758c0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t a, int16x8_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c
index 48b10dbd025..d2812c0aa05 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t a, int32x4_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c
index 9f0346fc841..5c188a6d91f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t a, int8x16_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c
index 8d5abfd7588..d9baa378fac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c
index 734f67ae251..ce4140a6fb8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c
index 3c6724f285b..ce576b01d65 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c
index 3e39599df8a..e861a7b1f6a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c
index 41f5945daf9..d4cb581c623 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c
index 9aad2599476..f170f225d95 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vqrshlq_m_n (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c
index 80045c5b583..7c5449fb168 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshlq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c
index 9b4cf1663cd..53a421cf830 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshlq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c
index 55e0dd57023..52ad4372916 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vqrshlq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vqrshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c
index cd5605444a1..e7ca4786363 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshlq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c
index 02c94d0a51f..3785bbea0dc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshlq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c
index e6058dfc4c5..c736abeceab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vqrshlq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vqrshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c
index 46fd917d2d9..231ce85f1a3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32_t b)
{
return vqrshlq_n_s16 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s16" } } */
+/*
+**foo1:
+** ...
+** vqrshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c
index 373de10b89c..05589eb86cc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32_t b)
{
return vqrshlq_n_s32 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s32" } } */
+/*
+**foo1:
+** ...
+** vqrshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c
index d05d2fc722f..182e7cf260a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int32_t b)
{
return vqrshlq_n_s8 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s8" } } */
+/*
+**foo1:
+** ...
+** vqrshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int32_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c
index 8a74d61e75d..1b5214623c6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32_t b)
{
return vqrshlq_n_u16 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u16" } } */
+/*
+**foo1:
+** ...
+** vqrshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c
index ccb0db7bb32..50d09bac3a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32_t b)
{
return vqrshlq_n_u32 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u32" } } */
+/*
+**foo1:
+** ...
+** vqrshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c
index c3319ea29d2..846d90a2470 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int32_t b)
{
return vqrshlq_n_u8 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u8" } } */
+/*
+**foo1:
+** ...
+** vqrshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int32_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c
index c5645cee518..2a4a0feb5e6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vqrshlq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s16" } } */
+/*
+**foo1:
+** ...
+** vqrshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c
index b773ccf9245..94665928299 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vqrshlq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s32" } } */
+/*
+**foo1:
+** ...
+** vqrshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c
index 1a61cb6de10..2836a6e4dc8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vqrshlq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s8" } } */
+/*
+**foo1:
+** ...
+** vqrshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c
index 8de05a290b7..2ea554253c1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int16x8_t b)
{
return vqrshlq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u16" } } */
+/*
+**foo1:
+** ...
+** vqrshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int16x8_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c
index 0ceee291bab..fef01d926b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32x4_t b)
{
return vqrshlq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u32" } } */
+/*
+**foo1:
+** ...
+** vqrshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32x4_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c
index 7779871c097..6ceafa0f473 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int8x16_t b)
{
return vqrshlq_u8 (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u8" } } */
+/*
+**foo1:
+** ...
+** vqrshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int8x16_t b)
{
return vqrshlq (a, b);
}
-/* { dg-final { scan-assembler "vqrshl.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c
index 16a4827e50d..76c38e07faa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrnbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshrnbq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrnbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c
index bb054bcf5a1..3af0ad96493 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrnbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshrnbq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrnbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c
index 45119720ed5..f81dd96efde 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrnbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqrshrnbq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrnbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqrshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c
index a3a7a7eac3e..ad52c378a07 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrnbt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqrshrnbq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrnbt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqrshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c
index d1b2ea58dd5..3f82f86029e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrnb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vqrshrnbq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnb.s16" } } */
+/*
+**foo1:
+** ...
+** vqrshrnb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vqrshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnb.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c
index da5db1b8951..02f303052a3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrnb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vqrshrnbq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnb.s32" } } */
+/*
+**foo1:
+** ...
+** vqrshrnb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vqrshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnb.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c
index 360999e3785..cda56ce3c48 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrnb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vqrshrnbq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnb.u16" } } */
+/*
+**foo1:
+** ...
+** vqrshrnb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vqrshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnb.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c
index f276f24a1dd..5202e6249a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrnb.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vqrshrnbq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnb.u32" } } */
+/*
+**foo1:
+** ...
+** vqrshrnb.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vqrshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnb.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c
index fb21072bfa0..39c0eff56f6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshrntq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c
index 77c4cb7e0b0..5fb6983237c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshrntq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c
index 1749f4866a4..91ec5795566 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrntt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqrshrntq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrntt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqrshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c
index e243319e256..986437e49ca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrntt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqrshrntq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrntt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqrshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c
index c7cdc394c35..5dfed5dcbaa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrnt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vqrshrntq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnt.s16" } } */
+/*
+**foo1:
+** ...
+** vqrshrnt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vqrshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c
index 68dfccccc66..7df82962342 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrnt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vqrshrntq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnt.s32" } } */
+/*
+**foo1:
+** ...
+** vqrshrnt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vqrshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c
index bc0572a454b..e76d98ee3f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrnt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vqrshrntq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnt.u16" } } */
+/*
+**foo1:
+** ...
+** vqrshrnt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vqrshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c
index 20bfdbf515a..bc0e39baeae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrnt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vqrshrntq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnt.u32" } } */
+/*
+**foo1:
+** ...
+** vqrshrnt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vqrshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrnt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c
index ea12f346b0e..299dd80a887 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrunbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshrunbq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrunbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrunbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshrunbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrunbt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c
index d127e5381bf..5c87efe4be9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrunbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshrunbq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrunbt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshrunbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshrunbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrunbt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c
index 88cb39970d4..3bbf72d4def 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrunb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b)
{
return vqrshrunbq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrunb.s16" } } */
+/*
+**foo1:
+** ...
+** vqrshrunb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b)
{
return vqrshrunbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrunb.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c
index 46f96127b1b..4dfd8f60e72 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrunb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b)
{
return vqrshrunbq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrunb.s32" } } */
+/*
+**foo1:
+** ...
+** vqrshrunb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b)
{
return vqrshrunbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrunb.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c
index 5ff25eb2d32..48c17e5e5b6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshruntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshruntq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshruntt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshruntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqrshruntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshruntt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c
index 4876414e308..46912882ff1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshruntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshruntq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshruntt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqrshruntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqrshruntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshruntt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c
index 0f6258b3524..9dc8d3b8f5a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrunt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b)
{
return vqrshruntq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrunt.s16" } } */
+/*
+**foo1:
+** ...
+** vqrshrunt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b)
{
return vqrshruntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrunt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c
index d307f38ec6c..8071367fa2f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqrshrunt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b)
{
return vqrshruntq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrunt.s32" } } */
+/*
+**foo1:
+** ...
+** vqrshrunt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b)
{
return vqrshruntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqrshrunt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c
index a33856f17a5..6eb7443d45e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vqshlq_m_n_s16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vqshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c
index bcfe4fc2874..d10829c90c8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vqshlq_m_n_s32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vqshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c
index fba2f0fe859..49886009d74 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vqshlq_m_n_s8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vqshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c
index 1383f6a9ab4..7eb330e6c18 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vqshlq_m_n_u16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vqshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c
index 7cff29f5a28..86ecdc6d563 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vqshlq_m_n_u32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vqshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c
index cbadcbeb77e..f3886e7bae6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vqshlq_m_n_u8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vqshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c
index a3057fec343..e89298c570b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c
index 6973b49a476..35e2552728a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c
index 282d4b45c59..366b45699a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c
index 111d7fa23d9..86774962f0f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c
index 96de168dd23..92a61fe4a2e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c
index 24e388824cc..bace3656143 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vqshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c
index ebae8beecb4..2df2ee5c836 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vqshlq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vqshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c
index 80e4d860fb9..e0b2de339f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vqshlq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vqshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c
index e8f88113003..b65df1998fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vqshlq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vqshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c
index 692ff54981d..bced90d13b9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vqshlq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vqshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c
index 1ece80681a7..409ef8524cb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vqshlq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vqshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c
index 7302669fe26..ce9a426ccc9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vqshlq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vqshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c
index b827993198d..859da655409 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a)
{
return vqshlq_n_s16 (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.s16" } } */
+/*
+**foo1:
+** ...
+** vqshl.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a)
{
return vqshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c
index dbc22df551e..1d61e880890 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a)
{
return vqshlq_n_s32 (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.s32" } } */
+/*
+**foo1:
+** ...
+** vqshl.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a)
{
return vqshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c
index e4e1d193c55..737c1bd3764 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a)
{
return vqshlq_n_s8 (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.s8" } } */
+/*
+**foo1:
+** ...
+** vqshl.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a)
{
return vqshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c
index 8227890fc4b..9ddb83e4287 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a)
{
return vqshlq_n_u16 (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.u16" } } */
+/*
+**foo1:
+** ...
+** vqshl.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a)
{
return vqshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c
index b91dc3b91d3..642060f2225 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a)
{
return vqshlq_n_u32 (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.u32" } } */
+/*
+**foo1:
+** ...
+** vqshl.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a)
{
return vqshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c
index ab4903ae407..bd8b9341007 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a)
{
return vqshlq_n_u8 (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.u8" } } */
+/*
+**foo1:
+** ...
+** vqshl.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a)
{
return vqshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vqshl.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c
index 4413d447b71..285f398b35a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32_t b)
{
return vqshlq_r_s16 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s16" } } */
+/*
+**foo1:
+** ...
+** vqshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32_t b)
{
return vqshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c
index 6df14afb48d..af594003c06 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32_t b)
{
return vqshlq_r_s32 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s32" } } */
+/*
+**foo1:
+** ...
+** vqshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32_t b)
{
return vqshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c
index c1b93793c8f..ef39f0c3924 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int32_t b)
{
return vqshlq_r_s8 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s8" } } */
+/*
+**foo1:
+** ...
+** vqshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int32_t b)
{
return vqshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c
index 20fa0263de4..e6cc0007a2b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32_t b)
{
return vqshlq_r_u16 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u16" } } */
+/*
+**foo1:
+** ...
+** vqshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32_t b)
{
return vqshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c
index 7d56784b3d5..b30ecdf4052 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32_t b)
{
return vqshlq_r_u32 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u32" } } */
+/*
+**foo1:
+** ...
+** vqshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32_t b)
{
return vqshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c
index 199249bf604..69b0a8d0b90 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int32_t b)
{
return vqshlq_r_u8 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u8" } } */
+/*
+**foo1:
+** ...
+** vqshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int32_t b)
{
return vqshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c
index 2b01d3e3d31..e7877019200 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vqshlq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s16" } } */
+/*
+**foo1:
+** ...
+** vqshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vqshlq (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c
index b9b66223ae9..a7787cabb62 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vqshlq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s32" } } */
+/*
+**foo1:
+** ...
+** vqshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vqshlq (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c
index 8096205cf28..73af1790b47 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vqshlq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s8" } } */
+/*
+**foo1:
+** ...
+** vqshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vqshlq (a, b);
}
-/* { dg-final { scan-assembler "vqshl.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c
index 61b6c18bd8a..26119eff397 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int16x8_t b)
{
return vqshlq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u16" } } */
+/*
+**foo1:
+** ...
+** vqshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int16x8_t b)
{
return vqshlq (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c
index 06b50442d30..01b66d5dfbc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32x4_t b)
{
return vqshlq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u32" } } */
+/*
+**foo1:
+** ...
+** vqshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32x4_t b)
{
return vqshlq (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c
index 0cc6a1dac4b..d4727de5de9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int8x16_t b)
{
return vqshlq_u8 (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u8" } } */
+/*
+**foo1:
+** ...
+** vqshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int8x16_t b)
{
return vqshlq (a, b);
}
-/* { dg-final { scan-assembler "vqshl.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c
index 885874d13fb..ada03b165c5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlut.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
- return vqshluq_m_n_s16 (inactive, a, 7, p);
+ return vqshluq_m_n_s16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlut.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlut.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
- return vqshluq_m (inactive, a, 7, p);
+ return vqshluq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c
index bb2a3294727..6ae38f1ca84 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlut.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
- return vqshluq_m_n_s32 (inactive, a, 7, p);
+ return vqshluq_m_n_s32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlut.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlut.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
- return vqshluq_m (inactive, a, 7, p);
+ return vqshluq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c
index 7f9a42f8027..8d536a7b0f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlut.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
- return vqshluq_m_n_s8 (inactive, a, 7, p);
+ return vqshluq_m_n_s8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlut.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshlut.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
- return vqshluq_m (inactive, a, 7, p);
+ return vqshluq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c
index 481a4465834..33ba80cbf97 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshlu.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (int16x8_t a)
{
- return vqshluq_n_s16 (a, 7);
+ return vqshluq_n_s16 (a, 1);
}
-/* { dg-final { scan-assembler "vqshlu.s16" } } */
+/*
+**foo1:
+** ...
+** vqshlu.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (int16x8_t a)
{
- return vqshluq (a, 7);
+ return vqshluq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vqshlu.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c
index 68298963824..0d5a35f1ed3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshlu.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (int32x4_t a)
{
- return vqshluq_n_s32 (a, 7);
+ return vqshluq_n_s32 (a, 1);
}
-/* { dg-final { scan-assembler "vqshlu.s32" } } */
+/*
+**foo1:
+** ...
+** vqshlu.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (int32x4_t a)
{
- return vqshluq (a, 7);
+ return vqshluq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vqshlu.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c
index 5d52c340667..1e2d9e044b9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshlu.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (int8x16_t a)
{
- return vqshluq_n_s8 (a, 7);
+ return vqshluq_n_s8 (a, 1);
}
-/* { dg-final { scan-assembler "vqshlu.s8" } } */
+/*
+**foo1:
+** ...
+** vqshlu.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (int8x16_t a)
{
- return vqshluq (a, 7);
+ return vqshluq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vqshlu.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c
index 9ea58e95d37..0266640a3ff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrnbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
- return vqshrnbq_m_n_s16 (a, b, 7, p);
+ return vqshrnbq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrnbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
- return vqshrnbq_m (a, b, 7, p);
+ return vqshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c
index b44f41b3699..59be6de392b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrnbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
- return vqshrnbq_m_n_s32 (a, b, 11, p);
+ return vqshrnbq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrnbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
- return vqshrnbq_m (a, b, 11, p);
+ return vqshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c
index f761d14ecec..f227a285ea9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrnbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqshrnbq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrnbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c
index 3073a5b223c..9711c2f9019 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrnbt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqshrnbq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrnbt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c
index 24133b57660..e7e9f974bd4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrnb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vqshrnbq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnb.s16" } } */
+/*
+**foo1:
+** ...
+** vqshrnb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vqshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnb.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c
index 34c11e156c3..b5e2b8af577 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrnb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
- return vqshrnbq_n_s32 (a, b, 2);
+ return vqshrnbq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnb.s32" } } */
+/*
+**foo1:
+** ...
+** vqshrnb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
- return vqshrnbq (a, b, 2);
+ return vqshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vqshrnb.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c
index 23a7596e0ab..708cf3e8d74 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrnb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vqshrnbq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnb.u16" } } */
+/*
+**foo1:
+** ...
+** vqshrnb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vqshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnb.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c
index 4cb7ceaf66b..07fbbaada67 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrnb.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
- return vqshrnbq_n_u32 (a, b, 15);
+ return vqshrnbq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnb.u32" } } */
+/*
+**foo1:
+** ...
+** vqshrnb.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
- return vqshrnbq (a, b, 15);
+ return vqshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vqshrnb.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c
index d2ff2d359e0..c25619df048 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqshrntq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c
index 50dde4047d4..1b1d435e282 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqshrntq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c
index 07949569581..f151a277cd1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrntt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqshrntq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrntt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vqshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c
index 17f0205c880..c336001c945 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrntt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqshrntq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrntt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vqshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c
index 9e8d5e88619..15b010d2c84 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrnt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vqshrntq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnt.s16" } } */
+/*
+**foo1:
+** ...
+** vqshrnt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vqshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c
index 0661cefa783..974e4a060ce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrnt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vqshrntq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnt.s32" } } */
+/*
+**foo1:
+** ...
+** vqshrnt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vqshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c
index cda26142559..3172a330f6b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrnt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vqshrntq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnt.u16" } } */
+/*
+**foo1:
+** ...
+** vqshrnt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vqshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c
index f242353f6b4..e9e31d63e98 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrnt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vqshrntq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnt.u32" } } */
+/*
+**foo1:
+** ...
+** vqshrnt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vqshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrnt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c
index 73c480646e7..b7fe0e51e82 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrunbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqshrunbq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrunbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrunbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqshrunbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrunbt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c
index f8887b1cecb..fb78dd44c5d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrunbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqshrunbq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrunbt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshrunbt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqshrunbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrunbt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c
index 2c64d7d0873..3c286e77a40 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrunb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b)
{
return vqshrunbq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrunb.s16" } } */
+/*
+**foo1:
+** ...
+** vqshrunb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b)
{
return vqshrunbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrunb.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c
index 17cb0aa5da1..e22fb2b2b36 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrunb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b)
{
return vqshrunbq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrunb.s32" } } */
+/*
+**foo1:
+** ...
+** vqshrunb.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b)
{
return vqshrunbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrunb.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c
index 4b9758df7ec..22ca346d98b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshruntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqshruntq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshruntt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshruntt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vqshruntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshruntt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c
index 18b9f117fb2..2f6adf26e5e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshruntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqshruntq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshruntt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vqshruntt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vqshruntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshruntt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c
index f6247751c44..96a377e13b9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrunt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int16x8_t b)
{
return vqshruntq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrunt.s16" } } */
+/*
+**foo1:
+** ...
+** vqshrunt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b)
{
return vqshruntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrunt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c
index 076fd29c69f..2e2eb93a0d6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vqshrunt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32x4_t b)
{
return vqshruntq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrunt.s32" } } */
+/*
+**foo1:
+** ...
+** vqshrunt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b)
{
return vqshruntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vqshrunt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c
index a64b6649938..f69649b58af 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c
index 350629cf234..a7843d07933 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c
index e5fa4c486bb..f1fb5ad2a05 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c
index 734ac2da8f7..7e7d2c07267 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c
@@ -62,4 +62,4 @@ foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c
index f54aec8dd00..13e54be06c1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c
@@ -62,4 +62,4 @@ foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c
index c96a8398bad..ae6baaba661 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c
@@ -62,4 +62,4 @@ foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c
index bd6a05e858d..fd52022fc26 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c
@@ -46,4 +46,4 @@ foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c
index baa9e9f192c..4225ec29c06 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c
@@ -46,4 +46,4 @@ foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c
index 746001d0efa..27496305ee8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c
@@ -46,4 +46,4 @@ foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c
index ed504fe3817..d840e51d350 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c
@@ -46,4 +46,4 @@ foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c
index 508b54ff41f..242903f9dc8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c
@@ -46,4 +46,4 @@ foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c
index 5cfb2c58940..e5a6b7aa0e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c
@@ -46,4 +46,4 @@ foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c
index a4407cc802f..7a286add743 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t a, int16_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c
index 80634f0a797..2532b216a34 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t a, int32_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c
index 172609a94e7..9e0a233baa0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t a, int8_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c
index 0a95d0ab3ce..20d3267e583 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c
@@ -50,4 +50,4 @@ foo2 (uint16x8_t a)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c
index 9964ea66ee8..4805e4cd969 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c
@@ -50,4 +50,4 @@ foo2 (uint32x4_t a)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c
index b28a93ffd00..db475615bbc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c
@@ -50,4 +50,4 @@ foo2 (uint8x16_t a)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c
index 1c5edd730ad..76def1b340d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c
@@ -38,4 +38,4 @@ foo1 (int16x8_t a, int16x8_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c
index a7b6c07fb4b..989ad501659 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c
@@ -38,4 +38,4 @@ foo1 (int32x4_t a, int32x4_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c
index 92676fdca4f..4cf804b4c99 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c
@@ -38,4 +38,4 @@ foo1 (int8x16_t a, int8x16_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c
index 0b816c6b765..4d937a35269 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c
@@ -38,4 +38,4 @@ foo1 (uint16x8_t a, uint16x8_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c
index 565508db865..5ee2c2d9cc2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c
@@ -38,4 +38,4 @@ foo1 (uint32x4_t a, uint32x4_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c
index cca60ff7247..14cfb55644c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c
@@ -38,4 +38,4 @@ foo1 (uint8x16_t a, uint8x16_t b)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c
index 7b06f0b3644..b366057dfde 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vrev16q_m_s8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev16t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vrev16q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c
index 8cf374d97c1..7baad3ba72f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vrev16q_m_u8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev16t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vrev16q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c
index 52688402437..23fcd61a464 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev16.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a)
{
return vrev16q_s8 (a);
}
-/* { dg-final { scan-assembler "vrev16.8" } } */
+/*
+**foo1:
+** ...
+** vrev16.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a)
{
return vrev16q (a);
}
-/* { dg-final { scan-assembler "vrev16.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c
index 56c05c523f3..e08b4b6cda2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev16.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a)
{
- return vrev16q_u8 (a);
+ return vrev16q_u8 (a);
}
-/* { dg-final { scan-assembler "vrev16.8" } } */
+/*
+**foo1:
+** ...
+** vrev16.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a)
{
- return vrev16q (a);
+ return vrev16q (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrev16.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c
index 700a6774e2e..6496bf89931 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, mve_pred16_t p)
{
return vrev16q_x_s8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev16t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, mve_pred16_t p)
{
return vrev16q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c
index 3b424061f0e..e03f6f177ff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, mve_pred16_t p)
{
return vrev16q_x_u8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev16t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev16t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, mve_pred16_t p)
{
return vrev16q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c
index 946fd8ddf5b..6e4c5691760 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a)
{
return vrev32q_f16 (a);
}
-/* { dg-final { scan-assembler "vrev32.16" } } */
+
+/*
+**foo1:
+** ...
+** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+ return vrev32q (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c
index 623b48a92c4..3b25f0314c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrev32q_m_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrev32q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c
index 4040707d02c..36f671924b3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vrev32q_m_s16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vrev32q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c
index ad15e9d2bca..13960569138 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vrev32q_m_s8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vrev32q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c
index 8cd61e6bb1f..7683397030b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vrev32q_m_u16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vrev32q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c
index 44600e2d1e7..72fc03bff2d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vrev32q_m_u8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vrev32q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c
index 503616e2a29..cd02518fd9d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a)
{
return vrev32q_s16 (a);
}
-/* { dg-final { scan-assembler "vrev32.16" } } */
+/*
+**foo1:
+** ...
+** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a)
{
return vrev32q (a);
}
-/* { dg-final { scan-assembler "vrev32.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c
index aa98f965713..3a156b7014f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev32.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a)
{
return vrev32q_s8 (a);
}
-/* { dg-final { scan-assembler "vrev32.8" } } */
+/*
+**foo1:
+** ...
+** vrev32.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a)
{
return vrev32q (a);
}
-/* { dg-final { scan-assembler "vrev32.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c
index 6a441ed0edb..299f015bb04 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a)
{
- return vrev32q_u16 (a);
+ return vrev32q_u16 (a);
}
-/* { dg-final { scan-assembler "vrev32.16" } } */
+/*
+**foo1:
+** ...
+** vrev32.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a)
{
- return vrev32q (a);
+ return vrev32q (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrev32.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c
index 787f236411d..fb65d0a3821 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev32.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a)
{
- return vrev32q_u8 (a);
+ return vrev32q_u8 (a);
}
-/* { dg-final { scan-assembler "vrev32.8" } } */
+/*
+**foo1:
+** ...
+** vrev32.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a)
{
- return vrev32q (a);
+ return vrev32q (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrev32.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c
index f7dc8fb14ec..d1c22aa72f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vrev32q_x_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, mve_pred16_t p)
{
return vrev32q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c
index 81ec83dec4b..0f0c19b1483 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
return vrev32q_x_s16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, mve_pred16_t p)
{
return vrev32q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c
index 8d3bac1e82c..2457dde2a58 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, mve_pred16_t p)
{
return vrev32q_x_s8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, mve_pred16_t p)
{
return vrev32q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c
index 36ba71752a8..b1b1237344e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vrev32q_x_u16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vrev32q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c
index 9d15c9df43c..21d39274577 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, mve_pred16_t p)
{
return vrev32q_x_u8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev32t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, mve_pred16_t p)
{
return vrev32q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c
index 7ec0962a95e..a2dc8957467 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a)
{
return vrev64q_f16 (a);
}
-/* { dg-final { scan-assembler "vrev64.16" } } */
+
+/*
+**foo1:
+** ...
+** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+ return vrev64q (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c
index 01c342496da..78add56a4da 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a)
{
return vrev64q_f32 (a);
}
-/* { dg-final { scan-assembler "vrev64.32" } } */
+
+/*
+**foo1:
+** ...
+** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+ return vrev64q (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c
index ef47bab0314..0fb44077ec4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrev64q_m_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrev64q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c
index 6df0ba62eff..ff62ea7d021 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrev64q_m_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrev64q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c
index 9f9bbe0e666..b30ce76c68f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vrev64q_m_s16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vrev64q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c
index 132628b5a80..b44d363a712 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vrev64q_m_s32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vrev64q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c
index eb6e560ac3c..4804b8acaf3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vrev64q_m_s8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vrev64q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c
index 4534a64ee84..12c26144cd2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vrev64q_m_u16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vrev64q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c
index 3f1ab24527c..ff90d92fff3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vrev64q_m_u32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vrev64q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c
index 4adb70963dd..267c3b6bee2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vrev64q_m_u8 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vrev64q_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c
index a886b0b0c6a..b6083f9d69c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a)
{
return vrev64q_s16 (a);
}
-/* { dg-final { scan-assembler "vrev64.16" } } */
+/*
+**foo1:
+** ...
+** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a)
{
return vrev64q (a);
}
-/* { dg-final { scan-assembler "vrev64.16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c
index b0ba64b186b..81fc7d1bdd0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a)
{
return vrev64q_s32 (a);
}
-/* { dg-final { scan-assembler "vrev64.32" } } */
+/*
+**foo1:
+** ...
+** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a)
{
return vrev64q (a);
}
-/* { dg-final { scan-assembler "vrev64.32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c
index 12f9f1ac389..3fced739681 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev64.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a)
{
return vrev64q_s8 (a);
}
-/* { dg-final { scan-assembler "vrev64.8" } } */
+/*
+**foo1:
+** ...
+** vrev64.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a)
{
return vrev64q (a);
}
-/* { dg-final { scan-assembler "vrev64.8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c
index ee3813428c9..b25fccc6c2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a)
{
- return vrev64q_u16 (a);
+ return vrev64q_u16 (a);
}
-/* { dg-final { scan-assembler "vrev64.16" } } */
+/*
+**foo1:
+** ...
+** vrev64.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a)
{
- return vrev64q (a);
+ return vrev64q (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrev64.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c
index c4a551dcc15..9d203b1f6bf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a)
{
- return vrev64q_u32 (a);
+ return vrev64q_u32 (a);
}
-/* { dg-final { scan-assembler "vrev64.32" } } */
+/*
+**foo1:
+** ...
+** vrev64.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a)
{
- return vrev64q (a);
+ return vrev64q (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrev64.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c
index 578d538f019..9acd52439e5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrev64.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a)
{
- return vrev64q_u8 (a);
+ return vrev64q_u8 (a);
}
-/* { dg-final { scan-assembler "vrev64.8" } } */
+/*
+**foo1:
+** ...
+** vrev64.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a)
{
- return vrev64q (a);
+ return vrev64q (a);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrev64.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c
index 467da7fe9ef..9c949028d8b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vrev64q_x_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, mve_pred16_t p)
{
return vrev64q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c
index 1a3cd17ebd6..445834a55f8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vrev64q_x_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, mve_pred16_t p)
{
return vrev64q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c
index b9932eddf38..66daa3d9131 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
return vrev64q_x_s16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, mve_pred16_t p)
{
return vrev64q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c
index 4eb3d4d09b1..2c5a5ee1a0c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
return vrev64q_x_s32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, mve_pred16_t p)
{
return vrev64q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c
index 5c22c387586..a24f17d5797 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, mve_pred16_t p)
{
return vrev64q_x_s8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, mve_pred16_t p)
{
return vrev64q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c
index bbf42931d92..4c11e79254b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vrev64q_x_u16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vrev64q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c
index 1b595c3ad2f..14f676e0cff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, mve_pred16_t p)
{
return vrev64q_x_u32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, mve_pred16_t p)
{
return vrev64q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c
index abff81e40b9..542dcaa782c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, mve_pred16_t p)
{
return vrev64q_x_u8 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrev64t.8 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, mve_pred16_t p)
{
return vrev64q_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c
index 01d72efc34b..0deef794352 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vrhaddq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vrhaddq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c
index dfe8d7334a8..e584987fb3e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrhaddq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrhaddq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c
index 9eceda2b115..40e3472bbf0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vrhaddq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vrhaddq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c
index ec11b660a4e..bd53871cc58 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vrhaddq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vrhaddq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c
index 25c6208ec06..30037083a01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrhaddq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrhaddq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c
index 7b25bf8faa8..3208ac1589b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vrhaddq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vrhaddq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c
index 36f36f77233..bafb1dc5795 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrhadd.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vrhaddq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.s16" } } */
+/*
+**foo1:
+** ...
+** vrhadd.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vrhaddq (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c
index 813cf91649e..bbee81fffd6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrhadd.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vrhaddq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.s32" } } */
+/*
+**foo1:
+** ...
+** vrhadd.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vrhaddq (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c
index 5ce1109d676..3fad58d4e0d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrhadd.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vrhaddq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.s8" } } */
+/*
+**foo1:
+** ...
+** vrhadd.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vrhaddq (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c
index 9d9bf18ec70..91273571ec8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrhadd.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b)
{
return vrhaddq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.u16" } } */
+/*
+**foo1:
+** ...
+** vrhadd.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b)
{
return vrhaddq (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c
index e465197505b..79a21051b0b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrhadd.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b)
{
return vrhaddq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.u32" } } */
+/*
+**foo1:
+** ...
+** vrhadd.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b)
{
return vrhaddq (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c
index cbede385f20..4bdd23419a3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrhadd.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b)
{
return vrhaddq_u8 (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.u8" } } */
+/*
+**foo1:
+** ...
+** vrhadd.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b)
{
return vrhaddq (a, b);
}
-/* { dg-final { scan-assembler "vrhadd.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c
index 8507b436dc8..363dedd3304 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vrhaddq_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vrhaddq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c
index 756c52f8f1e..f1df6749f33 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrhaddq_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrhaddq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c
index 9b580782098..107cf2daa58 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vrhaddq_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vrhaddq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c
index ec534c8262e..5837437d33c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vrhaddq_x_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vrhaddq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c
index c79f406439e..0d8d118987e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrhaddq_x_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrhaddq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c
index c4c16f8a753..37711710ee8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vrhaddq_x_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrhaddt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vrhaddq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
index 2134e3fc0dd..c18ff82f8f5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
@@ -46,4 +46,4 @@ foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
index 4ebd337e8ee..ba0a9587e3f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
@@ -62,4 +62,4 @@ foo2 (uint32x4_t b, uint32x4_t c, mve_pred16_t p)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c
index 2efde824eb3..b2ced4b41c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c
@@ -38,4 +38,4 @@ foo1 (int64_t a, int32x4_t b, int32x4_t c)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c
index 745655f31d0..96f1ab72e92 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c
@@ -50,4 +50,4 @@ foo2 (uint32x4_t b, uint32x4_t c)
}
#endif
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c
index 0e29e886ce1..a0164ed2bb7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlaldavhaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vrmlaldavhaxq_p_s32 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vrmlaldavhaxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlaldavhaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vrmlaldavhaxq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vrmlaldavhaxt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c
index 063c94d8c5b..4e71fd72e35 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmlaldavhax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c)
{
return vrmlaldavhaxq_s32 (a, b, c);
}
-/* { dg-final { scan-assembler "vrmlaldavhax.s32" } } */
+/*
+**foo1:
+** ...
+** vrmlaldavhax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c)
{
return vrmlaldavhaxq (a, b, c);
}
-/* { dg-final { scan-assembler "vrmlaldavhax.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c
index 1d7a5e3d690..b8f346f9740 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlaldavht.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmlaldavhq_p_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlaldavht.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlaldavht.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmlaldavhq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlaldavht.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c
index 539b04254cd..d6c6d503a9b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlaldavht.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrmlaldavhq_p_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlaldavht.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlaldavht.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrmlaldavhq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlaldavht.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c
index 566b85d1721..22c1164b6a9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmlaldavh.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b)
{
return vrmlaldavhq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vrmlaldavh.s32" } } */
+/*
+**foo1:
+** ...
+** vrmlaldavh.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b)
{
return vrmlaldavhq (a, b);
}
-/* { dg-final { scan-assembler "vrmlaldavh.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c
index 352cd58c8e8..6517ee8cd60 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmlaldavh.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
foo (uint32x4_t a, uint32x4_t b)
{
return vrmlaldavhq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vrmlaldavh.u32" } } */
+/*
+**foo1:
+** ...
+** vrmlaldavh.u32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint64_t
foo1 (uint32x4_t a, uint32x4_t b)
{
return vrmlaldavhq (a, b);
}
-/* { dg-final { scan-assembler "vrmlaldavh.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c
index d99ebffbea0..ebe1012f53f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlaldavhxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmlaldavhxq_p_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlaldavhxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlaldavhxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmlaldavhxq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlaldavhxt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c
index 64f02971eb3..56a2071d61c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmlaldavhx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b)
{
return vrmlaldavhxq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vrmlaldavhx.s32" } } */
+/*
+**foo1:
+** ...
+** vrmlaldavhx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b)
{
return vrmlaldavhxq (a, b);
}
-/* { dg-final { scan-assembler "vrmlaldavhx.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c
index 83d5a8ce251..aad2f009ba3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlsldavhat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vrmlsldavhaq_p_s32 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vrmlsldavhat.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlsldavhat.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vrmlsldavhaq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vrmlsldavhat.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c
index a8a320c6a43..f30870181b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmlsldavha.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c)
{
return vrmlsldavhaq_s32 (a, b, c);
}
-/* { dg-final { scan-assembler "vrmlsldavha.s32" } } */
+/*
+**foo1:
+** ...
+** vrmlsldavha.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c)
{
return vrmlsldavhaq (a, b, c);
}
-/* { dg-final { scan-assembler "vrmlsldavha.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c
index aa20ba1a7eb..2a3f441e429 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlsldavhaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vrmlsldavhaxq_p_s32 (a, b, c, p);
}
-/* { dg-final { scan-assembler "vrmlsldavhaxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlsldavhaxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
{
return vrmlsldavhaxq_p (a, b, c, p);
}
-/* { dg-final { scan-assembler "vrmlsldavhaxt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c
index 78932840dfe..06afa309bfa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmlsldavhax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c)
{
return vrmlsldavhaxq_s32 (a, b, c);
}
-/* { dg-final { scan-assembler "vrmlsldavhax.s32" } } */
+/*
+**foo1:
+** ...
+** vrmlsldavhax.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c)
{
return vrmlsldavhaxq (a, b, c);
}
-/* { dg-final { scan-assembler "vrmlsldavhax.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c
index 1e2127a17be..9f1f82a7c62 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlsldavht.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmlsldavhq_p_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlsldavht.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlsldavht.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmlsldavhq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlsldavht.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c
index 2a7844fa370..ff867d5c208 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmlsldavh.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b)
{
return vrmlsldavhq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vrmlsldavh.s32" } } */
+/*
+**foo1:
+** ...
+** vrmlsldavh.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b)
{
return vrmlsldavhq (a, b);
}
-/* { dg-final { scan-assembler "vrmlsldavh.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c
index ecbc9737d8f..2a127c76df8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlsldavhxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmlsldavhxq_p_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlsldavhxt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmlsldavhxt.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmlsldavhxq_p (a, b, p);
}
-/* { dg-final { scan-assembler "vrmlsldavhxt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c
index 0cea55724aa..41539059d7f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmlsldavhx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo (int32x4_t a, int32x4_t b)
{
return vrmlsldavhxq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vrmlsldavhx.s32" } } */
+/*
+**foo1:
+** ...
+** vrmlsldavhx.s32 (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int64_t
foo1 (int32x4_t a, int32x4_t b)
{
return vrmlsldavhxq (a, b);
}
-/* { dg-final { scan-assembler "vrmlsldavhx.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c
index 6adaf3f6431..e5c70a0a323 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vrmulhq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vrmulhq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c
index a90a67971c8..6b373e1739a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmulhq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmulhq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c
index d0dd99aa4c3..961ba71ccb7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vrmulhq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vrmulhq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c
index 50d05c1de11..3a782c295e1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vrmulhq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vrmulhq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c
index a7da7330266..818fb631ff7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrmulhq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrmulhq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c
index 42b0b9f0f2f..3d1eb365c63 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vrmulhq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vrmulhq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c
index ac77b9f13ba..34c3f182628 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmulh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vrmulhq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.s16" } } */
+/*
+**foo1:
+** ...
+** vrmulh.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vrmulhq (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c
index a7bbd19c393..fe4d11c5acd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmulh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vrmulhq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.s32" } } */
+/*
+**foo1:
+** ...
+** vrmulh.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vrmulhq (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c
index b0d1a856794..4b5a2e656ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmulh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vrmulhq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.s8" } } */
+/*
+**foo1:
+** ...
+** vrmulh.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vrmulhq (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c
index b43cb07b1bf..478d5885edd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmulh.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b)
{
return vrmulhq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.u16" } } */
+/*
+**foo1:
+** ...
+** vrmulh.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b)
{
return vrmulhq (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c
index f37eeb606f2..e3dc75d10aa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmulh.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b)
{
return vrmulhq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.u32" } } */
+/*
+**foo1:
+** ...
+** vrmulh.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b)
{
return vrmulhq (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c
index ab5d7597a43..108357b6d35 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrmulh.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b)
{
return vrmulhq_u8 (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.u8" } } */
+/*
+**foo1:
+** ...
+** vrmulh.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b)
{
return vrmulhq (a, b);
}
-/* { dg-final { scan-assembler "vrmulh.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c
index 3ef89bd686b..00f728bdaf2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vrmulhq_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vrmulhq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c
index 2a4b9d0d147..49a739d9a95 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmulhq_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vrmulhq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c
index d3ef8713dba..7d97cbc5f8e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vrmulhq_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vrmulhq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c
index 5ce4d01a235..31622dce8df 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vrmulhq_x_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
return vrmulhq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c
index 4a965976c2d..f6d2582bac8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrmulhq_x_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
return vrmulhq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c
index 015530c08b2..15e947618f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vrmulhq_x_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrmulht.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
return vrmulhq_x (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c
index ba8426fdff3..17b11972e84 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrinta.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a)
{
return vrndaq_f16 (a);
}
-/* { dg-final { scan-assembler "vrinta.f16" } } */
+
+/*
+**foo1:
+** ...
+** vrinta.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+ return vrndaq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c
index a8c9c28422f..dc3689a66d1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrinta.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a)
{
return vrndaq_f32 (a);
}
-/* { dg-final { scan-assembler "vrinta.f32" } } */
+
+/*
+**foo1:
+** ...
+** vrinta.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+ return vrndaq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c
index 3617d796351..ffbdf3dad94 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintat.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndaq_m_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintat.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintat.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndaq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c
index fdb9ddb3551..d20f8050c45 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintat.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndaq_m_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintat.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintat.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndaq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c
index f398e86b689..141f612ddcb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintat.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vrndaq_x_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintat.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintat.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, mve_pred16_t p)
{
return vrndaq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c
index f5f21808528..277d2a7b668 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintat.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vrndaq_x_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintat.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintat.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, mve_pred16_t p)
{
return vrndaq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c
index 911a2b1cb29..a51878645da 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintm.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a)
{
return vrndmq_f16 (a);
}
-/* { dg-final { scan-assembler "vrintm.f16" } } */
+
+/*
+**foo1:
+** ...
+** vrintm.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+ return vrndmq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c
index 496a2e55d55..4b79490cc21 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintm.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a)
{
return vrndmq_f32 (a);
}
-/* { dg-final { scan-assembler "vrintm.f32" } } */
+
+/*
+**foo1:
+** ...
+** vrintm.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+ return vrndmq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c
index 86f58e2eb88..e6eb2a1015d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintmt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndmq_m_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintmt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintmt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndmq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c
index 247595df56a..99f3f206823 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintmt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndmq_m_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintmt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintmt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndmq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c
index accc79579ec..cdef684f381 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintmt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vrndmq_x_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintmt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintmt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, mve_pred16_t p)
{
return vrndmq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c
index 0e4200dc2f5..94da7738d16 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintmt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vrndmq_x_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintmt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintmt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, mve_pred16_t p)
{
return vrndmq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c
index 23299c2a06f..b1b31bebb11 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintn.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a)
{
return vrndnq_f16 (a);
}
-/* { dg-final { scan-assembler "vrintn.f16" } } */
+
+/*
+**foo1:
+** ...
+** vrintn.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+ return vrndnq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c
index ce445f2249f..e2fec8a87e2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintn.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a)
{
return vrndnq_f32 (a);
}
-/* { dg-final { scan-assembler "vrintn.f32" } } */
+
+/*
+**foo1:
+** ...
+** vrintn.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+ return vrndnq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c
index c41e38070bf..04d828bde24 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintnt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndnq_m_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintnt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintnt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c
index 09b9b95d67d..b32eacd9b20 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintnt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndnq_m_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintnt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintnt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndnq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c
index beeb23cf364..093aaa04d57 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintnt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vrndnq_x_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintnt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintnt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, mve_pred16_t p)
{
return vrndnq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c
index d09e55d53b3..8428800d503 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintnt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vrndnq_x_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintnt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintnt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, mve_pred16_t p)
{
return vrndnq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c
index 25dcbd5f3bf..3145faf9f70 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintp.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a)
{
return vrndpq_f16 (a);
}
-/* { dg-final { scan-assembler "vrintp.f16" } } */
+
+/*
+**foo1:
+** ...
+** vrintp.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+ return vrndpq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c
index 5ab6f7ae9c3..2754af48612 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintp.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a)
{
return vrndpq_f32 (a);
}
-/* { dg-final { scan-assembler "vrintp.f32" } } */
+
+/*
+**foo1:
+** ...
+** vrintp.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+ return vrndpq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c
index 2cf8220c789..e62883c1edb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintpt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndpq_m_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintpt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintpt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndpq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c
index 7ed26e8d926..b8370b85373 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintpt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndpq_m_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintpt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintpt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndpq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c
index 233a6e843e8..57465385173 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintpt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vrndpq_x_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintpt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintpt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, mve_pred16_t p)
{
return vrndpq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c
index f689ce6510b..86a94c0dfe5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintpt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vrndpq_x_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintpt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintpt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, mve_pred16_t p)
{
return vrndpq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c
index 6fe3b2eae48..4b2ee2c3da2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintz.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a)
{
return vrndq_f16 (a);
}
-/* { dg-final { scan-assembler "vrintz.f16" } } */
+
+/*
+**foo1:
+** ...
+** vrintz.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+ return vrndq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c
index a27b5c99b3a..301e9e4c25e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintz.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a)
{
return vrndq_f32 (a);
}
-/* { dg-final { scan-assembler "vrintz.f32" } } */
+
+/*
+**foo1:
+** ...
+** vrintz.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+ return vrndq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c
index 3a9edafc772..d7ba6d4f11f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintzt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndq_m_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintzt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintzt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c
index 0ae4b92d235..6bfe1d49941 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintzt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndq_m_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintzt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintzt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c
index eb6c3c37876..13ba05011e4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintzt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vrndq_x_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintzt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintzt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, mve_pred16_t p)
{
return vrndq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c
index 8b4c8c1e289..162d199420d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintzt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vrndq_x_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintzt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintzt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, mve_pred16_t p)
{
return vrndq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c
index e6f2028de30..9df65c5473d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintx.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a)
{
return vrndxq_f16 (a);
}
-/* { dg-final { scan-assembler "vrintx.f16" } } */
+
+/*
+**foo1:
+** ...
+** vrintx.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+ return vrndxq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c
index 32e6c90e60e..92bc6df1361 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c
@@ -1,13 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrintx.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a)
{
return vrndxq_f32 (a);
}
-/* { dg-final { scan-assembler "vrintx.f32" } } */
+
+/*
+**foo1:
+** ...
+** vrintx.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+ return vrndxq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c
index 0e6a6119f08..9d92566b08d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintxt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndxq_m_f16 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintxt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintxt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vrndxq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c
index 3b09769814b..7a216050fb1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintxt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndxq_m_f32 (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintxt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintxt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vrndxq_m (inactive, a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c
index c160800023f..537506cd5be 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintxt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo (float16x8_t a, mve_pred16_t p)
{
return vrndxq_x_f16 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintxt.f16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintxt.f16 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float16x8_t
foo1 (float16x8_t a, mve_pred16_t p)
{
return vrndxq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c
index 48b76161032..e19ba0c0a3c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintxt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo (float32x4_t a, mve_pred16_t p)
{
return vrndxq_x_f32 (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintxt.f32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrintxt.f32 q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
float32x4_t
foo1 (float32x4_t a, mve_pred16_t p)
{
return vrndxq_x (a, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c
index 9e7f22ccad9..e30cfe16fdf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vrshrnbq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vrshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c
index 6b6a98c3da4..acb89bd462a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vrshrnbq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vrshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c
index e54893d2abc..4d0c6048971 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vrshrnbq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vrshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c
index ecb41a2c444..1b768a13061 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vrshrnbq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vrshrnbq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c
index f09db27adee..6350e3c4cca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vrshrnbq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnb.i16" } } */
+/*
+**foo1:
+** ...
+** vrshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vrshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnb.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c
index 2bc4170b07f..8ae96d8a2b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vrshrnbq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnb.i32" } } */
+/*
+**foo1:
+** ...
+** vrshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vrshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnb.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c
index 990871f5b9e..2918cb05e43 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vrshrnbq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnb.i16" } } */
+/*
+**foo1:
+** ...
+** vrshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vrshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnb.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c
index 875fed28fe7..c615d8083d7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vrshrnbq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnb.i32" } } */
+/*
+**foo1:
+** ...
+** vrshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vrshrnbq (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnb.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c
index 72206c36fda..639f25ed719 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vrshrntq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
return vrshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c
index e964af2e8b5..07a53e364f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vrshrntq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
return vrshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c
index ad98b7677f0..f00d62bcb7a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vrshrntq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
return vrshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c
index adee8b28b88..bb809acfe6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vrshrntq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
return vrshrntq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c
index 4c2f133b605..926a897d50e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vrshrntq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnt.i16" } } */
+/*
+**foo1:
+** ...
+** vrshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vrshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnt.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c
index 26508ba7961..7e931355751 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vrshrntq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnt.i32" } } */
+/*
+**foo1:
+** ...
+** vrshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vrshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnt.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c
index eea3d4974db..61636d301f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vrshrntq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnt.i16" } } */
+/*
+**foo1:
+** ...
+** vrshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vrshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnt.i16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c
index 49afdf0c61e..b82dad525f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vrshrntq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnt.i32" } } */
+/*
+**foo1:
+** ...
+** vrshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vrshrntq (a, b, 1);
}
-/* { dg-final { scan-assembler "vrshrnt.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c
index ee48f8c2733..b1a2f813320 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
- return vrshrq_m_n_s16 (inactive, a, 16, p);
+ return vrshrq_m_n_s16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
- return vrshrq_m (inactive, a, 16, p);
+ return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c
index 4330dcfaaa6..fb229273b86 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
- return vrshrq_m_n_s32 (inactive, a, 32, p);
+ return vrshrq_m_n_s32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
- return vrshrq_m (inactive, a, 32, p);
+ return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c
index 4b35c597a13..b9136b8dd69 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
- return vrshrq_m_n_s8 (inactive, a, 8, p);
+ return vrshrq_m_n_s8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
- return vrshrq_m (inactive, a, 8, p);
+ return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c
index 2e83c60ad95..9dbc3fed62a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
- return vrshrq_m_n_u16 (inactive, a, 16, p);
+ return vrshrq_m_n_u16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
- return vrshrq_m (inactive, a, 16, p);
+ return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c
index 5d2a9d8f4f4..0e0cb10b476 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
- return vrshrq_m_n_u32 (inactive, a, 32, p);
+ return vrshrq_m_n_u32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
- return vrshrq_m (inactive, a, 32, p);
+ return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c
index f5b43708689..010a7915c56 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
- return vrshrq_m_n_u8 (inactive, a, 8, p);
+ return vrshrq_m_n_u8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
- return vrshrq_m (inactive, a, 8, p);
+ return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c
index 2cd934774ce..ff3d552bd78 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshr.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a)
{
- return vrshrq_n_s16 (a, 16);
+ return vrshrq_n_s16 (a, 1);
}
-/* { dg-final { scan-assembler "vrshr.s16" } } */
+/*
+**foo1:
+** ...
+** vrshr.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a)
{
- return vrshrq (a, 16);
+ return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrshr.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c
index 3cc21f2b277..db161f7d009 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshr.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a)
{
- return vrshrq_n_s32 (a, 32);
+ return vrshrq_n_s32 (a, 1);
}
-/* { dg-final { scan-assembler "vrshr.s32" } } */
+/*
+**foo1:
+** ...
+** vrshr.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a)
{
- return vrshrq (a, 32);
+ return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrshr.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c
index 251d5324f5c..86a0294f8a8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshr.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a)
{
- return vrshrq_n_s8 (a, 8);
+ return vrshrq_n_s8 (a, 1);
}
-/* { dg-final { scan-assembler "vrshr.s8" } } */
+/*
+**foo1:
+** ...
+** vrshr.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a)
{
- return vrshrq (a, 8);
+ return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrshr.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c
index 6934597f844..897247fce6c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshr.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a)
{
- return vrshrq_n_u16 (a, 16);
+ return vrshrq_n_u16 (a, 1);
}
-/* { dg-final { scan-assembler "vrshr.u16" } } */
+/*
+**foo1:
+** ...
+** vrshr.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a)
{
- return vrshrq (a, 16);
+ return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrshr.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c
index 52b287b8f3b..e8f7f1c33e0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshr.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a)
{
- return vrshrq_n_u32 (a, 32);
+ return vrshrq_n_u32 (a, 1);
}
-/* { dg-final { scan-assembler "vrshr.u32" } } */
+/*
+**foo1:
+** ...
+** vrshr.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a)
{
- return vrshrq (a, 32);
+ return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrshr.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c
index ac595a9ac95..a22521b14ae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vrshr.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a)
{
- return vrshrq_n_u8 (a, 8);
+ return vrshrq_n_u8 (a, 1);
}
-/* { dg-final { scan-assembler "vrshr.u8" } } */
+/*
+**foo1:
+** ...
+** vrshr.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a)
{
- return vrshrq (a, 8);
+ return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vrshr.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c
index 14b5c1884f4..37f364cfc39 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
- return vrshrq_x_n_s16 (a, 16, p);
+ return vrshrq_x_n_s16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, mve_pred16_t p)
{
- return vrshrq_x (a, 16, p);
+ return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c
index 846ddb96782..0da2fd75056 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
- return vrshrq_x_n_s32 (a, 32, p);
+ return vrshrq_x_n_s32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, mve_pred16_t p)
{
- return vrshrq_x (a, 32, p);
+ return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c
index 06f75e56db6..90c814b20c5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, mve_pred16_t p)
{
- return vrshrq_x_n_s8 (a, 8, p);
+ return vrshrq_x_n_s8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, mve_pred16_t p)
{
- return vrshrq_x (a, 8, p);
+ return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c
index bc946497cfc..135b9e7e90f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
- return vrshrq_x_n_u16 (a, 16, p);
+ return vrshrq_x_n_u16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
- return vrshrq_x (a, 16, p);
+ return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c
index 55002cd196d..dd656f49aa7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, mve_pred16_t p)
{
- return vrshrq_x_n_u32 (a, 32, p);
+ return vrshrq_x_n_u32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, mve_pred16_t p)
{
- return vrshrq_x (a, 32, p);
+ return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c
index e3130657711..e41abc450a0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, mve_pred16_t p)
{
- return vrshrq_x_n_u8 (a, 8, p);
+ return vrshrq_x_n_u8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vrshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, mve_pred16_t p)
{
- return vrshrq_x (a, 8, p);
+ return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
index 21f4219faa3..66a5c4c9da3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
@@ -1,23 +1,61 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsbcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p)
{
return vsbciq_m_s32 (inactive, a, b, carry_out, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbcit.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsbcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p)
{
return vsbciq_m (inactive, a, b, carry_out, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbcit.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
index ef9eed92d33..9306f152cde 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
@@ -1,23 +1,61 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsbcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p)
{
return vsbciq_m_u32 (inactive, a, b, carry_out, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbcit.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsbcit.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p)
{
return vsbciq_m (inactive, a, b, carry_out, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbcit.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
index 2181a3a2879..0b5040f0b2a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsbci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t a, int32x4_t b, unsigned * carry_out)
+foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
{
return vsbciq_s32 (a, b, carry_out);
}
-/* { dg-final { scan-assembler "vsbci.i32" } } */
+/*
+**foo1:
+** ...
+** vsbci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t a, int32x4_t b, unsigned * carry_out)
+foo1 (int32x4_t a, int32x4_t b, unsigned *carry_out)
{
- return vsbciq_s32 (a, b, carry_out);
+ return vsbciq (a, b, carry_out);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsbci.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
index df0487f3b88..df211a64daa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
@@ -1,21 +1,53 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsbci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, unsigned * carry_out)
+foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
{
return vsbciq_u32 (a, b, carry_out);
}
-/* { dg-final { scan-assembler "vsbci.i32" } } */
+/*
+**foo1:
+** ...
+** vsbci.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry_out)
+foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
{
- return vsbciq_u32 (a, b, carry_out);
+ return vsbciq (a, b, carry_out);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsbci.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
index 73be46a8459..217cfa7ac21 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
@@ -1,23 +1,73 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p)
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p)
{
- return vsbcq_m_s32 (inactive, a, b, carry, p);
+ return vsbcq_m_s32 (inactive, a, b, carry, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbct.i32" } } */
+/*
+**foo1:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo1(int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p)
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p)
{
- return vsbcq_m (inactive, a, b, carry, p);
+ return vsbcq_m (inactive, a, b, carry, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbct.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
index 80cf70584e5..dad04d05d68 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
@@ -1,22 +1,73 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p)
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p)
{
- return vsbcq_m_u32 (inactive, a, b, carry, p);
+ return vsbcq_m_u32 (inactive, a, b, carry, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbct.i32" } } */
+
+/*
+**foo1:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p)
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p)
{
- return vsbcq_m (inactive, a, b, carry, p);
+ return vsbcq_m (inactive, a, b, carry, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbct.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
index 23e42575bd7..cd033640bcc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
@@ -1,21 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vsbc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t a, int32x4_t b, unsigned * carry)
+foo (int32x4_t a, int32x4_t b, unsigned *carry)
{
return vsbcq_s32 (a, b, carry);
}
-/* { dg-final { scan-assembler "vsbc.i32" } } */
+/*
+**foo1:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vsbc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t a, int32x4_t b, unsigned * carry)
+foo1 (int32x4_t a, int32x4_t b, unsigned *carry)
{
return vsbcq (a, b, carry);
}
-/* { dg-final { scan-assembler "vsbc.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
index d3aa66f6134..6ca0c753b5e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
@@ -1,21 +1,65 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vsbc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, unsigned * carry)
+foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
{
return vsbcq_u32 (a, b, carry);
}
-/* { dg-final { scan-assembler "vsbc.i32" } } */
+/*
+**foo1:
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
+** ...
+** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vsbc.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
+** ...
+** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
+** ...
+** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry)
+foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry)
{
return vsbcq (a, b, carry);
}
-/* { dg-final { scan-assembler "vsbc.i32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c
index c4c77f2559c..c603a89117f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
-foo (int16x8_t a, uint32_t * b, mve_pred16_t p)
+foo (int16x8_t a, uint32_t *b, mve_pred16_t p)
{
- return vshlcq_m_s16 (a, b, 32, p);
+ return vshlcq_m_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
-foo1 (int16x8_t a, uint32_t * b, mve_pred16_t p)
+foo1 (int16x8_t a, uint32_t *b, mve_pred16_t p)
{
- return vshlcq_m (a, b, 32, p);
+ return vshlcq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c
index 20cfd09c82d..46e75033ae6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t a, uint32_t * b, mve_pred16_t p)
+foo (int32x4_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t a, uint32_t * b, mve_pred16_t p)
+foo1 (int32x4_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c
index 33dde10e4a8..868de5df80b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
-foo (int8x16_t a, uint32_t * b, mve_pred16_t p)
+foo (int8x16_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m_s8 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
-foo1 (int8x16_t a, uint32_t * b, mve_pred16_t p)
+foo1 (int8x16_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c
index 2bf69f0c465..a1e1c3f9bc4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint16x8_t a, uint32_t * b, mve_pred16_t p)
+foo (uint16x8_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
-foo1 (uint16x8_t a, uint32_t * b, mve_pred16_t p)
+foo1 (uint16x8_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c
index e6650302ea7..bcb0bebd969 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t a, uint32_t * b, mve_pred16_t p)
+foo (uint32x4_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t a, uint32_t * b, mve_pred16_t p)
+foo1 (uint32x4_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c
index 95857f09371..98936447451 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
-foo (uint8x16_t a, uint32_t * b, mve_pred16_t p)
+foo (uint8x16_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m_u8 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlct q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
-foo1 (uint8x16_t a, uint32_t * b, mve_pred16_t p)
+foo1 (uint8x16_t a, uint32_t *b, mve_pred16_t p)
{
return vshlcq_m (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c
index ecd4fce5de3..e6c5069af21 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
-foo (int16x8_t a, uint32_t * b)
+foo (int16x8_t a, uint32_t *b)
{
return vshlcq_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+/*
+**foo1:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
-foo1 (int16x8_t a, uint32_t * b)
+foo1 (int16x8_t a, uint32_t *b)
{
return vshlcq (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c
index 2956b93138e..2c17845fd7e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
-foo (int32x4_t a, uint32_t * b)
+foo (int32x4_t a, uint32_t *b)
{
return vshlcq_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+/*
+**foo1:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
-foo1 (int32x4_t a, uint32_t * b)
+foo1 (int32x4_t a, uint32_t *b)
{
return vshlcq (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c
index cc22b1b1bd9..ab55f3a29ba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
-foo (int8x16_t a, uint32_t * b)
+foo (int8x16_t a, uint32_t *b)
{
return vshlcq_s8 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+/*
+**foo1:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
-foo1 (int8x16_t a, uint32_t * b)
+foo1 (int8x16_t a, uint32_t *b)
{
return vshlcq (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c
index bbf6c531573..e1862be0249 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
-foo (uint16x8_t a, uint32_t * b)
+foo (uint16x8_t a, uint32_t *b)
{
return vshlcq_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+/*
+**foo1:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
-foo1 (uint16x8_t a, uint32_t * b)
+foo1 (uint16x8_t a, uint32_t *b)
{
return vshlcq (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c
index c42d9c10afe..dc1030fbedf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
-foo (uint32x4_t a, uint32_t * b)
+foo (uint32x4_t a, uint32_t *b)
{
return vshlcq_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+/*
+**foo1:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
-foo1 (uint32x4_t a, uint32_t * b)
+foo1 (uint32x4_t a, uint32_t *b)
{
return vshlcq (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c
index f24b22797c2..cb24651a294 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
-foo (uint8x16_t a, uint32_t * b)
+foo (uint8x16_t a, uint32_t *b)
{
return vshlcq_u8 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+/*
+**foo1:
+** ...
+** vshlc q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
-foo1 (uint8x16_t a, uint32_t * b)
+foo1 (uint8x16_t a, uint32_t *b)
{
return vshlcq (a, b, 1);
}
-/* { dg-final { scan-assembler "vshlc" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c
index 6d6c4b2d737..1ee641d8d68 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
{
return vshllbq_m_n_s16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
{
return vshllbq_m (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c
index 5d7b9623f1a..93a06cb2676 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
{
return vshllbq_m_n_s8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
{
return vshllbq_m (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c
index 3697775ea0f..67039260cd5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vshllbq_m_n_u16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vshllbq_m (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c
index 39a10e21b0b..f02293bb874 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vshllbq_m_n_u8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vshllbq_m (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c
index 7d3a4d811cb..906f7fb75d1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshllb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int16x8_t a)
{
return vshllbq_n_s16 (a, 1);
}
-/* { dg-final { scan-assembler "vshllb.s16" } } */
+/*
+**foo1:
+** ...
+** vshllb.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int16x8_t a)
{
return vshllbq (a, 1);
}
-/* { dg-final { scan-assembler "vshllb.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c
index 63b406978c1..f63ff4b7556 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshllb.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int8x16_t a)
{
return vshllbq_n_s8 (a, 1);
}
-/* { dg-final { scan-assembler "vshllb.s8" } } */
+/*
+**foo1:
+** ...
+** vshllb.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int8x16_t a)
{
return vshllbq (a, 1);
}
-/* { dg-final { scan-assembler "vshllb.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c
index 9306d244645..883d2979f32 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshllb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint16x8_t a)
{
return vshllbq_n_u16 (a, 1);
}
-/* { dg-final { scan-assembler "vshllb.u16" } } */
+/*
+**foo1:
+** ...
+** vshllb.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint16x8_t a)
{
return vshllbq (a, 1);
}
-/* { dg-final { scan-assembler "vshllb.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c
index 0b24160216e..bbdec7ba321 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshllb.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint8x16_t a)
{
return vshllbq_n_u8 (a, 1);
}
-/* { dg-final { scan-assembler "vshllb.u8" } } */
+/*
+**foo1:
+** ...
+** vshllb.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint8x16_t a)
{
return vshllbq (a, 1);
}
-/* { dg-final { scan-assembler "vshllb.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c
index 689fc749b00..239c536f4a4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int16x8_t a, mve_pred16_t p)
{
- return vshllbq_x_n_s16 (a, 1, p);
+ return vshllbq_x_n_s16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int32x4_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+ return vshllbq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c
index 82f684d1cd5..9371b523c3f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int8x16_t a, mve_pred16_t p)
{
- return vshllbq_x_n_s8 (a, 1, p);
+ return vshllbq_x_n_s8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int16x8_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+ return vshllbq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c
index 5c51a4e4011..72f9aed343e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint16x8_t a, mve_pred16_t p)
{
- return vshllbq_x_n_u16 (a, 1, p);
+ return vshllbq_x_n_u16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint32x4_t
+foo1 (uint16x8_t a, mve_pred16_t p)
+{
+ return vshllbq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c
index 5a713befb27..bd209428300 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint8x16_t a, mve_pred16_t p)
{
- return vshllbq_x_n_u8 (a, 1, p);
+ return vshllbq_x_n_u8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshllbt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo1 (uint8x16_t a, mve_pred16_t p)
+{
+ return vshllbq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c
index 8153a570a9a..80035011527 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
{
return vshlltq_m_n_s16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
{
return vshlltq_m (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c
index 3f47337c9b6..19e2f3c7469 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
{
return vshlltq_m_n_s8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
{
return vshlltq_m (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c
index f5af1b31087..46af8731146 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vshlltq_m_n_u16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vshlltq_m (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c
index 92154d25387..ed7814c39dc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vshlltq_m_n_u8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vshlltq_m (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c
index ced2aa64217..b2987300406 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshllt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int16x8_t a)
{
return vshlltq_n_s16 (a, 1);
}
-/* { dg-final { scan-assembler "vshllt.s16" } } */
+/*
+**foo1:
+** ...
+** vshllt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int16x8_t a)
{
return vshlltq (a, 1);
}
-/* { dg-final { scan-assembler "vshllt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c
index 9fc0cd7ced9..c5b84aa5e2e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshllt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int8x16_t a)
{
return vshlltq_n_s8 (a, 1);
}
-/* { dg-final { scan-assembler "vshllt.s8" } } */
+/*
+**foo1:
+** ...
+** vshllt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int8x16_t a)
{
return vshlltq (a, 1);
}
-/* { dg-final { scan-assembler "vshllt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c
index 47b948e2468..358a5b4a3e7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshllt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint16x8_t a)
{
return vshlltq_n_u16 (a, 1);
}
-/* { dg-final { scan-assembler "vshllt.u16" } } */
+/*
+**foo1:
+** ...
+** vshllt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint16x8_t a)
{
return vshlltq (a, 1);
}
-/* { dg-final { scan-assembler "vshllt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c
index eac7422a1f1..223649215a6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshllt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint8x16_t a)
{
return vshlltq_n_u8 (a, 1);
}
-/* { dg-final { scan-assembler "vshllt.u8" } } */
+/*
+**foo1:
+** ...
+** vshllt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint8x16_t a)
{
return vshlltq (a, 1);
}
-/* { dg-final { scan-assembler "vshllt.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c
index 0e9e789c1e0..12d55e49aed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int16x8_t a, mve_pred16_t p)
{
- return vshlltq_x_n_s16 (a, 1, p);
+ return vshlltq_x_n_s16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int32x4_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+ return vshlltq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c
index 67966bed12c..dfad54a5eae 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int8x16_t a, mve_pred16_t p)
{
- return vshlltq_x_n_s8 (a, 1, p);
+ return vshlltq_x_n_s8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int16x8_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+ return vshlltq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c
index dedc795797e..e9077d26918 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint16x8_t a, mve_pred16_t p)
{
- return vshlltq_x_n_u16 (a, 1, p);
+ return vshlltq_x_n_u16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint32x4_t
+foo1 (uint16x8_t a, mve_pred16_t p)
+{
+ return vshlltq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c
index a93c69d8d98..1d4d2795fa9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint8x16_t a, mve_pred16_t p)
{
- return vshlltq_x_n_u8 (a, 1, p);
+ return vshlltq_x_n_u8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlltt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo1 (uint8x16_t a, mve_pred16_t p)
+{
+ return vshlltq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c
index 6c0342da0cc..754d412c81d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vshlq_m_n_s16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c
index 0e472801de5..5805f90a105 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vshlq_m_n_s32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c
index 0f9efacc749..b69b52cf099 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vshlq_m_n_s8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
return vshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c
index 0c4d9e9b7b5..152844bf318 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vshlq_m_n_u16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c
index cf247f879aa..9acfd9b8c6e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vshlq_m_n_u32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c
index 64bda13216d..d2e7fe59f3f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vshlq_m_n_u8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
return vshlq_m_n (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c
index abd747e9008..ce72e8c408b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c
index 001a8d170fc..219c7d2ca73 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c
index 890dd359e65..22fdee6bd6c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c
index 91574c5db26..25eca63907d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c
index f6ec8797a83..9d24eda6e60 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c
index 37f0f488801..2421e0b72ec 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
{
return vshlq_m_r (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c
index 759379c9fc5..c28996ad2cc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vshlq_m_s16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c
index 4878f0b0e4f..ca4801df9ba 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vshlq_m_s32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c
index f4ed7f5aaeb..782eedbc774 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vshlq_m_s8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c
index 99ae7ed9a53..941a6cc3578 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vshlq_m_u16 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
{
return vshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c
index 7094ba2ccd7..75e10801ae7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vshlq_m_u32 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
{
return vshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c
index e7c481a3b8c..dbabcd55900 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vshlq_m_u8 (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
{
return vshlq_m (inactive, a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c
index e24bb9acd75..83dee27238a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a)
{
return vshlq_n_s16 (a, 1);
}
-/* { dg-final { scan-assembler "vshl.s16" } } */
+/*
+**foo1:
+** ...
+** vshl.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a)
{
return vshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vshl.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c
index f537879249f..6b390c8b333 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a)
{
- return vshlq_n_s32 (a, 16);
+ return vshlq_n_s32 (a, 1);
}
-/* { dg-final { scan-assembler "vshl.s32" } } */
+/*
+**foo1:
+** ...
+** vshl.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a)
{
- return vshlq_n (a, 16);
+ return vshlq_n (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshl.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c
index ba6ddf3f8a1..e4fd7121bff 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a)
{
return vshlq_n_s8 (a, 1);
}
-/* { dg-final { scan-assembler "vshl.s8" } } */
+/*
+**foo1:
+** ...
+** vshl.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a)
{
return vshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vshl.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c
index 730c7af40c6..6c37303a9fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a)
{
- return vshlq_n_u16 (a, 11);
+ return vshlq_n_u16 (a, 1);
}
-/* { dg-final { scan-assembler "vshl.u16" } } */
+/*
+**foo1:
+** ...
+** vshl.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a)
{
- return vshlq_n (a, 11);
+ return vshlq_n (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshl.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c
index 36caf5a9032..408f756408f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a)
{
return vshlq_n_u32 (a, 1);
}
-/* { dg-final { scan-assembler "vshl.u32" } } */
+/*
+**foo1:
+** ...
+** vshl.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a)
{
return vshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vshl.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c
index a5ba9805d9b..5ecdddccadf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a)
{
return vshlq_n_u8 (a, 1);
}
-/* { dg-final { scan-assembler "vshl.u8" } } */
+/*
+**foo1:
+** ...
+** vshl.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a)
{
return vshlq_n (a, 1);
}
-/* { dg-final { scan-assembler "vshl.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c
index b6d3e858d7c..f9a8257729e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32_t b)
{
return vshlq_r_s16 (a, b);
}
-/* { dg-final { scan-assembler "vshl.s16" } } */
+/*
+**foo1:
+** ...
+** vshl.s16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32_t b)
{
return vshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vshl.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c
index e04e2a7bcf3..f4f8e363059 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32_t b)
{
return vshlq_r_s32 (a, b);
}
-/* { dg-final { scan-assembler "vshl.s32" } } */
+/*
+**foo1:
+** ...
+** vshl.s32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32_t b)
{
return vshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vshl.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c
index d5e54c0a79a..c14d012a1e2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int32_t b)
{
return vshlq_r_s8 (a, b);
}
-/* { dg-final { scan-assembler "vshl.s8" } } */
+/*
+**foo1:
+** ...
+** vshl.s8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int32_t b)
{
return vshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vshl.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c
index 813bea0575d..71634680deb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int32_t b)
{
return vshlq_r_u16 (a, b);
}
-/* { dg-final { scan-assembler "vshl.u16" } } */
+/*
+**foo1:
+** ...
+** vshl.u16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int32_t b)
{
return vshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vshl.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c
index 84a61e47ca7..0d47f85bc82 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32_t b)
{
return vshlq_r_u32 (a, b);
}
-/* { dg-final { scan-assembler "vshl.u32" } } */
+/*
+**foo1:
+** ...
+** vshl.u32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32_t b)
{
return vshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vshl.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c
index 01f9a7d8f19..2d64908eeca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int32_t b)
{
return vshlq_r_u8 (a, b);
}
-/* { dg-final { scan-assembler "vshl.u8" } } */
+/*
+**foo1:
+** ...
+** vshl.u8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int32_t b)
{
return vshlq_r (a, b);
}
-/* { dg-final { scan-assembler "vshl.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c
index 5d3e1e5fdf9..6158fafcdb5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
return vshlq_s16 (a, b);
}
-/* { dg-final { scan-assembler "vshl.s16" } } */
+/*
+**foo1:
+** ...
+** vshl.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
return vshlq (a, b);
}
-/* { dg-final { scan-assembler "vshl.s16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c
index cecd050888f..b0b18470dea 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
return vshlq_s32 (a, b);
}
-/* { dg-final { scan-assembler "vshl.s32" } } */
+/*
+**foo1:
+** ...
+** vshl.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
return vshlq (a, b);
}
-/* { dg-final { scan-assembler "vshl.s32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c
index d44610f4f5b..70b2d806131 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
return vshlq_s8 (a, b);
}
-/* { dg-final { scan-assembler "vshl.s8" } } */
+/*
+**foo1:
+** ...
+** vshl.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
return vshlq (a, b);
}
-/* { dg-final { scan-assembler "vshl.s8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c
index 210fa905d3d..3ab782fa734 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int16x8_t b)
{
return vshlq_u16 (a, b);
}
-/* { dg-final { scan-assembler "vshl.u16" } } */
+/*
+**foo1:
+** ...
+** vshl.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, int16x8_t b)
{
return vshlq (a, b);
}
-/* { dg-final { scan-assembler "vshl.u16" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c
index 8fc59620016..f104235caee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32x4_t b)
{
return vshlq_u32 (a, b);
}
-/* { dg-final { scan-assembler "vshl.u32" } } */
+/*
+**foo1:
+** ...
+** vshl.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, int32x4_t b)
{
return vshlq (a, b);
}
-/* { dg-final { scan-assembler "vshl.u32" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c
index 8332d501640..1a93abfefb1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int8x16_t b)
{
return vshlq_u8 (a, b);
}
-/* { dg-final { scan-assembler "vshl.u8" } } */
+/*
+**foo1:
+** ...
+** vshl.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, int8x16_t b)
{
return vshlq (a, b);
}
-/* { dg-final { scan-assembler "vshl.u8" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c
index 4bdbc848bb7..5ac725187e8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
- return vshlq_x_n_s16 (a, 1, p);
+ return vshlq_x_n_s16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int16x8_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+ return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c
index 7648d2e2c66..e5e3ab03f01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
- return vshlq_x_n_s32 (a, 1, p);
+ return vshlq_x_n_s32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int32x4_t
+foo1 (int32x4_t a, mve_pred16_t p)
+{
+ return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c
index 4b303e92e81..7618d83b85b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, mve_pred16_t p)
{
- return vshlq_x_n_s8 (a, 1, p);
+ return vshlq_x_n_s8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int8x16_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+ return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c
index a2b6ac2d4c0..b4f937ae8f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
- return vshlq_x_n_u16 (a, 1, p);
+ return vshlq_x_n_u16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo1 (uint16x8_t a, mve_pred16_t p)
+{
+ return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c
index 59aa9dbe182..e42270ba293 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, mve_pred16_t p)
{
- return vshlq_x_n_u32 (a, 1, p);
+ return vshlq_x_n_u32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint32x4_t
+foo1 (uint32x4_t a, mve_pred16_t p)
+{
+ return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c
index 64069bb1728..7e01f8b2ab5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, mve_pred16_t p)
{
- return vshlq_x_n_u8 (a, 1, p);
+ return vshlq_x_n_u8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint8x16_t
+foo1 (uint8x16_t a, mve_pred16_t p)
+{
+ return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c
index 61a643d64bd..a6eeff654e3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
- return vshlq_x_s16 (a, b, p);
+ return vshlq_x_s16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+int16x8_t
+foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c
index 71424456f7d..cc3c434708a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
- return vshlq_x_s32 (a, b, p);
+ return vshlq_x_s32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+int32x4_t
+foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c
index 0d4825a03ad..430a3ab43ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
- return vshlq_x_s8 (a, b, p);
+ return vshlq_x_s8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+int8x16_t
+foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c
index 7ce18722444..9f5d0903588 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, int16x8_t b, mve_pred16_t p)
{
- return vshlq_x_u16 (a, b, p);
+ return vshlq_x_u16 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c
index fe02cc694a2..32d729f6954 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, int32x4_t b, mve_pred16_t p)
{
- return vshlq_x_u32 (a, b, p);
+ return vshlq_x_u32 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+uint32x4_t
+foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c
index 9611b268ca5..45e72c9dffa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, int8x16_t b, mve_pred16_t p)
{
- return vshlq_x_u8 (a, b, p);
+ return vshlq_x_u8 (a, b, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshlt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
+** ...
+*/
+uint8x16_t
+foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c
index d069cb0db44..ab37f2605e0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
- return vshrnbq_m_n_s16 (a, b, 8, p);
+ return vshrnbq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
- return vshrnbq_m (a, b, 8, p);
+ return vshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c
index 50a450f5b52..9fd9f8a7804 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
- return vshrnbq_m_n_s32 (a, b, 16, p);
+ return vshrnbq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
- return vshrnbq_m (a, b, 16, p);
+ return vshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c
index e5762145e64..e9408eeb1bf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
- return vshrnbq_m_n_u16 (a, b, 8, p);
+ return vshrnbq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrnbt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
- return vshrnbq_m (a, b, 8, p);
+ return vshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c
index 88da8e6f341..69699fd15ab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
- return vshrnbq_m_n_u32 (a, b, 16, p);
+ return vshrnbq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrnbt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
- return vshrnbq_m (a, b, 16, p);
+ return vshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c
index 7fcd9e479dc..0320d690627 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
- return vshrnbq_n_s16 (a, b, 8);
+ return vshrnbq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshrnb.i16" } } */
+/*
+**foo1:
+** ...
+** vshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
- return vshrnbq (a, b, 8);
+ return vshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshrnb.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c
index 38d4fdfc05f..aa7b107f7f9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
- return vshrnbq_n_s32 (a, b, 16);
+ return vshrnbq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshrnb.i32" } } */
+/*
+**foo1:
+** ...
+** vshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
- return vshrnbq (a, b, 16);
+ return vshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshrnb.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c
index ff341a9f202..4f896469eb4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
- return vshrnbq_n_u16 (a, b, 8);
+ return vshrnbq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshrnb.i16" } } */
+/*
+**foo1:
+** ...
+** vshrnb.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
- return vshrnbq (a, b, 8);
+ return vshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshrnb.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c
index b891c036d36..d3d22978542 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
- return vshrnbq_n_u32 (a, b, 16);
+ return vshrnbq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshrnb.i32" } } */
+/*
+**foo1:
+** ...
+** vshrnb.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
- return vshrnbq (a, b, 16);
+ return vshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshrnb.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c
index 30535470961..77f39ac10c7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
- return vshrntq_m_n_s16 (a, b, 8, p);
+ return vshrntq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
{
- return vshrntq_m (a, b, 8, p);
+ return vshrntq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c
index 2d52f5b6bb1..462d5f446f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
- return vshrntq_m_n_s32 (a, b, 16, p);
+ return vshrntq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
{
- return vshrntq_m (a, b, 16, p);
+ return vshrntq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c
index ed774e0b31a..0328cc3ef93 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
- return vshrntq_m_n_u16 (a, b, 8, p);
+ return vshrntq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrntt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
{
- return vshrntq_m (a, b, 8, p);
+ return vshrntq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c
index e592e96a5f9..d4882dc2d6d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
- return vshrntq_m_n_u32 (a, b, 16, p);
+ return vshrntq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrntt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
{
- return vshrntq_m (a, b, 16, p);
+ return vshrntq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c
index ddd9d5c0507..c9016ac124f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
- return vshrntq_n_s16 (a, b, 8);
+ return vshrntq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshrnt.i16" } } */
+/*
+**foo1:
+** ...
+** vshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
- return vshrntq (a, b, 8);
+ return vshrntq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshrnt.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c
index e35dbf07fac..6150f28d872 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
- return vshrntq_n_s32 (a, b, 16);
+ return vshrntq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshrnt.i32" } } */
+/*
+**foo1:
+** ...
+** vshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
- return vshrntq (a, b, 16);
+ return vshrntq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshrnt.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c
index 58a6eea561a..75be307feaa 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
- return vshrntq_n_u16 (a, b, 8);
+ return vshrntq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshrnt.i16" } } */
+/*
+**foo1:
+** ...
+** vshrnt.i16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
- return vshrntq (a, b, 8);
+ return vshrntq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshrnt.i16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c
index ec0c10007ff..9b9e534e3d2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
- return vshrntq_n_u32 (a, b, 16);
+ return vshrntq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vshrnt.i32" } } */
+/*
+**foo1:
+** ...
+** vshrnt.i32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
- return vshrntq (a, b, 16);
+ return vshrntq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshrnt.i32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c
index 00f236c6d74..ed1833b8673 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
- return vshrq_m_n_s16 (inactive, a, 16, p);
+ return vshrq_m_n_s16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
- return vshrq_m (inactive, a, 16, p);
+ return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c
index 1d1be501e16..880cd9e3545 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
- return vshrq_m_n_s32 (inactive, a, 32, p);
+ return vshrq_m_n_s32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
- return vshrq_m (inactive, a, 32, p);
+ return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c
index 7410ba9c8e9..53fc84857b7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
- return vshrq_m_n_s8 (inactive, a, 8, p);
+ return vshrq_m_n_s8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
{
- return vshrq_m (inactive, a, 8, p);
+ return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c
index 4b0dd59eefa..c3e311454b6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
- return vshrq_m_n_u16 (inactive, a, 16, p);
+ return vshrq_m_n_u16 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
- return vshrq_m (inactive, a, 16, p);
+ return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c
index 47ccc1b7499..6c0471f0120 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
- return vshrq_m_n_u32 (inactive, a, 32, p);
+ return vshrq_m_n_u32 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
- return vshrq_m (inactive, a, 32, p);
+ return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c
index 44f96027a04..5621608a2eb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
- return vshrq_m_n_u8 (inactive, a, 8, p);
+ return vshrq_m_n_u8 (inactive, a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
{
- return vshrq_m (inactive, a, 8, p);
+ return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c
index 051fa4a14a1..59a589b21a1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshr.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a)
{
- return vshrq_n_s16 (a, 16);
+ return vshrq_n_s16 (a, 1);
}
-/* { dg-final { scan-assembler "vshr.s16" } } */
+/*
+**foo1:
+** ...
+** vshr.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a)
{
- return vshrq (a, 16);
+ return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshr.s16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c
index 65a0b2e6224..1666b6657f2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshr.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a)
{
- return vshrq_n_s32 (a, 32);
+ return vshrq_n_s32 (a, 1);
}
-/* { dg-final { scan-assembler "vshr.s32" } } */
+/*
+**foo1:
+** ...
+** vshr.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a)
{
- return vshrq (a, 32);
+ return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshr.s32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c
index c5adcc1a465..1ce29185bcf 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshr.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a)
{
- return vshrq_n_s8 (a, 8);
+ return vshrq_n_s8 (a, 1);
}
-/* { dg-final { scan-assembler "vshr.s8" } } */
+/*
+**foo1:
+** ...
+** vshr.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a)
{
- return vshrq (a, 8);
+ return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshr.s8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c
index 1b68fafea8a..c2dbe6e5041 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshr.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a)
{
- return vshrq_n_u16 (a, 16);
+ return vshrq_n_u16 (a, 1);
}
-/* { dg-final { scan-assembler "vshr.u16" } } */
+/*
+**foo1:
+** ...
+** vshr.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a)
{
- return vshrq (a, 16);
+ return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshr.u16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c
index 8b798b793c0..15d231c217f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshr.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a)
{
- return vshrq_n_u32 (a, 32);
+ return vshrq_n_u32 (a, 1);
}
-/* { dg-final { scan-assembler "vshr.u32" } } */
+/*
+**foo1:
+** ...
+** vshr.u32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a)
{
- return vshrq (a, 32);
+ return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshr.u32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c
index 14cdf5917e2..19924e0fcdb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vshr.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a)
{
- return vshrq_n_u8 (a, 8);
+ return vshrq_n_u8 (a, 1);
}
-/* { dg-final { scan-assembler "vshr.u8" } } */
+/*
+**foo1:
+** ...
+** vshr.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a)
{
- return vshrq (a, 8);
+ return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vshr.u8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c
index 4652693d75c..fc26fd8fd3b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
- return vshrq_x_n_s16 (a, 16, p);
+ return vshrq_x_n_s16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int16x8_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+ return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c
index 43fa28a1f8d..bc9ae54faad 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
- return vshrq_x_n_s32 (a, 32, p);
+ return vshrq_x_n_s32 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int32x4_t
+foo1 (int32x4_t a, mve_pred16_t p)
+{
+ return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c
index 042bf488284..391ced24079 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, mve_pred16_t p)
{
- return vshrq_x_n_s8 (a, 8, p);
+ return vshrq_x_n_s8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.s8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+int8x16_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+ return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c
index d627565fe84..eddb977fa83 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
- return vshrq_x_n_u16 (a, 16, p);
+ return vshrq_x_n_u16 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint16x8_t
+foo1 (uint16x8_t a, mve_pred16_t p)
+{
+ return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c
index 0f26e7b9efc..6867668d1ce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c
@@ -1,15 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, mve_pred16_t p)
{
- return vshrq_x_n_u8 (a, 8, p);
+ return vshrq_x_n_u8 (a, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vshrt.u8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
+uint8x16_t
+foo1 (uint8x16_t a, mve_pred16_t p)
+{
+ return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c
index 49d342e7c17..23b346b1cab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
- return vsliq_m_n_s16 (a, b, 15, p);
+ return vsliq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
- return vsliq_m (a, b, 15, p);
+ return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c
index f0f7619dd0a..d640e1f8df4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
- return vsliq_m_n_s32 (a, b, 31, p);
+ return vsliq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
- return vsliq_m (a, b, 31, p);
+ return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c
index 12d295e70f6..14b1afa1d01 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
- return vsliq_m_n_s8 (a, b, 7, p);
+ return vsliq_m_n_s8 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
- return vsliq_m (a, b, 7, p);
+ return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c
index 78cdbdf3950..521abbf4694 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
- return vsliq_m_n_u16 (a, b, 15, p);
+ return vsliq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
- return vsliq_m (a, b, 15, p);
+ return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c
index 62e9cfd9f31..951204a31a0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
- return vsliq_m_n_u32 (a, b, 31, p);
+ return vsliq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
- return vsliq_m (a, b, 31, p);
+ return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c
index f86fea32a90..8b893a8c4d2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c
@@ -1,23 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
- return vsliq_m_n_u8 (a, b, 7, p);
+ return vsliq_m_n_u8 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vslit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
- return vsliq_m (a, b, 7, p);
+ return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c
index 2c5f82bb317..a6c86764eab 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsli.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
- return vsliq_n_s16 (a, b, 15);
+ return vsliq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsli.16" } } */
+/*
+**foo1:
+** ...
+** vsli.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
- return vsliq (a, b, 15);
+ return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsli.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c
index 0738fd61203..301cdd463b5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsli.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
- return vsliq_n_s32 (a, b, 31);
+ return vsliq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsli.32" } } */
+/*
+**foo1:
+** ...
+** vsli.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
- return vsliq (a, b, 31);
+ return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsli.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c
index 25f2f761c3c..2a26f7f444b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsli.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
- return vsliq_n_s8 (a, b, 7);
+ return vsliq_n_s8 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsli.8" } } */
+/*
+**foo1:
+** ...
+** vsli.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
- return vsliq (a, b, 7);
+ return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsli.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c
index 25bbcd8f3fa..b71572a232e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsli.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b)
{
- return vsliq_n_u16 (a, b, 15);
+ return vsliq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsli.16" } } */
+/*
+**foo1:
+** ...
+** vsli.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b)
{
- return vsliq (a, b, 15);
+ return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsli.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c
index 970e069cabf..ecafb61b487 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsli.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b)
{
- return vsliq_n_u32 (a, b, 31);
+ return vsliq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsli.32" } } */
+/*
+**foo1:
+** ...
+** vsli.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b)
{
- return vsliq (a, b, 31);
+ return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsli.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c
index c24e354a957..e20ec7e030e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsli.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b)
{
- return vsliq_n_u8 (a, b, 7);
+ return vsliq_n_u8 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsli.8" } } */
+/*
+**foo1:
+** ...
+** vsli.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b)
{
- return vsliq (a, b, 7);
+ return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsli.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c
index 799232a8dc1..086f5f86fc1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
- return vsriq_m_n_s16 (a, b, 4, p);
+ return vsriq_m_n_s16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
{
- return vsriq_m (a, b, 4, p);
+ return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c
index 7e019782c88..90267f67e54 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
- return vsriq_m_n_s32 (a, b, 2, p);
+ return vsriq_m_n_s32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
{
- return vsriq_m (a, b, 2, p);
+ return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c
index 8fa3e757f6d..6c7552905b4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
- return vsriq_m_n_s8 (a, b, 4, p);
+ return vsriq_m_n_s8 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
{
- return vsriq_m (a, b, 4, p);
+ return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c
index 5e2c4a3deb3..624732b0c91 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
- return vsriq_m_n_u16 (a, b, 4, p);
+ return vsriq_m_n_u16 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
- return vsriq_m (a, b, 4, p);
+ return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c
index 368115e27b2..48abe8b9c0d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
- return vsriq_m_n_u32 (a, b, 4, p);
+ return vsriq_m_n_u32 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
- return vsriq_m (a, b, 4, p);
+ return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c
index 54db7d78836..b1f9ecd0c9f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c
@@ -1,22 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
- return vsriq_m_n_u8 (a, b, 4, p);
+ return vsriq_m_n_u8 (a, b, 1, p);
}
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vsrit.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
- return vsriq_m (a, b, 4, p);
+ return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c
index 75f57ae76a7..2f8bde64ff5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsri.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo (int16x8_t a, int16x8_t b)
{
- return vsriq_n_s16 (a, b, 4);
+ return vsriq_n_s16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsri.16" } } */
+/*
+**foo1:
+** ...
+** vsri.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int16x8_t
foo1 (int16x8_t a, int16x8_t b)
{
- return vsriq (a, b, 4);
+ return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsri.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c
index 46d9ead1e9a..a95e6dae8f7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsri.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo (int32x4_t a, int32x4_t b)
{
- return vsriq_n_s32 (a, b, 4);
+ return vsriq_n_s32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsri.32" } } */
+/*
+**foo1:
+** ...
+** vsri.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int32x4_t
foo1 (int32x4_t a, int32x4_t b)
{
- return vsriq (a, b, 4);
+ return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsri.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c
index 3dcc5a34f90..7726a7ed934 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsri.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo (int8x16_t a, int8x16_t b)
{
- return vsriq_n_s8 (a, b, 4);
+ return vsriq_n_s8 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsri.8" } } */
+/*
+**foo1:
+** ...
+** vsri.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
int8x16_t
foo1 (int8x16_t a, int8x16_t b)
{
- return vsriq (a, b, 4);
+ return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsri.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c
index ff6c4f0c277..4d8d5930b49 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsri.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo (uint16x8_t a, uint16x8_t b)
{
- return vsriq_n_u16 (a, b, 4);
+ return vsriq_n_u16 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsri.16" } } */
+/*
+**foo1:
+** ...
+** vsri.16 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint16x8_t
foo1 (uint16x8_t a, uint16x8_t b)
{
- return vsriq (a, b, 4);
+ return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsri.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c
index f6b79b26235..83a6b13ef40 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsri.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo (uint32x4_t a, uint32x4_t b)
{
- return vsriq_n_u32 (a, b, 4);
+ return vsriq_n_u32 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsri.32" } } */
+/*
+**foo1:
+** ...
+** vsri.32 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint32x4_t
foo1 (uint32x4_t a, uint32x4_t b)
{
- return vsriq (a, b, 4);
+ return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsri.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c
index 4c56b3ab00d..0bd9ac5ddfd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vsri.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo (uint8x16_t a, uint8x16_t b)
{
- return vsriq_n_u8 (a, b, 4);
+ return vsriq_n_u8 (a, b, 1);
}
-/* { dg-final { scan-assembler "vsri.8" } } */
+/*
+**foo1:
+** ...
+** vsri.8 q[0-9]+, q[0-9]+, #[0-9]+(?: @.*|)
+** ...
+*/
uint8x16_t
foo1 (uint8x16_t a, uint8x16_t b)
{
- return vsriq (a, b, 4);
+ return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vsri.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c
index 312b7464f17..1fa02f00f53 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c
@@ -1,25 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
-void
-foo (float16_t * addr, float16x8_t value)
-{
- vst1q_f16 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+**foo:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (float16_t * addr, float16x8_t value)
+foo (float16_t *base, float16x8_t value)
{
- vst1q (addr, value);
+ return vst1q_f16 (base, value);
}
-/* { dg-final { scan-assembler-times "vstrh.16" 2 } } */
+/*
+**foo1:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo2 (float16_t a, float16x8_t x)
+foo1 (float16_t *base, float16x8_t value)
{
- vst1q (&a, x);
+ return vst1q (base, value);
}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c
index a6ae1cef2d4..67cc3ae3b47 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (float32_t * addr, float32x4_t value)
+foo (float32_t *base, float32x4_t value)
{
- vst1q_f32 (addr, value);
+ return vst1q_f32 (base, value);
}
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/*
+**foo1:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (float32_t * addr, float32x4_t value)
+foo1 (float32_t *base, float32x4_t value)
{
- vst1q (addr, value);
+ return vst1q (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c
index f6db22d481a..06b2bd3910d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (float16_t * addr, float16x8_t value, mve_pred16_t p)
+foo (float16_t *base, float16x8_t value, mve_pred16_t p)
{
- vst1q_p_f16 (addr, value, p);
+ return vst1q_p_f16 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (float16_t * addr, float16x8_t value, mve_pred16_t p)
+foo1 (float16_t *base, float16x8_t value, mve_pred16_t p)
{
- vst1q_p (addr, value, p);
+ return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c
index 17e7f9c5dfd..e492a705ea0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (float32_t * addr, float32x4_t value, mve_pred16_t p)
+foo (float32_t *base, float32x4_t value, mve_pred16_t p)
{
- vst1q_p_f32 (addr, value, p);
+ return vst1q_p_f32 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p)
+foo1 (float32_t *base, float32x4_t value, mve_pred16_t p)
{
- vst1q_p (addr, value, p);
+ return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c
index b142fc3b021..7b76d1d7687 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int16_t * addr, int16x8_t value, mve_pred16_t p)
+foo (int16_t *base, int16x8_t value, mve_pred16_t p)
{
- vst1q_p_s16 (addr, value, p);
+ return vst1q_p_s16 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int16_t * addr, int16x8_t value, mve_pred16_t p)
+foo1 (int16_t *base, int16x8_t value, mve_pred16_t p)
{
- vst1q_p (addr, value, p);
+ return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c
index 6334462e230..4ad32a68a96 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int32_t * addr, int32x4_t value, mve_pred16_t p)
+foo (int32_t *base, int32x4_t value, mve_pred16_t p)
{
- vst1q_p_s32 (addr, value, p);
+ return vst1q_p_s32 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p)
+foo1 (int32_t *base, int32x4_t value, mve_pred16_t p)
{
- vst1q_p (addr, value, p);
+ return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c
index 1f3f0343820..2425b9cec00 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int8_t * addr, int8x16_t value, mve_pred16_t p)
+foo (int8_t *base, int8x16_t value, mve_pred16_t p)
{
- vst1q_p_s8 (addr, value, p);
+ return vst1q_p_s8 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrbt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int8_t * addr, int8x16_t value, mve_pred16_t p)
+foo1 (int8_t *base, int8x16_t value, mve_pred16_t p)
{
- vst1q_p (addr, value, p);
+ return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrbt.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c
index 331cd34cdce..c0065ef6ff5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint16_t * addr, uint16x8_t value, mve_pred16_t p)
+foo (uint16_t *base, uint16x8_t value, mve_pred16_t p)
{
- vst1q_p_u16 (addr, value, p);
+ return vst1q_p_u16 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint16_t * addr, uint16x8_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint16x8_t value, mve_pred16_t p)
{
- vst1q_p (addr, value, p);
+ return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrht.16" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c
index 27836c32451..c41c4184b9b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
+foo (uint32_t *base, uint32x4_t value, mve_pred16_t p)
{
- vst1q_p_u32 (addr, value, p);
+ return vst1q_p_u32 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
+foo1 (uint32_t *base, uint32x4_t value, mve_pred16_t p)
{
- vst1q_p (addr, value, p);
+ return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrwt.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c
index bfbc542dc35..1cd3a781357 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint8_t * addr, uint8x16_t value, mve_pred16_t p)
+foo (uint8_t *base, uint8x16_t value, mve_pred16_t p)
{
- vst1q_p_u8 (addr, value, p);
+ return vst1q_p_u8 (base, value, p);
}
-/* { dg-final { scan-assembler "vstrbt.8" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint8_t * addr, uint8x16_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint8x16_t value, mve_pred16_t p)
{
- vst1q_p (addr, value, p);
+ return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrbt.8" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c
index cd14e2c408f..052959b2083 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c
@@ -1,25 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
-void
-foo (int16_t * addr, int16x8_t value)
-{
- vst1q_s16 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+**foo:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int16_t * addr, int16x8_t value)
+foo (int16_t *base, int16x8_t value)
{
- vst1q (addr, value);
+ return vst1q_s16 (base, value);
}
-/* { dg-final { scan-assembler-times "vstrh.16" 2 } } */
+/*
+**foo1:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo2 (int16_t a, int16x8_t x)
+foo1 (int16_t *base, int16x8_t value)
{
- vst1q (&a, x);
+ return vst1q (base, value);
}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c
index e07e8a30f9d..444ad07f4ef 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (int32_t * addr, int32x4_t value)
+foo (int32_t *base, int32x4_t value)
{
- vst1q_s32 (addr, value);
+ return vst1q_s32 (base, value);
}
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/*
+**foo1:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int32_t * addr, int32x4_t value)
+foo1 (int32_t *base, int32x4_t value)
{
- vst1q (addr, value);
+ return vst1q (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c
index 0004c80963e..684ff0aca5b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c
@@ -1,25 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
-void
-foo (int8_t * addr, int8x16_t value)
-{
- vst1q_s8 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+**foo:
+** ...
+** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (int8_t * addr, int8x16_t value)
+foo (int8_t *base, int8x16_t value)
{
- vst1q (addr, value);
+ return vst1q_s8 (base, value);
}
-/* { dg-final { scan-assembler-times "vstrb.8" 2 } } */
+/*
+**foo1:
+** ...
+** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo2 (int8_t a, int8x16_t x)
+foo1 (int8_t *base, int8x16_t value)
{
- vst1q (&a, x);
+ return vst1q (base, value);
}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c
index 248e7ce82b0..1fea2de1e76 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c
@@ -1,25 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
-void
-foo (uint16_t * addr, uint16x8_t value)
-{
- vst1q_u16 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+**foo:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint16_t * addr, uint16x8_t value)
+foo (uint16_t *base, uint16x8_t value)
{
- vst1q (addr, value);
+ return vst1q_u16 (base, value);
}
-/* { dg-final { scan-assembler-times "vstrh.16" 2 } } */
+/*
+**foo1:
+** ...
+** vstrh.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo2 (uint16_t a, uint16x8_t x)
+foo1 (uint16_t *base, uint16x8_t value)
{
- vst1q (&a, x);
+ return vst1q (base, value);
}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c
index d1fdf8897b5..64c43c59d47 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo (uint32_t * addr, uint32x4_t value)
+foo (uint32_t *base, uint32x4_t value)
{
- vst1q_u32 (addr, value);
+ return vst1q_u32 (base, value);
}
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/*
+**foo1:
+** ...
+** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint32_t * addr, uint32x4_t value)
+foo1 (uint32_t *base, uint32x4_t value)
{
- vst1q (addr, value);
+ return vst1q (base, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrw.32" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c
index f8b48a69903..5517611bba6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c
@@ -1,25 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
-void
-foo (uint8_t * addr, uint8x16_t value)
-{
- vst1q_u8 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+**foo:
+** ...
+** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo1 (uint8_t * addr, uint8x16_t value)
+foo (uint8_t *base, uint8x16_t value)
{
- vst1q (addr, value);
+ return vst1q_u8 (base, value);
}
-/* { dg-final { scan-assembler-times "vstrb.8" 2 } } */
+/*
+**foo1:
+** ...
+** vstrb.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
+** ...
+*/
void
-foo2 (uint8_t a, uint8x16_t x)
+foo1 (uint8_t *base, uint8x16_t value)
{
- vst1q (&a, x);
+ return vst1q (base, value);
}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c
index c694e2b6ad3..25a889dd1f0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint64x2_t addr, const int offset, int64x2_t value, mve_pred16_t p)
+foo (uint64x2_t addr, int64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_base_p_s64 (addr, 8, value, p);
+ return vstrdq_scatter_base_p_s64 (addr, 0, value, p);
}
-/* { dg-final { scan-assembler "vstrdt.u64" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint64x2_t addr, const int offset, int64x2_t value, mve_pred16_t p)
+foo1 (uint64x2_t addr, int64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_base_p (addr, 8, value, p);
+ return vstrdq_scatter_base_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrdt.u64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c
index 6e8507c81d9..f0731f69a09 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint64x2_t addr, const int offset, uint64x2_t value, mve_pred16_t p)
+foo (uint64x2_t addr, uint64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_base_p_u64 (addr, 8, value, p);
+ return vstrdq_scatter_base_p_u64 (addr, 0, value, p);
}
-/* { dg-final { scan-assembler "vstrdt.u64" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint64x2_t addr, const int offset, uint64x2_t value, mve_pred16_t p)
+foo1 (uint64x2_t addr, uint64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_base_p (addr, 8, value, p);
+ return vstrdq_scatter_base_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrdt.u64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c
index b9aac8036d4..31cdec9ba0a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint64x2_t addr, const int offset, int64x2_t value)
+foo (uint64x2_t addr, int64x2_t value)
{
- vstrdq_scatter_base_s64 (addr, 1016, value);
+ return vstrdq_scatter_base_s64 (addr, 0, value);
}
-/* { dg-final { scan-assembler "vstrd.u64" } } */
+/*
+**foo1:
+** ...
+** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint64x2_t addr, const int offset, int64x2_t value)
+foo1 (uint64x2_t addr, int64x2_t value)
{
- vstrdq_scatter_base (addr, 1016, value);
+ return vstrdq_scatter_base (addr, 0, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrd.u64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c
index 888d4e0c031..8f0195c9e8f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint64x2_t addr, const int offset, uint64x2_t value)
+foo (uint64x2_t addr, uint64x2_t value)
{
- vstrdq_scatter_base_u64 (addr, 8, value);
+ return vstrdq_scatter_base_u64 (addr, 0, value);
}
-/* { dg-final { scan-assembler "vstrd.u64" } } */
+/*
+**foo1:
+** ...
+** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint64x2_t addr, const int offset, uint64x2_t value)
+foo1 (uint64x2_t addr, uint64x2_t value)
{
- vstrdq_scatter_base (addr, 8, value);
+ return vstrdq_scatter_base (addr, 0, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrd.u64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c
index 319188b706f..8f19ede4e1a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c
@@ -1,19 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo (uint64x2_t * addr, const int offset, int64x2_t value, mve_pred16_t p)
+foo (uint64x2_t *addr, int64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_base_wb_p_s64 (addr, 8, value, p);
+ return vstrdq_scatter_base_wb_p_s64 (addr, 0, value, p);
}
+
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo1 (uint64x2_t * addr, const int offset, int64x2_t value, mve_pred16_t p)
+foo1 (uint64x2_t *addr, int64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_base_wb_p (addr, 8, value, p);
+ return vstrdq_scatter_base_wb_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler-times "vstrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c
index 940b5421c84..41958c961f4 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c
@@ -1,19 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo (uint64x2_t * addr, const int offset, uint64x2_t value, mve_pred16_t p)
+foo (uint64x2_t *addr, uint64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_base_wb_p_u64 (addr, 8, value, p);
+ return vstrdq_scatter_base_wb_p_u64 (addr, 0, value, p);
}
+
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo1 (uint64x2_t * addr, const int offset, uint64x2_t value, mve_pred16_t p)
+foo1 (uint64x2_t *addr, uint64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_base_wb_p (addr, 8, value, p);
+ return vstrdq_scatter_base_wb_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler-times "vstrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c
index 33926d5c9e2..fc06db1c202 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c
@@ -1,19 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo (uint64x2_t * addr, const int offset, int64x2_t value)
+foo (uint64x2_t *addr, int64x2_t value)
{
- vstrdq_scatter_base_wb_s64 (addr, 8, value);
+ return vstrdq_scatter_base_wb_s64 (addr, 0, value);
}
+
+/*
+**foo1:
+** ...
+** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo1 (uint64x2_t * addr, const int offset, int64x2_t value)
+foo1 (uint64x2_t *addr, int64x2_t value)
{
- vstrdq_scatter_base_wb (addr, 8, value);
+ return vstrdq_scatter_base_wb (addr, 0, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler-times "vstrd.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c
index b7ffcf9b5dd..c6529e617e3 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c
@@ -1,19 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo (uint64x2_t * addr, const int offset, uint64x2_t value)
+foo (uint64x2_t *addr, uint64x2_t value)
{
- vstrdq_scatter_base_wb_u64 (addr, 8, value);
+ return vstrdq_scatter_base_wb_u64 (addr, 0, value);
}
+
+/*
+**foo1:
+** ...
+** vstrd.u64 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
+** ...
+*/
void
-foo1 (uint64x2_t * addr, const int offset, uint64x2_t value)
+foo1 (uint64x2_t *addr, uint64x2_t value)
{
- vstrdq_scatter_base_wb (addr, 8, value);
+ return vstrdq_scatter_base_wb (addr, 0, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler-times "vstrd.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c
index 7ebf858f816..754fb59df4c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
+foo (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_offset_p_s64 (base, offset, value, p);
+ return vstrdq_scatter_offset_p_s64 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrdt.64" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
+foo1 (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_offset_p (base, offset, value, p);
+ return vstrdq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrdt.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c
index 4829bada1a9..046f29a6621 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
+foo (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_offset_p_u64 (base, offset, value, p);
+ return vstrdq_scatter_offset_p_u64 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrdt.64" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
+foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_offset_p (base, offset, value, p);
+ return vstrdq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrdt.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c
index fb7317bc4d7..73e25cdf0ed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (int64_t * base, uint64x2_t offset, int64x2_t value)
+foo (int64_t *base, uint64x2_t offset, int64x2_t value)
{
- vstrdq_scatter_offset_s64 (base, offset, value);
+ return vstrdq_scatter_offset_s64 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrd.64" } } */
+/*
+**foo1:
+** ...
+** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value)
+foo1 (int64_t *base, uint64x2_t offset, int64x2_t value)
{
- vstrdq_scatter_offset (base, offset, value);
+ return vstrdq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrd.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c
index e8b3a0210b4..d49adde0b94 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value)
+foo (uint64_t *base, uint64x2_t offset, uint64x2_t value)
{
- vstrdq_scatter_offset_u64 (base, offset, value);
+ return vstrdq_scatter_offset_u64 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrd.64" } } */
+/*
+**foo1:
+** ...
+** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
+** ...
+*/
void
-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value)
+foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value)
{
- vstrdq_scatter_offset (base, offset, value);
+ return vstrdq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrd.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c
index 9ca83e0f3fd..8acfba1f55e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
void
-foo (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
+foo (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_shifted_offset_p_s64 (base, offset, value, p);
+ return vstrdq_scatter_shifted_offset_p_s64 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrdt.64" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
void
-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
+foo1 (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_shifted_offset_p (base, offset, value, p);
+ return vstrdq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrdt.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c
index 1c33df18e84..630c627d604 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c
@@ -1,21 +1,49 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
void
-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
+foo (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_shifted_offset_p_u64 (base, offset, value, p);
+ return vstrdq_scatter_shifted_offset_p_u64 (base, offset, value, p);
}
-/* { dg-final { scan-assembler "vstrdt.64" } } */
+/*
+**foo1:
+** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
+** vpst(?: @.*|)
+** ...
+** vstrdt.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
void
-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
+foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
{
- vstrdq_scatter_shifted_offset_p (base, offset, value, p);
+ return vstrdq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrdt.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c
index 8af348ddbe2..ec73bca4869 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
void
-foo (int64_t * base, uint64x2_t offset, int64x2_t value)
+foo (int64_t *base, uint64x2_t offset, int64x2_t value)
{
- vstrdq_scatter_shifted_offset_s64 (base, offset, value);
+ return vstrdq_scatter_shifted_offset_s64 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrd.64" } } */
+/*
+**foo1:
+** ...
+** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
void
-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value)
+foo1 (int64_t *base, uint64x2_t offset, int64x2_t value)
{
- vstrdq_scatter_shifted_offset (base, offset, value);
+ return vstrdq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrd.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c
index bc153a07192..9bdf8003961 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c
@@ -1,21 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+** ...
+** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
void
-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value)
+foo (uint64_t *base, uint64x2_t offset, uint64x2_t value)
{
- vstrdq_scatter_shifted_offset_u64 (base, offset, value);
+ return vstrdq_scatter_shifted_offset_u64 (base, offset, value);
}
-/* { dg-final { scan-assembler "vstrd.64" } } */
+/*
+**foo1:
+** ...
+** vstrd.64 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?: @.*|)
+** ...
+*/
void
-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value)
+foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value)
{
- vstrdq_scatter_shifted_offset (base, offset, value);
+ return vstrdq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
}
+#endif
-/* { dg-final { scan-assembler "vstrd.64" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--
2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests
2023-04-28 16:54 ` Kyrylo Tkachov
@ 2023-05-02 12:17 ` Stamatis Markianos-Wright
0 siblings, 0 replies; 31+ messages in thread
From: Stamatis Markianos-Wright @ 2023-05-02 12:17 UTC (permalink / raw)
To: Kyrylo Tkachov, Andrea Corallo, gcc-patches; +Cc: Richard Earnshaw
On 28/04/2023 17:54, Kyrylo Tkachov wrote:
>
>> -----Original Message-----
>> From: Andrea Corallo <andrea.corallo@arm.com>
>> Sent: Friday, April 28, 2023 12:30 PM
>> To: gcc-patches@gcc.gnu.org
>> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
>> <Richard.Earnshaw@arm.com>; Stam Markianos-Wright <Stam.Markianos-
>> Wright@arm.com>
>> Subject: [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests
>>
>> From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
>>
>> Hi all,
>>
>> This is a simple testsuite tidy-up patch, addressing to types of errors:
>>
>> * The vcmp vector-scalar tests failing due to the compiler's preference
>> of vector-vector comparisons, over vector-scalar comparisons. This is
>> due to the lack of cost model for MVE and the compiler not knowing that
>> the RTL vec_duplicate is free in those instructions. For now, we simply
>> XFAIL these checks.
> I'd like to see this deficiency tracked in Bugzilla before we mark these as XFAIL.
Yep! Raised https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109697
(And I'll also update this commit message to reference that PR now)
>
>> * The tests for pr108177 had strict usage of q0 and r0 registers,
>> meaning that they would FAIL with -mfloat-abi=softf. The register checks
>> have now been relaxed.
> This part is ok.
> Thanks,
> Kyrill
>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/arm/mve/intrinsics/srshr.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/srshrl.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/uqshl.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/uqshll.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/urshr.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/urshrl.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vadciq_s32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vadciq_u32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vadcq_s32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vadcq_u32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: XFAIL check.
>> * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: XFAIL check.
>> * gcc.target/arm/mve/pr108177-1.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-10.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-11.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-12.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-13.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-14.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-2.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-3.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-4.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-5.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-6.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-7.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-8.c: Relax registers.
>> * gcc.target/arm/mve/pr108177-9.c: Relax registers.
>> ---
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/pr108177-1.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-10.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-11.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-12.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-13.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-14.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-2.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-3.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-4.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-5.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-6.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-7.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-8.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/pr108177-9.c | 4 ++--
>> 38 files changed, 52 insertions(+), 52 deletions(-)
>>
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
>> index dc63c527743..9f8111438a1 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
>> @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
>> index 8c5d185ca22..799d3bcdab1 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
>> @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
>> index 2296f3e1655..16c3617c104 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
>> @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
>> index 1d870428c55..2f84d751c53 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
>> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
>> index 8b8610b0617..6cfe7338fce 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
>> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
>> index 409c9de58ba..362e830c908 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
>> @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
>> index c3b1736bfa1..583beb97849 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
>> @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
>> index 3728c738b54..db7f1877d73 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
>> @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
>> index 4e9a346ab14..978bd7d4b52 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
>> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
>> index 2cf1d1ab0b6..66b6d8b0056 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
>> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
>> index 89d8e2b9109..9c5f1f2f5c8 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
>> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
>> index 482ac094cf3..2723aa7f98f 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
>> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
>> index 085b8277736..5712db2ceef 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
>> @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
>> index a62a73ff24c..f7a25af8574 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
>> @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
>> index f05c9d24643..8cd28fb1681 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
>> @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
>> index 4f6276484ba..1d1f4bf0e58 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
>> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
>> index e71dcb8f174..bf77a808064 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
>> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
>> index c6fdb08d8ae..f9f091cd9b3 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
>> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
>> index 4f1ac3c0977..d22ea1aca30 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
>> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
>> index e36d8a95a85..83beca964d6 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
>> @@ -39,7 +39,7 @@ foo1 (float16x8_t a, float16_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
>> index 7262503eee6..abe1abfed2a 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
>> @@ -39,7 +39,7 @@ foo1 (float32x4_t a, float32_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
>> index 71d878dff9f..ca55fe2f76c 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
>> @@ -39,7 +39,7 @@ foo1 (uint16x8_t a, uint16_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
>> index 3f997e8e487..77bac757d68 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
>> @@ -39,7 +39,7 @@ foo1 (uint32x4_t a, uint32_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
>> index 9917a95ffb7..352afa798d1 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
>> @@ -39,7 +39,7 @@ foo1 (uint8x16_t a, uint8_t b)
>> }
>>
>> /*
>> -**foo2:
>> +**foo2: { xfail *-*-* }
>> ** ...
>> ** vcmp.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|)
>> ** ...
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
>> index 2d42062bc8e..8383b4d9e3a 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrbt.8 q0, \[r0\]
>> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrbt.8 q0, \[r0\]
>> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>>
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
>> index 4db594f588f..7b1cd3711d8 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrht.32 q0, \[r0\]
>> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrht.32 q0, \[r0\]
>> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>>
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
>> index 329fcb33eeb..e6ae8524052 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrwt.32 q0, \[r0\]
>> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrwt.32 q0, \[r0\]
>> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>>
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
>> index 3f7c5b2a4c1..e352508e07e 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrwt.32 q0, \[r0\]
>> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrwt.32 q0, \[r0\]
>> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>>
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
>> index 2f82228d8f6..13afa92771d 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrht.16 q0, \[r0\]
>> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrht.16 q0, \[r0\]
>> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>>
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
>> index ba6196b7994..a093cd4b708 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrwt.32 q0, \[r0\]
>> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrwt.32 q0, \[r0\]
>> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>>
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
>> index 52c8d87ccc8..da4181ff0b7 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrbt.8 q0, \[r0\]
>> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrbt.8 q0, \[r0\]
>> +** vstrbt.8 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>>
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
>> index ac89e7ea883..9604fd100e6 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrbt.16 q0, \[r0\]
>> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrbt.16 q0, \[r0\]
>> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>>
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
>> index dc4f7ddab07..07ba37b466c 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrbt.16 q0, \[r0\]
>> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrbt.16 q0, \[r0\]
>> +** vstrbt.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>>
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
>> index d1dfd328d66..72c1dd5a4d6 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrbt.32 q0, \[r0\]
>> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrbt.32 q0, \[r0\]
>> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>>
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
>> index fa70dde9eeb..3fedc9b98c8 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrbt.32 q0, \[r0\]
>> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrbt.32 q0, \[r0\]
>> +** vstrbt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>>
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
>> index 73cd8605171..c3b440c3b6c 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrht.16 q0, \[r0\]
>> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrht.16 q0, \[r0\]
>> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>>
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
>> index 187c2b3f4ce..5c450b81d1c 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrht.16 q0, \[r0\]
>> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrht.16 q0, \[r0\]
>> +** vstrht.16 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>>
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
>> b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
>> index caecd18a881..b5084efcc00 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
>> @@ -7,9 +7,9 @@
>> /*
>> ** test:
>> **...
>> -** vstrht.32 q0, \[r0\]
>> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> -** vstrht.32 q0, \[r0\]
>> +** vstrht.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
>> **...
>> */
>>
>> --
>> 2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 04/10] arm: Stop vadcq, vsbcq intrinsics from overwriting the FPSCR NZ flags
2023-04-28 16:45 ` Kyrylo Tkachov
@ 2023-05-03 12:19 ` Stamatis Markianos-Wright
2023-05-03 12:55 ` Kyrylo Tkachov
0 siblings, 1 reply; 31+ messages in thread
From: Stamatis Markianos-Wright @ 2023-05-03 12:19 UTC (permalink / raw)
To: Kyrylo Tkachov, Andrea Corallo, gcc-patches; +Cc: Richard Earnshaw
[-- Attachment #1: Type: text/plain, Size: 8068 bytes --]
On 28/04/2023 17:45, Kyrylo Tkachov wrote:
> Hi Andrea, Stam,
>
>> -----Original Message-----
>> From: Andrea Corallo <andrea.corallo@arm.com>
>> Sent: Friday, April 28, 2023 12:30 PM
>> To: gcc-patches@gcc.gnu.org
>> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
>> <Richard.Earnshaw@arm.com>; Stam Markianos-Wright <Stam.Markianos-
>> Wright@arm.com>
>> Subject: [PATCH 04/10] arm: Stop vadcq, vsbcq intrinsics from overwriting the
>> FPSCR NZ flags
>>
>> From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
>>
>> Hi all,
>>
>> We noticed that calls to the vadcq and vsbcq intrinsics, both of
>> which use __builtin_arm_set_fpscr_nzcvqc to set the Carry flag in
>> the FPSCR, would produce the following code:
>>
>> ```
>> < r2 is the *carry input >
>> vmrs r3, FPSCR_nzcvqc
>> bic r3, r3, #536870912
>> orr r3, r3, r2, lsl #29
>> vmsr FPSCR_nzcvqc, r3
>> ```
>>
>> when the MVE ACLE instead gives a different instruction sequence of:
>> ```
>> < Rt is the *carry input >
>> VMRS Rs,FPSCR_nzcvqc
>> BFI Rs,Rt,#29,#1
>> VMSR FPSCR_nzcvqc,Rs
>> ```
>>
>> the bic + orr pair is slower and it's also wrong, because, if the
>> *carry input is greater than 1, then we risk overwriting the top two
>> bits of the FPSCR register (the N and Z flags).
>>
>> This turned out to be a problem in the header file and the solution was
>> to simply add a `& 1x0u` to the `*carry` input: then the compiler knows
>> that we only care about the lowest bit and can optimise to a BFI.
>>
>> Ok for trunk?
> Ok, but I think this needs testsuite coverage for the bug?
> Thanks,
> Kyrill
So this can be seen in the new vadcq* , vsbcq* tests:
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
The fact that there's a BFI there rather than the BIC + ORR shows
that this has now been optimised by the compiler and the bug isn't
present in those intrinsics any longer... Sorry, I should have linked
that in better in our patch series!
Added a runtest, also, as it was fairly trivial to write it out :)
Thanks,
Stam
>
>> Thanks,
>> Stam Markianos-Wright
>>
>> gcc/ChangeLog:
>>
>> * config/arm/arm_mve.h (__arm_vadcq_s32): Fix arithmetic.
>> (__arm_vadcq_u32): Likewise.
>> (__arm_vadcq_m_s32): Likewise.
>> (__arm_vadcq_m_u32): Likewise.
>> (__arm_vsbcq_s32): Likewise.
>> (__arm_vsbcq_u32): Likewise.
>> (__arm_vsbcq_m_s32): Likewise.
>> (__arm_vsbcq_m_u32): Likewise.
>> ---
>> gcc/config/arm/arm_mve.h | 16 ++++++++--------
>> 1 file changed, 8 insertions(+), 8 deletions(-)
>>
>> diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
>> index 1262d668121..8778216304b 100644
>> --- a/gcc/config/arm/arm_mve.h
>> +++ b/gcc/config/arm/arm_mve.h
>> @@ -16055,7 +16055,7 @@ __extension__ extern __inline int32x4_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> __arm_vadcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry)
>> {
>> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
>> ~0x20000000u) | (*__carry << 29));
>> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
>> ~0x20000000u) | ((*__carry & 0x1u) << 29));
>> int32x4_t __res = __builtin_mve_vadcq_sv4si (__a, __b);
>> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
>> return __res;
>> @@ -16065,7 +16065,7 @@ __extension__ extern __inline uint32x4_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> __arm_vadcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry)
>> {
>> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
>> ~0x20000000u) | (*__carry << 29));
>> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
>> ~0x20000000u) | ((*__carry & 0x1u) << 29));
>> uint32x4_t __res = __builtin_mve_vadcq_uv4si (__a, __b);
>> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
>> return __res;
>> @@ -16075,7 +16075,7 @@ __extension__ extern __inline int32x4_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> __arm_vadcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b,
>> unsigned * __carry, mve_pred16_t __p)
>> {
>> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
>> ~0x20000000u) | (*__carry << 29));
>> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
>> ~0x20000000u) | ((*__carry & 0x1u) << 29));
>> int32x4_t __res = __builtin_mve_vadcq_m_sv4si (__inactive, __a, __b, __p);
>> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
>> return __res;
>> @@ -16085,7 +16085,7 @@ __extension__ extern __inline uint32x4_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> __arm_vadcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b,
>> unsigned * __carry, mve_pred16_t __p)
>> {
>> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
>> ~0x20000000u) | (*__carry << 29));
>> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
>> ~0x20000000u) | ((*__carry & 0x1u) << 29));
>> uint32x4_t __res = __builtin_mve_vadcq_m_uv4si (__inactive, __a, __b,
>> __p);
>> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
>> return __res;
>> @@ -16131,7 +16131,7 @@ __extension__ extern __inline int32x4_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> __arm_vsbcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry)
>> {
>> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
>> ~0x20000000u) | (*__carry << 29));
>> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
>> ~0x20000000u) | ((*__carry & 0x1u) << 29));
>> int32x4_t __res = __builtin_mve_vsbcq_sv4si (__a, __b);
>> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
>> return __res;
>> @@ -16141,7 +16141,7 @@ __extension__ extern __inline uint32x4_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> __arm_vsbcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry)
>> {
>> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
>> ~0x20000000u) | (*__carry << 29));
>> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
>> ~0x20000000u) | ((*__carry & 0x1u) << 29));
>> uint32x4_t __res = __builtin_mve_vsbcq_uv4si (__a, __b);
>> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
>> return __res;
>> @@ -16151,7 +16151,7 @@ __extension__ extern __inline int32x4_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> __arm_vsbcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b,
>> unsigned * __carry, mve_pred16_t __p)
>> {
>> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
>> ~0x20000000u) | (*__carry << 29));
>> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
>> ~0x20000000u) | ((*__carry & 0x1u) << 29));
>> int32x4_t __res = __builtin_mve_vsbcq_m_sv4si (__inactive, __a, __b, __p);
>> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
>> return __res;
>> @@ -16161,7 +16161,7 @@ __extension__ extern __inline uint32x4_t
>> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
>> __arm_vsbcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b,
>> unsigned * __carry, mve_pred16_t __p)
>> {
>> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
>> ~0x20000000u) | (*__carry << 29));
>> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
>> ~0x20000000u) | ((*__carry & 0x1u) << 29));
>> uint32x4_t __res = __builtin_mve_vsbcq_m_uv4si (__inactive, __a, __b,
>> __p);
>> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
>> return __res;
>> --
>> 2.25.1
[-- Attachment #2: rb16695.patch --]
[-- Type: text/x-patch, Size: 7119 bytes --]
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 1262d66812102e1d47d591ccccae0c24008dad60..8778216304b98fe26c0aa7867b6cea4a5703b8d7 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -16055,7 +16055,7 @@ __extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vadcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry)
{
- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
int32x4_t __res = __builtin_mve_vadcq_sv4si (__a, __b);
*__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
return __res;
@@ -16065,7 +16065,7 @@ __extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vadcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry)
{
- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
uint32x4_t __res = __builtin_mve_vadcq_uv4si (__a, __b);
*__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
return __res;
@@ -16075,7 +16075,7 @@ __extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vadcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry, mve_pred16_t __p)
{
- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
int32x4_t __res = __builtin_mve_vadcq_m_sv4si (__inactive, __a, __b, __p);
*__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
return __res;
@@ -16085,7 +16085,7 @@ __extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vadcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry, mve_pred16_t __p)
{
- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
uint32x4_t __res = __builtin_mve_vadcq_m_uv4si (__inactive, __a, __b, __p);
*__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
return __res;
@@ -16131,7 +16131,7 @@ __extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vsbcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry)
{
- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
int32x4_t __res = __builtin_mve_vsbcq_sv4si (__a, __b);
*__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
return __res;
@@ -16141,7 +16141,7 @@ __extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vsbcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry)
{
- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
uint32x4_t __res = __builtin_mve_vsbcq_uv4si (__a, __b);
*__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
return __res;
@@ -16151,7 +16151,7 @@ __extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vsbcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry, mve_pred16_t __p)
{
- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
int32x4_t __res = __builtin_mve_vsbcq_m_sv4si (__inactive, __a, __b, __p);
*__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
return __res;
@@ -16161,7 +16161,7 @@ __extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vsbcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry, mve_pred16_t __p)
{
- __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+ __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
uint32x4_t __res = __builtin_mve_vsbcq_m_uv4si (__inactive, __a, __b, __p);
*__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
return __res;
diff --git a/gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c b/gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c
new file mode 100644
index 0000000000000000000000000000000000000000..8bab684047f527ab8810d6372b5d41c30b601d38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c
@@ -0,0 +1,67 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include <arm_mve.h>
+
+volatile int32x4_t c1;
+volatile uint32x4_t c2;
+int *carry;
+
+int
+main ()
+{
+ int32x4_t a1 = vcreateq_s32 (0, 0);
+ int32x4_t b1 = vcreateq_s32 (0, 0);
+ int32x4_t inactive1 = vcreateq_s32 (0, 0);
+
+ uint32x4_t a2 = vcreateq_u32 (0, 0);
+ uint32x4_t b2 = vcreateq_u32 (0, 0);
+ uint32x4_t inactive2 = vcreateq_u32 (0, 0);
+
+ mve_pred16_t p = 0xFFFF;
+ (*carry) = 0xFFFFFFFF;
+
+ __builtin_arm_set_fpscr_nzcvqc (0);
+ c1 = vadcq (a1, b1, carry);
+ if (__builtin_arm_get_fpscr_nzcvqc ())
+ __builtin_abort ();
+
+ __builtin_arm_set_fpscr_nzcvqc (0);
+ c2 = vadcq (a2, b2, carry);
+ if (__builtin_arm_get_fpscr_nzcvqc ())
+ __builtin_abort ();
+
+ __builtin_arm_set_fpscr_nzcvqc (0);
+ c1 = vsbcq (a1, b1, carry);
+ if (__builtin_arm_get_fpscr_nzcvqc ())
+ __builtin_abort ();
+
+ __builtin_arm_set_fpscr_nzcvqc (0);
+ c2 = vsbcq (a2, b2, carry);
+ if (__builtin_arm_get_fpscr_nzcvqc ())
+ __builtin_abort ();
+
+ __builtin_arm_set_fpscr_nzcvqc (0);
+ c1 = vadcq_m (inactive1, a1, b1, carry, p);
+ if (__builtin_arm_get_fpscr_nzcvqc ())
+ __builtin_abort ();
+
+ __builtin_arm_set_fpscr_nzcvqc (0);
+ c2 = vadcq_m (inactive2, a2, b2, carry, p);
+ if (__builtin_arm_get_fpscr_nzcvqc ())
+ __builtin_abort ();
+
+ __builtin_arm_set_fpscr_nzcvqc (0);
+ c1 = vsbcq_m (inactive1, a1, b1, carry, p);
+ if (__builtin_arm_get_fpscr_nzcvqc ())
+ __builtin_abort ();
+
+ __builtin_arm_set_fpscr_nzcvqc (0);
+ c2 = vsbcq_m (inactive2, a2, b2, carry, p);
+ if (__builtin_arm_get_fpscr_nzcvqc ())
+ __builtin_abort ();
+
+ return 0;
+}
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 10/10] arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes
2023-04-28 16:58 ` Kyrylo Tkachov
@ 2023-05-03 12:34 ` Stamatis Markianos-Wright
2023-05-03 12:56 ` Kyrylo Tkachov
0 siblings, 1 reply; 31+ messages in thread
From: Stamatis Markianos-Wright @ 2023-05-03 12:34 UTC (permalink / raw)
To: Kyrylo Tkachov, Andrea Corallo, gcc-patches; +Cc: Richard Earnshaw
[-- Attachment #1: Type: text/plain, Size: 26641 bytes --]
Hi Kyrill,
On 28/04/2023 17:58, Kyrylo Tkachov wrote:
>
>> -----Original Message-----
>> From: Andrea Corallo <andrea.corallo@arm.com>
>> Sent: Friday, April 28, 2023 12:30 PM
>> To: gcc-patches@gcc.gnu.org
>> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
>> <Richard.Earnshaw@arm.com>; Stam Markianos-Wright <Stam.Markianos-
>> Wright@arm.com>
>> Subject: [PATCH 10/10] arm testsuite: Shifts and get_FPSCR ACLE optimisation
>> fixes
>>
>> From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
>>
>> These newly updated tests were rewritten by Andrea. Some of them
>> needed further manual fixing as follows:
>>
>> * The #shift immediate value not in the check-function-bodies as expected
>> * Some shifts getting optimised to mov immediates, e.g.
>> `uqshll (1, 1);` -> movs r0, #2; movs r1, #0
> Shouldn't this test be testing something that cannot be constant-folded away? i.e. have non-constant arguments?
> I think we should have conformance tests first and foremost, and follow-up tests for such optimisations should be (welcome) added separately.
Ahh, good point! I think in that case I've removed these checks
from here and put them into a new test (it's a bit trivial but I
couldn't find anywhere else where we doing this check with MVE
instructions)
Also, since this patch is the last one in this series, would the
series be Ok for backporting to GCC13?
Thank you!
Stam
>
>> * The ACLE was specifying sub-optimal code: lsr+and instead of ubfx. In
>> this case the test rewritten from the ACLE had the lsr+and pattern,
>> but the compiler was able to optimise to ubfx. Hence I've changed the
>> test to now match on ubfx.
> That looks ok.
> Thanks,
> Kyrill
>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/arm/mve/intrinsics/srshr.c: Update shift value.
>> * gcc.target/arm/mve/intrinsics/srshrl.c: Update shift value.
>> * gcc.target/arm/mve/intrinsics/uqshl.c: Update shift value and mov
>> imm.
>> * gcc.target/arm/mve/intrinsics/uqshll.c: Update shift value and mov
>> imm.
>> * gcc.target/arm/mve/intrinsics/urshr.c: Update shift value.
>> * gcc.target/arm/mve/intrinsics/urshrl.c: Update shift value.
>> * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Update to ubfx.
>> * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Update to ubfx.
>> * gcc.target/arm/mve/intrinsics/vadciq_s32.c: Update to ubfx.
>> * gcc.target/arm/mve/intrinsics/vadciq_u32.c: Update to ubfx.
>> * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Update to ubfx.
>> * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Update to ubfx.
>> * gcc.target/arm/mve/intrinsics/vadcq_s32.c: Update to ubfx.
>> * gcc.target/arm/mve/intrinsics/vadcq_u32.c: Update to ubfx.
>> * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Update to ubfx.
>> * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Update to ubfx.
>> * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Update to ubfx.
>> * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Update to ubfx.
>> * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Update to ubfx.
>> * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Update to ubfx.
>> * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Update to ubfx.
>> * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Update to ubfx.
>> ---
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c | 2 +-
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c | 5 +++--
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c | 4 ++--
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c | 4 ++--
>> .../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 8 ++------
>> .../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 8 ++------
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c | 8 ++------
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c | 8 ++------
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c | 8 ++------
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c | 8 ++------
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c | 8 ++------
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c | 8 ++------
>> .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 8 ++------
>> .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 8 ++------
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 8 ++------
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 8 ++------
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 8 ++------
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 8 ++------
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 8 ++------
>> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 8 ++------
>> 22 files changed, 43 insertions(+), 106 deletions(-)
>>
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
>> index 94e3f42fd33..734375d58c0 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
>> @@ -12,7 +12,7 @@ extern "C" {
>> /*
>> **foo:
>> ** ...
>> -** srshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
>> +** srshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> ** ...
>> */
>> int32_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
>> index 65f28ccbfde..a91943c38a0 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
>> @@ -12,7 +12,7 @@ extern "C" {
>> /*
>> **foo:
>> ** ...
>> -** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
>> +** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> ** ...
>> */
>> int64_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
>> index b23c9d97ba6..58aa7a61e42 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
>> @@ -12,7 +12,7 @@ extern "C" {
>> /*
>> **foo:
>> ** ...
>> -** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|)
>> +** uqshl (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> ** ...
>> */
>> uint32_t
>> @@ -24,7 +24,7 @@ foo (uint32_t value)
>> /*
>> **foo1:
>> ** ...
>> -** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|)
>> +** movs r0, #2
>> ** ...
>> */
>> uint32_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
>> index 6a3d08eea75..5584544aaf7 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
>> @@ -12,7 +12,7 @@ extern "C" {
>> /*
>> **foo:
>> ** ...
>> -** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
>> +** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> ** ...
>> */
>> uint64_t
>> @@ -24,7 +24,8 @@ foo (uint64_t value)
>> /*
>> **foo1:
>> ** ...
>> -** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
>> +** movs r0, #2
>> +** movs r1, #0
>> ** ...
>> */
>> uint64_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
>> index 23afcb8da4c..ff97bf5c473 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
>> @@ -12,7 +12,7 @@ extern "C" {
>> /*
>> **foo:
>> ** ...
>> -** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
>> +** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> ** ...
>> */
>> uint32_t
>> @@ -24,7 +24,7 @@ foo (uint32_t value)
>> /*
>> **foo1:
>> ** ...
>> -** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
>> +** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> ** ...
>> */
>> uint32_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
>> index 8014371f47f..ff6a69d300f 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
>> @@ -12,7 +12,7 @@ extern "C" {
>> /*
>> **foo:
>> ** ...
>> -** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
>> +** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> ** ...
>> */
>> uint64_t
>> @@ -24,7 +24,7 @@ foo (uint64_t value)
>> /*
>> **foo1:
>> ** ...
>> -** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
>> +** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> ** ...
>> */
>> uint64_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
>> index b262bf94d39..a6a059a19e9 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
>> @@ -20,9 +20,7 @@ extern "C" {
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> int32x4_t
>> @@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b,
>> unsigned *carry_out, mve_pred
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> int32x4_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
>> index d349caed36a..942111339f0 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
>> @@ -20,9 +20,7 @@ extern "C" {
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> uint32x4_t
>> @@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b,
>> unsigned *carry_out, mve_p
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> uint32x4_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
>> index 5166993a355..3b68bb6ac33 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
>> @@ -16,9 +16,7 @@ extern "C" {
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> int32x4_t
>> @@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> int32x4_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
>> index 080bd61d238..82228491043 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
>> @@ -16,9 +16,7 @@ extern "C" {
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> uint32x4_t
>> @@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> uint32x4_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
>> index 45e6ff03623..0d4cb779254 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
>> @@ -26,9 +26,7 @@ extern "C" {
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> int32x4_t
>> @@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b,
>> unsigned *carry, mve_pred16_t
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> int32x4_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
>> index 54f141b2093..a0ba6825d8c 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
>> @@ -26,9 +26,7 @@ extern "C" {
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> uint32x4_t
>> @@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b,
>> unsigned *carry, mve_pred1
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> uint32x4_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
>> index 06d5bae09da..47f5f22dde9 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
>> @@ -22,9 +22,7 @@ extern "C" {
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> int32x4_t
>> @@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> int32x4_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
>> index e2111cfd16a..55a961be217 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
>> @@ -22,9 +22,7 @@ extern "C" {
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> uint32x4_t
>> @@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> uint32x4_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
>> index 66a5c4c9da3..dcbaef1a571 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
>> @@ -20,9 +20,7 @@ extern "C" {
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> int32x4_t
>> @@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b,
>> unsigned *carry_out, mve_pred
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> int32x4_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
>> index 9306f152cde..08f67f665c1 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
>> @@ -20,9 +20,7 @@ extern "C" {
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> uint32x4_t
>> @@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b,
>> unsigned *carry_out, mve_p
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> uint32x4_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
>> index 0b5040f0b2a..803246c3235 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
>> @@ -16,9 +16,7 @@ extern "C" {
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> int32x4_t
>> @@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> int32x4_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
>> index df211a64daa..22d2b4355bc 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
>> @@ -16,9 +16,7 @@ extern "C" {
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> uint32x4_t
>> @@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> uint32x4_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
>> index 217cfa7ac21..7a332610c69 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
>> @@ -26,9 +26,7 @@ extern "C" {
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> int32x4_t
>> @@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b,
>> unsigned *carry, mve_pred16_t
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> int32x4_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
>> index dad04d05d68..60902196502 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
>> @@ -26,9 +26,7 @@ extern "C" {
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> uint32x4_t
>> @@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b,
>> unsigned *carry, mve_pred1
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> uint32x4_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
>> index cd033640bcc..523fa32ee0d 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
>> @@ -22,9 +22,7 @@ extern "C" {
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> int32x4_t
>> @@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> int32x4_t
>> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
>> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
>> index 6ca0c753b5e..ff720fd2df5 100644
>> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
>> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
>> @@ -22,9 +22,7 @@ extern "C" {
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> uint32x4_t
>> @@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
>> ** ...
>> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
>> ** ...
>> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
>> -** ...
>> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
>> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
>> ** ...
>> */
>> uint32x4_t
>> --
>> 2.25.1
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diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
index 94e3f42fd33aaf981c0b4bc1296e41f20346705e..734375d58c0664eb8c58a5a53f180bf9ebd74c9f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
@@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
-** srshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** srshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
int32_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
index 65f28ccbfdea445b3249b7c8ada9922e89b059da..a91943c38a017e2e26583d80f8e8665b54ed015e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
@@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
-** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
int64_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
index b23c9d97ba653af798f76f9e8e68968b7c75d074..462531cad54e5bfe21e8a5cbd72ef41200a2399b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
@@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
-** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** uqshl (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint32_t
@@ -21,18 +21,6 @@ foo (uint32_t value)
return uqshl (value, 1);
}
-/*
-**foo1:
-** ...
-** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|)
-** ...
-*/
-uint32_t
-foo1 ()
-{
- return uqshl (1, 1);
-}
-
#ifdef __cplusplus
}
#endif
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
index 6a3d08eea756afeed57be09b8f2f70dbb3275ac6..6fa97a561e317b7e1dfa11d0ef7f0fdd7ec3b5ee 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
@@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
-** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint64_t
@@ -21,18 +21,6 @@ foo (uint64_t value)
return uqshll (value, 1);
}
-/*
-**foo1:
-** ...
-** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
-** ...
-*/
-uint64_t
-foo1 ()
-{
- return uqshll (1, 1);
-}
-
#ifdef __cplusplus
}
#endif
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
index 23afcb8da4c407429fd25c5bfb252e5dbe3ed570..ff97bf5c473bf169c9028eaf7b23f0bcb6a980b6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
@@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
-** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint32_t
@@ -24,7 +24,7 @@ foo (uint32_t value)
/*
**foo1:
** ...
-** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint32_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
index 8014371f47fa8d134d240ebca72d9500978cbbe4..ff6a69d300fa64782777f9952d81edf45e115664 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
@@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
-** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint64_t
@@ -24,7 +24,7 @@ foo (uint64_t value)
/*
**foo1:
** ...
-** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint64_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
index b262bf94d39315a18af4098cfcb2cebc0acf9338..a6a059a19e959c8e3855f0596bdad4d694fcb391 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
@@ -20,9 +20,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
index d349caed36ac1ed5d830dbad09c84d301840cfb9..942111339f0debdd42c1962f3892f1a8e07af2de 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
@@ -20,9 +20,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_p
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
index 5166993a3555858f5cf8c98a78f2641d5eb96533..3b68bb6ac33eabd0d2f825f5c7728740b8935dd5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
@@ -16,9 +16,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
index 080bd61d23852bc5786691646223e0500ec31e13..82228491043202273e1254ef3e694cbf2d731735 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
@@ -16,9 +16,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
index 45e6ff03623c41e6489596866d00af30a4d2f7e2..0d4cb779254982b760d3ae91227df2b8e700459f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
@@ -26,9 +26,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
index 54f141b20931e9efc86224bc90f0af0c38306eec..a0ba6825d8c978fa3814e93c5b160fef59b3ea75 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
@@ -26,9 +26,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
index 06d5bae09da518c35933aa526ad8d8d71ea5445a..47f5f22dde935ca0ef1ae592e6ff40b07affb616 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
@@ -22,9 +22,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
index e2111cfd16aeff466376547bc169bf09b61338ae..55a961be2178b5bc2321321e3140b1dcb1c7de50 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
@@ -22,9 +22,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
index 66a5c4c9da3e3d1fb1be8db264a3ab45f0cc1c05..dcbaef1a5717cdce8fe6ee7b715f0346c13bbde0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
@@ -20,9 +20,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
index 9306f152cdeb0c9daba19b3e3855ddcd3d9f83aa..08f67f665c1c2137ad948b4c077540d4e394cf6d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
@@ -20,9 +20,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_p
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
index 0b5040f0b2a23720bdb61f82af06c8a754dbc612..803246c32352d8108b27365b1e7828367629f293 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
@@ -16,9 +16,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
index df211a64daad398250e253a1967a03c576dd5ba8..22d2b4355bc12477f9899f5c80b0c42ad473733f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
@@ -16,9 +16,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
index 217cfa7ac2136f4938e4921527b52d539c870b7f..7a332610c69392032289633c2e67f46efe98df9e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
@@ -26,9 +26,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
index dad04d05d68c772f3453443748b446b623315651..609021965022f442ad48f9db4a36bd7e42464a7f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
@@ -26,9 +26,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
index cd033640bcc0487c59c51c4aae1430596773855b..523fa32ee0d8e7c66f208c59d084a91cd663f860 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
@@ -22,9 +22,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
index 6ca0c753b5e45cbb7a48dc060901635f21644095..ff720fd2df589a49684545a1afc4378a46b98868 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
@@ -22,9 +22,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c b/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c
new file mode 100644
index 0000000000000000000000000000000000000000..1ad91070d93da13583eb37edb2b41135972bf70a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c
@@ -0,0 +1,66 @@
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "arm_mve.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo11:
+** ...
+** movs r0, #2
+** ...
+*/
+uint32_t
+foo11 ()
+{
+ return uqshl (1, 1);
+}
+
+/*
+**foo12:
+** ...
+** movs r0, #2
+** movs r1, #0
+** ...
+*/
+uint64_t
+foo12 ()
+{
+ return uqshll (1, 1);
+}
+
+/*
+**foo13:
+** ...
+** movs r0, #1
+** ...
+*/
+uint32_t
+foo13 ()
+{
+ return uqshr (3, 1);
+}
+
+/*
+**foo13:
+** ...
+** movs r0, #2
+** movs r1, #0
+** ...
+*/
+uint64_t
+foo13 ()
+{
+ return uqshrl (3, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH 04/10] arm: Stop vadcq, vsbcq intrinsics from overwriting the FPSCR NZ flags
2023-05-03 12:19 ` Stamatis Markianos-Wright
@ 2023-05-03 12:55 ` Kyrylo Tkachov
0 siblings, 0 replies; 31+ messages in thread
From: Kyrylo Tkachov @ 2023-05-03 12:55 UTC (permalink / raw)
To: Stam Markianos-Wright, Andrea Corallo, gcc-patches; +Cc: Richard Earnshaw
> -----Original Message-----
> From: Stam Markianos-Wright <Stam.Markianos-Wright@arm.com>
> Sent: Wednesday, May 3, 2023 1:19 PM
> To: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Andrea Corallo
> <Andrea.Corallo@arm.com>; gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>
> Subject: Re: [PATCH 04/10] arm: Stop vadcq, vsbcq intrinsics from overwriting
> the FPSCR NZ flags
>
>
> On 28/04/2023 17:45, Kyrylo Tkachov wrote:
> > Hi Andrea, Stam,
> >
> >> -----Original Message-----
> >> From: Andrea Corallo <andrea.corallo@arm.com>
> >> Sent: Friday, April 28, 2023 12:30 PM
> >> To: gcc-patches@gcc.gnu.org
> >> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> >> <Richard.Earnshaw@arm.com>; Stam Markianos-Wright
> <Stam.Markianos-
> >> Wright@arm.com>
> >> Subject: [PATCH 04/10] arm: Stop vadcq, vsbcq intrinsics from overwriting
> the
> >> FPSCR NZ flags
> >>
> >> From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
> >>
> >> Hi all,
> >>
> >> We noticed that calls to the vadcq and vsbcq intrinsics, both of
> >> which use __builtin_arm_set_fpscr_nzcvqc to set the Carry flag in
> >> the FPSCR, would produce the following code:
> >>
> >> ```
> >> < r2 is the *carry input >
> >> vmrs r3, FPSCR_nzcvqc
> >> bic r3, r3, #536870912
> >> orr r3, r3, r2, lsl #29
> >> vmsr FPSCR_nzcvqc, r3
> >> ```
> >>
> >> when the MVE ACLE instead gives a different instruction sequence of:
> >> ```
> >> < Rt is the *carry input >
> >> VMRS Rs,FPSCR_nzcvqc
> >> BFI Rs,Rt,#29,#1
> >> VMSR FPSCR_nzcvqc,Rs
> >> ```
> >>
> >> the bic + orr pair is slower and it's also wrong, because, if the
> >> *carry input is greater than 1, then we risk overwriting the top two
> >> bits of the FPSCR register (the N and Z flags).
> >>
> >> This turned out to be a problem in the header file and the solution was
> >> to simply add a `& 1x0u` to the `*carry` input: then the compiler knows
> >> that we only care about the lowest bit and can optimise to a BFI.
> >>
> >> Ok for trunk?
> > Ok, but I think this needs testsuite coverage for the bug?
> > Thanks,
> > Kyrill
>
> So this can be seen in the new vadcq* , vsbcq* tests:
>
> ** ...
> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> ** ...
> ** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> ** ...
> ** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
> ** ...
>
> The fact that there's a BFI there rather than the BIC + ORR shows
> that this has now been optimised by the compiler and the bug isn't
> present in those intrinsics any longer... Sorry, I should have linked
> that in better in our patch series!
>
> Added a runtest, also, as it was fairly trivial to write it out :)
Ok.
Thanks,
Kyrill
>
> Thanks,
> Stam
>
> >
> >> Thanks,
> >> Stam Markianos-Wright
> >>
> >> gcc/ChangeLog:
> >>
> >> * config/arm/arm_mve.h (__arm_vadcq_s32): Fix arithmetic.
> >> (__arm_vadcq_u32): Likewise.
> >> (__arm_vadcq_m_s32): Likewise.
> >> (__arm_vadcq_m_u32): Likewise.
> >> (__arm_vsbcq_s32): Likewise.
> >> (__arm_vsbcq_u32): Likewise.
> >> (__arm_vsbcq_m_s32): Likewise.
> >> (__arm_vsbcq_m_u32): Likewise.
> >> ---
> >> gcc/config/arm/arm_mve.h | 16 ++++++++--------
> >> 1 file changed, 8 insertions(+), 8 deletions(-)
> >>
> >> diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
> >> index 1262d668121..8778216304b 100644
> >> --- a/gcc/config/arm/arm_mve.h
> >> +++ b/gcc/config/arm/arm_mve.h
> >> @@ -16055,7 +16055,7 @@ __extension__ extern __inline int32x4_t
> >> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> >> __arm_vadcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry)
> >> {
> >> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> >> ~0x20000000u) | (*__carry << 29));
> >> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> >> ~0x20000000u) | ((*__carry & 0x1u) << 29));
> >> int32x4_t __res = __builtin_mve_vadcq_sv4si (__a, __b);
> >> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
> >> return __res;
> >> @@ -16065,7 +16065,7 @@ __extension__ extern __inline uint32x4_t
> >> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> >> __arm_vadcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry)
> >> {
> >> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> >> ~0x20000000u) | (*__carry << 29));
> >> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> >> ~0x20000000u) | ((*__carry & 0x1u) << 29));
> >> uint32x4_t __res = __builtin_mve_vadcq_uv4si (__a, __b);
> >> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
> >> return __res;
> >> @@ -16075,7 +16075,7 @@ __extension__ extern __inline int32x4_t
> >> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> >> __arm_vadcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b,
> >> unsigned * __carry, mve_pred16_t __p)
> >> {
> >> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> >> ~0x20000000u) | (*__carry << 29));
> >> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> >> ~0x20000000u) | ((*__carry & 0x1u) << 29));
> >> int32x4_t __res = __builtin_mve_vadcq_m_sv4si (__inactive, __a, __b,
> __p);
> >> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
> >> return __res;
> >> @@ -16085,7 +16085,7 @@ __extension__ extern __inline uint32x4_t
> >> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> >> __arm_vadcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t
> __b,
> >> unsigned * __carry, mve_pred16_t __p)
> >> {
> >> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> >> ~0x20000000u) | (*__carry << 29));
> >> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> >> ~0x20000000u) | ((*__carry & 0x1u) << 29));
> >> uint32x4_t __res = __builtin_mve_vadcq_m_uv4si (__inactive, __a, __b,
> >> __p);
> >> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
> >> return __res;
> >> @@ -16131,7 +16131,7 @@ __extension__ extern __inline int32x4_t
> >> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> >> __arm_vsbcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry)
> >> {
> >> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> >> ~0x20000000u) | (*__carry << 29));
> >> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> >> ~0x20000000u) | ((*__carry & 0x1u) << 29));
> >> int32x4_t __res = __builtin_mve_vsbcq_sv4si (__a, __b);
> >> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
> >> return __res;
> >> @@ -16141,7 +16141,7 @@ __extension__ extern __inline uint32x4_t
> >> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> >> __arm_vsbcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry)
> >> {
> >> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> >> ~0x20000000u) | (*__carry << 29));
> >> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> >> ~0x20000000u) | ((*__carry & 0x1u) << 29));
> >> uint32x4_t __res = __builtin_mve_vsbcq_uv4si (__a, __b);
> >> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
> >> return __res;
> >> @@ -16151,7 +16151,7 @@ __extension__ extern __inline int32x4_t
> >> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> >> __arm_vsbcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b,
> >> unsigned * __carry, mve_pred16_t __p)
> >> {
> >> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> >> ~0x20000000u) | (*__carry << 29));
> >> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> >> ~0x20000000u) | ((*__carry & 0x1u) << 29));
> >> int32x4_t __res = __builtin_mve_vsbcq_m_sv4si (__inactive, __a, __b,
> __p);
> >> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
> >> return __res;
> >> @@ -16161,7 +16161,7 @@ __extension__ extern __inline uint32x4_t
> >> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> >> __arm_vsbcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t
> __b,
> >> unsigned * __carry, mve_pred16_t __p)
> >> {
> >> - __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> >> ~0x20000000u) | (*__carry << 29));
> >> + __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () &
> >> ~0x20000000u) | ((*__carry & 0x1u) << 29));
> >> uint32x4_t __res = __builtin_mve_vsbcq_m_uv4si (__inactive, __a, __b,
> >> __p);
> >> *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
> >> return __res;
> >> --
> >> 2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH 10/10] arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes
2023-05-03 12:34 ` Stamatis Markianos-Wright
@ 2023-05-03 12:56 ` Kyrylo Tkachov
0 siblings, 0 replies; 31+ messages in thread
From: Kyrylo Tkachov @ 2023-05-03 12:56 UTC (permalink / raw)
To: Stam Markianos-Wright, Andrea Corallo, gcc-patches; +Cc: Richard Earnshaw
> -----Original Message-----
> From: Stam Markianos-Wright <Stam.Markianos-Wright@arm.com>
> Sent: Wednesday, May 3, 2023 1:35 PM
> To: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Andrea Corallo
> <Andrea.Corallo@arm.com>; gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>
> Subject: [PATCH 10/10] arm testsuite: Shifts and get_FPSCR ACLE optimisation
> fixes
>
> Hi Kyrill,
>
> On 28/04/2023 17:58, Kyrylo Tkachov wrote:
> >
> >> -----Original Message-----
> >> From: Andrea Corallo <andrea.corallo@arm.com>
> >> Sent: Friday, April 28, 2023 12:30 PM
> >> To: gcc-patches@gcc.gnu.org
> >> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> >> <Richard.Earnshaw@arm.com>; Stam Markianos-Wright
> <Stam.Markianos-
> >> Wright@arm.com>
> >> Subject: [PATCH 10/10] arm testsuite: Shifts and get_FPSCR ACLE
> optimisation
> >> fixes
> >>
> >> From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
> >>
> >> These newly updated tests were rewritten by Andrea. Some of them
> >> needed further manual fixing as follows:
> >>
> >> * The #shift immediate value not in the check-function-bodies as expected
> >> * Some shifts getting optimised to mov immediates, e.g.
> >> `uqshll (1, 1);` -> movs r0, #2; movs r1, #0
> > Shouldn't this test be testing something that cannot be constant-folded
> away? i.e. have non-constant arguments?
> > I think we should have conformance tests first and foremost, and follow-up
> tests for such optimisations should be (welcome) added separately.
>
> Ahh, good point! I think in that case I've removed these checks
> from here and put them into a new test (it's a bit trivial but I
> couldn't find anywhere else where we doing this check with MVE
> instructions)
>
>
> Also, since this patch is the last one in this series, would the
> series be Ok for backporting to GCC13?
Yes, ok for backporting too.
Thanks,
Kyrill
>
> Thank you!
> Stam
>
> >
> >> * The ACLE was specifying sub-optimal code: lsr+and instead of ubfx. In
> >> this case the test rewritten from the ACLE had the lsr+and pattern,
> >> but the compiler was able to optimise to ubfx. Hence I've changed the
> >> test to now match on ubfx.
> > That looks ok.
> > Thanks,
> > Kyrill
> >
> >> gcc/testsuite/ChangeLog:
> >>
> >> * gcc.target/arm/mve/intrinsics/srshr.c: Update shift value.
> >> * gcc.target/arm/mve/intrinsics/srshrl.c: Update shift value.
> >> * gcc.target/arm/mve/intrinsics/uqshl.c: Update shift value and mov
> >> imm.
> >> * gcc.target/arm/mve/intrinsics/uqshll.c: Update shift value and mov
> >> imm.
> >> * gcc.target/arm/mve/intrinsics/urshr.c: Update shift value.
> >> * gcc.target/arm/mve/intrinsics/urshrl.c: Update shift value.
> >> * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Update to ubfx.
> >> * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Update to ubfx.
> >> * gcc.target/arm/mve/intrinsics/vadciq_s32.c: Update to ubfx.
> >> * gcc.target/arm/mve/intrinsics/vadciq_u32.c: Update to ubfx.
> >> * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Update to ubfx.
> >> * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Update to ubfx.
> >> * gcc.target/arm/mve/intrinsics/vadcq_s32.c: Update to ubfx.
> >> * gcc.target/arm/mve/intrinsics/vadcq_u32.c: Update to ubfx.
> >> * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Update to ubfx.
> >> * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Update to ubfx.
> >> * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Update to ubfx.
> >> * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Update to ubfx.
> >> * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Update to ubfx.
> >> * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Update to ubfx.
> >> * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Update to ubfx.
> >> * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Update to ubfx.
> >> ---
> >> gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c | 2 +-
> >> gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c | 2 +-
> >> gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c | 4 ++--
> >> gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c | 5 +++--
> >> gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c | 4 ++--
> >> gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c | 4 ++--
> >> .../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 8 ++------
> >> .../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 8 ++------
> >> gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c | 8 ++------
> >> gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c | 8 ++------
> >> gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c | 8 ++------
> >> gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c | 8 ++------
> >> gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c | 8 ++------
> >> gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c | 8 ++------
> >> .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 8 ++------
> >> .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 8 ++------
> >> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 8 ++------
> >> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 8 ++------
> >> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 8 ++------
> >> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 8 ++------
> >> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 8 ++------
> >> gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 8 ++------
> >> 22 files changed, 43 insertions(+), 106 deletions(-)
> >>
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
> >> index 94e3f42fd33..734375d58c0 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
> >> @@ -12,7 +12,7 @@ extern "C" {
> >> /*
> >> **foo:
> >> ** ...
> >> -** srshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> >> +** srshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> ** ...
> >> */
> >> int32_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
> >> index 65f28ccbfde..a91943c38a0 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
> >> @@ -12,7 +12,7 @@ extern "C" {
> >> /*
> >> **foo:
> >> ** ...
> >> -** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> >> +** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> ** ...
> >> */
> >> int64_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
> >> index b23c9d97ba6..58aa7a61e42 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
> >> @@ -12,7 +12,7 @@ extern "C" {
> >> /*
> >> **foo:
> >> ** ...
> >> -** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> >> +** uqshl (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32_t
> >> @@ -24,7 +24,7 @@ foo (uint32_t value)
> >> /*
> >> **foo1:
> >> ** ...
> >> -** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> >> +** movs r0, #2
> >> ** ...
> >> */
> >> uint32_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
> >> index 6a3d08eea75..5584544aaf7 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
> >> @@ -12,7 +12,7 @@ extern "C" {
> >> /*
> >> **foo:
> >> ** ...
> >> -** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> >> +** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> ** ...
> >> */
> >> uint64_t
> >> @@ -24,7 +24,8 @@ foo (uint64_t value)
> >> /*
> >> **foo1:
> >> ** ...
> >> -** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> >> +** movs r0, #2
> >> +** movs r1, #0
> >> ** ...
> >> */
> >> uint64_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
> >> index 23afcb8da4c..ff97bf5c473 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
> >> @@ -12,7 +12,7 @@ extern "C" {
> >> /*
> >> **foo:
> >> ** ...
> >> -** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> >> +** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32_t
> >> @@ -24,7 +24,7 @@ foo (uint32_t value)
> >> /*
> >> **foo1:
> >> ** ...
> >> -** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> >> +** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
> >> index 8014371f47f..ff6a69d300f 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
> >> @@ -12,7 +12,7 @@ extern "C" {
> >> /*
> >> **foo:
> >> ** ...
> >> -** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> >> +** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> ** ...
> >> */
> >> uint64_t
> >> @@ -24,7 +24,7 @@ foo (uint64_t value)
> >> /*
> >> **foo1:
> >> ** ...
> >> -** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
> >> +** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> ** ...
> >> */
> >> uint64_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
> >> index b262bf94d39..a6a059a19e9 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
> >> @@ -20,9 +20,7 @@ extern "C" {
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> int32x4_t
> >> @@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b,
> >> unsigned *carry_out, mve_pred
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> int32x4_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
> >> index d349caed36a..942111339f0 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
> >> @@ -20,9 +20,7 @@ extern "C" {
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32x4_t
> >> @@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b,
> >> unsigned *carry_out, mve_p
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32x4_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
> >> index 5166993a355..3b68bb6ac33 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
> >> @@ -16,9 +16,7 @@ extern "C" {
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> int32x4_t
> >> @@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> int32x4_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
> >> index 080bd61d238..82228491043 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
> >> @@ -16,9 +16,7 @@ extern "C" {
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32x4_t
> >> @@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32x4_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
> >> index 45e6ff03623..0d4cb779254 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
> >> @@ -26,9 +26,7 @@ extern "C" {
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> int32x4_t
> >> @@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b,
> >> unsigned *carry, mve_pred16_t
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> int32x4_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
> >> index 54f141b2093..a0ba6825d8c 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
> >> @@ -26,9 +26,7 @@ extern "C" {
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32x4_t
> >> @@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b,
> >> unsigned *carry, mve_pred1
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32x4_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
> >> index 06d5bae09da..47f5f22dde9 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
> >> @@ -22,9 +22,7 @@ extern "C" {
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> int32x4_t
> >> @@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> int32x4_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
> >> index e2111cfd16a..55a961be217 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
> >> @@ -22,9 +22,7 @@ extern "C" {
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32x4_t
> >> @@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32x4_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
> >> index 66a5c4c9da3..dcbaef1a571 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
> >> @@ -20,9 +20,7 @@ extern "C" {
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> int32x4_t
> >> @@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b,
> >> unsigned *carry_out, mve_pred
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> int32x4_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
> >> index 9306f152cde..08f67f665c1 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
> >> @@ -20,9 +20,7 @@ extern "C" {
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32x4_t
> >> @@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b,
> >> unsigned *carry_out, mve_p
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32x4_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
> >> index 0b5040f0b2a..803246c3235 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
> >> @@ -16,9 +16,7 @@ extern "C" {
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> int32x4_t
> >> @@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> int32x4_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
> >> index df211a64daa..22d2b4355bc 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
> >> @@ -16,9 +16,7 @@ extern "C" {
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32x4_t
> >> @@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32x4_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
> >> index 217cfa7ac21..7a332610c69 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
> >> @@ -26,9 +26,7 @@ extern "C" {
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> int32x4_t
> >> @@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b,
> >> unsigned *carry, mve_pred16_t
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> int32x4_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
> >> index dad04d05d68..60902196502 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
> >> @@ -26,9 +26,7 @@ extern "C" {
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32x4_t
> >> @@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b,
> >> unsigned *carry, mve_pred1
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32x4_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
> >> index cd033640bcc..523fa32ee0d 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
> >> @@ -22,9 +22,7 @@ extern "C" {
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> int32x4_t
> >> @@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> int32x4_t
> >> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
> >> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
> >> index 6ca0c753b5e..ff720fd2df5 100644
> >> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
> >> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
> >> @@ -22,9 +22,7 @@ extern "C" {
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32x4_t
> >> @@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
> >> ** ...
> >> ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
> >> ** ...
> >> -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
> >> -** ...
> >> -** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
> >> +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
> >> ** ...
> >> */
> >> uint32x4_t
> >> --
> >> 2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2023-05-03 12:56 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-04-28 11:29 [PATCH 01/10] arm: Mve testsuite improvements Andrea Corallo
2023-04-28 11:29 ` [PATCH 02/10] arm: Fix vstrwq* backend + testsuite Andrea Corallo
2023-04-28 16:27 ` Kyrylo Tkachov
2023-05-02 8:21 ` Christophe Lyon
2023-05-02 8:45 ` Andrea Corallo
2023-05-02 10:18 ` Andrea Corallo
2023-04-28 11:29 ` [PATCH 03/10] arm: Mve backend + testsuite fixes 2 Andrea Corallo
2023-04-28 16:40 ` Kyrylo Tkachov
2023-05-02 11:53 ` Andrea Corallo
2023-04-28 11:29 ` [PATCH 04/10] arm: Stop vadcq, vsbcq intrinsics from overwriting the FPSCR NZ flags Andrea Corallo
2023-04-28 16:45 ` Kyrylo Tkachov
2023-05-03 12:19 ` Stamatis Markianos-Wright
2023-05-03 12:55 ` Kyrylo Tkachov
2023-04-28 11:29 ` [PATCH 05/10] arm: Add vorrq_n overloading into vorrq _Generic Andrea Corallo
2023-04-28 16:47 ` Kyrylo Tkachov
2023-04-28 11:29 ` [PATCH 06/10] arm: Fix overloading of MVE scalar constant parameters on vbicq, vmvnq_m Andrea Corallo
2023-04-28 16:47 ` Kyrylo Tkachov
2023-04-28 11:29 ` [PATCH 07/10] arm: Fix MVE header pointer overloads this time (and a bit more tidying) Andrea Corallo
2023-04-28 16:51 ` Kyrylo Tkachov
2023-04-28 11:30 ` [PATCH 08/10] arm testsuite: Remove reduntant tests Andrea Corallo
2023-04-28 16:52 ` Kyrylo Tkachov
2023-04-28 11:30 ` [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests Andrea Corallo
2023-04-28 16:54 ` Kyrylo Tkachov
2023-05-02 12:17 ` Stamatis Markianos-Wright
2023-05-02 8:28 ` Christophe Lyon
2023-05-02 9:33 ` Stamatis Markianos-Wright
2023-04-28 11:30 ` [PATCH 10/10] arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes Andrea Corallo
2023-04-28 16:58 ` Kyrylo Tkachov
2023-05-03 12:34 ` Stamatis Markianos-Wright
2023-05-03 12:56 ` Kyrylo Tkachov
2023-04-28 16:27 ` [PATCH 01/10] arm: Mve testsuite improvements Kyrylo Tkachov
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