From: "Paul Edwards" <mutazilah@gmail.com>
To: "Ulrich Weigand" <uweigand@de.ibm.com>
Cc: <gcc@gcc.gnu.org>
Subject: Re: i370 port
Date: Tue, 16 Aug 2011 11:20:00 -0000 [thread overview]
Message-ID: <6F866F5E4EEE4505945C7C6850D64491@pauldell> (raw)
In-Reply-To: <201108151723.p7FHNSmQ024681@d06av02.portsmouth.uk.ibm.com>
>> Unfortunately it's not quite right, seemingly not loading R9 properly:
>>
>> LR 9,13
>> AR 9,13
>> MVC 0(10,9),0(2)
> That's weird. What does the reload dump (.greg) say?
I have trimmed the code down to a reasonably small size so that I
could provide the .greg file (below) from the "-da" option. I don't
know how to read it so I don't know if I've provided everything
required.
Here is the current problematic generated code:
* Function pdosLoadExe code
L 2,4(11)
MVC 88(4,13),=A(LC0)
ST 2,92(13)
LA 1,88(,13)
L 15,=V(PRINTF)
BALR 14,15
LR 3,13 <========= probably wrong
AR 3,13 <========= else this is wrong
MVC 0(10,3),0(2)
Thanks. Paul.
#include <stdio.h>
#include <string.h>
#define MAXBLKSZ 32767
typedef struct { int ipldev; } PDOS;
typedef struct {
char ds1dsnam[44]; /* dataset name */
char ds1fmtid; /* must be set to '1' */
char startcchh[4];
} DSCB1;
int pdosLoadExe(PDOS *pdos, char *prog, char *parm)
{
char *raw;
char *initial;
char *load;
/* Standard C programs can start at a predictable offset */
int entry;
int cyl;
int head;
int rec;
int i;
int j;
char tbuf[MAXBLKSZ];
char srchprog[FILENAME_MAX+10]; /* give an extra space */
int cnt = -1;
int lastcnt = 0;
int ret = 0;
DSCB1 dscb1;
int pe = 0;
int exeLen;
/* try to find the load module's location */
printf("in pdosLoadExe with %.8s\n", prog);
/* +++ replace this 8 with some constant */
memcpy(srchprog, prog, 10);
printf("srchprog now %.8s\n", srchprog);
srchprog[8] = ' ';
*strchr(srchprog, ' ') = '\0';
strcat(srchprog, ".EXE "); /* extra space deliberate */
printf("going to search for %s\n", srchprog);
/* read VOL1 record */
cnt = rdblock(pdos->ipldev, 0, 0, 3, tbuf, MAXBLKSZ);
if (cnt >= 20)
{
cyl = head = rec = 0;
/* +++ probably time to create some macros for this */
memcpy((char *)&cyl + sizeof(int) - 2, tbuf + 15, 2);
memcpy((char *)&head + sizeof(int) - 2, tbuf + 17, 2);
memcpy((char *)&rec + sizeof(int) - 1, tbuf + 19, 1);
while ((cnt =
rdblock(pdos->ipldev, cyl, head, rec, &dscb1, sizeof dscb1))
> 0)
{
if (cnt >= sizeof dscb1)
{
if (dscb1.ds1fmtid == '1')
{
dscb1.ds1fmtid = ' '; /* for easy comparison */
if (memcmp(dscb1.ds1dsnam,
srchprog,
strlen(srchprog)) == 0)
{
cyl = head = 0;
rec = 1;
/* +++ more macros needed here */
memcpy((char *)&cyl + sizeof(int) - 2,
dscb1.startcchh, 2);
memcpy((char *)&head + sizeof(int) - 2,
dscb1.startcchh + 2, 2);
break;
}
}
}
rec++;
}
}
if (cnt <= 0)
{
printf("about to zap %s\n", srchprog);
*strchr(srchprog, ' ') = '\0';
printf("executable %s not found!\n", srchprog);
return (-1);
}
return (ret);
}
COPY PDPTOP
CSECT
* Program text area
LC0 EQU *
DC C'in pdosLoadExe with %.8s'
DC X'15'
DC X'0'
LC1 EQU *
DC C'srchprog now %.8s'
DC X'15'
DC X'0'
LC2 EQU *
DC C'.EXE '
DC X'0'
LC3 EQU *
DC C'going to search for %s'
DC X'15'
DC X'0'
LC4 EQU *
DC C'about to zap %s'
DC X'15'
DC X'0'
LC5 EQU *
DC C'executable %s not found!'
DC X'15'
DC X'0'
DS 0F
* X-func pdosLoadExe prologue
PDOSLOAD PDPPRLG CINDEX=0,FRAME=33224,BASER=12,ENTRY=YES
B FEN0
LTORG
FEN0 EQU *
DROP 12
BALR 12,0
USING *,12
PG0 EQU *
LR 11,1
L 10,=A(PGT0)
* Function pdosLoadExe code
L 2,4(11)
MVC 88(4,13),=A(LC0)
ST 2,92(13)
LA 1,88(,13)
L 15,=V(PRINTF)
BALR 14,15
LR 3,13
AR 3,13
MVC 0(10,3),0(2)
MVC 88(4,13),=A(LC1)
L 2,=F'32880'
AR 2,13
ST 2,92(13)
LA 1,88(,13)
L 15,=V(PRINTF)
BALR 14,15
L 2,=F'32768'
LA 3,64(0,0)
STC 3,120(2,13)
L 2,=F'32880'
AR 2,13
ST 2,88(13)
MVC 92(4,13),=F'64'
LA 1,88(,13)
L 15,=V(STRCHR)
BALR 14,15
MVI 0(15),0
ST 2,88(13)
MVC 92(4,13),=A(LC2)
LA 1,88(,13)
L 15,=V(STRCAT)
BALR 14,15
MVC 88(4,13),=A(LC3)
ST 2,92(13)
LA 1,88(,13)
L 15,=V(PRINTF)
BALR 14,15
L 3,0(11)
MVC 88(4,13),0(3)
MVC 92(4,13),=F'0'
MVC 96(4,13),=F'0'
MVC 100(4,13),=F'3'
LA 2,112(,13)
ST 2,104(13)
MVC 108(4,13),=F'32767'
LA 1,88(,13)
L 15,=V(RDBLOCK)
BALR 14,15
LR 6,15
LA 3,19(0,0)
CR 15,3
BNH L2
L 2,=F'33216'
AR 2,13
MVC 0(4,2),=F'0'
L 9,=F'33212'
AR 9,13
MVC 0(4,9),=F'0'
L 8,=F'33208'
AR 8,13
MVC 0(4,8),=F'0'
MVC 2(2,8),127(13)
MVC 2(2,9),129(13)
MVC 3(1,2),131(13)
B L3
L8 EQU *
LA 2,48(0,0)
CLR 6,2
BNH L5
L 3,=F'33040'
IC 2,156(3,13)
CLM 2,1,=XL1'F1'
BNE L5
LA 2,64(0,0)
STC 2,156(3,13)
L 3,=F'32880'
AR 3,13
ST 3,88(13)
LA 1,88(,13)
L 15,=V(STRLEN)
BALR 14,15
LA 4,112(,13)
A 4,=F'33040'
LR 5,15
LA 2,112(,13)
A 2,=F'32768'
LR 3,15
LA 15,1(0,0)
CLCL 4,2
BH *+12
BL *+6
SLR 15,15
LNR 15,15
LTR 15,15
BE L10
L5 EQU *
L 2,0(7)
A 2,=F'1'
ST 2,0(7)
L3 EQU *
L 3,0(11)
MVC 88(4,13),0(3)
MVC 92(4,13),0(8)
MVC 96(4,13),0(9)
L 7,=F'33216'
AR 7,13
MVC 100(4,13),0(7)
LR 2,13
A 2,=F'33152'
ST 2,104(13)
MVC 108(4,13),=F'49'
LA 1,88(,13)
L 15,=V(RDBLOCK)
BALR 14,15
LR 6,15
LTR 15,15
BH L8
L2 EQU *
SLR 15,15
LTR 6,6
BH L1
MVC 88(4,13),=A(LC4)
L 2,=F'32880'
AR 2,13
ST 2,92(13)
LA 1,88(,13)
L 15,=V(PRINTF)
BALR 14,15
ST 2,88(13)
MVC 92(4,13),=F'64'
LA 1,88(,13)
L 15,=V(STRCHR)
BALR 14,15
MVI 0(15),0
MVC 88(4,13),=A(LC5)
ST 2,92(13)
LA 1,88(,13)
L 15,=V(PRINTF)
BALR 14,15
L 15,=F'-1'
B L1
L10 EQU *
ST 15,0(9)
ST 15,0(8)
MVC 0(4,7),=F'1'
L 2,=F'33085'
LH 2,112(2,13)
STH 2,2(8)
L 2,=F'33087'
LH 2,112(2,13)
STH 2,2(9)
B L2
L1 EQU *
* Function pdosLoadExe epilogue
PDPEPIL
* Function pdosLoadExe literal pool
DS 0F
LTORG
* Function pdosLoadExe page table
DS 0F
PGT0 EQU *
DC A(PG0)
END
;; Function pdosLoadExe
;; 12 regs to allocate: 74 (2) 73 (2) 66 41 63 25 106 100 105 47 90 26
;; 25 conflicts: 25 41 11
;; 25 preferences: 15
;; 26 conflicts: 26 27 41 46 47 63 64 66 70 73 74 90 100 105 106 111 2 11 15
;; 27 conflicts: 26 27 47 90 2 11 15
;; 41 conflicts: 25 26 41 47 63 64 66 70 73 74 79 82 90 100 105 106 2 11 15
;; 46 conflicts: 26 46 47 90 2 11
;; 47 conflicts: 26 27 41 46 47 63 64 66 70 73 74 90 100 105 106 111 2 11 15
;; 63 conflicts: 26 41 47 63 64 90 100 105 106 2 11
;; 64 conflicts: 26 41 47 63 64 90 100 105 106 2 11
;; 66 conflicts: 26 41 47 66 73 74 90 100 105 106 11
;; 70 conflicts: 26 41 47 70 73 74 90 100 105 106 11 15
;; 73 conflicts: 26 41 47 66 70 73 74 90 100 105 106 11 15
;; 74 conflicts: 26 41 47 66 70 73 74 90 100 105 106 11 15
;; 79 conflicts: 41 79 100 105 2 11
;; 82 conflicts: 41 82 105 2 11
;; 84 conflicts: 84 2 11 15
;; 90 conflicts: 26 27 41 46 47 63 64 66 70 73 74 90 100 105 106 111 2 11 15
;; 100 conflicts: 26 41 47 63 64 66 70 73 74 79 90 100 105 106 111 2 11 15
;; 105 conflicts: 26 41 47 63 64 66 70 73 74 79 82 90 100 105 106 111 2 11
15
;; 106 conflicts: 26 41 47 63 64 66 70 73 74 90 100 105 106 2 11 15
;; 111 conflicts: 26 47 90 100 105 111 2 11
Spilling for insn 3.
Spilling for insn 4.
Spilling for insn 32.
Spilling for insn 33.
Spilling for insn 38.
Using reg 3 for reload 0
Using reg 3 for reload 1
Spilling for insn 41.
Spilling for insn 43.
Using reg 2 for reload 1
Spilling for insn 47.
Using reg 3 for reload 1
Spilling for insn 50.
Using reg 2 for reload 1
Spilling for insn 51.
Spilling for insn 54.
Spilling for insn 57.
Using reg 2 for reload 1
Spilling for insn 58.
Spilling for insn 61.
Spilling for insn 63.
Using reg 2 for reload 1
Spilling for insn 66.
Using reg 2 for reload 0
Spilling for insn 67.
Spilling for insn 68.
Spilling for insn 69.
Spilling for insn 70.
Using reg 2 for reload 1
Spilling for insn 71.
Spilling for insn 75.
Using reg 2 for reload 0
Spilling for insn 80.
Spilling for insn 81.
Spilling for insn 82.
Spilling for insn 86.
Spilling for insn 90.
Spilling for insn 94.
Spilling for insn 114.
Using reg 2 for reload 0
Spilling for insn 120.
Spilling for insn 127.
Using reg 2 for reload 1
Spilling for insn 132.
Using reg 2 for reload 1
Spilling for insn 139.
Spilling for insn 143.
Spilling for insn 173.
Using reg 2 for reload 0
Spilling for insn 98.
Using reg 2 for reload 0
Spilling for insn 99.
Spilling for insn 100.
Spilling for insn 101.
Spilling for insn 103.
Using reg 2 for reload 0
Spilling for insn 104.
Spilling for insn 189.
Spilling for insn 191.
Spilling for insn 195.
Spilling for insn 196.
Spilling for insn 199.
Spilling for insn 201.
Spilling for insn 203.
Spilling for insn 151.
Spilling for insn 152.
Spilling for insn 154.
Spilling for insn 159.
Spilling for insn 164.
Reloads for insn # 4
Reload 0: reload_in (SI) = (mem/f:SI (plus:SI (reg/f:SI 11 11)
(const_int 4 [0x4]))
[3 prog+0 S4 A32])
DATA_REGS, RELOAD_FOR_INPUT (opnum = 1), optional
reload_in_reg: (mem/f:SI (plus:SI (reg/f:SI 11 11)
(const_int 4 [0x4]))
[3 prog+0 S4 A32])
Reloads for insn # 32
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
Reloads for insn # 33
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
Reloads for insn # 38
Reload 0: reload_in (SI) = (const_int 32880 [0x8070])
ADDR_REGS, RELOAD_FOR_INPUT_ADDRESS (opnum = 0)
reload_in_reg: (const_int 32880 [0x8070])
reload_reg_rtx: (reg:SI 3 3)
Reload 1: reload_in (SI) = (plus:SI (reg/f:SI 13 13)
(const_int 32880
[0x8070]))
ADDR_REGS, RELOAD_FOR_INPUT (opnum = 0)
reload_in_reg: (plus:SI (reg/f:SI 13 13)
(const_int 32880
[0x8070]))
reload_reg_rtx: (reg:SI 3 3)
Reloads for insn # 41
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
Reloads for insn # 43
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
Reload 1: reload_in (SI) = (plus:SI (reg/f:SI 13 13)
(const_int 32880
[0x8070]))
ALL_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (plus:SI (reg/f:SI 13 13)
(const_int 32880
[0x8070]))
reload_reg_rtx: (reg:SI 2 2)
Reloads for insn # 47
Reload 0: reload_out (QI) = (mem/s:QI (plus:SI (plus:SI (reg/f:SI 13 13)
(reg:SI 2 2
[46]))
(const_int 120
[0x78])) [0 srchprog+8 S1 A64])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/s:QI (plus:SI (plus:SI (reg/f:SI 13 13)
(reg:SI 2 2
[46]))
(const_int 120
[0x78])) [0 srchprog+8 S1 A64])
Reload 1: reload_in (QI) = (const_int 64 [0x40])
ADDR_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (const_int 64 [0x40])
reload_reg_rtx: (reg:QI 3 3)
Reloads for insn # 50
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
Reload 1: reload_in (SI) = (plus:SI (reg/f:SI 13 13)
(const_int 32880
[0x8070]))
ALL_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (plus:SI (reg/f:SI 13 13)
(const_int 32880
[0x8070]))
reload_reg_rtx: (reg:SI 2 2)
Reloads for insn # 51
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
Reloads for insn # 54
Reload 0: reload_out (QI) = (mem:QI (reg:SI 15 15) [0 S1 A8])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem:QI (reg:SI 15 15) [0 S1 A8])
Reloads for insn # 57
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
Reload 1: reload_in (SI) = (plus:SI (reg/f:SI 13 13)
(const_int 32880
[0x8070]))
ALL_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (plus:SI (reg/f:SI 13 13)
(const_int 32880
[0x8070]))
reload_reg_rtx: (reg:SI 2 2)
Reloads for insn # 58
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
Reloads for insn # 61
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
Reloads for insn # 63
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
Reload 1: reload_in (SI) = (plus:SI (reg/f:SI 13 13)
(const_int 32880
[0x8070]))
ALL_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (plus:SI (reg/f:SI 13 13)
(const_int 32880
[0x8070]))
reload_reg_rtx: (reg:SI 2 2)
Reloads for insn # 66
Reload 0: reload_in (SI) = (reg/v/f:SI 26 [ pdos ])
ADDR_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum = 1)
reload_in_reg: (reg/v/f:SI 26 [ pdos ])
reload_reg_rtx: (reg:SI 3 3)
Reload 1: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
Reloads for insn # 67
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
Reloads for insn # 68
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 96
[0x60])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 96
[0x60])) [0 S4 A32])
Reloads for insn # 69
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 100
[0x64])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 100
[0x64])) [0 S4 A32])
Reloads for insn # 70
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 104
[0x68])) [0 S4 A32])
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 104
[0x68])) [0 S4 A32])
Reload 1: reload_in (SI) = (plus:SI (reg/f:SI 13 13)
(const_int 112 [0x70]))
ALL_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (plus:SI (reg/f:SI 13 13)
(const_int 112 [0x70]))
reload_reg_rtx: (reg:SI 2 2)
Reloads for insn # 71
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 108
[0x6c])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 108
[0x6c])) [0 S4 A32])
Reloads for insn # 75
Reload 0: reload_in (SI) = (const_int 19 [0x13])
ADDR_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (const_int 19 [0x13])
reload_reg_rtx: (reg:SI 3 3)
Reloads for insn # 80
Reload 0: reload_out (SI) = (mem/f:SI (reg/f:SI 2 2 [111]) [4 S4 A8])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (reg/f:SI 2 2 [111]) [4 S4 A8])
Reloads for insn # 81
Reload 0: reload_out (SI) = (mem/f:SI (reg/f:SI 9 9 [105]) [4 S4 A8])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (reg/f:SI 9 9 [105]) [4 S4 A8])
Reloads for insn # 82
Reload 0: reload_out (SI) = (mem/f:SI (reg/f:SI 8 8 [100]) [4 S4 A8])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (reg/f:SI 8 8 [100]) [4 S4 A8])
Reloads for insn # 86
Reload 0: reload_out (HI) = (mem:HI (plus:SI (reg/f:SI 8 8 [100])
(const_int 2 [0x2]))
[0 S2 A16])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem:HI (plus:SI (reg/f:SI 8 8 [100])
(const_int 2 [0x2]))
[0 S2 A16])
Reloads for insn # 90
Reload 0: reload_out (HI) = (mem:HI (plus:SI (reg/f:SI 9 9 [105])
(const_int 2 [0x2]))
[0 S2 A16])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem:HI (plus:SI (reg/f:SI 9 9 [105])
(const_int 2 [0x2]))
[0 S2 A16])
Reloads for insn # 94
Reload 0: reload_out (QI) = (mem:QI (plus:SI (reg/f:SI 2 2 [111])
(const_int 3 [0x3]))
[0 S1 A8])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem:QI (plus:SI (reg/f:SI 2 2 [111])
(const_int 3 [0x3]))
[0 S1 A8])
Reloads for insn # 114
Reload 0: reload_in (SI) = (const_int 48 [0x30])
ADDR_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (const_int 48 [0x30])
reload_reg_rtx: (reg:SI 2 2)
Reloads for insn # 120
Reload 0: reload_in (QI) = (mem/s:QI (plus:SI (plus:SI (reg/f:SI 13 13)
(reg:SI 3 3
[63]))
(const_int 156
[0x9c])) [0 dscb1.ds1fmtid+0 S1 A32])
DATA_REGS, RELOAD_FOR_INPUT (opnum = 1), optional
reload_in_reg: (mem/s:QI (plus:SI (plus:SI (reg/f:SI 13 13)
(reg:SI 3 3
[63]))
(const_int 156
[0x9c])) [0 dscb1.ds1fmtid+0 S1 A32])
Reloads for insn # 127
Reload 0: reload_out (QI) = (mem/s:QI (plus:SI (plus:SI (reg/f:SI 13 13)
(reg:SI 3 3
[63]))
(const_int 156
[0x9c])) [0 dscb1.ds1fmtid+0 S1 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/s:QI (plus:SI (plus:SI (reg/f:SI 13 13)
(reg:SI 3 3
[63]))
(const_int 156
[0x9c])) [0 dscb1.ds1fmtid+0 S1 A32])
Reload 1: reload_in (QI) = (const_int 64 [0x40])
ADDR_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (const_int 64 [0x40])
reload_reg_rtx: (reg:QI 2 2)
Reloads for insn # 132
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
Reload 1: reload_in (SI) = (plus:SI (reg/f:SI 13 13)
(const_int 32880
[0x8070]))
ALL_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (plus:SI (reg/f:SI 13 13)
(const_int 32880
[0x8070]))
reload_reg_rtx: (reg:SI 3 3)
Reloads for insn # 139
Reload 0: reload_in (SI) = (plus:SI (reg/f:SI 13 13)
(const_int 112 [0x70]))
reload_out (SI) = (reg:SI 4 4)
DATA_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (plus:SI (reg/f:SI 13 13)
(const_int 112 [0x70]))
reload_out_reg: (subreg:SI (reg:DI 4 4 [73]) 0)
reload_reg_rtx: (reg:SI 4 4)
Reloads for insn # 143
Reload 0: reload_in (SI) = (plus:SI (reg/f:SI 13 13)
(const_int 112 [0x70]))
reload_out (SI) = (reg:SI 2 2)
DATA_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (plus:SI (reg/f:SI 13 13)
(const_int 112 [0x70]))
reload_out_reg: (subreg:SI (reg:DI 2 2 [74]) 0)
reload_reg_rtx: (reg:SI 2 2)
Reloads for insn # 173
Reload 0: reload_in (SI) = (mem/f:SI (reg/f:SI 7 7 [106]) [4 rec+0 S4 A32])
reload_out (SI) = (mem/f:SI (reg/f:SI 7 7 [106]) [4 rec+0 S4 A32])
DATA_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (mem/f:SI (reg/f:SI 7 7 [106]) [4 rec+0 S4 A32])
reload_out_reg: (mem/f:SI (reg/f:SI 7 7 [106]) [4 rec+0 S4 A32])
reload_reg_rtx: (reg:SI 2 2)
Reloads for insn # 98
Reload 0: reload_in (SI) = (reg/v/f:SI 26 [ pdos ])
ADDR_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum = 1)
reload_in_reg: (reg/v/f:SI 26 [ pdos ])
reload_reg_rtx: (reg:SI 3 3)
Reload 1: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
Reloads for insn # 99
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
Reloads for insn # 100
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 96
[0x60])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 96
[0x60])) [0 S4 A32])
Reloads for insn # 101
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 100
[0x64])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 100
[0x64])) [0 S4 A32])
Reloads for insn # 103
Reload 0: reload_in (SI) = (reg/f:SI 13 13)
reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 104
[0x68])) [0 S4 A32])
DATA_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/f:SI 13 13)
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 104
[0x68])) [0 S4 A32])
reload_reg_rtx: (reg:SI 2 2)
Reloads for insn # 104
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 108
[0x6c])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 108
[0x6c])) [0 S4 A32])
Reloads for insn # 189
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
Reloads for insn # 191
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
Reloads for insn # 195
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
Reloads for insn # 196
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
Reloads for insn # 199
Reload 0: reload_out (QI) = (mem:QI (reg:SI 15 15) [0 S1 A8])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem:QI (reg:SI 15 15) [0 S1 A8])
Reloads for insn # 201
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88
[0x58])) [0 S4 A32])
Reloads for insn # 203
Reload 0: reload_out (SI) = (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92
[0x5c])) [0 S4 A32])
Reloads for insn # 151
Reload 0: reload_out (SI) = (mem/f:SI (reg/f:SI 9 9 [105]) [4 head+0 S4
A32])
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (reg/f:SI 9 9 [105]) [4 head+0 S4 A32])
Reloads for insn # 152
Reload 0: reload_out (SI) = (mem/f:SI (reg/f:SI 8 8 [100]) [4 cyl+0 S4 A32])
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (reg/f:SI 8 8 [100]) [4 cyl+0 S4 A32])
Reloads for insn # 154
Reload 0: reload_out (SI) = (mem/f:SI (reg/f:SI 7 7 [106]) [4 rec+0 S4 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:SI (reg/f:SI 7 7 [106]) [4 rec+0 S4 A32])
Reloads for insn # 159
Reload 0: reload_out (HI) = (mem:HI (plus:SI (reg/f:SI 8 8 [100])
(const_int 2 [0x2]))
[0 S2 A16])
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
reload_out_reg: (mem:HI (plus:SI (reg/f:SI 8 8 [100])
(const_int 2 [0x2]))
[0 S2 A16])
reload_reg_rtx: (reg:HI 2 2)
Reload 1: reload_in (HI) = (mem:HI (plus:SI (plus:SI (reg/f:SI 13 13)
(reg:SI 2 2
[79]))
(const_int 112
[0x70])) [0 S2 A8])
DATA_REGS, RELOAD_FOR_INPUT (opnum = 1), optional
reload_in_reg: (mem:HI (plus:SI (plus:SI (reg/f:SI 13 13)
(reg:SI 2 2
[79]))
(const_int 112
[0x70])) [0 S2 A8])
Reloads for insn # 164
Reload 0: reload_out (HI) = (mem:HI (plus:SI (reg/f:SI 9 9 [105])
(const_int 2 [0x2]))
[0 S2 A16])
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
reload_out_reg: (mem:HI (plus:SI (reg/f:SI 9 9 [105])
(const_int 2 [0x2]))
[0 S2 A16])
reload_reg_rtx: (reg:HI 2 2)
Reload 1: reload_in (HI) = (mem:HI (plus:SI (plus:SI (reg/f:SI 13 13)
(reg:SI 2 2
[82]))
(const_int 112
[0x70])) [0 S2 A8])
DATA_REGS, RELOAD_FOR_INPUT (opnum = 1), optional
reload_in_reg: (mem:HI (plus:SI (plus:SI (reg/f:SI 13 13)
(reg:SI 2 2
[82]))
(const_int 112
[0x70])) [0 S2 A8])
;; Register dispositions:
25 in 15 27 in 2 41 in 6 46 in 2 63 in 3 64 in 2
66 in 15 70 in 15 73 in 4 74 in 2 79 in 2 82 in 2
84 in 2 100 in 8 105 in 9 106 in 7 111 in 2
;; Hard regs used: 2 3 4 5 6 7 8 9 11 13 15
(note 2 0 227 NOTE_INSN_DELETED)
;; Start of basic block 0, registers live: 11 [11] 13 [13]
(note 227 2 3 0 [bb 0] NOTE_INSN_BASIC_BLOCK)
(note 3 227 4 0 NOTE_INSN_DELETED)
(insn 4 3 6 0 (set (reg/v/f:SI 2 2 [orig:27 prog ] [27])
(mem/f:SI (plus:SI (reg/f:SI 11 11)
(const_int 4 [0x4])) [3 prog+0 S4 A32])) 15 {movsi} (nil)
(expr_list:REG_EQUIV (mem/f:SI (plus:SI (reg/f:SI 11 11)
(const_int 4 [0x4])) [3 prog+0 S4 A32])
(nil)))
(note 6 4 32 0 NOTE_INSN_FUNCTION_BEG)
(insn 32 6 33 0 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88 [0x58])) [0 S4 A32])
(symbol_ref/f:SI ("*LC0") [flags 0x2] <string_cst 7d494c>)) 15
{movsi} (nil)
(nil))
(insn 33 32 34 0 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92 [0x5c])) [0 S4 A32])
(reg/v/f:SI 2 2 [orig:27 prog ] [27])) 15 {movsi} (insn_list 4
(nil))
(nil))
(call_insn 34 33 244 0 (set (reg:SI 15 15)
(call (mem:QI (symbol_ref/v:SI ("printf") [flags 0x41]
<function_decl 7729b4 printf>) [0 S1 A8])
(const_int 8 [0x8]))) 132 {*i370.md:4869} (nil)
(nil)
(nil))
(note 244 34 37 0 NOTE_INSN_DELETED)
(note 37 244 271 0 NOTE_INSN_DELETED)
(insn 271 37 273 0 (set (reg:SI 3 3)
(const_int 32880 [0x8070])) 15 {movsi} (nil)
(nil))
(insn 273 271 274 0 (set (reg:SI 3 3)
(reg/f:SI 13 13)) 15 {movsi} (nil)
(nil))
(insn 274 273 38 0 (set (reg:SI 3 3)
(plus:SI (reg:SI 3 3)
(reg:SI 3 3))) 41 {addsi3} (nil)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 13 13)
(reg:SI 3 3))
(nil)))
(insn 38 274 41 0 (parallel [
(set (mem/s:BLK (reg:SI 3 3) [6 srchprog+0 S10 A64])
(mem:BLK (reg/v/f:SI 2 2 [orig:27 prog ] [27]) [0 S10 A8]))
(use (const_int 10 [0xa]))
]) 25 {*i370.md:1623} (insn_list 37 (nil))
(nil))
(insn 41 38 275 0 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88 [0x58])) [0 S4 A32])
(symbol_ref/f:SI ("*LC1") [flags 0x2] <string_cst 7d49d8>)) 15
{movsi} (nil)
(nil))
(insn 275 41 43 0 (set (reg:SI 2 2)
(plus:SI (reg/f:SI 13 13)
(const_int 32880 [0x8070]))) 40 {*i370.md:2127} (nil)
(nil))
(insn 43 275 44 0 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92 [0x5c])) [0 S4 A32])
(reg:SI 2 2)) 15 {movsi} (nil)
(nil))
(call_insn 44 43 269 0 (set (reg:SI 15 15)
(call (mem:QI (symbol_ref/v:SI ("printf") [flags 0x41]
<function_decl 7729b4 printf>) [0 S1 A8])
(const_int 8 [0x8]))) 132 {*i370.md:4869} (nil)
(nil)
(nil))
(insn 269 44 276 0 (set (reg:SI 2 2 [46])
(const_int 32768 [0x8000])) 15 {movsi} (nil)
(expr_list:REG_EQUIV (const_int 32768 [0x8000])
(nil)))
(insn 276 269 47 0 (set (reg:QI 3 3)
(const_int 64 [0x40])) 18 {*i370.md:1098} (nil)
(nil))
(insn 47 276 277 0 (set (mem/s:QI (plus:SI (plus:SI (reg/f:SI 13 13)
(reg:SI 2 2 [46]))
(const_int 120 [0x78])) [0 srchprog+8 S1 A64])
(reg:QI 3 3)) 19 {movqi} (insn_list 36 (nil))
(nil))
(insn 277 47 50 0 (set (reg:SI 2 2)
(plus:SI (reg/f:SI 13 13)
(const_int 32880 [0x8070]))) 40 {*i370.md:2127} (nil)
(nil))
(insn 50 277 51 0 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88 [0x58])) [0 S4 A32])
(reg:SI 2 2)) 15 {movsi} (nil)
(nil))
(insn 51 50 52 0 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92 [0x5c])) [0 S4 A32])
(const_int 64 [0x40])) 15 {movsi} (nil)
(nil))
(call_insn 52 51 53 0 (set (reg:SI 15 15)
(call (mem:QI (symbol_ref/v:SI ("strchr") [flags 0x41]
<function_decl 7b3654 strchr>) [0 S1 A8])
(const_int 8 [0x8]))) 132 {*i370.md:4869} (nil)
(nil)
(nil))
(note 53 52 54 0 NOTE_INSN_DELETED)
(insn 54 53 57 0 (set (mem:QI (reg:SI 15 15) [0 S1 A8])
(const_int 0 [0x0])) 18 {*i370.md:1098} (insn_list 52 (nil))
(nil))
(insn 57 54 58 0 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88 [0x58])) [0 S4 A32])
(reg:SI 2 2)) 15 {movsi} (nil)
(nil))
(insn 58 57 59 0 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92 [0x5c])) [0 S4 A32])
(symbol_ref/f:SI ("*LC2") [flags 0x2] <string_cst 7d4a8c>)) 15
{movsi} (nil)
(nil))
(call_insn 59 58 61 0 (set (reg:SI 15 15)
(call (mem:QI (symbol_ref/v:SI ("strcat") [flags 0x41]
<function_decl 7b1654 strcat>) [0 S1 A8])
(const_int 8 [0x8]))) 132 {*i370.md:4869} (nil)
(nil)
(nil))
(insn 61 59 63 0 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88 [0x58])) [0 S4 A32])
(symbol_ref/f:SI ("*LC3") [flags 0x2] <string_cst 7d4adc>)) 15
{movsi} (nil)
(nil))
(insn 63 61 64 0 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92 [0x5c])) [0 S4 A32])
(reg:SI 2 2)) 15 {movsi} (nil)
(nil))
(call_insn 64 63 278 0 (set (reg:SI 15 15)
(call (mem:QI (symbol_ref/v:SI ("printf") [flags 0x41]
<function_decl 7729b4 printf>) [0 S1 A8])
(const_int 8 [0x8]))) 132 {*i370.md:4869} (nil)
(nil)
(nil))
(insn 278 64 66 0 (set (reg:SI 3 3)
(mem/f:SI (reg/f:SI 11 11) [2 pdos+0 S4 A32])) 15 {movsi} (nil)
(nil))
(insn 66 278 67 0 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88 [0x58])) [0 S4 A32])
(mem/s:SI (reg:SI 3 3) [4 <variable>.ipldev+0 S4 A32])) 15 {movsi}
(insn_list 3 (nil))
(nil))
(insn 67 66 68 0 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92 [0x5c])) [0 S4 A32])
(const_int 0 [0x0])) 15 {movsi} (nil)
(nil))
(insn 68 67 69 0 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 96 [0x60])) [0 S4 A32])
(const_int 0 [0x0])) 15 {movsi} (nil)
(nil))
(insn 69 68 279 0 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 100 [0x64])) [0 S4 A32])
(const_int 3 [0x3])) 15 {movsi} (nil)
(nil))
(insn 279 69 70 0 (set (reg:SI 2 2)
(plus:SI (reg/f:SI 13 13)
(const_int 112 [0x70]))) 39 {*i370.md:2110} (nil)
(nil))
(insn 70 279 71 0 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 104 [0x68])) [0 S4 A32])
(reg:SI 2 2)) 15 {movsi} (insn_list 244 (nil))
(nil))
(insn 71 70 72 0 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 108 [0x6c])) [0 S4 A32])
(const_int 32767 [0x7fff])) 15 {movsi} (nil)
(nil))
(call_insn 72 71 73 0 (set (reg:SI 15 15)
(call (mem:QI (symbol_ref/v:SI ("rdblock") [flags 0x41]
<function_decl 7bb21c rdblock>) [0 S1 A8])
(const_int 24 [0x18]))) 132 {*i370.md:4869} (nil)
(nil)
(nil))
(insn 73 72 280 0 (set (reg/v:SI 6 6 [orig:41 cnt ] [41])
(reg:SI 15 15)) 15 {movsi} (insn_list 72 (nil))
(nil))
(insn 280 73 75 0 (set (reg:SI 3 3)
(const_int 19 [0x13])) 15 {movsi} (nil)
(nil))
(insn:QI 75 280 76 0 (set (cc0)
(compare (reg/v:SI 6 6 [orig:41 cnt ] [41])
(reg:SI 3 3))) 5 {cmpsi} (insn_list 73 (nil))
(nil))
(jump_insn 76 75 228 0 (set (pc)
(if_then_else (le (cc0)
(const_int 0 [0x0]))
(label_ref 182)
(pc))) 112 {ble} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 0, registers live:
11 [11] 13 [13] 26 41 47 90
;; Start of basic block 1, registers live: 11 [11] 13 [13] 26 47 90
(note 228 76 265 1 [bb 1] NOTE_INSN_BASIC_BLOCK)
(insn 265 228 80 1 (set (reg/f:SI 2 2 [111])
(plus:SI (reg/f:SI 13 13)
(const_int 33216 [0x81c0]))) 40 {*i370.md:2127} (nil)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 13 13)
(const_int 33216 [0x81c0]))
(nil)))
(insn 80 265 259 1 (set (mem/f:SI (reg/f:SI 2 2 [111]) [4 S4 A8])
(const_int 0 [0x0])) 15 {movsi} (insn_list 265 (nil))
(nil))
(insn 259 80 81 1 (set (reg/f:SI 9 9 [105])
(plus:SI (reg/f:SI 13 13)
(const_int 33212 [0x81bc]))) 40 {*i370.md:2127} (nil)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 13 13)
(const_int 33212 [0x81bc]))
(nil)))
(insn 81 259 254 1 (set (mem/f:SI (reg/f:SI 9 9 [105]) [4 S4 A8])
(const_int 0 [0x0])) 15 {movsi} (insn_list 259 (nil))
(nil))
(insn 254 81 82 1 (set (reg/f:SI 8 8 [100])
(plus:SI (reg/f:SI 13 13)
(const_int 33208 [0x81b8]))) 40 {*i370.md:2127} (nil)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 13 13)
(const_int 33208 [0x81b8]))
(nil)))
(insn 82 254 85 1 (set (mem/f:SI (reg/f:SI 8 8 [100]) [4 S4 A8])
(const_int 0 [0x0])) 15 {movsi} (insn_list 254 (nil))
(nil))
(note 85 82 86 1 NOTE_INSN_DELETED)
(insn 86 85 89 1 (set (mem:HI (plus:SI (reg/f:SI 8 8 [100])
(const_int 2 [0x2])) [0 S2 A16])
(mem:HI (plus:SI (reg/f:SI 13 13)
(const_int 127 [0x7f])) [0 S2 A8])) 16 {*i370.md:1004} (nil)
(nil))
(note 89 86 90 1 NOTE_INSN_DELETED)
(insn 90 89 93 1 (set (mem:HI (plus:SI (reg/f:SI 9 9 [105])
(const_int 2 [0x2])) [0 S2 A16])
(mem:HI (plus:SI (reg/f:SI 13 13)
(const_int 129 [0x81])) [0 S2 A8])) 16 {*i370.md:1004} (nil)
(nil))
(note 93 90 94 1 NOTE_INSN_DELETED)
(insn 94 93 96 1 (set (mem:QI (plus:SI (reg/f:SI 2 2 [111])
(const_int 3 [0x3])) [0 S1 A8])
(mem:QI (plus:SI (reg/f:SI 13 13)
(const_int 131 [0x83])) [0 S1 A8])) 18 {*i370.md:1098} (nil)
(nil))
(note 96 94 176 1 NOTE_INSN_LOOP_BEG)
(jump_insn 176 96 177 1 (set (pc)
(label_ref 97)) 126 {jump} (nil)
(nil))
;; End of basic block 1, registers live:
11 [11] 13 [13] 26 47 90 100 105
(barrier 177 176 175)
;; Start of basic block 2, registers live: 11 [11] 13 [13] 26 41 47 90 100
105 106
(code_label 175 177 229 2 8 "" [1 uses])
(note 229 175 281 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 281 229 114 2 (set (reg:SI 2 2)
(const_int 48 [0x30])) 15 {movsi} (nil)
(nil))
(insn:QI 114 281 115 2 (set (cc0)
(compare (reg/v:SI 6 6 [orig:41 cnt ] [41])
(reg:SI 2 2))) 5 {cmpsi} (nil)
(nil))
(jump_insn 115 114 230 2 (set (pc)
(if_then_else (leu (cc0)
(const_int 0 [0x0]))
(label_ref 170)
(pc))) 113 {bleu} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 2, registers live:
11 [11] 13 [13] 26 41 47 90 100 105 106
;; Start of basic block 3, registers live: 11 [11] 13 [13] 26 41 47 90 100
105 106
(note 230 115 119 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 119 230 120 3 (set (reg:SI 3 3 [63])
(const_int 33040 [0x8110])) 15 {movsi} (nil)
(expr_list:REG_EQUIV (const_int 33040 [0x8110])
(nil)))
(insn 120 119 121 3 (set (reg:QI 2 2 [orig:64 dscb1.ds1fmtid ] [64])
(mem/s:QI (plus:SI (plus:SI (reg/f:SI 13 13)
(reg:SI 3 3 [63]))
(const_int 156 [0x9c])) [0 dscb1.ds1fmtid+0 S1 A32])) 18
{*i370.md:1098} (insn_list 119 (nil))
(expr_list:REG_EQUIV (mem/s:QI (plus:SI (plus:SI (reg/f:SI 13 13)
(reg:SI 3 3 [63]))
(const_int 156 [0x9c])) [0 dscb1.ds1fmtid+0 S1 A32])
(expr_list:REG_EQUAL (mem/s:QI (plus:SI (reg/f:SI 13 13)
(const_int 33196 [0x81ac])) [0 dscb1.ds1fmtid+0 S1 A32])
(nil))))
(insn:QI 121 120 122 3 (set (cc0)
(compare (reg:QI 2 2 [orig:64 dscb1.ds1fmtid ] [64])
(const_int -15 [0xfffffff1]))) 7 {*i370.md:517} (insn_list 120
(nil))
(nil))
(jump_insn 122 121 231 3 (set (pc)
(if_then_else (ne (cc0)
(const_int 0 [0x0]))
(label_ref 170)
(pc))) 105 {bne} (nil)
(expr_list:REG_BR_PROB (const_int 8510 [0x213e])
(nil)))
;; End of basic block 3, registers live:
11 [11] 13 [13] 26 41 47 63 90 100 105 106
;; Start of basic block 4, registers live: 11 [11] 13 [13] 26 41 47 63 90
100 105 106
(note 231 122 282 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn 282 231 127 4 (set (reg:QI 2 2)
(const_int 64 [0x40])) 18 {*i370.md:1098} (nil)
(nil))
(insn 127 282 283 4 (set (mem/s:QI (plus:SI (plus:SI (reg/f:SI 13 13)
(reg:SI 3 3 [63]))
(const_int 156 [0x9c])) [0 dscb1.ds1fmtid+0 S1 A32])
(reg:QI 2 2)) 19 {movqi} (nil)
(nil))
(insn 283 127 132 4 (set (reg:SI 3 3)
(plus:SI (reg/f:SI 13 13)
(const_int 32880 [0x8070]))) 40 {*i370.md:2127} (nil)
(nil))
(insn 132 283 133 4 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88 [0x58])) [0 S4 A32])
(reg:SI 3 3)) 15 {movsi} (nil)
(nil))
(call_insn 133 132 134 4 (set (reg:SI 15 15)
(call (mem:QI (symbol_ref/v:SI ("strlen") [flags 0x41]
<function_decl 7b557c strlen>) [0 S1 A8])
(const_int 8 [0x8]))) 132 {*i370.md:4869} (nil)
(nil)
(nil))
(insn 134 133 284 4 (set (reg:SI 15 15 [70])
(reg:SI 15 15)) 15 {movsi} (insn_list 133 (nil))
(nil))
(insn 284 134 139 4 (set (reg:SI 4 4)
(plus:SI (reg/f:SI 13 13)
(const_int 112 [0x70]))) 39 {*i370.md:2110} (nil)
(nil))
(insn 139 284 285 4 (set (reg:SI 4 4)
(plus:SI (reg:SI 4 4)
(const_int 33040 [0x8110]))) 41 {addsi3} (insn_list 137 (nil))
(nil))
(insn 285 139 140 4 (set (reg:SI 4 4)
(reg:SI 4 4)) 15 {movsi} (nil)
(nil))
(insn 140 285 286 4 (set (reg:SI 5 5 [orig:73+4 ] [73])
(reg:SI 15 15 [70])) 15 {movsi} (insn_list 134 (insn_list 139
(nil)))
(nil))
(insn 286 140 143 4 (set (reg:SI 2 2)
(plus:SI (reg/f:SI 13 13)
(const_int 112 [0x70]))) 39 {*i370.md:2110} (nil)
(nil))
(insn 143 286 287 4 (set (reg:SI 2 2)
(plus:SI (reg:SI 2 2)
(const_int 32768 [0x8000]))) 41 {addsi3} (insn_list 141 (nil))
(nil))
(insn 287 143 144 4 (set (reg:SI 2 2)
(reg:SI 2 2)) 15 {movsi} (nil)
(nil))
(insn 144 287 145 4 (set (reg:SI 3 3 [orig:74+4 ] [74])
(reg:SI 15 15 [70])) 15 {movsi} (insn_list 143 (nil))
(nil))
(insn 145 144 146 4 (parallel [
(set (reg:SI 15 15 [66])
(compare:SI (mem:BLK (reg:DI 4 4 [73]) [0 A8])
(mem:BLK (reg:DI 2 2 [74]) [0 A8])))
(use (reg:DI 4 4 [73]))
(use (reg:DI 2 2 [74]))
(clobber (reg:DI 4 4 [73]))
(clobber (reg:DI 2 2 [74]))
]) 12 {cmpmemsi_1} (insn_list 140 (insn_list 144 (nil)))
(nil))
(insn:QI 146 145 147 4 (set (cc0)
(reg:SI 15 15 [66])) 1 {tstsi} (insn_list 145 (nil))
(nil))
(jump_insn 147 146 170 4 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref/s 268)
(pc))) 104 {beq} (nil)
(expr_list:REG_BR_PROB (const_int 500 [0x1f4])
(nil)))
;; End of basic block 4, registers live:
11 [11] 13 [13] 26 41 47 66 90 100 105 106
;; Start of basic block 5, registers live: 11 [11] 13 [13] 26 47 90 100 105
106
(code_label 170 147 235 5 5 "" [2 uses])
(note 235 170 172 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(note 172 235 288 5 NOTE_INSN_DELETED)
(insn 288 172 173 5 (set (reg:SI 2 2)
(mem/f:SI (reg/f:SI 7 7 [106]) [4 rec+0 S4 A32])) 15 {movsi} (nil)
(nil))
(insn 173 288 289 5 (set (reg:SI 2 2)
(plus:SI (reg:SI 2 2)
(const_int 1 [0x1]))) 41 {addsi3} (nil)
(nil))
(insn 289 173 174 5 (set (mem/f:SI (reg/f:SI 7 7 [106]) [4 rec+0 S4 A32])
(reg:SI 2 2)) 15 {movsi} (nil)
(nil))
;; End of basic block 5, registers live:
11 [11] 13 [13] 26 47 90 100 105
(note 174 289 97 NOTE_INSN_LOOP_CONT)
;; Start of basic block 6, registers live: 11 [11] 13 [13] 26 47 90 100 105
(code_label 97 174 236 6 3 "" [1 uses])
(note 236 97 290 6 [bb 6] NOTE_INSN_BASIC_BLOCK)
(insn 290 236 98 6 (set (reg:SI 3 3)
(mem/f:SI (reg/f:SI 11 11) [2 pdos+0 S4 A32])) 15 {movsi} (nil)
(nil))
(insn 98 290 99 6 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88 [0x58])) [0 S4 A32])
(mem/s:SI (reg:SI 3 3) [4 <variable>.ipldev+0 S4 A32])) 15 {movsi}
(nil)
(nil))
(insn 99 98 100 6 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92 [0x5c])) [0 S4 A32])
(mem/f:SI (reg/f:SI 8 8 [100]) [4 cyl+0 S4 A32])) 15 {movsi} (nil)
(nil))
(insn 100 99 260 6 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 96 [0x60])) [0 S4 A32])
(mem/f:SI (reg/f:SI 9 9 [105]) [4 head+0 S4 A32])) 15 {movsi} (nil)
(nil))
(insn 260 100 101 6 (set (reg/f:SI 7 7 [106])
(plus:SI (reg/f:SI 13 13)
(const_int 33216 [0x81c0]))) 40 {*i370.md:2127} (nil)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 13 13)
(const_int 33216 [0x81c0]))
(nil)))
(insn 101 260 291 6 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 100 [0x64])) [0 S4 A32])
(mem/f:SI (reg/f:SI 7 7 [106]) [4 rec+0 S4 A32])) 15 {movsi}
(insn_list 260 (nil))
(nil))
(insn 291 101 103 6 (set (reg:SI 2 2)
(reg/f:SI 13 13)) 15 {movsi} (nil)
(nil))
(insn 103 291 292 6 (set (reg:SI 2 2)
(plus:SI (reg:SI 2 2)
(const_int 33152 [0x8180]))) 41 {addsi3} (nil)
(nil))
(insn 292 103 104 6 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 104 [0x68])) [0 S4 A32])
(reg:SI 2 2)) 15 {movsi} (nil)
(nil))
(insn 104 292 105 6 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 108 [0x6c])) [0 S4 A32])
(const_int 49 [0x31])) 15 {movsi} (nil)
(nil))
(call_insn 105 104 106 6 (set (reg:SI 15 15)
(call (mem:QI (symbol_ref/v:SI ("rdblock") [flags 0x41]
<function_decl 7bb21c rdblock>) [0 S1 A8])
(const_int 24 [0x18]))) 132 {*i370.md:4869} (nil)
(nil)
(nil))
(insn 106 105 108 6 (set (reg/v:SI 6 6 [orig:41 cnt ] [41])
(reg:SI 15 15)) 15 {movsi} (insn_list 105 (nil))
(nil))
(insn:QI 108 106 109 6 (set (cc0)
(reg/v:SI 6 6 [orig:41 cnt ] [41])) 1 {tstsi} (insn_list 106 (nil))
(nil))
(jump_insn 109 108 180 6 (set (pc)
(if_then_else (le (cc0)
(const_int 0 [0x0]))
(pc)
(label_ref 175))) 122 {*i370.md:4516} (nil)
(expr_list:REG_BR_PROB (const_int 9500 [0x251c])
(nil)))
;; End of basic block 6, registers live:
11 [11] 13 [13] 26 41 47 90 100 105 106
(note 180 109 182 NOTE_INSN_LOOP_END)
;; Start of basic block 7, registers live: 11 [11] 13 [13] 41
(code_label 182 180 239 7 2 "" [2 uses])
(note 239 182 216 7 [bb 7] NOTE_INSN_BASIC_BLOCK)
(insn 216 239 184 7 (set (reg:SI 15 15 [orig:25 <result> ] [25])
(const_int 0 [0x0])) 15 {movsi} (nil)
(nil))
(insn:QI 184 216 185 7 (set (cc0)
(reg/v:SI 6 6 [orig:41 cnt ] [41])) 1 {tstsi} (nil)
(nil))
(jump_insn 185 184 240 7 (set (pc)
(if_then_else (gt (cc0)
(const_int 0 [0x0]))
(label_ref 222)
(pc))) 106 {bgt} (nil)
(expr_list:REG_BR_PROB (const_int 9953 [0x26e1])
(nil)))
;; End of basic block 7, registers live:
11 [11] 13 [13] 25
;; Start of basic block 8, registers live: 11 [11] 13 [13]
(note 240 185 189 8 [bb 8] NOTE_INSN_BASIC_BLOCK)
(insn 189 240 190 8 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88 [0x58])) [0 S4 A32])
(symbol_ref/f:SI ("*LC4") [flags 0x2] <string_cst 7d4d48>)) 15
{movsi} (nil)
(nil))
(insn 190 189 191 8 (set (reg/f:SI 2 2 [84])
(plus:SI (reg/f:SI 13 13)
(const_int 32880 [0x8070]))) 40 {*i370.md:2127} (nil)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 13 13)
(const_int 32880 [0x8070]))
(nil)))
(insn 191 190 192 8 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92 [0x5c])) [0 S4 A32])
(reg/f:SI 2 2 [84])) 15 {movsi} (insn_list 190 (nil))
(nil))
(call_insn 192 191 195 8 (set (reg:SI 15 15)
(call (mem:QI (symbol_ref/v:SI ("printf") [flags 0x41]
<function_decl 7729b4 printf>) [0 S1 A8])
(const_int 8 [0x8]))) 132 {*i370.md:4869} (nil)
(nil)
(nil))
(insn 195 192 196 8 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88 [0x58])) [0 S4 A32])
(reg/f:SI 2 2 [84])) 15 {movsi} (nil)
(nil))
(insn 196 195 197 8 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92 [0x5c])) [0 S4 A32])
(const_int 64 [0x40])) 15 {movsi} (nil)
(nil))
(call_insn 197 196 198 8 (set (reg:SI 15 15)
(call (mem:QI (symbol_ref/v:SI ("strchr") [flags 0x41]
<function_decl 7b3654 strchr>) [0 S1 A8])
(const_int 8 [0x8]))) 132 {*i370.md:4869} (nil)
(nil)
(nil))
(note 198 197 199 8 NOTE_INSN_DELETED)
(insn 199 198 201 8 (set (mem:QI (reg:SI 15 15) [0 S1 A8])
(const_int 0 [0x0])) 18 {*i370.md:1098} (insn_list 197 (nil))
(nil))
(insn 201 199 203 8 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 88 [0x58])) [0 S4 A32])
(symbol_ref/f:SI ("*LC5") [flags 0x2] <string_cst 7d4d98>)) 15
{movsi} (nil)
(nil))
(insn 203 201 204 8 (set (mem/f:SI (plus:SI (reg/f:SI 13 13)
(const_int 92 [0x5c])) [0 S4 A32])
(reg/f:SI 2 2 [84])) 15 {movsi} (nil)
(nil))
(call_insn 204 203 209 8 (set (reg:SI 15 15)
(call (mem:QI (symbol_ref/v:SI ("printf") [flags 0x41]
<function_decl 7729b4 printf>) [0 S1 A8])
(const_int 8 [0x8]))) 132 {*i370.md:4869} (nil)
(nil)
(nil))
(insn 209 204 210 8 (set (reg:SI 15 15 [orig:25 <result> ] [25])
(const_int -1 [0xffffffff])) 15 {movsi} (nil)
(expr_list:REG_EQUAL (const_int -1 [0xffffffff])
(nil)))
(jump_insn 210 209 211 8 (set (pc)
(label_ref 222)) 126 {jump} (nil)
(nil))
;; End of basic block 8, registers live:
11 [11] 13 [13] 25
(barrier 211 210 268)
;; Start of basic block 9, registers live: 11 [11] 13 [13] 41 66 100 105 106
(code_label 268 211 232 9 10 "" [1 uses])
(note 232 268 151 9 [bb 9] NOTE_INSN_BASIC_BLOCK)
(insn 151 232 152 9 (set (mem/f:SI (reg/f:SI 9 9 [105]) [4 head+0 S4 A32])
(reg:SI 15 15 [66])) 15 {movsi} (nil)
(nil))
(insn 152 151 154 9 (set (mem/f:SI (reg/f:SI 8 8 [100]) [4 cyl+0 S4 A32])
(reg:SI 15 15 [66])) 15 {movsi} (nil)
(nil))
(insn 154 152 157 9 (set (mem/f:SI (reg/f:SI 7 7 [106]) [4 rec+0 S4 A32])
(const_int 1 [0x1])) 15 {movsi} (nil)
(nil))
(note 157 154 158 9 NOTE_INSN_DELETED)
(insn 158 157 159 9 (set (reg:SI 2 2 [79])
(const_int 33085 [0x813d])) 15 {movsi} (nil)
(expr_list:REG_EQUIV (const_int 33085 [0x813d])
(nil)))
(insn 159 158 293 9 (set (reg:HI 2 2)
(mem:HI (plus:SI (plus:SI (reg/f:SI 13 13)
(reg:SI 2 2 [79]))
(const_int 112 [0x70])) [0 S2 A8])) 16 {*i370.md:1004}
(insn_list 158 (nil))
(nil))
(insn 293 159 162 9 (set (mem:HI (plus:SI (reg/f:SI 8 8 [100])
(const_int 2 [0x2])) [0 S2 A16])
(reg:HI 2 2)) 16 {*i370.md:1004} (nil)
(nil))
(note 162 293 163 9 NOTE_INSN_DELETED)
(insn 163 162 164 9 (set (reg:SI 2 2 [82])
(const_int 33087 [0x813f])) 15 {movsi} (nil)
(expr_list:REG_EQUIV (const_int 33087 [0x813f])
(nil)))
(insn 164 163 294 9 (set (reg:HI 2 2)
(mem:HI (plus:SI (plus:SI (reg/f:SI 13 13)
(reg:SI 2 2 [82]))
(const_int 112 [0x70])) [0 S2 A8])) 16 {*i370.md:1004}
(insn_list 163 (nil))
(nil))
(insn 294 164 166 9 (set (mem:HI (plus:SI (reg/f:SI 9 9 [105])
(const_int 2 [0x2])) [0 S2 A16])
(reg:HI 2 2)) 16 {*i370.md:1004} (nil)
(nil))
(jump_insn 166 294 167 9 (set (pc)
(label_ref 182)) 126 {jump} (nil)
(nil))
;; End of basic block 9, registers live:
11 [11] 13 [13] 41
(barrier 167 166 220)
(note 220 167 222 NOTE_INSN_FUNCTION_END)
;; Start of basic block 10, registers live: 11 [11] 13 [13] 25
(code_label 222 220 243 10 1 "" [2 uses])
(note 243 222 223 10 [bb 10] NOTE_INSN_BASIC_BLOCK)
(insn 223 243 226 10 (set (reg/i:SI 15 15 [ <result> ])
(reg:SI 15 15 [orig:25 <result> ] [25])) 15 {movsi} (nil)
(nil))
(insn 226 223 270 10 (use (reg/i:SI 15 15 [ <result> ])) -1 (insn_list 223
(nil))
(nil))
;; End of basic block 10, registers live:
11 [11] 13 [13] 15 [15]
(note 270 226 0 NOTE_INSN_DELETED)
next prev parent reply other threads:[~2011-08-16 11:20 UTC|newest]
Thread overview: 162+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-09-09 22:33 Paul Edwards
2009-09-14 15:42 ` Ulrich Weigand
2009-09-15 12:59 ` Paul Edwards
2009-09-15 13:51 ` Ulrich Weigand
2009-09-17 13:00 ` Paul Edwards
2009-09-17 17:55 ` Ulrich Weigand
2009-09-18 0:35 ` Paul Edwards
2009-09-18 12:06 ` Ulrich Weigand
2009-09-18 12:23 ` Paul Edwards
2009-09-18 13:27 ` Ulrich Weigand
2009-09-18 13:42 ` Paul Edwards
2009-09-18 16:08 ` Ulrich Weigand
2009-09-19 12:57 ` Paul Edwards
2009-09-25 10:19 ` Paul Edwards
2009-09-25 15:20 ` Ulrich Weigand
2009-09-30 17:24 ` i370 port - constructing compile script Paul Edwards
2009-09-30 17:36 ` Richard Henderson
2009-09-30 21:40 ` Paul Edwards
[not found] ` <mcrpr98x9w8.fsf@dhcp-172-17-9-151.mtv.corp.google.com>
2009-10-01 0:16 ` Joseph S. Myers
2009-10-01 14:00 ` Paul Edwards
2009-10-02 12:41 ` Paul Edwards
2009-10-02 16:00 ` Ian Lance Taylor
2009-10-02 22:53 ` Paul Edwards
2009-10-04 4:11 ` Ian Lance Taylor
2009-10-04 5:14 ` Paul Edwards
2009-10-04 6:04 ` Ian Lance Taylor
2009-10-04 6:50 ` Paul Edwards
2009-10-04 15:38 ` Ulrich Weigand
2009-10-04 22:51 ` Paul Edwards
2009-10-05 13:15 ` Ulrich Weigand
2009-10-06 9:32 ` Paul Edwards
2009-10-06 13:15 ` Ulrich Weigand
2009-10-06 13:38 ` Paul Edwards
2009-10-06 14:01 ` Ulrich Weigand
2009-10-14 14:33 ` Paul Edwards
2009-10-19 14:19 ` Paul Edwards
2009-10-19 17:37 ` Ulrich Weigand
2009-10-20 14:18 ` Paul Edwards
2009-10-20 15:30 ` Ulrich Weigand
2009-11-12 14:03 ` Paul Edwards
2009-11-12 20:06 ` Ralf Wildenhues
2009-11-12 20:56 ` Paul Edwards
2009-11-13 11:43 ` Paul Edwards
2009-11-13 12:01 ` Ulrich Weigand
2009-11-13 12:18 ` Paul Edwards
2009-11-13 12:57 ` Ulrich Weigand
2009-11-14 8:52 ` Paul Edwards
2009-11-14 10:49 ` Ralf Wildenhues
2009-11-14 11:28 ` Paul Edwards
2009-11-22 0:51 ` Paolo Bonzini
2009-11-18 10:51 ` Paul Edwards
2009-11-19 14:27 ` Ulrich Weigand
2009-11-21 13:40 ` Paul Edwards
2009-11-23 10:33 ` i370 port - 3.4.6 to 4.4 upgrade attempt Paul Edwards
2009-11-23 10:43 ` Andreas Schwab
2009-11-23 15:43 ` Paolo Bonzini
2009-11-24 14:05 ` Ulrich Weigand
2009-11-24 14:36 ` Paul Edwards
2009-11-28 15:14 ` i370 port - music/sp - possible generic gcc problem Paul Edwards
2009-11-28 16:03 ` Richard Guenther
2009-11-28 16:35 ` Paul Edwards
2009-11-28 17:03 ` Richard Guenther
2009-11-28 23:44 ` Paul Edwards
2010-05-26 14:40 ` i370 port - status Paul Edwards
2021-03-14 5:55 ` negative indexes Paul Edwards
2021-03-14 8:05 ` Richard Biener
2021-03-14 8:12 ` Paul Edwards
2021-03-14 13:37 ` Richard Biener
[not found] ` <755065BE2A0B4B508DD3A262B2A83801@DESKTOP0OKG1VA>
2021-03-15 9:22 ` Richard Biener
2021-03-15 13:55 ` extended segments on 80386 Paul Edwards
2009-12-07 12:05 ` i370 port - 3.4.6 to 4.4 upgrade attempt Paul Edwards
2009-12-08 13:55 ` Ulrich Weigand
2009-11-15 14:22 ` i370 port - finally building Paul Edwards
2009-11-22 0:46 ` i370 port - constructing compile script Paolo Bonzini
2009-11-13 12:08 ` Ulrich Weigand
2009-10-05 13:17 ` Michael Matz
2009-10-05 13:38 ` Paul Edwards
2009-10-05 13:46 ` Michael Matz
2009-10-01 14:28 ` Paul Brook
2009-10-01 16:00 ` Paul Edwards
2009-10-01 18:36 ` Ian Lance Taylor
2009-10-01 23:43 ` Paul Edwards
2009-10-01 21:10 ` David Edelsohn
2009-10-01 22:22 ` Toon Moene
2009-10-02 0:19 ` Paul Edwards
2009-11-04 5:21 ` i370 port Paul Edwards
2009-11-04 16:47 ` Ulrich Weigand
2009-11-09 14:55 ` Paul Edwards
2009-11-09 15:57 ` Ian Lance Taylor
2009-11-09 23:10 ` Paul Edwards
2009-11-10 14:58 ` Paul Edwards
2009-11-10 15:36 ` Ian Lance Taylor
2009-11-10 15:51 ` Paul Edwards
2009-11-10 15:56 ` Ian Lance Taylor
2009-12-02 22:03 ` Paul Edwards
2011-08-13 8:34 ` Paul Edwards
2011-08-15 14:32 ` Ulrich Weigand
2011-08-15 15:26 ` Paul Edwards
2011-08-15 17:23 ` Ulrich Weigand
2011-08-16 11:20 ` Paul Edwards [this message]
2011-08-16 13:26 ` Ulrich Weigand
2011-08-18 12:15 ` Paul Edwards
2011-08-18 13:14 ` Ulrich Weigand
2011-08-18 14:18 ` Paul Edwards
-- strict thread matches above, loose matches on Subject: below --
2014-02-13 4:23 Paul Edwards
2012-04-07 5:45 Paul Edwards
2012-04-08 17:43 ` Ulrich Weigand
2014-02-11 17:01 ` Paul Edwards
2012-04-06 12:49 Paul Edwards
2012-04-06 18:16 ` Ulrich Weigand
2012-04-07 4:12 ` Paul Edwards
2012-04-06 5:51 Paul Edwards
2011-08-20 12:15 Paul Edwards
2011-08-22 12:23 ` Ulrich Weigand
2012-04-05 13:32 ` Paul Edwards
2012-04-06 18:13 ` Ulrich Weigand
2011-08-20 10:09 Paul Edwards
2011-08-20 7:44 Paul Edwards
2009-09-22 12:31 Paul Edwards
2009-08-23 8:50 Paul Edwards
2009-08-26 22:13 ` Henrik Sorensen
2009-06-05 12:45 Paul Edwards
2009-06-05 14:33 ` Joseph S. Myers
2009-06-05 14:57 ` Paul Edwards
2009-06-05 15:03 ` Joseph S. Myers
2009-06-05 15:24 ` Paul Edwards
2009-06-05 15:47 ` Joseph S. Myers
2017-03-31 10:34 ` Paul Edwards
2009-09-12 12:41 ` Paul Edwards
2009-06-05 15:21 ` Ulrich Weigand
2009-06-05 15:39 ` Paul Edwards
2009-06-05 15:49 ` Daniel Jacobowitz
2009-06-05 15:57 ` Paul Edwards
2009-06-05 20:20 ` Joseph S. Myers
2009-06-05 20:45 ` Paul Edwards
2009-06-06 15:00 ` Paul Edwards
2009-06-15 17:46 ` Ulrich Weigand
2009-06-19 0:06 ` Paul Edwards
2009-06-19 12:28 ` Ulrich Weigand
2009-07-18 11:28 ` Paul Edwards
2009-07-20 14:27 ` Ulrich Weigand
2009-08-08 12:04 ` Paul Edwards
2009-08-10 21:25 ` Ulrich Weigand
2009-08-11 0:34 ` Paul Edwards
2009-08-11 15:21 ` Ulrich Weigand
2009-08-12 11:52 ` Paul Edwards
2009-08-12 15:27 ` Paolo Bonzini
2009-08-12 16:35 ` Ulrich Weigand
2009-08-12 17:27 ` Paul Edwards
2009-08-12 17:56 ` Paolo Bonzini
2009-08-12 19:46 ` Ulrich Weigand
2009-08-12 20:31 ` Paul Edwards
2009-08-19 12:07 ` Paul Edwards
2009-08-19 12:27 ` Paolo Bonzini
2009-08-20 12:49 ` Paul Edwards
2009-08-20 22:48 ` Ulrich Weigand
2009-08-21 2:37 ` Paul Edwards
2009-08-21 16:46 ` Ulrich Weigand
2009-06-05 15:44 ` Joseph S. Myers
2009-06-05 15:52 ` Paul Edwards
2009-09-08 15:55 ` Paul Edwards
2009-09-14 15:32 ` Ulrich Weigand
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