[PATCH v4 0/3] RISC-V: Add 'Zmmul' extension

[PATCH v4 0/3] RISC-V: Add 'Zmmul' extension

[Tsukasa OI]

Hi RISC-V folks,

This patch is PATCH v4 of the Zmmul support patchset primarily for Binutils
but also contains some GDB changes (simulator fix and new testcase).

***WARNING (BLOCKER)***

Although I already assigned the copyright for my Binutils contribution, I
haven't completed the copyright assignment for my GDB contribution (because
the simulator that need to be fixed is a part of GDB).

So don't merge this until my copyright assignment completes.
Once that's done, I will send a ping to the people concerned.


Note:
To test the simulator, it requires another patch:
<https://sourceware.org/pipermail/binutils/2022-July/121814.html>
that fixes a minor problem on the arch-specific simulator testing.
This is also a GDB change so once my copyright assignment is done, I will ping
*and* submit the same patch to gdb-patches@sourceware.org.



Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_zmmul>
PATCH v1:
<https://sourceware.org/pipermail/binutils/2022-July/121685.html>
PATCH v2:
<https://sourceware.org/pipermail/binutils/2022-July/121791.html>
PATCH v3:
<https://sourceware.org/pipermail/binutils/2022-July/121810.html>


This is based on the ISA Manual, draft-20220707-f518c25:
<https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220707-f518c25>
<https://github.com/riscv/riscv-isa-manual/commit/f518c259c008f926eba4aba67804f62531b6e94b>

This patchset also contains generic 'M' extension testcases.


[Changes: v3 -> v4]

-   Minor rebase
-   Fixed the issue that caused the failure of the simulator test.


[Changes: v2 -> v3]

-   Minor rebase
-   Fixed an issue which caused the simulator to stop working.


[Changes: v1 -> v2]

-   Minor rebase
-   On testcases, use macro symbols with no leading underscores
    (__64_bit__ -> rv64  and  __zmmul__ -> zmmul)
    Thanks to Shihua for feedback.
-   Renamed some testcases


[BUG in PATCH v2: Simulator stopped working after PATCH v2]

The cause was simple.  The simulator supports I, M and A extensions and
the instruction is identified by those instruction classes:

-   INSN_CLASS_I (for 'I')
-   INSN_CLASS_M (for 'M')
-   INSN_CLASS_A (for 'A')

I forgot to add INSN_CLASS_ZMMUL (for 'M') and that caused multiply
instructions to cause failure.

PATCH v3 fixed that and I added a testcase (checks whether all RV32M
instructions run without any fault).


[RFC: Implied extension (same text as PATCH v2)]

Tsukasa OI's (my) patchset implies 'Zmmul' from 'M'.
LIAO Shihua's patch does not imply 'Zmmul' from 'M'.

c.f. <https://sourceware.org/pipermail/binutils/2022-July/121685.html> (OI)
c.f. <https://sourceware.org/pipermail/binutils/2022-July/121728.html> (LIAO)

My position is derived from existing implications: Zhinx -> Zhinxmin and
Zfh -> Zfhmin.  Big problem is, those implications are implemented by ME.

I have no or a little preference here and I would like
to hear your thoughts.


Thanks,
Tsukasa




Tsukasa OI (3):
  RISC-V: Add 'M' extension testcases
  RISC-V: Add 'Zmmul' extension
  RISC-V: Add 'Zmmul' failure testcases

 bfd/elfxx-riscv.c                             |  6 +++++
 gas/testsuite/gas/riscv/attribute-09.d        |  2 +-
 gas/testsuite/gas/riscv/m-ext-32.d            | 18 +++++++++++++
 gas/testsuite/gas/riscv/m-ext-64.d            | 23 ++++++++++++++++
 .../gas/riscv/m-ext-fail-noarch-64.d          |  4 +++
 .../gas/riscv/m-ext-fail-noarch-64.l          | 14 ++++++++++
 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d  |  4 +++
 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l  |  6 +++++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d |  4 +++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l |  5 ++++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d |  4 +++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l |  9 +++++++
 gas/testsuite/gas/riscv/m-ext.s               | 21 +++++++++++++++
 gas/testsuite/gas/riscv/option-arch-02.d      |  2 +-
 gas/testsuite/gas/riscv/zmmul-32.d            | 14 ++++++++++
 gas/testsuite/gas/riscv/zmmul-64.d            | 15 +++++++++++
 include/opcode/riscv.h                        |  1 +
 opcodes/riscv-opc.c                           | 26 +++++++++----------
 sim/riscv/sim-main.c                          |  1 +
 sim/testsuite/riscv/m-ext.s                   | 18 +++++++++++++
 20 files changed, 182 insertions(+), 15 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/m-ext-32.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-64.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext.s
 create mode 100644 gas/testsuite/gas/riscv/zmmul-32.d
 create mode 100644 gas/testsuite/gas/riscv/zmmul-64.d
 create mode 100644 sim/testsuite/riscv/m-ext.s


base-commit: 65c9841b6fee984714509acef6e52366363072b6
-- 
2.34.1

[PATCH v4 1/3] RISC-V: Add 'M' extension testcases

[Tsukasa OI]

This commit adds basic 'M' (multiply/divide) extension testcases.

gas/ChangeLog:

	* testsuite/gas/riscv/m-ext.s: New test.
	* testsuite/gas/riscv/m-ext-32.d: New test (RV32).
	* testsuite/gas/riscv/m-ext-64.d: New test (RV64).
	* testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure
	by using RV64-only instructions in RV32).
	* testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise.
---
 gas/testsuite/gas/riscv/m-ext-32.d           | 18 +++++++++++++++
 gas/testsuite/gas/riscv/m-ext-64.d           | 23 ++++++++++++++++++++
 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d |  4 ++++
 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l |  6 +++++
 gas/testsuite/gas/riscv/m-ext.s              | 21 ++++++++++++++++++
 5 files changed, 72 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/m-ext-32.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-64.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext.s

diff --git a/gas/testsuite/gas/riscv/m-ext-32.d b/gas/testsuite/gas/riscv/m-ext-32.d
new file mode 100644
index 00000000000..fe2ef9af54b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-32.d
@@ -0,0 +1,18 @@
+#as: -march=rv32im
+#source: m-ext.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+02c58533[ 	]+mul[  	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c59533[ 	]+mulh[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5a533[ 	]+mulhsu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5b533[ 	]+mulhu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5c533[ 	]+div[  	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5d533[ 	]+divu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5e533[ 	]+rem[  	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5f533[ 	]+remu[ 	]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/m-ext-64.d b/gas/testsuite/gas/riscv/m-ext-64.d
new file mode 100644
index 00000000000..05099b14e9e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-64.d
@@ -0,0 +1,23 @@
+#as: -march=rv64im -defsym rv64=1
+#source: m-ext.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+02c58533[ 	]+mul[  	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c59533[ 	]+mulh[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5a533[ 	]+mulhsu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5b533[ 	]+mulhu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5c533[ 	]+div[  	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5d533[ 	]+divu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5e533[ 	]+rem[  	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5f533[ 	]+remu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5853b[ 	]+mulw[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5c53b[ 	]+divw[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5d53b[ 	]+divuw[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5e53b[ 	]+remw[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5f53b[ 	]+remuw[ 	]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
new file mode 100644
index 00000000000..54f8b8225dc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
@@ -0,0 +1,4 @@
+#as: -march=rv32im -defsym rv64=1
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-fail-xlen-32.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
new file mode 100644
index 00000000000..d65ca4980e6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
@@ -0,0 +1,6 @@
+.*Assembler messages:
+.*: Error: unrecognized opcode `mulw a0,a1,a2'
+.*: Error: unrecognized opcode `divw a0,a1,a2'
+.*: Error: unrecognized opcode `divuw a0,a1,a2'
+.*: Error: unrecognized opcode `remw a0,a1,a2'
+.*: Error: unrecognized opcode `remuw a0,a1,a2'
diff --git a/gas/testsuite/gas/riscv/m-ext.s b/gas/testsuite/gas/riscv/m-ext.s
new file mode 100644
index 00000000000..68baf2ab9c0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext.s
@@ -0,0 +1,21 @@
+target:
+	mul	a0, a1, a2
+	mulh	a0, a1, a2
+	mulhsu	a0, a1, a2
+	mulhu	a0, a1, a2
+.ifndef zmmul
+	div	a0, a1, a2
+	divu	a0, a1, a2
+	rem	a0, a1, a2
+	remu	a0, a1, a2
+.endif
+
+.ifdef rv64
+	mulw	a0, a1, a2
+.ifndef zmmul
+	divw	a0, a1, a2
+	divuw	a0, a1, a2
+	remw	a0, a1, a2
+	remuw	a0, a1, a2
+.endif
+.endif
-- 
2.34.1

[PATCH v4 2/3] RISC-V: Add 'Zmmul' extension

[Tsukasa OI]

This commit adds 'Zmmul' (multiply-only subset of 'M') extension and
changes so that multiply instructions a part of 'Zmmul'.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zmmul' extension
	implied by 'M'. (riscv_supported_std_z_ext) Add 'Zmmul'
	extension. (riscv_multi_subset_supports): Add handling for
	new instruction class.

gas/ChangeLog:

	* testsuite/gas/riscv/attribute-09.d: Include implied 'Zmmul'
	extension to expected output.
	* testsuite/gas/riscv/option-arch-02.d: Include implied 'Zmmul'
	extension to expected output.
	* testsuite/gas/riscv/zmmul-32.d: New expected output.
	* testsuite/gas/riscv/zmmul-64.d: Likewise.

include/ChangeLog:

	* opcode/riscv.h (enum riscv_insn_class): Add new instruction
	class INSN_CLASS_ZMMUL.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Change multiply instructions so
	that a part of 'Zmmul' extension.

sim/ChangeLog:

	* riscv/sim-main.c (execute_one): Add INSN_CLASS_ZMMUL
	to run multiply instructions correctly.
	* testsuite/riscv/m-ext.s: New test.
---
 bfd/elfxx-riscv.c                        |  6 ++++++
 gas/testsuite/gas/riscv/attribute-09.d   |  2 +-
 gas/testsuite/gas/riscv/option-arch-02.d |  2 +-
 gas/testsuite/gas/riscv/zmmul-32.d       | 14 +++++++++++++
 gas/testsuite/gas/riscv/zmmul-64.d       | 15 ++++++++++++++
 include/opcode/riscv.h                   |  1 +
 opcodes/riscv-opc.c                      | 26 ++++++++++++------------
 sim/riscv/sim-main.c                     |  1 +
 sim/testsuite/riscv/m-ext.s              | 18 ++++++++++++++++
 9 files changed, 70 insertions(+), 15 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/zmmul-32.d
 create mode 100644 gas/testsuite/gas/riscv/zmmul-64.d
 create mode 100644 sim/testsuite/riscv/m-ext.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 0b2021f5cc7..b0b89158152 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1065,6 +1065,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"e", "i",		check_implicit_always},
   {"i", "zicsr",	check_implicit_for_i},
   {"i", "zifencei",	check_implicit_for_i},
+  {"m", "zmmul",	check_implicit_always},
   {"g", "i",		check_implicit_always},
   {"g", "m",		check_implicit_always},
   {"g", "a",		check_implicit_always},
@@ -1186,6 +1187,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zifencei",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
   {"zifencei",		ISA_SPEC_CLASS_20190608,	2, 0,  0 },
   {"zihintpause",	ISA_SPEC_CLASS_DRAFT,		2, 0,  0 },
+  {"zmmul",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfhmin",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfinx",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2313,6 +2315,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zihintpause");
     case INSN_CLASS_M:
       return riscv_subset_supports (rps, "m");
+    case INSN_CLASS_ZMMUL:
+      return riscv_subset_supports (rps, "zmmul");
     case INSN_CLASS_A:
       return riscv_subset_supports (rps, "a");
     case INSN_CLASS_F:
@@ -2428,6 +2432,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zihintpause";
     case INSN_CLASS_M:
       return "m";
+    case INSN_CLASS_ZMMUL:
+      return _ ("m' or `zmmul");
     case INSN_CLASS_A:
       return "a";
     case INSN_CLASS_F:
diff --git a/gas/testsuite/gas/riscv/attribute-09.d b/gas/testsuite/gas/riscv/attribute-09.d
index fc87f82c554..c92dc970eea 100644
--- a/gas/testsuite/gas/riscv/attribute-09.d
+++ b/gas/testsuite/gas/riscv/attribute-09.d
@@ -3,4 +3,4 @@
 #source: empty.s
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p2_m2p0_zicsr2p0"
+  Tag_RISCV_arch: "rv32i2p2_m2p0_zicsr2p0_zmmul1p0"
diff --git a/gas/testsuite/gas/riscv/option-arch-02.d b/gas/testsuite/gas/riscv/option-arch-02.d
index 9ca013e507e..3c27419f9d3 100644
--- a/gas/testsuite/gas/riscv/option-arch-02.d
+++ b/gas/testsuite/gas/riscv/option-arch-02.d
@@ -4,5 +4,5 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv64i2p0_m3p0_f2p0_d3p0_c2p0_xvendor32x3p0"
+  Tag_RISCV_arch: "rv64i2p0_m3p0_f2p0_d3p0_c2p0_zmmul1p0_xvendor32x3p0"
 #...
diff --git a/gas/testsuite/gas/riscv/zmmul-32.d b/gas/testsuite/gas/riscv/zmmul-32.d
new file mode 100644
index 00000000000..c9cf56ab33f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zmmul-32.d
@@ -0,0 +1,14 @@
+#as: -march=rv32im -defsym zmmul=1
+#source: m-ext.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+02c58533[ 	]+mul[  	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c59533[ 	]+mulh[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5a533[ 	]+mulhsu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5b533[ 	]+mulhu[ 	]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zmmul-64.d b/gas/testsuite/gas/riscv/zmmul-64.d
new file mode 100644
index 00000000000..67ef3604755
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zmmul-64.d
@@ -0,0 +1,15 @@
+#as: -march=rv64im -defsym zmmul=1 -defsym rv64=1
+#source: m-ext.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+02c58533[ 	]+mul[  	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c59533[ 	]+mulh[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5a533[ 	]+mulhsu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5b533[ 	]+mulhu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5853b[ 	]+mulw[ 	]+a0,a1,a2
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index b115e338a05..f1dabeaab8e 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -367,6 +367,7 @@ enum riscv_insn_class
   INSN_CLASS_ZICSR,
   INSN_CLASS_ZIFENCEI,
   INSN_CLASS_ZIHINTPAUSE,
+  INSN_CLASS_ZMMUL,
   INSN_CLASS_F_OR_ZFINX,
   INSN_CLASS_D_OR_ZDINX,
   INSN_CLASS_Q_OR_ZQINX,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 2f9945aa930..79be78eb367 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -558,19 +558,19 @@ const struct riscv_opcode riscv_opcodes[] =
 {"amominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
 
 /* Multiply/Divide instruction subset.  */
-{"mul",        0, INSN_CLASS_M,   "d,s,t",     MATCH_MUL, MASK_MUL, match_opcode, 0 },
-{"mulh",       0, INSN_CLASS_M,   "d,s,t",     MATCH_MULH, MASK_MULH, match_opcode, 0 },
-{"mulhu",      0, INSN_CLASS_M,   "d,s,t",     MATCH_MULHU, MASK_MULHU, match_opcode, 0 },
-{"mulhsu",     0, INSN_CLASS_M,   "d,s,t",     MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
-{"div",        0, INSN_CLASS_M,   "d,s,t",     MATCH_DIV, MASK_DIV, match_opcode, 0 },
-{"divu",       0, INSN_CLASS_M,   "d,s,t",     MATCH_DIVU, MASK_DIVU, match_opcode, 0 },
-{"rem",        0, INSN_CLASS_M,   "d,s,t",     MATCH_REM, MASK_REM, match_opcode, 0 },
-{"remu",       0, INSN_CLASS_M,   "d,s,t",     MATCH_REMU, MASK_REMU, match_opcode, 0 },
-{"mulw",      64, INSN_CLASS_M,   "d,s,t",     MATCH_MULW, MASK_MULW, match_opcode, 0 },
-{"divw",      64, INSN_CLASS_M,   "d,s,t",     MATCH_DIVW, MASK_DIVW, match_opcode, 0 },
-{"divuw",     64, INSN_CLASS_M,   "d,s,t",     MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 },
-{"remw",      64, INSN_CLASS_M,   "d,s,t",     MATCH_REMW, MASK_REMW, match_opcode, 0 },
-{"remuw",     64, INSN_CLASS_M,   "d,s,t",     MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
+{"mul",        0, INSN_CLASS_ZMMUL, "d,s,t",     MATCH_MUL, MASK_MUL, match_opcode, 0 },
+{"mulh",       0, INSN_CLASS_ZMMUL, "d,s,t",     MATCH_MULH, MASK_MULH, match_opcode, 0 },
+{"mulhu",      0, INSN_CLASS_ZMMUL, "d,s,t",     MATCH_MULHU, MASK_MULHU, match_opcode, 0 },
+{"mulhsu",     0, INSN_CLASS_ZMMUL, "d,s,t",     MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
+{"div",        0, INSN_CLASS_M,     "d,s,t",     MATCH_DIV, MASK_DIV, match_opcode, 0 },
+{"divu",       0, INSN_CLASS_M,     "d,s,t",     MATCH_DIVU, MASK_DIVU, match_opcode, 0 },
+{"rem",        0, INSN_CLASS_M,     "d,s,t",     MATCH_REM, MASK_REM, match_opcode, 0 },
+{"remu",       0, INSN_CLASS_M,     "d,s,t",     MATCH_REMU, MASK_REMU, match_opcode, 0 },
+{"mulw",      64, INSN_CLASS_ZMMUL, "d,s,t",     MATCH_MULW, MASK_MULW, match_opcode, 0 },
+{"divw",      64, INSN_CLASS_M,     "d,s,t",     MATCH_DIVW, MASK_DIVW, match_opcode, 0 },
+{"divuw",     64, INSN_CLASS_M,     "d,s,t",     MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 },
+{"remw",      64, INSN_CLASS_M,     "d,s,t",     MATCH_REMW, MASK_REMW, match_opcode, 0 },
+{"remuw",     64, INSN_CLASS_M,     "d,s,t",     MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
 
 /* Half-precision floating-point instruction subset.  */
 {"flh",        0, INSN_CLASS_ZFHMIN,   "D,o(s)",    MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 62f475671c9..ea88103098a 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case INSN_CLASS_I:
       return execute_i (cpu, iw, op);
     case INSN_CLASS_M:
+    case INSN_CLASS_ZMMUL:
       return execute_m (cpu, iw, op);
     default:
       TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class);
diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s
new file mode 100644
index 00000000000..b85397a32a0
--- /dev/null
+++ b/sim/testsuite/riscv/m-ext.s
@@ -0,0 +1,18 @@
+# check that the RV32M instructions run without any fault.
+# mach: riscv
+
+.include "testutils.inc"
+
+	start
+
+	.option	arch, +m
+	mul	x0, x1, x2
+	mulh	x0, x1, x2
+	mulhu	x0, x1, x2
+	mulhsu	x0, x1, x2
+	div	x0, x1, x2
+	divu	x0, x1, x2
+	rem	x0, x1, x2
+	remu	x0, x1, x2
+
+	pass
-- 
2.34.1

[PATCH v4 3/3] RISC-V: Add 'Zmmul' failure testcases

[Tsukasa OI]

This commit adds failure testcases on 'Zmmul' extension with no 'M'
extension.

gas/ChangeLog:

	* testsuite/gas/riscv/m-ext-fail-zmmul-32.d: New failure test
	(RV32 + Zmmul but with no M).
	* testsuite/gas/riscv/m-ext-fail-zmmul-32.l: Likewise.
	* testsuite/gas/riscv/m-ext-fail-zmmul-64.d: New failure test
	(RV64 + Zmmul but with no M).
	* testsuite/gas/riscv/m-ext-fail-zmmul-64.l: Likewise.
	* testsuite/gas/riscv/m-ext-fail-noarch-64.d: New failure test
	(no Zmmul or M).
	* testsuite/gas/riscv/m-ext-fail-noarch-64.l: Likewise.
---
 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d |  4 ++++
 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l | 14 ++++++++++++++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d  |  4 ++++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l  |  5 +++++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d  |  4 ++++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l  |  9 +++++++++
 6 files changed, 40 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l

diff --git a/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
new file mode 100644
index 00000000000..3c4fc9a0a50
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
@@ -0,0 +1,4 @@
+#as: -march=rv64i -defsym rv64=1
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-fail-noarch-64.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
new file mode 100644
index 00000000000..db9c8fb8396
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
@@ -0,0 +1,14 @@
+.*Assembler messages:
+.*: Error: unrecognized opcode `mul a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `mulh a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `mulhsu a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `mulhu a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `div a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `rem a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `mulw a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `divw a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divuw a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remw a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remuw a0,a1,a2', extension `m' required
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
new file mode 100644
index 00000000000..c164fa96f8f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
@@ -0,0 +1,4 @@
+#as: -march=rv32i_zmmul
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-fail-zmmul-32.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
new file mode 100644
index 00000000000..01510012c4c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
@@ -0,0 +1,5 @@
+.*Assembler messages:
+.*: Error: unrecognized opcode `div a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `rem a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remu a0,a1,a2', extension `m' required
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
new file mode 100644
index 00000000000..f736d9c66c6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
@@ -0,0 +1,4 @@
+#as: -march=rv64i_zmmul -defsym rv64=1
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-fail-zmmul-64.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l
new file mode 100644
index 00000000000..77799732e28
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l
@@ -0,0 +1,9 @@
+.*Assembler messages:
+.*: Error: unrecognized opcode `div a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `rem a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divw a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divuw a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remw a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remuw a0,a1,a2', extension `m' required
-- 
2.34.1

[PATCH v5 0/3] RISC-V: Add 'Zmmul' extension

[Tsukasa OI]

Hi RISC-V folks,

'Zmmul' is a RISC-V extension consisting of only multiply instructions (a
subset of 'M'; multiply and divide instructions).

This patch is PATCH v5 of the Zmmul support patchset primarily for Binutils
but also contains some GDB changes (a simulator fix and a new testcase).

I completed the copyright assignment for my GDB contribution so minor
simulator changes are now safe enough to merge.

Changed Project(s):
PATCH 1/3: Binutils
PATCH 2/3: Binutils and GDB (not to make "temporally broken" revision)
PATCH 3/3: Binutils


Note:
To confirm that the simulator is fixed, it requires another patch.
<https://sourceware.org/pipermail/gdb-patches/2022-August/191564.html>
Without the patch above, 'Zmmul' extension will still work perfectly
(even the simulator).  Still, testing whether the simulator works with this
extension (with `make check-sim') requires it.


Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_zmmul>
PATCH v1:
<https://sourceware.org/pipermail/binutils/2022-July/121685.html>
PATCH v2:
<https://sourceware.org/pipermail/binutils/2022-July/121791.html>
PATCH v3:
<https://sourceware.org/pipermail/binutils/2022-July/121810.html>
PATCH v4:
<https://sourceware.org/pipermail/binutils/2022-August/122300.html>


This is based on the ISA Manual, draft-20220707-f518c25:
<https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220707-f518c25>
<https://github.com/riscv/riscv-isa-manual/commit/f518c259c008f926eba4aba67804f62531b6e94b>

This patchset also contains generic 'M' extension testcases as PATCH 1/3 (it
also tests for existence of the symbol `zmmul' so that it can also be a
base of 'Zmmul' testcases).


[Changes: v4 -> v5]

-   Clarify that PATCH 1/3 (new 'M' extension testcases) contains
    preparation for the 'Zmmul' extension.


[BUG in PATCH v2 (fixed in v3): Simulator stopped working]

The cause was simple.  The RISC-V simulator supports I, M and A extensions
and the instruction is identified by those instruction classes:

-   INSN_CLASS_I (for 'I')
-   INSN_CLASS_M (for 'M')
-   INSN_CLASS_A (for 'A')

I forgot to add INSN_CLASS_ZMMUL (also for 'M') to that list and that caused
multiply instructions to cause failure.

PATCH v3 fixed that and I added a testcase (checks whether all RV32M
instructions run without any fault).


Thanks,
Tsukasa




Tsukasa OI (3):
  RISC-V: Add 'M' extension testcases
  RISC-V: Add 'Zmmul' extension
  RISC-V: Add 'Zmmul' failure testcases

 bfd/elfxx-riscv.c                             |  6 +++++
 gas/testsuite/gas/riscv/attribute-09.d        |  2 +-
 gas/testsuite/gas/riscv/m-ext-32.d            | 18 +++++++++++++
 gas/testsuite/gas/riscv/m-ext-64.d            | 23 ++++++++++++++++
 .../gas/riscv/m-ext-fail-noarch-64.d          |  4 +++
 .../gas/riscv/m-ext-fail-noarch-64.l          | 14 ++++++++++
 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d  |  4 +++
 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l  |  6 +++++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d |  4 +++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l |  5 ++++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d |  4 +++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l |  9 +++++++
 gas/testsuite/gas/riscv/m-ext.s               | 21 +++++++++++++++
 gas/testsuite/gas/riscv/option-arch-02.d      |  2 +-
 gas/testsuite/gas/riscv/zmmul-32.d            | 14 ++++++++++
 gas/testsuite/gas/riscv/zmmul-64.d            | 15 +++++++++++
 include/opcode/riscv.h                        |  1 +
 opcodes/riscv-opc.c                           | 26 +++++++++----------
 sim/riscv/sim-main.c                          |  1 +
 sim/testsuite/riscv/m-ext.s                   | 18 +++++++++++++
 20 files changed, 182 insertions(+), 15 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/m-ext-32.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-64.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext.s
 create mode 100644 gas/testsuite/gas/riscv/zmmul-32.d
 create mode 100644 gas/testsuite/gas/riscv/zmmul-64.d
 create mode 100644 sim/testsuite/riscv/m-ext.s


base-commit: 27d582267a1d06e94661979f8893799ac235a768
-- 
2.34.1

[PATCH v5 1/3] RISC-V: Add 'M' extension testcases

[Tsukasa OI]

This commit adds basic 'M' (multiply/divide) extension testcases.  m-ext.s
also contains preparation for 'Zmmul' extension testing (`zmmul' symbol).

gas/ChangeLog:

	* testsuite/gas/riscv/m-ext.s: New test.
	* testsuite/gas/riscv/m-ext-32.d: New test (RV32).
	* testsuite/gas/riscv/m-ext-64.d: New test (RV64).
	* testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure
	by using RV64-only instructions in RV32).
	* testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise.
---
 gas/testsuite/gas/riscv/m-ext-32.d           | 18 +++++++++++++++
 gas/testsuite/gas/riscv/m-ext-64.d           | 23 ++++++++++++++++++++
 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d |  4 ++++
 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l |  6 +++++
 gas/testsuite/gas/riscv/m-ext.s              | 21 ++++++++++++++++++
 5 files changed, 72 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/m-ext-32.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-64.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext.s

diff --git a/gas/testsuite/gas/riscv/m-ext-32.d b/gas/testsuite/gas/riscv/m-ext-32.d
new file mode 100644
index 00000000000..fe2ef9af54b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-32.d
@@ -0,0 +1,18 @@
+#as: -march=rv32im
+#source: m-ext.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+02c58533[ 	]+mul[  	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c59533[ 	]+mulh[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5a533[ 	]+mulhsu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5b533[ 	]+mulhu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5c533[ 	]+div[  	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5d533[ 	]+divu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5e533[ 	]+rem[  	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5f533[ 	]+remu[ 	]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/m-ext-64.d b/gas/testsuite/gas/riscv/m-ext-64.d
new file mode 100644
index 00000000000..05099b14e9e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-64.d
@@ -0,0 +1,23 @@
+#as: -march=rv64im -defsym rv64=1
+#source: m-ext.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+02c58533[ 	]+mul[  	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c59533[ 	]+mulh[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5a533[ 	]+mulhsu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5b533[ 	]+mulhu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5c533[ 	]+div[  	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5d533[ 	]+divu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5e533[ 	]+rem[  	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5f533[ 	]+remu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5853b[ 	]+mulw[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5c53b[ 	]+divw[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5d53b[ 	]+divuw[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5e53b[ 	]+remw[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5f53b[ 	]+remuw[ 	]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
new file mode 100644
index 00000000000..54f8b8225dc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
@@ -0,0 +1,4 @@
+#as: -march=rv32im -defsym rv64=1
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-fail-xlen-32.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
new file mode 100644
index 00000000000..d65ca4980e6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
@@ -0,0 +1,6 @@
+.*Assembler messages:
+.*: Error: unrecognized opcode `mulw a0,a1,a2'
+.*: Error: unrecognized opcode `divw a0,a1,a2'
+.*: Error: unrecognized opcode `divuw a0,a1,a2'
+.*: Error: unrecognized opcode `remw a0,a1,a2'
+.*: Error: unrecognized opcode `remuw a0,a1,a2'
diff --git a/gas/testsuite/gas/riscv/m-ext.s b/gas/testsuite/gas/riscv/m-ext.s
new file mode 100644
index 00000000000..68baf2ab9c0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext.s
@@ -0,0 +1,21 @@
+target:
+	mul	a0, a1, a2
+	mulh	a0, a1, a2
+	mulhsu	a0, a1, a2
+	mulhu	a0, a1, a2
+.ifndef zmmul
+	div	a0, a1, a2
+	divu	a0, a1, a2
+	rem	a0, a1, a2
+	remu	a0, a1, a2
+.endif
+
+.ifdef rv64
+	mulw	a0, a1, a2
+.ifndef zmmul
+	divw	a0, a1, a2
+	divuw	a0, a1, a2
+	remw	a0, a1, a2
+	remuw	a0, a1, a2
+.endif
+.endif
-- 
2.34.1

[PATCH v5 2/3] RISC-V: Add 'Zmmul' extension

[Tsukasa OI]

This commit adds 'Zmmul' (multiply-only subset of 'M') extension and
changes so that multiply instructions a part of 'Zmmul'.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zmmul' extension
	implied by 'M'. (riscv_supported_std_z_ext) Add 'Zmmul'
	extension. (riscv_multi_subset_supports): Add handling for
	new instruction class.

gas/ChangeLog:

	* testsuite/gas/riscv/attribute-09.d: Include implied 'Zmmul'
	extension to expected output.
	* testsuite/gas/riscv/option-arch-02.d: Include implied 'Zmmul'
	extension to expected output.
	* testsuite/gas/riscv/zmmul-32.d: New expected output.
	* testsuite/gas/riscv/zmmul-64.d: Likewise.

include/ChangeLog:

	* opcode/riscv.h (enum riscv_insn_class): Add new instruction
	class INSN_CLASS_ZMMUL.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Change multiply instructions so
	that a part of 'Zmmul' extension.

sim/ChangeLog:

	* riscv/sim-main.c (execute_one): Add INSN_CLASS_ZMMUL
	to run multiply instructions correctly.
	* testsuite/riscv/m-ext.s: New test.
---
 bfd/elfxx-riscv.c                        |  6 ++++++
 gas/testsuite/gas/riscv/attribute-09.d   |  2 +-
 gas/testsuite/gas/riscv/option-arch-02.d |  2 +-
 gas/testsuite/gas/riscv/zmmul-32.d       | 14 +++++++++++++
 gas/testsuite/gas/riscv/zmmul-64.d       | 15 ++++++++++++++
 include/opcode/riscv.h                   |  1 +
 opcodes/riscv-opc.c                      | 26 ++++++++++++------------
 sim/riscv/sim-main.c                     |  1 +
 sim/testsuite/riscv/m-ext.s              | 18 ++++++++++++++++
 9 files changed, 70 insertions(+), 15 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/zmmul-32.d
 create mode 100644 gas/testsuite/gas/riscv/zmmul-64.d
 create mode 100644 sim/testsuite/riscv/m-ext.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index c9636bcbdc8..8cb3c8d4930 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1039,6 +1039,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"e", "i",		check_implicit_always},
   {"i", "zicsr",	check_implicit_for_i},
   {"i", "zifencei",	check_implicit_for_i},
+  {"m", "zmmul",	check_implicit_always},
   {"g", "i",		check_implicit_always},
   {"g", "m",		check_implicit_always},
   {"g", "a",		check_implicit_always},
@@ -1160,6 +1161,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zifencei",		ISA_SPEC_CLASS_20191213,	2, 0,  0 },
   {"zifencei",		ISA_SPEC_CLASS_20190608,	2, 0,  0 },
   {"zihintpause",	ISA_SPEC_CLASS_DRAFT,		2, 0,  0 },
+  {"zmmul",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfhmin",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfinx",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2287,6 +2289,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zihintpause");
     case INSN_CLASS_M:
       return riscv_subset_supports (rps, "m");
+    case INSN_CLASS_ZMMUL:
+      return riscv_subset_supports (rps, "zmmul");
     case INSN_CLASS_A:
       return riscv_subset_supports (rps, "a");
     case INSN_CLASS_F:
@@ -2402,6 +2406,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zihintpause";
     case INSN_CLASS_M:
       return "m";
+    case INSN_CLASS_ZMMUL:
+      return _ ("m' or `zmmul");
     case INSN_CLASS_A:
       return "a";
     case INSN_CLASS_F:
diff --git a/gas/testsuite/gas/riscv/attribute-09.d b/gas/testsuite/gas/riscv/attribute-09.d
index fc87f82c554..c92dc970eea 100644
--- a/gas/testsuite/gas/riscv/attribute-09.d
+++ b/gas/testsuite/gas/riscv/attribute-09.d
@@ -3,4 +3,4 @@
 #source: empty.s
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p2_m2p0_zicsr2p0"
+  Tag_RISCV_arch: "rv32i2p2_m2p0_zicsr2p0_zmmul1p0"
diff --git a/gas/testsuite/gas/riscv/option-arch-02.d b/gas/testsuite/gas/riscv/option-arch-02.d
index 9ca013e507e..3c27419f9d3 100644
--- a/gas/testsuite/gas/riscv/option-arch-02.d
+++ b/gas/testsuite/gas/riscv/option-arch-02.d
@@ -4,5 +4,5 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv64i2p0_m3p0_f2p0_d3p0_c2p0_xvendor32x3p0"
+  Tag_RISCV_arch: "rv64i2p0_m3p0_f2p0_d3p0_c2p0_zmmul1p0_xvendor32x3p0"
 #...
diff --git a/gas/testsuite/gas/riscv/zmmul-32.d b/gas/testsuite/gas/riscv/zmmul-32.d
new file mode 100644
index 00000000000..c9cf56ab33f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zmmul-32.d
@@ -0,0 +1,14 @@
+#as: -march=rv32im -defsym zmmul=1
+#source: m-ext.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+02c58533[ 	]+mul[  	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c59533[ 	]+mulh[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5a533[ 	]+mulhsu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5b533[ 	]+mulhu[ 	]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zmmul-64.d b/gas/testsuite/gas/riscv/zmmul-64.d
new file mode 100644
index 00000000000..67ef3604755
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zmmul-64.d
@@ -0,0 +1,15 @@
+#as: -march=rv64im -defsym zmmul=1 -defsym rv64=1
+#source: m-ext.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+02c58533[ 	]+mul[  	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c59533[ 	]+mulh[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5a533[ 	]+mulhsu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5b533[ 	]+mulhu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+02c5853b[ 	]+mulw[ 	]+a0,a1,a2
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index b115e338a05..f1dabeaab8e 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -367,6 +367,7 @@ enum riscv_insn_class
   INSN_CLASS_ZICSR,
   INSN_CLASS_ZIFENCEI,
   INSN_CLASS_ZIHINTPAUSE,
+  INSN_CLASS_ZMMUL,
   INSN_CLASS_F_OR_ZFINX,
   INSN_CLASS_D_OR_ZDINX,
   INSN_CLASS_Q_OR_ZQINX,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 2f9945aa930..79be78eb367 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -558,19 +558,19 @@ const struct riscv_opcode riscv_opcodes[] =
 {"amominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
 
 /* Multiply/Divide instruction subset.  */
-{"mul",        0, INSN_CLASS_M,   "d,s,t",     MATCH_MUL, MASK_MUL, match_opcode, 0 },
-{"mulh",       0, INSN_CLASS_M,   "d,s,t",     MATCH_MULH, MASK_MULH, match_opcode, 0 },
-{"mulhu",      0, INSN_CLASS_M,   "d,s,t",     MATCH_MULHU, MASK_MULHU, match_opcode, 0 },
-{"mulhsu",     0, INSN_CLASS_M,   "d,s,t",     MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
-{"div",        0, INSN_CLASS_M,   "d,s,t",     MATCH_DIV, MASK_DIV, match_opcode, 0 },
-{"divu",       0, INSN_CLASS_M,   "d,s,t",     MATCH_DIVU, MASK_DIVU, match_opcode, 0 },
-{"rem",        0, INSN_CLASS_M,   "d,s,t",     MATCH_REM, MASK_REM, match_opcode, 0 },
-{"remu",       0, INSN_CLASS_M,   "d,s,t",     MATCH_REMU, MASK_REMU, match_opcode, 0 },
-{"mulw",      64, INSN_CLASS_M,   "d,s,t",     MATCH_MULW, MASK_MULW, match_opcode, 0 },
-{"divw",      64, INSN_CLASS_M,   "d,s,t",     MATCH_DIVW, MASK_DIVW, match_opcode, 0 },
-{"divuw",     64, INSN_CLASS_M,   "d,s,t",     MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 },
-{"remw",      64, INSN_CLASS_M,   "d,s,t",     MATCH_REMW, MASK_REMW, match_opcode, 0 },
-{"remuw",     64, INSN_CLASS_M,   "d,s,t",     MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
+{"mul",        0, INSN_CLASS_ZMMUL, "d,s,t",     MATCH_MUL, MASK_MUL, match_opcode, 0 },
+{"mulh",       0, INSN_CLASS_ZMMUL, "d,s,t",     MATCH_MULH, MASK_MULH, match_opcode, 0 },
+{"mulhu",      0, INSN_CLASS_ZMMUL, "d,s,t",     MATCH_MULHU, MASK_MULHU, match_opcode, 0 },
+{"mulhsu",     0, INSN_CLASS_ZMMUL, "d,s,t",     MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
+{"div",        0, INSN_CLASS_M,     "d,s,t",     MATCH_DIV, MASK_DIV, match_opcode, 0 },
+{"divu",       0, INSN_CLASS_M,     "d,s,t",     MATCH_DIVU, MASK_DIVU, match_opcode, 0 },
+{"rem",        0, INSN_CLASS_M,     "d,s,t",     MATCH_REM, MASK_REM, match_opcode, 0 },
+{"remu",       0, INSN_CLASS_M,     "d,s,t",     MATCH_REMU, MASK_REMU, match_opcode, 0 },
+{"mulw",      64, INSN_CLASS_ZMMUL, "d,s,t",     MATCH_MULW, MASK_MULW, match_opcode, 0 },
+{"divw",      64, INSN_CLASS_M,     "d,s,t",     MATCH_DIVW, MASK_DIVW, match_opcode, 0 },
+{"divuw",     64, INSN_CLASS_M,     "d,s,t",     MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 },
+{"remw",      64, INSN_CLASS_M,     "d,s,t",     MATCH_REMW, MASK_REMW, match_opcode, 0 },
+{"remuw",     64, INSN_CLASS_M,     "d,s,t",     MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
 
 /* Half-precision floating-point instruction subset.  */
 {"flh",        0, INSN_CLASS_ZFHMIN,   "D,o(s)",    MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 62f475671c9..ea88103098a 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case INSN_CLASS_I:
       return execute_i (cpu, iw, op);
     case INSN_CLASS_M:
+    case INSN_CLASS_ZMMUL:
       return execute_m (cpu, iw, op);
     default:
       TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class);
diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s
new file mode 100644
index 00000000000..b85397a32a0
--- /dev/null
+++ b/sim/testsuite/riscv/m-ext.s
@@ -0,0 +1,18 @@
+# check that the RV32M instructions run without any fault.
+# mach: riscv
+
+.include "testutils.inc"
+
+	start
+
+	.option	arch, +m
+	mul	x0, x1, x2
+	mulh	x0, x1, x2
+	mulhu	x0, x1, x2
+	mulhsu	x0, x1, x2
+	div	x0, x1, x2
+	divu	x0, x1, x2
+	rem	x0, x1, x2
+	remu	x0, x1, x2
+
+	pass
-- 
2.34.1

[PATCH v5 3/3] RISC-V: Add 'Zmmul' failure testcases

[Tsukasa OI]

This commit adds failure testcases on 'Zmmul' extension with no 'M'
extension.

gas/ChangeLog:

	* testsuite/gas/riscv/m-ext-fail-zmmul-32.d: New failure test
	(RV32 + Zmmul but with no M).
	* testsuite/gas/riscv/m-ext-fail-zmmul-32.l: Likewise.
	* testsuite/gas/riscv/m-ext-fail-zmmul-64.d: New failure test
	(RV64 + Zmmul but with no M).
	* testsuite/gas/riscv/m-ext-fail-zmmul-64.l: Likewise.
	* testsuite/gas/riscv/m-ext-fail-noarch-64.d: New failure test
	(no Zmmul or M).
	* testsuite/gas/riscv/m-ext-fail-noarch-64.l: Likewise.
---
 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d |  4 ++++
 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l | 14 ++++++++++++++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d  |  4 ++++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l  |  5 +++++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d  |  4 ++++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l  |  9 +++++++++
 6 files changed, 40 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l

diff --git a/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
new file mode 100644
index 00000000000..3c4fc9a0a50
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
@@ -0,0 +1,4 @@
+#as: -march=rv64i -defsym rv64=1
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-fail-noarch-64.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
new file mode 100644
index 00000000000..db9c8fb8396
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
@@ -0,0 +1,14 @@
+.*Assembler messages:
+.*: Error: unrecognized opcode `mul a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `mulh a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `mulhsu a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `mulhu a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `div a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `rem a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `mulw a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `divw a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divuw a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remw a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remuw a0,a1,a2', extension `m' required
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
new file mode 100644
index 00000000000..c164fa96f8f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
@@ -0,0 +1,4 @@
+#as: -march=rv32i_zmmul
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-fail-zmmul-32.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
new file mode 100644
index 00000000000..01510012c4c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
@@ -0,0 +1,5 @@
+.*Assembler messages:
+.*: Error: unrecognized opcode `div a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `rem a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remu a0,a1,a2', extension `m' required
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
new file mode 100644
index 00000000000..f736d9c66c6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
@@ -0,0 +1,4 @@
+#as: -march=rv64i_zmmul -defsym rv64=1
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-fail-zmmul-64.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l
new file mode 100644
index 00000000000..77799732e28
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l
@@ -0,0 +1,9 @@
+.*Assembler messages:
+.*: Error: unrecognized opcode `div a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `rem a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divw a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divuw a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remw a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remuw a0,a1,a2', extension `m' required
-- 
2.34.1

Re: [PATCH v5 0/3] RISC-V: Add 'Zmmul' extension

[Nelson Chu]

Thanks, committed except the gdb-sim part, since I'm not the
maintainer of gdb and sim, so I cannot approve the related stuff.
Besides that, some minor failures of ld testcases which caused by m
adding implicit zmmul.  However, I also fix that since it's minor.

Nelson

On Mon, Aug 29, 2022 at 9:59 AM Tsukasa OI via Binutils
<binutils@sourceware.org> wrote:
>
> Hi RISC-V folks,
>
> 'Zmmul' is a RISC-V extension consisting of only multiply instructions (a
> subset of 'M'; multiply and divide instructions).
>
> This patch is PATCH v5 of the Zmmul support patchset primarily for Binutils
> but also contains some GDB changes (a simulator fix and a new testcase).
>
> I completed the copyright assignment for my GDB contribution so minor
> simulator changes are now safe enough to merge.
>
> Changed Project(s):
> PATCH 1/3: Binutils
> PATCH 2/3: Binutils and GDB (not to make "temporally broken" revision)
> PATCH 3/3: Binutils
>
>
> Note:
> To confirm that the simulator is fixed, it requires another patch.
> <https://sourceware.org/pipermail/gdb-patches/2022-August/191564.html>
> Without the patch above, 'Zmmul' extension will still work perfectly
> (even the simulator).  Still, testing whether the simulator works with this
> extension (with `make check-sim') requires it.
>
>
> Tracker on GitHub:
> <https://github.com/a4lg/binutils-gdb/wiki/riscv_zmmul>
> PATCH v1:
> <https://sourceware.org/pipermail/binutils/2022-July/121685.html>
> PATCH v2:
> <https://sourceware.org/pipermail/binutils/2022-July/121791.html>
> PATCH v3:
> <https://sourceware.org/pipermail/binutils/2022-July/121810.html>
> PATCH v4:
> <https://sourceware.org/pipermail/binutils/2022-August/122300.html>
>
>
> This is based on the ISA Manual, draft-20220707-f518c25:
> <https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220707-f518c25>
> <https://github.com/riscv/riscv-isa-manual/commit/f518c259c008f926eba4aba67804f62531b6e94b>
>
> This patchset also contains generic 'M' extension testcases as PATCH 1/3 (it
> also tests for existence of the symbol `zmmul' so that it can also be a
> base of 'Zmmul' testcases).
>
>
> [Changes: v4 -> v5]
>
> -   Clarify that PATCH 1/3 (new 'M' extension testcases) contains
>     preparation for the 'Zmmul' extension.
>
>
> [BUG in PATCH v2 (fixed in v3): Simulator stopped working]
>
> The cause was simple.  The RISC-V simulator supports I, M and A extensions
> and the instruction is identified by those instruction classes:
>
> -   INSN_CLASS_I (for 'I')
> -   INSN_CLASS_M (for 'M')
> -   INSN_CLASS_A (for 'A')
>
> I forgot to add INSN_CLASS_ZMMUL (also for 'M') to that list and that caused
> multiply instructions to cause failure.
>
> PATCH v3 fixed that and I added a testcase (checks whether all RV32M
> instructions run without any fault).
>
>
> Thanks,
> Tsukasa
>
>
>
>
> Tsukasa OI (3):
>   RISC-V: Add 'M' extension testcases
>   RISC-V: Add 'Zmmul' extension
>   RISC-V: Add 'Zmmul' failure testcases
>
>  bfd/elfxx-riscv.c                             |  6 +++++
>  gas/testsuite/gas/riscv/attribute-09.d        |  2 +-
>  gas/testsuite/gas/riscv/m-ext-32.d            | 18 +++++++++++++
>  gas/testsuite/gas/riscv/m-ext-64.d            | 23 ++++++++++++++++
>  .../gas/riscv/m-ext-fail-noarch-64.d          |  4 +++
>  .../gas/riscv/m-ext-fail-noarch-64.l          | 14 ++++++++++
>  gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d  |  4 +++
>  gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l  |  6 +++++
>  gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d |  4 +++
>  gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l |  5 ++++
>  gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d |  4 +++
>  gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l |  9 +++++++
>  gas/testsuite/gas/riscv/m-ext.s               | 21 +++++++++++++++
>  gas/testsuite/gas/riscv/option-arch-02.d      |  2 +-
>  gas/testsuite/gas/riscv/zmmul-32.d            | 14 ++++++++++
>  gas/testsuite/gas/riscv/zmmul-64.d            | 15 +++++++++++
>  include/opcode/riscv.h                        |  1 +
>  opcodes/riscv-opc.c                           | 26 +++++++++----------
>  sim/riscv/sim-main.c                          |  1 +
>  sim/testsuite/riscv/m-ext.s                   | 18 +++++++++++++
>  20 files changed, 182 insertions(+), 15 deletions(-)
>  create mode 100644 gas/testsuite/gas/riscv/m-ext-32.d
>  create mode 100644 gas/testsuite/gas/riscv/m-ext-64.d
>  create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
>  create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
>  create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
>  create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
>  create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
>  create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
>  create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
>  create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l
>  create mode 100644 gas/testsuite/gas/riscv/m-ext.s
>  create mode 100644 gas/testsuite/gas/riscv/zmmul-32.d
>  create mode 100644 gas/testsuite/gas/riscv/zmmul-64.d
>  create mode 100644 sim/testsuite/riscv/m-ext.s
>
>
> base-commit: 27d582267a1d06e94661979f8893799ac235a768
> --
> 2.34.1
>

Re: [PATCH v5 0/3] RISC-V: Add 'Zmmul' extension

[Tsukasa OI]

On 2022/08/30 18:55, Nelson Chu wrote:
> Thanks, committed except the gdb-sim part, since I'm not the
> maintainer of gdb and sim, so I cannot approve the related stuff.
> Besides that, some minor failures of ld testcases which caused by m
> adding implicit zmmul.  However, I also fix that since it's minor.
> 
> Nelson

Thanks, and I resubmitted the sim part because it's now broken.
<https://sourceware.org/pipermail/gdb-patches/2022-August/191609.html>

Tsukasa

> 
> On Mon, Aug 29, 2022 at 9:59 AM Tsukasa OI via Binutils
> <binutils@sourceware.org> wrote:
>>
>> Hi RISC-V folks,
>>
>> 'Zmmul' is a RISC-V extension consisting of only multiply instructions (a
>> subset of 'M'; multiply and divide instructions).
>>
>> This patch is PATCH v5 of the Zmmul support patchset primarily for Binutils
>> but also contains some GDB changes (a simulator fix and a new testcase).
>>
>> I completed the copyright assignment for my GDB contribution so minor
>> simulator changes are now safe enough to merge.
>>
>> Changed Project(s):
>> PATCH 1/3: Binutils
>> PATCH 2/3: Binutils and GDB (not to make "temporally broken" revision)
>> PATCH 3/3: Binutils
>>
>>
>> Note:
>> To confirm that the simulator is fixed, it requires another patch.
>> <https://sourceware.org/pipermail/gdb-patches/2022-August/191564.html>
>> Without the patch above, 'Zmmul' extension will still work perfectly
>> (even the simulator).  Still, testing whether the simulator works with this
>> extension (with `make check-sim') requires it.
>>
>>
>> Tracker on GitHub:
>> <https://github.com/a4lg/binutils-gdb/wiki/riscv_zmmul>
>> PATCH v1:
>> <https://sourceware.org/pipermail/binutils/2022-July/121685.html>
>> PATCH v2:
>> <https://sourceware.org/pipermail/binutils/2022-July/121791.html>
>> PATCH v3:
>> <https://sourceware.org/pipermail/binutils/2022-July/121810.html>
>> PATCH v4:
>> <https://sourceware.org/pipermail/binutils/2022-August/122300.html>
>>
>>
>> This is based on the ISA Manual, draft-20220707-f518c25:
>> <https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220707-f518c25>
>> <https://github.com/riscv/riscv-isa-manual/commit/f518c259c008f926eba4aba67804f62531b6e94b>
>>
>> This patchset also contains generic 'M' extension testcases as PATCH 1/3 (it
>> also tests for existence of the symbol `zmmul' so that it can also be a
>> base of 'Zmmul' testcases).
>>
>>
>> [Changes: v4 -> v5]
>>
>> -   Clarify that PATCH 1/3 (new 'M' extension testcases) contains
>>     preparation for the 'Zmmul' extension.
>>
>>
>> [BUG in PATCH v2 (fixed in v3): Simulator stopped working]
>>
>> The cause was simple.  The RISC-V simulator supports I, M and A extensions
>> and the instruction is identified by those instruction classes:
>>
>> -   INSN_CLASS_I (for 'I')
>> -   INSN_CLASS_M (for 'M')
>> -   INSN_CLASS_A (for 'A')
>>
>> I forgot to add INSN_CLASS_ZMMUL (also for 'M') to that list and that caused
>> multiply instructions to cause failure.
>>
>> PATCH v3 fixed that and I added a testcase (checks whether all RV32M
>> instructions run without any fault).
>>
>>
>> Thanks,
>> Tsukasa
>>
>>
>>
>>
>> Tsukasa OI (3):
>>   RISC-V: Add 'M' extension testcases
>>   RISC-V: Add 'Zmmul' extension
>>   RISC-V: Add 'Zmmul' failure testcases
>>
>>  bfd/elfxx-riscv.c                             |  6 +++++
>>  gas/testsuite/gas/riscv/attribute-09.d        |  2 +-
>>  gas/testsuite/gas/riscv/m-ext-32.d            | 18 +++++++++++++
>>  gas/testsuite/gas/riscv/m-ext-64.d            | 23 ++++++++++++++++
>>  .../gas/riscv/m-ext-fail-noarch-64.d          |  4 +++
>>  .../gas/riscv/m-ext-fail-noarch-64.l          | 14 ++++++++++
>>  gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d  |  4 +++
>>  gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l  |  6 +++++
>>  gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d |  4 +++
>>  gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l |  5 ++++
>>  gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d |  4 +++
>>  gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l |  9 +++++++
>>  gas/testsuite/gas/riscv/m-ext.s               | 21 +++++++++++++++
>>  gas/testsuite/gas/riscv/option-arch-02.d      |  2 +-
>>  gas/testsuite/gas/riscv/zmmul-32.d            | 14 ++++++++++
>>  gas/testsuite/gas/riscv/zmmul-64.d            | 15 +++++++++++
>>  include/opcode/riscv.h                        |  1 +
>>  opcodes/riscv-opc.c                           | 26 +++++++++----------
>>  sim/riscv/sim-main.c                          |  1 +
>>  sim/testsuite/riscv/m-ext.s                   | 18 +++++++++++++
>>  20 files changed, 182 insertions(+), 15 deletions(-)
>>  create mode 100644 gas/testsuite/gas/riscv/m-ext-32.d
>>  create mode 100644 gas/testsuite/gas/riscv/m-ext-64.d
>>  create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
>>  create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
>>  create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
>>  create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
>>  create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
>>  create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
>>  create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
>>  create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l
>>  create mode 100644 gas/testsuite/gas/riscv/m-ext.s
>>  create mode 100644 gas/testsuite/gas/riscv/zmmul-32.d
>>  create mode 100644 gas/testsuite/gas/riscv/zmmul-64.d
>>  create mode 100644 sim/testsuite/riscv/m-ext.s
>>
>>
>> base-commit: 27d582267a1d06e94661979f8893799ac235a768
>> --
>> 2.34.1
>>
> 

[PATCH 0/1] sim: Fix RISC-V multiply instructions on simulator

[Tsukasa OI]

Hi,

Due to opcodes changes (to add the 'Zmmul' extension in the
commit 0938b032daa5 "RISC-V: Add 'Zmmul' extension in assembler."), the
instruction simulator for RISC-V is now broken.

This is because only one side of my 'Zmmul' patchset is applied.

Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/sim_riscv_zmmul>
Previous: 'Zmmul' v5:
<https://sourceware.org/pipermail/gdb-patches/2022-August/191295.html>


In the current master, multiply instructions of the RISC-V simulator doesn't
work.  The cause was simple.  The RISC-V simulator supports 'I', 'M' and 'A'
extensions and the instruction is identified by those instruction classes:

-   INSN_CLASS_I (for 'I')
-   INSN_CLASS_M (for 'M')
-   INSN_CLASS_A (for 'A')

After adding the 'Zmmul' extension, INSN_CLASS_M is splitted to:

-   INSN_CLASS_ZMMUL (multiply instructions)
-   INSN_CLASS_M     (division instructions)

So, the simulator must handle INSN_CLASS_ZMMUL separately.

My 'Zmmul' patchset fixed that and I added a testcase (checks whether all
RV32M instructions run without any fault) but only opcodes part is applied
so it's now broken state for the simulator.

This is the simulator part of the original 'Zmmul' patchset (from PATCH v5).


Note:
To confirm that the simulator is fixed, it requires another patch.
<https://sourceware.org/pipermail/gdb-patches/2022-August/191564.html>
Without the patch above, all multiply instructions will still work.
Still, testing whether the simulator works with this extension
(with `make check-sim') requires it.


Thanks,
Tsukasa




Tsukasa OI (1):
  sim: Fix RISC-V multiply instructions on simulator

 sim/riscv/sim-main.c        |  1 +
 sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+)
 create mode 100644 sim/testsuite/riscv/m-ext.s


base-commit: 803584b96d97e1f6ea50b0a0064d2a03ab0baa60
-- 
2.34.1

[PATCH 1/1] sim: Fix RISC-V multiply instructions on simulator

[Tsukasa OI]

Because of recent 'Zmmul' support, the simulator is broken.  This is caused
by instruction classification changes:

[Before]
-   INSN_CLASS_M     : multiply / divide
[After Zmmul]
-   INSN_CLASS_M     : divide
-   INSN_CLASS_ZMMUL : multiply

The simulator checks the instruction class to execute an instruction:

-   INSN_CLASS_I  : 'I'
-   INSN_CLASS_M  : 'M' (multiply / divide)
-   INSN_CLASS_A  : 'A'

'Zmmul' moved multiply instructions to INSN_CLASS_ZMMUL and that instruction
class is not handled by the simulator.

This commit handles INSN_CLASS_ZMMUL for all 'M' instructions and adds a
testcase to test all RV32M instructions run without any faults.

sim/ChangeLog:

	* riscv/sim-main.c (execute_one): Add INSN_CLASS_ZMMUL
	to run multiply instructions correctly.
	* testsuite/riscv/m-ext.s: New test.
---
 sim/riscv/sim-main.c        |  1 +
 sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+)
 create mode 100644 sim/testsuite/riscv/m-ext.s

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 62f475671c9..ea88103098a 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case INSN_CLASS_I:
       return execute_i (cpu, iw, op);
     case INSN_CLASS_M:
+    case INSN_CLASS_ZMMUL:
       return execute_m (cpu, iw, op);
     default:
       TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class);
diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s
new file mode 100644
index 00000000000..b85397a32a0
--- /dev/null
+++ b/sim/testsuite/riscv/m-ext.s
@@ -0,0 +1,18 @@
+# check that the RV32M instructions run without any fault.
+# mach: riscv
+
+.include "testutils.inc"
+
+	start
+
+	.option	arch, +m
+	mul	x0, x1, x2
+	mulh	x0, x1, x2
+	mulhu	x0, x1, x2
+	mulhsu	x0, x1, x2
+	div	x0, x1, x2
+	divu	x0, x1, x2
+	rem	x0, x1, x2
+	remu	x0, x1, x2
+
+	pass
-- 
2.34.1

[PING^1 PATCH 0/1] sim: Fix RISC-V multiply instructions on simulator

[Tsukasa OI]

NOTE: the cover letter may change each time I ping.

Hello,

As I describe later, this patchset fixes now-broken RISC-V instruction
simulator.  I hope this patchset is approved as fast as possible since it's
clearly a functional blocker for GDB 13.1.


The patch is a PING (1) of
<https://sourceware.org/pipermail/gdb-patches/2022-August/191609.html>.

Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/sim_riscv_zmmul>
Previous: 'Zmmul' v5:
<https://sourceware.org/pipermail/gdb-patches/2022-August/191295.html>


Due to opcodes changes (to add the 'Zmmul' extension in the
commit 0938b032daa5 "RISC-V: Add 'Zmmul' extension in assembler."), the
instruction simulator for RISC-V is now broken.

For multiply/divide instructions in the 'M' extension, only division /
remainder instructions work and **multiply instructions cause a trap**.

This is because only one side of my 'Zmmul' patchset is applied and GDB-
part of my 'Zmmul' patchset (this) is not approved yet.

In the current master, multiply instructions of the RISC-V simulator doesn't
work.  The cause was simple.  The RISC-V simulator supports 'I', 'M' and 'A'
extensions and the instruction is identified by those instruction classes:

-   INSN_CLASS_I (for 'I')
-   INSN_CLASS_M (for 'M')
-   INSN_CLASS_A (for 'A')

After adding the 'Zmmul' extension, INSN_CLASS_M is splitted to:

-   INSN_CLASS_ZMMUL (multiply instructions)
-   INSN_CLASS_M     (division instructions)

So, the simulator must handle INSN_CLASS_ZMMUL separately.

My 'Zmmul' patchset fixed that and I added a testcase (checks whether all
RV32M instructions run without any fault) but only opcodes part is applied
so it's now broken state for the simulator.

This is the simulator part of the original 'Zmmul' patchset (from PATCH v5).


Note:
To confirm that the simulator is fixed, it requires another patch.
<https://sourceware.org/pipermail/gdb-patches/2022-August/191564.html>
Without the patch above, all multiply instructions will still work.
Still, testing whether the simulator works with this extension
(with `make check-sim') requires it.


Regards,
Tsukasa




Tsukasa OI (1):
  sim/riscv: Fix RISC-V multiply instructions on the simulator

 sim/riscv/sim-main.c        |  1 +
 sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+)
 create mode 100644 sim/testsuite/riscv/m-ext.s


base-commit: e959744eca88a4d145f39d5fbf4ab095af0f16b4
-- 
2.34.1

[PING^1 PATCH 1/1] sim/riscv: Fix RISC-V multiply instructions on the simulator

[Tsukasa OI]

Because of recent 'Zmmul' support, the simulator is broken.  This is caused
by instruction classification changes:

[Before]
-   INSN_CLASS_M     : multiply / divide
[After Zmmul]
-   INSN_CLASS_M     : divide
-   INSN_CLASS_ZMMUL : multiply

The simulator checks the instruction class to execute an instruction:

-   INSN_CLASS_I  : 'I'
-   INSN_CLASS_M  : 'M' (multiply / divide)
-   INSN_CLASS_A  : 'A'

'Zmmul' moved multiply instructions to INSN_CLASS_ZMMUL and that instruction
class is not handled by the simulator.

This commit handles INSN_CLASS_ZMMUL for all 'M' instructions and adds a
testcase to test all RV32M instructions run without any faults.

sim/ChangeLog:

	* riscv/sim-main.c (execute_one): Add INSN_CLASS_ZMMUL
	to run multiply instructions correctly.
	* testsuite/riscv/m-ext.s: New test.
---
 sim/riscv/sim-main.c        |  1 +
 sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+)
 create mode 100644 sim/testsuite/riscv/m-ext.s

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 30d2f1e1c9a..0156f791d4b 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case INSN_CLASS_I:
       return execute_i (cpu, iw, op);
     case INSN_CLASS_M:
+    case INSN_CLASS_ZMMUL:
       return execute_m (cpu, iw, op);
     default:
       TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class);
diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s
new file mode 100644
index 00000000000..b85397a32a0
--- /dev/null
+++ b/sim/testsuite/riscv/m-ext.s
@@ -0,0 +1,18 @@
+# check that the RV32M instructions run without any fault.
+# mach: riscv
+
+.include "testutils.inc"
+
+	start
+
+	.option	arch, +m
+	mul	x0, x1, x2
+	mulh	x0, x1, x2
+	mulhu	x0, x1, x2
+	mulhsu	x0, x1, x2
+	div	x0, x1, x2
+	divu	x0, x1, x2
+	rem	x0, x1, x2
+	remu	x0, x1, x2
+
+	pass
-- 
2.34.1

[PING^2 PATCH 0/1] sim/riscv: Fix broken RISC-V simulater after implementing 'Zmmul'

[Tsukasa OI]

TODO
NOTE: the cover letter and subject may change each time I ping.

Hello,

As I describe later, this patchset fixes now-broken RISC-V instruction
simulator.  I hope this patchset is approved as fast as possible since it's
clearly a functional blocker for GDB 13.1.


The patch is a PING (1) of
<https://sourceware.org/pipermail/gdb-patches/2022-August/191609.html>.

Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/sim_riscv_zmmul>
Previous: 'Zmmul' v5:
<https://sourceware.org/pipermail/gdb-patches/2022-August/191295.html>


Due to opcodes changes (to add the 'Zmmul' extension in the
commit 0938b032daa5 "RISC-V: Add 'Zmmul' extension in assembler."), the
instruction simulator for RISC-V is now broken.

For multiply/divide instructions in the 'M' extension, only division /
remainder instructions work and **multiply instructions cause a trap**.

This is because only one side of my 'Zmmul' patchset is applied and GDB-
part of my 'Zmmul' patchset (this) is not approved yet.

In the current master, multiply instructions of the RISC-V simulator doesn't
work.  The cause was simple.  The RISC-V simulator supports 'I', 'M' and 'A'
extensions and the instruction is identified by those instruction classes:

-   INSN_CLASS_I (for 'I')
-   INSN_CLASS_M (for 'M')
-   INSN_CLASS_A (for 'A')

After adding the 'Zmmul' extension, INSN_CLASS_M is splitted to:

-   INSN_CLASS_ZMMUL (multiply instructions)
-   INSN_CLASS_M     (division instructions)

So, the simulator must handle INSN_CLASS_ZMMUL separately.

My 'Zmmul' patchset fixed that and I added a testcase (checks whether all
RV32M instructions run without any fault) but only opcodes part is applied
so it's now broken state for the simulator.

This is the simulator part of the original 'Zmmul' patchset (from PATCH v5).


Note:
To confirm that the simulator is fixed, it requires another patch.
<https://sourceware.org/pipermail/gdb-patches/2022-August/191564.html>
Without the patch above, all multiply instructions will still work.
Still, testing whether the simulator works with this extension
(with `make check-sim') requires it.


Regards,
Tsukasa




Tsukasa OI (1):
  sim/riscv: Fix RISC-V multiply instructions on the simulator

 sim/riscv/sim-main.c        |  1 +
 sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+)
 create mode 100644 sim/testsuite/riscv/m-ext.s


base-commit: 0242db993f8ad0a0de16dafc4ebd35bb6190c833
-- 
2.34.1

[PING^2 PATCH 1/1] sim/riscv: Fix RISC-V multiply instructions on the simulator

[Tsukasa OI]

Because of recent 'Zmmul' support, the simulator is broken.  This is caused
by instruction classification changes:

[Before]
-   INSN_CLASS_M     : multiply / divide
[After Zmmul]
-   INSN_CLASS_M     : divide
-   INSN_CLASS_ZMMUL : multiply

The simulator checks the instruction class to execute an instruction:

-   INSN_CLASS_I  : 'I'
-   INSN_CLASS_M  : 'M' (multiply / divide)
-   INSN_CLASS_A  : 'A'

'Zmmul' moved multiply instructions to INSN_CLASS_ZMMUL and that instruction
class is not handled by the simulator.

This commit handles INSN_CLASS_ZMMUL for all 'M' instructions and adds a
testcase to test all RV32M instructions run without any faults.

sim/ChangeLog:

	* riscv/sim-main.c (execute_one): Add INSN_CLASS_ZMMUL
	to run multiply instructions correctly.
	* testsuite/riscv/m-ext.s: New test.
---
 sim/riscv/sim-main.c        |  1 +
 sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+)
 create mode 100644 sim/testsuite/riscv/m-ext.s

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 30d2f1e1c9a..0156f791d4b 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case INSN_CLASS_I:
       return execute_i (cpu, iw, op);
     case INSN_CLASS_M:
+    case INSN_CLASS_ZMMUL:
       return execute_m (cpu, iw, op);
     default:
       TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class);
diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s
new file mode 100644
index 00000000000..b85397a32a0
--- /dev/null
+++ b/sim/testsuite/riscv/m-ext.s
@@ -0,0 +1,18 @@
+# check that the RV32M instructions run without any fault.
+# mach: riscv
+
+.include "testutils.inc"
+
+	start
+
+	.option	arch, +m
+	mul	x0, x1, x2
+	mulh	x0, x1, x2
+	mulhu	x0, x1, x2
+	mulhsu	x0, x1, x2
+	div	x0, x1, x2
+	divu	x0, x1, x2
+	rem	x0, x1, x2
+	remu	x0, x1, x2
+
+	pass
-- 
2.34.1

[PING^3 PATCH 0/1] sim/riscv: PR29595, Fix broken RISC-V simulater after implementing 'Zmmul'

[Tsukasa OI]

NOTE: the cover letter and subject may change each time I ping.

Hello,

As I describe later, this patchset fixes now-broken RISC-V instruction
simulator.  I hope this patchset is approved as fast as possible since it's
clearly a functional blocker for GDB 13.1.


The patch is a PING (3) of
<https://sourceware.org/pipermail/gdb-patches/2022-August/191609.html>.

Issue Tracker on Sourceware Bugzilla:
<https://sourceware.org/bugzilla/show_bug.cgi?id=29595>

Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/sim_riscv_zmmul>
Previous: 'Zmmul' v5:
<https://sourceware.org/pipermail/gdb-patches/2022-August/191295.html>


Due to opcodes changes (to add the 'Zmmul' extension in the
commit 0938b032daa5 "RISC-V: Add 'Zmmul' extension in assembler."), the
instruction simulator for RISC-V is now broken.

For multiply/divide instructions in the 'M' extension, only division /
remainder instructions work and **multiply instructions cause a trap**.

This is because only one side of my 'Zmmul' patchset is applied and GDB-
part of my 'Zmmul' patchset (this) is not approved yet.

In the current master, multiply instructions of the RISC-V simulator doesn't
work.  The cause was simple.  The RISC-V simulator supports 'I', 'M' and 'A'
extensions and the instruction is identified by those instruction classes:

-   INSN_CLASS_I (for 'I')
-   INSN_CLASS_M (for 'M')
-   INSN_CLASS_A (for 'A')

After adding the 'Zmmul' extension, INSN_CLASS_M is splitted to:

-   INSN_CLASS_ZMMUL (multiply instructions)
-   INSN_CLASS_M     (division instructions)

So, the simulator must handle INSN_CLASS_ZMMUL separately.

My 'Zmmul' patchset fixed that and I added a testcase (checks whether all
RV32M instructions run without any fault) but only opcodes part is applied
so it's now broken state for the simulator.

This is the simulator part of the original 'Zmmul' patchset (from PATCH v5).


Note:
To confirm that the simulator is fixed, it requires another patch.
<https://sourceware.org/pipermail/gdb-patches/2022-August/191564.html>
Without the patch above, all multiply instructions will still work.
Still, testing whether the simulator works with this extension
(with `make check-sim') requires it.


Regards,
Tsukasa




Tsukasa OI (1):
  sim/riscv: PR29595, Fix multiply instructions

 sim/riscv/sim-main.c        |  1 +
 sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+)
 create mode 100644 sim/testsuite/riscv/m-ext.s


base-commit: 80e0c6dc91f52fad32c3ff3cf20da889d77013ac
-- 
2.34.1

[PING^3 PATCH 1/1] sim/riscv: PR29595, Fix multiply instructions

[Tsukasa OI]

Because of recent 'Zmmul' support, the simulator is now broken.  This is
caused by instruction classification changes:

[Before]
-   INSN_CLASS_M     : multiply / divide
[After Zmmul]
-   INSN_CLASS_M     : divide
-   INSN_CLASS_ZMMUL : multiply

The simulator checks the instruction class to execute an instruction:

-   INSN_CLASS_I  : 'I'
-   INSN_CLASS_M  : 'M' (multiply / divide)
-   INSN_CLASS_A  : 'A'

'Zmmul' moved multiply instructions to INSN_CLASS_ZMMUL and that instruction
class is not handled by the simulator.

This commit handles INSN_CLASS_ZMMUL for all 'M' instructions and adds a
testcase to test all RV32M instructions run without any faults.
---
 sim/riscv/sim-main.c        |  1 +
 sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+)
 create mode 100644 sim/testsuite/riscv/m-ext.s

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 30d2f1e1c9a..0156f791d4b 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case INSN_CLASS_I:
       return execute_i (cpu, iw, op);
     case INSN_CLASS_M:
+    case INSN_CLASS_ZMMUL:
       return execute_m (cpu, iw, op);
     default:
       TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class);
diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s
new file mode 100644
index 00000000000..b85397a32a0
--- /dev/null
+++ b/sim/testsuite/riscv/m-ext.s
@@ -0,0 +1,18 @@
+# check that the RV32M instructions run without any fault.
+# mach: riscv
+
+.include "testutils.inc"
+
+	start
+
+	.option	arch, +m
+	mul	x0, x1, x2
+	mulh	x0, x1, x2
+	mulhu	x0, x1, x2
+	mulhsu	x0, x1, x2
+	div	x0, x1, x2
+	divu	x0, x1, x2
+	rem	x0, x1, x2
+	remu	x0, x1, x2
+
+	pass
-- 
2.34.1

Re: [PING^3 PATCH 1/1] sim/riscv: PR29595, Fix multiply instructions

[Palmer Dabbelt]

On Thu, 06 Oct 2022 03:33:00 PDT (-0700), research_trasio@irq.a4lg.com wrote:
> Because of recent 'Zmmul' support, the simulator is now broken.  This is
> caused by instruction classification changes:
>
> [Before]
> -   INSN_CLASS_M     : multiply / divide
> [After Zmmul]
> -   INSN_CLASS_M     : divide
> -   INSN_CLASS_ZMMUL : multiply
>
> The simulator checks the instruction class to execute an instruction:
>
> -   INSN_CLASS_I  : 'I'
> -   INSN_CLASS_M  : 'M' (multiply / divide)
> -   INSN_CLASS_A  : 'A'
>
> 'Zmmul' moved multiply instructions to INSN_CLASS_ZMMUL and that instruction
> class is not handled by the simulator.
>
> This commit handles INSN_CLASS_ZMMUL for all 'M' instructions and adds a
> testcase to test all RV32M instructions run without any faults.
> ---
>  sim/riscv/sim-main.c        |  1 +
>  sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++
>  2 files changed, 19 insertions(+)
>  create mode 100644 sim/testsuite/riscv/m-ext.s
>
> diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
> index 30d2f1e1c9a..0156f791d4b 100644
> --- a/sim/riscv/sim-main.c
> +++ b/sim/riscv/sim-main.c
> @@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
>      case INSN_CLASS_I:
>        return execute_i (cpu, iw, op);
>      case INSN_CLASS_M:
> +    case INSN_CLASS_ZMMUL:
>        return execute_m (cpu, iw, op);
>      default:
>        TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class);
> diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s
> new file mode 100644
> index 00000000000..b85397a32a0
> --- /dev/null
> +++ b/sim/testsuite/riscv/m-ext.s
> @@ -0,0 +1,18 @@
> +# check that the RV32M instructions run without any fault.
> +# mach: riscv
> +
> +.include "testutils.inc"
> +
> +	start
> +
> +	.option	arch, +m
> +	mul	x0, x1, x2
> +	mulh	x0, x1, x2
> +	mulhu	x0, x1, x2
> +	mulhsu	x0, x1, x2
> +	div	x0, x1, x2
> +	divu	x0, x1, x2
> +	rem	x0, x1, x2
> +	remu	x0, x1, x2
> +
> +	pass

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>

though as we're talking about in this meeting, I'm not actually a gdbsim 
maintainer so I'm not sure I can formally approve it.

Re: [PING^3 PATCH 1/1] sim/riscv: PR29595, Fix multiply instructions

[Tsukasa OI]

On 2022/10/07 0:58, Palmer Dabbelt wrote:
> On Thu, 06 Oct 2022 03:33:00 PDT (-0700), research_trasio@irq.a4lg.com
> wrote:
>> Because of recent 'Zmmul' support, the simulator is now broken.  This is
>> caused by instruction classification changes:
>>
>> [Before]
>> -   INSN_CLASS_M     : multiply / divide
>> [After Zmmul]
>> -   INSN_CLASS_M     : divide
>> -   INSN_CLASS_ZMMUL : multiply
>>
>> The simulator checks the instruction class to execute an instruction:
>>
>> -   INSN_CLASS_I  : 'I'
>> -   INSN_CLASS_M  : 'M' (multiply / divide)
>> -   INSN_CLASS_A  : 'A'
>>
>> 'Zmmul' moved multiply instructions to INSN_CLASS_ZMMUL and that
>> instruction
>> class is not handled by the simulator.
>>
>> This commit handles INSN_CLASS_ZMMUL for all 'M' instructions and adds a
>> testcase to test all RV32M instructions run without any faults.
>> ---
>>  sim/riscv/sim-main.c        |  1 +
>>  sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++
>>  2 files changed, 19 insertions(+)
>>  create mode 100644 sim/testsuite/riscv/m-ext.s
>>
>> diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
>> index 30d2f1e1c9a..0156f791d4b 100644
>> --- a/sim/riscv/sim-main.c
>> +++ b/sim/riscv/sim-main.c
>> @@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const
>> struct riscv_opcode *op)
>>      case INSN_CLASS_I:
>>        return execute_i (cpu, iw, op);
>>      case INSN_CLASS_M:
>> +    case INSN_CLASS_ZMMUL:
>>        return execute_m (cpu, iw, op);
>>      default:
>>        TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class);
>> diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s
>> new file mode 100644
>> index 00000000000..b85397a32a0
>> --- /dev/null
>> +++ b/sim/testsuite/riscv/m-ext.s
>> @@ -0,0 +1,18 @@
>> +# check that the RV32M instructions run without any fault.
>> +# mach: riscv
>> +
>> +.include "testutils.inc"
>> +
>> +    start
>> +
>> +    .option    arch, +m
>> +    mul    x0, x1, x2
>> +    mulh    x0, x1, x2
>> +    mulhu    x0, x1, x2
>> +    mulhsu    x0, x1, x2
>> +    div    x0, x1, x2
>> +    divu    x0, x1, x2
>> +    rem    x0, x1, x2
>> +    remu    x0, x1, x2
>> +
>> +    pass
> 
> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> 
> though as we're talking about in this meeting, I'm not actually a gdbsim
> maintainer so I'm not sure I can formally approve it.
> 

Palmer,

I saw following files and thought you are one of the person who can
formally approve my patch.

Quoting sim/MAINTAINERS:
>                 SIM Maintainers
> 
> The simulator is part of the GDB project, so see the file
> gdb/MAINTAINERS for general information about maintaining these files....
> common          Frank Ch. Eigler <fche@redhat.com>
> *               (target, then global maintainers)

I know that Andrew and Palmer are RISC-V target maintainers of GDB so I
assumed you are responsible for this area.  But it seems... no one knows
exactly.  It seems very few people is interested in the simulator so...
well... for now, I will continue pinging until someone who thinks
responsible notices.

Thanks,
Tsukasa

Re: [PING^3 PATCH 1/1] sim/riscv: PR29595, Fix multiply instructions

[Palmer Dabbelt]

On Thu, 06 Oct 2022 09:14:37 PDT (-0700), research_trasio@irq.a4lg.com wrote:
> On 2022/10/07 0:58, Palmer Dabbelt wrote:
>> On Thu, 06 Oct 2022 03:33:00 PDT (-0700), research_trasio@irq.a4lg.com
>> wrote:
>>> Because of recent 'Zmmul' support, the simulator is now broken.  This is
>>> caused by instruction classification changes:
>>>
>>> [Before]
>>> -   INSN_CLASS_M     : multiply / divide
>>> [After Zmmul]
>>> -   INSN_CLASS_M     : divide
>>> -   INSN_CLASS_ZMMUL : multiply
>>>
>>> The simulator checks the instruction class to execute an instruction:
>>>
>>> -   INSN_CLASS_I  : 'I'
>>> -   INSN_CLASS_M  : 'M' (multiply / divide)
>>> -   INSN_CLASS_A  : 'A'
>>>
>>> 'Zmmul' moved multiply instructions to INSN_CLASS_ZMMUL and that
>>> instruction
>>> class is not handled by the simulator.
>>>
>>> This commit handles INSN_CLASS_ZMMUL for all 'M' instructions and adds a
>>> testcase to test all RV32M instructions run without any faults.
>>> ---
>>>  sim/riscv/sim-main.c        |  1 +
>>>  sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++
>>>  2 files changed, 19 insertions(+)
>>>  create mode 100644 sim/testsuite/riscv/m-ext.s
>>>
>>> diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
>>> index 30d2f1e1c9a..0156f791d4b 100644
>>> --- a/sim/riscv/sim-main.c
>>> +++ b/sim/riscv/sim-main.c
>>> @@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const
>>> struct riscv_opcode *op)
>>>      case INSN_CLASS_I:
>>>        return execute_i (cpu, iw, op);
>>>      case INSN_CLASS_M:
>>> +    case INSN_CLASS_ZMMUL:
>>>        return execute_m (cpu, iw, op);
>>>      default:
>>>        TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class);
>>> diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s
>>> new file mode 100644
>>> index 00000000000..b85397a32a0
>>> --- /dev/null
>>> +++ b/sim/testsuite/riscv/m-ext.s
>>> @@ -0,0 +1,18 @@
>>> +# check that the RV32M instructions run without any fault.
>>> +# mach: riscv
>>> +
>>> +.include "testutils.inc"
>>> +
>>> +    start
>>> +
>>> +    .option    arch, +m
>>> +    mul    x0, x1, x2
>>> +    mulh    x0, x1, x2
>>> +    mulhu    x0, x1, x2
>>> +    mulhsu    x0, x1, x2
>>> +    div    x0, x1, x2
>>> +    divu    x0, x1, x2
>>> +    rem    x0, x1, x2
>>> +    remu    x0, x1, x2
>>> +
>>> +    pass
>>
>> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>>
>> though as we're talking about in this meeting, I'm not actually a gdbsim
>> maintainer so I'm not sure I can formally approve it.
>>
>
> Palmer,
>
> I saw following files and thought you are one of the person who can
> formally approve my patch.
>
> Quoting sim/MAINTAINERS:
>>                 SIM Maintainers
>>
>> The simulator is part of the GDB project, so see the file
>> gdb/MAINTAINERS for general information about maintaining these files....
>> common          Frank Ch. Eigler <fche@redhat.com>
>> *               (target, then global maintainers)
>
> I know that Andrew and Palmer are RISC-V target maintainers of GDB so I
> assumed you are responsible for this area.  But it seems... no one knows
> exactly.  It seems very few people is interested in the simulator so...
> well... for now, I will continue pinging until someone who thinks
> responsible notices.

Ah, I guess I wasn't looking close enough.  I also didn't write the sim 
port, Mike Frysinger did and he's a sim gloabal maintainer so I'd 
generally just deferred to him on these things.

+Mike and Andrew: I'm OK reviewing sim patches, at least for the stuff 
that's pretty much just ISA encoding.  The port certainly needs some 
love and I don't really have the time to write the code, but I'm OK 
finding some time to review stuff if that's what's necessary for patches 
to land (though I'd be very happy to have someone else do the work, as 
usual ;)).

Re: [PING^3 PATCH 1/1] sim/riscv: PR29595, Fix multiply instructions

[Andrew Burgess]

Palmer Dabbelt <palmer@dabbelt.com> writes:

> On Thu, 06 Oct 2022 09:14:37 PDT (-0700), research_trasio@irq.a4lg.com wrote:
>> On 2022/10/07 0:58, Palmer Dabbelt wrote:
>>> On Thu, 06 Oct 2022 03:33:00 PDT (-0700), research_trasio@irq.a4lg.com
>>> wrote:
>>>> Because of recent 'Zmmul' support, the simulator is now broken.  This is
>>>> caused by instruction classification changes:
>>>>
>>>> [Before]
>>>> -   INSN_CLASS_M     : multiply / divide
>>>> [After Zmmul]
>>>> -   INSN_CLASS_M     : divide
>>>> -   INSN_CLASS_ZMMUL : multiply
>>>>
>>>> The simulator checks the instruction class to execute an instruction:
>>>>
>>>> -   INSN_CLASS_I  : 'I'
>>>> -   INSN_CLASS_M  : 'M' (multiply / divide)
>>>> -   INSN_CLASS_A  : 'A'
>>>>
>>>> 'Zmmul' moved multiply instructions to INSN_CLASS_ZMMUL and that
>>>> instruction
>>>> class is not handled by the simulator.
>>>>
>>>> This commit handles INSN_CLASS_ZMMUL for all 'M' instructions and adds a
>>>> testcase to test all RV32M instructions run without any faults.
>>>> ---
>>>>  sim/riscv/sim-main.c        |  1 +
>>>>  sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++
>>>>  2 files changed, 19 insertions(+)
>>>>  create mode 100644 sim/testsuite/riscv/m-ext.s
>>>>
>>>> diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
>>>> index 30d2f1e1c9a..0156f791d4b 100644
>>>> --- a/sim/riscv/sim-main.c
>>>> +++ b/sim/riscv/sim-main.c
>>>> @@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const
>>>> struct riscv_opcode *op)
>>>>      case INSN_CLASS_I:
>>>>        return execute_i (cpu, iw, op);
>>>>      case INSN_CLASS_M:
>>>> +    case INSN_CLASS_ZMMUL:
>>>>        return execute_m (cpu, iw, op);
>>>>      default:
>>>>        TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class);
>>>> diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s
>>>> new file mode 100644
>>>> index 00000000000..b85397a32a0
>>>> --- /dev/null
>>>> +++ b/sim/testsuite/riscv/m-ext.s
>>>> @@ -0,0 +1,18 @@
>>>> +# check that the RV32M instructions run without any fault.
>>>> +# mach: riscv
>>>> +
>>>> +.include "testutils.inc"
>>>> +
>>>> +    start
>>>> +
>>>> +    .option    arch, +m
>>>> +    mul    x0, x1, x2
>>>> +    mulh    x0, x1, x2
>>>> +    mulhu    x0, x1, x2
>>>> +    mulhsu    x0, x1, x2
>>>> +    div    x0, x1, x2
>>>> +    divu    x0, x1, x2
>>>> +    rem    x0, x1, x2
>>>> +    remu    x0, x1, x2
>>>> +
>>>> +    pass
>>>
>>> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
>>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>>>
>>> though as we're talking about in this meeting, I'm not actually a gdbsim
>>> maintainer so I'm not sure I can formally approve it.
>>>
>>
>> Palmer,
>>
>> I saw following files and thought you are one of the person who can
>> formally approve my patch.
>>
>> Quoting sim/MAINTAINERS:
>>>                 SIM Maintainers
>>>
>>> The simulator is part of the GDB project, so see the file
>>> gdb/MAINTAINERS for general information about maintaining these files....
>>> common          Frank Ch. Eigler <fche@redhat.com>
>>> *               (target, then global maintainers)
>>
>> I know that Andrew and Palmer are RISC-V target maintainers of GDB so I
>> assumed you are responsible for this area.  But it seems... no one knows
>> exactly.  It seems very few people is interested in the simulator so...
>> well... for now, I will continue pinging until someone who thinks
>> responsible notices.
>
> Ah, I guess I wasn't looking close enough.  I also didn't write the sim 
> port, Mike Frysinger did and he's a sim gloabal maintainer so I'd 
> generally just deferred to him on these things.
>
> +Mike and Andrew: I'm OK reviewing sim patches, at least for the stuff 
> that's pretty much just ISA encoding.  The port certainly needs some 
> love and I don't really have the time to write the code, but I'm OK 
> finding some time to review stuff if that's what's necessary for patches 
> to land (though I'd be very happy to have someone else do the work, as 
> usual ;)).

Hi Palmer,

Apologies for letting some of the sim/ reviews lag.  I've been pretty
rushed for the last few weeks, but I'm trying to get on top of any
outstanding sim/ patches, and hopefully will try to keep on top of the
reviews going forward.

Thanks,
Andrew

Re: [PING^3 PATCH 1/1] sim/riscv: PR29595, Fix multiply instructions

[Andrew Burgess]

Tsukasa OI via Gdb-patches <gdb-patches@sourceware.org> writes:

> Because of recent 'Zmmul' support, the simulator is now broken.  This is
> caused by instruction classification changes:
>
> [Before]
> -   INSN_CLASS_M     : multiply / divide
> [After Zmmul]
> -   INSN_CLASS_M     : divide
> -   INSN_CLASS_ZMMUL : multiply
>
> The simulator checks the instruction class to execute an instruction:
>
> -   INSN_CLASS_I  : 'I'
> -   INSN_CLASS_M  : 'M' (multiply / divide)
> -   INSN_CLASS_A  : 'A'
>
> 'Zmmul' moved multiply instructions to INSN_CLASS_ZMMUL and that instruction
> class is not handled by the simulator.
>
> This commit handles INSN_CLASS_ZMMUL for all 'M' instructions and adds a
> testcase to test all RV32M instructions run without any faults.

Tsukasa,

Thanks for fixing this.  I've pushed a version of this patch, the
biggest change was that I rewrote the commit message, merging in the
useful information from the cover letter.  There was also one nit which
I fixed, pointed out below...

> ---
>  sim/riscv/sim-main.c        |  1 +
>  sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++
>  2 files changed, 19 insertions(+)
>  create mode 100644 sim/testsuite/riscv/m-ext.s
>
> diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
> index 30d2f1e1c9a..0156f791d4b 100644
> --- a/sim/riscv/sim-main.c
> +++ b/sim/riscv/sim-main.c
> @@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
>      case INSN_CLASS_I:
>        return execute_i (cpu, iw, op);
>      case INSN_CLASS_M:
> +    case INSN_CLASS_ZMMUL:
>        return execute_m (cpu, iw, op);
>      default:
>        TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class);
> diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s
> new file mode 100644
> index 00000000000..b85397a32a0
> --- /dev/null
> +++ b/sim/testsuite/riscv/m-ext.s
> @@ -0,0 +1,18 @@
> +# check that the RV32M instructions run without any fault.

Missing capital letter here, 'Check that ....'.

Thanks,
Andrew


> +# mach: riscv
> +
> +.include "testutils.inc"
> +
> +	start
> +
> +	.option	arch, +m
> +	mul	x0, x1, x2
> +	mulh	x0, x1, x2
> +	mulhu	x0, x1, x2
> +	mulhsu	x0, x1, x2
> +	div	x0, x1, x2
> +	divu	x0, x1, x2
> +	rem	x0, x1, x2
> +	remu	x0, x1, x2
> +
> +	pass
> -- 
> 2.34.1