* [PATCH v4 0/3] RISC-V: Support Scalar Cryptography extension
@ 2021-11-15 3:03 jiawei
2021-11-15 3:03 ` [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension jiawei
` (3 more replies)
0 siblings, 4 replies; 16+ messages in thread
From: jiawei @ 2021-11-15 3:03 UTC (permalink / raw)
To: binutils
Cc: kito.cheng, nelson.chu, jimw, philipp.tomsich, mjos,
ben.marshall, cmuellner, palmer, andrew, lazyparser, siyu,
schwab, jbeulich, jiawei
This patch is support Scalar Cryptography extension(k-ext v1.0.0-rc6) as
binutils part, you can find gcc patches part in https://github.com/WuSiYu/riscv-gcc/tree/trunk-crypto-rebase by siyu@isrc.iscas.ac.cn.
The first patch fix the order check with 'z' begin sub-extension, it set 'zb' before 'zk' as a right case. Some instruction in 'zbkb' and 'zbkc' is both used by Bitmanip and Scalar Cryptography extension, we just redefine the class with them.
Here is the github repo link contain this patch: https://github.com/pz9115/riscv-binutils-gdb/commits/k-ext-rebase, the old version of this work is form https://github.com/riscv-collab/riscv-binutils-gdb/pull/254, Thanks for Nelson Chu and Jim Wilson's review and help.
Version logs:
v2: Add missing arch "k" in riscv_supported_std_ext[] to make the order check right with "zk" behind "zb" as Neslon Chu's comment.
v3: Remove the trailing spaces as Andreas Schwab's comment. Add commit for each patch and add split testcases into sub-extension tests as Christoph Muellner's comment.
v4: Change letter order in riscv_supported_std_ext[], Move INSN_CLASS_* into follow patch, Fix SHFL/UNSHFL Mask error, Fix typo error, Add CSR_CLASS ZKR for ES_CSR as Neslon Chu's comment.
jiawei (3):
RISC-V: Minimal support of scalar crypto extension
RISC-V: Scalar crypto instructions and operand set
RISC-V: Scalar crypto instruction and Entropy Source CSR testcases
bfd/elfxx-riscv.c | 53 ++++++++++++
gas/config/tc-riscv.c | 29 +++++++
gas/testsuite/gas/riscv/k-ext-64.d | 47 ++++++++++
gas/testsuite/gas/riscv/k-ext-64.s | 38 ++++++++
gas/testsuite/gas/riscv/k-ext.d | 44 ++++++++++
gas/testsuite/gas/riscv/k-ext.s | 35 ++++++++
.../gas/riscv/priv-reg-fail-version-1p10.d | 2 +-
.../gas/riscv/priv-reg-fail-version-1p11.d | 2 +-
.../gas/riscv/priv-reg-fail-version-1p9p1.d | 2 +-
.../gas/riscv/priv-reg-version-1p10.d | 1 +
.../gas/riscv/priv-reg-version-1p11.d | 1 +
.../gas/riscv/priv-reg-version-1p9p1.d | 1 +
gas/testsuite/gas/riscv/priv-reg.s | 3 +
gas/testsuite/gas/riscv/zbkb-32.d | 22 +++++
gas/testsuite/gas/riscv/zbkb-32.s | 13 +++
gas/testsuite/gas/riscv/zbkb-64.d | 24 ++++++
gas/testsuite/gas/riscv/zbkb-64.s | 15 ++++
gas/testsuite/gas/riscv/zbkc-32.d | 12 +++
gas/testsuite/gas/riscv/zbkc-64.d | 12 +++
gas/testsuite/gas/riscv/zbkc.s | 3 +
gas/testsuite/gas/riscv/zbkx-32.d | 12 +++
gas/testsuite/gas/riscv/zbkx-64.d | 12 +++
gas/testsuite/gas/riscv/zbkx.s | 3 +
gas/testsuite/gas/riscv/zknd-32.d | 12 +++
gas/testsuite/gas/riscv/zknd-32.s | 3 +
gas/testsuite/gas/riscv/zknd-64.d | 15 ++++
gas/testsuite/gas/riscv/zknd-64.s | 6 ++
gas/testsuite/gas/riscv/zkne-32.d | 12 +++
gas/testsuite/gas/riscv/zkne-32.s | 3 +
gas/testsuite/gas/riscv/zkne-64.d | 14 +++
gas/testsuite/gas/riscv/zkne-64.s | 5 ++
gas/testsuite/gas/riscv/zknh-32.d | 20 +++++
gas/testsuite/gas/riscv/zknh-32.s | 11 +++
gas/testsuite/gas/riscv/zknh-64.d | 18 ++++
gas/testsuite/gas/riscv/zknh-64.s | 9 ++
gas/testsuite/gas/riscv/zksed-32.d | 12 +++
gas/testsuite/gas/riscv/zksed-64.d | 12 +++
gas/testsuite/gas/riscv/zksed.s | 3 +
gas/testsuite/gas/riscv/zksh-32.d | 12 +++
gas/testsuite/gas/riscv/zksh-64.d | 12 +++
gas/testsuite/gas/riscv/zksh.s | 3 +
include/opcode/riscv-opc.h | 75 ++++++++++++++++
include/opcode/riscv.h | 18 ++++
opcodes/riscv-dis.c | 8 ++
opcodes/riscv-opc.c | 86 +++++++++++++++----
45 files changed, 735 insertions(+), 20 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/k-ext-64.d
create mode 100644 gas/testsuite/gas/riscv/k-ext-64.s
create mode 100644 gas/testsuite/gas/riscv/k-ext.d
create mode 100644 gas/testsuite/gas/riscv/k-ext.s
create mode 100644 gas/testsuite/gas/riscv/zbkb-32.d
create mode 100644 gas/testsuite/gas/riscv/zbkb-32.s
create mode 100644 gas/testsuite/gas/riscv/zbkb-64.d
create mode 100644 gas/testsuite/gas/riscv/zbkb-64.s
create mode 100644 gas/testsuite/gas/riscv/zbkc-32.d
create mode 100644 gas/testsuite/gas/riscv/zbkc-64.d
create mode 100644 gas/testsuite/gas/riscv/zbkc.s
create mode 100644 gas/testsuite/gas/riscv/zbkx-32.d
create mode 100644 gas/testsuite/gas/riscv/zbkx-64.d
create mode 100644 gas/testsuite/gas/riscv/zbkx.s
create mode 100644 gas/testsuite/gas/riscv/zknd-32.d
create mode 100644 gas/testsuite/gas/riscv/zknd-32.s
create mode 100644 gas/testsuite/gas/riscv/zknd-64.d
create mode 100644 gas/testsuite/gas/riscv/zknd-64.s
create mode 100644 gas/testsuite/gas/riscv/zkne-32.d
create mode 100644 gas/testsuite/gas/riscv/zkne-32.s
create mode 100644 gas/testsuite/gas/riscv/zkne-64.d
create mode 100644 gas/testsuite/gas/riscv/zkne-64.s
create mode 100644 gas/testsuite/gas/riscv/zknh-32.d
create mode 100644 gas/testsuite/gas/riscv/zknh-32.s
create mode 100644 gas/testsuite/gas/riscv/zknh-64.d
create mode 100644 gas/testsuite/gas/riscv/zknh-64.s
create mode 100644 gas/testsuite/gas/riscv/zksed-32.d
create mode 100644 gas/testsuite/gas/riscv/zksed-64.d
create mode 100644 gas/testsuite/gas/riscv/zksed.s
create mode 100644 gas/testsuite/gas/riscv/zksh-32.d
create mode 100644 gas/testsuite/gas/riscv/zksh-64.d
create mode 100644 gas/testsuite/gas/riscv/zksh.s
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension
2021-11-15 3:03 [PATCH v4 0/3] RISC-V: Support Scalar Cryptography extension jiawei
@ 2021-11-15 3:03 ` jiawei
2022-02-21 13:24 ` Jan Beulich
2021-11-15 3:03 ` [PATCH v4 2/3] RISC-V: Scalar crypto instructions and operand set jiawei
` (2 subsequent siblings)
3 siblings, 1 reply; 16+ messages in thread
From: jiawei @ 2021-11-15 3:03 UTC (permalink / raw)
To: binutils
Cc: kito.cheng, nelson.chu, jimw, philipp.tomsich, mjos,
ben.marshall, cmuellner, palmer, andrew, lazyparser, siyu,
schwab, jbeulich, jiawei
Minimal support of scalar crypto extension, add "k" in riscv_supported_std_ext[] to make the order check right with "zk" behind "zb". "zbk*" is sub-extension for k-ext, so it added behind "zbs" in riscv_supported_std_z_ext[].
---
bfd/elfxx-riscv.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 3ffbaad66dd..152fbe3d160 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1075,6 +1075,20 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"q", "d", check_implicit_always},
{"d", "f", check_implicit_always},
{"f", "zicsr", check_implicit_always},
+ {"zk", "zkn", check_implicit_always},
+ {"zk", "zkr", check_implicit_always},
+ {"zk", "zkt", check_implicit_always},
+ {"zkn", "zbkb", check_implicit_always},
+ {"zkn", "zbkc", check_implicit_always},
+ {"zkn", "zbkx", check_implicit_always},
+ {"zkn", "zkne", check_implicit_always},
+ {"zkn", "zknd", check_implicit_always},
+ {"zkn", "zknh", check_implicit_always},
+ {"zks", "zbkb", check_implicit_always},
+ {"zks", "zbkc", check_implicit_always},
+ {"zks", "zbkx", check_implicit_always},
+ {"zks", "zksed", check_implicit_always},
+ {"zks", "zksh", check_implicit_always},
{NULL, NULL, NULL}
};
@@ -1127,6 +1141,7 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
{"c", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"c", ISA_SPEC_CLASS_2P2, 2, 0, 0 },
{"b", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
+ {"k", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
{"j", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
{"t", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
{"p", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
@@ -1146,6 +1161,19 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zbkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zbkc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zbkx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zk", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zknd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zkne", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zknh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zkr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zkt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{NULL, 0, 0, 0, 0}
};
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v4 2/3] RISC-V: Scalar crypto instructions and operand set
2021-11-15 3:03 [PATCH v4 0/3] RISC-V: Support Scalar Cryptography extension jiawei
2021-11-15 3:03 ` [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension jiawei
@ 2021-11-15 3:03 ` jiawei
2022-01-04 8:04 ` Jan Beulich
2021-11-15 3:03 ` [PATCH v4 3/3] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases jiawei
2021-11-16 4:07 ` [PATCH v4 0/3] RISC-V: Support Scalar Cryptography extension Nelson Chu
3 siblings, 1 reply; 16+ messages in thread
From: jiawei @ 2021-11-15 3:03 UTC (permalink / raw)
To: binutils
Cc: kito.cheng, nelson.chu, jimw, philipp.tomsich, mjos,
ben.marshall, cmuellner, palmer, andrew, lazyparser, siyu,
schwab, jbeulich, jiawei
Add instructions in k-ext, some instruction in zbkb, zbkc is reuse from zbb,zbc, we just change the class attribute to make them both support.
The 'aes64ks1i' and 'aes64ks2' instructions are present in both the Zknd and Zkne extensions on rv64.
Add new operand letter 'y' to present 'bs' symbol and 'Y' to present 'rnum' symbolc for zkn instructions.
Add new Entropy Source CSR define 'seed' located at address 0x015.
---
bfd/elfxx-riscv.c | 25 +++++++++++
gas/config/tc-riscv.c | 29 +++++++++++++
include/opcode/riscv-opc.h | 75 +++++++++++++++++++++++++++++++++
include/opcode/riscv.h | 18 ++++++++
opcodes/riscv-dis.c | 8 ++++
opcodes/riscv-opc.c | 86 ++++++++++++++++++++++++++++++--------
6 files changed, 224 insertions(+), 17 deletions(-)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 152fbe3d160..289da404a78 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -2180,6 +2180,31 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zbc");
case INSN_CLASS_ZBS:
return riscv_subset_supports (rps, "zbs");
+ case INSN_CLASS_ZBKB:
+ return riscv_subset_supports (rps, "zbkb");
+ case INSN_CLASS_ZBKC:
+ return riscv_subset_supports (rps, "zbkc");
+ case INSN_CLASS_ZBKX:
+ return riscv_subset_supports (rps, "zbkx");
+ case INSN_CLASS_ZBB_OR_ZBKB:
+ return (riscv_subset_supports (rps, "zbb")
+ || riscv_subset_supports (rps, "zbkb"));
+ case INSN_CLASS_ZBC_OR_ZBKC:
+ return (riscv_subset_supports (rps, "zbc")
+ || riscv_subset_supports (rps, "zbkc"));
+ case INSN_CLASS_ZKND:
+ return riscv_subset_supports (rps, "zknd");
+ case INSN_CLASS_ZKNE:
+ return riscv_subset_supports (rps, "zkne");
+ case INSN_CLASS_ZKNH:
+ return riscv_subset_supports (rps, "zknh");
+ case INSN_CLASS_ZKND_OR_ZKNE:
+ return (riscv_subset_supports (rps, "zknd")
+ || riscv_subset_supports (rps, "zkne"));
+ case INSN_CLASS_ZKSED:
+ return riscv_subset_supports (rps, "zksed");
+ case INSN_CLASS_ZKSH:
+ return riscv_subset_supports (rps, "zksh");
default:
rps->error_handler
(_("internal: unreachable INSN_CLASS_*"));
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 8cea72a9025..29330170dbe 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -63,6 +63,7 @@ enum riscv_csr_class
CSR_CLASS_I,
CSR_CLASS_I_32, /* rv32 only */
CSR_CLASS_F, /* f-ext only */
+ CSR_CLASS_ZKR, /* zkr only */
CSR_CLASS_DEBUG /* debug CSR */
};
@@ -875,6 +876,10 @@ riscv_csr_address (const char *csr_name,
result = riscv_subset_supports (&riscv_rps_as, "f");
need_check_version = false;
break;
+ case CSR_CLASS_ZKR:
+ result = riscv_subset_supports (&riscv_rps_as, "zkr");
+ need_check_version = false;
+ break;
case CSR_CLASS_DEBUG:
need_check_version = false;
break;
@@ -1085,6 +1090,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'I': break; /* Macro operand, must be constant. */
case 'D': /* RD, floating point. */
case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
+ case 'y': USE_BITS (OP_MASK_BS, OP_SH_BS); break;
+ case 'Y': USE_BITS (OP_MASK_RNUM, OP_SH_RNUM); break;
case 'Z': /* RS1, CSR number. */
case 'S': /* RS1, floating point. */
case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
@@ -2706,6 +2713,28 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
}
break;
+ case 'y': /* bs immediate */
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, FALSE);
+ if ((unsigned long)imm_expr->X_add_number > 3)
+ as_bad(_("Improper bs immediate (%lu)"),
+ (unsigned long)imm_expr->X_add_number);
+ INSERT_OPERAND(BS, *ip, imm_expr->X_add_number);
+ imm_expr->X_op = O_absent;
+ asarg = expr_end;
+ continue;
+
+ case 'Y': /* rnum immediate */
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, FALSE);
+ if ((unsigned long)imm_expr->X_add_number > 10)
+ as_bad(_("Improper rnum immediate (%lu)"),
+ (unsigned long)imm_expr->X_add_number);
+ INSERT_OPERAND(RNUM, *ip, imm_expr->X_add_number);
+ imm_expr->X_op = O_absent;
+ asarg = expr_end;
+ continue;
+
case 'z':
if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)
|| imm_expr->X_op != O_constant
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 45a207da0cd..425e6da2764 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -443,6 +443,8 @@
#define MASK_SEXT_H 0xfff0707f
#define MATCH_PACK 0x8004033
#define MASK_PACK 0xfe00707f
+#define MATCH_PACKH 0x8007033
+#define MASK_PACKH 0xfe00707f
#define MATCH_PACKW 0x800403b
#define MASK_PACKW 0xfe00707f
#define MATCH_ANDN 0x40007033
@@ -461,6 +463,10 @@
#define MASK_GREVI 0xfc00707f
#define MATCH_GORCI 0x28005013
#define MASK_GORCI 0xfc00707f
+#define MATCH_SHFLI 0x8001013
+#define MASK_SHFLI 0xfe00707f
+#define MATCH_UNSHFLI 0x8005013
+#define MASK_UNSHFLI 0xfe00707f
#define MATCH_CLZW 0x6000101b
#define MASK_CLZW 0xfff0707f
#define MATCH_CTZW 0x6010101b
@@ -495,6 +501,10 @@
#define MASK_CLMULH 0xfe00707f
#define MATCH_CLMULR 0xa002033
#define MASK_CLMULR 0xfe00707f
+#define MATCH_XPERM4 0x28002033
+#define MASK_XPERM4 0xfe00707f
+#define MATCH_XPERM8 0x28004033
+#define MASK_XPERM8 0xfe00707f
#define MATCH_BCLRI 0x48001013
#define MASK_BCLRI 0xfc00707f
#define MATCH_BSETI 0x28001013
@@ -637,6 +647,64 @@
#define MASK_C_LDSP 0xe003
#define MATCH_C_SDSP 0xe002
#define MASK_C_SDSP 0xe003
+#define MATCH_SM3P0 0x10801013
+#define MASK_SM3P0 0xfff0707f
+#define MATCH_SM3P1 0x10901013
+#define MASK_SM3P1 0xfff0707f
+#define MATCH_SHA256SUM0 0x10001013
+#define MASK_SHA256SUM0 0xfff0707f
+#define MATCH_SHA256SUM1 0x10101013
+#define MASK_SHA256SUM1 0xfff0707f
+#define MATCH_SHA256SIG0 0x10201013
+#define MASK_SHA256SIG0 0xfff0707f
+#define MATCH_SHA256SIG1 0x10301013
+#define MASK_SHA256SIG1 0xfff0707f
+#define MATCH_SHA512SUM0R 0x50000033
+#define MASK_SHA512SUM0R 0xfe00707f
+#define MATCH_SHA512SUM1R 0x52000033
+#define MASK_SHA512SUM1R 0xfe00707f
+#define MATCH_SHA512SIG0L 0x54000033
+#define MASK_SHA512SIG0L 0xfe00707f
+#define MATCH_SHA512SIG0H 0x5c000033
+#define MASK_SHA512SIG0H 0xfe00707f
+#define MATCH_SHA512SIG1L 0x56000033
+#define MASK_SHA512SIG1L 0xfe00707f
+#define MATCH_SHA512SIG1H 0x5e000033
+#define MASK_SHA512SIG1H 0xfe00707f
+#define MATCH_SM4ED 0x30000033
+#define MASK_SM4ED 0x3e00707f
+#define MATCH_SM4KS 0x34000033
+#define MASK_SM4KS 0x3e00707f
+#define MATCH_AES32ESMI 0x26000033
+#define MASK_AES32ESMI 0x3e00707f
+#define MATCH_AES32ESI 0x22000033
+#define MASK_AES32ESI 0x3e00707f
+#define MATCH_AES32DSMI 0x2e000033
+#define MASK_AES32DSMI 0x3e00707f
+#define MATCH_AES32DSI 0x2a000033
+#define MASK_AES32DSI 0x3e00707f
+#define MATCH_SHA512SUM0 0x10401013
+#define MASK_SHA512SUM0 0xfff0707f
+#define MATCH_SHA512SUM1 0x10501013
+#define MASK_SHA512SUM1 0xfff0707f
+#define MATCH_SHA512SIG0 0x10601013
+#define MASK_SHA512SIG0 0xfff0707f
+#define MATCH_SHA512SIG1 0x10701013
+#define MASK_SHA512SIG1 0xfff0707f
+#define MATCH_AES64KS1I 0x31001013
+#define MASK_AES64KS1I 0xff00707f
+#define MATCH_AES64IM 0x30001013
+#define MASK_AES64IM 0xfff0707f
+#define MATCH_AES64KS2 0x7e000033
+#define MASK_AES64KS2 0xfe00707f
+#define MATCH_AES64ESM 0x36000033
+#define MASK_AES64ESM 0xfe00707f
+#define MATCH_AES64ES 0x32000033
+#define MASK_AES64ES 0xfe00707f
+#define MATCH_AES64DSM 0x3e000033
+#define MASK_AES64DSM 0xfe00707f
+#define MATCH_AES64DS 0x3a000033
+#define MASK_AES64DS 0xfe00707f
/* Privileged CSR addresses. */
#define CSR_USTATUS 0x0
#define CSR_UIE 0x4
@@ -884,6 +952,7 @@
#define CSR_TCONTROL 0x7a5
#define CSR_MCONTEXT 0x7a8
#define CSR_SCONTEXT 0x7aa
+#define CSR_SEED 0x015
#endif /* RISCV_ENCODING_H */
#ifdef DECLARE_INSN
DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
@@ -1118,6 +1187,11 @@ DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
+DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
+DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
+DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
+DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4)
+DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8)
DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
@@ -1436,6 +1510,7 @@ DECLARE_CSR(tinfo, CSR_TINFO, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_C
DECLARE_CSR(tcontrol, CSR_TCONTROL, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(scontext, CSR_SCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(seed, CSR_SEED, CSR_CLASS_ZKR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
#endif /* DECLARE_CSR */
#ifdef DECLARE_CSR_ALIAS
DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index afcd41ff1dd..1b5b7cb6ffc 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -261,6 +261,13 @@ static const char * const riscv_pred_succ[16] =
#define OP_MASK_CFUNCT2 0x3
#define OP_SH_CFUNCT2 5
+/* Scalar crypto fields. */
+
+#define OP_SH_BS 30
+#define OP_MASK_BS 3
+#define OP_SH_RNUM 20
+#define OP_MASK_RNUM 0xf
+
/* ABI names for selected x-registers. */
#define X_RA 1
@@ -320,6 +327,17 @@ enum riscv_insn_class
INSN_CLASS_ZBB,
INSN_CLASS_ZBC,
INSN_CLASS_ZBS,
+ INSN_CLASS_ZBKB,
+ INSN_CLASS_ZBKC,
+ INSN_CLASS_ZBKX,
+ INSN_CLASS_ZKND,
+ INSN_CLASS_ZKNE,
+ INSN_CLASS_ZKNH,
+ INSN_CLASS_ZKSED,
+ INSN_CLASS_ZKSH,
+ INSN_CLASS_ZBB_OR_ZBKB,
+ INSN_CLASS_ZBC_OR_ZBKC,
+ INSN_CLASS_ZKND_OR_ZKNE,
};
/* This structure holds information for a particular instruction. */
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index d097c167d1b..86e2e5ab214 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -375,6 +375,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
print (info->stream, "%s", riscv_gpr_names[rd]);
break;
+ case 'y':
+ print (info->stream, "0x%x", (int)EXTRACT_OPERAND (BS, l));
+ break;
+
case 'z':
print (info->stream, "%s", riscv_gpr_names[0]);
break;
@@ -440,6 +444,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
break;
}
+ case 'Y':
+ print (info->stream, "0x%x", (int)EXTRACT_OPERAND (RNUM, l));
+ break;
+
case 'Z':
print (info->stream, "%d", rs1);
break;
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index b756bae64ab..9c6c245432d 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -84,6 +84,8 @@ const char * const riscv_fpr_names_abi[NFPR] =
#define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
#define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
#define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
+#define MATCH_SHAMT_BREV8 (0b00111 << OP_SH_SHAMT)
+#define MATCH_SHAMT_ZIP_32 (0b1111 << OP_SH_SHAMT)
#define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
static int
@@ -783,7 +785,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
-/* Zbb instructions */
+/* Zbb or zbkb instructions */
{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
{"cpop", 0, INSN_CLASS_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
@@ -798,23 +800,30 @@ const struct riscv_opcode riscv_opcodes[] =
{"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 },
{"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 },
{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
-{"andn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
-{"orn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
-{"xnor", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
-{"rol", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
-{"rori", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
-{"ror", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
-{"ror", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
-{"rev8", 32, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_32 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
-{"rev8", 64, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_64 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
{"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI | MATCH_SHAMT_ORC_B, MASK_GORCI | MASK_SHAMT, match_opcode, 0 },
{"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
{"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
{"cpopw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
-{"rolw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
-{"roriw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
-{"rorw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
-{"rorw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
+{"brev8", 32, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
+{"brev8", 64, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
+{"zip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
+{"unzip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
+{"pack", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 },
+{"packh", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
+{"packw", 64, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
+{"andn", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
+{"orn", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
+{"xnor", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
+{"rol", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
+{"rori", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
+{"ror", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
+{"ror", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
+{"rev8", 32, INSN_CLASS_ZBB_OR_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_32, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
+{"rev8", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_64, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
+{"rolw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
+{"roriw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
+{"rorw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
+{"rorw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
/* Zba instructions */
{"sh1add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
@@ -828,9 +837,9 @@ const struct riscv_opcode riscv_opcodes[] =
{"add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
{"slli.uw", 64, INSN_CLASS_ZBA, "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
-/* Zbc instructions */
-{"clmul", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
-{"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
+/* Zbc or zbkc instructions */
+{"clmul", 0, INSN_CLASS_ZBC_OR_ZBKC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
+{"clmulh", 0, INSN_CLASS_ZBC_OR_ZBKC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
{"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
/* Zbs instructions */
@@ -847,6 +856,49 @@ const struct riscv_opcode riscv_opcodes[] =
{"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
{"bext", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
+/* Zbkx instructions */
+{"xperm4", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM4, MASK_XPERM4, match_opcode, 0 },
+{"xperm8", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM8, MASK_XPERM8, match_opcode, 0 },
+
+/* Zknd instructions */
+{"aes32dsi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSI, MASK_AES32DSI, match_opcode, 0 },
+{"aes32dsmi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSMI, MASK_AES32DSMI, match_opcode, 0 },
+{"aes64ds", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DS, MASK_AES64DS, match_opcode, 0 },
+{"aes64dsm", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DSM, MASK_AES64DSM, match_opcode, 0 },
+{"aes64im", 64, INSN_CLASS_ZKND, "d,s", MATCH_AES64IM, MASK_AES64IM, match_opcode, 0 },
+{"aes64ks1i", 64, INSN_CLASS_ZKND_OR_ZKNE, "d,s,Y", MATCH_AES64KS1I, MASK_AES64KS1I, match_opcode, 0 },
+{"aes64ks2", 64, INSN_CLASS_ZKND_OR_ZKNE, "d,s,t", MATCH_AES64KS2, MASK_AES64KS2, match_opcode, 0 },
+
+/* Zkne instructions */
+{"aes32esi", 32, INSN_CLASS_ZKNE, "d,s,t,y", MATCH_AES32ESI, MASK_AES32ESI, match_opcode, 0 },
+{"aes32esmi", 32, INSN_CLASS_ZKNE, "d,s,t,y", MATCH_AES32ESMI, MASK_AES32ESMI, match_opcode, 0 },
+{"aes64es", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ES, MASK_AES64ES, match_opcode, 0 },
+{"aes64esm", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ESM, MASK_AES64ESM, match_opcode, 0 },
+
+/* Zknh instructions */
+{"sha256sig0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG0, MASK_SHA256SIG0, match_opcode, 0 },
+{"sha256sig1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG1, MASK_SHA256SIG1, match_opcode, 0 },
+{"sha256sum0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM0, MASK_SHA256SUM0, match_opcode, 0 },
+{"sha256sum1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM1, MASK_SHA256SUM1, match_opcode, 0 },
+{"sha512sig0h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0H, MASK_SHA512SIG0H, match_opcode, 0 },
+{"sha512sig0l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0L, MASK_SHA512SIG0L, match_opcode, 0 },
+{"sha512sig1h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1H, MASK_SHA512SIG1H, match_opcode, 0 },
+{"sha512sig1l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1L, MASK_SHA512SIG1L, match_opcode, 0 },
+{"sha512sum0r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM0R, MASK_SHA512SUM0R, match_opcode, 0 },
+{"sha512sum1r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM1R, MASK_SHA512SUM1R, match_opcode, 0 },
+{"sha512sig0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG0, MASK_SHA512SIG0, match_opcode, 0 },
+{"sha512sig1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG1, MASK_SHA512SIG1, match_opcode, 0 },
+{"sha512sum0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM0, MASK_SHA512SUM0, match_opcode, 0 },
+{"sha512sum1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM1, MASK_SHA512SUM1, match_opcode, 0 },
+
+/* Zksed instructions */
+{"sm4ed", 0, INSN_CLASS_ZKSED, "d,s,t,y", MATCH_SM4ED, MASK_SM4ED, match_opcode, 0 },
+{"sm4ks", 0, INSN_CLASS_ZKSED, "d,s,t,y", MATCH_SM4KS, MASK_SM4KS, match_opcode, 0 },
+
+/* Zksh instructions */
+{"sm3p0", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P0, MASK_SM3P0, match_opcode, 0 },
+{"sm3p1", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P1, MASK_SM3P1, match_opcode, 0 },
+
/* Terminate the list. */
{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
};
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v4 3/3] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases
2021-11-15 3:03 [PATCH v4 0/3] RISC-V: Support Scalar Cryptography extension jiawei
2021-11-15 3:03 ` [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension jiawei
2021-11-15 3:03 ` [PATCH v4 2/3] RISC-V: Scalar crypto instructions and operand set jiawei
@ 2021-11-15 3:03 ` jiawei
2021-12-21 16:06 ` Jan Beulich
2021-11-16 4:07 ` [PATCH v4 0/3] RISC-V: Support Scalar Cryptography extension Nelson Chu
3 siblings, 1 reply; 16+ messages in thread
From: jiawei @ 2021-11-15 3:03 UTC (permalink / raw)
To: binutils
Cc: kito.cheng, nelson.chu, jimw, philipp.tomsich, mjos,
ben.marshall, cmuellner, palmer, andrew, lazyparser, siyu,
schwab, jbeulich, jiawei
Add testcases for Scalar Crypto extension, with total testcase contain all instructions in k-ext/k-ext-64 and sub-extension testcase for zbk* zk*. Also add testcase for new CSR name 'seed' which is the Entropy Source in zkr.
---
gas/testsuite/gas/riscv/k-ext-64.d | 47 +++++++++++++++++++
gas/testsuite/gas/riscv/k-ext-64.s | 38 +++++++++++++++
gas/testsuite/gas/riscv/k-ext.d | 44 +++++++++++++++++
gas/testsuite/gas/riscv/k-ext.s | 35 ++++++++++++++
.../gas/riscv/priv-reg-fail-version-1p10.d | 2 +-
.../gas/riscv/priv-reg-fail-version-1p11.d | 2 +-
.../gas/riscv/priv-reg-fail-version-1p9p1.d | 2 +-
.../gas/riscv/priv-reg-version-1p10.d | 1 +
.../gas/riscv/priv-reg-version-1p11.d | 1 +
.../gas/riscv/priv-reg-version-1p9p1.d | 1 +
gas/testsuite/gas/riscv/priv-reg.s | 3 ++
gas/testsuite/gas/riscv/zbkb-32.d | 22 +++++++++
gas/testsuite/gas/riscv/zbkb-32.s | 13 +++++
gas/testsuite/gas/riscv/zbkb-64.d | 24 ++++++++++
gas/testsuite/gas/riscv/zbkb-64.s | 15 ++++++
gas/testsuite/gas/riscv/zbkc-32.d | 12 +++++
gas/testsuite/gas/riscv/zbkc-64.d | 12 +++++
gas/testsuite/gas/riscv/zbkc.s | 3 ++
gas/testsuite/gas/riscv/zbkx-32.d | 12 +++++
gas/testsuite/gas/riscv/zbkx-64.d | 12 +++++
gas/testsuite/gas/riscv/zbkx.s | 3 ++
gas/testsuite/gas/riscv/zknd-32.d | 12 +++++
gas/testsuite/gas/riscv/zknd-32.s | 3 ++
gas/testsuite/gas/riscv/zknd-64.d | 15 ++++++
gas/testsuite/gas/riscv/zknd-64.s | 6 +++
gas/testsuite/gas/riscv/zkne-32.d | 12 +++++
gas/testsuite/gas/riscv/zkne-32.s | 3 ++
gas/testsuite/gas/riscv/zkne-64.d | 14 ++++++
gas/testsuite/gas/riscv/zkne-64.s | 5 ++
gas/testsuite/gas/riscv/zknh-32.d | 20 ++++++++
gas/testsuite/gas/riscv/zknh-32.s | 11 +++++
gas/testsuite/gas/riscv/zknh-64.d | 18 +++++++
gas/testsuite/gas/riscv/zknh-64.s | 9 ++++
gas/testsuite/gas/riscv/zksed-32.d | 12 +++++
gas/testsuite/gas/riscv/zksed-64.d | 12 +++++
gas/testsuite/gas/riscv/zksed.s | 3 ++
gas/testsuite/gas/riscv/zksh-32.d | 12 +++++
gas/testsuite/gas/riscv/zksh-64.d | 12 +++++
gas/testsuite/gas/riscv/zksh.s | 3 ++
39 files changed, 483 insertions(+), 3 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/k-ext-64.d
create mode 100644 gas/testsuite/gas/riscv/k-ext-64.s
create mode 100644 gas/testsuite/gas/riscv/k-ext.d
create mode 100644 gas/testsuite/gas/riscv/k-ext.s
create mode 100644 gas/testsuite/gas/riscv/zbkb-32.d
create mode 100644 gas/testsuite/gas/riscv/zbkb-32.s
create mode 100644 gas/testsuite/gas/riscv/zbkb-64.d
create mode 100644 gas/testsuite/gas/riscv/zbkb-64.s
create mode 100644 gas/testsuite/gas/riscv/zbkc-32.d
create mode 100644 gas/testsuite/gas/riscv/zbkc-64.d
create mode 100644 gas/testsuite/gas/riscv/zbkc.s
create mode 100644 gas/testsuite/gas/riscv/zbkx-32.d
create mode 100644 gas/testsuite/gas/riscv/zbkx-64.d
create mode 100644 gas/testsuite/gas/riscv/zbkx.s
create mode 100644 gas/testsuite/gas/riscv/zknd-32.d
create mode 100644 gas/testsuite/gas/riscv/zknd-32.s
create mode 100644 gas/testsuite/gas/riscv/zknd-64.d
create mode 100644 gas/testsuite/gas/riscv/zknd-64.s
create mode 100644 gas/testsuite/gas/riscv/zkne-32.d
create mode 100644 gas/testsuite/gas/riscv/zkne-32.s
create mode 100644 gas/testsuite/gas/riscv/zkne-64.d
create mode 100644 gas/testsuite/gas/riscv/zkne-64.s
create mode 100644 gas/testsuite/gas/riscv/zknh-32.d
create mode 100644 gas/testsuite/gas/riscv/zknh-32.s
create mode 100644 gas/testsuite/gas/riscv/zknh-64.d
create mode 100644 gas/testsuite/gas/riscv/zknh-64.s
create mode 100644 gas/testsuite/gas/riscv/zksed-32.d
create mode 100644 gas/testsuite/gas/riscv/zksed-64.d
create mode 100644 gas/testsuite/gas/riscv/zksed.s
create mode 100644 gas/testsuite/gas/riscv/zksh-32.d
create mode 100644 gas/testsuite/gas/riscv/zksh-64.d
create mode 100644 gas/testsuite/gas/riscv/zksh.s
diff --git a/gas/testsuite/gas/riscv/k-ext-64.d b/gas/testsuite/gas/riscv/k-ext-64.d
new file mode 100644
index 00000000000..06f47566ac8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/k-ext-64.d
@@ -0,0 +1,47 @@
+#as: -march=rv64i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt
+#source: k-ext-64.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+ror[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rol[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rori[ ]+a0,a1,0x2
+[ ]+.*:[ ]+.*[ ]+rorw[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rolw[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+roriw[ ]+a0,a1,0x2
+[ ]+.*:[ ]+.*[ ]+andn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+orn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xnor[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+pack[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+packh[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+packw[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+brev8[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+rev8[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+clmul[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+clmulh[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xperm4[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xperm8[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64ds[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64dsm[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64im[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+aes64ks1i[ ]+a0,a1,0x4
+[ ]+.*:[ ]+.*[ ]+aes64ks2[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64es[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64esm[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha256sig0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sig1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sig0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sig1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sum0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sum1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sm4ed[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sm4ks[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sm3p0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sm3p1[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/k-ext-64.s b/gas/testsuite/gas/riscv/k-ext-64.s
new file mode 100644
index 00000000000..302b82ea005
--- /dev/null
+++ b/gas/testsuite/gas/riscv/k-ext-64.s
@@ -0,0 +1,38 @@
+target:
+ ror a0, a1, a2
+ rol a0, a1, a2
+ rori a0, a1, 2
+ rorw a0, a1, a2
+ rolw a0, a1, a2
+ roriw a0, a1, 2
+ andn a0, a1, a2
+ orn a0, a1, a2
+ xnor a0, a1, a2
+ pack a0, a1, a2
+ packh a0, a1, a2
+ packw a0, a1, a2
+ brev8 a0, a0
+ rev8 a0, a0
+ clmul a0, a1, a2
+ clmulh a0, a1, a2
+ xperm4 a0, a1, a2
+ xperm8 a0, a1, a2
+ aes64ds a0, a1, a2
+ aes64dsm a0, a1, a2
+ aes64im a0, a0
+ aes64ks1i a0, a1, 4
+ aes64ks2 a0, a1, a2
+ aes64es a0, a1, a2
+ aes64esm a0, a1, a2
+ sha256sig0 a0, a0
+ sha256sig1 a0, a0
+ sha256sum0 a0, a0
+ sha256sum1 a0, a0
+ sha512sig0 a0, a0
+ sha512sig1 a0, a0
+ sha512sum0 a0, a0
+ sha512sum1 a0, a0
+ sm4ed a0, a1, a2, 2
+ sm4ks a0, a1, a2, 2
+ sm3p0 a0, a0
+ sm3p1 a0, a0
diff --git a/gas/testsuite/gas/riscv/k-ext.d b/gas/testsuite/gas/riscv/k-ext.d
new file mode 100644
index 00000000000..3ba65aadc74
--- /dev/null
+++ b/gas/testsuite/gas/riscv/k-ext.d
@@ -0,0 +1,44 @@
+#as: -march=rv32i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt
+#source: k-ext.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+ror[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rol[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rori[ ]+a0,a1,0x2
+[ ]+.*:[ ]+.*[ ]+andn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+orn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xnor[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+pack[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+packh[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+brev8[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+rev8[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+zip[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+unzip[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+clmul[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+clmulh[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xperm4[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xperm8[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes32dsi[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+aes32dsmi[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+aes32esi[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+aes32esmi[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sha256sig0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sig1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sig0h[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sig0l[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sig1h[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sig1l[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sum0r[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sum1r[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sm4ed[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sm4ks[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sm3p0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sm3p1[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/k-ext.s b/gas/testsuite/gas/riscv/k-ext.s
new file mode 100644
index 00000000000..8eb27684710
--- /dev/null
+++ b/gas/testsuite/gas/riscv/k-ext.s
@@ -0,0 +1,35 @@
+target:
+ ror a0, a1, a2
+ rol a0, a1, a2
+ rori a0, a1, 2
+ andn a0, a1, a2
+ orn a0, a1, a2
+ xnor a0, a1, a2
+ pack a0, a1, a2
+ packh a0, a1, a2
+ brev8 a0, a0
+ rev8 a0, a0
+ zip a0, a0
+ unzip a0, a0
+ clmul a0, a1, a2
+ clmulh a0, a1, a2
+ xperm4 a0, a1, a2
+ xperm8 a0, a1, a2
+ aes32dsi a0, a1, a2, 2
+ aes32dsmi a0, a1, a2, 2
+ aes32esi a0, a1, a2, 2
+ aes32esmi a0, a1, a2, 2
+ sha256sig0 a0, a0
+ sha256sig1 a0, a0
+ sha256sum0 a0, a0
+ sha256sum1 a0, a0
+ sha512sig0h a0, a1, a2
+ sha512sig0l a0, a1, a2
+ sha512sig1h a0, a1, a2
+ sha512sig1l a0, a1, a2
+ sha512sum0r a0, a1, a2
+ sha512sum1r a0, a1, a2
+ sm4ed a0, a1, a2, 2
+ sm4ks a0, a1, a2, 2
+ sm3p0 a0, a0
+ sm3p1 a0, a0
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
index 07cf05a9c29..5f2a387e0e0 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
@@ -1,4 +1,4 @@
-#as: -march=rv32if -mcsr-check -mpriv-spec=1.10 -march-attr
+#as: -march=rv32ifzkr -mcsr-check -mpriv-spec=1.10 -march-attr
#source: priv-reg.s
#warning_output: priv-reg-fail-version-1p10.l
#readelf: -A
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
index bf4b1db3ed6..5b13b2f8edc 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
@@ -1,4 +1,4 @@
-#as: -march=rv32if -mcsr-check -mpriv-spec=1.11 -march-attr
+#as: -march=rv32ifzkr -mcsr-check -mpriv-spec=1.11 -march-attr
#source: priv-reg.s
#warning_output: priv-reg-fail-version-1p11.l
#readelf: -A
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
index e2c33d81dc8..c5d413a5129 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
@@ -1,4 +1,4 @@
-#as: -march=rv32if -mcsr-check -mpriv-spec=1.9.1 -march-attr
+#as: -march=rv32ifzkr -mcsr-check -mpriv-spec=1.9.1 -march-attr
#source: priv-reg.s
#warning_output: priv-reg-fail-version-1p9p1.l
#readelf: -A
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
index 3ad8eebe851..78c683d3dea 100644
--- a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
@@ -265,3 +265,4 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
index 5824bc5e1f6..6c1cc70479b 100644
--- a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
@@ -265,3 +265,4 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
index 569b9587e29..3d2ab74eb35 100644
--- a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
@@ -265,3 +265,4 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed
diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
index c40d28862b7..85ff2a6f466 100644
--- a/gas/testsuite/gas/riscv/priv-reg.s
+++ b/gas/testsuite/gas/riscv/priv-reg.s
@@ -282,3 +282,6 @@
csr etrigger # 0x7a1, alias to tdata1
csr textra32 # 0x7a3, alias to tdata3
csr textra64 # 0x7a3, alias to tdata3
+
+ # Scalar crypto
+ csr seed # 0x015, Entropy Source
diff --git a/gas/testsuite/gas/riscv/zbkb-32.d b/gas/testsuite/gas/riscv/zbkb-32.d
new file mode 100644
index 00000000000..75a9259c5d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkb-32.d
@@ -0,0 +1,22 @@
+#as: -march=rv32i_zbkb
+#source: zbkb-32.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+ror[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rol[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rori[ ]+a0,a1,0x2
+[ ]+.*:[ ]+.*[ ]+andn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+orn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xnor[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+pack[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+packh[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+brev8[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+rev8[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+zip[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+unzip[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zbkb-32.s b/gas/testsuite/gas/riscv/zbkb-32.s
new file mode 100644
index 00000000000..6f917154517
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkb-32.s
@@ -0,0 +1,13 @@
+target:
+ ror a0, a1, a2
+ rol a0, a1, a2
+ rori a0, a1, 2
+ andn a0, a1, a2
+ orn a0, a1, a2
+ xnor a0, a1, a2
+ pack a0, a1, a2
+ packh a0, a1, a2
+ brev8 a0, a0
+ rev8 a0, a0
+ zip a0, a0
+ unzip a0, a0
diff --git a/gas/testsuite/gas/riscv/zbkb-64.d b/gas/testsuite/gas/riscv/zbkb-64.d
new file mode 100644
index 00000000000..2f51db19f06
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkb-64.d
@@ -0,0 +1,24 @@
+#as: -march=rv64i_zbkb
+#source: zbkb-64.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+ror[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rol[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rori[ ]+a0,a1,0x2
+[ ]+.*:[ ]+.*[ ]+rorw[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+rolw[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+roriw[ ]+a0,a1,0x2
+[ ]+.*:[ ]+.*[ ]+andn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+orn[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xnor[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+pack[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+packh[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+packw[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+brev8[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+rev8[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zbkb-64.s b/gas/testsuite/gas/riscv/zbkb-64.s
new file mode 100644
index 00000000000..b5cf79f890e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkb-64.s
@@ -0,0 +1,15 @@
+target:
+ ror a0, a1, a2
+ rol a0, a1, a2
+ rori a0, a1, 2
+ rorw a0, a1, a2
+ rolw a0, a1, a2
+ roriw a0, a1, 2
+ andn a0, a1, a2
+ orn a0, a1, a2
+ xnor a0, a1, a2
+ pack a0, a1, a2
+ packh a0, a1, a2
+ packw a0, a1, a2
+ brev8 a0, a0
+ rev8 a0, a0
diff --git a/gas/testsuite/gas/riscv/zbkc-32.d b/gas/testsuite/gas/riscv/zbkc-32.d
new file mode 100644
index 00000000000..7052f4be451
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkc-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zbkc
+#source: zbkc.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+clmul[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+clmulh[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbkc-64.d b/gas/testsuite/gas/riscv/zbkc-64.d
new file mode 100644
index 00000000000..1620ea9c8db
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkc-64.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i_zbkc
+#source: zbkc.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+clmul[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+clmulh[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbkc.s b/gas/testsuite/gas/riscv/zbkc.s
new file mode 100644
index 00000000000..2a987746e7b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkc.s
@@ -0,0 +1,3 @@
+target:
+ clmul a0, a1, a2
+ clmulh a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zbkx-32.d b/gas/testsuite/gas/riscv/zbkx-32.d
new file mode 100644
index 00000000000..3306ab42e32
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkx-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zbkx
+#source: zbkx.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+xperm4[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xperm8[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbkx-64.d b/gas/testsuite/gas/riscv/zbkx-64.d
new file mode 100644
index 00000000000..95cca8e9049
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkx-64.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i_zbkx
+#source: zbkx.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+xperm4[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+xperm8[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbkx.s b/gas/testsuite/gas/riscv/zbkx.s
new file mode 100644
index 00000000000..8c3077105fe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkx.s
@@ -0,0 +1,3 @@
+target:
+ xperm4 a0, a1, a2
+ xperm8 a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zknd-32.d b/gas/testsuite/gas/riscv/zknd-32.d
new file mode 100644
index 00000000000..4571261e494
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknd-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zknd
+#source: zknd-32.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+aes32dsi[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+aes32dsmi[ ]+a0,a1,a2,0x2
diff --git a/gas/testsuite/gas/riscv/zknd-32.s b/gas/testsuite/gas/riscv/zknd-32.s
new file mode 100644
index 00000000000..0d09badd1c6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknd-32.s
@@ -0,0 +1,3 @@
+target:
+ aes32dsi a0, a1, a2, 2
+ aes32dsmi a0, a1, a2, 2
diff --git a/gas/testsuite/gas/riscv/zknd-64.d b/gas/testsuite/gas/riscv/zknd-64.d
new file mode 100644
index 00000000000..e12b3ef204b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknd-64.d
@@ -0,0 +1,15 @@
+#as: -march=rv64i_zknd
+#source: zknd-64.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+aes64ds[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64dsm[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64im[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+aes64ks1i[ ]+a0,a1,0x4
+[ ]+.*:[ ]+.*[ ]+aes64ks2[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zknd-64.s b/gas/testsuite/gas/riscv/zknd-64.s
new file mode 100644
index 00000000000..4846e93c16f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknd-64.s
@@ -0,0 +1,6 @@
+target:
+ aes64ds a0, a1, a2
+ aes64dsm a0, a1, a2
+ aes64im a0, a0
+ aes64ks1i a0, a1, 4
+ aes64ks2 a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zkne-32.d b/gas/testsuite/gas/riscv/zkne-32.d
new file mode 100644
index 00000000000..2f5735971cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zkne-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zkne
+#source: zkne-32.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+aes32esi[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+aes32esmi[ ]+a0,a1,a2,0x2
diff --git a/gas/testsuite/gas/riscv/zkne-32.s b/gas/testsuite/gas/riscv/zkne-32.s
new file mode 100644
index 00000000000..f864fc1778b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zkne-32.s
@@ -0,0 +1,3 @@
+target:
+ aes32esi a0, a1, a2, 2
+ aes32esmi a0, a1, a2, 2
diff --git a/gas/testsuite/gas/riscv/zkne-64.d b/gas/testsuite/gas/riscv/zkne-64.d
new file mode 100644
index 00000000000..6f6e9c31116
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zkne-64.d
@@ -0,0 +1,14 @@
+#as: -march=rv64i_zkne
+#source: zkne-64.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+aes64es[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64esm[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+aes64ks1i[ ]+a0,a1,0x4
+[ ]+.*:[ ]+.*[ ]+aes64ks2[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zkne-64.s b/gas/testsuite/gas/riscv/zkne-64.s
new file mode 100644
index 00000000000..9b5612001af
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zkne-64.s
@@ -0,0 +1,5 @@
+target:
+ aes64es a0, a1, a2
+ aes64esm a0, a1, a2
+ aes64ks1i a0, a1, 4
+ aes64ks2 a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zknh-32.d b/gas/testsuite/gas/riscv/zknh-32.d
new file mode 100644
index 00000000000..ac4b2447629
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknh-32.d
@@ -0,0 +1,20 @@
+#as: -march=rv32i_zknh
+#source: zknh-32.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+sha256sig0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sig1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sig0h[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sig0l[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sig1h[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sig1l[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sum0r[ ]+a0,a1,a2
+[ ]+.*:[ ]+.*[ ]+sha512sum1r[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zknh-32.s b/gas/testsuite/gas/riscv/zknh-32.s
new file mode 100644
index 00000000000..dc2cd3c6657
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknh-32.s
@@ -0,0 +1,11 @@
+target:
+ sha256sig0 a0, a0
+ sha256sig1 a0, a0
+ sha256sum0 a0, a0
+ sha256sum1 a0, a0
+ sha512sig0h a0, a1, a2
+ sha512sig0l a0, a1, a2
+ sha512sig1h a0, a1, a2
+ sha512sig1l a0, a1, a2
+ sha512sum0r a0, a1, a2
+ sha512sum1r a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zknh-64.d b/gas/testsuite/gas/riscv/zknh-64.d
new file mode 100644
index 00000000000..890d5d826f3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknh-64.d
@@ -0,0 +1,18 @@
+#as: -march=rv64i_zknh
+#source: zknh-64.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+sha256sig0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sig1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha256sum1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sig0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sig1[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sum0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sha512sum1[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zknh-64.s b/gas/testsuite/gas/riscv/zknh-64.s
new file mode 100644
index 00000000000..897dc0ba32e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zknh-64.s
@@ -0,0 +1,9 @@
+target:
+ sha256sig0 a0, a0
+ sha256sig1 a0, a0
+ sha256sum0 a0, a0
+ sha256sum1 a0, a0
+ sha512sig0 a0, a0
+ sha512sig1 a0, a0
+ sha512sum0 a0, a0
+ sha512sum1 a0, a0
diff --git a/gas/testsuite/gas/riscv/zksed-32.d b/gas/testsuite/gas/riscv/zksed-32.d
new file mode 100644
index 00000000000..228130ae4c1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zksed-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zksed
+#source: zksed.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+sm4ed[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sm4ks[ ]+a0,a1,a2,0x2
diff --git a/gas/testsuite/gas/riscv/zksed-64.d b/gas/testsuite/gas/riscv/zksed-64.d
new file mode 100644
index 00000000000..9a4efdff649
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zksed-64.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i_zksed
+#source: zksed.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+sm4ed[ ]+a0,a1,a2,0x2
+[ ]+.*:[ ]+.*[ ]+sm4ks[ ]+a0,a1,a2,0x2
diff --git a/gas/testsuite/gas/riscv/zksed.s b/gas/testsuite/gas/riscv/zksed.s
new file mode 100644
index 00000000000..ee95c7a8584
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zksed.s
@@ -0,0 +1,3 @@
+target:
+ sm4ed a0, a1, a2, 2
+ sm4ks a0, a1, a2, 2
diff --git a/gas/testsuite/gas/riscv/zksh-32.d b/gas/testsuite/gas/riscv/zksh-32.d
new file mode 100644
index 00000000000..ab22b3f1f4f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zksh-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zksh
+#source: zksh.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+sm3p0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sm3p1[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zksh-64.d b/gas/testsuite/gas/riscv/zksh-64.d
new file mode 100644
index 00000000000..91a3f16e511
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zksh-64.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i_zksh
+#source: zksh.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+.*:[ ]+.*[ ]+sm3p0[ ]+a0,a0
+[ ]+.*:[ ]+.*[ ]+sm3p1[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zksh.s b/gas/testsuite/gas/riscv/zksh.s
new file mode 100644
index 00000000000..b321c26f2b2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zksh.s
@@ -0,0 +1,3 @@
+target:
+ sm3p0 a0, a0
+ sm3p1 a0, a0
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 0/3] RISC-V: Support Scalar Cryptography extension
2021-11-15 3:03 [PATCH v4 0/3] RISC-V: Support Scalar Cryptography extension jiawei
` (2 preceding siblings ...)
2021-11-15 3:03 ` [PATCH v4 3/3] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases jiawei
@ 2021-11-16 4:07 ` Nelson Chu
3 siblings, 0 replies; 16+ messages in thread
From: Nelson Chu @ 2021-11-16 4:07 UTC (permalink / raw)
To: jiawei
Cc: Binutils, Kito Cheng, Jim Wilson, Philipp Tomsich, mjos,
ben.marshall, cmuellner, Palmer Dabbelt, Andrew Waterman,
Wei Wu (吴伟),
siyu, Andreas Schwab, Jan Beulich
Hi Guys,
I have added the missing ChangeLogs in the commit comment, and fixed
some minor indent. These k extension patches look good to me, so
committed.
Thanks
Nelson
On Mon, Nov 15, 2021 at 11:04 AM jiawei <jiawei@iscas.ac.cn> wrote:
>
> This patch is support Scalar Cryptography extension(k-ext v1.0.0-rc6) as
> binutils part, you can find gcc patches part in https://github.com/WuSiYu/riscv-gcc/tree/trunk-crypto-rebase by siyu@isrc.iscas.ac.cn.
>
> The first patch fix the order check with 'z' begin sub-extension, it set 'zb' before 'zk' as a right case. Some instruction in 'zbkb' and 'zbkc' is both used by Bitmanip and Scalar Cryptography extension, we just redefine the class with them.
>
> Here is the github repo link contain this patch: https://github.com/pz9115/riscv-binutils-gdb/commits/k-ext-rebase, the old version of this work is form https://github.com/riscv-collab/riscv-binutils-gdb/pull/254, Thanks for Nelson Chu and Jim Wilson's review and help.
>
> Version logs:
>
> v2: Add missing arch "k" in riscv_supported_std_ext[] to make the order check right with "zk" behind "zb" as Neslon Chu's comment.
>
> v3: Remove the trailing spaces as Andreas Schwab's comment. Add commit for each patch and add split testcases into sub-extension tests as Christoph Muellner's comment.
>
> v4: Change letter order in riscv_supported_std_ext[], Move INSN_CLASS_* into follow patch, Fix SHFL/UNSHFL Mask error, Fix typo error, Add CSR_CLASS ZKR for ES_CSR as Neslon Chu's comment.
>
> jiawei (3):
> RISC-V: Minimal support of scalar crypto extension
> RISC-V: Scalar crypto instructions and operand set
> RISC-V: Scalar crypto instruction and Entropy Source CSR testcases
>
> bfd/elfxx-riscv.c | 53 ++++++++++++
> gas/config/tc-riscv.c | 29 +++++++
> gas/testsuite/gas/riscv/k-ext-64.d | 47 ++++++++++
> gas/testsuite/gas/riscv/k-ext-64.s | 38 ++++++++
> gas/testsuite/gas/riscv/k-ext.d | 44 ++++++++++
> gas/testsuite/gas/riscv/k-ext.s | 35 ++++++++
> .../gas/riscv/priv-reg-fail-version-1p10.d | 2 +-
> .../gas/riscv/priv-reg-fail-version-1p11.d | 2 +-
> .../gas/riscv/priv-reg-fail-version-1p9p1.d | 2 +-
> .../gas/riscv/priv-reg-version-1p10.d | 1 +
> .../gas/riscv/priv-reg-version-1p11.d | 1 +
> .../gas/riscv/priv-reg-version-1p9p1.d | 1 +
> gas/testsuite/gas/riscv/priv-reg.s | 3 +
> gas/testsuite/gas/riscv/zbkb-32.d | 22 +++++
> gas/testsuite/gas/riscv/zbkb-32.s | 13 +++
> gas/testsuite/gas/riscv/zbkb-64.d | 24 ++++++
> gas/testsuite/gas/riscv/zbkb-64.s | 15 ++++
> gas/testsuite/gas/riscv/zbkc-32.d | 12 +++
> gas/testsuite/gas/riscv/zbkc-64.d | 12 +++
> gas/testsuite/gas/riscv/zbkc.s | 3 +
> gas/testsuite/gas/riscv/zbkx-32.d | 12 +++
> gas/testsuite/gas/riscv/zbkx-64.d | 12 +++
> gas/testsuite/gas/riscv/zbkx.s | 3 +
> gas/testsuite/gas/riscv/zknd-32.d | 12 +++
> gas/testsuite/gas/riscv/zknd-32.s | 3 +
> gas/testsuite/gas/riscv/zknd-64.d | 15 ++++
> gas/testsuite/gas/riscv/zknd-64.s | 6 ++
> gas/testsuite/gas/riscv/zkne-32.d | 12 +++
> gas/testsuite/gas/riscv/zkne-32.s | 3 +
> gas/testsuite/gas/riscv/zkne-64.d | 14 +++
> gas/testsuite/gas/riscv/zkne-64.s | 5 ++
> gas/testsuite/gas/riscv/zknh-32.d | 20 +++++
> gas/testsuite/gas/riscv/zknh-32.s | 11 +++
> gas/testsuite/gas/riscv/zknh-64.d | 18 ++++
> gas/testsuite/gas/riscv/zknh-64.s | 9 ++
> gas/testsuite/gas/riscv/zksed-32.d | 12 +++
> gas/testsuite/gas/riscv/zksed-64.d | 12 +++
> gas/testsuite/gas/riscv/zksed.s | 3 +
> gas/testsuite/gas/riscv/zksh-32.d | 12 +++
> gas/testsuite/gas/riscv/zksh-64.d | 12 +++
> gas/testsuite/gas/riscv/zksh.s | 3 +
> include/opcode/riscv-opc.h | 75 ++++++++++++++++
> include/opcode/riscv.h | 18 ++++
> opcodes/riscv-dis.c | 8 ++
> opcodes/riscv-opc.c | 86 +++++++++++++++----
> 45 files changed, 735 insertions(+), 20 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/k-ext-64.d
> create mode 100644 gas/testsuite/gas/riscv/k-ext-64.s
> create mode 100644 gas/testsuite/gas/riscv/k-ext.d
> create mode 100644 gas/testsuite/gas/riscv/k-ext.s
> create mode 100644 gas/testsuite/gas/riscv/zbkb-32.d
> create mode 100644 gas/testsuite/gas/riscv/zbkb-32.s
> create mode 100644 gas/testsuite/gas/riscv/zbkb-64.d
> create mode 100644 gas/testsuite/gas/riscv/zbkb-64.s
> create mode 100644 gas/testsuite/gas/riscv/zbkc-32.d
> create mode 100644 gas/testsuite/gas/riscv/zbkc-64.d
> create mode 100644 gas/testsuite/gas/riscv/zbkc.s
> create mode 100644 gas/testsuite/gas/riscv/zbkx-32.d
> create mode 100644 gas/testsuite/gas/riscv/zbkx-64.d
> create mode 100644 gas/testsuite/gas/riscv/zbkx.s
> create mode 100644 gas/testsuite/gas/riscv/zknd-32.d
> create mode 100644 gas/testsuite/gas/riscv/zknd-32.s
> create mode 100644 gas/testsuite/gas/riscv/zknd-64.d
> create mode 100644 gas/testsuite/gas/riscv/zknd-64.s
> create mode 100644 gas/testsuite/gas/riscv/zkne-32.d
> create mode 100644 gas/testsuite/gas/riscv/zkne-32.s
> create mode 100644 gas/testsuite/gas/riscv/zkne-64.d
> create mode 100644 gas/testsuite/gas/riscv/zkne-64.s
> create mode 100644 gas/testsuite/gas/riscv/zknh-32.d
> create mode 100644 gas/testsuite/gas/riscv/zknh-32.s
> create mode 100644 gas/testsuite/gas/riscv/zknh-64.d
> create mode 100644 gas/testsuite/gas/riscv/zknh-64.s
> create mode 100644 gas/testsuite/gas/riscv/zksed-32.d
> create mode 100644 gas/testsuite/gas/riscv/zksed-64.d
> create mode 100644 gas/testsuite/gas/riscv/zksed.s
> create mode 100644 gas/testsuite/gas/riscv/zksh-32.d
> create mode 100644 gas/testsuite/gas/riscv/zksh-64.d
> create mode 100644 gas/testsuite/gas/riscv/zksh.s
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 3/3] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases
2021-11-15 3:03 ` [PATCH v4 3/3] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases jiawei
@ 2021-12-21 16:06 ` Jan Beulich
0 siblings, 0 replies; 16+ messages in thread
From: Jan Beulich @ 2021-12-21 16:06 UTC (permalink / raw)
To: jiawei
Cc: kito.cheng, nelson.chu, jimw, philipp.tomsich, mjos,
ben.marshall, cmuellner, palmer, andrew, lazyparser, siyu,
schwab, binutils
On 15.11.2021 04:03, jiawei wrote:
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/k-ext-64.d
> @@ -0,0 +1,47 @@
> +#as: -march=rv64i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt
> +#source: k-ext-64.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+.*:[ ]+.*[ ]+ror[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+rol[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+rori[ ]+a0,a1,0x2
> +[ ]+.*:[ ]+.*[ ]+rorw[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+rolw[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+roriw[ ]+a0,a1,0x2
> +[ ]+.*:[ ]+.*[ ]+andn[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+orn[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+xnor[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+pack[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+packh[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+packw[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+brev8[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+rev8[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+clmul[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+clmulh[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+xperm4[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+xperm8[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+aes64ds[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+aes64dsm[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+aes64im[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+aes64ks1i[ ]+a0,a1,0x4
> +[ ]+.*:[ ]+.*[ ]+aes64ks2[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+aes64es[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+aes64esm[ ]+a0,a1,a2
> +[ ]+.*:[ ]+.*[ ]+sha256sig0[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+sha256sig1[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+sha256sum0[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+sha256sum1[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+sha512sig0[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+sha512sig1[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+sha512sum0[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+sha512sum1[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+sm4ed[ ]+a0,a1,a2,0x2
> +[ ]+.*:[ ]+.*[ ]+sm4ks[ ]+a0,a1,a2,0x2
> +[ ]+.*:[ ]+.*[ ]+sm3p0[ ]+a0,a0
> +[ ]+.*:[ ]+.*[ ]+sm3p1[ ]+a0,a0
Since most (all) other insn-specific tests are different in this regard,
I wonder whether it is on purpose that the actual encodings get omitted
here (or to be precise, skipped by way of using .* ). Since these tests
serve as both assembler and disassembler ones, I think checking that the
correct encodings get produced (and consumed) would be at least helpful.
Jan
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 2/3] RISC-V: Scalar crypto instructions and operand set
2021-11-15 3:03 ` [PATCH v4 2/3] RISC-V: Scalar crypto instructions and operand set jiawei
@ 2022-01-04 8:04 ` Jan Beulich
2022-01-04 8:38 ` 陈嘉炜
0 siblings, 1 reply; 16+ messages in thread
From: Jan Beulich @ 2022-01-04 8:04 UTC (permalink / raw)
To: jiawei
Cc: kito.cheng, nelson.chu, jimw, philipp.tomsich, mjos,
ben.marshall, cmuellner, palmer, andrew, lazyparser, siyu,
schwab, binutils
On 15.11.2021 04:03, jiawei wrote:
> @@ -847,6 +856,49 @@ const struct riscv_opcode riscv_opcodes[] =
> {"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
> {"bext", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
>
> +/* Zbkx instructions */
> +{"xperm4", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM4, MASK_XPERM4, match_opcode, 0 },
> +{"xperm8", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM8, MASK_XPERM8, match_opcode, 0 },
> +
> +/* Zknd instructions */
> +{"aes32dsi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSI, MASK_AES32DSI, match_opcode, 0 },
> +{"aes32dsmi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSMI, MASK_AES32DSMI, match_opcode, 0 },
For these two and a few more with immediate operands and a trailing 'i'
in the mnemonics: Shouldn't they have i-suffix-less pseudos, matching
other insns with immediate operands?
Jan
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: Re: [PATCH v4 2/3] RISC-V: Scalar crypto instructions and operand set
2022-01-04 8:04 ` Jan Beulich
@ 2022-01-04 8:38 ` 陈嘉炜
2022-01-04 8:49 ` Jan Beulich
0 siblings, 1 reply; 16+ messages in thread
From: 陈嘉炜 @ 2022-01-04 8:38 UTC (permalink / raw)
To: Jan Beulich
Cc: kito.cheng, nelson.chu, jimw, philipp.tomsich, mjos,
ben.marshall, cmuellner, palmer, andrew, lazyparser, siyu,
schwab, binutils
> -----原始邮件-----
> 发件人: "Jan Beulich" <jbeulich@suse.com>
> 发送时间: 2022-01-04 16:04:31 (星期二)
> 收件人: jiawei <jiawei@iscas.ac.cn>
> 抄送: kito.cheng@sifive.com, nelson.chu@sifive.com, jimw@sifive.com, philipp.tomsich@vrull.eu, mjos@pqshield.com, ben.marshall@pqshield.com, cmuellner@ventanamicro.com, palmer@dabbelt.com, andrew@sifive.com, lazyparser@gmail.com, siyu@isrc.iscas.ac.cn, schwab@linux-m68k.org, binutils@sourceware.org
> 主题: Re: [PATCH v4 2/3] RISC-V: Scalar crypto instructions and operand set
>
> On 15.11.2021 04:03, jiawei wrote:
> > @@ -847,6 +856,49 @@ const struct riscv_opcode riscv_opcodes[] =
> > {"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
> > {"bext", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
> >
> > +/* Zbkx instructions */
> > +{"xperm4", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM4, MASK_XPERM4, match_opcode, 0 },
> > +{"xperm8", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM8, MASK_XPERM8, match_opcode, 0 },
> > +
> > +/* Zknd instructions */
> > +{"aes32dsi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSI, MASK_AES32DSI, match_opcode, 0 },
> > +{"aes32dsmi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSMI, MASK_AES32DSMI, match_opcode, 0 },
>
> For these two and a few more with immediate operands and a trailing 'i'
> in the mnemonics: Shouldn't they have i-suffix-less pseudos, matching
> other insns with immediate operands?
>
> Jan
I think the 'i' trailing is just a dinstinguishing symbol in zknd extension, there are no i-suffix-less pseudo definitions in the cryptogrpah extension spec, please check it.
https://github.com/riscv/riscv-crypto/releases/download/v1.0.0-rc6-scalar/riscv-crypto-spec-scalar-1.0.0-rc6.pdf
PLCT Jiawei
</jiawei@iscas.ac.cn></jbeulich@suse.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 2/3] RISC-V: Scalar crypto instructions and operand set
2022-01-04 8:38 ` 陈嘉炜
@ 2022-01-04 8:49 ` Jan Beulich
2022-01-04 13:13 ` Markku-Juhani O. Saarinen
0 siblings, 1 reply; 16+ messages in thread
From: Jan Beulich @ 2022-01-04 8:49 UTC (permalink / raw)
To: 陈嘉炜
Cc: kito.cheng, nelson.chu, jimw, philipp.tomsich, mjos,
ben.marshall, cmuellner, palmer, andrew, lazyparser, siyu,
schwab, binutils
On 04.01.2022 09:38, 陈嘉炜 wrote:
> > -----原始邮件-----
> > 发件人: "Jan Beulich" <jbeulich@suse.com>
> > 发送时间: 2022-01-04 16:04:31 (星期二)
> > 收件人: jiawei <jiawei@iscas.ac.cn>
> > 抄送: kito.cheng@sifive.com, nelson.chu@sifive.com, jimw@sifive.com, philipp.tomsich@vrull.eu, mjos@pqshield.com, ben.marshall@pqshield.com, cmuellner@ventanamicro.com, palmer@dabbelt.com, andrew@sifive.com, lazyparser@gmail.com, siyu@isrc.iscas.ac.cn, schwab@linux-m68k.org, binutils@sourceware.org
> > 主题: Re: [PATCH v4 2/3] RISC-V: Scalar crypto instructions and operand set
> >
> > On 15.11.2021 04:03, jiawei wrote:
> > > @@ -847,6 +856,49 @@ const struct riscv_opcode riscv_opcodes[] =
> > > {"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
> > > {"bext", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
> > >
> > > +/* Zbkx instructions */
> > > +{"xperm4", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM4, MASK_XPERM4, match_opcode, 0 },
> > > +{"xperm8", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM8, MASK_XPERM8, match_opcode, 0 },
> > > +
> > > +/* Zknd instructions */
> > > +{"aes32dsi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSI, MASK_AES32DSI, match_opcode, 0 },
> > > +{"aes32dsmi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSMI, MASK_AES32DSMI, match_opcode, 0 },
> >
> > For these two and a few more with immediate operands and a trailing 'i'
> > in the mnemonics: Shouldn't they have i-suffix-less pseudos, matching
> > other insns with immediate operands?
> >
> > Jan
>
> I think the 'i' trailing is just a dinstinguishing symbol in zknd extension, there are no i-suffix-less pseudo definitions in the cryptogrpah extension spec, please check it.
Perhaps I should have said explicitly that this is a question not so much
on the implementation, but on the spec itself.
Jan
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 2/3] RISC-V: Scalar crypto instructions and operand set
2022-01-04 8:49 ` Jan Beulich
@ 2022-01-04 13:13 ` Markku-Juhani O. Saarinen
0 siblings, 0 replies; 16+ messages in thread
From: Markku-Juhani O. Saarinen @ 2022-01-04 13:13 UTC (permalink / raw)
To: Jan Beulich
Cc: 陈嘉炜,
Kito Cheng, nelson.chu, Jim Wilson, Philipp Tomsich,
Ben Marshall, Christoph Muellner, Palmer Dabbelt,
Andrew Waterman, Wei Wu (吴伟),
siyu, schwab, binutils
On Tue, Jan 4, 2022 at 8:49 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> > > For these two and a few more with immediate operands and a trailing
> 'i'
> > > in the mnemonics: Shouldn't they have i-suffix-less pseudos,
> matching
> > > other insns with immediate operands?
> > >
> > > Jan
> >
> > I think the 'i' trailing is just a dinstinguishing symbol in zknd
> extension, there are no i-suffix-less pseudo definitions in the cryptogrpah
> extension spec, please check it.
>
> Perhaps I should have said explicitly that this is a question not so much
> on the implementation, but on the spec itself.
>
Hi,
I agree that it's a bit odd that sm4* instructions don't have an "i" but
equivalent-format aes32* instructions have it. Hence I wouldn't assign too
much meaning to the "i" here; there is no equivalent "register input"
version for these as there would be with something like "addi" vs "add".
For 32-bit aes/sm4 the immediate refers to a 2-bit field that could have
even been incorporated into the mnemonic (e.g. sm4ed0, sm4ed1, sm4ed2,
sm4ed3) -- to me, these instructions fundamentally have an R-type encoding.
For aes64ks1i it's a 4-bit value holding 0x0..0xA.
If we consider C language intrinsics, passing a variable as an immediate
for K extension instruction needs to be an illegal operation: if the
compiler generates some kind of switch-case statement, that is unlikely to
be constant-time and defeats half of the purpose of the instruction. At
least the inline assembler headers work this way; I hope proper builtins
will fault at attempts to use variables too.
Wrt to "the spec", the Scalar K spec was ratified in November. In the
RISC-V process, ISA ratification means that those mnemonics are beyond
"stable" and "freeze" stages in terms of unmovability. That would require
really serious technical arguments. The consistency of mnemonic and opcode
assignments is really a matter for the top architecture committee chairs,
so even us in the committee that authored that spec did not have final
control over them. Krste & Co changed some of the mnemonics (such as the
names of xperm4 and xperm8) as late as August, before the ratification.
One more thing about intrinsics: If we consider also Bitmanip intrinsics,
my take is that if an instruction has both immediate and register-based
form, it makes obvious sense to combine them into the same intrinsic (e.g.
GREV and GREVI would be better served by a single intrinsic, even though
they are separate mnemonics). K instructions only have one form -- one
avoids confusion by using the mnemonic name to create an intrinsic function
(with a consistent prefix). That's how the current C language intrinsic
proposal works.
Cheers,
- markku
Dr. Markku-Juhani O. Saarinen <mjos@pqshield.com> PQShield, Oxford UK.
>
> Jan
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension
2021-11-15 3:03 ` [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension jiawei
@ 2022-02-21 13:24 ` Jan Beulich
2022-02-21 14:14 ` jiawei
0 siblings, 1 reply; 16+ messages in thread
From: Jan Beulich @ 2022-02-21 13:24 UTC (permalink / raw)
To: jiawei
Cc: kito.cheng, nelson.chu, jimw, philipp.tomsich, mjos,
ben.marshall, cmuellner, palmer, andrew, lazyparser, siyu,
schwab, binutils
On 15.11.2021 04:03, jiawei wrote:
> Minimal support of scalar crypto extension, add "k" in riscv_supported_std_ext[] to make the order check right with "zk" behind "zb". "zbk*" is sub-extension for k-ext, so it added behind "zbs" in riscv_supported_std_z_ext[].
> ---
> bfd/elfxx-riscv.c | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 3ffbaad66dd..152fbe3d160 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1075,6 +1075,20 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
> {"q", "d", check_implicit_always},
> {"d", "f", check_implicit_always},
> {"f", "zicsr", check_implicit_always},
> + {"zk", "zkn", check_implicit_always},
> + {"zk", "zkr", check_implicit_always},
> + {"zk", "zkt", check_implicit_always},
> + {"zkn", "zbkb", check_implicit_always},
> + {"zkn", "zbkc", check_implicit_always},
> + {"zkn", "zbkx", check_implicit_always},
> + {"zkn", "zkne", check_implicit_always},
> + {"zkn", "zknd", check_implicit_always},
> + {"zkn", "zknh", check_implicit_always},
> + {"zks", "zbkb", check_implicit_always},
> + {"zks", "zbkc", check_implicit_always},
> + {"zks", "zbkx", check_implicit_always},
> + {"zks", "zksed", check_implicit_always},
> + {"zks", "zksh", check_implicit_always},
> {NULL, NULL, NULL}
> };
>
> @@ -1127,6 +1141,7 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
> {"c", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
> {"c", ISA_SPEC_CLASS_2P2, 2, 0, 0 },
> {"b", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
> + {"k", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
May I ask what purpose this addition serves? Without its use enabling
smaller scope extensions implicitly, I find it at best unhelpful that
".option arch, +k" is accepted without having any effect.
Jan
> @@ -1146,6 +1161,19 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
> {"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zbkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zbkc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zbkx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zk", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zknd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zkne", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zknh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zkr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zkt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {NULL, 0, 0, 0, 0}
> };
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: Re: [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension
2022-02-21 13:24 ` Jan Beulich
@ 2022-02-21 14:14 ` jiawei
2022-02-21 14:16 ` Philipp Tomsich
0 siblings, 1 reply; 16+ messages in thread
From: jiawei @ 2022-02-21 14:14 UTC (permalink / raw)
To: Jan Beulich
Cc: kito.cheng, nelson.chu, jimw, philipp.tomsich, mjos,
ben.marshall, cmuellner, palmer, andrew, lazyparser, siyu,
schwab, binutils
> -----原始邮件-----
> 发件人: "Jan Beulich" <jbeulich@suse.com>
> 发送时间: 2022-02-21 21:24:11 (星期一)
> 收件人: jiawei <jiawei@iscas.ac.cn>
> 抄送: kito.cheng@sifive.com, nelson.chu@sifive.com, jimw@sifive.com, philipp.tomsich@vrull.eu, mjos@pqshield.com, ben.marshall@pqshield.com, cmuellner@ventanamicro.com, palmer@dabbelt.com, andrew@sifive.com, lazyparser@gmail.com, siyu@isrc.iscas.ac.cn, schwab@linux-m68k.org, binutils@sourceware.org
> 主题: Re: [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension
>
> On 15.11.2021 04:03, jiawei wrote:
> > Minimal support of scalar crypto extension, add "k" in riscv_supported_std_ext[] to make the order check right with "zk" behind "zb". "zbk*" is sub-extension for k-ext, so it added behind "zbs" in riscv_supported_std_z_ext[].
> > ---
> > bfd/elfxx-riscv.c | 28 ++++++++++++++++++++++++++++
> > 1 file changed, 28 insertions(+)
> >
> > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> > index 3ffbaad66dd..152fbe3d160 100644
> > --- a/bfd/elfxx-riscv.c
> > +++ b/bfd/elfxx-riscv.c
> > @@ -1075,6 +1075,20 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
> > {"q", "d", check_implicit_always},
> > {"d", "f", check_implicit_always},
> > {"f", "zicsr", check_implicit_always},
> > + {"zk", "zkn", check_implicit_always},
> > + {"zk", "zkr", check_implicit_always},
> > + {"zk", "zkt", check_implicit_always},
> > + {"zkn", "zbkb", check_implicit_always},
> > + {"zkn", "zbkc", check_implicit_always},
> > + {"zkn", "zbkx", check_implicit_always},
> > + {"zkn", "zkne", check_implicit_always},
> > + {"zkn", "zknd", check_implicit_always},
> > + {"zkn", "zknh", check_implicit_always},
> > + {"zks", "zbkb", check_implicit_always},
> > + {"zks", "zbkc", check_implicit_always},
> > + {"zks", "zbkx", check_implicit_always},
> > + {"zks", "zksed", check_implicit_always},
> > + {"zks", "zksh", check_implicit_always},
> > {NULL, NULL, NULL}
> > };
> >
> > @@ -1127,6 +1141,7 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
> > {"c", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
> > {"c", ISA_SPEC_CLASS_2P2, 2, 0, 0 },
> > {"b", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
> > + {"k", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
>
> May I ask what purpose this addition serves? Without its use enabling
> smaller scope extensions implicitly, I find it at best unhelpful that
> ".option arch, +k" is accepted without having any effect.
>
> Jan
It's same like bitmanip extension, add this will make k extension as a subextension
and set it's canonical order as ISA spec defined.
BR,
Jiawei
>
> > @@ -1146,6 +1161,19 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
> > {"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > {"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > {"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > + {"zbkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > + {"zbkc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > + {"zbkx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > + {"zk", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > + {"zkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > + {"zknd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > + {"zkne", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > + {"zknh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > + {"zkr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > + {"zks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > + {"zksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > + {"zksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > + {"zkt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > {NULL, 0, 0, 0, 0}
> > };
> >
</jiawei@iscas.ac.cn></jbeulich@suse.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: Re: [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension
2022-02-21 14:14 ` jiawei
@ 2022-02-21 14:16 ` Philipp Tomsich
2022-02-21 14:25 ` Jan Beulich
2022-02-21 14:44 ` Tsukasa OI
0 siblings, 2 replies; 16+ messages in thread
From: Philipp Tomsich @ 2022-02-21 14:16 UTC (permalink / raw)
To: jiawei
Cc: Jan Beulich, kito.cheng, nelson.chu, jimw, mjos, ben.marshall,
cmuellner, palmer, andrew, lazyparser, siyu, schwab, binutils
On Mon, 21 Feb 2022 at 15:14, <jiawei@iscas.ac.cn> wrote:
>
>
>
>
> > -----原始邮件-----
> > 发件人: "Jan Beulich" <jbeulich@suse.com>
> > 发送时间: 2022-02-21 21:24:11 (星期一)
> > 收件人: jiawei <jiawei@iscas.ac.cn>
> > 抄送: kito.cheng@sifive.com, nelson.chu@sifive.com, jimw@sifive.com, philipp.tomsich@vrull.eu, mjos@pqshield.com, ben.marshall@pqshield.com, cmuellner@ventanamicro.com, palmer@dabbelt.com, andrew@sifive.com, lazyparser@gmail.com, siyu@isrc.iscas.ac.cn, schwab@linux-m68k.org, binutils@sourceware.org
> > 主题: Re: [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension
> >
> > On 15.11.2021 04:03, jiawei wrote:
> > > Minimal support of scalar crypto extension, add "k" in riscv_supported_std_ext[] to make the order check right with "zk" behind "zb". "zbk*" is sub-extension for k-ext, so it added behind "zbs" in riscv_supported_std_z_ext[].
> > > ---
> > > bfd/elfxx-riscv.c | 28 ++++++++++++++++++++++++++++
> > > 1 file changed, 28 insertions(+)
> > >
> > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> > > index 3ffbaad66dd..152fbe3d160 100644
> > > --- a/bfd/elfxx-riscv.c
> > > +++ b/bfd/elfxx-riscv.c
> > > @@ -1075,6 +1075,20 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
> > > {"q", "d", check_implicit_always},
> > > {"d", "f", check_implicit_always},
> > > {"f", "zicsr", check_implicit_always},
> > > + {"zk", "zkn", check_implicit_always},
> > > + {"zk", "zkr", check_implicit_always},
> > > + {"zk", "zkt", check_implicit_always},
> > > + {"zkn", "zbkb", check_implicit_always},
> > > + {"zkn", "zbkc", check_implicit_always},
> > > + {"zkn", "zbkx", check_implicit_always},
> > > + {"zkn", "zkne", check_implicit_always},
> > > + {"zkn", "zknd", check_implicit_always},
> > > + {"zkn", "zknh", check_implicit_always},
> > > + {"zks", "zbkb", check_implicit_always},
> > > + {"zks", "zbkc", check_implicit_always},
> > > + {"zks", "zbkx", check_implicit_always},
> > > + {"zks", "zksed", check_implicit_always},
> > > + {"zks", "zksh", check_implicit_always},
> > > {NULL, NULL, NULL}
> > > };
> > >
> > > @@ -1127,6 +1141,7 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
> > > {"c", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
> > > {"c", ISA_SPEC_CLASS_2P2, 2, 0, 0 },
> > > {"b", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
> > > + {"k", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
> >
> > May I ask what purpose this addition serves? Without its use enabling
> > smaller scope extensions implicitly, I find it at best unhelpful that
> > ".option arch, +k" is accepted without having any effect.
> >
> > Jan
>
> It's same like bitmanip extension, add this will make k extension as a subextension
> and set it's canonical order as ISA spec defined.
Let me point out that this is not the same as with the
bit-manipulation family of extensions.
Zb[abcs] are all standalone extensions, and there is no Zb.
--Phil.
>
> >
> > > @@ -1146,6 +1161,19 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
> > > {"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > > {"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > > {"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > > + {"zbkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > > + {"zbkc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > > + {"zbkx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > > + {"zk", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > > + {"zkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > > + {"zknd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > > + {"zkne", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > > + {"zknh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > > + {"zkr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > > + {"zks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > > + {"zksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > > + {"zksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > > + {"zkt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > > {NULL, 0, 0, 0, 0}
> > > };
> > >
> </jiawei@iscas.ac.cn></jbeulich@suse.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension
2022-02-21 14:16 ` Philipp Tomsich
@ 2022-02-21 14:25 ` Jan Beulich
2022-02-21 14:44 ` Tsukasa OI
1 sibling, 0 replies; 16+ messages in thread
From: Jan Beulich @ 2022-02-21 14:25 UTC (permalink / raw)
To: Philipp Tomsich, jiawei
Cc: kito.cheng, nelson.chu, jimw, mjos, ben.marshall, cmuellner,
palmer, andrew, lazyparser, siyu, schwab, binutils
On 21.02.2022 15:16, Philipp Tomsich wrote:
> On Mon, 21 Feb 2022 at 15:14, <jiawei@iscas.ac.cn> wrote:
>>
>>
>>
>>
>> > -----原始邮件-----
>> > 发件人: "Jan Beulich" <jbeulich@suse.com>
>> > 发送时间: 2022-02-21 21:24:11 (星期一)
>> > 收件人: jiawei <jiawei@iscas.ac.cn>
>> > 抄送: kito.cheng@sifive.com, nelson.chu@sifive.com, jimw@sifive.com, philipp.tomsich@vrull.eu, mjos@pqshield.com, ben.marshall@pqshield.com, cmuellner@ventanamicro.com, palmer@dabbelt.com, andrew@sifive.com, lazyparser@gmail.com, siyu@isrc.iscas.ac.cn, schwab@linux-m68k.org, binutils@sourceware.org
>> > 主题: Re: [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension
>> >
>> > On 15.11.2021 04:03, jiawei wrote:
>> > > Minimal support of scalar crypto extension, add "k" in riscv_supported_std_ext[] to make the order check right with "zk" behind "zb". "zbk*" is sub-extension for k-ext, so it added behind "zbs" in riscv_supported_std_z_ext[].
>> > > ---
>> > > bfd/elfxx-riscv.c | 28 ++++++++++++++++++++++++++++
>> > > 1 file changed, 28 insertions(+)
>> > >
>> > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
>> > > index 3ffbaad66dd..152fbe3d160 100644
>> > > --- a/bfd/elfxx-riscv.c
>> > > +++ b/bfd/elfxx-riscv.c
>> > > @@ -1075,6 +1075,20 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
>> > > {"q", "d", check_implicit_always},
>> > > {"d", "f", check_implicit_always},
>> > > {"f", "zicsr", check_implicit_always},
>> > > + {"zk", "zkn", check_implicit_always},
>> > > + {"zk", "zkr", check_implicit_always},
>> > > + {"zk", "zkt", check_implicit_always},
>> > > + {"zkn", "zbkb", check_implicit_always},
>> > > + {"zkn", "zbkc", check_implicit_always},
>> > > + {"zkn", "zbkx", check_implicit_always},
>> > > + {"zkn", "zkne", check_implicit_always},
>> > > + {"zkn", "zknd", check_implicit_always},
>> > > + {"zkn", "zknh", check_implicit_always},
>> > > + {"zks", "zbkb", check_implicit_always},
>> > > + {"zks", "zbkc", check_implicit_always},
>> > > + {"zks", "zbkx", check_implicit_always},
>> > > + {"zks", "zksed", check_implicit_always},
>> > > + {"zks", "zksh", check_implicit_always},
>> > > {NULL, NULL, NULL}
>> > > };
>> > >
>> > > @@ -1127,6 +1141,7 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
>> > > {"c", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
>> > > {"c", ISA_SPEC_CLASS_2P2, 2, 0, 0 },
>> > > {"b", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
>> > > + {"k", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
>> >
>> > May I ask what purpose this addition serves? Without its use enabling
>> > smaller scope extensions implicitly, I find it at best unhelpful that
>> > ".option arch, +k" is accepted without having any effect.
>> >
>> > Jan
>>
>> It's same like bitmanip extension, add this will make k extension as a subextension
>> and set it's canonical order as ISA spec defined.
>
> Let me point out that this is not the same as with the
> bit-manipulation family of extensions.
> Zb[abcs] are all standalone extensions, and there is no Zb.
Then there the same question arises: Why does gas accept ".option arch, +b"?
Jan
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension
2022-02-21 14:16 ` Philipp Tomsich
2022-02-21 14:25 ` Jan Beulich
@ 2022-02-21 14:44 ` Tsukasa OI
2022-02-21 14:50 ` Kito Cheng
1 sibling, 1 reply; 16+ messages in thread
From: Tsukasa OI @ 2022-02-21 14:44 UTC (permalink / raw)
To: Philipp Tomsich, jiawei
Cc: ben.marshall, mjos, siyu, cmuellner, binutils, schwab, kito.cheng, jimw
On 2022/02/21 23:16, Philipp Tomsich wrote:
> On Mon, 21 Feb 2022 at 15:14, <jiawei@iscas.ac.cn> wrote:
>>
>>
>>
>>
>> > -----原始邮件-----
>> > 发件人: "Jan Beulich" <jbeulich@suse.com>
>> > 发送时间: 2022-02-21 21:24:11 (星期一)
>> > 收件人: jiawei <jiawei@iscas.ac.cn>
>> > 抄送: kito.cheng@sifive.com, nelson.chu@sifive.com, jimw@sifive.com, philipp.tomsich@vrull.eu, mjos@pqshield.com, ben.marshall@pqshield.com, cmuellner@ventanamicro.com, palmer@dabbelt.com, andrew@sifive.com, lazyparser@gmail.com, siyu@isrc.iscas.ac.cn, schwab@linux-m68k.org, binutils@sourceware.org
>> > 主题: Re: [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension
>> >
>> > On 15.11.2021 04:03, jiawei wrote:
>> > > Minimal support of scalar crypto extension, add "k" in riscv_supported_std_ext[] to make the order check right with "zk" behind "zb". "zbk*" is sub-extension for k-ext, so it added behind "zbs" in riscv_supported_std_z_ext[].
>> > > ---
>> > > bfd/elfxx-riscv.c | 28 ++++++++++++++++++++++++++++
>> > > 1 file changed, 28 insertions(+)
>> > >
>> > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
>> > > index 3ffbaad66dd..152fbe3d160 100644
>> > > --- a/bfd/elfxx-riscv.c
>> > > +++ b/bfd/elfxx-riscv.c
>> > > @@ -1075,6 +1075,20 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
>> > > {"q", "d", check_implicit_always},
>> > > {"d", "f", check_implicit_always},
>> > > {"f", "zicsr", check_implicit_always},
>> > > + {"zk", "zkn", check_implicit_always},
>> > > + {"zk", "zkr", check_implicit_always},
>> > > + {"zk", "zkt", check_implicit_always},
>> > > + {"zkn", "zbkb", check_implicit_always},
>> > > + {"zkn", "zbkc", check_implicit_always},
>> > > + {"zkn", "zbkx", check_implicit_always},
>> > > + {"zkn", "zkne", check_implicit_always},
>> > > + {"zkn", "zknd", check_implicit_always},
>> > > + {"zkn", "zknh", check_implicit_always},
>> > > + {"zks", "zbkb", check_implicit_always},
>> > > + {"zks", "zbkc", check_implicit_always},
>> > > + {"zks", "zbkx", check_implicit_always},
>> > > + {"zks", "zksed", check_implicit_always},
>> > > + {"zks", "zksh", check_implicit_always},
>> > > {NULL, NULL, NULL}
>> > > };
>> > >
>> > > @@ -1127,6 +1141,7 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
>> > > {"c", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
>> > > {"c", ISA_SPEC_CLASS_2P2, 2, 0, 0 },
>> > > {"b", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
>> > > + {"k", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
>> >
>> > May I ask what purpose this addition serves? Without its use enabling
>> > smaller scope extensions implicitly, I find it at best unhelpful that
>> > ".option arch, +k" is accepted without having any effect.
>> >
>> > Jan
>>
>> It's same like bitmanip extension, add this will make k extension as a subextension
>> and set it's canonical order as ISA spec defined.
>
> Let me point out that this is not the same as with the
> bit-manipulation family of extensions.
> Zb[abcs] are all standalone extensions, and there is no Zb.
>
> --Phil.
I agree.
But we cannot remove these now for a good reason.
This is because riscv_supported_std_ext is used to determine canonical
order of multi-letter extensions (starting with 'Z'). See
riscv_init_ext_order function (bfd/elfxx-riscv.c) for details.
Maybe we should make a marker (flag?) for "canonical order is determined
by this but not an actual extension". This will apply to...
- "L"
- "B"
- "K"
- "J"
- "T"
- "P"
- "N"
Tsukasa
>
>>
>> >
>> > > @@ -1146,6 +1161,19 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
>> > > {"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > > {"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > > {"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > > + {"zbkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > > + {"zbkc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > > + {"zbkx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > > + {"zk", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > > + {"zkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > > + {"zknd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > > + {"zkne", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > > + {"zknh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > > + {"zkr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > > + {"zks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > > + {"zksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > > + {"zksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > > + {"zkt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > > {NULL, 0, 0, 0, 0}
>> > > };
>> > >
>> </jiawei@iscas.ac.cn></jbeulich@suse.com>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension
2022-02-21 14:44 ` Tsukasa OI
@ 2022-02-21 14:50 ` Kito Cheng
0 siblings, 0 replies; 16+ messages in thread
From: Kito Cheng @ 2022-02-21 14:50 UTC (permalink / raw)
To: Tsukasa OI
Cc: Philipp Tomsich, jiawei, ben.marshall, mjos, siyu,
Christoph Muellner, Binutils, Andreas Schwab, Jim Wilson
Maybe hold a string for the canonical order? I think accepting those
extensions is kind of buggy.
My patch for this proposal:
https://sourceware.org/pipermail/binutils/2022-February/119827.html
On Mon, Feb 21, 2022 at 10:44 PM Tsukasa OI
<research_trasio@irq.a4lg.com> wrote:
>
>
>
> On 2022/02/21 23:16, Philipp Tomsich wrote:
> > On Mon, 21 Feb 2022 at 15:14, <jiawei@iscas.ac.cn> wrote:
> >>
> >>
> >>
> >>
> >> > -----原始邮件-----
> >> > 发件人: "Jan Beulich" <jbeulich@suse.com>
> >> > 发送时间: 2022-02-21 21:24:11 (星期一)
> >> > 收件人: jiawei <jiawei@iscas.ac.cn>
> >> > 抄送: kito.cheng@sifive.com, nelson.chu@sifive.com, jimw@sifive.com, philipp.tomsich@vrull.eu, mjos@pqshield.com, ben.marshall@pqshield.com, cmuellner@ventanamicro.com, palmer@dabbelt.com, andrew@sifive.com, lazyparser@gmail.com, siyu@isrc.iscas.ac.cn, schwab@linux-m68k.org, binutils@sourceware.org
> >> > 主题: Re: [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension
> >> >
> >> > On 15.11.2021 04:03, jiawei wrote:
> >> > > Minimal support of scalar crypto extension, add "k" in riscv_supported_std_ext[] to make the order check right with "zk" behind "zb". "zbk*" is sub-extension for k-ext, so it added behind "zbs" in riscv_supported_std_z_ext[].
> >> > > ---
> >> > > bfd/elfxx-riscv.c | 28 ++++++++++++++++++++++++++++
> >> > > 1 file changed, 28 insertions(+)
> >> > >
> >> > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> >> > > index 3ffbaad66dd..152fbe3d160 100644
> >> > > --- a/bfd/elfxx-riscv.c
> >> > > +++ b/bfd/elfxx-riscv.c
> >> > > @@ -1075,6 +1075,20 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
> >> > > {"q", "d", check_implicit_always},
> >> > > {"d", "f", check_implicit_always},
> >> > > {"f", "zicsr", check_implicit_always},
> >> > > + {"zk", "zkn", check_implicit_always},
> >> > > + {"zk", "zkr", check_implicit_always},
> >> > > + {"zk", "zkt", check_implicit_always},
> >> > > + {"zkn", "zbkb", check_implicit_always},
> >> > > + {"zkn", "zbkc", check_implicit_always},
> >> > > + {"zkn", "zbkx", check_implicit_always},
> >> > > + {"zkn", "zkne", check_implicit_always},
> >> > > + {"zkn", "zknd", check_implicit_always},
> >> > > + {"zkn", "zknh", check_implicit_always},
> >> > > + {"zks", "zbkb", check_implicit_always},
> >> > > + {"zks", "zbkc", check_implicit_always},
> >> > > + {"zks", "zbkx", check_implicit_always},
> >> > > + {"zks", "zksed", check_implicit_always},
> >> > > + {"zks", "zksh", check_implicit_always},
> >> > > {NULL, NULL, NULL}
> >> > > };
> >> > >
> >> > > @@ -1127,6 +1141,7 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
> >> > > {"c", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
> >> > > {"c", ISA_SPEC_CLASS_2P2, 2, 0, 0 },
> >> > > {"b", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
> >> > > + {"k", ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
> >> >
> >> > May I ask what purpose this addition serves? Without its use enabling
> >> > smaller scope extensions implicitly, I find it at best unhelpful that
> >> > ".option arch, +k" is accepted without having any effect.
> >> >
> >> > Jan
> >>
> >> It's same like bitmanip extension, add this will make k extension as a subextension
> >> and set it's canonical order as ISA spec defined.
> >
> > Let me point out that this is not the same as with the
> > bit-manipulation family of extensions.
> > Zb[abcs] are all standalone extensions, and there is no Zb.
> >
> > --Phil.
>
> I agree.
>
> But we cannot remove these now for a good reason.
>
> This is because riscv_supported_std_ext is used to determine canonical
> order of multi-letter extensions (starting with 'Z'). See
> riscv_init_ext_order function (bfd/elfxx-riscv.c) for details.
>
> Maybe we should make a marker (flag?) for "canonical order is determined
> by this but not an actual extension". This will apply to...
>
> - "L"
> - "B"
> - "K"
> - "J"
> - "T"
> - "P"
> - "N"
>
> Tsukasa
>
> >
> >>
> >> >
> >> > > @@ -1146,6 +1161,19 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
> >> > > {"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> > > {"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> > > {"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> > > + {"zbkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> > > + {"zbkc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> > > + {"zbkx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> > > + {"zk", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> > > + {"zkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> > > + {"zknd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> > > + {"zkne", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> > > + {"zknh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> > > + {"zkr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> > > + {"zks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> > > + {"zksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> > > + {"zksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> > > + {"zkt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> > > {NULL, 0, 0, 0, 0}
> >> > > };
> >> > >
> >> </jiawei@iscas.ac.cn></jbeulich@suse.com>
> >
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2022-02-21 14:50 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-15 3:03 [PATCH v4 0/3] RISC-V: Support Scalar Cryptography extension jiawei
2021-11-15 3:03 ` [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension jiawei
2022-02-21 13:24 ` Jan Beulich
2022-02-21 14:14 ` jiawei
2022-02-21 14:16 ` Philipp Tomsich
2022-02-21 14:25 ` Jan Beulich
2022-02-21 14:44 ` Tsukasa OI
2022-02-21 14:50 ` Kito Cheng
2021-11-15 3:03 ` [PATCH v4 2/3] RISC-V: Scalar crypto instructions and operand set jiawei
2022-01-04 8:04 ` Jan Beulich
2022-01-04 8:38 ` 陈嘉炜
2022-01-04 8:49 ` Jan Beulich
2022-01-04 13:13 ` Markku-Juhani O. Saarinen
2021-11-15 3:03 ` [PATCH v4 3/3] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases jiawei
2021-12-21 16:06 ` Jan Beulich
2021-11-16 4:07 ` [PATCH v4 0/3] RISC-V: Support Scalar Cryptography extension Nelson Chu
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