* [PATCH 00/12] RISC-V: Test refinements (Batch 1)
@ 2022-11-05 12:29 Tsukasa OI
2022-11-05 12:29 ` [PATCH 01/12] RISC-V: Remove unnecessary empty matching file Tsukasa OI
` (12 more replies)
0 siblings, 13 replies; 26+ messages in thread
From: Tsukasa OI @ 2022-11-05 12:29 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
Hello,
After mapping symbol with ISA string support with commit 40f1a1a4564b
("RISC-V: Output mapping symbols with ISA string.") and commit 0ce50fc900a5
("RISC-V: Always generate mapping symbols at the start of the sections."),
we can merge multiple testcases.
At the same time, we can improve the test coverage.
This patchset:
1. Makes minor tidyings
2. Adds small testing utilities
3. Combines multiple testcases
4. Improves test coverage
* Add "no required extensions" testcases
* Uses different registers per operand (as long as allowed)
While improving the test coverage, it reduces the number of testcases by 4
(470 -> 466).
Of course, this is batch 1. Although this is regular PATCH, it also intends
to be a RFC to confirm whether I can go forward like this.
I tested those testcases work with both my working tree and Nelson's.
Thanks,
Tsukasa
Tsukasa OI (12):
RISC-V: Remove unnecessary empty matching file
RISC-V: Tidy disassembler corner case tests
RISC-V: Tidying related to 'Zfinx' disassembler test
RISC-V: GAS: Add basic shared test utilities
RISC-V: Redefine "nop" test
RISC-V: Reorganize/enhance {sign,zero}-extension instructions
RISC-V: Combine complex extension error handling tests
RISC-V: Refine/enhance 'M'/'Zmmul' extension tests
RISC-V: Combine/enhance 'Zicbo[mz]' extension tests
RISC-V: Enhance 'Zicbop' testcases
RISC-V: Reorganize/enhance 'Zb*' extension tests
RISC-V: Combine/enhance 'Zk*'/'Zbk*' extension tests
gas/testsuite/gas/riscv/b-ext-64.d | 72 -----------
gas/testsuite/gas/riscv/b-ext-64.s | 64 ----------
gas/testsuite/gas/riscv/b-ext.d | 51 --------
gas/testsuite/gas/riscv/b-ext.s | 43 -------
gas/testsuite/gas/riscv/dis-addr-addiw-a.d | 2 +-
gas/testsuite/gas/riscv/dis-addr-addiw-b.d | 2 +-
.../gas/riscv/dis-addr-overflow-32.d | 4 +-
.../gas/riscv/dis-addr-overflow-64.d | 4 +-
gas/testsuite/gas/riscv/dis-addr-overflow.s | 40 +++----
.../gas/riscv/dis-addr-topaddr-gp-32.d | 4 +-
.../gas/riscv/dis-addr-topaddr-gp-64.d | 4 +-
gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s | 12 +-
...opaddr-32.d => dis-addr-topaddr-zero-32.d} | 6 +-
...opaddr-64.d => dis-addr-topaddr-zero-64.d} | 6 +-
.../gas/riscv/dis-addr-topaddr-zero.s | 11 ++
gas/testsuite/gas/riscv/dis-addr-topaddr.s | 10 --
gas/testsuite/gas/riscv/empty.l | 1 -
gas/testsuite/gas/riscv/ext-32.d | 39 ------
gas/testsuite/gas/riscv/ext-64.d | 51 --------
gas/testsuite/gas/riscv/ext-insn-32-noalias.d | 39 ++++++
gas/testsuite/gas/riscv/ext-insn-32-noarch.d | 3 +
gas/testsuite/gas/riscv/ext-insn-32-noarch.l | 9 ++
gas/testsuite/gas/riscv/ext-insn-64-noalias.d | 51 ++++++++
gas/testsuite/gas/riscv/ext-insn-64-noarch.d | 5 +
.../gas/riscv/ext-insn-zba-32-noalias.d | 39 ++++++
.../gas/riscv/ext-insn-zba-64-noalias.d | 47 ++++++++
.../gas/riscv/ext-insn-zbb-32-noalias.d | 27 +++++
.../gas/riscv/ext-insn-zbb-64-noalias.d | 39 ++++++
gas/testsuite/gas/riscv/ext-insn.s | 23 ++++
gas/testsuite/gas/riscv/ext.s | 38 ------
gas/testsuite/gas/riscv/k-ext-64.d | 47 --------
gas/testsuite/gas/riscv/k-ext-64.s | 38 ------
gas/testsuite/gas/riscv/k-ext.d | 44 -------
gas/testsuite/gas/riscv/k-ext.s | 35 ------
gas/testsuite/gas/riscv/m-ext-32-noarch-m.d | 4 +
...xt-fail-zmmul-32.l => m-ext-32-noarch-m.l} | 0
gas/testsuite/gas/riscv/m-ext-32-noarch.d | 4 +
gas/testsuite/gas/riscv/m-ext-32-noarch.l | 14 +++
gas/testsuite/gas/riscv/m-ext-32.d | 2 +-
gas/testsuite/gas/riscv/m-ext-64-noarch-m.d | 4 +
...xt-fail-zmmul-64.l => m-ext-64-noarch-m.l} | 0
gas/testsuite/gas/riscv/m-ext-64-noarch.d | 4 +
...ext-fail-noarch-64.l => m-ext-64-noarch.l} | 0
gas/testsuite/gas/riscv/m-ext-64.d | 2 +-
.../gas/riscv/m-ext-fail-noarch-64.d | 4 -
gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d | 4 -
gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l | 6 -
gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d | 4 -
gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d | 4 -
gas/testsuite/gas/riscv/m-ext.s | 17 ++-
gas/testsuite/gas/riscv/nop-noalias.d | 13 ++
gas/testsuite/gas/riscv/nop-noarch.d | 3 +
gas/testsuite/gas/riscv/nop-noarch.l | 2 +
gas/testsuite/gas/riscv/nop.d | 12 ++
gas/testsuite/gas/riscv/nop.s | 9 ++
gas/testsuite/gas/riscv/t_insns.d | 10 --
gas/testsuite/gas/riscv/t_insns.s | 2 -
gas/testsuite/gas/riscv/testutils.inc | 113 ++++++++++++++++++
.../riscv/{b-ext-na.d => zb-ext-32-noalias.d} | 38 +++---
gas/testsuite/gas/riscv/zb-ext-32-noarch.d | 3 +
gas/testsuite/gas/riscv/zb-ext-32-noarch.l | 60 ++++++++++
gas/testsuite/gas/riscv/zb-ext-32.d | 51 ++++++++
.../{b-ext-64-na.d => zb-ext-64-noalias.d} | 72 +++++------
gas/testsuite/gas/riscv/zb-ext-64-noarch.d | 3 +
gas/testsuite/gas/riscv/zb-ext-64-noarch.l | 59 +++++++++
gas/testsuite/gas/riscv/zb-ext-64.d | 72 +++++++++++
gas/testsuite/gas/riscv/zb-ext.s | 84 +++++++++++++
gas/testsuite/gas/riscv/zbk-ext-32-noalias.d | 26 ++++
gas/testsuite/gas/riscv/zbk-ext-32-noarch.d | 3 +
gas/testsuite/gas/riscv/zbk-ext-32-noarch.l | 21 ++++
gas/testsuite/gas/riscv/zbk-ext-32.d | 26 ++++
gas/testsuite/gas/riscv/zbk-ext-64-noalias.d | 28 +++++
gas/testsuite/gas/riscv/zbk-ext-64-noarch.d | 3 +
gas/testsuite/gas/riscv/zbk-ext-64-noarch.l | 21 ++++
gas/testsuite/gas/riscv/zbk-ext-64.d | 28 +++++
gas/testsuite/gas/riscv/zbk-ext.s | 37 ++++++
gas/testsuite/gas/riscv/zbkb-32-na.d | 23 ----
gas/testsuite/gas/riscv/zbkb-32.d | 22 ----
gas/testsuite/gas/riscv/zbkb-32.s | 13 --
gas/testsuite/gas/riscv/zbkb-64.d | 24 ----
gas/testsuite/gas/riscv/zbkb-64.s | 15 ---
gas/testsuite/gas/riscv/zbkc-32.d | 12 --
gas/testsuite/gas/riscv/zbkc-64.d | 12 --
gas/testsuite/gas/riscv/zbkc.s | 3 -
gas/testsuite/gas/riscv/zbkx-32.d | 12 --
gas/testsuite/gas/riscv/zbkx-64.d | 12 --
gas/testsuite/gas/riscv/zbkx.s | 3 -
.../gas/riscv/zfhmin-d-insn-class-fail-1.d | 3 -
.../gas/riscv/zfhmin-d-insn-class-fail-1.l | 2 -
.../gas/riscv/zfhmin-d-insn-class-fail-2.d | 3 -
.../gas/riscv/zfhmin-d-insn-class-fail-2.l | 2 -
.../gas/riscv/zfhmin-d-insn-class-fail-3.d | 3 -
.../gas/riscv/zfhmin-d-insn-class-fail-3.l | 2 -
.../gas/riscv/zfhmin-d-insn-class-fail-4.d | 3 -
.../gas/riscv/zfhmin-d-insn-class-fail-4.l | 2 -
.../gas/riscv/zfhmin-d-insn-class-fail-5.d | 3 -
.../gas/riscv/zfhmin-d-insn-class-fail-5.l | 2 -
.../gas/riscv/zfhmin-d-insn-class-fail.s | 4 -
gas/testsuite/gas/riscv/zfhmin-d-noarch.d | 2 +
gas/testsuite/gas/riscv/zfhmin-d-noarch.l | 6 +
gas/testsuite/gas/riscv/zfhmin-d-noarch.s | 25 ++++
gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 7 +-
gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d | 2 +
gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l | 11 ++
.../{zicbom-fail.s => zicbo-mz-ext-fail.s} | 4 +
gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d | 3 +
gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l | 11 ++
.../gas/riscv/{zicbom.d => zicbo-mz-ext.d} | 9 +-
gas/testsuite/gas/riscv/zicbo-mz-ext.s | 16 +++
gas/testsuite/gas/riscv/zicbom-fail.d | 3 -
gas/testsuite/gas/riscv/zicbom-fail.l | 7 --
gas/testsuite/gas/riscv/zicbom.s | 7 --
gas/testsuite/gas/riscv/zicbop-fail-offset.d | 2 +
.../{zicbop-fail.l => zicbop-fail-offset.l} | 0
.../{zicbop-fail.s => zicbop-fail-offset.s} | 0
gas/testsuite/gas/riscv/zicbop-fail.d | 3 -
gas/testsuite/gas/riscv/zicbop-noarch.d | 4 +
gas/testsuite/gas/riscv/zicbop-noarch.l | 7 ++
gas/testsuite/gas/riscv/zicbop.d | 8 +-
gas/testsuite/gas/riscv/zicbop.s | 7 ++
gas/testsuite/gas/riscv/zicboz-fail.d | 3 -
gas/testsuite/gas/riscv/zicboz-fail.l | 5 -
gas/testsuite/gas/riscv/zicboz-fail.s | 5 -
gas/testsuite/gas/riscv/zicboz.d | 13 --
gas/testsuite/gas/riscv/zicboz.s | 5 -
gas/testsuite/gas/riscv/zk-ext-32-noarch.d | 3 +
gas/testsuite/gas/riscv/zk-ext-32-noarch.l | 20 ++++
gas/testsuite/gas/riscv/zk-ext-32.d | 28 +++++
gas/testsuite/gas/riscv/zk-ext-32.s | 41 +++++++
gas/testsuite/gas/riscv/zk-ext-64-noarch.d | 3 +
gas/testsuite/gas/riscv/zk-ext-64-noarch.l | 23 ++++
gas/testsuite/gas/riscv/zk-ext-64.d | 31 +++++
gas/testsuite/gas/riscv/zk-ext-64.s | 44 +++++++
gas/testsuite/gas/riscv/zknd-32.d | 12 --
gas/testsuite/gas/riscv/zknd-32.s | 3 -
gas/testsuite/gas/riscv/zknd-64.d | 15 ---
gas/testsuite/gas/riscv/zknd-64.s | 6 -
gas/testsuite/gas/riscv/zkne-32.d | 12 --
gas/testsuite/gas/riscv/zkne-32.s | 3 -
gas/testsuite/gas/riscv/zkne-64.d | 14 ---
gas/testsuite/gas/riscv/zkne-64.s | 5 -
gas/testsuite/gas/riscv/zknh-32.d | 20 ----
gas/testsuite/gas/riscv/zknh-32.s | 11 --
gas/testsuite/gas/riscv/zknh-64.d | 18 ---
gas/testsuite/gas/riscv/zknh-64.s | 9 --
gas/testsuite/gas/riscv/zksed-32.d | 12 --
gas/testsuite/gas/riscv/zksed-64.d | 12 --
gas/testsuite/gas/riscv/zksed.s | 3 -
gas/testsuite/gas/riscv/zksh-32.d | 12 --
gas/testsuite/gas/riscv/zksh-64.d | 12 --
gas/testsuite/gas/riscv/zksh.s | 3 -
gas/testsuite/gas/riscv/zkt.d | 5 +
gas/testsuite/gas/riscv/zmmul-32.d | 14 ---
gas/testsuite/gas/riscv/zmmul-64.d | 15 ---
154 files changed, 1422 insertions(+), 1124 deletions(-)
delete mode 100644 gas/testsuite/gas/riscv/b-ext-64.d
delete mode 100644 gas/testsuite/gas/riscv/b-ext-64.s
delete mode 100644 gas/testsuite/gas/riscv/b-ext.d
delete mode 100644 gas/testsuite/gas/riscv/b-ext.s
rename gas/testsuite/gas/riscv/{dis-addr-topaddr-32.d => dis-addr-topaddr-zero-32.d} (60%)
rename gas/testsuite/gas/riscv/{dis-addr-topaddr-64.d => dis-addr-topaddr-zero-64.d} (58%)
create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-zero.s
delete mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr.s
delete mode 100644 gas/testsuite/gas/riscv/empty.l
delete mode 100644 gas/testsuite/gas/riscv/ext-32.d
delete mode 100644 gas/testsuite/gas/riscv/ext-64.d
create mode 100644 gas/testsuite/gas/riscv/ext-insn-32-noalias.d
create mode 100644 gas/testsuite/gas/riscv/ext-insn-32-noarch.d
create mode 100644 gas/testsuite/gas/riscv/ext-insn-32-noarch.l
create mode 100644 gas/testsuite/gas/riscv/ext-insn-64-noalias.d
create mode 100644 gas/testsuite/gas/riscv/ext-insn-64-noarch.d
create mode 100644 gas/testsuite/gas/riscv/ext-insn-zba-32-noalias.d
create mode 100644 gas/testsuite/gas/riscv/ext-insn-zba-64-noalias.d
create mode 100644 gas/testsuite/gas/riscv/ext-insn-zbb-32-noalias.d
create mode 100644 gas/testsuite/gas/riscv/ext-insn-zbb-64-noalias.d
create mode 100644 gas/testsuite/gas/riscv/ext-insn.s
delete mode 100644 gas/testsuite/gas/riscv/ext.s
delete mode 100644 gas/testsuite/gas/riscv/k-ext-64.d
delete mode 100644 gas/testsuite/gas/riscv/k-ext-64.s
delete mode 100644 gas/testsuite/gas/riscv/k-ext.d
delete mode 100644 gas/testsuite/gas/riscv/k-ext.s
create mode 100644 gas/testsuite/gas/riscv/m-ext-32-noarch-m.d
rename gas/testsuite/gas/riscv/{m-ext-fail-zmmul-32.l => m-ext-32-noarch-m.l} (100%)
create mode 100644 gas/testsuite/gas/riscv/m-ext-32-noarch.d
create mode 100644 gas/testsuite/gas/riscv/m-ext-32-noarch.l
create mode 100644 gas/testsuite/gas/riscv/m-ext-64-noarch-m.d
rename gas/testsuite/gas/riscv/{m-ext-fail-zmmul-64.l => m-ext-64-noarch-m.l} (100%)
create mode 100644 gas/testsuite/gas/riscv/m-ext-64-noarch.d
rename gas/testsuite/gas/riscv/{m-ext-fail-noarch-64.l => m-ext-64-noarch.l} (100%)
delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
create mode 100644 gas/testsuite/gas/riscv/nop-noalias.d
create mode 100644 gas/testsuite/gas/riscv/nop-noarch.d
create mode 100644 gas/testsuite/gas/riscv/nop-noarch.l
create mode 100644 gas/testsuite/gas/riscv/nop.d
create mode 100644 gas/testsuite/gas/riscv/nop.s
delete mode 100644 gas/testsuite/gas/riscv/t_insns.d
delete mode 100644 gas/testsuite/gas/riscv/t_insns.s
create mode 100644 gas/testsuite/gas/riscv/testutils.inc
rename gas/testsuite/gas/riscv/{b-ext-na.d => zb-ext-32-noalias.d} (67%)
create mode 100644 gas/testsuite/gas/riscv/zb-ext-32-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zb-ext-32-noarch.l
create mode 100644 gas/testsuite/gas/riscv/zb-ext-32.d
rename gas/testsuite/gas/riscv/{b-ext-64-na.d => zb-ext-64-noalias.d} (73%)
create mode 100644 gas/testsuite/gas/riscv/zb-ext-64-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zb-ext-64-noarch.l
create mode 100644 gas/testsuite/gas/riscv/zb-ext-64.d
create mode 100644 gas/testsuite/gas/riscv/zb-ext.s
create mode 100644 gas/testsuite/gas/riscv/zbk-ext-32-noalias.d
create mode 100644 gas/testsuite/gas/riscv/zbk-ext-32-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zbk-ext-32-noarch.l
create mode 100644 gas/testsuite/gas/riscv/zbk-ext-32.d
create mode 100644 gas/testsuite/gas/riscv/zbk-ext-64-noalias.d
create mode 100644 gas/testsuite/gas/riscv/zbk-ext-64-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zbk-ext-64-noarch.l
create mode 100644 gas/testsuite/gas/riscv/zbk-ext-64.d
create mode 100644 gas/testsuite/gas/riscv/zbk-ext.s
delete mode 100644 gas/testsuite/gas/riscv/zbkb-32-na.d
delete mode 100644 gas/testsuite/gas/riscv/zbkb-32.d
delete mode 100644 gas/testsuite/gas/riscv/zbkb-32.s
delete mode 100644 gas/testsuite/gas/riscv/zbkb-64.d
delete mode 100644 gas/testsuite/gas/riscv/zbkb-64.s
delete mode 100644 gas/testsuite/gas/riscv/zbkc-32.d
delete mode 100644 gas/testsuite/gas/riscv/zbkc-64.d
delete mode 100644 gas/testsuite/gas/riscv/zbkc.s
delete mode 100644 gas/testsuite/gas/riscv/zbkx-32.d
delete mode 100644 gas/testsuite/gas/riscv/zbkx-64.d
delete mode 100644 gas/testsuite/gas/riscv/zbkx.s
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-noarch.l
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-noarch.s
create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d
create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l
rename gas/testsuite/gas/riscv/{zicbom-fail.s => zicbo-mz-ext-fail.s} (61%)
create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l
rename gas/testsuite/gas/riscv/{zicbom.d => zicbo-mz-ext.d} (60%)
create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext.s
delete mode 100644 gas/testsuite/gas/riscv/zicbom-fail.d
delete mode 100644 gas/testsuite/gas/riscv/zicbom-fail.l
delete mode 100644 gas/testsuite/gas/riscv/zicbom.s
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail-offset.d
rename gas/testsuite/gas/riscv/{zicbop-fail.l => zicbop-fail-offset.l} (100%)
rename gas/testsuite/gas/riscv/{zicbop-fail.s => zicbop-fail-offset.s} (100%)
delete mode 100644 gas/testsuite/gas/riscv/zicbop-fail.d
create mode 100644 gas/testsuite/gas/riscv/zicbop-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zicbop-noarch.l
delete mode 100644 gas/testsuite/gas/riscv/zicboz-fail.d
delete mode 100644 gas/testsuite/gas/riscv/zicboz-fail.l
delete mode 100644 gas/testsuite/gas/riscv/zicboz-fail.s
delete mode 100644 gas/testsuite/gas/riscv/zicboz.d
delete mode 100644 gas/testsuite/gas/riscv/zicboz.s
create mode 100644 gas/testsuite/gas/riscv/zk-ext-32-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zk-ext-32-noarch.l
create mode 100644 gas/testsuite/gas/riscv/zk-ext-32.d
create mode 100644 gas/testsuite/gas/riscv/zk-ext-32.s
create mode 100644 gas/testsuite/gas/riscv/zk-ext-64-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zk-ext-64-noarch.l
create mode 100644 gas/testsuite/gas/riscv/zk-ext-64.d
create mode 100644 gas/testsuite/gas/riscv/zk-ext-64.s
delete mode 100644 gas/testsuite/gas/riscv/zknd-32.d
delete mode 100644 gas/testsuite/gas/riscv/zknd-32.s
delete mode 100644 gas/testsuite/gas/riscv/zknd-64.d
delete mode 100644 gas/testsuite/gas/riscv/zknd-64.s
delete mode 100644 gas/testsuite/gas/riscv/zkne-32.d
delete mode 100644 gas/testsuite/gas/riscv/zkne-32.s
delete mode 100644 gas/testsuite/gas/riscv/zkne-64.d
delete mode 100644 gas/testsuite/gas/riscv/zkne-64.s
delete mode 100644 gas/testsuite/gas/riscv/zknh-32.d
delete mode 100644 gas/testsuite/gas/riscv/zknh-32.s
delete mode 100644 gas/testsuite/gas/riscv/zknh-64.d
delete mode 100644 gas/testsuite/gas/riscv/zknh-64.s
delete mode 100644 gas/testsuite/gas/riscv/zksed-32.d
delete mode 100644 gas/testsuite/gas/riscv/zksed-64.d
delete mode 100644 gas/testsuite/gas/riscv/zksed.s
delete mode 100644 gas/testsuite/gas/riscv/zksh-32.d
delete mode 100644 gas/testsuite/gas/riscv/zksh-64.d
delete mode 100644 gas/testsuite/gas/riscv/zksh.s
create mode 100644 gas/testsuite/gas/riscv/zkt.d
delete mode 100644 gas/testsuite/gas/riscv/zmmul-32.d
delete mode 100644 gas/testsuite/gas/riscv/zmmul-64.d
base-commit: cb9bdc02fdf1650341276861f6ca7e7a215a1ce6
--
2.37.2
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 01/12] RISC-V: Remove unnecessary empty matching file
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
@ 2022-11-05 12:29 ` Tsukasa OI
2022-11-29 7:38 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 02/12] RISC-V: Tidy disassembler corner case tests Tsukasa OI
` (11 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Tsukasa OI @ 2022-11-05 12:29 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
We don't need empty "output" matching file since we can just omit specifying
error_output or warning_output. So, this commit removes unused and
unnecessary empty.l.
gas/ChangeLog:
* testsuite/gas/riscv/empty.l: Removed.
---
gas/testsuite/gas/riscv/empty.l | 1 -
1 file changed, 1 deletion(-)
delete mode 100644 gas/testsuite/gas/riscv/empty.l
diff --git a/gas/testsuite/gas/riscv/empty.l b/gas/testsuite/gas/riscv/empty.l
deleted file mode 100644
index 8b137891791..00000000000
--- a/gas/testsuite/gas/riscv/empty.l
+++ /dev/null
@@ -1 +0,0 @@
-
--
2.37.2
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 02/12] RISC-V: Tidy disassembler corner case tests
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
2022-11-05 12:29 ` [PATCH 01/12] RISC-V: Remove unnecessary empty matching file Tsukasa OI
@ 2022-11-05 12:29 ` Tsukasa OI
2022-11-29 7:48 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 03/12] RISC-V: Tidying related to 'Zfinx' disassembler test Tsukasa OI
` (10 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Tsukasa OI @ 2022-11-05 12:29 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
Because later commits use "XLEN" symbol rather than "rv64", it replaces
occurrences of "rv64" with "XLEN" and makes other tidying changes for
consistency with other testcases.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-addiw-a.d: Tidying.
* testsuite/gas/riscv/dis-addr-addiw-b.d: Likewise.
* testsuite/gas/riscv/dis-addr-overflow.s: Tidying.
* testsuite/gas/riscv/dis-addr-overflow-32.d: Use XLEN symbol.
* testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-gp.s: Tidying.
* testsuite/gas/riscv/dis-addr-topaddr-gp-32.d: Use XLEN symbol.
* testsuite/gas/riscv/dis-addr-topaddr-gp-64.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr.s: Moved to...
* testsuite/gas/riscv/dis-addr-topaddr-zero.s: ...here
with tidying.
* testsuite/gas/riscv/dis-addr-topaddr-32.d: Moved to...
* testsuite/gas/riscv/dis-addr-topaddr-zero-32.d: ...here.
Use XLEN symbol. Minimize architecture requirements.
* testsuite/gas/riscv/dis-addr-topaddr-64.d: Moved to...
* testsuite/gas/riscv/dis-addr-topaddr-zero-64.d: ...here.
Use XLEN symbol. Minimize architecture requirements.
---
gas/testsuite/gas/riscv/dis-addr-addiw-a.d | 2 +-
gas/testsuite/gas/riscv/dis-addr-addiw-b.d | 2 +-
.../gas/riscv/dis-addr-overflow-32.d | 4 +-
.../gas/riscv/dis-addr-overflow-64.d | 4 +-
gas/testsuite/gas/riscv/dis-addr-overflow.s | 40 +++++++++----------
.../gas/riscv/dis-addr-topaddr-gp-32.d | 4 +-
.../gas/riscv/dis-addr-topaddr-gp-64.d | 4 +-
gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s | 12 +++---
...opaddr-32.d => dis-addr-topaddr-zero-32.d} | 6 +--
...opaddr-64.d => dis-addr-topaddr-zero-64.d} | 6 +--
.../gas/riscv/dis-addr-topaddr-zero.s | 11 +++++
gas/testsuite/gas/riscv/dis-addr-topaddr.s | 10 -----
12 files changed, 53 insertions(+), 52 deletions(-)
rename gas/testsuite/gas/riscv/{dis-addr-topaddr-32.d => dis-addr-topaddr-zero-32.d} (60%)
rename gas/testsuite/gas/riscv/{dis-addr-topaddr-64.d => dis-addr-topaddr-zero-64.d} (58%)
create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-zero.s
delete mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr.s
diff --git a/gas/testsuite/gas/riscv/dis-addr-addiw-a.d b/gas/testsuite/gas/riscv/dis-addr-addiw-a.d
index c4e4cfe6df7..44837ff4f69 100644
--- a/gas/testsuite/gas/riscv/dis-addr-addiw-a.d
+++ b/gas/testsuite/gas/riscv/dis-addr-addiw-a.d
@@ -2,7 +2,7 @@
#source: dis-addr-addiw.s
#objdump: -d --adjust-vma=0xffffffe0
-.*: file format elf64-(little|big)riscv
+.*:[ ]+file format .*
Disassembly of section .text:
diff --git a/gas/testsuite/gas/riscv/dis-addr-addiw-b.d b/gas/testsuite/gas/riscv/dis-addr-addiw-b.d
index d5f84db172e..bc1841f35f1 100644
--- a/gas/testsuite/gas/riscv/dis-addr-addiw-b.d
+++ b/gas/testsuite/gas/riscv/dis-addr-addiw-b.d
@@ -2,7 +2,7 @@
#source: dis-addr-addiw.s
#objdump: -d --adjust-vma=0x7fffffe0
-.*: file format elf64-(little|big)riscv
+.*:[ ]+file format .*
Disassembly of section .text:
diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow-32.d b/gas/testsuite/gas/riscv/dis-addr-overflow-32.d
index 287c5ea022f..b246605e361 100644
--- a/gas/testsuite/gas/riscv/dis-addr-overflow-32.d
+++ b/gas/testsuite/gas/riscv/dis-addr-overflow-32.d
@@ -1,8 +1,8 @@
-#as: -march=rv32ic
+#as: -march=rv32ic -defsym XLEN=32
#source: dis-addr-overflow.s
#objdump: -d
-.*: file format elf32-(little|big)riscv
+.*:[ ]+file format .*
Disassembly of section .text:
diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow-64.d b/gas/testsuite/gas/riscv/dis-addr-overflow-64.d
index 1966a5ed743..61885edbc75 100644
--- a/gas/testsuite/gas/riscv/dis-addr-overflow-64.d
+++ b/gas/testsuite/gas/riscv/dis-addr-overflow-64.d
@@ -1,8 +1,8 @@
-#as: -march=rv64ic -defsym rv64=1
+#as: -march=rv64ic -defsym XLEN=64
#source: dis-addr-overflow.s
#objdump: -d
-.*: file format elf64-(little|big)riscv
+.*:[ ]+file format .*
Disassembly of section .text:
diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow.s b/gas/testsuite/gas/riscv/dis-addr-overflow.s
index 77ca39c07b6..47e5351c9fc 100644
--- a/gas/testsuite/gas/riscv/dis-addr-overflow.s
+++ b/gas/testsuite/gas/riscv/dis-addr-overflow.s
@@ -1,26 +1,26 @@
-.set __global_pointer$, 0x00000200
+.set __global_pointer$, 0x00000200
-.ifdef rv64
-topbase = 0xffffffff00000000
+.ifge XLEN-64
+.set topbase, 0xffffffff00000000
.else
-topbase = 0
+.set topbase, 0
.endif
-.set addr_load, topbase + 0xffffeffc # -0x1000 -4
-.set addr_store, topbase + 0xffffdff8 # -0x2000 -8
-.set addr_jalr_1, topbase + 0xffffd000 # -0x3000
-.set addr_jalr_2, topbase + 0xffffbff4 # -0x4000 -12
-.set addr_jalr_3, topbase + 0xffffb000 # -0x5000
-.set addr_loadaddr, topbase + 0xffff9ff0 # -0x6000 -16
-.set addr_loadaddr_c, topbase + 0xffff8fec # -0x7000 -20
-.set addr_loadaddr_w, topbase + 0xffff7fe8 # -0x8000 -24
-.set addr_loadaddr_w_c, topbase + 0xffff6fe4 # -0x9000 -28
-.set addr_rel_gp_pos, 0x00000600 # __global_pointer$ + 0x400
-.set addr_rel_gp_neg, topbase + 0xfffffe00 # __global_pointer$ - 0x400
-.set addr_rel_zero_pos, 0x00000100
-.set addr_rel_zero_neg, topbase + 0xfffff800 # -0x800
-.set addr_jalr_rel_zero_pos, 0x00000104
-.set addr_jalr_rel_zero_neg, topbase + 0xfffff804 # -0x7fc
+.set addr_load, topbase + 0xffffeffc # -0x1000 -4
+.set addr_store, topbase + 0xffffdff8 # -0x2000 -8
+.set addr_jalr_1, topbase + 0xffffd000 # -0x3000
+.set addr_jalr_2, topbase + 0xffffbff4 # -0x4000 -12
+.set addr_jalr_3, topbase + 0xffffb000 # -0x5000
+.set addr_loadaddr, topbase + 0xffff9ff0 # -0x6000 -16
+.set addr_loadaddr_c, topbase + 0xffff8fec # -0x7000 -20
+.set addr_loadaddr_w, topbase + 0xffff7fe8 # -0x8000 -24
+.set addr_loadaddr_w_c, topbase + 0xffff6fe4 # -0x9000 -28
+.set addr_rel_gp_pos, 0x00000600 # __global_pointer$ + 0x400
+.set addr_rel_gp_neg, topbase + 0xfffffe00 # __global_pointer$ - 0x400
+.set addr_rel_zero_pos, 0x00000100
+.set addr_rel_zero_neg, topbase + 0xfffff800 # -0x800
+.set addr_jalr_rel_zero_pos, 0x00000104
+.set addr_jalr_rel_zero_neg, topbase + 0xfffff804 # -0x7fc
target:
.option push
@@ -48,7 +48,7 @@ target:
lui t6, 0xffff9
.option pop
c.addi t6, -20
-.ifdef rv64
+.ifge XLEN-64
.option push
.option arch, -c
# ADDIW (not compressed)
diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
index 875bfe73189..cdbbe3bf846 100644
--- a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
+++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
@@ -1,8 +1,8 @@
-#as: -march=rv32i
+#as: -march=rv32i -defsym XLEN=32
#source: dis-addr-topaddr-gp.s
#objdump: -d
-.*: file format elf32-(little|big)riscv
+.*:[ ]+file format .*
Disassembly of section .text:
diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
index 5ac4b52b18d..54fc8631901 100644
--- a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
+++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
@@ -1,8 +1,8 @@
-#as: -march=rv64i -defsym rv64=1
+#as: -march=rv64i -defsym XLEN=64
#source: dis-addr-topaddr-gp.s
#objdump: -d
-.*: file format elf64-(little|big)riscv
+.*:[ ]+file format .*
Disassembly of section .text:
diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s
index 6ba9fc7a39d..1689cdf89c1 100644
--- a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s
+++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s
@@ -1,12 +1,12 @@
-.ifdef rv64
-topbase = 0xffffffff00000000
+.ifge XLEN-64
+.set topbase, 0xffffffff00000000
.else
-topbase = 0
+.set topbase, 0
.endif
-.set __global_pointer$, topbase + 0xffffffff # -1
-.set addr_rel_gp_pos, 0x00000004 # +4
-.set addr_rel_gp_neg, topbase + 0xfffffffc # -4
+.set __global_pointer$, topbase + 0xffffffff # -1
+.set addr_rel_gp_pos, 0x00000004 # +4
+.set addr_rel_gp_neg, topbase + 0xfffffffc # -4
target:
# Use addresses relative to gp
diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-32.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-zero-32.d
similarity index 60%
rename from gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
rename to gas/testsuite/gas/riscv/dis-addr-topaddr-zero-32.d
index 87854cd58e6..2934e2d5fec 100644
--- a/gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
+++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-zero-32.d
@@ -1,8 +1,8 @@
-#as: -march=rv32ic
-#source: dis-addr-topaddr.s
+#as: -march=rv32i -defsym XLEN=32
+#source: dis-addr-topaddr-zero.s
#objdump: -d
-.*: file format elf32-(little|big)riscv
+.*:[ ]+file format .*
Disassembly of section .text:
diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-64.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-zero-64.d
similarity index 58%
rename from gas/testsuite/gas/riscv/dis-addr-topaddr-64.d
rename to gas/testsuite/gas/riscv/dis-addr-topaddr-zero-64.d
index 38f67efdcaf..9b2d170d3d6 100644
--- a/gas/testsuite/gas/riscv/dis-addr-topaddr-64.d
+++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-zero-64.d
@@ -1,8 +1,8 @@
-#as: -march=rv64ic -defsym rv64=1
-#source: dis-addr-topaddr.s
+#as: -march=rv64i -defsym XLEN=64
+#source: dis-addr-topaddr-zero.s
#objdump: -d
-.*: file format elf64-(little|big)riscv
+.*:[ ]+file format .*
Disassembly of section .text:
diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-zero.s b/gas/testsuite/gas/riscv/dis-addr-topaddr-zero.s
new file mode 100644
index 00000000000..cdf44b5403b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-zero.s
@@ -0,0 +1,11 @@
+.ifge XLEN-64
+.set topbase, 0xffffffff00000000
+.else
+.set topbase, 0
+.endif
+
+.set addr_top, topbase + 0xffffffff # -1
+
+target:
+ # Use address relative to zero
+ lb t0, -1(zero)
diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr.s b/gas/testsuite/gas/riscv/dis-addr-topaddr.s
deleted file mode 100644
index b66587f448d..00000000000
--- a/gas/testsuite/gas/riscv/dis-addr-topaddr.s
+++ /dev/null
@@ -1,10 +0,0 @@
-.ifdef rv64
-topbase = 0xffffffff00000000
-.else
-topbase = 0
-.endif
-
-.set addr_top, topbase + 0xffffffff # -1
-
-target:
- lb t0, -1(zero)
--
2.37.2
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 03/12] RISC-V: Tidying related to 'Zfinx' disassembler test
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
2022-11-05 12:29 ` [PATCH 01/12] RISC-V: Remove unnecessary empty matching file Tsukasa OI
2022-11-05 12:29 ` [PATCH 02/12] RISC-V: Tidy disassembler corner case tests Tsukasa OI
@ 2022-11-05 12:29 ` Tsukasa OI
2022-11-29 7:50 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 04/12] RISC-V: GAS: Add basic shared test utilities Tsukasa OI
` (9 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Tsukasa OI @ 2022-11-05 12:29 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
This commit makes some tidying to zfinx-dis-numeric.d.
gas/ChangeLog:
* testsuite/gas/riscv/zfinx-dis-numeric.d: Minimize extension
requirements. Remove redundant source line. Make test pattern
stricter. Remove -r from objdump options.
---
gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.d b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d
index ba3f62295eb..1c61d61f8f3 100644
--- a/gas/testsuite/gas/riscv/zfinx-dis-numeric.d
+++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d
@@ -1,10 +1,9 @@
-#as: -march=rv64ima_zfinx
-#source: zfinx-dis-numeric.s
-#objdump: -dr -Mnumeric
+#as: -march=rv32i_zfinx
+#objdump: -d -M numeric
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+a0c5a553[ ]+feq.s[ ]+x10,x11,x12
+[ ]+[0-9a-f]+:[ ]+a0c5a553[ ]+feq\.s[ ]+x10,x11,x12
--
2.37.2
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 04/12] RISC-V: GAS: Add basic shared test utilities
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
` (2 preceding siblings ...)
2022-11-05 12:29 ` [PATCH 03/12] RISC-V: Tidying related to 'Zfinx' disassembler test Tsukasa OI
@ 2022-11-05 12:29 ` Tsukasa OI
2022-11-29 7:53 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 05/12] RISC-V: Redefine "nop" test Tsukasa OI
` (8 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Tsukasa OI @ 2022-11-05 12:29 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
This commit adds basic shared test utilities intended for future
extension tests.
gas/ChangeLog:
* testsuite/gas/riscv/testutils.inc: New test utilities.
---
gas/testsuite/gas/riscv/testutils.inc | 113 ++++++++++++++++++++++++++
1 file changed, 113 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/testutils.inc
diff --git a/gas/testsuite/gas/riscv/testutils.inc b/gas/testsuite/gas/riscv/testutils.inc
new file mode 100644
index 00000000000..009484eefed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/testutils.inc
@@ -0,0 +1,113 @@
+# Set NOARCH symbols.
+.ifndef NOARCH
+.set NOARCH, 0
+.endif
+.ifndef NOARCH_ARCH
+.set NOARCH_ARCH, 0
+.endif
+.ifndef NOARCH_XLEN
+.set NOARCH_XLEN, 0
+.endif
+.if NOARCH
+.set NOARCH_ARCH, 1
+.set NOARCH_XLEN, 1
+.endif
+
+# Update XLEN constraint symbols.
+# For intentional error handling tests, .if SYM ... .endif block should be
+# used to test those varibales.
+.macro UPDATE_XLEN
+ .if NOARCH_XLEN
+ # When NOARCH_XLEN is set,
+ # set those variables to "invalid" 1 to generate errors.
+ .set XLEN_EQ_32, 1
+ .set XLEN_EQ_64, 1
+ .set XLEN_GE_64, 1
+ .else
+ # Set symbol values depending on the XLEN.
+ .ifdef XLEN
+ .ifeq XLEN-32
+ .set XLEN_EQ_32, 1
+ .else
+ .set XLEN_EQ_32, 0
+ .endif
+ .ifeq XLEN-64
+ .set XLEN_EQ_64, 1
+ .else
+ .set XLEN_EQ_64, 0
+ .endif
+ .ifge XLEN-64
+ .set XLEN_GE_64, 1
+ .else
+ .set XLEN_GE_64, 0
+ .endif
+ .else
+ .set XLEN_EQ_32, 0
+ .set XLEN_EQ_64, 0
+ .set XLEN_GE_64, 0
+ .endif
+ .endif
+.endm
+UPDATE_XLEN
+
+# Set the base architecture.
+.macro SET_BASE_FORCE xlen, basearch=i
+ .option arch, rv\xlen\basearch
+ .set XLEN, \xlen
+ UPDATE_XLEN
+.endm
+
+# Set the base architecture unless the symbol NOARCH_ARCH is set.
+.macro SET_BASE xlen, basearch=i
+ .if !NOARCH_ARCH
+ SET_BASE_FORCE \xlen, \basearch
+ .endif
+.endm
+
+# Begin base architecture block.
+.macro SET_BASE_START_FORCE xlen, basearch=i
+ .option push
+ SET_BASE_FORCE \xlen, \basearch
+.endm
+
+# Begin base architecture block.
+# Don't change the architecture if NOARCH_ARCH is set.
+.macro SET_BASE_START xlen, basearch=i
+ .option push
+ SET_BASE \xlen, \basearch
+.endm
+
+# End base architecture block.
+.macro SET_BASE_END
+ .option pop
+.endm
+
+# Set the architecture.
+.macro SET_ARCH_FORCE arch
+ .option arch, \arch
+.endm
+
+# Set the architecture unless the symbol NOARCH_ARCH is set.
+.macro SET_ARCH arch
+ .ifeq NOARCH_ARCH-0
+ SET_ARCH_FORCE \arch
+ .endif
+.endm
+
+# Begin architecture block.
+.macro SET_ARCH_START_FORCE arch
+ .option push
+ SET_ARCH_FORCE \arch
+.endm
+
+# Begin architecture block.
+# Don't change the architecture if NOARCH_ARCH is set.
+.macro SET_ARCH_START arch
+ .option push
+ SET_ARCH \arch
+.endm
+
+# End architecture block.
+.macro SET_ARCH_END
+ .option pop
+.endm
--
2.37.2
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 05/12] RISC-V: Redefine "nop" test
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
` (3 preceding siblings ...)
2022-11-05 12:29 ` [PATCH 04/12] RISC-V: GAS: Add basic shared test utilities Tsukasa OI
@ 2022-11-05 12:29 ` Tsukasa OI
2022-11-29 7:58 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 06/12] RISC-V: Reorganize/enhance {sign,zero}-extension instructions Tsukasa OI
` (7 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Tsukasa OI @ 2022-11-05 12:29 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
Seemingly, t_insns.[sd] was the first GAS test for RISC-V. This commit
redefines this test as a template of the new testing utility for
"nop" and "c.nop".
gas/ChangeLog:
* testsuite/gas/riscv/nop.s: New test.
* testsuite/gas/riscv/nop.d: New test.
* testsuite/gas/riscv/nop-noalias.d: New test.
* testsuite/gas/riscv/nop-noarch.d: New failure test.
* testsuite/gas/riscv/nop-noarch.l: Likewise.
* testsuite/gas/riscv/t_insns.d: Removed.
* testsuite/gas/riscv/t_insns.s: Removed.
---
gas/testsuite/gas/riscv/nop-noalias.d | 13 +++++++++++++
gas/testsuite/gas/riscv/nop-noarch.d | 3 +++
gas/testsuite/gas/riscv/nop-noarch.l | 2 ++
gas/testsuite/gas/riscv/nop.d | 12 ++++++++++++
gas/testsuite/gas/riscv/nop.s | 9 +++++++++
gas/testsuite/gas/riscv/t_insns.d | 10 ----------
gas/testsuite/gas/riscv/t_insns.s | 2 --
7 files changed, 39 insertions(+), 12 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/nop-noalias.d
create mode 100644 gas/testsuite/gas/riscv/nop-noarch.d
create mode 100644 gas/testsuite/gas/riscv/nop-noarch.l
create mode 100644 gas/testsuite/gas/riscv/nop.d
create mode 100644 gas/testsuite/gas/riscv/nop.s
delete mode 100644 gas/testsuite/gas/riscv/t_insns.d
delete mode 100644 gas/testsuite/gas/riscv/t_insns.s
diff --git a/gas/testsuite/gas/riscv/nop-noalias.d b/gas/testsuite/gas/riscv/nop-noalias.d
new file mode 100644
index 00000000000..8dca3c8e01f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/nop-noalias.d
@@ -0,0 +1,13 @@
+#as: -march=rv32i -I$srcdir/$subdir
+#source: nop.s
+#objdump: -d -M no-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+00000013[ ]+addi[ ]+zero,zero,0
+[ ]+[0-9a-f]+:[ ]+0001[ ]+c\.addi[ ]+zero,0
+[ ]+[0-9a-f]+:[ ]+0001[ ]+c\.addi[ ]+zero,0
diff --git a/gas/testsuite/gas/riscv/nop-noarch.d b/gas/testsuite/gas/riscv/nop-noarch.d
new file mode 100644
index 00000000000..d3fe5dc763e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/nop-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i -I$srcdir/$subdir -defsym NOARCH=1
+#source: nop.s
+#error_output: nop-noarch.l
diff --git a/gas/testsuite/gas/riscv/nop-noarch.l b/gas/testsuite/gas/riscv/nop-noarch.l
new file mode 100644
index 00000000000..4e418e1291d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/nop-noarch.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `c\.nop', extension `c' required
diff --git a/gas/testsuite/gas/riscv/nop.d b/gas/testsuite/gas/riscv/nop.d
new file mode 100644
index 00000000000..19b5fc13b55
--- /dev/null
+++ b/gas/testsuite/gas/riscv/nop.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i -I$srcdir/$subdir
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+00000013[ ]+nop
+[ ]+[0-9a-f]+:[ ]+0001[ ]+nop
+[ ]+[0-9a-f]+:[ ]+0001[ ]+nop
diff --git a/gas/testsuite/gas/riscv/nop.s b/gas/testsuite/gas/riscv/nop.s
new file mode 100644
index 00000000000..1a2dd75f3b1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/nop.s
@@ -0,0 +1,9 @@
+.include "testutils.inc"
+
+target:
+ nop
+ # Architecture block: change disabled when NOARCH is defined.
+ SET_ARCH_START +c
+ nop
+ c.nop
+ SET_ARCH_END
diff --git a/gas/testsuite/gas/riscv/t_insns.d b/gas/testsuite/gas/riscv/t_insns.d
deleted file mode 100644
index 720f0db2930..00000000000
--- a/gas/testsuite/gas/riscv/t_insns.d
+++ /dev/null
@@ -1,10 +0,0 @@
-#as:
-#objdump: -dr
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+00000013[ ]+nop
diff --git a/gas/testsuite/gas/riscv/t_insns.s b/gas/testsuite/gas/riscv/t_insns.s
deleted file mode 100644
index 99456883315..00000000000
--- a/gas/testsuite/gas/riscv/t_insns.s
+++ /dev/null
@@ -1,2 +0,0 @@
-target:
- nop
--
2.37.2
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 06/12] RISC-V: Reorganize/enhance {sign,zero}-extension instructions
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
` (4 preceding siblings ...)
2022-11-05 12:29 ` [PATCH 05/12] RISC-V: Redefine "nop" test Tsukasa OI
@ 2022-11-05 12:29 ` Tsukasa OI
2022-11-29 8:10 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 07/12] RISC-V: Combine complex extension error handling tests Tsukasa OI
` (6 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Tsukasa OI @ 2022-11-05 12:29 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
This commit:
- Clarifies the roles of {sign,zero}-extension instruction tests,
- Shortens ".s" file using macro,
- Enhances the tests with 'Zba' and 'Zbb' extensions and
- Makes some tidying (e.g. making matching patterns stricter).
gas/ChangeLog:
* testsuite/gas/riscv/ext-insn.s: Reorganize based on ext.s.
* testsuite/gas/riscv/ext-insn-32-noalias.d: Based on ext-32.d.
Make matching pattern stricter.
* testsuite/gas/riscv/ext-insn-64-noalias.d: Based on ext-64.d.
Make matching pattern stricter.
* testsuite/gas/riscv/ext-insn-32-noarch.d: New failure test.
* testsuite/gas/riscv/ext-insn-32-noarch.l: Likewise.
* testsuite/gas/riscv/ext-insn-64-noarch.d: New test to make sure
that NOARCH=1 does not make errors since all opcodes are valid.
* testsuite/gas/riscv/ext-insn-zba-32-noalias.d: Test with 'Zba'.
* testsuite/gas/riscv/ext-insn-zba-64-noalias.d: Likewise.
* testsuite/gas/riscv/ext-insn-zbb-32-noalias.d: Test with 'Zbb'.
* testsuite/gas/riscv/ext-insn-zbb-64-noalias.d: Likewise.
* testsuite/gas/riscv/ext.s: Removed.
* testsuite/gas/riscv/ext-32.d: Removed.
* testsuite/gas/riscv/ext-64.d: Removed.
---
gas/testsuite/gas/riscv/ext-32.d | 39 --------------
gas/testsuite/gas/riscv/ext-64.d | 51 -------------------
gas/testsuite/gas/riscv/ext-insn-32-noalias.d | 39 ++++++++++++++
gas/testsuite/gas/riscv/ext-insn-32-noarch.d | 3 ++
gas/testsuite/gas/riscv/ext-insn-32-noarch.l | 9 ++++
gas/testsuite/gas/riscv/ext-insn-64-noalias.d | 51 +++++++++++++++++++
gas/testsuite/gas/riscv/ext-insn-64-noarch.d | 5 ++
.../gas/riscv/ext-insn-zba-32-noalias.d | 39 ++++++++++++++
.../gas/riscv/ext-insn-zba-64-noalias.d | 47 +++++++++++++++++
.../gas/riscv/ext-insn-zbb-32-noalias.d | 27 ++++++++++
.../gas/riscv/ext-insn-zbb-64-noalias.d | 39 ++++++++++++++
gas/testsuite/gas/riscv/ext-insn.s | 23 +++++++++
gas/testsuite/gas/riscv/ext.s | 38 --------------
13 files changed, 282 insertions(+), 128 deletions(-)
delete mode 100644 gas/testsuite/gas/riscv/ext-32.d
delete mode 100644 gas/testsuite/gas/riscv/ext-64.d
create mode 100644 gas/testsuite/gas/riscv/ext-insn-32-noalias.d
create mode 100644 gas/testsuite/gas/riscv/ext-insn-32-noarch.d
create mode 100644 gas/testsuite/gas/riscv/ext-insn-32-noarch.l
create mode 100644 gas/testsuite/gas/riscv/ext-insn-64-noalias.d
create mode 100644 gas/testsuite/gas/riscv/ext-insn-64-noarch.d
create mode 100644 gas/testsuite/gas/riscv/ext-insn-zba-32-noalias.d
create mode 100644 gas/testsuite/gas/riscv/ext-insn-zba-64-noalias.d
create mode 100644 gas/testsuite/gas/riscv/ext-insn-zbb-32-noalias.d
create mode 100644 gas/testsuite/gas/riscv/ext-insn-zbb-64-noalias.d
create mode 100644 gas/testsuite/gas/riscv/ext-insn.s
delete mode 100644 gas/testsuite/gas/riscv/ext.s
diff --git a/gas/testsuite/gas/riscv/ext-32.d b/gas/testsuite/gas/riscv/ext-32.d
deleted file mode 100644
index 97daa31d0e9..00000000000
--- a/gas/testsuite/gas/riscv/ext-32.d
+++ /dev/null
@@ -1,39 +0,0 @@
-#as: -march=rv32i
-#source: ext.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+0ff57513[ ]+zext.b[ ]+a0,a0
-[ ]+4:[ ]+01051513[ ]+sll[ ]+a0,a0,0x10
-[ ]+8:[ ]+01055513[ ]+srl[ ]+a0,a0,0x10
-[ ]+c:[ ]+01851513[ ]+sll[ ]+a0,a0,0x18
-[ ]+10:[ ]+41855513[ ]+sra[ ]+a0,a0,0x18
-[ ]+14:[ ]+01051513[ ]+sll[ ]+a0,a0,0x10
-[ ]+18:[ ]+41055513[ ]+sra[ ]+a0,a0,0x10
-[ ]+1c:[ ]+0ff67593[ ]+zext.b[ ]+a1,a2
-[ ]+20:[ ]+01061593[ ]+sll[ ]+a1,a2,0x10
-[ ]+24:[ ]+0105d593[ ]+srl[ ]+a1,a1,0x10
-[ ]+28:[ ]+01861593[ ]+sll[ ]+a1,a2,0x18
-[ ]+2c:[ ]+4185d593[ ]+sra[ ]+a1,a1,0x18
-[ ]+30:[ ]+01061593[ ]+sll[ ]+a1,a2,0x10
-[ ]+34:[ ]+4105d593[ ]+sra[ ]+a1,a1,0x10
-[ ]+38:[ ]+0ff57513[ ]+zext.b[ ]+a0,a0
-[ ]+3c:[ ]+0542[ ]+sll[ ]+a0,a0,0x10
-[ ]+3e:[ ]+8141[ ]+srl[ ]+a0,a0,0x10
-[ ]+40:[ ]+0562[ ]+sll[ ]+a0,a0,0x18
-[ ]+42:[ ]+8561[ ]+sra[ ]+a0,a0,0x18
-[ ]+44:[ ]+0542[ ]+sll[ ]+a0,a0,0x10
-[ ]+46:[ ]+8541[ ]+sra[ ]+a0,a0,0x10
-[ ]+48:[ ]+0ff67593[ ]+zext.b[ ]+a1,a2
-[ ]+4c:[ ]+01061593[ ]+sll[ ]+a1,a2,0x10
-[ ]+50:[ ]+81c1[ ]+srl[ ]+a1,a1,0x10
-[ ]+52:[ ]+01861593[ ]+sll[ ]+a1,a2,0x18
-[ ]+56:[ ]+85e1[ ]+sra[ ]+a1,a1,0x18
-[ ]+58:[ ]+01061593[ ]+sll[ ]+a1,a2,0x10
-[ ]+5c:[ ]+85c1[ ]+sra[ ]+a1,a1,0x10
-#...
diff --git a/gas/testsuite/gas/riscv/ext-64.d b/gas/testsuite/gas/riscv/ext-64.d
deleted file mode 100644
index 1fe339c4af4..00000000000
--- a/gas/testsuite/gas/riscv/ext-64.d
+++ /dev/null
@@ -1,51 +0,0 @@
-#as: -march=rv64i -defsym __64_bit__=1
-#source: ext.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+0ff57513[ ]+zext.b[ ]+a0,a0
-[ ]+4:[ ]+03051513[ ]+sll[ ]+a0,a0,0x30
-[ ]+8:[ ]+03055513[ ]+srl[ ]+a0,a0,0x30
-[ ]+c:[ ]+03851513[ ]+sll[ ]+a0,a0,0x38
-[ ]+10:[ ]+43855513[ ]+sra[ ]+a0,a0,0x38
-[ ]+14:[ ]+03051513[ ]+sll[ ]+a0,a0,0x30
-[ ]+18:[ ]+43055513[ ]+sra[ ]+a0,a0,0x30
-[ ]+1c:[ ]+0ff67593[ ]+zext.b[ ]+a1,a2
-[ ]+20:[ ]+03061593[ ]+sll[ ]+a1,a2,0x30
-[ ]+24:[ ]+0305d593[ ]+srl[ ]+a1,a1,0x30
-[ ]+28:[ ]+03861593[ ]+sll[ ]+a1,a2,0x38
-[ ]+2c:[ ]+4385d593[ ]+sra[ ]+a1,a1,0x38
-[ ]+30:[ ]+03061593[ ]+sll[ ]+a1,a2,0x30
-[ ]+34:[ ]+4305d593[ ]+sra[ ]+a1,a1,0x30
-[ ]+38:[ ]+02051513[ ]+sll[ ]+a0,a0,0x20
-[ ]+3c:[ ]+02055513[ ]+srl[ ]+a0,a0,0x20
-[ ]+40:[ ]+0005051b[ ]+sext.w[ ]+a0,a0
-[ ]+44:[ ]+02061593[ ]+sll[ ]+a1,a2,0x20
-[ ]+48:[ ]+0205d593[ ]+srl[ ]+a1,a1,0x20
-[ ]+4c:[ ]+0006059b[ ]+sext.w[ ]+a1,a2
-[ ]+50:[ ]+0ff57513[ ]+zext.b[ ]+a0,a0
-[ ]+54:[ ]+1542[ ]+sll[ ]+a0,a0,0x30
-[ ]+56:[ ]+9141[ ]+srl[ ]+a0,a0,0x30
-[ ]+58:[ ]+1562[ ]+sll[ ]+a0,a0,0x38
-[ ]+5a:[ ]+9561[ ]+sra[ ]+a0,a0,0x38
-[ ]+5c:[ ]+1542[ ]+sll[ ]+a0,a0,0x30
-[ ]+5e:[ ]+9541[ ]+sra[ ]+a0,a0,0x30
-[ ]+60:[ ]+0ff67593[ ]+zext.b[ ]+a1,a2
-[ ]+64:[ ]+03061593[ ]+sll[ ]+a1,a2,0x30
-[ ]+68:[ ]+91c1[ ]+srl[ ]+a1,a1,0x30
-[ ]+6a:[ ]+03861593[ ]+sll[ ]+a1,a2,0x38
-[ ]+6e:[ ]+95e1[ ]+sra[ ]+a1,a1,0x38
-[ ]+70:[ ]+03061593[ ]+sll[ ]+a1,a2,0x30
-[ ]+74:[ ]+95c1[ ]+sra[ ]+a1,a1,0x30
-[ ]+76:[ ]+1502[ ]+sll[ ]+a0,a0,0x20
-[ ]+78:[ ]+9101[ ]+srl[ ]+a0,a0,0x20
-[ ]+7a:[ ]+2501[ ]+sext.w[ ]+a0,a0
-[ ]+7c:[ ]+02061593[ ]+sll[ ]+a1,a2,0x20
-[ ]+80:[ ]+9181[ ]+srl[ ]+a1,a1,0x20
-[ ]+82:[ ]+0006059b[ ]+sext.w[ ]+a1,a2
-#...
diff --git a/gas/testsuite/gas/riscv/ext-insn-32-noalias.d b/gas/testsuite/gas/riscv/ext-insn-32-noalias.d
new file mode 100644
index 00000000000..237fcf033d0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/ext-insn-32-noalias.d
@@ -0,0 +1,39 @@
+#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32
+#source: ext-insn.s
+#objdump: -d -M no-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
+[ ]+[0-9a-f]+:[ ]+01051513[ ]+slli[ ]+a0,a0,0x10
+[ ]+[0-9a-f]+:[ ]+01055513[ ]+srli[ ]+a0,a0,0x10
+[ ]+[0-9a-f]+:[ ]+01851513[ ]+slli[ ]+a0,a0,0x18
+[ ]+[0-9a-f]+:[ ]+41855513[ ]+srai[ ]+a0,a0,0x18
+[ ]+[0-9a-f]+:[ ]+01051513[ ]+slli[ ]+a0,a0,0x10
+[ ]+[0-9a-f]+:[ ]+41055513[ ]+srai[ ]+a0,a0,0x10
+[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
+[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
+[ ]+[0-9a-f]+:[ ]+0105d593[ ]+srli[ ]+a1,a1,0x10
+[ ]+[0-9a-f]+:[ ]+01861593[ ]+slli[ ]+a1,a2,0x18
+[ ]+[0-9a-f]+:[ ]+4185d593[ ]+srai[ ]+a1,a1,0x18
+[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
+[ ]+[0-9a-f]+:[ ]+4105d593[ ]+srai[ ]+a1,a1,0x10
+[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
+[ ]+[0-9a-f]+:[ ]+0542[ ]+c\.slli[ ]+a0,0x10
+[ ]+[0-9a-f]+:[ ]+8141[ ]+c\.srli[ ]+a0,0x10
+[ ]+[0-9a-f]+:[ ]+0562[ ]+c\.slli[ ]+a0,0x18
+[ ]+[0-9a-f]+:[ ]+8561[ ]+c\.srai[ ]+a0,0x18
+[ ]+[0-9a-f]+:[ ]+0542[ ]+c\.slli[ ]+a0,0x10
+[ ]+[0-9a-f]+:[ ]+8541[ ]+c\.srai[ ]+a0,0x10
+[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
+[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
+[ ]+[0-9a-f]+:[ ]+81c1[ ]+c\.srli[ ]+a1,0x10
+[ ]+[0-9a-f]+:[ ]+01861593[ ]+slli[ ]+a1,a2,0x18
+[ ]+[0-9a-f]+:[ ]+85e1[ ]+c\.srai[ ]+a1,0x18
+[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
+[ ]+[0-9a-f]+:[ ]+85c1[ ]+c\.srai[ ]+a1,0x10
+#...
diff --git a/gas/testsuite/gas/riscv/ext-insn-32-noarch.d b/gas/testsuite/gas/riscv/ext-insn-32-noarch.d
new file mode 100644
index 00000000000..7a2f4ddfec2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/ext-insn-32-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32 -defsym NOARCH=1
+#source: ext-insn.s
+#error_output: ext-insn-32-noarch.l
diff --git a/gas/testsuite/gas/riscv/ext-insn-32-noarch.l b/gas/testsuite/gas/riscv/ext-insn-32-noarch.l
new file mode 100644
index 00000000000..f5954f207f0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/ext-insn-32-noarch.l
@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `zext.w a0,a0'
+.*: Error: unrecognized opcode `sext.w a0,a0'
+.*: Error: unrecognized opcode `zext.w a1,a2'
+.*: Error: unrecognized opcode `sext.w a1,a2'
+.*: Error: unrecognized opcode `zext.w a0,a0'
+.*: Error: unrecognized opcode `sext.w a0,a0'
+.*: Error: unrecognized opcode `zext.w a1,a2'
+.*: Error: unrecognized opcode `sext.w a1,a2'
diff --git a/gas/testsuite/gas/riscv/ext-insn-64-noalias.d b/gas/testsuite/gas/riscv/ext-insn-64-noalias.d
new file mode 100644
index 00000000000..9a273eea0d7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/ext-insn-64-noalias.d
@@ -0,0 +1,51 @@
+#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64
+#source: ext-insn.s
+#objdump: -d -M no-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
+[ ]+[0-9a-f]+:[ ]+03051513[ ]+slli[ ]+a0,a0,0x30
+[ ]+[0-9a-f]+:[ ]+03055513[ ]+srli[ ]+a0,a0,0x30
+[ ]+[0-9a-f]+:[ ]+03851513[ ]+slli[ ]+a0,a0,0x38
+[ ]+[0-9a-f]+:[ ]+43855513[ ]+srai[ ]+a0,a0,0x38
+[ ]+[0-9a-f]+:[ ]+03051513[ ]+slli[ ]+a0,a0,0x30
+[ ]+[0-9a-f]+:[ ]+43055513[ ]+srai[ ]+a0,a0,0x30
+[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
+[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
+[ ]+[0-9a-f]+:[ ]+0305d593[ ]+srli[ ]+a1,a1,0x30
+[ ]+[0-9a-f]+:[ ]+03861593[ ]+slli[ ]+a1,a2,0x38
+[ ]+[0-9a-f]+:[ ]+4385d593[ ]+srai[ ]+a1,a1,0x38
+[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
+[ ]+[0-9a-f]+:[ ]+4305d593[ ]+srai[ ]+a1,a1,0x30
+[ ]+[0-9a-f]+:[ ]+02051513[ ]+slli[ ]+a0,a0,0x20
+[ ]+[0-9a-f]+:[ ]+02055513[ ]+srli[ ]+a0,a0,0x20
+[ ]+[0-9a-f]+:[ ]+0005051b[ ]+addiw[ ]+a0,a0,0
+[ ]+[0-9a-f]+:[ ]+02061593[ ]+slli[ ]+a1,a2,0x20
+[ ]+[0-9a-f]+:[ ]+0205d593[ ]+srli[ ]+a1,a1,0x20
+[ ]+[0-9a-f]+:[ ]+0006059b[ ]+addiw[ ]+a1,a2,0
+[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
+[ ]+[0-9a-f]+:[ ]+1542[ ]+c\.slli[ ]+a0,0x30
+[ ]+[0-9a-f]+:[ ]+9141[ ]+c\.srli[ ]+a0,0x30
+[ ]+[0-9a-f]+:[ ]+1562[ ]+c\.slli[ ]+a0,0x38
+[ ]+[0-9a-f]+:[ ]+9561[ ]+c\.srai[ ]+a0,0x38
+[ ]+[0-9a-f]+:[ ]+1542[ ]+c\.slli[ ]+a0,0x30
+[ ]+[0-9a-f]+:[ ]+9541[ ]+c\.srai[ ]+a0,0x30
+[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
+[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
+[ ]+[0-9a-f]+:[ ]+91c1[ ]+c\.srli[ ]+a1,0x30
+[ ]+[0-9a-f]+:[ ]+03861593[ ]+slli[ ]+a1,a2,0x38
+[ ]+[0-9a-f]+:[ ]+95e1[ ]+c\.srai[ ]+a1,0x38
+[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
+[ ]+[0-9a-f]+:[ ]+95c1[ ]+c\.srai[ ]+a1,0x30
+[ ]+[0-9a-f]+:[ ]+1502[ ]+c\.slli[ ]+a0,0x20
+[ ]+[0-9a-f]+:[ ]+9101[ ]+c\.srli[ ]+a0,0x20
+[ ]+[0-9a-f]+:[ ]+2501[ ]+c\.addiw[ ]+a0,0
+[ ]+[0-9a-f]+:[ ]+02061593[ ]+slli[ ]+a1,a2,0x20
+[ ]+[0-9a-f]+:[ ]+9181[ ]+c\.srli[ ]+a1,0x20
+[ ]+[0-9a-f]+:[ ]+0006059b[ ]+addiw[ ]+a1,a2,0
+#...
diff --git a/gas/testsuite/gas/riscv/ext-insn-64-noarch.d b/gas/testsuite/gas/riscv/ext-insn-64-noarch.d
new file mode 100644
index 00000000000..6061373bb71
--- /dev/null
+++ b/gas/testsuite/gas/riscv/ext-insn-64-noarch.d
@@ -0,0 +1,5 @@
+#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64 -defsym NOARCH=1
+#source: ext-insn.s
+#objdump: -d -M no-aliases
+
+#...
diff --git a/gas/testsuite/gas/riscv/ext-insn-zba-32-noalias.d b/gas/testsuite/gas/riscv/ext-insn-zba-32-noalias.d
new file mode 100644
index 00000000000..ccea949debc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/ext-insn-zba-32-noalias.d
@@ -0,0 +1,39 @@
+#as: -march=rv32i_zba -I$srcdir/$subdir -defsym XLEN=32
+#source: ext-insn.s
+#objdump: -d -M no-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
+[ ]+[0-9a-f]+:[ ]+01051513[ ]+slli[ ]+a0,a0,0x10
+[ ]+[0-9a-f]+:[ ]+01055513[ ]+srli[ ]+a0,a0,0x10
+[ ]+[0-9a-f]+:[ ]+01851513[ ]+slli[ ]+a0,a0,0x18
+[ ]+[0-9a-f]+:[ ]+41855513[ ]+srai[ ]+a0,a0,0x18
+[ ]+[0-9a-f]+:[ ]+01051513[ ]+slli[ ]+a0,a0,0x10
+[ ]+[0-9a-f]+:[ ]+41055513[ ]+srai[ ]+a0,a0,0x10
+[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
+[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
+[ ]+[0-9a-f]+:[ ]+0105d593[ ]+srli[ ]+a1,a1,0x10
+[ ]+[0-9a-f]+:[ ]+01861593[ ]+slli[ ]+a1,a2,0x18
+[ ]+[0-9a-f]+:[ ]+4185d593[ ]+srai[ ]+a1,a1,0x18
+[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
+[ ]+[0-9a-f]+:[ ]+4105d593[ ]+srai[ ]+a1,a1,0x10
+[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
+[ ]+[0-9a-f]+:[ ]+0542[ ]+c\.slli[ ]+a0,0x10
+[ ]+[0-9a-f]+:[ ]+8141[ ]+c\.srli[ ]+a0,0x10
+[ ]+[0-9a-f]+:[ ]+0562[ ]+c\.slli[ ]+a0,0x18
+[ ]+[0-9a-f]+:[ ]+8561[ ]+c\.srai[ ]+a0,0x18
+[ ]+[0-9a-f]+:[ ]+0542[ ]+c\.slli[ ]+a0,0x10
+[ ]+[0-9a-f]+:[ ]+8541[ ]+c\.srai[ ]+a0,0x10
+[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
+[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
+[ ]+[0-9a-f]+:[ ]+81c1[ ]+c\.srli[ ]+a1,0x10
+[ ]+[0-9a-f]+:[ ]+01861593[ ]+slli[ ]+a1,a2,0x18
+[ ]+[0-9a-f]+:[ ]+85e1[ ]+c\.srai[ ]+a1,0x18
+[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
+[ ]+[0-9a-f]+:[ ]+85c1[ ]+c\.srai[ ]+a1,0x10
+#...
diff --git a/gas/testsuite/gas/riscv/ext-insn-zba-64-noalias.d b/gas/testsuite/gas/riscv/ext-insn-zba-64-noalias.d
new file mode 100644
index 00000000000..a9e191a7449
--- /dev/null
+++ b/gas/testsuite/gas/riscv/ext-insn-zba-64-noalias.d
@@ -0,0 +1,47 @@
+#as: -march=rv64i_zba -I$srcdir/$subdir -defsym XLEN=64
+#source: ext-insn.s
+#objdump: -d -M no-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
+[ ]+[0-9a-f]+:[ ]+03051513[ ]+slli[ ]+a0,a0,0x30
+[ ]+[0-9a-f]+:[ ]+03055513[ ]+srli[ ]+a0,a0,0x30
+[ ]+[0-9a-f]+:[ ]+03851513[ ]+slli[ ]+a0,a0,0x38
+[ ]+[0-9a-f]+:[ ]+43855513[ ]+srai[ ]+a0,a0,0x38
+[ ]+[0-9a-f]+:[ ]+03051513[ ]+slli[ ]+a0,a0,0x30
+[ ]+[0-9a-f]+:[ ]+43055513[ ]+srai[ ]+a0,a0,0x30
+[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
+[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
+[ ]+[0-9a-f]+:[ ]+0305d593[ ]+srli[ ]+a1,a1,0x30
+[ ]+[0-9a-f]+:[ ]+03861593[ ]+slli[ ]+a1,a2,0x38
+[ ]+[0-9a-f]+:[ ]+4385d593[ ]+srai[ ]+a1,a1,0x38
+[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
+[ ]+[0-9a-f]+:[ ]+4305d593[ ]+srai[ ]+a1,a1,0x30
+[ ]+[0-9a-f]+:[ ]+0805053b[ ]+add\.uw[ ]+a0,a0,zero
+[ ]+[0-9a-f]+:[ ]+0005051b[ ]+addiw[ ]+a0,a0,0
+[ ]+[0-9a-f]+:[ ]+080605bb[ ]+add\.uw[ ]+a1,a2,zero
+[ ]+[0-9a-f]+:[ ]+0006059b[ ]+addiw[ ]+a1,a2,0
+[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
+[ ]+[0-9a-f]+:[ ]+1542[ ]+c\.slli[ ]+a0,0x30
+[ ]+[0-9a-f]+:[ ]+9141[ ]+c\.srli[ ]+a0,0x30
+[ ]+[0-9a-f]+:[ ]+1562[ ]+c\.slli[ ]+a0,0x38
+[ ]+[0-9a-f]+:[ ]+9561[ ]+c\.srai[ ]+a0,0x38
+[ ]+[0-9a-f]+:[ ]+1542[ ]+c\.slli[ ]+a0,0x30
+[ ]+[0-9a-f]+:[ ]+9541[ ]+c\.srai[ ]+a0,0x30
+[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
+[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
+[ ]+[0-9a-f]+:[ ]+91c1[ ]+c\.srli[ ]+a1,0x30
+[ ]+[0-9a-f]+:[ ]+03861593[ ]+slli[ ]+a1,a2,0x38
+[ ]+[0-9a-f]+:[ ]+95e1[ ]+c\.srai[ ]+a1,0x38
+[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
+[ ]+[0-9a-f]+:[ ]+95c1[ ]+c\.srai[ ]+a1,0x30
+[ ]+[0-9a-f]+:[ ]+0805053b[ ]+add\.uw[ ]+a0,a0,zero
+[ ]+[0-9a-f]+:[ ]+2501[ ]+c\.addiw[ ]+a0,0
+[ ]+[0-9a-f]+:[ ]+080605bb[ ]+add\.uw[ ]+a1,a2,zero
+[ ]+[0-9a-f]+:[ ]+0006059b[ ]+addiw[ ]+a1,a2,0
+#...
diff --git a/gas/testsuite/gas/riscv/ext-insn-zbb-32-noalias.d b/gas/testsuite/gas/riscv/ext-insn-zbb-32-noalias.d
new file mode 100644
index 00000000000..edb2dcde2cf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/ext-insn-zbb-32-noalias.d
@@ -0,0 +1,27 @@
+#as: -march=rv32i_zbb -I$srcdir/$subdir -defsym XLEN=32
+#source: ext-insn.s
+#objdump: -d -M no-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
+[ ]+[0-9a-f]+:[ ]+08054533[ ]+zext\.h[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+60451513[ ]+sext\.b[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+60551513[ ]+sext\.h[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
+[ ]+[0-9a-f]+:[ ]+080645b3[ ]+zext\.h[ ]+a1,a2
+[ ]+[0-9a-f]+:[ ]+60461593[ ]+sext\.b[ ]+a1,a2
+[ ]+[0-9a-f]+:[ ]+60561593[ ]+sext\.h[ ]+a1,a2
+[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
+[ ]+[0-9a-f]+:[ ]+08054533[ ]+zext\.h[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+60451513[ ]+sext\.b[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+60551513[ ]+sext\.h[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
+[ ]+[0-9a-f]+:[ ]+080645b3[ ]+zext\.h[ ]+a1,a2
+[ ]+[0-9a-f]+:[ ]+60461593[ ]+sext\.b[ ]+a1,a2
+[ ]+[0-9a-f]+:[ ]+60561593[ ]+sext\.h[ ]+a1,a2
+#...
diff --git a/gas/testsuite/gas/riscv/ext-insn-zbb-64-noalias.d b/gas/testsuite/gas/riscv/ext-insn-zbb-64-noalias.d
new file mode 100644
index 00000000000..bc7b6145e59
--- /dev/null
+++ b/gas/testsuite/gas/riscv/ext-insn-zbb-64-noalias.d
@@ -0,0 +1,39 @@
+#as: -march=rv64i_zbb -I$srcdir/$subdir -defsym XLEN=64
+#source: ext-insn.s
+#objdump: -d -M no-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
+[ ]+[0-9a-f]+:[ ]+0805453b[ ]+zext\.h[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+60451513[ ]+sext\.b[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+60551513[ ]+sext\.h[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
+[ ]+[0-9a-f]+:[ ]+080645bb[ ]+zext\.h[ ]+a1,a2
+[ ]+[0-9a-f]+:[ ]+60461593[ ]+sext\.b[ ]+a1,a2
+[ ]+[0-9a-f]+:[ ]+60561593[ ]+sext\.h[ ]+a1,a2
+[ ]+[0-9a-f]+:[ ]+02051513[ ]+slli[ ]+a0,a0,0x20
+[ ]+[0-9a-f]+:[ ]+02055513[ ]+srli[ ]+a0,a0,0x20
+[ ]+[0-9a-f]+:[ ]+0005051b[ ]+addiw[ ]+a0,a0,0
+[ ]+[0-9a-f]+:[ ]+02061593[ ]+slli[ ]+a1,a2,0x20
+[ ]+[0-9a-f]+:[ ]+0205d593[ ]+srli[ ]+a1,a1,0x20
+[ ]+[0-9a-f]+:[ ]+0006059b[ ]+addiw[ ]+a1,a2,0
+[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
+[ ]+[0-9a-f]+:[ ]+0805453b[ ]+zext\.h[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+60451513[ ]+sext\.b[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+60551513[ ]+sext\.h[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
+[ ]+[0-9a-f]+:[ ]+080645bb[ ]+zext\.h[ ]+a1,a2
+[ ]+[0-9a-f]+:[ ]+60461593[ ]+sext\.b[ ]+a1,a2
+[ ]+[0-9a-f]+:[ ]+60561593[ ]+sext\.h[ ]+a1,a2
+[ ]+[0-9a-f]+:[ ]+1502[ ]+c\.slli[ ]+a0,0x20
+[ ]+[0-9a-f]+:[ ]+9101[ ]+c\.srli[ ]+a0,0x20
+[ ]+[0-9a-f]+:[ ]+2501[ ]+c\.addiw[ ]+a0,0
+[ ]+[0-9a-f]+:[ ]+02061593[ ]+slli[ ]+a1,a2,0x20
+[ ]+[0-9a-f]+:[ ]+9181[ ]+c\.srli[ ]+a1,0x20
+[ ]+[0-9a-f]+:[ ]+0006059b[ ]+addiw[ ]+a1,a2,0
+#...
diff --git a/gas/testsuite/gas/riscv/ext-insn.s b/gas/testsuite/gas/riscv/ext-insn.s
new file mode 100644
index 00000000000..2e4dc1ed850
--- /dev/null
+++ b/gas/testsuite/gas/riscv/ext-insn.s
@@ -0,0 +1,23 @@
+.include "testutils.inc"
+
+.macro INSN_SEQ
+ zext.b a0, a0 # andi (I)
+ zext.h a0, a0 # Zbb (RV32!=RV64) / shifts (I/C)
+ sext.b a0, a0 # Zbb / shifts (I/C)
+ sext.h a0, a0 # Zbb / shifts (I/C)
+ zext.b a1, a2 # andi (I)
+ zext.h a1, a2 # Zbb (RV32!=RV64) / shifts (I/C)
+ sext.b a1, a2 # Zbb / shifts (I/C)
+ sext.h a1, a2 # Zbb / shifts (I/C)
+.if XLEN_GE_64
+ zext.w a0, a0 # add.uw (RV64_Zba) / shifts (I/C)
+ sext.w a0, a0 # addiw (I) / c.addiw (C)
+ zext.w a1, a2 # add.uw (RV64_Zba) / shifts (I/C)
+ sext.w a1, a2 # addiw (I/C)
+.endif
+.endm
+
+target:
+ INSN_SEQ
+ .option arch, +c
+ INSN_SEQ
diff --git a/gas/testsuite/gas/riscv/ext.s b/gas/testsuite/gas/riscv/ext.s
deleted file mode 100644
index 0268dcafc1d..00000000000
--- a/gas/testsuite/gas/riscv/ext.s
+++ /dev/null
@@ -1,38 +0,0 @@
-target:
- .option arch, -c
- zext.b a0, a0
- zext.h a0, a0
- sext.b a0, a0
- sext.h a0, a0
-
- zext.b a1, a2
- zext.h a1, a2
- sext.b a1, a2
- sext.h a1, a2
-
-.ifdef __64_bit__
- zext.w a0, a0
- sext.w a0, a0
-
- zext.w a1, a2
- sext.w a1, a2
-.endif
-
- .option arch, +c
- zext.b a0, a0
- zext.h a0, a0
- sext.b a0, a0
- sext.h a0, a0
-
- zext.b a1, a2
- zext.h a1, a2
- sext.b a1, a2
- sext.h a1, a2
-
-.ifdef __64_bit__
- zext.w a0, a0
- sext.w a0, a0
-
- zext.w a1, a2
- sext.w a1, a2
-.endif
--
2.37.2
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 07/12] RISC-V: Combine complex extension error handling tests
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
` (5 preceding siblings ...)
2022-11-05 12:29 ` [PATCH 06/12] RISC-V: Reorganize/enhance {sign,zero}-extension instructions Tsukasa OI
@ 2022-11-05 12:29 ` Tsukasa OI
2022-11-29 8:16 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 08/12] RISC-V: Refine/enhance 'M'/'Zmmul' extension tests Tsukasa OI
` (5 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Tsukasa OI @ 2022-11-05 12:29 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
Because mapping symbols with ISA string is now supported, we can now
combine five complex "no required extensions" testcases related to
the "fcvt.d.h" instruction into one.
gas/ChangeLog:
* testsuite/gas/riscv/zfhmin-d-noarch.s: Combined.
* testsuite/gas/riscv/zfhmin-d-noarch.d: Likewise.
Minimize extension requirements.
* testsuite/gas/riscv/zfhmin-d-noarch.l: Likewise.
Make matching pattern stricter.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail.s: Removed.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d: Removed.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l: Removed.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d: Removed.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l: Removed.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d: Removed.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l: Removed.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d: Removed.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l: Removed.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d: Removed.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l: Removed.
---
.../gas/riscv/zfhmin-d-insn-class-fail-1.d | 3 ---
.../gas/riscv/zfhmin-d-insn-class-fail-1.l | 2 --
.../gas/riscv/zfhmin-d-insn-class-fail-2.d | 3 ---
.../gas/riscv/zfhmin-d-insn-class-fail-2.l | 2 --
.../gas/riscv/zfhmin-d-insn-class-fail-3.d | 3 ---
.../gas/riscv/zfhmin-d-insn-class-fail-3.l | 2 --
.../gas/riscv/zfhmin-d-insn-class-fail-4.d | 3 ---
.../gas/riscv/zfhmin-d-insn-class-fail-4.l | 2 --
.../gas/riscv/zfhmin-d-insn-class-fail-5.d | 3 ---
.../gas/riscv/zfhmin-d-insn-class-fail-5.l | 2 --
.../gas/riscv/zfhmin-d-insn-class-fail.s | 4 ---
gas/testsuite/gas/riscv/zfhmin-d-noarch.d | 2 ++
gas/testsuite/gas/riscv/zfhmin-d-noarch.l | 6 +++++
gas/testsuite/gas/riscv/zfhmin-d-noarch.s | 25 +++++++++++++++++++
14 files changed, 33 insertions(+), 29 deletions(-)
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l
delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-noarch.l
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-noarch.s
diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d
deleted file mode 100644
index 02a11943cf2..00000000000
--- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv64i
-#source: zfhmin-d-insn-class-fail.s
-#error_output: zfhmin-d-insn-class-fail-1.l
diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l
deleted file mode 100644
index 12f41a39ae0..00000000000
--- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l
+++ /dev/null
@@ -1,2 +0,0 @@
-.*: Assembler messages:
-.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zfhmin' and `d', or `zhinxmin' and `zdinx' required
diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d
deleted file mode 100644
index 27b5a12857e..00000000000
--- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv64i_zhinxmin
-#source: zfhmin-d-insn-class-fail.s
-#error_output: zfhmin-d-insn-class-fail-2.l
diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l
deleted file mode 100644
index 255f96cb5a1..00000000000
--- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l
+++ /dev/null
@@ -1,2 +0,0 @@
-.*: Assembler messages:
-.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zdinx' required
diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d
deleted file mode 100644
index 4f195bfa7c5..00000000000
--- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv64i_zdinx
-#source: zfhmin-d-insn-class-fail.s
-#error_output: zfhmin-d-insn-class-fail-3.l
diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l
deleted file mode 100644
index 7ff7b278fe3..00000000000
--- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l
+++ /dev/null
@@ -1,2 +0,0 @@
-.*: Assembler messages:
-.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zhinxmin' required
diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d
deleted file mode 100644
index 940d48c5dfd..00000000000
--- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv64i_zfhmin
-#source: zfhmin-d-insn-class-fail.s
-#error_output: zfhmin-d-insn-class-fail-4.l
diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l
deleted file mode 100644
index 2d58e4ce1ce..00000000000
--- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l
+++ /dev/null
@@ -1,2 +0,0 @@
-.*: Assembler messages:
-.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `d' required
diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d
deleted file mode 100644
index af26d5e9ea7..00000000000
--- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv64id
-#source: zfhmin-d-insn-class-fail.s
-#error_output: zfhmin-d-insn-class-fail-5.l
diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l
deleted file mode 100644
index 2fa6e8c754b..00000000000
--- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l
+++ /dev/null
@@ -1,2 +0,0 @@
-.*: Assembler messages:
-.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zfhmin' required
diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s
deleted file mode 100644
index 691d0a929dc..00000000000
--- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s
+++ /dev/null
@@ -1,4 +0,0 @@
-# This test checks error message corresponding required extension(s).
-# Operands are invalid on Zhinxmin+Zdinx but they are not parsed since
-# extension test fails.
-fcvt.d.h fa0, fa1
diff --git a/gas/testsuite/gas/riscv/zfhmin-d-noarch.d b/gas/testsuite/gas/riscv/zfhmin-d-noarch.d
new file mode 100644
index 00000000000..fded578caea
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfhmin-d-noarch.d
@@ -0,0 +1,2 @@
+#as: -march=rv64i -I$srcdir/$subdir
+#error_output: zfhmin-d-noarch.l
diff --git a/gas/testsuite/gas/riscv/zfhmin-d-noarch.l b/gas/testsuite/gas/riscv/zfhmin-d-noarch.l
new file mode 100644
index 00000000000..8a55ccaac2b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfhmin-d-noarch.l
@@ -0,0 +1,6 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `fcvt\.d\.h fa0,fa1', extension `zfhmin' and `d', or `zhinxmin' and `zdinx' required
+.*: Error: unrecognized opcode `fcvt\.d\.h fa0,fa1', extension `d' required
+.*: Error: unrecognized opcode `fcvt\.d\.h fa0,fa1', extension `zfhmin' required
+.*: Error: unrecognized opcode `fcvt\.d\.h a0,a1', extension `zdinx' required
+.*: Error: unrecognized opcode `fcvt\.d\.h a0,a1', extension `zhinxmin' required
diff --git a/gas/testsuite/gas/riscv/zfhmin-d-noarch.s b/gas/testsuite/gas/riscv/zfhmin-d-noarch.s
new file mode 100644
index 00000000000..f247de1bd36
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfhmin-d-noarch.s
@@ -0,0 +1,25 @@
+.include "testutils.inc"
+
+target:
+ # Case 1: No 'Zfhmin', 'D', 'Zhinxmin' or 'Zdinx'
+ fcvt.d.h fa0, fa1
+
+ # Case 2: 'Zfhmin' but no 'D'
+ SET_ARCH_START +zfhmin
+ fcvt.d.h fa0, fa1
+ SET_ARCH_END
+
+ # Case 3: 'D' but no 'Zfhmin'
+ SET_ARCH_START +d
+ fcvt.d.h fa0, fa1
+ SET_ARCH_END
+
+ # Case 4: 'Zhinxmin' but no 'Zdinx'
+ SET_ARCH_START +zhinxmin
+ fcvt.d.h a0, a1
+ SET_ARCH_END
+
+ # Case 5: 'Zdinx' but no 'Zhinxmin'
+ SET_ARCH_START +zdinx
+ fcvt.d.h a0, a1
+ SET_ARCH_END
--
2.37.2
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 08/12] RISC-V: Refine/enhance 'M'/'Zmmul' extension tests
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
` (6 preceding siblings ...)
2022-11-05 12:29 ` [PATCH 07/12] RISC-V: Combine complex extension error handling tests Tsukasa OI
@ 2022-11-05 12:29 ` Tsukasa OI
2022-11-29 8:23 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 09/12] RISC-V: Combine/enhance 'Zicbo[mz]' " Tsukasa OI
` (4 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Tsukasa OI @ 2022-11-05 12:29 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
This commit refines tests for 'M' and 'Zmmul' extensions and adds "no
required extension" testcases based on new test utilities.
gas/ChangeLog:
* testsuite/gas/riscv/m-ext.s: Refine using new testing utils.
* testsuite/gas/riscv/m-ext-32.d: Refine.
* testsuite/gas/riscv/m-ext-32-noarch.d: New test.
* testsuite/gas/riscv/m-ext-32-noarch.l: Likewise.
* testsuite/gas/riscv/m-ext-32-noarch-m.d: New test ased on
m-ext-fail-zmmul-32.d but refine.
* testsuite/gas/riscv/m-ext-32-noarch-m.l: New test ased on
m-ext-fail-zmmul-32.l.
* testsuite/gas/riscv/m-ext-64.d: Refine.
* testsuite/gas/riscv/m-ext-64-noarch.d: New test ased on
m-ext-fail-noarch-64.d but refine.
* testsuite/gas/riscv/m-ext-64-noarch.l: New test ased on
m-ext-fail-noarch-64.l.
* testsuite/gas/riscv/m-ext-64-noarch-m.d: New test ased on
m-ext-fail-zmmul-64.d but refine.
* testsuite/gas/riscv/m-ext-64-noarch-m.l: New test ased on
m-ext-fail-zmmul-64.l.
* testsuite/gas/riscv/m-ext-fail-xlen-32.d: Removed.
* testsuite/gas/riscv/m-ext-fail-xlen-32.l: Removed.
* testsuite/gas/riscv/m-ext-fail-zmmul-32.d: Removed.
* testsuite/gas/riscv/m-ext-fail-zmmul-64.d: Removed.
* testsuite/gas/riscv/m-ext-fail-noarch-64.d: Removed.
* testsuite/gas/riscv/zmmul-32.d: Removed as duplicate.
* testsuite/gas/riscv/zmmul-64.d: Removed as duplicate.
---
gas/testsuite/gas/riscv/m-ext-32-noarch-m.d | 4 ++++
...-ext-fail-zmmul-32.l => m-ext-32-noarch-m.l} | 0
gas/testsuite/gas/riscv/m-ext-32-noarch.d | 4 ++++
gas/testsuite/gas/riscv/m-ext-32-noarch.l | 14 ++++++++++++++
gas/testsuite/gas/riscv/m-ext-32.d | 2 +-
gas/testsuite/gas/riscv/m-ext-64-noarch-m.d | 4 ++++
...-ext-fail-zmmul-64.l => m-ext-64-noarch-m.l} | 0
gas/testsuite/gas/riscv/m-ext-64-noarch.d | 4 ++++
...m-ext-fail-noarch-64.l => m-ext-64-noarch.l} | 0
gas/testsuite/gas/riscv/m-ext-64.d | 2 +-
gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d | 4 ----
gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d | 4 ----
gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l | 6 ------
gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d | 4 ----
gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d | 4 ----
gas/testsuite/gas/riscv/m-ext.s | 17 +++++++++++------
gas/testsuite/gas/riscv/zmmul-32.d | 14 --------------
gas/testsuite/gas/riscv/zmmul-64.d | 15 ---------------
18 files changed, 43 insertions(+), 59 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/m-ext-32-noarch-m.d
rename gas/testsuite/gas/riscv/{m-ext-fail-zmmul-32.l => m-ext-32-noarch-m.l} (100%)
create mode 100644 gas/testsuite/gas/riscv/m-ext-32-noarch.d
create mode 100644 gas/testsuite/gas/riscv/m-ext-32-noarch.l
create mode 100644 gas/testsuite/gas/riscv/m-ext-64-noarch-m.d
rename gas/testsuite/gas/riscv/{m-ext-fail-zmmul-64.l => m-ext-64-noarch-m.l} (100%)
create mode 100644 gas/testsuite/gas/riscv/m-ext-64-noarch.d
rename gas/testsuite/gas/riscv/{m-ext-fail-noarch-64.l => m-ext-64-noarch.l} (100%)
delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
delete mode 100644 gas/testsuite/gas/riscv/zmmul-32.d
delete mode 100644 gas/testsuite/gas/riscv/zmmul-64.d
diff --git a/gas/testsuite/gas/riscv/m-ext-32-noarch-m.d b/gas/testsuite/gas/riscv/m-ext-32-noarch-m.d
new file mode 100644
index 00000000000..1d05564125f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-32-noarch-m.d
@@ -0,0 +1,4 @@
+#as: -march=rv32i_zmmul -I$srcdir/$subdir -defsym XLEN=32 -defsym NOARCH_ARCH=1
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-32-noarch-m.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l b/gas/testsuite/gas/riscv/m-ext-32-noarch-m.l
similarity index 100%
rename from gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
rename to gas/testsuite/gas/riscv/m-ext-32-noarch-m.l
diff --git a/gas/testsuite/gas/riscv/m-ext-32-noarch.d b/gas/testsuite/gas/riscv/m-ext-32-noarch.d
new file mode 100644
index 00000000000..a708d429ac7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-32-noarch.d
@@ -0,0 +1,4 @@
+#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32 -defsym NOARCH=1
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-32-noarch.l
diff --git a/gas/testsuite/gas/riscv/m-ext-32-noarch.l b/gas/testsuite/gas/riscv/m-ext-32-noarch.l
new file mode 100644
index 00000000000..f9179f45bb4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-32-noarch.l
@@ -0,0 +1,14 @@
+.*Assembler messages:
+.*: Error: unrecognized opcode `mul a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `mulh a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `mulhsu a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `mulhu a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `div a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `rem a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `mulw a0,a1,a2'
+.*: Error: unrecognized opcode `divw a0,a1,a2'
+.*: Error: unrecognized opcode `divuw a0,a1,a2'
+.*: Error: unrecognized opcode `remw a0,a1,a2'
+.*: Error: unrecognized opcode `remuw a0,a1,a2'
diff --git a/gas/testsuite/gas/riscv/m-ext-32.d b/gas/testsuite/gas/riscv/m-ext-32.d
index fe2ef9af54b..02be2ef9569 100644
--- a/gas/testsuite/gas/riscv/m-ext-32.d
+++ b/gas/testsuite/gas/riscv/m-ext-32.d
@@ -1,4 +1,4 @@
-#as: -march=rv32im
+#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32
#source: m-ext.s
#objdump: -d
diff --git a/gas/testsuite/gas/riscv/m-ext-64-noarch-m.d b/gas/testsuite/gas/riscv/m-ext-64-noarch-m.d
new file mode 100644
index 00000000000..d74fbd0b682
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-64-noarch-m.d
@@ -0,0 +1,4 @@
+#as: -march=rv64i_zmmul -I$srcdir/$subdir -defsym XLEN=64 -defsym NOARCH_ARCH=1
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-64-noarch-m.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l b/gas/testsuite/gas/riscv/m-ext-64-noarch-m.l
similarity index 100%
rename from gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l
rename to gas/testsuite/gas/riscv/m-ext-64-noarch-m.l
diff --git a/gas/testsuite/gas/riscv/m-ext-64-noarch.d b/gas/testsuite/gas/riscv/m-ext-64-noarch.d
new file mode 100644
index 00000000000..2d7031e5a35
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-64-noarch.d
@@ -0,0 +1,4 @@
+#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64 -defsym NOARCH=1
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-64-noarch.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l b/gas/testsuite/gas/riscv/m-ext-64-noarch.l
similarity index 100%
rename from gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
rename to gas/testsuite/gas/riscv/m-ext-64-noarch.l
diff --git a/gas/testsuite/gas/riscv/m-ext-64.d b/gas/testsuite/gas/riscv/m-ext-64.d
index 05099b14e9e..ad086829ae5 100644
--- a/gas/testsuite/gas/riscv/m-ext-64.d
+++ b/gas/testsuite/gas/riscv/m-ext-64.d
@@ -1,4 +1,4 @@
-#as: -march=rv64im -defsym rv64=1
+#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64
#source: m-ext.s
#objdump: -d
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
deleted file mode 100644
index 3c4fc9a0a50..00000000000
--- a/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
+++ /dev/null
@@ -1,4 +0,0 @@
-#as: -march=rv64i -defsym rv64=1
-#source: m-ext.s
-#objdump: -d
-#error_output: m-ext-fail-noarch-64.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
deleted file mode 100644
index 54f8b8225dc..00000000000
--- a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
+++ /dev/null
@@ -1,4 +0,0 @@
-#as: -march=rv32im -defsym rv64=1
-#source: m-ext.s
-#objdump: -d
-#error_output: m-ext-fail-xlen-32.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
deleted file mode 100644
index d65ca4980e6..00000000000
--- a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
+++ /dev/null
@@ -1,6 +0,0 @@
-.*Assembler messages:
-.*: Error: unrecognized opcode `mulw a0,a1,a2'
-.*: Error: unrecognized opcode `divw a0,a1,a2'
-.*: Error: unrecognized opcode `divuw a0,a1,a2'
-.*: Error: unrecognized opcode `remw a0,a1,a2'
-.*: Error: unrecognized opcode `remuw a0,a1,a2'
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
deleted file mode 100644
index c164fa96f8f..00000000000
--- a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
+++ /dev/null
@@ -1,4 +0,0 @@
-#as: -march=rv32i_zmmul
-#source: m-ext.s
-#objdump: -d
-#error_output: m-ext-fail-zmmul-32.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
deleted file mode 100644
index f736d9c66c6..00000000000
--- a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
+++ /dev/null
@@ -1,4 +0,0 @@
-#as: -march=rv64i_zmmul -defsym rv64=1
-#source: m-ext.s
-#objdump: -d
-#error_output: m-ext-fail-zmmul-64.l
diff --git a/gas/testsuite/gas/riscv/m-ext.s b/gas/testsuite/gas/riscv/m-ext.s
index 68baf2ab9c0..8d599f20aef 100644
--- a/gas/testsuite/gas/riscv/m-ext.s
+++ b/gas/testsuite/gas/riscv/m-ext.s
@@ -1,21 +1,26 @@
+.include "testutils.inc"
+
target:
+ SET_ARCH_START +zmmul
mul a0, a1, a2
mulh a0, a1, a2
mulhsu a0, a1, a2
mulhu a0, a1, a2
-.ifndef zmmul
+ SET_ARCH_START +m
div a0, a1, a2
divu a0, a1, a2
rem a0, a1, a2
remu a0, a1, a2
-.endif
-
-.ifdef rv64
+ SET_ARCH_END
+ SET_ARCH_END
+.if XLEN_GE_64
+ SET_ARCH_START +zmmul
mulw a0, a1, a2
-.ifndef zmmul
+ SET_ARCH_START +m
divw a0, a1, a2
divuw a0, a1, a2
remw a0, a1, a2
remuw a0, a1, a2
-.endif
+ SET_ARCH_END
+ SET_ARCH_END
.endif
diff --git a/gas/testsuite/gas/riscv/zmmul-32.d b/gas/testsuite/gas/riscv/zmmul-32.d
deleted file mode 100644
index c9cf56ab33f..00000000000
--- a/gas/testsuite/gas/riscv/zmmul-32.d
+++ /dev/null
@@ -1,14 +0,0 @@
-#as: -march=rv32im -defsym zmmul=1
-#source: m-ext.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+02c58533[ ]+mul[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+02c59533[ ]+mulh[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+02c5a533[ ]+mulhsu[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+02c5b533[ ]+mulhu[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zmmul-64.d b/gas/testsuite/gas/riscv/zmmul-64.d
deleted file mode 100644
index 67ef3604755..00000000000
--- a/gas/testsuite/gas/riscv/zmmul-64.d
+++ /dev/null
@@ -1,15 +0,0 @@
-#as: -march=rv64im -defsym zmmul=1 -defsym rv64=1
-#source: m-ext.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+02c58533[ ]+mul[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+02c59533[ ]+mulh[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+02c5a533[ ]+mulhsu[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+02c5b533[ ]+mulhu[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+02c5853b[ ]+mulw[ ]+a0,a1,a2
--
2.37.2
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 09/12] RISC-V: Combine/enhance 'Zicbo[mz]' extension tests
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
` (7 preceding siblings ...)
2022-11-05 12:29 ` [PATCH 08/12] RISC-V: Refine/enhance 'M'/'Zmmul' extension tests Tsukasa OI
@ 2022-11-05 12:29 ` Tsukasa OI
2022-11-29 8:38 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 10/12] RISC-V: Enhance 'Zicbop' testcases Tsukasa OI
` (3 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Tsukasa OI @ 2022-11-05 12:29 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
This commit combines tests for 'Zicbom' and 'Zicboz' extensions and adds
"no required extension" testcases based on new test utilities. It also
contains minor tidying (such as minimizing base from RV64G to RV32I).
gas/ChangeLog:
* testsuite/gas/riscv/zicbo-mz-ext.s: Combine zicbo[mz].s.
* testsuite/gas/riscv/zicbo-mz-ext.d: Likewise.
Minimize extension requirements and remove source.
* testsuite/gas/riscv/zicbo-mz-ext-noarch.d: New test for
architecture failure.
* testsuite/gas/riscv/zicbo-mz-ext-noarch.l: Likewise.
* testsuite/gas/riscv/zicbo-mz-ext-fail.s: Combine
zicbo[mz]-fail.s.
* testsuite/gas/riscv/zicbo-mz-ext-fail.d: Likewise.
Minimize extension requirements.
* testsuite/gas/riscv/zicbo-mz-ext-fail.l: Likewise.
Make matching pattern stricter.
* testsuite/gas/riscv/zicbom.s: Removed.
* testsuite/gas/riscv/zicbom.d: Removed.
* testsuite/gas/riscv/zicbom-fail.s: Removed.
* testsuite/gas/riscv/zicbom-fail.d: Removed.
* testsuite/gas/riscv/zicbom-fail.l: Removed.
* testsuite/gas/riscv/zicboz.s: Removed.
* testsuite/gas/riscv/zicboz.d: Removed.
* testsuite/gas/riscv/zicboz-fail.s: Removed.
* testsuite/gas/riscv/zicboz-fail.d: Removed.
* testsuite/gas/riscv/zicboz-fail.l: Removed.
---
gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d | 2 ++
gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l | 11 +++++++++++
.../riscv/{zicbom-fail.s => zicbo-mz-ext-fail.s} | 4 ++++
gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d | 3 +++
gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l | 11 +++++++++++
.../gas/riscv/{zicbom.d => zicbo-mz-ext.d} | 9 ++++++---
gas/testsuite/gas/riscv/zicbo-mz-ext.s | 16 ++++++++++++++++
gas/testsuite/gas/riscv/zicbom-fail.d | 3 ---
gas/testsuite/gas/riscv/zicbom-fail.l | 7 -------
gas/testsuite/gas/riscv/zicbom.s | 7 -------
gas/testsuite/gas/riscv/zicboz-fail.d | 3 ---
gas/testsuite/gas/riscv/zicboz-fail.l | 5 -----
gas/testsuite/gas/riscv/zicboz-fail.s | 5 -----
gas/testsuite/gas/riscv/zicboz.d | 13 -------------
gas/testsuite/gas/riscv/zicboz.s | 5 -----
15 files changed, 53 insertions(+), 51 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d
create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l
rename gas/testsuite/gas/riscv/{zicbom-fail.s => zicbo-mz-ext-fail.s} (61%)
create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l
rename gas/testsuite/gas/riscv/{zicbom.d => zicbo-mz-ext.d} (60%)
create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext.s
delete mode 100644 gas/testsuite/gas/riscv/zicbom-fail.d
delete mode 100644 gas/testsuite/gas/riscv/zicbom-fail.l
delete mode 100644 gas/testsuite/gas/riscv/zicbom.s
delete mode 100644 gas/testsuite/gas/riscv/zicboz-fail.d
delete mode 100644 gas/testsuite/gas/riscv/zicboz-fail.l
delete mode 100644 gas/testsuite/gas/riscv/zicboz-fail.s
delete mode 100644 gas/testsuite/gas/riscv/zicboz.d
delete mode 100644 gas/testsuite/gas/riscv/zicboz.s
diff --git a/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d b/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d
new file mode 100644
index 00000000000..e84233b09a1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d
@@ -0,0 +1,2 @@
+#as: -march=rv32i_zicbom_zicboz
+#error_output: zicbo-mz-ext-fail.l
diff --git a/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l b/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l
new file mode 100644
index 00000000000..a0bd7096f25
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l
@@ -0,0 +1,11 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cbo\.clean 1\(x1\)'
+.*: Error: illegal operands `cbo\.clean x30'
+.*: Error: illegal operands `cbo\.flush \(0\+1\)\(x1\)'
+.*: Error: illegal operands `cbo\.flush x30'
+.*: Error: illegal operands `cbo\.inval 3\*2\+5\(x1\)'
+.*: Error: illegal operands `cbo\.inval x30'
+.*: Error: illegal operands `cbo\.zero x1'
+.*: Error: illegal operands `cbo\.zero 1\(x30\)'
+.*: Error: illegal operands `cbo\.zero 3\+5\(x1\)'
+.*: Error: illegal operands `cbo\.zero \(2\*4\)\(x30\)'
diff --git a/gas/testsuite/gas/riscv/zicbom-fail.s b/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.s
similarity index 61%
rename from gas/testsuite/gas/riscv/zicbom-fail.s
rename to gas/testsuite/gas/riscv/zicbo-mz-ext-fail.s
index 5fa22749b3a..447e9c37de7 100644
--- a/gas/testsuite/gas/riscv/zicbom-fail.s
+++ b/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.s
@@ -5,3 +5,7 @@ target:
cbo.flush x30
cbo.inval 3*2+5(x1)
cbo.inval x30
+ cbo.zero x1
+ cbo.zero 1(x30)
+ cbo.zero 3+5(x1)
+ cbo.zero (2*4)(x30)
diff --git a/gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d b/gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d
new file mode 100644
index 00000000000..33db96dd471
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i -I$srcdir/$subdir -defsym NOARCH=1
+#source: zicbo-mz-ext.s
+#error_output: zicbo-mz-ext-noarch.l
diff --git a/gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l b/gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l
new file mode 100644
index 00000000000..6cf1e4821a2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l
@@ -0,0 +1,11 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `cbo\.clean \(x1\)', extension `zicbom' required
+.*: Error: unrecognized opcode `cbo\.clean 0\(x30\)', extension `zicbom' required
+.*: Error: unrecognized opcode `cbo\.flush \(x1\)', extension `zicbom' required
+.*: Error: unrecognized opcode `cbo\.flush \(2-2\)\(x30\)', extension `zicbom' required
+.*: Error: unrecognized opcode `cbo\.inval \(x1\)', extension `zicbom' required
+.*: Error: unrecognized opcode `cbo\.inval 3\*4-12\(x30\)', extension `zicbom' required
+.*: Error: unrecognized opcode `cbo\.zero 0\(x1\)', extension `zicboz' required
+.*: Error: unrecognized opcode `cbo\.zero \(x30\)', extension `zicboz' required
+.*: Error: unrecognized opcode `cbo\.zero 2-2\(x1\)', extension `zicboz' required
+.*: Error: unrecognized opcode `cbo\.zero \(3\*5-15\)\(x30\)', extension `zicboz' required
diff --git a/gas/testsuite/gas/riscv/zicbom.d b/gas/testsuite/gas/riscv/zicbo-mz-ext.d
similarity index 60%
rename from gas/testsuite/gas/riscv/zicbom.d
rename to gas/testsuite/gas/riscv/zicbo-mz-ext.d
index edd8a7079f4..9daa1cc4a93 100644
--- a/gas/testsuite/gas/riscv/zicbom.d
+++ b/gas/testsuite/gas/riscv/zicbo-mz-ext.d
@@ -1,6 +1,5 @@
-#as: -march=rv64g_zicbom
-#source: zicbom.s
-#objdump: -dr
+#as: -march=rv32i -I$srcdir/$subdir
+#objdump: -d
.*:[ ]+file format .*
@@ -13,3 +12,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+002f200f[ ]+cbo\.flush[ ]+\(t5\)
[ ]+[0-9a-f]+:[ ]+0000a00f[ ]+cbo\.inval[ ]+\(ra\)
[ ]+[0-9a-f]+:[ ]+000f200f[ ]+cbo\.inval[ ]+\(t5\)
+[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+\(ra\)
+[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+\(t5\)
+[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+\(ra\)
+[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+\(t5\)
diff --git a/gas/testsuite/gas/riscv/zicbo-mz-ext.s b/gas/testsuite/gas/riscv/zicbo-mz-ext.s
new file mode 100644
index 00000000000..af997377903
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbo-mz-ext.s
@@ -0,0 +1,16 @@
+.include "testutils.inc"
+target:
+ SET_ARCH_START +zicbom
+ cbo.clean (x1)
+ cbo.clean 0(x30)
+ cbo.flush (x1)
+ cbo.flush (2-2)(x30)
+ cbo.inval (x1)
+ cbo.inval 3*4-12(x30)
+ SET_ARCH_END
+ SET_ARCH_START +zicboz
+ cbo.zero 0(x1)
+ cbo.zero (x30)
+ cbo.zero 2-2(x1)
+ cbo.zero (3*5-15)(x30)
+ SET_ARCH_END
diff --git a/gas/testsuite/gas/riscv/zicbom-fail.d b/gas/testsuite/gas/riscv/zicbom-fail.d
deleted file mode 100644
index a6a61dfd37e..00000000000
--- a/gas/testsuite/gas/riscv/zicbom-fail.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv64g_zicbom
-#source: zicbom-fail.s
-#error_output: zicbom-fail.l
diff --git a/gas/testsuite/gas/riscv/zicbom-fail.l b/gas/testsuite/gas/riscv/zicbom-fail.l
deleted file mode 100644
index 2cf76356d2b..00000000000
--- a/gas/testsuite/gas/riscv/zicbom-fail.l
+++ /dev/null
@@ -1,7 +0,0 @@
-.*: Assembler messages:
-.*: Error: illegal operands `cbo.clean 1\(x1\)'
-.*: Error: illegal operands `cbo.clean x30'
-.*: Error: illegal operands `cbo.flush \(0\+1\)\(x1\)'
-.*: Error: illegal operands `cbo.flush x30'
-.*: Error: illegal operands `cbo.inval 3\*2\+5\(x1\)'
-.*: Error: illegal operands `cbo.inval x30'
diff --git a/gas/testsuite/gas/riscv/zicbom.s b/gas/testsuite/gas/riscv/zicbom.s
deleted file mode 100644
index 6a306b931ed..00000000000
--- a/gas/testsuite/gas/riscv/zicbom.s
+++ /dev/null
@@ -1,7 +0,0 @@
-target:
- cbo.clean (x1)
- cbo.clean 0(x30)
- cbo.flush (x1)
- cbo.flush (2-2)(x30)
- cbo.inval (x1)
- cbo.inval 3*4-12(x30)
diff --git a/gas/testsuite/gas/riscv/zicboz-fail.d b/gas/testsuite/gas/riscv/zicboz-fail.d
deleted file mode 100644
index 74cfd2fc911..00000000000
--- a/gas/testsuite/gas/riscv/zicboz-fail.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv64g_zicboz
-#source: zicboz-fail.s
-#error_output: zicboz-fail.l
diff --git a/gas/testsuite/gas/riscv/zicboz-fail.l b/gas/testsuite/gas/riscv/zicboz-fail.l
deleted file mode 100644
index ad8dcf54e00..00000000000
--- a/gas/testsuite/gas/riscv/zicboz-fail.l
+++ /dev/null
@@ -1,5 +0,0 @@
-.*: Assembler messages:
-.*: Error: illegal operands `cbo.zero x1'
-.*: Error: illegal operands `cbo.zero 1\(x30\)'
-.*: Error: illegal operands `cbo.zero 3\+5\(x1\)'
-.*: Error: illegal operands `cbo.zero \(2\*4\)\(x30\)'
diff --git a/gas/testsuite/gas/riscv/zicboz-fail.s b/gas/testsuite/gas/riscv/zicboz-fail.s
deleted file mode 100644
index 0856ea85ab1..00000000000
--- a/gas/testsuite/gas/riscv/zicboz-fail.s
+++ /dev/null
@@ -1,5 +0,0 @@
-target:
- cbo.zero x1
- cbo.zero 1(x30)
- cbo.zero 3+5(x1)
- cbo.zero (2*4)(x30)
diff --git a/gas/testsuite/gas/riscv/zicboz.d b/gas/testsuite/gas/riscv/zicboz.d
deleted file mode 100644
index e04ab3491db..00000000000
--- a/gas/testsuite/gas/riscv/zicboz.d
+++ /dev/null
@@ -1,13 +0,0 @@
-#as: -march=rv64g_zicboz
-#source: zicboz.s
-#objdump: -dr
-
-.*:[ ]+file format .*
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+\(ra\)
-[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+\(t5\)
-[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+\(ra\)
-[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+\(t5\)
diff --git a/gas/testsuite/gas/riscv/zicboz.s b/gas/testsuite/gas/riscv/zicboz.s
deleted file mode 100644
index 3830362c376..00000000000
--- a/gas/testsuite/gas/riscv/zicboz.s
+++ /dev/null
@@ -1,5 +0,0 @@
-target:
- cbo.zero 0(x1)
- cbo.zero (x30)
- cbo.zero 2-2(x1)
- cbo.zero (3*5-15)(x30)
--
2.37.2
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 10/12] RISC-V: Enhance 'Zicbop' testcases
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
` (8 preceding siblings ...)
2022-11-05 12:29 ` [PATCH 09/12] RISC-V: Combine/enhance 'Zicbo[mz]' " Tsukasa OI
@ 2022-11-05 12:29 ` Tsukasa OI
2022-11-29 8:51 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 11/12] RISC-V: Reorganize/enhance 'Zb*' extension tests Tsukasa OI
` (2 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Tsukasa OI @ 2022-11-05 12:29 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
This commit makes some tidying and enhancements to 'Zicbop' testcases.
It adds "no required extension" testcases based on new test utilities. It
adds the hint of the failure reason to the file names.
gas/ChangeLog:
* testsuite/gas/riscv/zicbop.s: Enhanced to test offset zero.
* testsuite/gas/riscv/zicbop.d: Likewise.
Minimize extension requirements and objdump options.
* testsuite/gas/riscv/zicbop-noarch.s: New test for
architecture failure.
* testsuite/gas/riscv/zicbop-noarch.d: Likewise.
* testsuite/gas/riscv/zicbop-noarch.l: Likewise.
* testsuite/gas/riscv/zicbop-fail-offset.s: Move from
zicbop-fail.s.
* testsuite/gas/riscv/zicbop-fail-offset.d: Likewise.
Minimize extension requirements.
* testsuite/gas/riscv/zicbop-fail-offset.l: Likewise.
* testsuite/gas/riscv/zicbop-fail.s: Removed.
* testsuite/gas/riscv/zicbop-fail.d: Removed.
* testsuite/gas/riscv/zicbop-fail.l: Removed.
---
gas/testsuite/gas/riscv/zicbop-fail-offset.d | 2 ++
.../gas/riscv/{zicbop-fail.l => zicbop-fail-offset.l} | 0
.../gas/riscv/{zicbop-fail.s => zicbop-fail-offset.s} | 0
gas/testsuite/gas/riscv/zicbop-fail.d | 3 ---
gas/testsuite/gas/riscv/zicbop-noarch.d | 4 ++++
gas/testsuite/gas/riscv/zicbop-noarch.l | 7 +++++++
gas/testsuite/gas/riscv/zicbop.d | 8 +++++---
gas/testsuite/gas/riscv/zicbop.s | 7 +++++++
8 files changed, 25 insertions(+), 6 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/zicbop-fail-offset.d
rename gas/testsuite/gas/riscv/{zicbop-fail.l => zicbop-fail-offset.l} (100%)
rename gas/testsuite/gas/riscv/{zicbop-fail.s => zicbop-fail-offset.s} (100%)
delete mode 100644 gas/testsuite/gas/riscv/zicbop-fail.d
create mode 100644 gas/testsuite/gas/riscv/zicbop-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zicbop-noarch.l
diff --git a/gas/testsuite/gas/riscv/zicbop-fail-offset.d b/gas/testsuite/gas/riscv/zicbop-fail-offset.d
new file mode 100644
index 00000000000..4680f6eef0d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop-fail-offset.d
@@ -0,0 +1,2 @@
+#as: -march=rv32i_zicbop
+#error_output: zicbop-fail-offset.l
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.l b/gas/testsuite/gas/riscv/zicbop-fail-offset.l
similarity index 100%
rename from gas/testsuite/gas/riscv/zicbop-fail.l
rename to gas/testsuite/gas/riscv/zicbop-fail-offset.l
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.s b/gas/testsuite/gas/riscv/zicbop-fail-offset.s
similarity index 100%
rename from gas/testsuite/gas/riscv/zicbop-fail.s
rename to gas/testsuite/gas/riscv/zicbop-fail-offset.s
diff --git a/gas/testsuite/gas/riscv/zicbop-fail.d b/gas/testsuite/gas/riscv/zicbop-fail.d
deleted file mode 100644
index d734c7d4d15..00000000000
--- a/gas/testsuite/gas/riscv/zicbop-fail.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv64g_zicbop
-#source: zicbop-fail.s
-#error_output: zicbop-fail.l
diff --git a/gas/testsuite/gas/riscv/zicbop-noarch.d b/gas/testsuite/gas/riscv/zicbop-noarch.d
new file mode 100644
index 00000000000..2f51eb9b8d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop-noarch.d
@@ -0,0 +1,4 @@
+#as: -march=rv32i -I$srcdir/$subdir -defsym NOARCH=1
+#source: zicbop.s
+#objdump: -d
+#error_output: zicbop-noarch.l
diff --git a/gas/testsuite/gas/riscv/zicbop-noarch.l b/gas/testsuite/gas/riscv/zicbop-noarch.l
new file mode 100644
index 00000000000..742fedd9009
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbop-noarch.l
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `prefetch\.i \(x1\)', extension `zicbop' required
+.*: Error: unrecognized opcode `prefetch\.i 0x20\(x1\)', extension `zicbop' required
+.*: Error: unrecognized opcode `prefetch\.r \(x16\)', extension `zicbop' required
+.*: Error: unrecognized opcode `prefetch\.r -2048\(x16\)', extension `zicbop' required
+.*: Error: unrecognized opcode `prefetch\.w \(x31\)', extension `zicbop' required
+.*: Error: unrecognized opcode `prefetch\.w \+0x7e0\(x31\)', extension `zicbop' required
diff --git a/gas/testsuite/gas/riscv/zicbop.d b/gas/testsuite/gas/riscv/zicbop.d
index 056a8a501ff..b19ead39cd6 100644
--- a/gas/testsuite/gas/riscv/zicbop.d
+++ b/gas/testsuite/gas/riscv/zicbop.d
@@ -1,12 +1,14 @@
-#as: -march=rv64g_zicbop
-#source: zicbop.s
-#objdump: -dr
+#as: -march=rv32i -I$srcdir/$subdir
+#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0000e013[ ]+prefetch\.i[ ]+0\(ra\)
[ ]+[0-9a-f]+:[ ]+0200e013[ ]+prefetch\.i[ ]+32\(ra\)
+[ ]+[0-9a-f]+:[ ]+00186013[ ]+prefetch\.r[ ]+0\(a6\)
[ ]+[0-9a-f]+:[ ]+80186013[ ]+prefetch\.r[ ]+-2048\(a6\)
+[ ]+[0-9a-f]+:[ ]+003fe013[ ]+prefetch\.w[ ]+0\(t6\)
[ ]+[0-9a-f]+:[ ]+7e3fe013[ ]+prefetch\.w[ ]+2016\(t6\)
diff --git a/gas/testsuite/gas/riscv/zicbop.s b/gas/testsuite/gas/riscv/zicbop.s
index ffe2014be6f..698bb5d0d8e 100644
--- a/gas/testsuite/gas/riscv/zicbop.s
+++ b/gas/testsuite/gas/riscv/zicbop.s
@@ -1,4 +1,11 @@
+.include "testutils.inc"
+
target:
+ SET_ARCH_START +zicbop
+ prefetch.i (x1)
prefetch.i 0x20(x1)
+ prefetch.r (x16)
prefetch.r -2048(x16)
+ prefetch.w (x31)
prefetch.w +0x7e0(x31)
+ SET_ARCH_END
--
2.37.2
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 11/12] RISC-V: Reorganize/enhance 'Zb*' extension tests
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
` (9 preceding siblings ...)
2022-11-05 12:29 ` [PATCH 10/12] RISC-V: Enhance 'Zicbop' testcases Tsukasa OI
@ 2022-11-05 12:29 ` Tsukasa OI
2022-11-29 8:57 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 12/12] RISC-V: Combine/enhance 'Zk*'/'Zbk*' " Tsukasa OI
2022-11-20 2:28 ` [PING^1][PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
12 siblings, 1 reply; 26+ messages in thread
From: Tsukasa OI @ 2022-11-05 12:29 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
This commit reorganizes tests for 'Zb*' extensions and adds "no required
extension" testcases based on new test utilities. It also contains minor
tidying (such as using different registers per operand).
gas/ChangeLog:
* testsuite/gas/riscv/zb-ext.s: Reorganize and make some tidying.
* testsuite/gas/riscv/zb-ext-32.d: Reflect new zb-ext.s.
Make matching pattern stricter.
* testsuite/gas/riscv/zb-ext-64.d: Likewise.
* testsuite/gas/riscv/zb-ext-32-noalias.d: Likewise.
* testsuite/gas/riscv/zb-ext-64-noalias.d: Likewise.
* testsuite/gas/riscv/zb-ext-32-noarch.d: New test.
* testsuite/gas/riscv/zb-ext-32-noarch.l: Likewise.
* testsuite/gas/riscv/zb-ext-64-noarch.d: New test.
* testsuite/gas/riscv/zb-ext-64-noarch.l: Likewise.
* testsuite/gas/riscv/b-ext.s: Removed.
* testsuite/gas/riscv/b-ext.d: Removed.
* testsuite/gas/riscv/b-ext-64.s: Removed.
* testsuite/gas/riscv/b-ext-64.d: Removed.
* testsuite/gas/riscv/b-ext-na.d: Removed.
* testsuite/gas/riscv/b-ext-64-na.d: Removed.
---
gas/testsuite/gas/riscv/b-ext-64.d | 72 ----------------
gas/testsuite/gas/riscv/b-ext-64.s | 64 --------------
gas/testsuite/gas/riscv/b-ext.d | 51 -----------
gas/testsuite/gas/riscv/b-ext.s | 43 ----------
.../riscv/{b-ext-na.d => zb-ext-32-noalias.d} | 38 ++++-----
gas/testsuite/gas/riscv/zb-ext-32-noarch.d | 3 +
gas/testsuite/gas/riscv/zb-ext-32-noarch.l | 60 +++++++++++++
gas/testsuite/gas/riscv/zb-ext-32.d | 51 +++++++++++
.../{b-ext-64-na.d => zb-ext-64-noalias.d} | 72 ++++++++--------
gas/testsuite/gas/riscv/zb-ext-64-noarch.d | 3 +
gas/testsuite/gas/riscv/zb-ext-64-noarch.l | 59 +++++++++++++
gas/testsuite/gas/riscv/zb-ext-64.d | 72 ++++++++++++++++
gas/testsuite/gas/riscv/zb-ext.s | 84 +++++++++++++++++++
13 files changed, 387 insertions(+), 285 deletions(-)
delete mode 100644 gas/testsuite/gas/riscv/b-ext-64.d
delete mode 100644 gas/testsuite/gas/riscv/b-ext-64.s
delete mode 100644 gas/testsuite/gas/riscv/b-ext.d
delete mode 100644 gas/testsuite/gas/riscv/b-ext.s
rename gas/testsuite/gas/riscv/{b-ext-na.d => zb-ext-32-noalias.d} (67%)
create mode 100644 gas/testsuite/gas/riscv/zb-ext-32-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zb-ext-32-noarch.l
create mode 100644 gas/testsuite/gas/riscv/zb-ext-32.d
rename gas/testsuite/gas/riscv/{b-ext-64-na.d => zb-ext-64-noalias.d} (73%)
create mode 100644 gas/testsuite/gas/riscv/zb-ext-64-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zb-ext-64-noarch.l
create mode 100644 gas/testsuite/gas/riscv/zb-ext-64.d
create mode 100644 gas/testsuite/gas/riscv/zb-ext.s
diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
deleted file mode 100644
index f88fef9aeb2..00000000000
--- a/gas/testsuite/gas/riscv/b-ext-64.d
+++ /dev/null
@@ -1,72 +0,0 @@
-#as: -march=rv64i_zba_zbb_zbc_zbs
-#source: b-ext-64.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+60051513[ ]+clz[ ]+a0,a0
-[ ]+4:[ ]+60151513[ ]+ctz[ ]+a0,a0
-[ ]+8:[ ]+60251513[ ]+cpop[ ]+a0,a0
-[ ]+c:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
-[ ]+10:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
-[ ]+14:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
-[ ]+18:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
-[ ]+1c:[ ]+60451513[ ]+sext.b[ ]+a0,a0
-[ ]+20:[ ]+60551513[ ]+sext.h[ ]+a0,a0
-[ ]+24:[ ]+0805453b[ ]+zext.h[ ]+a0,a0
-[ ]+28:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
-[ ]+2c:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
-[ ]+30:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
-[ ]+34:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
-[ ]+38:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
-[ ]+3c:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
-[ ]+40:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
-[ ]+44:[ ]+6b855513[ ]+rev8[ ]+a0,a0
-[ ]+48:[ ]+28755513[ ]+orc.b[ ]+a0,a0
-[ ]+4c:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
-[ ]+50:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
-[ ]+54:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
-[ ]+58:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
-[ ]+5c:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
-[ ]+60:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
-[ ]+64:[ ]+6005151b[ ]+clzw[ ]+a0,a0
-[ ]+68:[ ]+6015151b[ ]+ctzw[ ]+a0,a0
-[ ]+6c:[ ]+6025151b[ ]+cpopw[ ]+a0,a0
-[ ]+70:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
-[ ]+74:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
-[ ]+78:[ ]+6025d51b[ ]+rorw[ ]+a0,a1,0x2
-[ ]+7c:[ ]+6025d51b[ ]+rorw[ ]+a0,a1,0x2
-[ ]+80:[ ]+20c5a53b[ ]+sh1add.uw[ ]+a0,a1,a2
-[ ]+84:[ ]+20c5c53b[ ]+sh2add.uw[ ]+a0,a1,a2
-[ ]+88:[ ]+20c5e53b[ ]+sh3add.uw[ ]+a0,a1,a2
-[ ]+8c:[ ]+08c5853b[ ]+add.uw[ ]+a0,a1,a2
-[ ]+90:[ ]+0805853b[ ]+zext.w[ ]+a0,a1
-[ ]+94:[ ]+0825951b[ ]+slli.uw[ ]+a0,a1,0x2
-[ ]+[0-9a-f]+:[ ]+48059513[ ]+bclr[ ]+a0,a1,0x0
-[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclr[ ]+a0,a1,0x1f
-[ ]+[0-9a-f]+:[ ]+28059513[ ]+bset[ ]+a0,a1,0x0
-[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bset[ ]+a0,a1,0x1f
-[ ]+[0-9a-f]+:[ ]+68059513[ ]+binv[ ]+a0,a1,0x0
-[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binv[ ]+a0,a1,0x1f
-[ ]+[0-9a-f]+:[ ]+4805d513[ ]+bext[ ]+a0,a1,0x0
-[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bext[ ]+a0,a1,0x1f
-[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclr[ ]+a0,a1,0x3f
-[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bset[ ]+a0,a1,0x3f
-[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binv[ ]+a0,a1,0x3f
-[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bext[ ]+a0,a1,0x3f
-[ ]+[0-9a-f]+:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclr[ ]+a0,a1,0x1f
-[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bset[ ]+a0,a1,0x1f
-[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binv[ ]+a0,a1,0x1f
-[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bext[ ]+a0,a1,0x1f
-[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclr[ ]+a0,a1,0x3f
-[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bset[ ]+a0,a1,0x3f
-[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binv[ ]+a0,a1,0x3f
-[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bext[ ]+a0,a1,0x3f
diff --git a/gas/testsuite/gas/riscv/b-ext-64.s b/gas/testsuite/gas/riscv/b-ext-64.s
deleted file mode 100644
index 57e501e9a41..00000000000
--- a/gas/testsuite/gas/riscv/b-ext-64.s
+++ /dev/null
@@ -1,64 +0,0 @@
-target:
- clz a0, a0
- ctz a0, a0
- cpop a0, a0
- min a0, a1, a2
- minu a0, a1, a2
- max a0, a1, a2
- maxu a0, a1, a2
- sext.b a0, a0
- sext.h a0, a0
- zext.h a0, a0
- andn a0, a1, a2
- orn a0, a1, a2
- xnor a0, a1, a2
- rol a0, a1, a2
- ror a0, a1, a2
- ror a0, a1, 2
- rori a0, a1, 2
- rev8 a0, a0
- orc.b a0, a0
- sh1add a0, a1, a2
- sh2add a0, a1, a2
- sh3add a0, a1, a2
- clmul a0, a1, a2
- clmulh a0, a1, a2
- clmulr a0, a1, a2
- clzw a0, a0
- ctzw a0, a0
- cpopw a0, a0
- rolw a0, a1, a2
- rorw a0, a1, a2
- rorw a0, a1, 2
- roriw a0, a1, 2
- sh1add.uw a0, a1, a2
- sh2add.uw a0, a1, a2
- sh3add.uw a0, a1, a2
- add.uw a0, a1, a2
- zext.w a0, a1
- slli.uw a0, a1, 2
- bclri a0, a1, 0
- bclri a0, a1, 31
- bseti a0, a1, 0
- bseti a0, a1, 31
- binvi a0, a1, 0
- binvi a0, a1, 31
- bexti a0, a1, 0
- bexti a0, a1, 31
- bclri a0, a1, 63
- bseti a0, a1, 63
- binvi a0, a1, 63
- bexti a0, a1, 63
- bclr a0, a1, a2
- bset a0, a1, a2
- binv a0, a1, a2
- bext a0, a1, a2
- #aliases
- bclr a0, a1, 31
- bset a0, a1, 31
- binv a0, a1, 31
- bext a0, a1, 31
- bclr a0, a1, 63
- bset a0, a1, 63
- binv a0, a1, 63
- bext a0, a1, 63
diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d
deleted file mode 100644
index 6bbbeb0f96b..00000000000
--- a/gas/testsuite/gas/riscv/b-ext.d
+++ /dev/null
@@ -1,51 +0,0 @@
-#as: -march=rv32i_zba_zbb_zbc_zbs
-#source: b-ext.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+60051513[ ]+clz[ ]+a0,a0
-[ ]+4:[ ]+60151513[ ]+ctz[ ]+a0,a0
-[ ]+8:[ ]+60251513[ ]+cpop[ ]+a0,a0
-[ ]+c:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
-[ ]+10:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
-[ ]+14:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
-[ ]+18:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
-[ ]+1c:[ ]+60451513[ ]+sext.b[ ]+a0,a0
-[ ]+20:[ ]+60551513[ ]+sext.h[ ]+a0,a0
-[ ]+24:[ ]+08054533[ ]+zext.h[ ]+a0,a0
-[ ]+28:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
-[ ]+2c:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
-[ ]+30:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
-[ ]+34:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
-[ ]+38:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
-[ ]+3c:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
-[ ]+40:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
-[ ]+44:[ ]+69855513[ ]+rev8[ ]+a0,a0
-[ ]+48:[ ]+28755513[ ]+orc.b[ ]+a0,a0
-[ ]+4c:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
-[ ]+50:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
-[ ]+54:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
-[ ]+58:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
-[ ]+5c:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
-[ ]+60:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+48059513[ ]+bclr[ ]+a0,a1,0x0
-[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclr[ ]+a0,a1,0x1f
-[ ]+[0-9a-f]+:[ ]+28059513[ ]+bset[ ]+a0,a1,0x0
-[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bset[ ]+a0,a1,0x1f
-[ ]+[0-9a-f]+:[ ]+68059513[ ]+binv[ ]+a0,a1,0x0
-[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binv[ ]+a0,a1,0x1f
-[ ]+[0-9a-f]+:[ ]+4805d513[ ]+bext[ ]+a0,a1,0x0
-[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bext[ ]+a0,a1,0x1f
-[ ]+[0-9a-f]+:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclr[ ]+a0,a1,0x1f
-[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bset[ ]+a0,a1,0x1f
-[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binv[ ]+a0,a1,0x1f
-[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bext[ ]+a0,a1,0x1f
diff --git a/gas/testsuite/gas/riscv/b-ext.s b/gas/testsuite/gas/riscv/b-ext.s
deleted file mode 100644
index 9de3fc32806..00000000000
--- a/gas/testsuite/gas/riscv/b-ext.s
+++ /dev/null
@@ -1,43 +0,0 @@
-target:
- clz a0, a0
- ctz a0, a0
- cpop a0, a0
- min a0, a1, a2
- minu a0, a1, a2
- max a0, a1, a2
- maxu a0, a1, a2
- sext.b a0, a0
- sext.h a0, a0
- zext.h a0, a0
- andn a0, a1, a2
- orn a0, a1, a2
- xnor a0, a1, a2
- rol a0, a1, a2
- ror a0, a1, a2
- ror a0, a1, 2
- rori a0, a1, 2
- rev8 a0, a0
- orc.b a0, a0
- sh1add a0, a1, a2
- sh2add a0, a1, a2
- sh3add a0, a1, a2
- clmul a0, a1, a2
- clmulh a0, a1, a2
- clmulr a0, a1, a2
- bclri a0, a1, 0
- bclri a0, a1, 31
- bseti a0, a1, 0
- bseti a0, a1, 31
- binvi a0, a1, 0
- binvi a0, a1, 31
- bexti a0, a1, 0
- bexti a0, a1, 31
- bclr a0, a1, a2
- bset a0, a1, a2
- binv a0, a1, a2
- bext a0, a1, a2
- #aliases
- bclr a0, a1, 31
- bset a0, a1, 31
- binv a0, a1, 31
- bext a0, a1, 31
diff --git a/gas/testsuite/gas/riscv/b-ext-na.d b/gas/testsuite/gas/riscv/zb-ext-32-noalias.d
similarity index 67%
rename from gas/testsuite/gas/riscv/b-ext-na.d
rename to gas/testsuite/gas/riscv/zb-ext-32-noalias.d
index 0c80a379fae..2d532321910 100644
--- a/gas/testsuite/gas/riscv/b-ext-na.d
+++ b/gas/testsuite/gas/riscv/zb-ext-32-noalias.d
@@ -1,6 +1,6 @@
-#as: -march=rv32i_zba_zbb_zbc_zbs
-#source: b-ext.s
-#objdump: -d -Mno-aliases
+#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32
+#source: zb-ext.s
+#objdump: -d -M no-aliases
.*:[ ]+file format .*
@@ -8,28 +8,28 @@
Disassembly of section .text:
0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+60051513[ ]+clz[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+60151513[ ]+ctz[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+60251513[ ]+cpop[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60059513[ ]+clz[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60159513[ ]+ctz[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60259513[ ]+cpop[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+60451513[ ]+sext\.b[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+60551513[ ]+sext\.h[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+08054533[ ]+zext\.h[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+60459513[ ]+sext\.b[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60559513[ ]+sext\.h[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+0805c533[ ]+zext\.h[ ]+a0,a1
[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+6985d513[ ]+rev8[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+2875d513[ ]+orc\.b[ ]+a0,a1
[ ]+[0-9a-f]+:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
-[ ]+[0-9a-f]+:[ ]+69855513[ ]+rev8[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+28755513[ ]+orc\.b[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zb-ext-32-noarch.d b/gas/testsuite/gas/riscv/zb-ext-32-noarch.d
new file mode 100644
index 00000000000..e9a2c0dda07
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zb-ext-32-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32 -defsym NOARCH=1
+#source: zb-ext.s
+#error_output: zb-ext-32-noarch.l
diff --git a/gas/testsuite/gas/riscv/zb-ext-32-noarch.l b/gas/testsuite/gas/riscv/zb-ext-32-noarch.l
new file mode 100644
index 00000000000..16859b86ad9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zb-ext-32-noarch.l
@@ -0,0 +1,60 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `sh1add a0,a1,a2', extension `zba' required
+.*: Error: unrecognized opcode `sh2add a0,a1,a2', extension `zba' required
+.*: Error: unrecognized opcode `sh3add a0,a1,a2', extension `zba' required
+.*: Error: unrecognized opcode `sh1add\.uw a0,a1,a2'
+.*: Error: unrecognized opcode `sh2add\.uw a0,a1,a2'
+.*: Error: unrecognized opcode `sh3add\.uw a0,a1,a2'
+.*: Error: unrecognized opcode `add\.uw a0,a1,a2'
+.*: Error: unrecognized opcode `slli\.uw a0,a1,2'
+.*: Error: unrecognized opcode `zext\.w a0,a1'
+.*: Error: unrecognized opcode `clz a0,a1', extension `zbb' required
+.*: Error: unrecognized opcode `ctz a0,a1', extension `zbb' required
+.*: Error: unrecognized opcode `cpop a0,a1', extension `zbb' required
+.*: Error: unrecognized opcode `min a0,a1,a2', extension `zbb' required
+.*: Error: unrecognized opcode `minu a0,a1,a2', extension `zbb' required
+.*: Error: unrecognized opcode `max a0,a1,a2', extension `zbb' required
+.*: Error: unrecognized opcode `maxu a0,a1,a2', extension `zbb' required
+.*: Error: unrecognized opcode `andn a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `orn a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `xnor a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `rol a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `ror a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `rori a0,a1,2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `rev8 a0,a1', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `orc\.b a0,a1', extension `zbb' required
+.*: Error: unrecognized opcode `clzw a0,a1'
+.*: Error: unrecognized opcode `ctzw a0,a1'
+.*: Error: unrecognized opcode `cpopw a0,a1'
+.*: Error: unrecognized opcode `rolw a0,a1,a2'
+.*: Error: unrecognized opcode `rorw a0,a1,a2'
+.*: Error: unrecognized opcode `roriw a0,a1,2'
+.*: Error: unrecognized opcode `ror a0,a1,2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `rorw a0,a1,2'
+.*: Error: unrecognized opcode `clmul a0,a1,a2', extension `zbc' or `zbkc' required
+.*: Error: unrecognized opcode `clmulh a0,a1,a2', extension `zbc' or `zbkc' required
+.*: Error: unrecognized opcode `clmulr a0,a1,a2', extension `zbc' required
+.*: Error: unrecognized opcode `bclri a0,a1,0', extension `zbs' required
+.*: Error: unrecognized opcode `bclri a0,a1,31', extension `zbs' required
+.*: Error: unrecognized opcode `bseti a0,a1,0', extension `zbs' required
+.*: Error: unrecognized opcode `bseti a0,a1,31', extension `zbs' required
+.*: Error: unrecognized opcode `binvi a0,a1,0', extension `zbs' required
+.*: Error: unrecognized opcode `binvi a0,a1,31', extension `zbs' required
+.*: Error: unrecognized opcode `bexti a0,a1,0', extension `zbs' required
+.*: Error: unrecognized opcode `bexti a0,a1,31', extension `zbs' required
+.*: Error: unrecognized opcode `bclr a0,a1,a2', extension `zbs' required
+.*: Error: unrecognized opcode `bset a0,a1,a2', extension `zbs' required
+.*: Error: unrecognized opcode `binv a0,a1,a2', extension `zbs' required
+.*: Error: unrecognized opcode `bext a0,a1,a2', extension `zbs' required
+.*: Error: unrecognized opcode `bclr a0,a1,31', extension `zbs' required
+.*: Error: unrecognized opcode `bset a0,a1,31', extension `zbs' required
+.*: Error: unrecognized opcode `binv a0,a1,31', extension `zbs' required
+.*: Error: unrecognized opcode `bext a0,a1,31', extension `zbs' required
+.*: Error: unrecognized opcode `bclri a0,a1,63', extension `zbs' required
+.*: Error: unrecognized opcode `bseti a0,a1,63', extension `zbs' required
+.*: Error: unrecognized opcode `binvi a0,a1,63', extension `zbs' required
+.*: Error: unrecognized opcode `bexti a0,a1,63', extension `zbs' required
+.*: Error: unrecognized opcode `bclr a0,a1,63', extension `zbs' required
+.*: Error: unrecognized opcode `bset a0,a1,63', extension `zbs' required
+.*: Error: unrecognized opcode `binv a0,a1,63', extension `zbs' required
+.*: Error: unrecognized opcode `bext a0,a1,63', extension `zbs' required
diff --git a/gas/testsuite/gas/riscv/zb-ext-32.d b/gas/testsuite/gas/riscv/zb-ext-32.d
new file mode 100644
index 00000000000..419f36a0745
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zb-ext-32.d
@@ -0,0 +1,51 @@
+#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32
+#source: zb-ext.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60059513[ ]+clz[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60159513[ ]+ctz[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60259513[ ]+cpop[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60459513[ ]+sext\.b[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60559513[ ]+sext\.h[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+0805c533[ ]+zext\.h[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+6985d513[ ]+rev8[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+2875d513[ ]+orc\.b[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+48059513[ ]+bclr[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclr[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+28059513[ ]+bset[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bset[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+68059513[ ]+binv[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binv[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+4805d513[ ]+bext[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bext[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclr[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bset[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binv[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bext[ ]+a0,a1,0x1f
diff --git a/gas/testsuite/gas/riscv/b-ext-64-na.d b/gas/testsuite/gas/riscv/zb-ext-64-noalias.d
similarity index 73%
rename from gas/testsuite/gas/riscv/b-ext-64-na.d
rename to gas/testsuite/gas/riscv/zb-ext-64-noalias.d
index ec5acd017ed..341eb22eb1b 100644
--- a/gas/testsuite/gas/riscv/b-ext-64-na.d
+++ b/gas/testsuite/gas/riscv/zb-ext-64-noalias.d
@@ -1,6 +1,6 @@
-#as: -march=rv64i_zba_zbb_zbc_zbs
-#source: b-ext-64.s
-#objdump: -d -Mno-aliases
+#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64
+#source: zb-ext.s
+#objdump: -d -M no-aliases
.*:[ ]+file format .*
@@ -8,44 +8,44 @@
Disassembly of section .text:
0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+60051513[ ]+clz[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+60151513[ ]+ctz[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+60251513[ ]+cpop[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5a53b[ ]+sh1add\.uw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5c53b[ ]+sh2add\.uw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5e53b[ ]+sh3add\.uw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+08c5853b[ ]+add\.uw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0825951b[ ]+slli\.uw[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+0805853b[ ]+add\.uw[ ]+a0,a1,zero
+[ ]+[0-9a-f]+:[ ]+60059513[ ]+clz[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60159513[ ]+ctz[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60259513[ ]+cpop[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+60451513[ ]+sext\.b[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+60551513[ ]+sext\.h[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+0805453b[ ]+zext\.h[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+60459513[ ]+sext\.b[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60559513[ ]+sext\.h[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+0805c53b[ ]+zext\.h[ ]+a0,a1
[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
-[ ]+[0-9a-f]+:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
-[ ]+[0-9a-f]+:[ ]+6b855513[ ]+rev8[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+28755513[ ]+orc\.b[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+6005151b[ ]+clzw[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+6015151b[ ]+ctzw[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+6025151b[ ]+cpopw[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+6b85d513[ ]+rev8[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+2875d513[ ]+orc\.b[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+6005951b[ ]+clzw[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+6015951b[ ]+ctzw[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+6025951b[ ]+cpopw[ ]+a0,a1
[ ]+[0-9a-f]+:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+6025d51b[ ]+roriw[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
[ ]+[0-9a-f]+:[ ]+6025d51b[ ]+roriw[ ]+a0,a1,0x2
-[ ]+[0-9a-f]+:[ ]+20c5a53b[ ]+sh1add\.uw[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+20c5c53b[ ]+sh2add\.uw[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+20c5e53b[ ]+sh3add\.uw[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+08c5853b[ ]+add\.uw[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+0805853b[ ]+add\.uw[ ]+a0,a1,zero
-[ ]+[0-9a-f]+:[ ]+0825951b[ ]+slli\.uw[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+48059513[ ]+bclri[ ]+a0,a1,0x0
[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclri[ ]+a0,a1,0x1f
[ ]+[0-9a-f]+:[ ]+28059513[ ]+bseti[ ]+a0,a1,0x0
@@ -54,10 +54,6 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binvi[ ]+a0,a1,0x1f
[ ]+[0-9a-f]+:[ ]+4805d513[ ]+bexti[ ]+a0,a1,0x0
[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bexti[ ]+a0,a1,0x1f
-[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclri[ ]+a0,a1,0x3f
-[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bseti[ ]+a0,a1,0x3f
-[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binvi[ ]+a0,a1,0x3f
-[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bexti[ ]+a0,a1,0x3f
[ ]+[0-9a-f]+:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
@@ -70,3 +66,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bseti[ ]+a0,a1,0x3f
[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binvi[ ]+a0,a1,0x3f
[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bexti[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclri[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bseti[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binvi[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bexti[ ]+a0,a1,0x3f
diff --git a/gas/testsuite/gas/riscv/zb-ext-64-noarch.d b/gas/testsuite/gas/riscv/zb-ext-64-noarch.d
new file mode 100644
index 00000000000..3655678814f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zb-ext-64-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64 -defsym NOARCH=1
+#source: zb-ext.s
+#error_output: zb-ext-64-noarch.l
diff --git a/gas/testsuite/gas/riscv/zb-ext-64-noarch.l b/gas/testsuite/gas/riscv/zb-ext-64-noarch.l
new file mode 100644
index 00000000000..9b358fb3b55
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zb-ext-64-noarch.l
@@ -0,0 +1,59 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `sh1add a0,a1,a2', extension `zba' required
+.*: Error: unrecognized opcode `sh2add a0,a1,a2', extension `zba' required
+.*: Error: unrecognized opcode `sh3add a0,a1,a2', extension `zba' required
+.*: Error: unrecognized opcode `sh1add\.uw a0,a1,a2', extension `zba' required
+.*: Error: unrecognized opcode `sh2add\.uw a0,a1,a2', extension `zba' required
+.*: Error: unrecognized opcode `sh3add\.uw a0,a1,a2', extension `zba' required
+.*: Error: unrecognized opcode `add\.uw a0,a1,a2', extension `zba' required
+.*: Error: unrecognized opcode `slli\.uw a0,a1,2', extension `zba' required
+.*: Error: unrecognized opcode `clz a0,a1', extension `zbb' required
+.*: Error: unrecognized opcode `ctz a0,a1', extension `zbb' required
+.*: Error: unrecognized opcode `cpop a0,a1', extension `zbb' required
+.*: Error: unrecognized opcode `min a0,a1,a2', extension `zbb' required
+.*: Error: unrecognized opcode `minu a0,a1,a2', extension `zbb' required
+.*: Error: unrecognized opcode `max a0,a1,a2', extension `zbb' required
+.*: Error: unrecognized opcode `maxu a0,a1,a2', extension `zbb' required
+.*: Error: unrecognized opcode `andn a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `orn a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `xnor a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `rol a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `ror a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `rori a0,a1,2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `rev8 a0,a1', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `orc\.b a0,a1', extension `zbb' required
+.*: Error: unrecognized opcode `clzw a0,a1', extension `zbb' required
+.*: Error: unrecognized opcode `ctzw a0,a1', extension `zbb' required
+.*: Error: unrecognized opcode `cpopw a0,a1', extension `zbb' required
+.*: Error: unrecognized opcode `rolw a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `rorw a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `roriw a0,a1,2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `ror a0,a1,2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `rorw a0,a1,2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `clmul a0,a1,a2', extension `zbc' or `zbkc' required
+.*: Error: unrecognized opcode `clmulh a0,a1,a2', extension `zbc' or `zbkc' required
+.*: Error: unrecognized opcode `clmulr a0,a1,a2', extension `zbc' required
+.*: Error: unrecognized opcode `bclri a0,a1,0', extension `zbs' required
+.*: Error: unrecognized opcode `bclri a0,a1,31', extension `zbs' required
+.*: Error: unrecognized opcode `bseti a0,a1,0', extension `zbs' required
+.*: Error: unrecognized opcode `bseti a0,a1,31', extension `zbs' required
+.*: Error: unrecognized opcode `binvi a0,a1,0', extension `zbs' required
+.*: Error: unrecognized opcode `binvi a0,a1,31', extension `zbs' required
+.*: Error: unrecognized opcode `bexti a0,a1,0', extension `zbs' required
+.*: Error: unrecognized opcode `bexti a0,a1,31', extension `zbs' required
+.*: Error: unrecognized opcode `bclr a0,a1,a2', extension `zbs' required
+.*: Error: unrecognized opcode `bset a0,a1,a2', extension `zbs' required
+.*: Error: unrecognized opcode `binv a0,a1,a2', extension `zbs' required
+.*: Error: unrecognized opcode `bext a0,a1,a2', extension `zbs' required
+.*: Error: unrecognized opcode `bclr a0,a1,31', extension `zbs' required
+.*: Error: unrecognized opcode `bset a0,a1,31', extension `zbs' required
+.*: Error: unrecognized opcode `binv a0,a1,31', extension `zbs' required
+.*: Error: unrecognized opcode `bext a0,a1,31', extension `zbs' required
+.*: Error: unrecognized opcode `bclri a0,a1,63', extension `zbs' required
+.*: Error: unrecognized opcode `bseti a0,a1,63', extension `zbs' required
+.*: Error: unrecognized opcode `binvi a0,a1,63', extension `zbs' required
+.*: Error: unrecognized opcode `bexti a0,a1,63', extension `zbs' required
+.*: Error: unrecognized opcode `bclr a0,a1,63', extension `zbs' required
+.*: Error: unrecognized opcode `bset a0,a1,63', extension `zbs' required
+.*: Error: unrecognized opcode `binv a0,a1,63', extension `zbs' required
+.*: Error: unrecognized opcode `bext a0,a1,63', extension `zbs' required
diff --git a/gas/testsuite/gas/riscv/zb-ext-64.d b/gas/testsuite/gas/riscv/zb-ext-64.d
new file mode 100644
index 00000000000..df206c0f298
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zb-ext-64.d
@@ -0,0 +1,72 @@
+#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64
+#source: zb-ext.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5a53b[ ]+sh1add\.uw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5c53b[ ]+sh2add\.uw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5e53b[ ]+sh3add\.uw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+08c5853b[ ]+add\.uw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0825951b[ ]+slli\.uw[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+0805853b[ ]+zext\.w[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60059513[ ]+clz[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60159513[ ]+ctz[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60259513[ ]+cpop[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60459513[ ]+sext\.b[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60559513[ ]+sext\.h[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+0805c53b[ ]+zext\.h[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+6b85d513[ ]+rev8[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+2875d513[ ]+orc\.b[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+6005951b[ ]+clzw[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+6015951b[ ]+ctzw[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+6025951b[ ]+cpopw[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6025d51b[ ]+rorw[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+6025d51b[ ]+rorw[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+48059513[ ]+bclr[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclr[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+28059513[ ]+bset[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bset[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+68059513[ ]+binv[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binv[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+4805d513[ ]+bext[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bext[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclr[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bset[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binv[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bext[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclr[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bset[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binv[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bext[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclr[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bset[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binv[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bext[ ]+a0,a1,0x3f
diff --git a/gas/testsuite/gas/riscv/zb-ext.s b/gas/testsuite/gas/riscv/zb-ext.s
new file mode 100644
index 00000000000..2489fcd47c2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zb-ext.s
@@ -0,0 +1,84 @@
+.include "testutils.inc"
+
+target:
+ SET_ARCH_START +zba
+ sh1add a0, a1, a2
+ sh2add a0, a1, a2
+ sh3add a0, a1, a2
+.if XLEN_GE_64
+ sh1add.uw a0, a1, a2
+ sh2add.uw a0, a1, a2
+ sh3add.uw a0, a1, a2
+ add.uw a0, a1, a2
+ slli.uw a0, a1, 2
+ zext.w a0, a1 # Alias (has RVI macro)
+.endif
+ SET_ARCH_END
+
+ SET_ARCH_START +zbb
+ clz a0, a1
+ ctz a0, a1
+ cpop a0, a1
+ min a0, a1, a2
+ minu a0, a1, a2
+ max a0, a1, a2
+ maxu a0, a1, a2
+ sext.b a0, a1 # Has RVI macro
+ sext.h a0, a1 # Has RVI macro
+ zext.h a0, a1 # Has RVI macro
+ andn a0, a1, a2
+ orn a0, a1, a2
+ xnor a0, a1, a2
+ rol a0, a1, a2
+ ror a0, a1, a2
+ rori a0, a1, 2
+ rev8 a0, a1
+ orc.b a0, a1
+.if XLEN_GE_64
+ clzw a0, a1
+ ctzw a0, a1
+ cpopw a0, a1
+ rolw a0, a1, a2
+ rorw a0, a1, a2
+ roriw a0, a1, 2
+.endif
+ ror a0, a1, 2 # Alias
+.if XLEN_GE_64
+ rorw a0, a1, 2 # Alias
+.endif
+ SET_ARCH_END
+
+ SET_ARCH_START +zbc
+ clmul a0, a1, a2
+ clmulh a0, a1, a2
+ clmulr a0, a1, a2
+ SET_ARCH_END
+
+ SET_ARCH_START +zbs
+ bclri a0, a1, 0
+ bclri a0, a1, 31
+ bseti a0, a1, 0
+ bseti a0, a1, 31
+ binvi a0, a1, 0
+ binvi a0, a1, 31
+ bexti a0, a1, 0
+ bexti a0, a1, 31
+ bclr a0, a1, a2
+ bset a0, a1, a2
+ binv a0, a1, a2
+ bext a0, a1, a2
+ bclr a0, a1, 31 # Alias
+ bset a0, a1, 31 # Alias
+ binv a0, a1, 31 # Alias
+ bext a0, a1, 31 # Alias
+.if XLEN_GE_64
+ bclri a0, a1, 63
+ bseti a0, a1, 63
+ binvi a0, a1, 63
+ bexti a0, a1, 63
+ bclr a0, a1, 63 # Alias
+ bset a0, a1, 63 # Alias
+ binv a0, a1, 63 # Alias
+ bext a0, a1, 63 # Alias
+.endif
+ SET_ARCH_END
--
2.37.2
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 12/12] RISC-V: Combine/enhance 'Zk*'/'Zbk*' extension tests
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
` (10 preceding siblings ...)
2022-11-05 12:29 ` [PATCH 11/12] RISC-V: Reorganize/enhance 'Zb*' extension tests Tsukasa OI
@ 2022-11-05 12:29 ` Tsukasa OI
2022-11-29 9:00 ` Nelson Chu
2022-11-20 2:28 ` [PING^1][PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
12 siblings, 1 reply; 26+ messages in thread
From: Tsukasa OI @ 2022-11-05 12:29 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
This commit combines tests for 'Zk*' and 'Zbk*' extensions and adds
"no required extension" testcases based on new test utilities. It also
contains minor tidying (such as using different registers per operand).
gas/ChangeLog:
* testsuite/gas/riscv/zbk-ext.s: Combine zbkb-{32,64}.s, zbkc.s
and zbkx.s. Use different register per operand.
* testsuite/gas/riscv/zbk-ext-32.d: Combine zbk[bcx]-32.d.
Reflect zbk-ext.s changes.
* testsuite/gas/riscv/zbk-ext-64.d: Combine zbk[bcx]-64.d.
Reflect zbk-ext.s changes.
* testsuite/gas/riscv/zbk-ext-32-noalias.d: New test based on the
concept of zbkb-32-na.d and the code based on zbk-ext-32.d.
* testsuite/gas/riscv/zbk-ext-64-noalias.d: Likewise but new.
* testsuite/gas/riscv/zbk-ext-32-noarch.d: New test.
* testsuite/gas/riscv/zbk-ext-32-noarch.l: Likewise.
* testsuite/gas/riscv/zbk-ext-64-noarch.d: New test.
* testsuite/gas/riscv/zbk-ext-64-noarch.l: Likewise.
* testsuite/gas/riscv/zk-ext-32.s: Combine zkn*-32.s, zksed.s
and zksh.s. Use different register per operand.
* testsuite/gas/riscv/zk-ext-32.d: Combine zk[ns]*-32.d.
Reflect zk-ext-32.s changes.
* testsuite/gas/riscv/zk-ext-64.s: Combine zkn*-64.s, zksed.s
and zksh.s. Use different register per operand.
* testsuite/gas/riscv/zk-ext-64.d: Combine zk[ns]*-64.d.
Reflect zk-ext-64.s changes.
* testsuite/gas/riscv/zk-ext-32-noarch.d: New test.
* testsuite/gas/riscv/zk-ext-32-noarch.l: Likewise.
* testsuite/gas/riscv/zk-ext-64-noarch.d: New test.
* testsuite/gas/riscv/zk-ext-64-noarch.l: Likewise.
* testsuite/gas/riscv/zkt.d: Separate test for the 'Zkt' extension
whether this extension is supported through -march.
* testsuite/gas/riscv/k-ext.s: Removed as duplicate.
* testsuite/gas/riscv/k-ext.d: Removed as duplicate.
* testsuite/gas/riscv/k-ext-64.s: Removed as duplicate.
* testsuite/gas/riscv/k-ext-64.d: Removed as duplicate.
* testsuite/gas/riscv/zbkb-32.s: Removed.
* testsuite/gas/riscv/zbkb-32.d: Removed.
* testsuite/gas/riscv/zbkb-32-na.d: Removed.
* testsuite/gas/riscv/zbkb-64.s: Removed.
* testsuite/gas/riscv/zbkb-64.d: Removed.
* testsuite/gas/riscv/zbkc.s: Removed.
* testsuite/gas/riscv/zbkc-32.d: Removed.
* testsuite/gas/riscv/zbkc-64.d: Removed.
* testsuite/gas/riscv/zbkx.s: Removed.
* testsuite/gas/riscv/zbkx-32.d: Removed.
* testsuite/gas/riscv/zbkx-64.d: Removed.
* testsuite/gas/riscv/zknd-32.s: Removed.
* testsuite/gas/riscv/zknd-32.d: Removed.
* testsuite/gas/riscv/zknd-64.s: Removed.
* testsuite/gas/riscv/zknd-64.d: Removed.
* testsuite/gas/riscv/zkne-32.s: Removed.
* testsuite/gas/riscv/zkne-32.d: Removed.
* testsuite/gas/riscv/zkne-64.s: Removed.
* testsuite/gas/riscv/zkne-64.d: Removed.
* testsuite/gas/riscv/zknh-32.s: Removed.
* testsuite/gas/riscv/zknh-32.d: Removed.
* testsuite/gas/riscv/zknh-64.s: Removed.
* testsuite/gas/riscv/zknh-64.d: Removed.
* testsuite/gas/riscv/zksed.s: Removed.
* testsuite/gas/riscv/zksed-32.d: Removed.
* testsuite/gas/riscv/zksed-64.d: Removed.
* testsuite/gas/riscv/zksh.s: Removed.
* testsuite/gas/riscv/zksh-32.d: Removed.
* testsuite/gas/riscv/zksh-64.d: Removed.
---
gas/testsuite/gas/riscv/k-ext-64.d | 47 --------------------
gas/testsuite/gas/riscv/k-ext-64.s | 38 ----------------
gas/testsuite/gas/riscv/k-ext.d | 44 ------------------
gas/testsuite/gas/riscv/k-ext.s | 35 ---------------
gas/testsuite/gas/riscv/zbk-ext-32-noalias.d | 26 +++++++++++
gas/testsuite/gas/riscv/zbk-ext-32-noarch.d | 3 ++
gas/testsuite/gas/riscv/zbk-ext-32-noarch.l | 21 +++++++++
gas/testsuite/gas/riscv/zbk-ext-32.d | 26 +++++++++++
gas/testsuite/gas/riscv/zbk-ext-64-noalias.d | 28 ++++++++++++
gas/testsuite/gas/riscv/zbk-ext-64-noarch.d | 3 ++
gas/testsuite/gas/riscv/zbk-ext-64-noarch.l | 21 +++++++++
gas/testsuite/gas/riscv/zbk-ext-64.d | 28 ++++++++++++
gas/testsuite/gas/riscv/zbk-ext.s | 37 +++++++++++++++
gas/testsuite/gas/riscv/zbkb-32-na.d | 23 ----------
gas/testsuite/gas/riscv/zbkb-32.d | 22 ---------
gas/testsuite/gas/riscv/zbkb-32.s | 13 ------
gas/testsuite/gas/riscv/zbkb-64.d | 24 ----------
gas/testsuite/gas/riscv/zbkb-64.s | 15 -------
gas/testsuite/gas/riscv/zbkc-32.d | 12 -----
gas/testsuite/gas/riscv/zbkc-64.d | 12 -----
gas/testsuite/gas/riscv/zbkc.s | 3 --
gas/testsuite/gas/riscv/zbkx-32.d | 12 -----
gas/testsuite/gas/riscv/zbkx-64.d | 12 -----
gas/testsuite/gas/riscv/zbkx.s | 3 --
gas/testsuite/gas/riscv/zk-ext-32-noarch.d | 3 ++
gas/testsuite/gas/riscv/zk-ext-32-noarch.l | 20 +++++++++
gas/testsuite/gas/riscv/zk-ext-32.d | 28 ++++++++++++
gas/testsuite/gas/riscv/zk-ext-32.s | 41 +++++++++++++++++
gas/testsuite/gas/riscv/zk-ext-64-noarch.d | 3 ++
gas/testsuite/gas/riscv/zk-ext-64-noarch.l | 23 ++++++++++
gas/testsuite/gas/riscv/zk-ext-64.d | 31 +++++++++++++
gas/testsuite/gas/riscv/zk-ext-64.s | 44 ++++++++++++++++++
gas/testsuite/gas/riscv/zknd-32.d | 12 -----
gas/testsuite/gas/riscv/zknd-32.s | 3 --
gas/testsuite/gas/riscv/zknd-64.d | 15 -------
gas/testsuite/gas/riscv/zknd-64.s | 6 ---
gas/testsuite/gas/riscv/zkne-32.d | 12 -----
gas/testsuite/gas/riscv/zkne-32.s | 3 --
gas/testsuite/gas/riscv/zkne-64.d | 14 ------
gas/testsuite/gas/riscv/zkne-64.s | 5 ---
gas/testsuite/gas/riscv/zknh-32.d | 20 ---------
gas/testsuite/gas/riscv/zknh-32.s | 11 -----
gas/testsuite/gas/riscv/zknh-64.d | 18 --------
gas/testsuite/gas/riscv/zknh-64.s | 9 ----
gas/testsuite/gas/riscv/zksed-32.d | 12 -----
gas/testsuite/gas/riscv/zksed-64.d | 12 -----
gas/testsuite/gas/riscv/zksed.s | 3 --
gas/testsuite/gas/riscv/zksh-32.d | 12 -----
gas/testsuite/gas/riscv/zksh-64.d | 12 -----
gas/testsuite/gas/riscv/zksh.s | 3 --
gas/testsuite/gas/riscv/zkt.d | 5 +++
51 files changed, 391 insertions(+), 497 deletions(-)
delete mode 100644 gas/testsuite/gas/riscv/k-ext-64.d
delete mode 100644 gas/testsuite/gas/riscv/k-ext-64.s
delete mode 100644 gas/testsuite/gas/riscv/k-ext.d
delete mode 100644 gas/testsuite/gas/riscv/k-ext.s
create mode 100644 gas/testsuite/gas/riscv/zbk-ext-32-noalias.d
create mode 100644 gas/testsuite/gas/riscv/zbk-ext-32-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zbk-ext-32-noarch.l
create mode 100644 gas/testsuite/gas/riscv/zbk-ext-32.d
create mode 100644 gas/testsuite/gas/riscv/zbk-ext-64-noalias.d
create mode 100644 gas/testsuite/gas/riscv/zbk-ext-64-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zbk-ext-64-noarch.l
create mode 100644 gas/testsuite/gas/riscv/zbk-ext-64.d
create mode 100644 gas/testsuite/gas/riscv/zbk-ext.s
delete mode 100644 gas/testsuite/gas/riscv/zbkb-32-na.d
delete mode 100644 gas/testsuite/gas/riscv/zbkb-32.d
delete mode 100644 gas/testsuite/gas/riscv/zbkb-32.s
delete mode 100644 gas/testsuite/gas/riscv/zbkb-64.d
delete mode 100644 gas/testsuite/gas/riscv/zbkb-64.s
delete mode 100644 gas/testsuite/gas/riscv/zbkc-32.d
delete mode 100644 gas/testsuite/gas/riscv/zbkc-64.d
delete mode 100644 gas/testsuite/gas/riscv/zbkc.s
delete mode 100644 gas/testsuite/gas/riscv/zbkx-32.d
delete mode 100644 gas/testsuite/gas/riscv/zbkx-64.d
delete mode 100644 gas/testsuite/gas/riscv/zbkx.s
create mode 100644 gas/testsuite/gas/riscv/zk-ext-32-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zk-ext-32-noarch.l
create mode 100644 gas/testsuite/gas/riscv/zk-ext-32.d
create mode 100644 gas/testsuite/gas/riscv/zk-ext-32.s
create mode 100644 gas/testsuite/gas/riscv/zk-ext-64-noarch.d
create mode 100644 gas/testsuite/gas/riscv/zk-ext-64-noarch.l
create mode 100644 gas/testsuite/gas/riscv/zk-ext-64.d
create mode 100644 gas/testsuite/gas/riscv/zk-ext-64.s
delete mode 100644 gas/testsuite/gas/riscv/zknd-32.d
delete mode 100644 gas/testsuite/gas/riscv/zknd-32.s
delete mode 100644 gas/testsuite/gas/riscv/zknd-64.d
delete mode 100644 gas/testsuite/gas/riscv/zknd-64.s
delete mode 100644 gas/testsuite/gas/riscv/zkne-32.d
delete mode 100644 gas/testsuite/gas/riscv/zkne-32.s
delete mode 100644 gas/testsuite/gas/riscv/zkne-64.d
delete mode 100644 gas/testsuite/gas/riscv/zkne-64.s
delete mode 100644 gas/testsuite/gas/riscv/zknh-32.d
delete mode 100644 gas/testsuite/gas/riscv/zknh-32.s
delete mode 100644 gas/testsuite/gas/riscv/zknh-64.d
delete mode 100644 gas/testsuite/gas/riscv/zknh-64.s
delete mode 100644 gas/testsuite/gas/riscv/zksed-32.d
delete mode 100644 gas/testsuite/gas/riscv/zksed-64.d
delete mode 100644 gas/testsuite/gas/riscv/zksed.s
delete mode 100644 gas/testsuite/gas/riscv/zksh-32.d
delete mode 100644 gas/testsuite/gas/riscv/zksh-64.d
delete mode 100644 gas/testsuite/gas/riscv/zksh.s
create mode 100644 gas/testsuite/gas/riscv/zkt.d
diff --git a/gas/testsuite/gas/riscv/k-ext-64.d b/gas/testsuite/gas/riscv/k-ext-64.d
deleted file mode 100644
index d56e0354a37..00000000000
--- a/gas/testsuite/gas/riscv/k-ext-64.d
+++ /dev/null
@@ -1,47 +0,0 @@
-#as: -march=rv64i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt
-#source: k-ext-64.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
-[ ]+[0-9a-f]+:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+6025d51b[ ]+rorw[ ]+a0,a1,0x2
-[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+08c5c53b[ ]+packw[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+68755513[ ]+brev8[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+6b855513[ ]+rev8[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+28c5a533[ ]+xperm4[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+28c5c533[ ]+xperm8[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+3ac58533[ ]+aes64ds[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+3ec58533[ ]+aes64dsm[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+30051513[ ]+aes64im[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+31459513[ ]+aes64ks1i[ ]+a0,a1,0x4
-[ ]+[0-9a-f]+:[ ]+7ec58533[ ]+aes64ks2[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+32c58533[ ]+aes64es[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+36c58533[ ]+aes64esm[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+10251513[ ]+sha256sig0[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10351513[ ]+sha256sig1[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10051513[ ]+sha256sum0[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10151513[ ]+sha256sum1[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10651513[ ]+sha512sig0[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10751513[ ]+sha512sig1[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10451513[ ]+sha512sum0[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10551513[ ]+sha512sum1[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+b0c58533[ ]+sm4ed[ ]+a0,a1,a2,0x2
-[ ]+[0-9a-f]+:[ ]+b4c58533[ ]+sm4ks[ ]+a0,a1,a2,0x2
-[ ]+[0-9a-f]+:[ ]+10851513[ ]+sm3p0[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10951513[ ]+sm3p1[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/k-ext-64.s b/gas/testsuite/gas/riscv/k-ext-64.s
deleted file mode 100644
index 302b82ea005..00000000000
--- a/gas/testsuite/gas/riscv/k-ext-64.s
+++ /dev/null
@@ -1,38 +0,0 @@
-target:
- ror a0, a1, a2
- rol a0, a1, a2
- rori a0, a1, 2
- rorw a0, a1, a2
- rolw a0, a1, a2
- roriw a0, a1, 2
- andn a0, a1, a2
- orn a0, a1, a2
- xnor a0, a1, a2
- pack a0, a1, a2
- packh a0, a1, a2
- packw a0, a1, a2
- brev8 a0, a0
- rev8 a0, a0
- clmul a0, a1, a2
- clmulh a0, a1, a2
- xperm4 a0, a1, a2
- xperm8 a0, a1, a2
- aes64ds a0, a1, a2
- aes64dsm a0, a1, a2
- aes64im a0, a0
- aes64ks1i a0, a1, 4
- aes64ks2 a0, a1, a2
- aes64es a0, a1, a2
- aes64esm a0, a1, a2
- sha256sig0 a0, a0
- sha256sig1 a0, a0
- sha256sum0 a0, a0
- sha256sum1 a0, a0
- sha512sig0 a0, a0
- sha512sig1 a0, a0
- sha512sum0 a0, a0
- sha512sum1 a0, a0
- sm4ed a0, a1, a2, 2
- sm4ks a0, a1, a2, 2
- sm3p0 a0, a0
- sm3p1 a0, a0
diff --git a/gas/testsuite/gas/riscv/k-ext.d b/gas/testsuite/gas/riscv/k-ext.d
deleted file mode 100644
index b00a1c959c2..00000000000
--- a/gas/testsuite/gas/riscv/k-ext.d
+++ /dev/null
@@ -1,44 +0,0 @@
-#as: -march=rv32i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt
-#source: k-ext.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
-[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+68755513[ ]+brev8[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+69855513[ ]+rev8[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+08f51513[ ]+zip[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+08f55513[ ]+unzip[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+28c5a533[ ]+xperm4[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+28c5c533[ ]+xperm8[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+aac58533[ ]+aes32dsi[ ]+a0,a1,a2,0x2
-[ ]+[0-9a-f]+:[ ]+aec58533[ ]+aes32dsmi[ ]+a0,a1,a2,0x2
-[ ]+[0-9a-f]+:[ ]+a2c58533[ ]+aes32esi[ ]+a0,a1,a2,0x2
-[ ]+[0-9a-f]+:[ ]+a6c58533[ ]+aes32esmi[ ]+a0,a1,a2,0x2
-[ ]+[0-9a-f]+:[ ]+10251513[ ]+sha256sig0[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10351513[ ]+sha256sig1[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10051513[ ]+sha256sum0[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10151513[ ]+sha256sum1[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+5cc58533[ ]+sha512sig0h[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+54c58533[ ]+sha512sig0l[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+5ec58533[ ]+sha512sig1h[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+56c58533[ ]+sha512sig1l[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+50c58533[ ]+sha512sum0r[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+52c58533[ ]+sha512sum1r[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+b0c58533[ ]+sm4ed[ ]+a0,a1,a2,0x2
-[ ]+[0-9a-f]+:[ ]+b4c58533[ ]+sm4ks[ ]+a0,a1,a2,0x2
-[ ]+[0-9a-f]+:[ ]+10851513[ ]+sm3p0[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10951513[ ]+sm3p1[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/k-ext.s b/gas/testsuite/gas/riscv/k-ext.s
deleted file mode 100644
index 8eb27684710..00000000000
--- a/gas/testsuite/gas/riscv/k-ext.s
+++ /dev/null
@@ -1,35 +0,0 @@
-target:
- ror a0, a1, a2
- rol a0, a1, a2
- rori a0, a1, 2
- andn a0, a1, a2
- orn a0, a1, a2
- xnor a0, a1, a2
- pack a0, a1, a2
- packh a0, a1, a2
- brev8 a0, a0
- rev8 a0, a0
- zip a0, a0
- unzip a0, a0
- clmul a0, a1, a2
- clmulh a0, a1, a2
- xperm4 a0, a1, a2
- xperm8 a0, a1, a2
- aes32dsi a0, a1, a2, 2
- aes32dsmi a0, a1, a2, 2
- aes32esi a0, a1, a2, 2
- aes32esmi a0, a1, a2, 2
- sha256sig0 a0, a0
- sha256sig1 a0, a0
- sha256sum0 a0, a0
- sha256sum1 a0, a0
- sha512sig0h a0, a1, a2
- sha512sig0l a0, a1, a2
- sha512sig1h a0, a1, a2
- sha512sig1l a0, a1, a2
- sha512sum0r a0, a1, a2
- sha512sum1r a0, a1, a2
- sm4ed a0, a1, a2, 2
- sm4ks a0, a1, a2, 2
- sm3p0 a0, a0
- sm3p1 a0, a0
diff --git a/gas/testsuite/gas/riscv/zbk-ext-32-noalias.d b/gas/testsuite/gas/riscv/zbk-ext-32-noalias.d
new file mode 100644
index 00000000000..bbbd0caefc2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbk-ext-32-noalias.d
@@ -0,0 +1,26 @@
+#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32
+#source: zbk-ext.s
+#objdump: -d -M no-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6875d513[ ]+brev8[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+6985d513[ ]+rev8[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+08f59513[ ]+zip[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+08f5d513[ ]+unzip[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+28c5a533[ ]+xperm4[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+28c5c533[ ]+xperm8[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbk-ext-32-noarch.d b/gas/testsuite/gas/riscv/zbk-ext-32-noarch.d
new file mode 100644
index 00000000000..be2c8bd653b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbk-ext-32-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32 -defsym NOARCH=1
+#source: zbk-ext.s
+#error_output: zbk-ext-32-noarch.l
diff --git a/gas/testsuite/gas/riscv/zbk-ext-32-noarch.l b/gas/testsuite/gas/riscv/zbk-ext-32-noarch.l
new file mode 100644
index 00000000000..0a9c603e7db
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbk-ext-32-noarch.l
@@ -0,0 +1,21 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `ror a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `rol a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `rori a0,a1,2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `rorw a0,a1,a2'
+.*: Error: unrecognized opcode `rolw a0,a1,a2'
+.*: Error: unrecognized opcode `roriw a0,a1,2'
+.*: Error: unrecognized opcode `andn a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `orn a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `xnor a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `pack a0,a1,a2', extension `zbkb' required
+.*: Error: unrecognized opcode `packh a0,a1,a2', extension `zbkb' required
+.*: Error: unrecognized opcode `packw a0,a1,a2'
+.*: Error: unrecognized opcode `brev8 a0,a1', extension `zbkb' required
+.*: Error: unrecognized opcode `rev8 a0,a1', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `zip a0,a1', extension `zbkb' required
+.*: Error: unrecognized opcode `unzip a0,a1', extension `zbkb' required
+.*: Error: unrecognized opcode `clmul a0,a1,a2', extension `zbc' or `zbkc' required
+.*: Error: unrecognized opcode `clmulh a0,a1,a2', extension `zbc' or `zbkc' required
+.*: Error: unrecognized opcode `xperm4 a0,a1,a2', extension `zbkx' required
+.*: Error: unrecognized opcode `xperm8 a0,a1,a2', extension `zbkx' required
diff --git a/gas/testsuite/gas/riscv/zbk-ext-32.d b/gas/testsuite/gas/riscv/zbk-ext-32.d
new file mode 100644
index 00000000000..05c6fddaef4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbk-ext-32.d
@@ -0,0 +1,26 @@
+#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32
+#source: zbk-ext.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6875d513[ ]+brev8[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+6985d513[ ]+rev8[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+08f59513[ ]+zip[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+08f5d513[ ]+unzip[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+28c5a533[ ]+xperm4[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+28c5c533[ ]+xperm8[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbk-ext-64-noalias.d b/gas/testsuite/gas/riscv/zbk-ext-64-noalias.d
new file mode 100644
index 00000000000..03ee8c809b0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbk-ext-64-noalias.d
@@ -0,0 +1,28 @@
+#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64
+#source: zbk-ext.s
+#objdump: -d -M no-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6025d51b[ ]+roriw[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+08c5c53b[ ]+packw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6875d513[ ]+brev8[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+6b85d513[ ]+rev8[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+28c5a533[ ]+xperm4[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+28c5c533[ ]+xperm8[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbk-ext-64-noarch.d b/gas/testsuite/gas/riscv/zbk-ext-64-noarch.d
new file mode 100644
index 00000000000..de1c854b808
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbk-ext-64-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64 -defsym NOARCH=1
+#source: zbk-ext.s
+#error_output: zbk-ext-64-noarch.l
diff --git a/gas/testsuite/gas/riscv/zbk-ext-64-noarch.l b/gas/testsuite/gas/riscv/zbk-ext-64-noarch.l
new file mode 100644
index 00000000000..e0759ac4b7a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbk-ext-64-noarch.l
@@ -0,0 +1,21 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `ror a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `rol a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `rori a0,a1,2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `rorw a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `rolw a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `roriw a0,a1,2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `andn a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `orn a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `xnor a0,a1,a2', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `pack a0,a1,a2', extension `zbkb' required
+.*: Error: unrecognized opcode `packh a0,a1,a2', extension `zbkb' required
+.*: Error: unrecognized opcode `packw a0,a1,a2', extension `zbkb' required
+.*: Error: unrecognized opcode `brev8 a0,a1', extension `zbkb' required
+.*: Error: unrecognized opcode `rev8 a0,a1', extension `zbb' or `zbkb' required
+.*: Error: unrecognized opcode `zip a0,a1'
+.*: Error: unrecognized opcode `unzip a0,a1'
+.*: Error: unrecognized opcode `clmul a0,a1,a2', extension `zbc' or `zbkc' required
+.*: Error: unrecognized opcode `clmulh a0,a1,a2', extension `zbc' or `zbkc' required
+.*: Error: unrecognized opcode `xperm4 a0,a1,a2', extension `zbkx' required
+.*: Error: unrecognized opcode `xperm8 a0,a1,a2', extension `zbkx' required
diff --git a/gas/testsuite/gas/riscv/zbk-ext-64.d b/gas/testsuite/gas/riscv/zbk-ext-64.d
new file mode 100644
index 00000000000..2c2a0098cac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbk-ext-64.d
@@ -0,0 +1,28 @@
+#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64
+#source: zbk-ext.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6025d51b[ ]+rorw[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+08c5c53b[ ]+packw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6875d513[ ]+brev8[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+6b85d513[ ]+rev8[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+28c5a533[ ]+xperm4[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+28c5c533[ ]+xperm8[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbk-ext.s b/gas/testsuite/gas/riscv/zbk-ext.s
new file mode 100644
index 00000000000..d839513d592
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbk-ext.s
@@ -0,0 +1,37 @@
+.include "testutils.inc"
+
+target:
+ SET_ARCH_START +zbkb
+ ror a0, a1, a2
+ rol a0, a1, a2
+ rori a0, a1, 2
+.if XLEN_GE_64
+ rorw a0, a1, a2
+ rolw a0, a1, a2
+ roriw a0, a1, 2
+.endif
+ andn a0, a1, a2
+ orn a0, a1, a2
+ xnor a0, a1, a2
+ pack a0, a1, a2
+ packh a0, a1, a2
+.if XLEN_GE_64
+ packw a0, a1, a2
+.endif
+ brev8 a0, a1
+ rev8 a0, a1
+.if XLEN_EQ_32
+ zip a0, a1
+ unzip a0, a1
+.endif
+ SET_ARCH_END
+
+ SET_ARCH_START +zbkc
+ clmul a0, a1, a2
+ clmulh a0, a1, a2
+ SET_ARCH_END
+
+ SET_ARCH_START +zbkx
+ xperm4 a0, a1, a2
+ xperm8 a0, a1, a2
+ SET_ARCH_END
diff --git a/gas/testsuite/gas/riscv/zbkb-32-na.d b/gas/testsuite/gas/riscv/zbkb-32-na.d
deleted file mode 100644
index a7b67ca4468..00000000000
--- a/gas/testsuite/gas/riscv/zbkb-32-na.d
+++ /dev/null
@@ -1,23 +0,0 @@
-#as: -march=rv32i_zbkb
-#source: zbkb-32.s
-#objdump: -d -Mno-aliases
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
-[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+68755513[ ]+brev8[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+69855513[ ]+rev8[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+08f51513[ ]+zip[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+08f55513[ ]+unzip[ ]+a0,a0
-#pass
diff --git a/gas/testsuite/gas/riscv/zbkb-32.d b/gas/testsuite/gas/riscv/zbkb-32.d
deleted file mode 100644
index 1ab233c7778..00000000000
--- a/gas/testsuite/gas/riscv/zbkb-32.d
+++ /dev/null
@@ -1,22 +0,0 @@
-#as: -march=rv32i_zbkb
-#source: zbkb-32.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
-[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+68755513[ ]+brev8[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+69855513[ ]+rev8[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+08f51513[ ]+zip[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+08f55513[ ]+unzip[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zbkb-32.s b/gas/testsuite/gas/riscv/zbkb-32.s
deleted file mode 100644
index 6f917154517..00000000000
--- a/gas/testsuite/gas/riscv/zbkb-32.s
+++ /dev/null
@@ -1,13 +0,0 @@
-target:
- ror a0, a1, a2
- rol a0, a1, a2
- rori a0, a1, 2
- andn a0, a1, a2
- orn a0, a1, a2
- xnor a0, a1, a2
- pack a0, a1, a2
- packh a0, a1, a2
- brev8 a0, a0
- rev8 a0, a0
- zip a0, a0
- unzip a0, a0
diff --git a/gas/testsuite/gas/riscv/zbkb-64.d b/gas/testsuite/gas/riscv/zbkb-64.d
deleted file mode 100644
index e942bc6f1f0..00000000000
--- a/gas/testsuite/gas/riscv/zbkb-64.d
+++ /dev/null
@@ -1,24 +0,0 @@
-#as: -march=rv64i_zbkb
-#source: zbkb-64.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
-[ ]+[0-9a-f]+:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+6025d51b[ ]+rorw[ ]+a0,a1,0x2
-[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+08c5c53b[ ]+packw[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+68755513[ ]+brev8[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+6b855513[ ]+rev8[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zbkb-64.s b/gas/testsuite/gas/riscv/zbkb-64.s
deleted file mode 100644
index b5cf79f890e..00000000000
--- a/gas/testsuite/gas/riscv/zbkb-64.s
+++ /dev/null
@@ -1,15 +0,0 @@
-target:
- ror a0, a1, a2
- rol a0, a1, a2
- rori a0, a1, 2
- rorw a0, a1, a2
- rolw a0, a1, a2
- roriw a0, a1, 2
- andn a0, a1, a2
- orn a0, a1, a2
- xnor a0, a1, a2
- pack a0, a1, a2
- packh a0, a1, a2
- packw a0, a1, a2
- brev8 a0, a0
- rev8 a0, a0
diff --git a/gas/testsuite/gas/riscv/zbkc-32.d b/gas/testsuite/gas/riscv/zbkc-32.d
deleted file mode 100644
index 69d89875652..00000000000
--- a/gas/testsuite/gas/riscv/zbkc-32.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_zbkc
-#source: zbkc.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbkc-64.d b/gas/testsuite/gas/riscv/zbkc-64.d
deleted file mode 100644
index 26cdf7014c9..00000000000
--- a/gas/testsuite/gas/riscv/zbkc-64.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv64i_zbkc
-#source: zbkc.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbkc.s b/gas/testsuite/gas/riscv/zbkc.s
deleted file mode 100644
index 2a987746e7b..00000000000
--- a/gas/testsuite/gas/riscv/zbkc.s
+++ /dev/null
@@ -1,3 +0,0 @@
-target:
- clmul a0, a1, a2
- clmulh a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zbkx-32.d b/gas/testsuite/gas/riscv/zbkx-32.d
deleted file mode 100644
index b1f7fc017bf..00000000000
--- a/gas/testsuite/gas/riscv/zbkx-32.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_zbkx
-#source: zbkx.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+28c5a533[ ]+xperm4[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+28c5c533[ ]+xperm8[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbkx-64.d b/gas/testsuite/gas/riscv/zbkx-64.d
deleted file mode 100644
index 3ab8bf69c75..00000000000
--- a/gas/testsuite/gas/riscv/zbkx-64.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv64i_zbkx
-#source: zbkx.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+28c5a533[ ]+xperm4[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+28c5c533[ ]+xperm8[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zbkx.s b/gas/testsuite/gas/riscv/zbkx.s
deleted file mode 100644
index 8c3077105fe..00000000000
--- a/gas/testsuite/gas/riscv/zbkx.s
+++ /dev/null
@@ -1,3 +0,0 @@
-target:
- xperm4 a0, a1, a2
- xperm8 a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zk-ext-32-noarch.d b/gas/testsuite/gas/riscv/zk-ext-32-noarch.d
new file mode 100644
index 00000000000..7a489dedbac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zk-ext-32-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i -mcsr-check -I$srcdir/$subdir -defsym NOARCH=1
+#source: zk-ext-32.s
+#error_output: zk-ext-32-noarch.l
diff --git a/gas/testsuite/gas/riscv/zk-ext-32-noarch.l b/gas/testsuite/gas/riscv/zk-ext-32-noarch.l
new file mode 100644
index 00000000000..372dc523276
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zk-ext-32-noarch.l
@@ -0,0 +1,20 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `aes32dsi a0,a1,a2,2', extension `zknd' required
+.*: Error: unrecognized opcode `aes32dsmi a0,a1,a2,2', extension `zknd' required
+.*: Error: unrecognized opcode `aes32esi a0,a1,a2,2', extension `zkne' required
+.*: Error: unrecognized opcode `aes32esmi a0,a1,a2,2', extension `zkne' required
+.*: Error: unrecognized opcode `sha256sig0 a0,a1', extension `zknh' required
+.*: Error: unrecognized opcode `sha256sig1 a0,a1', extension `zknh' required
+.*: Error: unrecognized opcode `sha256sum0 a0,a1', extension `zknh' required
+.*: Error: unrecognized opcode `sha256sum1 a0,a1', extension `zknh' required
+.*: Error: unrecognized opcode `sha512sig0h a0,a1,a2', extension `zknh' required
+.*: Error: unrecognized opcode `sha512sig0l a0,a1,a2', extension `zknh' required
+.*: Error: unrecognized opcode `sha512sig1h a0,a1,a2', extension `zknh' required
+.*: Error: unrecognized opcode `sha512sig1l a0,a1,a2', extension `zknh' required
+.*: Error: unrecognized opcode `sha512sum0r a0,a1,a2', extension `zknh' required
+.*: Error: unrecognized opcode `sha512sum1r a0,a1,a2', extension `zknh' required
+.*: Error: unrecognized opcode `sm4ed a0,a1,a2,2', extension `zksed' required
+.*: Error: unrecognized opcode `sm4ks a0,a1,a2,2', extension `zksed' required
+.*: Error: unrecognized opcode `sm3p0 a0,a1', extension `zksh' required
+.*: Error: unrecognized opcode `sm3p1 a0,a1', extension `zksh' required
+.*: Warning: invalid CSR `seed', needs `zkr' extension
diff --git a/gas/testsuite/gas/riscv/zk-ext-32.d b/gas/testsuite/gas/riscv/zk-ext-32.d
new file mode 100644
index 00000000000..03cd158ab43
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zk-ext-32.d
@@ -0,0 +1,28 @@
+#as: -march=rv32i -mcsr-check -I$srcdir/$subdir
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+aac58533[ ]+aes32dsi[ ]+a0,a1,a2,0x2
+[ ]+[0-9a-f]+:[ ]+aec58533[ ]+aes32dsmi[ ]+a0,a1,a2,0x2
+[ ]+[0-9a-f]+:[ ]+a2c58533[ ]+aes32esi[ ]+a0,a1,a2,0x2
+[ ]+[0-9a-f]+:[ ]+a6c58533[ ]+aes32esmi[ ]+a0,a1,a2,0x2
+[ ]+[0-9a-f]+:[ ]+10259513[ ]+sha256sig0[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+10359513[ ]+sha256sig1[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+10059513[ ]+sha256sum0[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+10159513[ ]+sha256sum1[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+5cc58533[ ]+sha512sig0h[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+54c58533[ ]+sha512sig0l[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+5ec58533[ ]+sha512sig1h[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+56c58533[ ]+sha512sig1l[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+50c58533[ ]+sha512sum0r[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+52c58533[ ]+sha512sum1r[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+b0c58533[ ]+sm4ed[ ]+a0,a1,a2,0x2
+[ ]+[0-9a-f]+:[ ]+b4c58533[ ]+sm4ks[ ]+a0,a1,a2,0x2
+[ ]+[0-9a-f]+:[ ]+10859513[ ]+sm3p0[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+10959513[ ]+sm3p1[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed
diff --git a/gas/testsuite/gas/riscv/zk-ext-32.s b/gas/testsuite/gas/riscv/zk-ext-32.s
new file mode 100644
index 00000000000..892644c054a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zk-ext-32.s
@@ -0,0 +1,41 @@
+.include "testutils.inc"
+
+target:
+ SET_ARCH_START +zknd
+ aes32dsi a0, a1, a2, 2
+ aes32dsmi a0, a1, a2, 2
+ SET_ARCH_END
+
+ SET_ARCH_START +zkne
+ aes32esi a0, a1, a2, 2
+ aes32esmi a0, a1, a2, 2
+ SET_ARCH_END
+
+ SET_ARCH_START +zknh
+ sha256sig0 a0, a1
+ sha256sig1 a0, a1
+ sha256sum0 a0, a1
+ sha256sum1 a0, a1
+ sha512sig0h a0, a1, a2
+ sha512sig0l a0, a1, a2
+ sha512sig1h a0, a1, a2
+ sha512sig1l a0, a1, a2
+ sha512sum0r a0, a1, a2
+ sha512sum1r a0, a1, a2
+ SET_ARCH_END
+
+ SET_ARCH_START +zksed
+ sm4ed a0, a1, a2, 2
+ sm4ks a0, a1, a2, 2
+ SET_ARCH_END
+
+ SET_ARCH_START +zksh
+ sm3p0 a0, a1
+ sm3p1 a0, a1
+ SET_ARCH_END
+
+ SET_ARCH_START_FORCE +zicsr
+ SET_ARCH_START +zkr
+ csrr a0, seed
+ SET_ARCH_END
+ SET_ARCH_END
diff --git a/gas/testsuite/gas/riscv/zk-ext-64-noarch.d b/gas/testsuite/gas/riscv/zk-ext-64-noarch.d
new file mode 100644
index 00000000000..e83e4b17a81
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zk-ext-64-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=rv64i -mcsr-check -I$srcdir/$subdir -defsym NOARCH=1
+#source: zk-ext-64.s
+#error_output: zk-ext-64-noarch.l
diff --git a/gas/testsuite/gas/riscv/zk-ext-64-noarch.l b/gas/testsuite/gas/riscv/zk-ext-64-noarch.l
new file mode 100644
index 00000000000..38362f54465
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zk-ext-64-noarch.l
@@ -0,0 +1,23 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `aes64ds a0,a1,a2', extension `zknd' required
+.*: Error: unrecognized opcode `aes64dsm a0,a1,a2', extension `zknd' required
+.*: Error: unrecognized opcode `aes64im a0,a1', extension `zknd' required
+.*: Error: unrecognized opcode `aes64ks1i a0,a1,4', extension `zknd' or `zkne' required
+.*: Error: unrecognized opcode `aes64ks2 a0,a1,a2', extension `zknd' or `zkne' required
+.*: Error: unrecognized opcode `aes64es a0,a1,a2', extension `zkne' required
+.*: Error: unrecognized opcode `aes64esm a0,a1,a2', extension `zkne' required
+.*: Error: unrecognized opcode `aes64ks1i a0,a1,4', extension `zknd' or `zkne' required
+.*: Error: unrecognized opcode `aes64ks2 a0,a1,a2', extension `zknd' or `zkne' required
+.*: Error: unrecognized opcode `sha256sig0 a0,a1', extension `zknh' required
+.*: Error: unrecognized opcode `sha256sig1 a0,a1', extension `zknh' required
+.*: Error: unrecognized opcode `sha256sum0 a0,a1', extension `zknh' required
+.*: Error: unrecognized opcode `sha256sum1 a0,a1', extension `zknh' required
+.*: Error: unrecognized opcode `sha512sig0 a0,a1', extension `zknh' required
+.*: Error: unrecognized opcode `sha512sig1 a0,a1', extension `zknh' required
+.*: Error: unrecognized opcode `sha512sum0 a0,a1', extension `zknh' required
+.*: Error: unrecognized opcode `sha512sum1 a0,a1', extension `zknh' required
+.*: Error: unrecognized opcode `sm4ed a0,a1,a2,2', extension `zksed' required
+.*: Error: unrecognized opcode `sm4ks a0,a1,a2,2', extension `zksed' required
+.*: Error: unrecognized opcode `sm3p0 a0,a1', extension `zksh' required
+.*: Error: unrecognized opcode `sm3p1 a0,a1', extension `zksh' required
+.*: Warning: invalid CSR `seed', needs `zkr' extension
diff --git a/gas/testsuite/gas/riscv/zk-ext-64.d b/gas/testsuite/gas/riscv/zk-ext-64.d
new file mode 100644
index 00000000000..ee134f6cdf0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zk-ext-64.d
@@ -0,0 +1,31 @@
+#as: -march=rv64i -mcsr-check -I$srcdir/$subdir
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+3ac58533[ ]+aes64ds[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+3ec58533[ ]+aes64dsm[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+30059513[ ]+aes64im[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+31459513[ ]+aes64ks1i[ ]+a0,a1,0x4
+[ ]+[0-9a-f]+:[ ]+7ec58533[ ]+aes64ks2[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+32c58533[ ]+aes64es[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+36c58533[ ]+aes64esm[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+31459513[ ]+aes64ks1i[ ]+a0,a1,0x4
+[ ]+[0-9a-f]+:[ ]+7ec58533[ ]+aes64ks2[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+10259513[ ]+sha256sig0[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+10359513[ ]+sha256sig1[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+10059513[ ]+sha256sum0[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+10159513[ ]+sha256sum1[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+10659513[ ]+sha512sig0[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+10759513[ ]+sha512sig1[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+10459513[ ]+sha512sum0[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+10559513[ ]+sha512sum1[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+b0c58533[ ]+sm4ed[ ]+a0,a1,a2,0x2
+[ ]+[0-9a-f]+:[ ]+b4c58533[ ]+sm4ks[ ]+a0,a1,a2,0x2
+[ ]+[0-9a-f]+:[ ]+10859513[ ]+sm3p0[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+10959513[ ]+sm3p1[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed
diff --git a/gas/testsuite/gas/riscv/zk-ext-64.s b/gas/testsuite/gas/riscv/zk-ext-64.s
new file mode 100644
index 00000000000..9d8104908a9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zk-ext-64.s
@@ -0,0 +1,44 @@
+.include "testutils.inc"
+
+target:
+ SET_ARCH_START +zknd
+ aes64ds a0, a1, a2
+ aes64dsm a0, a1, a2
+ aes64im a0, a1
+ aes64ks1i a0, a1, 4
+ aes64ks2 a0, a1, a2
+ SET_ARCH_END
+
+ SET_ARCH_START +zkne
+ aes64es a0, a1, a2
+ aes64esm a0, a1, a2
+ aes64ks1i a0, a1, 4
+ aes64ks2 a0, a1, a2
+ SET_ARCH_END
+
+ SET_ARCH_START +zknh
+ sha256sig0 a0, a1
+ sha256sig1 a0, a1
+ sha256sum0 a0, a1
+ sha256sum1 a0, a1
+ sha512sig0 a0, a1
+ sha512sig1 a0, a1
+ sha512sum0 a0, a1
+ sha512sum1 a0, a1
+ SET_ARCH_END
+
+ SET_ARCH_START +zksed
+ sm4ed a0, a1, a2, 2
+ sm4ks a0, a1, a2, 2
+ SET_ARCH_END
+
+ SET_ARCH_START +zksh
+ sm3p0 a0, a1
+ sm3p1 a0, a1
+ SET_ARCH_END
+
+ SET_ARCH_START_FORCE +zicsr
+ SET_ARCH_START +zkr
+ csrr a0, seed
+ SET_ARCH_END
+ SET_ARCH_END
diff --git a/gas/testsuite/gas/riscv/zknd-32.d b/gas/testsuite/gas/riscv/zknd-32.d
deleted file mode 100644
index a6995bf6f1c..00000000000
--- a/gas/testsuite/gas/riscv/zknd-32.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_zknd
-#source: zknd-32.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+aac58533[ ]+aes32dsi[ ]+a0,a1,a2,0x2
-[ ]+[0-9a-f]+:[ ]+aec58533[ ]+aes32dsmi[ ]+a0,a1,a2,0x2
diff --git a/gas/testsuite/gas/riscv/zknd-32.s b/gas/testsuite/gas/riscv/zknd-32.s
deleted file mode 100644
index 0d09badd1c6..00000000000
--- a/gas/testsuite/gas/riscv/zknd-32.s
+++ /dev/null
@@ -1,3 +0,0 @@
-target:
- aes32dsi a0, a1, a2, 2
- aes32dsmi a0, a1, a2, 2
diff --git a/gas/testsuite/gas/riscv/zknd-64.d b/gas/testsuite/gas/riscv/zknd-64.d
deleted file mode 100644
index ba4c91ceb34..00000000000
--- a/gas/testsuite/gas/riscv/zknd-64.d
+++ /dev/null
@@ -1,15 +0,0 @@
-#as: -march=rv64i_zknd
-#source: zknd-64.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+3ac58533[ ]+aes64ds[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+3ec58533[ ]+aes64dsm[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+30051513[ ]+aes64im[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+31459513[ ]+aes64ks1i[ ]+a0,a1,0x4
-[ ]+[0-9a-f]+:[ ]+7ec58533[ ]+aes64ks2[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zknd-64.s b/gas/testsuite/gas/riscv/zknd-64.s
deleted file mode 100644
index 4846e93c16f..00000000000
--- a/gas/testsuite/gas/riscv/zknd-64.s
+++ /dev/null
@@ -1,6 +0,0 @@
-target:
- aes64ds a0, a1, a2
- aes64dsm a0, a1, a2
- aes64im a0, a0
- aes64ks1i a0, a1, 4
- aes64ks2 a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zkne-32.d b/gas/testsuite/gas/riscv/zkne-32.d
deleted file mode 100644
index 4950e748800..00000000000
--- a/gas/testsuite/gas/riscv/zkne-32.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_zkne
-#source: zkne-32.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+a2c58533[ ]+aes32esi[ ]+a0,a1,a2,0x2
-[ ]+[0-9a-f]+:[ ]+a6c58533[ ]+aes32esmi[ ]+a0,a1,a2,0x2
diff --git a/gas/testsuite/gas/riscv/zkne-32.s b/gas/testsuite/gas/riscv/zkne-32.s
deleted file mode 100644
index f864fc1778b..00000000000
--- a/gas/testsuite/gas/riscv/zkne-32.s
+++ /dev/null
@@ -1,3 +0,0 @@
-target:
- aes32esi a0, a1, a2, 2
- aes32esmi a0, a1, a2, 2
diff --git a/gas/testsuite/gas/riscv/zkne-64.d b/gas/testsuite/gas/riscv/zkne-64.d
deleted file mode 100644
index 31bc084a807..00000000000
--- a/gas/testsuite/gas/riscv/zkne-64.d
+++ /dev/null
@@ -1,14 +0,0 @@
-#as: -march=rv64i_zkne
-#source: zkne-64.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+32c58533[ ]+aes64es[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+36c58533[ ]+aes64esm[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+31459513[ ]+aes64ks1i[ ]+a0,a1,0x4
-[ ]+[0-9a-f]+:[ ]+7ec58533[ ]+aes64ks2[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zkne-64.s b/gas/testsuite/gas/riscv/zkne-64.s
deleted file mode 100644
index 9b5612001af..00000000000
--- a/gas/testsuite/gas/riscv/zkne-64.s
+++ /dev/null
@@ -1,5 +0,0 @@
-target:
- aes64es a0, a1, a2
- aes64esm a0, a1, a2
- aes64ks1i a0, a1, 4
- aes64ks2 a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zknh-32.d b/gas/testsuite/gas/riscv/zknh-32.d
deleted file mode 100644
index c8ef70d67f4..00000000000
--- a/gas/testsuite/gas/riscv/zknh-32.d
+++ /dev/null
@@ -1,20 +0,0 @@
-#as: -march=rv32i_zknh
-#source: zknh-32.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+10251513[ ]+sha256sig0[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10351513[ ]+sha256sig1[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10051513[ ]+sha256sum0[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10151513[ ]+sha256sum1[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+5cc58533[ ]+sha512sig0h[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+54c58533[ ]+sha512sig0l[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+5ec58533[ ]+sha512sig1h[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+56c58533[ ]+sha512sig1l[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+50c58533[ ]+sha512sum0r[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+52c58533[ ]+sha512sum1r[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zknh-32.s b/gas/testsuite/gas/riscv/zknh-32.s
deleted file mode 100644
index dc2cd3c6657..00000000000
--- a/gas/testsuite/gas/riscv/zknh-32.s
+++ /dev/null
@@ -1,11 +0,0 @@
-target:
- sha256sig0 a0, a0
- sha256sig1 a0, a0
- sha256sum0 a0, a0
- sha256sum1 a0, a0
- sha512sig0h a0, a1, a2
- sha512sig0l a0, a1, a2
- sha512sig1h a0, a1, a2
- sha512sig1l a0, a1, a2
- sha512sum0r a0, a1, a2
- sha512sum1r a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/zknh-64.d b/gas/testsuite/gas/riscv/zknh-64.d
deleted file mode 100644
index b72e31e3547..00000000000
--- a/gas/testsuite/gas/riscv/zknh-64.d
+++ /dev/null
@@ -1,18 +0,0 @@
-#as: -march=rv64i_zknh
-#source: zknh-64.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+10251513[ ]+sha256sig0[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10351513[ ]+sha256sig1[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10051513[ ]+sha256sum0[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10151513[ ]+sha256sum1[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10651513[ ]+sha512sig0[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10751513[ ]+sha512sig1[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10451513[ ]+sha512sum0[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10551513[ ]+sha512sum1[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zknh-64.s b/gas/testsuite/gas/riscv/zknh-64.s
deleted file mode 100644
index 897dc0ba32e..00000000000
--- a/gas/testsuite/gas/riscv/zknh-64.s
+++ /dev/null
@@ -1,9 +0,0 @@
-target:
- sha256sig0 a0, a0
- sha256sig1 a0, a0
- sha256sum0 a0, a0
- sha256sum1 a0, a0
- sha512sig0 a0, a0
- sha512sig1 a0, a0
- sha512sum0 a0, a0
- sha512sum1 a0, a0
diff --git a/gas/testsuite/gas/riscv/zksed-32.d b/gas/testsuite/gas/riscv/zksed-32.d
deleted file mode 100644
index 3c84c0f31ce..00000000000
--- a/gas/testsuite/gas/riscv/zksed-32.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_zksed
-#source: zksed.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+b0c58533[ ]+sm4ed[ ]+a0,a1,a2,0x2
-[ ]+[0-9a-f]+:[ ]+b4c58533[ ]+sm4ks[ ]+a0,a1,a2,0x2
diff --git a/gas/testsuite/gas/riscv/zksed-64.d b/gas/testsuite/gas/riscv/zksed-64.d
deleted file mode 100644
index 29d828a9009..00000000000
--- a/gas/testsuite/gas/riscv/zksed-64.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv64i_zksed
-#source: zksed.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+b0c58533[ ]+sm4ed[ ]+a0,a1,a2,0x2
-[ ]+[0-9a-f]+:[ ]+b4c58533[ ]+sm4ks[ ]+a0,a1,a2,0x2
diff --git a/gas/testsuite/gas/riscv/zksed.s b/gas/testsuite/gas/riscv/zksed.s
deleted file mode 100644
index ee95c7a8584..00000000000
--- a/gas/testsuite/gas/riscv/zksed.s
+++ /dev/null
@@ -1,3 +0,0 @@
-target:
- sm4ed a0, a1, a2, 2
- sm4ks a0, a1, a2, 2
diff --git a/gas/testsuite/gas/riscv/zksh-32.d b/gas/testsuite/gas/riscv/zksh-32.d
deleted file mode 100644
index 14ac63d95e6..00000000000
--- a/gas/testsuite/gas/riscv/zksh-32.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv32i_zksh
-#source: zksh.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+10851513[ ]+sm3p0[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10951513[ ]+sm3p1[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zksh-64.d b/gas/testsuite/gas/riscv/zksh-64.d
deleted file mode 100644
index 2d13e38dd37..00000000000
--- a/gas/testsuite/gas/riscv/zksh-64.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#as: -march=rv64i_zksh
-#source: zksh.s
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+10851513[ ]+sm3p0[ ]+a0,a0
-[ ]+[0-9a-f]+:[ ]+10951513[ ]+sm3p1[ ]+a0,a0
diff --git a/gas/testsuite/gas/riscv/zksh.s b/gas/testsuite/gas/riscv/zksh.s
deleted file mode 100644
index b321c26f2b2..00000000000
--- a/gas/testsuite/gas/riscv/zksh.s
+++ /dev/null
@@ -1,3 +0,0 @@
-target:
- sm3p0 a0, a0
- sm3p1 a0, a0
diff --git a/gas/testsuite/gas/riscv/zkt.d b/gas/testsuite/gas/riscv/zkt.d
new file mode 100644
index 00000000000..feca41b64fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zkt.d
@@ -0,0 +1,5 @@
+#as: -march=rv32i_zkt
+#source: empty.s
+#objdump: -d
+
+#...
--
2.37.2
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PING^1][PATCH 00/12] RISC-V: Test refinements (Batch 1)
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
` (11 preceding siblings ...)
2022-11-05 12:29 ` [PATCH 12/12] RISC-V: Combine/enhance 'Zk*'/'Zbk*' " Tsukasa OI
@ 2022-11-20 2:28 ` Tsukasa OI
12 siblings, 0 replies; 26+ messages in thread
From: Tsukasa OI @ 2022-11-20 2:28 UTC (permalink / raw)
To: Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils
Ping.
c.f.: Original
<https://sourceware.org/pipermail/binutils/2022-November/124195.html>
Regards,
Tsukasa
On 2022/11/05 21:29, Tsukasa OI wrote:
> Hello,
>
> After mapping symbol with ISA string support with commit 40f1a1a4564b
> ("RISC-V: Output mapping symbols with ISA string.") and commit 0ce50fc900a5
> ("RISC-V: Always generate mapping symbols at the start of the sections."),
> we can merge multiple testcases.
>
> At the same time, we can improve the test coverage.
>
> This patchset:
>
> 1. Makes minor tidyings
> 2. Adds small testing utilities
> 3. Combines multiple testcases
> 4. Improves test coverage
> * Add "no required extensions" testcases
> * Uses different registers per operand (as long as allowed)
>
> While improving the test coverage, it reduces the number of testcases by 4
> (470 -> 466).
>
> Of course, this is batch 1. Although this is regular PATCH, it also intends
> to be a RFC to confirm whether I can go forward like this.
>
> I tested those testcases work with both my working tree and Nelson's.
>
> Thanks,
> Tsukasa
>
>
>
>
> Tsukasa OI (12):
> RISC-V: Remove unnecessary empty matching file
> RISC-V: Tidy disassembler corner case tests
> RISC-V: Tidying related to 'Zfinx' disassembler test
> RISC-V: GAS: Add basic shared test utilities
> RISC-V: Redefine "nop" test
> RISC-V: Reorganize/enhance {sign,zero}-extension instructions
> RISC-V: Combine complex extension error handling tests
> RISC-V: Refine/enhance 'M'/'Zmmul' extension tests
> RISC-V: Combine/enhance 'Zicbo[mz]' extension tests
> RISC-V: Enhance 'Zicbop' testcases
> RISC-V: Reorganize/enhance 'Zb*' extension tests
> RISC-V: Combine/enhance 'Zk*'/'Zbk*' extension tests
>
> gas/testsuite/gas/riscv/b-ext-64.d | 72 -----------
> gas/testsuite/gas/riscv/b-ext-64.s | 64 ----------
> gas/testsuite/gas/riscv/b-ext.d | 51 --------
> gas/testsuite/gas/riscv/b-ext.s | 43 -------
> gas/testsuite/gas/riscv/dis-addr-addiw-a.d | 2 +-
> gas/testsuite/gas/riscv/dis-addr-addiw-b.d | 2 +-
> .../gas/riscv/dis-addr-overflow-32.d | 4 +-
> .../gas/riscv/dis-addr-overflow-64.d | 4 +-
> gas/testsuite/gas/riscv/dis-addr-overflow.s | 40 +++----
> .../gas/riscv/dis-addr-topaddr-gp-32.d | 4 +-
> .../gas/riscv/dis-addr-topaddr-gp-64.d | 4 +-
> gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s | 12 +-
> ...opaddr-32.d => dis-addr-topaddr-zero-32.d} | 6 +-
> ...opaddr-64.d => dis-addr-topaddr-zero-64.d} | 6 +-
> .../gas/riscv/dis-addr-topaddr-zero.s | 11 ++
> gas/testsuite/gas/riscv/dis-addr-topaddr.s | 10 --
> gas/testsuite/gas/riscv/empty.l | 1 -
> gas/testsuite/gas/riscv/ext-32.d | 39 ------
> gas/testsuite/gas/riscv/ext-64.d | 51 --------
> gas/testsuite/gas/riscv/ext-insn-32-noalias.d | 39 ++++++
> gas/testsuite/gas/riscv/ext-insn-32-noarch.d | 3 +
> gas/testsuite/gas/riscv/ext-insn-32-noarch.l | 9 ++
> gas/testsuite/gas/riscv/ext-insn-64-noalias.d | 51 ++++++++
> gas/testsuite/gas/riscv/ext-insn-64-noarch.d | 5 +
> .../gas/riscv/ext-insn-zba-32-noalias.d | 39 ++++++
> .../gas/riscv/ext-insn-zba-64-noalias.d | 47 ++++++++
> .../gas/riscv/ext-insn-zbb-32-noalias.d | 27 +++++
> .../gas/riscv/ext-insn-zbb-64-noalias.d | 39 ++++++
> gas/testsuite/gas/riscv/ext-insn.s | 23 ++++
> gas/testsuite/gas/riscv/ext.s | 38 ------
> gas/testsuite/gas/riscv/k-ext-64.d | 47 --------
> gas/testsuite/gas/riscv/k-ext-64.s | 38 ------
> gas/testsuite/gas/riscv/k-ext.d | 44 -------
> gas/testsuite/gas/riscv/k-ext.s | 35 ------
> gas/testsuite/gas/riscv/m-ext-32-noarch-m.d | 4 +
> ...xt-fail-zmmul-32.l => m-ext-32-noarch-m.l} | 0
> gas/testsuite/gas/riscv/m-ext-32-noarch.d | 4 +
> gas/testsuite/gas/riscv/m-ext-32-noarch.l | 14 +++
> gas/testsuite/gas/riscv/m-ext-32.d | 2 +-
> gas/testsuite/gas/riscv/m-ext-64-noarch-m.d | 4 +
> ...xt-fail-zmmul-64.l => m-ext-64-noarch-m.l} | 0
> gas/testsuite/gas/riscv/m-ext-64-noarch.d | 4 +
> ...ext-fail-noarch-64.l => m-ext-64-noarch.l} | 0
> gas/testsuite/gas/riscv/m-ext-64.d | 2 +-
> .../gas/riscv/m-ext-fail-noarch-64.d | 4 -
> gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d | 4 -
> gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l | 6 -
> gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d | 4 -
> gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d | 4 -
> gas/testsuite/gas/riscv/m-ext.s | 17 ++-
> gas/testsuite/gas/riscv/nop-noalias.d | 13 ++
> gas/testsuite/gas/riscv/nop-noarch.d | 3 +
> gas/testsuite/gas/riscv/nop-noarch.l | 2 +
> gas/testsuite/gas/riscv/nop.d | 12 ++
> gas/testsuite/gas/riscv/nop.s | 9 ++
> gas/testsuite/gas/riscv/t_insns.d | 10 --
> gas/testsuite/gas/riscv/t_insns.s | 2 -
> gas/testsuite/gas/riscv/testutils.inc | 113 ++++++++++++++++++
> .../riscv/{b-ext-na.d => zb-ext-32-noalias.d} | 38 +++---
> gas/testsuite/gas/riscv/zb-ext-32-noarch.d | 3 +
> gas/testsuite/gas/riscv/zb-ext-32-noarch.l | 60 ++++++++++
> gas/testsuite/gas/riscv/zb-ext-32.d | 51 ++++++++
> .../{b-ext-64-na.d => zb-ext-64-noalias.d} | 72 +++++------
> gas/testsuite/gas/riscv/zb-ext-64-noarch.d | 3 +
> gas/testsuite/gas/riscv/zb-ext-64-noarch.l | 59 +++++++++
> gas/testsuite/gas/riscv/zb-ext-64.d | 72 +++++++++++
> gas/testsuite/gas/riscv/zb-ext.s | 84 +++++++++++++
> gas/testsuite/gas/riscv/zbk-ext-32-noalias.d | 26 ++++
> gas/testsuite/gas/riscv/zbk-ext-32-noarch.d | 3 +
> gas/testsuite/gas/riscv/zbk-ext-32-noarch.l | 21 ++++
> gas/testsuite/gas/riscv/zbk-ext-32.d | 26 ++++
> gas/testsuite/gas/riscv/zbk-ext-64-noalias.d | 28 +++++
> gas/testsuite/gas/riscv/zbk-ext-64-noarch.d | 3 +
> gas/testsuite/gas/riscv/zbk-ext-64-noarch.l | 21 ++++
> gas/testsuite/gas/riscv/zbk-ext-64.d | 28 +++++
> gas/testsuite/gas/riscv/zbk-ext.s | 37 ++++++
> gas/testsuite/gas/riscv/zbkb-32-na.d | 23 ----
> gas/testsuite/gas/riscv/zbkb-32.d | 22 ----
> gas/testsuite/gas/riscv/zbkb-32.s | 13 --
> gas/testsuite/gas/riscv/zbkb-64.d | 24 ----
> gas/testsuite/gas/riscv/zbkb-64.s | 15 ---
> gas/testsuite/gas/riscv/zbkc-32.d | 12 --
> gas/testsuite/gas/riscv/zbkc-64.d | 12 --
> gas/testsuite/gas/riscv/zbkc.s | 3 -
> gas/testsuite/gas/riscv/zbkx-32.d | 12 --
> gas/testsuite/gas/riscv/zbkx-64.d | 12 --
> gas/testsuite/gas/riscv/zbkx.s | 3 -
> .../gas/riscv/zfhmin-d-insn-class-fail-1.d | 3 -
> .../gas/riscv/zfhmin-d-insn-class-fail-1.l | 2 -
> .../gas/riscv/zfhmin-d-insn-class-fail-2.d | 3 -
> .../gas/riscv/zfhmin-d-insn-class-fail-2.l | 2 -
> .../gas/riscv/zfhmin-d-insn-class-fail-3.d | 3 -
> .../gas/riscv/zfhmin-d-insn-class-fail-3.l | 2 -
> .../gas/riscv/zfhmin-d-insn-class-fail-4.d | 3 -
> .../gas/riscv/zfhmin-d-insn-class-fail-4.l | 2 -
> .../gas/riscv/zfhmin-d-insn-class-fail-5.d | 3 -
> .../gas/riscv/zfhmin-d-insn-class-fail-5.l | 2 -
> .../gas/riscv/zfhmin-d-insn-class-fail.s | 4 -
> gas/testsuite/gas/riscv/zfhmin-d-noarch.d | 2 +
> gas/testsuite/gas/riscv/zfhmin-d-noarch.l | 6 +
> gas/testsuite/gas/riscv/zfhmin-d-noarch.s | 25 ++++
> gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 7 +-
> gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d | 2 +
> gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l | 11 ++
> .../{zicbom-fail.s => zicbo-mz-ext-fail.s} | 4 +
> gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d | 3 +
> gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l | 11 ++
> .../gas/riscv/{zicbom.d => zicbo-mz-ext.d} | 9 +-
> gas/testsuite/gas/riscv/zicbo-mz-ext.s | 16 +++
> gas/testsuite/gas/riscv/zicbom-fail.d | 3 -
> gas/testsuite/gas/riscv/zicbom-fail.l | 7 --
> gas/testsuite/gas/riscv/zicbom.s | 7 --
> gas/testsuite/gas/riscv/zicbop-fail-offset.d | 2 +
> .../{zicbop-fail.l => zicbop-fail-offset.l} | 0
> .../{zicbop-fail.s => zicbop-fail-offset.s} | 0
> gas/testsuite/gas/riscv/zicbop-fail.d | 3 -
> gas/testsuite/gas/riscv/zicbop-noarch.d | 4 +
> gas/testsuite/gas/riscv/zicbop-noarch.l | 7 ++
> gas/testsuite/gas/riscv/zicbop.d | 8 +-
> gas/testsuite/gas/riscv/zicbop.s | 7 ++
> gas/testsuite/gas/riscv/zicboz-fail.d | 3 -
> gas/testsuite/gas/riscv/zicboz-fail.l | 5 -
> gas/testsuite/gas/riscv/zicboz-fail.s | 5 -
> gas/testsuite/gas/riscv/zicboz.d | 13 --
> gas/testsuite/gas/riscv/zicboz.s | 5 -
> gas/testsuite/gas/riscv/zk-ext-32-noarch.d | 3 +
> gas/testsuite/gas/riscv/zk-ext-32-noarch.l | 20 ++++
> gas/testsuite/gas/riscv/zk-ext-32.d | 28 +++++
> gas/testsuite/gas/riscv/zk-ext-32.s | 41 +++++++
> gas/testsuite/gas/riscv/zk-ext-64-noarch.d | 3 +
> gas/testsuite/gas/riscv/zk-ext-64-noarch.l | 23 ++++
> gas/testsuite/gas/riscv/zk-ext-64.d | 31 +++++
> gas/testsuite/gas/riscv/zk-ext-64.s | 44 +++++++
> gas/testsuite/gas/riscv/zknd-32.d | 12 --
> gas/testsuite/gas/riscv/zknd-32.s | 3 -
> gas/testsuite/gas/riscv/zknd-64.d | 15 ---
> gas/testsuite/gas/riscv/zknd-64.s | 6 -
> gas/testsuite/gas/riscv/zkne-32.d | 12 --
> gas/testsuite/gas/riscv/zkne-32.s | 3 -
> gas/testsuite/gas/riscv/zkne-64.d | 14 ---
> gas/testsuite/gas/riscv/zkne-64.s | 5 -
> gas/testsuite/gas/riscv/zknh-32.d | 20 ----
> gas/testsuite/gas/riscv/zknh-32.s | 11 --
> gas/testsuite/gas/riscv/zknh-64.d | 18 ---
> gas/testsuite/gas/riscv/zknh-64.s | 9 --
> gas/testsuite/gas/riscv/zksed-32.d | 12 --
> gas/testsuite/gas/riscv/zksed-64.d | 12 --
> gas/testsuite/gas/riscv/zksed.s | 3 -
> gas/testsuite/gas/riscv/zksh-32.d | 12 --
> gas/testsuite/gas/riscv/zksh-64.d | 12 --
> gas/testsuite/gas/riscv/zksh.s | 3 -
> gas/testsuite/gas/riscv/zkt.d | 5 +
> gas/testsuite/gas/riscv/zmmul-32.d | 14 ---
> gas/testsuite/gas/riscv/zmmul-64.d | 15 ---
> 154 files changed, 1422 insertions(+), 1124 deletions(-)
> delete mode 100644 gas/testsuite/gas/riscv/b-ext-64.d
> delete mode 100644 gas/testsuite/gas/riscv/b-ext-64.s
> delete mode 100644 gas/testsuite/gas/riscv/b-ext.d
> delete mode 100644 gas/testsuite/gas/riscv/b-ext.s
> rename gas/testsuite/gas/riscv/{dis-addr-topaddr-32.d => dis-addr-topaddr-zero-32.d} (60%)
> rename gas/testsuite/gas/riscv/{dis-addr-topaddr-64.d => dis-addr-topaddr-zero-64.d} (58%)
> create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-zero.s
> delete mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr.s
> delete mode 100644 gas/testsuite/gas/riscv/empty.l
> delete mode 100644 gas/testsuite/gas/riscv/ext-32.d
> delete mode 100644 gas/testsuite/gas/riscv/ext-64.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-32-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-32-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-32-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-64-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-64-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-zba-32-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-zba-64-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-zbb-32-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-zbb-64-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn.s
> delete mode 100644 gas/testsuite/gas/riscv/ext.s
> delete mode 100644 gas/testsuite/gas/riscv/k-ext-64.d
> delete mode 100644 gas/testsuite/gas/riscv/k-ext-64.s
> delete mode 100644 gas/testsuite/gas/riscv/k-ext.d
> delete mode 100644 gas/testsuite/gas/riscv/k-ext.s
> create mode 100644 gas/testsuite/gas/riscv/m-ext-32-noarch-m.d
> rename gas/testsuite/gas/riscv/{m-ext-fail-zmmul-32.l => m-ext-32-noarch-m.l} (100%)
> create mode 100644 gas/testsuite/gas/riscv/m-ext-32-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/m-ext-32-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/m-ext-64-noarch-m.d
> rename gas/testsuite/gas/riscv/{m-ext-fail-zmmul-64.l => m-ext-64-noarch-m.l} (100%)
> create mode 100644 gas/testsuite/gas/riscv/m-ext-64-noarch.d
> rename gas/testsuite/gas/riscv/{m-ext-fail-noarch-64.l => m-ext-64-noarch.l} (100%)
> delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
> delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
> delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
> delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
> delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
> create mode 100644 gas/testsuite/gas/riscv/nop-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/nop-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/nop-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/nop.d
> create mode 100644 gas/testsuite/gas/riscv/nop.s
> delete mode 100644 gas/testsuite/gas/riscv/t_insns.d
> delete mode 100644 gas/testsuite/gas/riscv/t_insns.s
> create mode 100644 gas/testsuite/gas/riscv/testutils.inc
> rename gas/testsuite/gas/riscv/{b-ext-na.d => zb-ext-32-noalias.d} (67%)
> create mode 100644 gas/testsuite/gas/riscv/zb-ext-32-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zb-ext-32-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/zb-ext-32.d
> rename gas/testsuite/gas/riscv/{b-ext-64-na.d => zb-ext-64-noalias.d} (73%)
> create mode 100644 gas/testsuite/gas/riscv/zb-ext-64-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zb-ext-64-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/zb-ext-64.d
> create mode 100644 gas/testsuite/gas/riscv/zb-ext.s
> create mode 100644 gas/testsuite/gas/riscv/zbk-ext-32-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/zbk-ext-32-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zbk-ext-32-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/zbk-ext-32.d
> create mode 100644 gas/testsuite/gas/riscv/zbk-ext-64-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/zbk-ext-64-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zbk-ext-64-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/zbk-ext-64.d
> create mode 100644 gas/testsuite/gas/riscv/zbk-ext.s
> delete mode 100644 gas/testsuite/gas/riscv/zbkb-32-na.d
> delete mode 100644 gas/testsuite/gas/riscv/zbkb-32.d
> delete mode 100644 gas/testsuite/gas/riscv/zbkb-32.s
> delete mode 100644 gas/testsuite/gas/riscv/zbkb-64.d
> delete mode 100644 gas/testsuite/gas/riscv/zbkb-64.s
> delete mode 100644 gas/testsuite/gas/riscv/zbkc-32.d
> delete mode 100644 gas/testsuite/gas/riscv/zbkc-64.d
> delete mode 100644 gas/testsuite/gas/riscv/zbkc.s
> delete mode 100644 gas/testsuite/gas/riscv/zbkx-32.d
> delete mode 100644 gas/testsuite/gas/riscv/zbkx-64.d
> delete mode 100644 gas/testsuite/gas/riscv/zbkx.s
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s
> create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-noarch.s
> create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d
> create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l
> rename gas/testsuite/gas/riscv/{zicbom-fail.s => zicbo-mz-ext-fail.s} (61%)
> create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l
> rename gas/testsuite/gas/riscv/{zicbom.d => zicbo-mz-ext.d} (60%)
> create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext.s
> delete mode 100644 gas/testsuite/gas/riscv/zicbom-fail.d
> delete mode 100644 gas/testsuite/gas/riscv/zicbom-fail.l
> delete mode 100644 gas/testsuite/gas/riscv/zicbom.s
> create mode 100644 gas/testsuite/gas/riscv/zicbop-fail-offset.d
> rename gas/testsuite/gas/riscv/{zicbop-fail.l => zicbop-fail-offset.l} (100%)
> rename gas/testsuite/gas/riscv/{zicbop-fail.s => zicbop-fail-offset.s} (100%)
> delete mode 100644 gas/testsuite/gas/riscv/zicbop-fail.d
> create mode 100644 gas/testsuite/gas/riscv/zicbop-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zicbop-noarch.l
> delete mode 100644 gas/testsuite/gas/riscv/zicboz-fail.d
> delete mode 100644 gas/testsuite/gas/riscv/zicboz-fail.l
> delete mode 100644 gas/testsuite/gas/riscv/zicboz-fail.s
> delete mode 100644 gas/testsuite/gas/riscv/zicboz.d
> delete mode 100644 gas/testsuite/gas/riscv/zicboz.s
> create mode 100644 gas/testsuite/gas/riscv/zk-ext-32-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zk-ext-32-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/zk-ext-32.d
> create mode 100644 gas/testsuite/gas/riscv/zk-ext-32.s
> create mode 100644 gas/testsuite/gas/riscv/zk-ext-64-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zk-ext-64-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/zk-ext-64.d
> create mode 100644 gas/testsuite/gas/riscv/zk-ext-64.s
> delete mode 100644 gas/testsuite/gas/riscv/zknd-32.d
> delete mode 100644 gas/testsuite/gas/riscv/zknd-32.s
> delete mode 100644 gas/testsuite/gas/riscv/zknd-64.d
> delete mode 100644 gas/testsuite/gas/riscv/zknd-64.s
> delete mode 100644 gas/testsuite/gas/riscv/zkne-32.d
> delete mode 100644 gas/testsuite/gas/riscv/zkne-32.s
> delete mode 100644 gas/testsuite/gas/riscv/zkne-64.d
> delete mode 100644 gas/testsuite/gas/riscv/zkne-64.s
> delete mode 100644 gas/testsuite/gas/riscv/zknh-32.d
> delete mode 100644 gas/testsuite/gas/riscv/zknh-32.s
> delete mode 100644 gas/testsuite/gas/riscv/zknh-64.d
> delete mode 100644 gas/testsuite/gas/riscv/zknh-64.s
> delete mode 100644 gas/testsuite/gas/riscv/zksed-32.d
> delete mode 100644 gas/testsuite/gas/riscv/zksed-64.d
> delete mode 100644 gas/testsuite/gas/riscv/zksed.s
> delete mode 100644 gas/testsuite/gas/riscv/zksh-32.d
> delete mode 100644 gas/testsuite/gas/riscv/zksh-64.d
> delete mode 100644 gas/testsuite/gas/riscv/zksh.s
> create mode 100644 gas/testsuite/gas/riscv/zkt.d
> delete mode 100644 gas/testsuite/gas/riscv/zmmul-32.d
> delete mode 100644 gas/testsuite/gas/riscv/zmmul-64.d
>
>
> base-commit: cb9bdc02fdf1650341276861f6ca7e7a215a1ce6
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 01/12] RISC-V: Remove unnecessary empty matching file
2022-11-05 12:29 ` [PATCH 01/12] RISC-V: Remove unnecessary empty matching file Tsukasa OI
@ 2022-11-29 7:38 ` Nelson Chu
0 siblings, 0 replies; 26+ messages in thread
From: Nelson Chu @ 2022-11-29 7:38 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Kito Cheng, Palmer Dabbelt, binutils
OKay, that makes sense.
Thanks
Nelson
On Sat, Nov 5, 2022 at 8:29 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> We don't need empty "output" matching file since we can just omit specifying
> error_output or warning_output. So, this commit removes unused and
> unnecessary empty.l.
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/empty.l: Removed.
> ---
> gas/testsuite/gas/riscv/empty.l | 1 -
> 1 file changed, 1 deletion(-)
> delete mode 100644 gas/testsuite/gas/riscv/empty.l
>
> diff --git a/gas/testsuite/gas/riscv/empty.l b/gas/testsuite/gas/riscv/empty.l
> deleted file mode 100644
> index 8b137891791..00000000000
> --- a/gas/testsuite/gas/riscv/empty.l
> +++ /dev/null
> @@ -1 +0,0 @@
> -
> --
> 2.37.2
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 02/12] RISC-V: Tidy disassembler corner case tests
2022-11-05 12:29 ` [PATCH 02/12] RISC-V: Tidy disassembler corner case tests Tsukasa OI
@ 2022-11-29 7:48 ` Nelson Chu
0 siblings, 0 replies; 26+ messages in thread
From: Nelson Chu @ 2022-11-29 7:48 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Kito Cheng, Palmer Dabbelt, binutils
If the purpose of this patch is to prepare to support rv128 or larger
xlen, then I'm ok with it, although it seems useless until we have
already had any rv128 instructions. Btw, I cannot figure out the
purpose of this patch from the title "RISC-V: Tidy disassembler corner
case tests". It seems like it's not only for the tidy from the
contents.
Thanks
Nelson
On Sat, Nov 5, 2022 at 8:29 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> Because later commits use "XLEN" symbol rather than "rv64", it replaces
> occurrences of "rv64" with "XLEN" and makes other tidying changes for
> consistency with other testcases.
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/dis-addr-addiw-a.d: Tidying.
> * testsuite/gas/riscv/dis-addr-addiw-b.d: Likewise.
> * testsuite/gas/riscv/dis-addr-overflow.s: Tidying.
> * testsuite/gas/riscv/dis-addr-overflow-32.d: Use XLEN symbol.
> * testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise.
> * testsuite/gas/riscv/dis-addr-topaddr-gp.s: Tidying.
> * testsuite/gas/riscv/dis-addr-topaddr-gp-32.d: Use XLEN symbol.
> * testsuite/gas/riscv/dis-addr-topaddr-gp-64.d: Likewise.
> * testsuite/gas/riscv/dis-addr-topaddr.s: Moved to...
> * testsuite/gas/riscv/dis-addr-topaddr-zero.s: ...here
> with tidying.
> * testsuite/gas/riscv/dis-addr-topaddr-32.d: Moved to...
> * testsuite/gas/riscv/dis-addr-topaddr-zero-32.d: ...here.
> Use XLEN symbol. Minimize architecture requirements.
> * testsuite/gas/riscv/dis-addr-topaddr-64.d: Moved to...
> * testsuite/gas/riscv/dis-addr-topaddr-zero-64.d: ...here.
> Use XLEN symbol. Minimize architecture requirements.
> ---
> gas/testsuite/gas/riscv/dis-addr-addiw-a.d | 2 +-
> gas/testsuite/gas/riscv/dis-addr-addiw-b.d | 2 +-
> .../gas/riscv/dis-addr-overflow-32.d | 4 +-
> .../gas/riscv/dis-addr-overflow-64.d | 4 +-
> gas/testsuite/gas/riscv/dis-addr-overflow.s | 40 +++++++++----------
> .../gas/riscv/dis-addr-topaddr-gp-32.d | 4 +-
> .../gas/riscv/dis-addr-topaddr-gp-64.d | 4 +-
> gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s | 12 +++---
> ...opaddr-32.d => dis-addr-topaddr-zero-32.d} | 6 +--
> ...opaddr-64.d => dis-addr-topaddr-zero-64.d} | 6 +--
> .../gas/riscv/dis-addr-topaddr-zero.s | 11 +++++
> gas/testsuite/gas/riscv/dis-addr-topaddr.s | 10 -----
> 12 files changed, 53 insertions(+), 52 deletions(-)
> rename gas/testsuite/gas/riscv/{dis-addr-topaddr-32.d => dis-addr-topaddr-zero-32.d} (60%)
> rename gas/testsuite/gas/riscv/{dis-addr-topaddr-64.d => dis-addr-topaddr-zero-64.d} (58%)
> create mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr-zero.s
> delete mode 100644 gas/testsuite/gas/riscv/dis-addr-topaddr.s
>
> diff --git a/gas/testsuite/gas/riscv/dis-addr-addiw-a.d b/gas/testsuite/gas/riscv/dis-addr-addiw-a.d
> index c4e4cfe6df7..44837ff4f69 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-addiw-a.d
> +++ b/gas/testsuite/gas/riscv/dis-addr-addiw-a.d
> @@ -2,7 +2,7 @@
> #source: dis-addr-addiw.s
> #objdump: -d --adjust-vma=0xffffffe0
>
> -.*: file format elf64-(little|big)riscv
> +.*:[ ]+file format .*
>
>
> Disassembly of section .text:
> diff --git a/gas/testsuite/gas/riscv/dis-addr-addiw-b.d b/gas/testsuite/gas/riscv/dis-addr-addiw-b.d
> index d5f84db172e..bc1841f35f1 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-addiw-b.d
> +++ b/gas/testsuite/gas/riscv/dis-addr-addiw-b.d
> @@ -2,7 +2,7 @@
> #source: dis-addr-addiw.s
> #objdump: -d --adjust-vma=0x7fffffe0
>
> -.*: file format elf64-(little|big)riscv
> +.*:[ ]+file format .*
>
>
> Disassembly of section .text:
> diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow-32.d b/gas/testsuite/gas/riscv/dis-addr-overflow-32.d
> index 287c5ea022f..b246605e361 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-overflow-32.d
> +++ b/gas/testsuite/gas/riscv/dis-addr-overflow-32.d
> @@ -1,8 +1,8 @@
> -#as: -march=rv32ic
> +#as: -march=rv32ic -defsym XLEN=32
> #source: dis-addr-overflow.s
> #objdump: -d
>
> -.*: file format elf32-(little|big)riscv
> +.*:[ ]+file format .*
>
>
> Disassembly of section .text:
> diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow-64.d b/gas/testsuite/gas/riscv/dis-addr-overflow-64.d
> index 1966a5ed743..61885edbc75 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-overflow-64.d
> +++ b/gas/testsuite/gas/riscv/dis-addr-overflow-64.d
> @@ -1,8 +1,8 @@
> -#as: -march=rv64ic -defsym rv64=1
> +#as: -march=rv64ic -defsym XLEN=64
> #source: dis-addr-overflow.s
> #objdump: -d
>
> -.*: file format elf64-(little|big)riscv
> +.*:[ ]+file format .*
>
>
> Disassembly of section .text:
> diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow.s b/gas/testsuite/gas/riscv/dis-addr-overflow.s
> index 77ca39c07b6..47e5351c9fc 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-overflow.s
> +++ b/gas/testsuite/gas/riscv/dis-addr-overflow.s
> @@ -1,26 +1,26 @@
> -.set __global_pointer$, 0x00000200
> +.set __global_pointer$, 0x00000200
>
> -.ifdef rv64
> -topbase = 0xffffffff00000000
> +.ifge XLEN-64
> +.set topbase, 0xffffffff00000000
> .else
> -topbase = 0
> +.set topbase, 0
> .endif
>
> -.set addr_load, topbase + 0xffffeffc # -0x1000 -4
> -.set addr_store, topbase + 0xffffdff8 # -0x2000 -8
> -.set addr_jalr_1, topbase + 0xffffd000 # -0x3000
> -.set addr_jalr_2, topbase + 0xffffbff4 # -0x4000 -12
> -.set addr_jalr_3, topbase + 0xffffb000 # -0x5000
> -.set addr_loadaddr, topbase + 0xffff9ff0 # -0x6000 -16
> -.set addr_loadaddr_c, topbase + 0xffff8fec # -0x7000 -20
> -.set addr_loadaddr_w, topbase + 0xffff7fe8 # -0x8000 -24
> -.set addr_loadaddr_w_c, topbase + 0xffff6fe4 # -0x9000 -28
> -.set addr_rel_gp_pos, 0x00000600 # __global_pointer$ + 0x400
> -.set addr_rel_gp_neg, topbase + 0xfffffe00 # __global_pointer$ - 0x400
> -.set addr_rel_zero_pos, 0x00000100
> -.set addr_rel_zero_neg, topbase + 0xfffff800 # -0x800
> -.set addr_jalr_rel_zero_pos, 0x00000104
> -.set addr_jalr_rel_zero_neg, topbase + 0xfffff804 # -0x7fc
> +.set addr_load, topbase + 0xffffeffc # -0x1000 -4
> +.set addr_store, topbase + 0xffffdff8 # -0x2000 -8
> +.set addr_jalr_1, topbase + 0xffffd000 # -0x3000
> +.set addr_jalr_2, topbase + 0xffffbff4 # -0x4000 -12
> +.set addr_jalr_3, topbase + 0xffffb000 # -0x5000
> +.set addr_loadaddr, topbase + 0xffff9ff0 # -0x6000 -16
> +.set addr_loadaddr_c, topbase + 0xffff8fec # -0x7000 -20
> +.set addr_loadaddr_w, topbase + 0xffff7fe8 # -0x8000 -24
> +.set addr_loadaddr_w_c, topbase + 0xffff6fe4 # -0x9000 -28
> +.set addr_rel_gp_pos, 0x00000600 # __global_pointer$ + 0x400
> +.set addr_rel_gp_neg, topbase + 0xfffffe00 # __global_pointer$ - 0x400
> +.set addr_rel_zero_pos, 0x00000100
> +.set addr_rel_zero_neg, topbase + 0xfffff800 # -0x800
> +.set addr_jalr_rel_zero_pos, 0x00000104
> +.set addr_jalr_rel_zero_neg, topbase + 0xfffff804 # -0x7fc
>
> target:
> .option push
> @@ -48,7 +48,7 @@ target:
> lui t6, 0xffff9
> .option pop
> c.addi t6, -20
> -.ifdef rv64
> +.ifge XLEN-64
> .option push
> .option arch, -c
> # ADDIW (not compressed)
> diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
> index 875bfe73189..cdbbe3bf846 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
> +++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-32.d
> @@ -1,8 +1,8 @@
> -#as: -march=rv32i
> +#as: -march=rv32i -defsym XLEN=32
> #source: dis-addr-topaddr-gp.s
> #objdump: -d
>
> -.*: file format elf32-(little|big)riscv
> +.*:[ ]+file format .*
>
>
> Disassembly of section .text:
> diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
> index 5ac4b52b18d..54fc8631901 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
> +++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp-64.d
> @@ -1,8 +1,8 @@
> -#as: -march=rv64i -defsym rv64=1
> +#as: -march=rv64i -defsym XLEN=64
> #source: dis-addr-topaddr-gp.s
> #objdump: -d
>
> -.*: file format elf64-(little|big)riscv
> +.*:[ ]+file format .*
>
>
> Disassembly of section .text:
> diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s
> index 6ba9fc7a39d..1689cdf89c1 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s
> +++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-gp.s
> @@ -1,12 +1,12 @@
> -.ifdef rv64
> -topbase = 0xffffffff00000000
> +.ifge XLEN-64
> +.set topbase, 0xffffffff00000000
> .else
> -topbase = 0
> +.set topbase, 0
> .endif
>
> -.set __global_pointer$, topbase + 0xffffffff # -1
> -.set addr_rel_gp_pos, 0x00000004 # +4
> -.set addr_rel_gp_neg, topbase + 0xfffffffc # -4
> +.set __global_pointer$, topbase + 0xffffffff # -1
> +.set addr_rel_gp_pos, 0x00000004 # +4
> +.set addr_rel_gp_neg, topbase + 0xfffffffc # -4
>
> target:
> # Use addresses relative to gp
> diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-32.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-zero-32.d
> similarity index 60%
> rename from gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
> rename to gas/testsuite/gas/riscv/dis-addr-topaddr-zero-32.d
> index 87854cd58e6..2934e2d5fec 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-topaddr-32.d
> +++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-zero-32.d
> @@ -1,8 +1,8 @@
> -#as: -march=rv32ic
> -#source: dis-addr-topaddr.s
> +#as: -march=rv32i -defsym XLEN=32
> +#source: dis-addr-topaddr-zero.s
> #objdump: -d
>
> -.*: file format elf32-(little|big)riscv
> +.*:[ ]+file format .*
>
>
> Disassembly of section .text:
> diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-64.d b/gas/testsuite/gas/riscv/dis-addr-topaddr-zero-64.d
> similarity index 58%
> rename from gas/testsuite/gas/riscv/dis-addr-topaddr-64.d
> rename to gas/testsuite/gas/riscv/dis-addr-topaddr-zero-64.d
> index 38f67efdcaf..9b2d170d3d6 100644
> --- a/gas/testsuite/gas/riscv/dis-addr-topaddr-64.d
> +++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-zero-64.d
> @@ -1,8 +1,8 @@
> -#as: -march=rv64ic -defsym rv64=1
> -#source: dis-addr-topaddr.s
> +#as: -march=rv64i -defsym XLEN=64
> +#source: dis-addr-topaddr-zero.s
> #objdump: -d
>
> -.*: file format elf64-(little|big)riscv
> +.*:[ ]+file format .*
>
>
> Disassembly of section .text:
> diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr-zero.s b/gas/testsuite/gas/riscv/dis-addr-topaddr-zero.s
> new file mode 100644
> index 00000000000..cdf44b5403b
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/dis-addr-topaddr-zero.s
> @@ -0,0 +1,11 @@
> +.ifge XLEN-64
> +.set topbase, 0xffffffff00000000
> +.else
> +.set topbase, 0
> +.endif
> +
> +.set addr_top, topbase + 0xffffffff # -1
> +
> +target:
> + # Use address relative to zero
> + lb t0, -1(zero)
> diff --git a/gas/testsuite/gas/riscv/dis-addr-topaddr.s b/gas/testsuite/gas/riscv/dis-addr-topaddr.s
> deleted file mode 100644
> index b66587f448d..00000000000
> --- a/gas/testsuite/gas/riscv/dis-addr-topaddr.s
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -.ifdef rv64
> -topbase = 0xffffffff00000000
> -.else
> -topbase = 0
> -.endif
> -
> -.set addr_top, topbase + 0xffffffff # -1
> -
> -target:
> - lb t0, -1(zero)
> --
> 2.37.2
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 03/12] RISC-V: Tidying related to 'Zfinx' disassembler test
2022-11-05 12:29 ` [PATCH 03/12] RISC-V: Tidying related to 'Zfinx' disassembler test Tsukasa OI
@ 2022-11-29 7:50 ` Nelson Chu
0 siblings, 0 replies; 26+ messages in thread
From: Nelson Chu @ 2022-11-29 7:50 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Kito Cheng, Palmer Dabbelt, binutils
Okay, thanks.
Nelson
On Sat, Nov 5, 2022 at 8:29 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> This commit makes some tidying to zfinx-dis-numeric.d.
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/zfinx-dis-numeric.d: Minimize extension
> requirements. Remove redundant source line. Make test pattern
> stricter. Remove -r from objdump options.
> ---
> gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.d b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d
> index ba3f62295eb..1c61d61f8f3 100644
> --- a/gas/testsuite/gas/riscv/zfinx-dis-numeric.d
> +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d
> @@ -1,10 +1,9 @@
> -#as: -march=rv64ima_zfinx
> -#source: zfinx-dis-numeric.s
> -#objdump: -dr -Mnumeric
> +#as: -march=rv32i_zfinx
> +#objdump: -d -M numeric
>
> .*:[ ]+file format .*
>
> Disassembly of section .text:
>
> 0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+a0c5a553[ ]+feq.s[ ]+x10,x11,x12
> +[ ]+[0-9a-f]+:[ ]+a0c5a553[ ]+feq\.s[ ]+x10,x11,x12
> --
> 2.37.2
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 04/12] RISC-V: GAS: Add basic shared test utilities
2022-11-05 12:29 ` [PATCH 04/12] RISC-V: GAS: Add basic shared test utilities Tsukasa OI
@ 2022-11-29 7:53 ` Nelson Chu
0 siblings, 0 replies; 26+ messages in thread
From: Nelson Chu @ 2022-11-29 7:53 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Kito Cheng, Palmer Dabbelt, binutils
I disagree with this change. This make testcase too complicated.
Besides, I also don't prefer to add something only used for future
purposes. Just add the stuff when we really need it.
Nelson
On Sat, Nov 5, 2022 at 8:30 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> This commit adds basic shared test utilities intended for future
> extension tests.
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/testutils.inc: New test utilities.
> ---
> gas/testsuite/gas/riscv/testutils.inc | 113 ++++++++++++++++++++++++++
> 1 file changed, 113 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/testutils.inc
>
> diff --git a/gas/testsuite/gas/riscv/testutils.inc b/gas/testsuite/gas/riscv/testutils.inc
> new file mode 100644
> index 00000000000..009484eefed
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/testutils.inc
> @@ -0,0 +1,113 @@
> +# Set NOARCH symbols.
> +.ifndef NOARCH
> +.set NOARCH, 0
> +.endif
> +.ifndef NOARCH_ARCH
> +.set NOARCH_ARCH, 0
> +.endif
> +.ifndef NOARCH_XLEN
> +.set NOARCH_XLEN, 0
> +.endif
> +.if NOARCH
> +.set NOARCH_ARCH, 1
> +.set NOARCH_XLEN, 1
> +.endif
> +
> +# Update XLEN constraint symbols.
> +# For intentional error handling tests, .if SYM ... .endif block should be
> +# used to test those varibales.
> +.macro UPDATE_XLEN
> + .if NOARCH_XLEN
> + # When NOARCH_XLEN is set,
> + # set those variables to "invalid" 1 to generate errors.
> + .set XLEN_EQ_32, 1
> + .set XLEN_EQ_64, 1
> + .set XLEN_GE_64, 1
> + .else
> + # Set symbol values depending on the XLEN.
> + .ifdef XLEN
> + .ifeq XLEN-32
> + .set XLEN_EQ_32, 1
> + .else
> + .set XLEN_EQ_32, 0
> + .endif
> + .ifeq XLEN-64
> + .set XLEN_EQ_64, 1
> + .else
> + .set XLEN_EQ_64, 0
> + .endif
> + .ifge XLEN-64
> + .set XLEN_GE_64, 1
> + .else
> + .set XLEN_GE_64, 0
> + .endif
> + .else
> + .set XLEN_EQ_32, 0
> + .set XLEN_EQ_64, 0
> + .set XLEN_GE_64, 0
> + .endif
> + .endif
> +.endm
> +UPDATE_XLEN
> +
> +# Set the base architecture.
> +.macro SET_BASE_FORCE xlen, basearch=i
> + .option arch, rv\xlen\basearch
> + .set XLEN, \xlen
> + UPDATE_XLEN
> +.endm
> +
> +# Set the base architecture unless the symbol NOARCH_ARCH is set.
> +.macro SET_BASE xlen, basearch=i
> + .if !NOARCH_ARCH
> + SET_BASE_FORCE \xlen, \basearch
> + .endif
> +.endm
> +
> +# Begin base architecture block.
> +.macro SET_BASE_START_FORCE xlen, basearch=i
> + .option push
> + SET_BASE_FORCE \xlen, \basearch
> +.endm
> +
> +# Begin base architecture block.
> +# Don't change the architecture if NOARCH_ARCH is set.
> +.macro SET_BASE_START xlen, basearch=i
> + .option push
> + SET_BASE \xlen, \basearch
> +.endm
> +
> +# End base architecture block.
> +.macro SET_BASE_END
> + .option pop
> +.endm
> +
> +# Set the architecture.
> +.macro SET_ARCH_FORCE arch
> + .option arch, \arch
> +.endm
> +
> +# Set the architecture unless the symbol NOARCH_ARCH is set.
> +.macro SET_ARCH arch
> + .ifeq NOARCH_ARCH-0
> + SET_ARCH_FORCE \arch
> + .endif
> +.endm
> +
> +# Begin architecture block.
> +.macro SET_ARCH_START_FORCE arch
> + .option push
> + SET_ARCH_FORCE \arch
> +.endm
> +
> +# Begin architecture block.
> +# Don't change the architecture if NOARCH_ARCH is set.
> +.macro SET_ARCH_START arch
> + .option push
> + SET_ARCH \arch
> +.endm
> +
> +# End architecture block.
> +.macro SET_ARCH_END
> + .option pop
> +.endm
> --
> 2.37.2
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 05/12] RISC-V: Redefine "nop" test
2022-11-05 12:29 ` [PATCH 05/12] RISC-V: Redefine "nop" test Tsukasa OI
@ 2022-11-29 7:58 ` Nelson Chu
0 siblings, 0 replies; 26+ messages in thread
From: Nelson Chu @ 2022-11-29 7:58 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Kito Cheng, Palmer Dabbelt, binutils
On Sat, Nov 5, 2022 at 8:30 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> Seemingly, t_insns.[sd] was the first GAS test for RISC-V. This commit
> redefines this test as a template of the new testing utility for
> "nop" and "c.nop".
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/nop.s: New test.
> * testsuite/gas/riscv/nop.d: New test.
> * testsuite/gas/riscv/nop-noalias.d: New test.
> * testsuite/gas/riscv/nop-noarch.d: New failure test.
> * testsuite/gas/riscv/nop-noarch.l: Likewise.
> * testsuite/gas/riscv/t_insns.d: Removed.
> * testsuite/gas/riscv/t_insns.s: Removed.
> ---
> gas/testsuite/gas/riscv/nop-noalias.d | 13 +++++++++++++
> gas/testsuite/gas/riscv/nop-noarch.d | 3 +++
> gas/testsuite/gas/riscv/nop-noarch.l | 2 ++
> gas/testsuite/gas/riscv/nop.d | 12 ++++++++++++
> gas/testsuite/gas/riscv/nop.s | 9 +++++++++
> gas/testsuite/gas/riscv/t_insns.d | 10 ----------
> gas/testsuite/gas/riscv/t_insns.s | 2 --
> 7 files changed, 39 insertions(+), 12 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/nop-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/nop-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/nop-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/nop.d
> create mode 100644 gas/testsuite/gas/riscv/nop.s
> delete mode 100644 gas/testsuite/gas/riscv/t_insns.d
> delete mode 100644 gas/testsuite/gas/riscv/t_insns.s
>
> diff --git a/gas/testsuite/gas/riscv/nop-noalias.d b/gas/testsuite/gas/riscv/nop-noalias.d
> new file mode 100644
> index 00000000000..8dca3c8e01f
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/nop-noalias.d
> @@ -0,0 +1,13 @@
> +#as: -march=rv32i -I$srcdir/$subdir
> +#source: nop.s
> +#objdump: -d -M no-aliases
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+00000013[ ]+addi[ ]+zero,zero,0
> +[ ]+[0-9a-f]+:[ ]+0001[ ]+c\.addi[ ]+zero,0
> +[ ]+[0-9a-f]+:[ ]+0001[ ]+c\.addi[ ]+zero,0
> diff --git a/gas/testsuite/gas/riscv/nop-noarch.d b/gas/testsuite/gas/riscv/nop-noarch.d
> new file mode 100644
> index 00000000000..d3fe5dc763e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/nop-noarch.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i -I$srcdir/$subdir -defsym NOARCH=1
> +#source: nop.s
> +#error_output: nop-noarch.l
> diff --git a/gas/testsuite/gas/riscv/nop-noarch.l b/gas/testsuite/gas/riscv/nop-noarch.l
> new file mode 100644
> index 00000000000..4e418e1291d
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/nop-noarch.l
> @@ -0,0 +1,2 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `c\.nop', extension `c' required
> diff --git a/gas/testsuite/gas/riscv/nop.d b/gas/testsuite/gas/riscv/nop.d
> new file mode 100644
> index 00000000000..19b5fc13b55
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/nop.d
> @@ -0,0 +1,12 @@
> +#as: -march=rv32i -I$srcdir/$subdir
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+00000013[ ]+nop
> +[ ]+[0-9a-f]+:[ ]+0001[ ]+nop
> +[ ]+[0-9a-f]+:[ ]+0001[ ]+nop
> diff --git a/gas/testsuite/gas/riscv/nop.s b/gas/testsuite/gas/riscv/nop.s
> new file mode 100644
> index 00000000000..1a2dd75f3b1
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/nop.s
> @@ -0,0 +1,9 @@
> +.include "testutils.inc"
> +
> +target:
> + nop
> + # Architecture block: change disabled when NOARCH is defined.
> + SET_ARCH_START +c
> + nop
> + c.nop
> + SET_ARCH_END
It should be the ".option arch, +c", so that's why I don't agree with
the related changes. Please make the test cases simple and don't make
them too complicated.
> diff --git a/gas/testsuite/gas/riscv/t_insns.d b/gas/testsuite/gas/riscv/t_insns.d
> deleted file mode 100644
> index 720f0db2930..00000000000
> --- a/gas/testsuite/gas/riscv/t_insns.d
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -#as:
> -#objdump: -dr
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+0:[ ]+00000013[ ]+nop
> diff --git a/gas/testsuite/gas/riscv/t_insns.s b/gas/testsuite/gas/riscv/t_insns.s
> deleted file mode 100644
> index 99456883315..00000000000
> --- a/gas/testsuite/gas/riscv/t_insns.s
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -target:
> - nop
> --
I prefer to keep the old one.
Nelson
> 2.37.2
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 06/12] RISC-V: Reorganize/enhance {sign,zero}-extension instructions
2022-11-05 12:29 ` [PATCH 06/12] RISC-V: Reorganize/enhance {sign,zero}-extension instructions Tsukasa OI
@ 2022-11-29 8:10 ` Nelson Chu
0 siblings, 0 replies; 26+ messages in thread
From: Nelson Chu @ 2022-11-29 8:10 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Kito Cheng, Palmer Dabbelt, binutils
This is not what I expected... What I expect is that we just have a
.s file for those instructions, and then just use ".option arch" to
generate the mapping symbols to let dis-assembler dumps the right
things. Although you may think that rv32 and rv64 in the same file
looks weird, but according to the purpose of the .option arch, this
should be allowed, so... From my side, you are not tidying the test
cases, defining lots of symbols by -defsym and macros by *.inc file
make things more complicated. What I worry is that except you, it's
too complicated for others to add test cases, so your new rules aren't
convenient, it not only increases the difficulty for everyone to
develop, but also increases the cost of maintenance... So again, I
disagree and suggest not to add these kinds of support.
Nelson
On Sat, Nov 5, 2022 at 8:30 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> This commit:
>
> - Clarifies the roles of {sign,zero}-extension instruction tests,
> - Shortens ".s" file using macro,
> - Enhances the tests with 'Zba' and 'Zbb' extensions and
> - Makes some tidying (e.g. making matching patterns stricter).
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/ext-insn.s: Reorganize based on ext.s.
> * testsuite/gas/riscv/ext-insn-32-noalias.d: Based on ext-32.d.
> Make matching pattern stricter.
> * testsuite/gas/riscv/ext-insn-64-noalias.d: Based on ext-64.d.
> Make matching pattern stricter.
> * testsuite/gas/riscv/ext-insn-32-noarch.d: New failure test.
> * testsuite/gas/riscv/ext-insn-32-noarch.l: Likewise.
> * testsuite/gas/riscv/ext-insn-64-noarch.d: New test to make sure
> that NOARCH=1 does not make errors since all opcodes are valid.
> * testsuite/gas/riscv/ext-insn-zba-32-noalias.d: Test with 'Zba'.
> * testsuite/gas/riscv/ext-insn-zba-64-noalias.d: Likewise.
> * testsuite/gas/riscv/ext-insn-zbb-32-noalias.d: Test with 'Zbb'.
> * testsuite/gas/riscv/ext-insn-zbb-64-noalias.d: Likewise.
> * testsuite/gas/riscv/ext.s: Removed.
> * testsuite/gas/riscv/ext-32.d: Removed.
> * testsuite/gas/riscv/ext-64.d: Removed.
> ---
> gas/testsuite/gas/riscv/ext-32.d | 39 --------------
> gas/testsuite/gas/riscv/ext-64.d | 51 -------------------
> gas/testsuite/gas/riscv/ext-insn-32-noalias.d | 39 ++++++++++++++
> gas/testsuite/gas/riscv/ext-insn-32-noarch.d | 3 ++
> gas/testsuite/gas/riscv/ext-insn-32-noarch.l | 9 ++++
> gas/testsuite/gas/riscv/ext-insn-64-noalias.d | 51 +++++++++++++++++++
> gas/testsuite/gas/riscv/ext-insn-64-noarch.d | 5 ++
> .../gas/riscv/ext-insn-zba-32-noalias.d | 39 ++++++++++++++
> .../gas/riscv/ext-insn-zba-64-noalias.d | 47 +++++++++++++++++
> .../gas/riscv/ext-insn-zbb-32-noalias.d | 27 ++++++++++
> .../gas/riscv/ext-insn-zbb-64-noalias.d | 39 ++++++++++++++
> gas/testsuite/gas/riscv/ext-insn.s | 23 +++++++++
> gas/testsuite/gas/riscv/ext.s | 38 --------------
> 13 files changed, 282 insertions(+), 128 deletions(-)
> delete mode 100644 gas/testsuite/gas/riscv/ext-32.d
> delete mode 100644 gas/testsuite/gas/riscv/ext-64.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-32-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-32-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-32-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-64-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-64-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-zba-32-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-zba-64-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-zbb-32-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn-zbb-64-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/ext-insn.s
> delete mode 100644 gas/testsuite/gas/riscv/ext.s
>
> diff --git a/gas/testsuite/gas/riscv/ext-32.d b/gas/testsuite/gas/riscv/ext-32.d
> deleted file mode 100644
> index 97daa31d0e9..00000000000
> --- a/gas/testsuite/gas/riscv/ext-32.d
> +++ /dev/null
> @@ -1,39 +0,0 @@
> -#as: -march=rv32i
> -#source: ext.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+0:[ ]+0ff57513[ ]+zext.b[ ]+a0,a0
> -[ ]+4:[ ]+01051513[ ]+sll[ ]+a0,a0,0x10
> -[ ]+8:[ ]+01055513[ ]+srl[ ]+a0,a0,0x10
> -[ ]+c:[ ]+01851513[ ]+sll[ ]+a0,a0,0x18
> -[ ]+10:[ ]+41855513[ ]+sra[ ]+a0,a0,0x18
> -[ ]+14:[ ]+01051513[ ]+sll[ ]+a0,a0,0x10
> -[ ]+18:[ ]+41055513[ ]+sra[ ]+a0,a0,0x10
> -[ ]+1c:[ ]+0ff67593[ ]+zext.b[ ]+a1,a2
> -[ ]+20:[ ]+01061593[ ]+sll[ ]+a1,a2,0x10
> -[ ]+24:[ ]+0105d593[ ]+srl[ ]+a1,a1,0x10
> -[ ]+28:[ ]+01861593[ ]+sll[ ]+a1,a2,0x18
> -[ ]+2c:[ ]+4185d593[ ]+sra[ ]+a1,a1,0x18
> -[ ]+30:[ ]+01061593[ ]+sll[ ]+a1,a2,0x10
> -[ ]+34:[ ]+4105d593[ ]+sra[ ]+a1,a1,0x10
> -[ ]+38:[ ]+0ff57513[ ]+zext.b[ ]+a0,a0
> -[ ]+3c:[ ]+0542[ ]+sll[ ]+a0,a0,0x10
> -[ ]+3e:[ ]+8141[ ]+srl[ ]+a0,a0,0x10
> -[ ]+40:[ ]+0562[ ]+sll[ ]+a0,a0,0x18
> -[ ]+42:[ ]+8561[ ]+sra[ ]+a0,a0,0x18
> -[ ]+44:[ ]+0542[ ]+sll[ ]+a0,a0,0x10
> -[ ]+46:[ ]+8541[ ]+sra[ ]+a0,a0,0x10
> -[ ]+48:[ ]+0ff67593[ ]+zext.b[ ]+a1,a2
> -[ ]+4c:[ ]+01061593[ ]+sll[ ]+a1,a2,0x10
> -[ ]+50:[ ]+81c1[ ]+srl[ ]+a1,a1,0x10
> -[ ]+52:[ ]+01861593[ ]+sll[ ]+a1,a2,0x18
> -[ ]+56:[ ]+85e1[ ]+sra[ ]+a1,a1,0x18
> -[ ]+58:[ ]+01061593[ ]+sll[ ]+a1,a2,0x10
> -[ ]+5c:[ ]+85c1[ ]+sra[ ]+a1,a1,0x10
> -#...
> diff --git a/gas/testsuite/gas/riscv/ext-64.d b/gas/testsuite/gas/riscv/ext-64.d
> deleted file mode 100644
> index 1fe339c4af4..00000000000
> --- a/gas/testsuite/gas/riscv/ext-64.d
> +++ /dev/null
> @@ -1,51 +0,0 @@
> -#as: -march=rv64i -defsym __64_bit__=1
> -#source: ext.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+0:[ ]+0ff57513[ ]+zext.b[ ]+a0,a0
> -[ ]+4:[ ]+03051513[ ]+sll[ ]+a0,a0,0x30
> -[ ]+8:[ ]+03055513[ ]+srl[ ]+a0,a0,0x30
> -[ ]+c:[ ]+03851513[ ]+sll[ ]+a0,a0,0x38
> -[ ]+10:[ ]+43855513[ ]+sra[ ]+a0,a0,0x38
> -[ ]+14:[ ]+03051513[ ]+sll[ ]+a0,a0,0x30
> -[ ]+18:[ ]+43055513[ ]+sra[ ]+a0,a0,0x30
> -[ ]+1c:[ ]+0ff67593[ ]+zext.b[ ]+a1,a2
> -[ ]+20:[ ]+03061593[ ]+sll[ ]+a1,a2,0x30
> -[ ]+24:[ ]+0305d593[ ]+srl[ ]+a1,a1,0x30
> -[ ]+28:[ ]+03861593[ ]+sll[ ]+a1,a2,0x38
> -[ ]+2c:[ ]+4385d593[ ]+sra[ ]+a1,a1,0x38
> -[ ]+30:[ ]+03061593[ ]+sll[ ]+a1,a2,0x30
> -[ ]+34:[ ]+4305d593[ ]+sra[ ]+a1,a1,0x30
> -[ ]+38:[ ]+02051513[ ]+sll[ ]+a0,a0,0x20
> -[ ]+3c:[ ]+02055513[ ]+srl[ ]+a0,a0,0x20
> -[ ]+40:[ ]+0005051b[ ]+sext.w[ ]+a0,a0
> -[ ]+44:[ ]+02061593[ ]+sll[ ]+a1,a2,0x20
> -[ ]+48:[ ]+0205d593[ ]+srl[ ]+a1,a1,0x20
> -[ ]+4c:[ ]+0006059b[ ]+sext.w[ ]+a1,a2
> -[ ]+50:[ ]+0ff57513[ ]+zext.b[ ]+a0,a0
> -[ ]+54:[ ]+1542[ ]+sll[ ]+a0,a0,0x30
> -[ ]+56:[ ]+9141[ ]+srl[ ]+a0,a0,0x30
> -[ ]+58:[ ]+1562[ ]+sll[ ]+a0,a0,0x38
> -[ ]+5a:[ ]+9561[ ]+sra[ ]+a0,a0,0x38
> -[ ]+5c:[ ]+1542[ ]+sll[ ]+a0,a0,0x30
> -[ ]+5e:[ ]+9541[ ]+sra[ ]+a0,a0,0x30
> -[ ]+60:[ ]+0ff67593[ ]+zext.b[ ]+a1,a2
> -[ ]+64:[ ]+03061593[ ]+sll[ ]+a1,a2,0x30
> -[ ]+68:[ ]+91c1[ ]+srl[ ]+a1,a1,0x30
> -[ ]+6a:[ ]+03861593[ ]+sll[ ]+a1,a2,0x38
> -[ ]+6e:[ ]+95e1[ ]+sra[ ]+a1,a1,0x38
> -[ ]+70:[ ]+03061593[ ]+sll[ ]+a1,a2,0x30
> -[ ]+74:[ ]+95c1[ ]+sra[ ]+a1,a1,0x30
> -[ ]+76:[ ]+1502[ ]+sll[ ]+a0,a0,0x20
> -[ ]+78:[ ]+9101[ ]+srl[ ]+a0,a0,0x20
> -[ ]+7a:[ ]+2501[ ]+sext.w[ ]+a0,a0
> -[ ]+7c:[ ]+02061593[ ]+sll[ ]+a1,a2,0x20
> -[ ]+80:[ ]+9181[ ]+srl[ ]+a1,a1,0x20
> -[ ]+82:[ ]+0006059b[ ]+sext.w[ ]+a1,a2
> -#...
> diff --git a/gas/testsuite/gas/riscv/ext-insn-32-noalias.d b/gas/testsuite/gas/riscv/ext-insn-32-noalias.d
> new file mode 100644
> index 00000000000..237fcf033d0
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn-32-noalias.d
> @@ -0,0 +1,39 @@
> +#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32
> +#source: ext-insn.s
> +#objdump: -d -M no-aliases
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+01051513[ ]+slli[ ]+a0,a0,0x10
> +[ ]+[0-9a-f]+:[ ]+01055513[ ]+srli[ ]+a0,a0,0x10
> +[ ]+[0-9a-f]+:[ ]+01851513[ ]+slli[ ]+a0,a0,0x18
> +[ ]+[0-9a-f]+:[ ]+41855513[ ]+srai[ ]+a0,a0,0x18
> +[ ]+[0-9a-f]+:[ ]+01051513[ ]+slli[ ]+a0,a0,0x10
> +[ ]+[0-9a-f]+:[ ]+41055513[ ]+srai[ ]+a0,a0,0x10
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
> +[ ]+[0-9a-f]+:[ ]+0105d593[ ]+srli[ ]+a1,a1,0x10
> +[ ]+[0-9a-f]+:[ ]+01861593[ ]+slli[ ]+a1,a2,0x18
> +[ ]+[0-9a-f]+:[ ]+4185d593[ ]+srai[ ]+a1,a1,0x18
> +[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
> +[ ]+[0-9a-f]+:[ ]+4105d593[ ]+srai[ ]+a1,a1,0x10
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+0542[ ]+c\.slli[ ]+a0,0x10
> +[ ]+[0-9a-f]+:[ ]+8141[ ]+c\.srli[ ]+a0,0x10
> +[ ]+[0-9a-f]+:[ ]+0562[ ]+c\.slli[ ]+a0,0x18
> +[ ]+[0-9a-f]+:[ ]+8561[ ]+c\.srai[ ]+a0,0x18
> +[ ]+[0-9a-f]+:[ ]+0542[ ]+c\.slli[ ]+a0,0x10
> +[ ]+[0-9a-f]+:[ ]+8541[ ]+c\.srai[ ]+a0,0x10
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
> +[ ]+[0-9a-f]+:[ ]+81c1[ ]+c\.srli[ ]+a1,0x10
> +[ ]+[0-9a-f]+:[ ]+01861593[ ]+slli[ ]+a1,a2,0x18
> +[ ]+[0-9a-f]+:[ ]+85e1[ ]+c\.srai[ ]+a1,0x18
> +[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
> +[ ]+[0-9a-f]+:[ ]+85c1[ ]+c\.srai[ ]+a1,0x10
> +#...
> diff --git a/gas/testsuite/gas/riscv/ext-insn-32-noarch.d b/gas/testsuite/gas/riscv/ext-insn-32-noarch.d
> new file mode 100644
> index 00000000000..7a2f4ddfec2
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn-32-noarch.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32 -defsym NOARCH=1
> +#source: ext-insn.s
> +#error_output: ext-insn-32-noarch.l
> diff --git a/gas/testsuite/gas/riscv/ext-insn-32-noarch.l b/gas/testsuite/gas/riscv/ext-insn-32-noarch.l
> new file mode 100644
> index 00000000000..f5954f207f0
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn-32-noarch.l
> @@ -0,0 +1,9 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `zext.w a0,a0'
> +.*: Error: unrecognized opcode `sext.w a0,a0'
> +.*: Error: unrecognized opcode `zext.w a1,a2'
> +.*: Error: unrecognized opcode `sext.w a1,a2'
> +.*: Error: unrecognized opcode `zext.w a0,a0'
> +.*: Error: unrecognized opcode `sext.w a0,a0'
> +.*: Error: unrecognized opcode `zext.w a1,a2'
> +.*: Error: unrecognized opcode `sext.w a1,a2'
> diff --git a/gas/testsuite/gas/riscv/ext-insn-64-noalias.d b/gas/testsuite/gas/riscv/ext-insn-64-noalias.d
> new file mode 100644
> index 00000000000..9a273eea0d7
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn-64-noalias.d
> @@ -0,0 +1,51 @@
> +#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64
> +#source: ext-insn.s
> +#objdump: -d -M no-aliases
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+03051513[ ]+slli[ ]+a0,a0,0x30
> +[ ]+[0-9a-f]+:[ ]+03055513[ ]+srli[ ]+a0,a0,0x30
> +[ ]+[0-9a-f]+:[ ]+03851513[ ]+slli[ ]+a0,a0,0x38
> +[ ]+[0-9a-f]+:[ ]+43855513[ ]+srai[ ]+a0,a0,0x38
> +[ ]+[0-9a-f]+:[ ]+03051513[ ]+slli[ ]+a0,a0,0x30
> +[ ]+[0-9a-f]+:[ ]+43055513[ ]+srai[ ]+a0,a0,0x30
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
> +[ ]+[0-9a-f]+:[ ]+0305d593[ ]+srli[ ]+a1,a1,0x30
> +[ ]+[0-9a-f]+:[ ]+03861593[ ]+slli[ ]+a1,a2,0x38
> +[ ]+[0-9a-f]+:[ ]+4385d593[ ]+srai[ ]+a1,a1,0x38
> +[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
> +[ ]+[0-9a-f]+:[ ]+4305d593[ ]+srai[ ]+a1,a1,0x30
> +[ ]+[0-9a-f]+:[ ]+02051513[ ]+slli[ ]+a0,a0,0x20
> +[ ]+[0-9a-f]+:[ ]+02055513[ ]+srli[ ]+a0,a0,0x20
> +[ ]+[0-9a-f]+:[ ]+0005051b[ ]+addiw[ ]+a0,a0,0
> +[ ]+[0-9a-f]+:[ ]+02061593[ ]+slli[ ]+a1,a2,0x20
> +[ ]+[0-9a-f]+:[ ]+0205d593[ ]+srli[ ]+a1,a1,0x20
> +[ ]+[0-9a-f]+:[ ]+0006059b[ ]+addiw[ ]+a1,a2,0
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+1542[ ]+c\.slli[ ]+a0,0x30
> +[ ]+[0-9a-f]+:[ ]+9141[ ]+c\.srli[ ]+a0,0x30
> +[ ]+[0-9a-f]+:[ ]+1562[ ]+c\.slli[ ]+a0,0x38
> +[ ]+[0-9a-f]+:[ ]+9561[ ]+c\.srai[ ]+a0,0x38
> +[ ]+[0-9a-f]+:[ ]+1542[ ]+c\.slli[ ]+a0,0x30
> +[ ]+[0-9a-f]+:[ ]+9541[ ]+c\.srai[ ]+a0,0x30
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
> +[ ]+[0-9a-f]+:[ ]+91c1[ ]+c\.srli[ ]+a1,0x30
> +[ ]+[0-9a-f]+:[ ]+03861593[ ]+slli[ ]+a1,a2,0x38
> +[ ]+[0-9a-f]+:[ ]+95e1[ ]+c\.srai[ ]+a1,0x38
> +[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
> +[ ]+[0-9a-f]+:[ ]+95c1[ ]+c\.srai[ ]+a1,0x30
> +[ ]+[0-9a-f]+:[ ]+1502[ ]+c\.slli[ ]+a0,0x20
> +[ ]+[0-9a-f]+:[ ]+9101[ ]+c\.srli[ ]+a0,0x20
> +[ ]+[0-9a-f]+:[ ]+2501[ ]+c\.addiw[ ]+a0,0
> +[ ]+[0-9a-f]+:[ ]+02061593[ ]+slli[ ]+a1,a2,0x20
> +[ ]+[0-9a-f]+:[ ]+9181[ ]+c\.srli[ ]+a1,0x20
> +[ ]+[0-9a-f]+:[ ]+0006059b[ ]+addiw[ ]+a1,a2,0
> +#...
> diff --git a/gas/testsuite/gas/riscv/ext-insn-64-noarch.d b/gas/testsuite/gas/riscv/ext-insn-64-noarch.d
> new file mode 100644
> index 00000000000..6061373bb71
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn-64-noarch.d
> @@ -0,0 +1,5 @@
> +#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64 -defsym NOARCH=1
> +#source: ext-insn.s
> +#objdump: -d -M no-aliases
> +
> +#...
> diff --git a/gas/testsuite/gas/riscv/ext-insn-zba-32-noalias.d b/gas/testsuite/gas/riscv/ext-insn-zba-32-noalias.d
> new file mode 100644
> index 00000000000..ccea949debc
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn-zba-32-noalias.d
> @@ -0,0 +1,39 @@
> +#as: -march=rv32i_zba -I$srcdir/$subdir -defsym XLEN=32
> +#source: ext-insn.s
> +#objdump: -d -M no-aliases
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+01051513[ ]+slli[ ]+a0,a0,0x10
> +[ ]+[0-9a-f]+:[ ]+01055513[ ]+srli[ ]+a0,a0,0x10
> +[ ]+[0-9a-f]+:[ ]+01851513[ ]+slli[ ]+a0,a0,0x18
> +[ ]+[0-9a-f]+:[ ]+41855513[ ]+srai[ ]+a0,a0,0x18
> +[ ]+[0-9a-f]+:[ ]+01051513[ ]+slli[ ]+a0,a0,0x10
> +[ ]+[0-9a-f]+:[ ]+41055513[ ]+srai[ ]+a0,a0,0x10
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
> +[ ]+[0-9a-f]+:[ ]+0105d593[ ]+srli[ ]+a1,a1,0x10
> +[ ]+[0-9a-f]+:[ ]+01861593[ ]+slli[ ]+a1,a2,0x18
> +[ ]+[0-9a-f]+:[ ]+4185d593[ ]+srai[ ]+a1,a1,0x18
> +[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
> +[ ]+[0-9a-f]+:[ ]+4105d593[ ]+srai[ ]+a1,a1,0x10
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+0542[ ]+c\.slli[ ]+a0,0x10
> +[ ]+[0-9a-f]+:[ ]+8141[ ]+c\.srli[ ]+a0,0x10
> +[ ]+[0-9a-f]+:[ ]+0562[ ]+c\.slli[ ]+a0,0x18
> +[ ]+[0-9a-f]+:[ ]+8561[ ]+c\.srai[ ]+a0,0x18
> +[ ]+[0-9a-f]+:[ ]+0542[ ]+c\.slli[ ]+a0,0x10
> +[ ]+[0-9a-f]+:[ ]+8541[ ]+c\.srai[ ]+a0,0x10
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
> +[ ]+[0-9a-f]+:[ ]+81c1[ ]+c\.srli[ ]+a1,0x10
> +[ ]+[0-9a-f]+:[ ]+01861593[ ]+slli[ ]+a1,a2,0x18
> +[ ]+[0-9a-f]+:[ ]+85e1[ ]+c\.srai[ ]+a1,0x18
> +[ ]+[0-9a-f]+:[ ]+01061593[ ]+slli[ ]+a1,a2,0x10
> +[ ]+[0-9a-f]+:[ ]+85c1[ ]+c\.srai[ ]+a1,0x10
> +#...
> diff --git a/gas/testsuite/gas/riscv/ext-insn-zba-64-noalias.d b/gas/testsuite/gas/riscv/ext-insn-zba-64-noalias.d
> new file mode 100644
> index 00000000000..a9e191a7449
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn-zba-64-noalias.d
> @@ -0,0 +1,47 @@
> +#as: -march=rv64i_zba -I$srcdir/$subdir -defsym XLEN=64
> +#source: ext-insn.s
> +#objdump: -d -M no-aliases
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+03051513[ ]+slli[ ]+a0,a0,0x30
> +[ ]+[0-9a-f]+:[ ]+03055513[ ]+srli[ ]+a0,a0,0x30
> +[ ]+[0-9a-f]+:[ ]+03851513[ ]+slli[ ]+a0,a0,0x38
> +[ ]+[0-9a-f]+:[ ]+43855513[ ]+srai[ ]+a0,a0,0x38
> +[ ]+[0-9a-f]+:[ ]+03051513[ ]+slli[ ]+a0,a0,0x30
> +[ ]+[0-9a-f]+:[ ]+43055513[ ]+srai[ ]+a0,a0,0x30
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
> +[ ]+[0-9a-f]+:[ ]+0305d593[ ]+srli[ ]+a1,a1,0x30
> +[ ]+[0-9a-f]+:[ ]+03861593[ ]+slli[ ]+a1,a2,0x38
> +[ ]+[0-9a-f]+:[ ]+4385d593[ ]+srai[ ]+a1,a1,0x38
> +[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
> +[ ]+[0-9a-f]+:[ ]+4305d593[ ]+srai[ ]+a1,a1,0x30
> +[ ]+[0-9a-f]+:[ ]+0805053b[ ]+add\.uw[ ]+a0,a0,zero
> +[ ]+[0-9a-f]+:[ ]+0005051b[ ]+addiw[ ]+a0,a0,0
> +[ ]+[0-9a-f]+:[ ]+080605bb[ ]+add\.uw[ ]+a1,a2,zero
> +[ ]+[0-9a-f]+:[ ]+0006059b[ ]+addiw[ ]+a1,a2,0
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+1542[ ]+c\.slli[ ]+a0,0x30
> +[ ]+[0-9a-f]+:[ ]+9141[ ]+c\.srli[ ]+a0,0x30
> +[ ]+[0-9a-f]+:[ ]+1562[ ]+c\.slli[ ]+a0,0x38
> +[ ]+[0-9a-f]+:[ ]+9561[ ]+c\.srai[ ]+a0,0x38
> +[ ]+[0-9a-f]+:[ ]+1542[ ]+c\.slli[ ]+a0,0x30
> +[ ]+[0-9a-f]+:[ ]+9541[ ]+c\.srai[ ]+a0,0x30
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
> +[ ]+[0-9a-f]+:[ ]+91c1[ ]+c\.srli[ ]+a1,0x30
> +[ ]+[0-9a-f]+:[ ]+03861593[ ]+slli[ ]+a1,a2,0x38
> +[ ]+[0-9a-f]+:[ ]+95e1[ ]+c\.srai[ ]+a1,0x38
> +[ ]+[0-9a-f]+:[ ]+03061593[ ]+slli[ ]+a1,a2,0x30
> +[ ]+[0-9a-f]+:[ ]+95c1[ ]+c\.srai[ ]+a1,0x30
> +[ ]+[0-9a-f]+:[ ]+0805053b[ ]+add\.uw[ ]+a0,a0,zero
> +[ ]+[0-9a-f]+:[ ]+2501[ ]+c\.addiw[ ]+a0,0
> +[ ]+[0-9a-f]+:[ ]+080605bb[ ]+add\.uw[ ]+a1,a2,zero
> +[ ]+[0-9a-f]+:[ ]+0006059b[ ]+addiw[ ]+a1,a2,0
> +#...
> diff --git a/gas/testsuite/gas/riscv/ext-insn-zbb-32-noalias.d b/gas/testsuite/gas/riscv/ext-insn-zbb-32-noalias.d
> new file mode 100644
> index 00000000000..edb2dcde2cf
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn-zbb-32-noalias.d
> @@ -0,0 +1,27 @@
> +#as: -march=rv32i_zbb -I$srcdir/$subdir -defsym XLEN=32
> +#source: ext-insn.s
> +#objdump: -d -M no-aliases
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+08054533[ ]+zext\.h[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+60451513[ ]+sext\.b[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+60551513[ ]+sext\.h[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+080645b3[ ]+zext\.h[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+60461593[ ]+sext\.b[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+60561593[ ]+sext\.h[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+08054533[ ]+zext\.h[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+60451513[ ]+sext\.b[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+60551513[ ]+sext\.h[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+080645b3[ ]+zext\.h[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+60461593[ ]+sext\.b[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+60561593[ ]+sext\.h[ ]+a1,a2
> +#...
> diff --git a/gas/testsuite/gas/riscv/ext-insn-zbb-64-noalias.d b/gas/testsuite/gas/riscv/ext-insn-zbb-64-noalias.d
> new file mode 100644
> index 00000000000..bc7b6145e59
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn-zbb-64-noalias.d
> @@ -0,0 +1,39 @@
> +#as: -march=rv64i_zbb -I$srcdir/$subdir -defsym XLEN=64
> +#source: ext-insn.s
> +#objdump: -d -M no-aliases
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+0805453b[ ]+zext\.h[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+60451513[ ]+sext\.b[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+60551513[ ]+sext\.h[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+080645bb[ ]+zext\.h[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+60461593[ ]+sext\.b[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+60561593[ ]+sext\.h[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+02051513[ ]+slli[ ]+a0,a0,0x20
> +[ ]+[0-9a-f]+:[ ]+02055513[ ]+srli[ ]+a0,a0,0x20
> +[ ]+[0-9a-f]+:[ ]+0005051b[ ]+addiw[ ]+a0,a0,0
> +[ ]+[0-9a-f]+:[ ]+02061593[ ]+slli[ ]+a1,a2,0x20
> +[ ]+[0-9a-f]+:[ ]+0205d593[ ]+srli[ ]+a1,a1,0x20
> +[ ]+[0-9a-f]+:[ ]+0006059b[ ]+addiw[ ]+a1,a2,0
> +[ ]+[0-9a-f]+:[ ]+0ff57513[ ]+andi[ ]+a0,a0,255
> +[ ]+[0-9a-f]+:[ ]+0805453b[ ]+zext\.h[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+60451513[ ]+sext\.b[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+60551513[ ]+sext\.h[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+0ff67593[ ]+andi[ ]+a1,a2,255
> +[ ]+[0-9a-f]+:[ ]+080645bb[ ]+zext\.h[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+60461593[ ]+sext\.b[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+60561593[ ]+sext\.h[ ]+a1,a2
> +[ ]+[0-9a-f]+:[ ]+1502[ ]+c\.slli[ ]+a0,0x20
> +[ ]+[0-9a-f]+:[ ]+9101[ ]+c\.srli[ ]+a0,0x20
> +[ ]+[0-9a-f]+:[ ]+2501[ ]+c\.addiw[ ]+a0,0
> +[ ]+[0-9a-f]+:[ ]+02061593[ ]+slli[ ]+a1,a2,0x20
> +[ ]+[0-9a-f]+:[ ]+9181[ ]+c\.srli[ ]+a1,0x20
> +[ ]+[0-9a-f]+:[ ]+0006059b[ ]+addiw[ ]+a1,a2,0
> +#...
> diff --git a/gas/testsuite/gas/riscv/ext-insn.s b/gas/testsuite/gas/riscv/ext-insn.s
> new file mode 100644
> index 00000000000..2e4dc1ed850
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/ext-insn.s
> @@ -0,0 +1,23 @@
> +.include "testutils.inc"
> +
> +.macro INSN_SEQ
> + zext.b a0, a0 # andi (I)
> + zext.h a0, a0 # Zbb (RV32!=RV64) / shifts (I/C)
> + sext.b a0, a0 # Zbb / shifts (I/C)
> + sext.h a0, a0 # Zbb / shifts (I/C)
> + zext.b a1, a2 # andi (I)
> + zext.h a1, a2 # Zbb (RV32!=RV64) / shifts (I/C)
> + sext.b a1, a2 # Zbb / shifts (I/C)
> + sext.h a1, a2 # Zbb / shifts (I/C)
> +.if XLEN_GE_64
> + zext.w a0, a0 # add.uw (RV64_Zba) / shifts (I/C)
> + sext.w a0, a0 # addiw (I) / c.addiw (C)
> + zext.w a1, a2 # add.uw (RV64_Zba) / shifts (I/C)
> + sext.w a1, a2 # addiw (I/C)
> +.endif
> +.endm
> +
> +target:
> + INSN_SEQ
> + .option arch, +c
> + INSN_SEQ
> diff --git a/gas/testsuite/gas/riscv/ext.s b/gas/testsuite/gas/riscv/ext.s
> deleted file mode 100644
> index 0268dcafc1d..00000000000
> --- a/gas/testsuite/gas/riscv/ext.s
> +++ /dev/null
> @@ -1,38 +0,0 @@
> -target:
> - .option arch, -c
> - zext.b a0, a0
> - zext.h a0, a0
> - sext.b a0, a0
> - sext.h a0, a0
> -
> - zext.b a1, a2
> - zext.h a1, a2
> - sext.b a1, a2
> - sext.h a1, a2
> -
> -.ifdef __64_bit__
> - zext.w a0, a0
> - sext.w a0, a0
> -
> - zext.w a1, a2
> - sext.w a1, a2
> -.endif
> -
> - .option arch, +c
> - zext.b a0, a0
> - zext.h a0, a0
> - sext.b a0, a0
> - sext.h a0, a0
> -
> - zext.b a1, a2
> - zext.h a1, a2
> - sext.b a1, a2
> - sext.h a1, a2
> -
> -.ifdef __64_bit__
> - zext.w a0, a0
> - sext.w a0, a0
> -
> - zext.w a1, a2
> - sext.w a1, a2
> -.endif
> --
> 2.37.2
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 07/12] RISC-V: Combine complex extension error handling tests
2022-11-05 12:29 ` [PATCH 07/12] RISC-V: Combine complex extension error handling tests Tsukasa OI
@ 2022-11-29 8:16 ` Nelson Chu
0 siblings, 0 replies; 26+ messages in thread
From: Nelson Chu @ 2022-11-29 8:16 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Kito Cheng, Palmer Dabbelt, binutils
On Sat, Nov 5, 2022 at 8:30 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> Because mapping symbols with ISA string is now supported, we can now
> combine five complex "no required extensions" testcases related to
> the "fcvt.d.h" instruction into one.
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/zfhmin-d-noarch.s: Combined.
> * testsuite/gas/riscv/zfhmin-d-noarch.d: Likewise.
> Minimize extension requirements.
> * testsuite/gas/riscv/zfhmin-d-noarch.l: Likewise.
> Make matching pattern stricter.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail.s: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d: Removed.
> * testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l: Removed.
> ---
> .../gas/riscv/zfhmin-d-insn-class-fail-1.d | 3 ---
> .../gas/riscv/zfhmin-d-insn-class-fail-1.l | 2 --
> .../gas/riscv/zfhmin-d-insn-class-fail-2.d | 3 ---
> .../gas/riscv/zfhmin-d-insn-class-fail-2.l | 2 --
> .../gas/riscv/zfhmin-d-insn-class-fail-3.d | 3 ---
> .../gas/riscv/zfhmin-d-insn-class-fail-3.l | 2 --
> .../gas/riscv/zfhmin-d-insn-class-fail-4.d | 3 ---
> .../gas/riscv/zfhmin-d-insn-class-fail-4.l | 2 --
> .../gas/riscv/zfhmin-d-insn-class-fail-5.d | 3 ---
> .../gas/riscv/zfhmin-d-insn-class-fail-5.l | 2 --
> .../gas/riscv/zfhmin-d-insn-class-fail.s | 4 ---
> gas/testsuite/gas/riscv/zfhmin-d-noarch.d | 2 ++
> gas/testsuite/gas/riscv/zfhmin-d-noarch.l | 6 +++++
> gas/testsuite/gas/riscv/zfhmin-d-noarch.s | 25 +++++++++++++++++++
> 14 files changed, 33 insertions(+), 29 deletions(-)
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l
> delete mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s
> create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-noarch.s
>
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d
> deleted file mode 100644
> index 02a11943cf2..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv64i
> -#source: zfhmin-d-insn-class-fail.s
> -#error_output: zfhmin-d-insn-class-fail-1.l
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l
> deleted file mode 100644
> index 12f41a39ae0..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -.*: Assembler messages:
> -.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zfhmin' and `d', or `zhinxmin' and `zdinx' required
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d
> deleted file mode 100644
> index 27b5a12857e..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv64i_zhinxmin
> -#source: zfhmin-d-insn-class-fail.s
> -#error_output: zfhmin-d-insn-class-fail-2.l
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l
> deleted file mode 100644
> index 255f96cb5a1..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -.*: Assembler messages:
> -.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zdinx' required
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d
> deleted file mode 100644
> index 4f195bfa7c5..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv64i_zdinx
> -#source: zfhmin-d-insn-class-fail.s
> -#error_output: zfhmin-d-insn-class-fail-3.l
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l
> deleted file mode 100644
> index 7ff7b278fe3..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -.*: Assembler messages:
> -.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zhinxmin' required
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d
> deleted file mode 100644
> index 940d48c5dfd..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv64i_zfhmin
> -#source: zfhmin-d-insn-class-fail.s
> -#error_output: zfhmin-d-insn-class-fail-4.l
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l
> deleted file mode 100644
> index 2d58e4ce1ce..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -.*: Assembler messages:
> -.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `d' required
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d
> deleted file mode 100644
> index af26d5e9ea7..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv64id
> -#source: zfhmin-d-insn-class-fail.s
> -#error_output: zfhmin-d-insn-class-fail-5.l
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l
> deleted file mode 100644
> index 2fa6e8c754b..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -.*: Assembler messages:
> -.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zfhmin' required
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s
> deleted file mode 100644
> index 691d0a929dc..00000000000
> --- a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -# This test checks error message corresponding required extension(s).
> -# Operands are invalid on Zhinxmin+Zdinx but they are not parsed since
> -# extension test fails.
> -fcvt.d.h fa0, fa1
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-noarch.d b/gas/testsuite/gas/riscv/zfhmin-d-noarch.d
> new file mode 100644
> index 00000000000..fded578caea
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zfhmin-d-noarch.d
> @@ -0,0 +1,2 @@
> +#as: -march=rv64i -I$srcdir/$subdir
> +#error_output: zfhmin-d-noarch.l
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-noarch.l b/gas/testsuite/gas/riscv/zfhmin-d-noarch.l
> new file mode 100644
> index 00000000000..8a55ccaac2b
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zfhmin-d-noarch.l
> @@ -0,0 +1,6 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `fcvt\.d\.h fa0,fa1', extension `zfhmin' and `d', or `zhinxmin' and `zdinx' required
> +.*: Error: unrecognized opcode `fcvt\.d\.h fa0,fa1', extension `d' required
> +.*: Error: unrecognized opcode `fcvt\.d\.h fa0,fa1', extension `zfhmin' required
> +.*: Error: unrecognized opcode `fcvt\.d\.h a0,a1', extension `zdinx' required
> +.*: Error: unrecognized opcode `fcvt\.d\.h a0,a1', extension `zhinxmin' required
> diff --git a/gas/testsuite/gas/riscv/zfhmin-d-noarch.s b/gas/testsuite/gas/riscv/zfhmin-d-noarch.s
> new file mode 100644
> index 00000000000..f247de1bd36
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zfhmin-d-noarch.s
> @@ -0,0 +1,25 @@
> +.include "testutils.inc"
> +
> +target:
> + # Case 1: No 'Zfhmin', 'D', 'Zhinxmin' or 'Zdinx'
> + fcvt.d.h fa0, fa1
> +
> + # Case 2: 'Zfhmin' but no 'D'
> + SET_ARCH_START +zfhmin
> + fcvt.d.h fa0, fa1
> + SET_ARCH_END
> +
> + # Case 3: 'D' but no 'Zfhmin'
> + SET_ARCH_START +d
> + fcvt.d.h fa0, fa1
> + SET_ARCH_END
> +
> + # Case 4: 'Zhinxmin' but no 'Zdinx'
> + SET_ARCH_START +zhinxmin
> + fcvt.d.h a0, a1
> + SET_ARCH_END
> +
> + # Case 5: 'Zdinx' but no 'Zhinxmin'
> + SET_ARCH_START +zdinx
> + fcvt.d.h a0, a1
> + SET_ARCH_END
This is pretty close to what I thought, but don't need to add those
complicated macros. Just using ".option arch" directly should be
enough.
Thanks
Nelson
> --
> 2.37.2
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 08/12] RISC-V: Refine/enhance 'M'/'Zmmul' extension tests
2022-11-05 12:29 ` [PATCH 08/12] RISC-V: Refine/enhance 'M'/'Zmmul' extension tests Tsukasa OI
@ 2022-11-29 8:23 ` Nelson Chu
0 siblings, 0 replies; 26+ messages in thread
From: Nelson Chu @ 2022-11-29 8:23 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Kito Cheng, Palmer Dabbelt, binutils
On Sat, Nov 5, 2022 at 8:30 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> This commit refines tests for 'M' and 'Zmmul' extensions and adds "no
> required extension" testcases based on new test utilities.
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/m-ext.s: Refine using new testing utils.
> * testsuite/gas/riscv/m-ext-32.d: Refine.
> * testsuite/gas/riscv/m-ext-32-noarch.d: New test.
> * testsuite/gas/riscv/m-ext-32-noarch.l: Likewise.
> * testsuite/gas/riscv/m-ext-32-noarch-m.d: New test ased on
> m-ext-fail-zmmul-32.d but refine.
> * testsuite/gas/riscv/m-ext-32-noarch-m.l: New test ased on
> m-ext-fail-zmmul-32.l.
> * testsuite/gas/riscv/m-ext-64.d: Refine.
> * testsuite/gas/riscv/m-ext-64-noarch.d: New test ased on
> m-ext-fail-noarch-64.d but refine.
> * testsuite/gas/riscv/m-ext-64-noarch.l: New test ased on
> m-ext-fail-noarch-64.l.
> * testsuite/gas/riscv/m-ext-64-noarch-m.d: New test ased on
> m-ext-fail-zmmul-64.d but refine.
> * testsuite/gas/riscv/m-ext-64-noarch-m.l: New test ased on
> m-ext-fail-zmmul-64.l.
> * testsuite/gas/riscv/m-ext-fail-xlen-32.d: Removed.
> * testsuite/gas/riscv/m-ext-fail-xlen-32.l: Removed.
> * testsuite/gas/riscv/m-ext-fail-zmmul-32.d: Removed.
> * testsuite/gas/riscv/m-ext-fail-zmmul-64.d: Removed.
> * testsuite/gas/riscv/m-ext-fail-noarch-64.d: Removed.
> * testsuite/gas/riscv/zmmul-32.d: Removed as duplicate.
> * testsuite/gas/riscv/zmmul-64.d: Removed as duplicate.
> ---
> gas/testsuite/gas/riscv/m-ext-32-noarch-m.d | 4 ++++
> ...-ext-fail-zmmul-32.l => m-ext-32-noarch-m.l} | 0
> gas/testsuite/gas/riscv/m-ext-32-noarch.d | 4 ++++
> gas/testsuite/gas/riscv/m-ext-32-noarch.l | 14 ++++++++++++++
> gas/testsuite/gas/riscv/m-ext-32.d | 2 +-
> gas/testsuite/gas/riscv/m-ext-64-noarch-m.d | 4 ++++
> ...-ext-fail-zmmul-64.l => m-ext-64-noarch-m.l} | 0
> gas/testsuite/gas/riscv/m-ext-64-noarch.d | 4 ++++
> ...m-ext-fail-noarch-64.l => m-ext-64-noarch.l} | 0
> gas/testsuite/gas/riscv/m-ext-64.d | 2 +-
> gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d | 4 ----
> gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d | 4 ----
> gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l | 6 ------
> gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d | 4 ----
> gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d | 4 ----
> gas/testsuite/gas/riscv/m-ext.s | 17 +++++++++++------
> gas/testsuite/gas/riscv/zmmul-32.d | 14 --------------
> gas/testsuite/gas/riscv/zmmul-64.d | 15 ---------------
> 18 files changed, 43 insertions(+), 59 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/m-ext-32-noarch-m.d
> rename gas/testsuite/gas/riscv/{m-ext-fail-zmmul-32.l => m-ext-32-noarch-m.l} (100%)
> create mode 100644 gas/testsuite/gas/riscv/m-ext-32-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/m-ext-32-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/m-ext-64-noarch-m.d
> rename gas/testsuite/gas/riscv/{m-ext-fail-zmmul-64.l => m-ext-64-noarch-m.l} (100%)
> create mode 100644 gas/testsuite/gas/riscv/m-ext-64-noarch.d
> rename gas/testsuite/gas/riscv/{m-ext-fail-noarch-64.l => m-ext-64-noarch.l} (100%)
> delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
> delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
> delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
> delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
> delete mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
> delete mode 100644 gas/testsuite/gas/riscv/zmmul-32.d
> delete mode 100644 gas/testsuite/gas/riscv/zmmul-64.d
>
> diff --git a/gas/testsuite/gas/riscv/m-ext-32-noarch-m.d b/gas/testsuite/gas/riscv/m-ext-32-noarch-m.d
> new file mode 100644
> index 00000000000..1d05564125f
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/m-ext-32-noarch-m.d
> @@ -0,0 +1,4 @@
> +#as: -march=rv32i_zmmul -I$srcdir/$subdir -defsym XLEN=32 -defsym NOARCH_ARCH=1
> +#source: m-ext.s
> +#objdump: -d
> +#error_output: m-ext-32-noarch-m.l
> diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l b/gas/testsuite/gas/riscv/m-ext-32-noarch-m.l
> similarity index 100%
> rename from gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
> rename to gas/testsuite/gas/riscv/m-ext-32-noarch-m.l
> diff --git a/gas/testsuite/gas/riscv/m-ext-32-noarch.d b/gas/testsuite/gas/riscv/m-ext-32-noarch.d
> new file mode 100644
> index 00000000000..a708d429ac7
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/m-ext-32-noarch.d
> @@ -0,0 +1,4 @@
> +#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32 -defsym NOARCH=1
> +#source: m-ext.s
> +#objdump: -d
> +#error_output: m-ext-32-noarch.l
> diff --git a/gas/testsuite/gas/riscv/m-ext-32-noarch.l b/gas/testsuite/gas/riscv/m-ext-32-noarch.l
> new file mode 100644
> index 00000000000..f9179f45bb4
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/m-ext-32-noarch.l
> @@ -0,0 +1,14 @@
> +.*Assembler messages:
> +.*: Error: unrecognized opcode `mul a0,a1,a2', extension `m' or `zmmul' required
> +.*: Error: unrecognized opcode `mulh a0,a1,a2', extension `m' or `zmmul' required
> +.*: Error: unrecognized opcode `mulhsu a0,a1,a2', extension `m' or `zmmul' required
> +.*: Error: unrecognized opcode `mulhu a0,a1,a2', extension `m' or `zmmul' required
> +.*: Error: unrecognized opcode `div a0,a1,a2', extension `m' required
> +.*: Error: unrecognized opcode `divu a0,a1,a2', extension `m' required
> +.*: Error: unrecognized opcode `rem a0,a1,a2', extension `m' required
> +.*: Error: unrecognized opcode `remu a0,a1,a2', extension `m' required
> +.*: Error: unrecognized opcode `mulw a0,a1,a2'
> +.*: Error: unrecognized opcode `divw a0,a1,a2'
> +.*: Error: unrecognized opcode `divuw a0,a1,a2'
> +.*: Error: unrecognized opcode `remw a0,a1,a2'
> +.*: Error: unrecognized opcode `remuw a0,a1,a2'
> diff --git a/gas/testsuite/gas/riscv/m-ext-32.d b/gas/testsuite/gas/riscv/m-ext-32.d
> index fe2ef9af54b..02be2ef9569 100644
> --- a/gas/testsuite/gas/riscv/m-ext-32.d
> +++ b/gas/testsuite/gas/riscv/m-ext-32.d
> @@ -1,4 +1,4 @@
> -#as: -march=rv32im
> +#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32
> #source: m-ext.s
> #objdump: -d
>
> diff --git a/gas/testsuite/gas/riscv/m-ext-64-noarch-m.d b/gas/testsuite/gas/riscv/m-ext-64-noarch-m.d
> new file mode 100644
> index 00000000000..d74fbd0b682
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/m-ext-64-noarch-m.d
> @@ -0,0 +1,4 @@
> +#as: -march=rv64i_zmmul -I$srcdir/$subdir -defsym XLEN=64 -defsym NOARCH_ARCH=1
> +#source: m-ext.s
> +#objdump: -d
> +#error_output: m-ext-64-noarch-m.l
> diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l b/gas/testsuite/gas/riscv/m-ext-64-noarch-m.l
> similarity index 100%
> rename from gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l
> rename to gas/testsuite/gas/riscv/m-ext-64-noarch-m.l
> diff --git a/gas/testsuite/gas/riscv/m-ext-64-noarch.d b/gas/testsuite/gas/riscv/m-ext-64-noarch.d
> new file mode 100644
> index 00000000000..2d7031e5a35
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/m-ext-64-noarch.d
> @@ -0,0 +1,4 @@
> +#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64 -defsym NOARCH=1
> +#source: m-ext.s
> +#objdump: -d
> +#error_output: m-ext-64-noarch.l
> diff --git a/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l b/gas/testsuite/gas/riscv/m-ext-64-noarch.l
> similarity index 100%
> rename from gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
> rename to gas/testsuite/gas/riscv/m-ext-64-noarch.l
> diff --git a/gas/testsuite/gas/riscv/m-ext-64.d b/gas/testsuite/gas/riscv/m-ext-64.d
> index 05099b14e9e..ad086829ae5 100644
> --- a/gas/testsuite/gas/riscv/m-ext-64.d
> +++ b/gas/testsuite/gas/riscv/m-ext-64.d
> @@ -1,4 +1,4 @@
> -#as: -march=rv64im -defsym rv64=1
> +#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64
> #source: m-ext.s
> #objdump: -d
>
> diff --git a/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
> deleted file mode 100644
> index 3c4fc9a0a50..00000000000
> --- a/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -#as: -march=rv64i -defsym rv64=1
> -#source: m-ext.s
> -#objdump: -d
> -#error_output: m-ext-fail-noarch-64.l
> diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
> deleted file mode 100644
> index 54f8b8225dc..00000000000
> --- a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -#as: -march=rv32im -defsym rv64=1
> -#source: m-ext.s
> -#objdump: -d
> -#error_output: m-ext-fail-xlen-32.l
> diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
> deleted file mode 100644
> index d65ca4980e6..00000000000
> --- a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -.*Assembler messages:
> -.*: Error: unrecognized opcode `mulw a0,a1,a2'
> -.*: Error: unrecognized opcode `divw a0,a1,a2'
> -.*: Error: unrecognized opcode `divuw a0,a1,a2'
> -.*: Error: unrecognized opcode `remw a0,a1,a2'
> -.*: Error: unrecognized opcode `remuw a0,a1,a2'
> diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
> deleted file mode 100644
> index c164fa96f8f..00000000000
> --- a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -#as: -march=rv32i_zmmul
> -#source: m-ext.s
> -#objdump: -d
> -#error_output: m-ext-fail-zmmul-32.l
> diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
> deleted file mode 100644
> index f736d9c66c6..00000000000
> --- a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -#as: -march=rv64i_zmmul -defsym rv64=1
> -#source: m-ext.s
> -#objdump: -d
> -#error_output: m-ext-fail-zmmul-64.l
> diff --git a/gas/testsuite/gas/riscv/m-ext.s b/gas/testsuite/gas/riscv/m-ext.s
> index 68baf2ab9c0..8d599f20aef 100644
> --- a/gas/testsuite/gas/riscv/m-ext.s
> +++ b/gas/testsuite/gas/riscv/m-ext.s
> @@ -1,21 +1,26 @@
> +.include "testutils.inc"
> +
> target:
> + SET_ARCH_START +zmmul
Use .option arch/push/pop to enable the zmmul.
> mul a0, a1, a2
> mulh a0, a1, a2
> mulhsu a0, a1, a2
> mulhu a0, a1, a2
> -.ifndef zmmul
> + SET_ARCH_START +m
Likewise, but disable the zmmul and enable m.
> div a0, a1, a2
> divu a0, a1, a2
> rem a0, a1, a2
> remu a0, a1, a2
> -.endif
> -
> -.ifdef rv64
> + SET_ARCH_END
> + SET_ARCH_END
> +.if XLEN_GE_64
Use .option arch, rv64xxx.
> + SET_ARCH_START +zmmul
> mulw a0, a1, a2
> -.ifndef zmmul
> + SET_ARCH_START +m
> divw a0, a1, a2
> divuw a0, a1, a2
> remw a0, a1, a2
> remuw a0, a1, a2
> -.endif
> + SET_ARCH_END
> + SET_ARCH_END
> .endif
> diff --git a/gas/testsuite/gas/riscv/zmmul-32.d b/gas/testsuite/gas/riscv/zmmul-32.d
> deleted file mode 100644
> index c9cf56ab33f..00000000000
> --- a/gas/testsuite/gas/riscv/zmmul-32.d
> +++ /dev/null
> @@ -1,14 +0,0 @@
> -#as: -march=rv32im -defsym zmmul=1
> -#source: m-ext.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+02c58533[ ]+mul[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+02c59533[ ]+mulh[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+02c5a533[ ]+mulhsu[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+02c5b533[ ]+mulhu[ ]+a0,a1,a2
> diff --git a/gas/testsuite/gas/riscv/zmmul-64.d b/gas/testsuite/gas/riscv/zmmul-64.d
> deleted file mode 100644
> index 67ef3604755..00000000000
> --- a/gas/testsuite/gas/riscv/zmmul-64.d
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -#as: -march=rv64im -defsym zmmul=1 -defsym rv64=1
> -#source: m-ext.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+02c58533[ ]+mul[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+02c59533[ ]+mulh[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+02c5a533[ ]+mulhsu[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+02c5b533[ ]+mulhu[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+02c5853b[ ]+mulw[ ]+a0,a1,a2
Therefore, we don't need zmmul-32 and zmmul-64, and defines those
special symbols by -defsym, just need one file includes multiple
mapping symbols to make instructions dumped right.
Thanks
Nelson
> --
> 2.37.2
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 09/12] RISC-V: Combine/enhance 'Zicbo[mz]' extension tests
2022-11-05 12:29 ` [PATCH 09/12] RISC-V: Combine/enhance 'Zicbo[mz]' " Tsukasa OI
@ 2022-11-29 8:38 ` Nelson Chu
0 siblings, 0 replies; 26+ messages in thread
From: Nelson Chu @ 2022-11-29 8:38 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Kito Cheng, Palmer Dabbelt, binutils
On Sat, Nov 5, 2022 at 8:30 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> This commit combines tests for 'Zicbom' and 'Zicboz' extensions and adds
> "no required extension" testcases based on new test utilities. It also
> contains minor tidying (such as minimizing base from RV64G to RV32I).
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/zicbo-mz-ext.s: Combine zicbo[mz].s.
> * testsuite/gas/riscv/zicbo-mz-ext.d: Likewise.
> Minimize extension requirements and remove source.
> * testsuite/gas/riscv/zicbo-mz-ext-noarch.d: New test for
> architecture failure.
> * testsuite/gas/riscv/zicbo-mz-ext-noarch.l: Likewise.
> * testsuite/gas/riscv/zicbo-mz-ext-fail.s: Combine
> zicbo[mz]-fail.s.
> * testsuite/gas/riscv/zicbo-mz-ext-fail.d: Likewise.
> Minimize extension requirements.
> * testsuite/gas/riscv/zicbo-mz-ext-fail.l: Likewise.
> Make matching pattern stricter.
> * testsuite/gas/riscv/zicbom.s: Removed.
> * testsuite/gas/riscv/zicbom.d: Removed.
> * testsuite/gas/riscv/zicbom-fail.s: Removed.
> * testsuite/gas/riscv/zicbom-fail.d: Removed.
> * testsuite/gas/riscv/zicbom-fail.l: Removed.
> * testsuite/gas/riscv/zicboz.s: Removed.
> * testsuite/gas/riscv/zicboz.d: Removed.
> * testsuite/gas/riscv/zicboz-fail.s: Removed.
> * testsuite/gas/riscv/zicboz-fail.d: Removed.
> * testsuite/gas/riscv/zicboz-fail.l: Removed.
> ---
> gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d | 2 ++
> gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l | 11 +++++++++++
> .../riscv/{zicbom-fail.s => zicbo-mz-ext-fail.s} | 4 ++++
> gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d | 3 +++
> gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l | 11 +++++++++++
> .../gas/riscv/{zicbom.d => zicbo-mz-ext.d} | 9 ++++++---
> gas/testsuite/gas/riscv/zicbo-mz-ext.s | 16 ++++++++++++++++
One testcase for zicbom-zicboz.s/d, and the other testcase for
zicbom-zicboz-fail.s/d. Use .option arch directly rather than those
new defined macros. Personally, I think we don't need the no-arch
test cases since it's trivial, but that's just my personal thought.
Thanks
Nelson
> gas/testsuite/gas/riscv/zicbom-fail.d | 3 ---
> gas/testsuite/gas/riscv/zicbom-fail.l | 7 -------
> gas/testsuite/gas/riscv/zicbom.s | 7 -------
> gas/testsuite/gas/riscv/zicboz-fail.d | 3 ---
> gas/testsuite/gas/riscv/zicboz-fail.l | 5 -----
> gas/testsuite/gas/riscv/zicboz-fail.s | 5 -----
> gas/testsuite/gas/riscv/zicboz.d | 13 -------------
> gas/testsuite/gas/riscv/zicboz.s | 5 -----
> 15 files changed, 53 insertions(+), 51 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d
> create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l
> rename gas/testsuite/gas/riscv/{zicbom-fail.s => zicbo-mz-ext-fail.s} (61%)
> create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l
> rename gas/testsuite/gas/riscv/{zicbom.d => zicbo-mz-ext.d} (60%)
> create mode 100644 gas/testsuite/gas/riscv/zicbo-mz-ext.s
> delete mode 100644 gas/testsuite/gas/riscv/zicbom-fail.d
> delete mode 100644 gas/testsuite/gas/riscv/zicbom-fail.l
> delete mode 100644 gas/testsuite/gas/riscv/zicbom.s
> delete mode 100644 gas/testsuite/gas/riscv/zicboz-fail.d
> delete mode 100644 gas/testsuite/gas/riscv/zicboz-fail.l
> delete mode 100644 gas/testsuite/gas/riscv/zicboz-fail.s
> delete mode 100644 gas/testsuite/gas/riscv/zicboz.d
> delete mode 100644 gas/testsuite/gas/riscv/zicboz.s
>
> diff --git a/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d b/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d
> new file mode 100644
> index 00000000000..e84233b09a1
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.d
> @@ -0,0 +1,2 @@
> +#as: -march=rv32i_zicbom_zicboz
> +#error_output: zicbo-mz-ext-fail.l
> diff --git a/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l b/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l
> new file mode 100644
> index 00000000000..a0bd7096f25
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.l
> @@ -0,0 +1,11 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `cbo\.clean 1\(x1\)'
> +.*: Error: illegal operands `cbo\.clean x30'
> +.*: Error: illegal operands `cbo\.flush \(0\+1\)\(x1\)'
> +.*: Error: illegal operands `cbo\.flush x30'
> +.*: Error: illegal operands `cbo\.inval 3\*2\+5\(x1\)'
> +.*: Error: illegal operands `cbo\.inval x30'
> +.*: Error: illegal operands `cbo\.zero x1'
> +.*: Error: illegal operands `cbo\.zero 1\(x30\)'
> +.*: Error: illegal operands `cbo\.zero 3\+5\(x1\)'
> +.*: Error: illegal operands `cbo\.zero \(2\*4\)\(x30\)'
> diff --git a/gas/testsuite/gas/riscv/zicbom-fail.s b/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.s
> similarity index 61%
> rename from gas/testsuite/gas/riscv/zicbom-fail.s
> rename to gas/testsuite/gas/riscv/zicbo-mz-ext-fail.s
> index 5fa22749b3a..447e9c37de7 100644
> --- a/gas/testsuite/gas/riscv/zicbom-fail.s
> +++ b/gas/testsuite/gas/riscv/zicbo-mz-ext-fail.s
> @@ -5,3 +5,7 @@ target:
> cbo.flush x30
> cbo.inval 3*2+5(x1)
> cbo.inval x30
> + cbo.zero x1
> + cbo.zero 1(x30)
> + cbo.zero 3+5(x1)
> + cbo.zero (2*4)(x30)
> diff --git a/gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d b/gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d
> new file mode 100644
> index 00000000000..33db96dd471
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i -I$srcdir/$subdir -defsym NOARCH=1
> +#source: zicbo-mz-ext.s
> +#error_output: zicbo-mz-ext-noarch.l
> diff --git a/gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l b/gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l
> new file mode 100644
> index 00000000000..6cf1e4821a2
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicbo-mz-ext-noarch.l
> @@ -0,0 +1,11 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `cbo\.clean \(x1\)', extension `zicbom' required
> +.*: Error: unrecognized opcode `cbo\.clean 0\(x30\)', extension `zicbom' required
> +.*: Error: unrecognized opcode `cbo\.flush \(x1\)', extension `zicbom' required
> +.*: Error: unrecognized opcode `cbo\.flush \(2-2\)\(x30\)', extension `zicbom' required
> +.*: Error: unrecognized opcode `cbo\.inval \(x1\)', extension `zicbom' required
> +.*: Error: unrecognized opcode `cbo\.inval 3\*4-12\(x30\)', extension `zicbom' required
> +.*: Error: unrecognized opcode `cbo\.zero 0\(x1\)', extension `zicboz' required
> +.*: Error: unrecognized opcode `cbo\.zero \(x30\)', extension `zicboz' required
> +.*: Error: unrecognized opcode `cbo\.zero 2-2\(x1\)', extension `zicboz' required
> +.*: Error: unrecognized opcode `cbo\.zero \(3\*5-15\)\(x30\)', extension `zicboz' required
> diff --git a/gas/testsuite/gas/riscv/zicbom.d b/gas/testsuite/gas/riscv/zicbo-mz-ext.d
> similarity index 60%
> rename from gas/testsuite/gas/riscv/zicbom.d
> rename to gas/testsuite/gas/riscv/zicbo-mz-ext.d
> index edd8a7079f4..9daa1cc4a93 100644
> --- a/gas/testsuite/gas/riscv/zicbom.d
> +++ b/gas/testsuite/gas/riscv/zicbo-mz-ext.d
> @@ -1,6 +1,5 @@
> -#as: -march=rv64g_zicbom
> -#source: zicbom.s
> -#objdump: -dr
> +#as: -march=rv32i -I$srcdir/$subdir
> +#objdump: -d
>
> .*:[ ]+file format .*
>
> @@ -13,3 +12,7 @@ Disassembly of section .text:
> [ ]+[0-9a-f]+:[ ]+002f200f[ ]+cbo\.flush[ ]+\(t5\)
> [ ]+[0-9a-f]+:[ ]+0000a00f[ ]+cbo\.inval[ ]+\(ra\)
> [ ]+[0-9a-f]+:[ ]+000f200f[ ]+cbo\.inval[ ]+\(t5\)
> +[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+\(ra\)
> +[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+\(t5\)
> +[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+\(ra\)
> +[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+\(t5\)
> diff --git a/gas/testsuite/gas/riscv/zicbo-mz-ext.s b/gas/testsuite/gas/riscv/zicbo-mz-ext.s
> new file mode 100644
> index 00000000000..af997377903
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicbo-mz-ext.s
> @@ -0,0 +1,16 @@
> +.include "testutils.inc"
> +target:
> + SET_ARCH_START +zicbom
> + cbo.clean (x1)
> + cbo.clean 0(x30)
> + cbo.flush (x1)
> + cbo.flush (2-2)(x30)
> + cbo.inval (x1)
> + cbo.inval 3*4-12(x30)
> + SET_ARCH_END
> + SET_ARCH_START +zicboz
> + cbo.zero 0(x1)
> + cbo.zero (x30)
> + cbo.zero 2-2(x1)
> + cbo.zero (3*5-15)(x30)
> + SET_ARCH_END
> diff --git a/gas/testsuite/gas/riscv/zicbom-fail.d b/gas/testsuite/gas/riscv/zicbom-fail.d
> deleted file mode 100644
> index a6a61dfd37e..00000000000
> --- a/gas/testsuite/gas/riscv/zicbom-fail.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv64g_zicbom
> -#source: zicbom-fail.s
> -#error_output: zicbom-fail.l
> diff --git a/gas/testsuite/gas/riscv/zicbom-fail.l b/gas/testsuite/gas/riscv/zicbom-fail.l
> deleted file mode 100644
> index 2cf76356d2b..00000000000
> --- a/gas/testsuite/gas/riscv/zicbom-fail.l
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -.*: Assembler messages:
> -.*: Error: illegal operands `cbo.clean 1\(x1\)'
> -.*: Error: illegal operands `cbo.clean x30'
> -.*: Error: illegal operands `cbo.flush \(0\+1\)\(x1\)'
> -.*: Error: illegal operands `cbo.flush x30'
> -.*: Error: illegal operands `cbo.inval 3\*2\+5\(x1\)'
> -.*: Error: illegal operands `cbo.inval x30'
> diff --git a/gas/testsuite/gas/riscv/zicbom.s b/gas/testsuite/gas/riscv/zicbom.s
> deleted file mode 100644
> index 6a306b931ed..00000000000
> --- a/gas/testsuite/gas/riscv/zicbom.s
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -target:
> - cbo.clean (x1)
> - cbo.clean 0(x30)
> - cbo.flush (x1)
> - cbo.flush (2-2)(x30)
> - cbo.inval (x1)
> - cbo.inval 3*4-12(x30)
> diff --git a/gas/testsuite/gas/riscv/zicboz-fail.d b/gas/testsuite/gas/riscv/zicboz-fail.d
> deleted file mode 100644
> index 74cfd2fc911..00000000000
> --- a/gas/testsuite/gas/riscv/zicboz-fail.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv64g_zicboz
> -#source: zicboz-fail.s
> -#error_output: zicboz-fail.l
> diff --git a/gas/testsuite/gas/riscv/zicboz-fail.l b/gas/testsuite/gas/riscv/zicboz-fail.l
> deleted file mode 100644
> index ad8dcf54e00..00000000000
> --- a/gas/testsuite/gas/riscv/zicboz-fail.l
> +++ /dev/null
> @@ -1,5 +0,0 @@
> -.*: Assembler messages:
> -.*: Error: illegal operands `cbo.zero x1'
> -.*: Error: illegal operands `cbo.zero 1\(x30\)'
> -.*: Error: illegal operands `cbo.zero 3\+5\(x1\)'
> -.*: Error: illegal operands `cbo.zero \(2\*4\)\(x30\)'
> diff --git a/gas/testsuite/gas/riscv/zicboz-fail.s b/gas/testsuite/gas/riscv/zicboz-fail.s
> deleted file mode 100644
> index 0856ea85ab1..00000000000
> --- a/gas/testsuite/gas/riscv/zicboz-fail.s
> +++ /dev/null
> @@ -1,5 +0,0 @@
> -target:
> - cbo.zero x1
> - cbo.zero 1(x30)
> - cbo.zero 3+5(x1)
> - cbo.zero (2*4)(x30)
> diff --git a/gas/testsuite/gas/riscv/zicboz.d b/gas/testsuite/gas/riscv/zicboz.d
> deleted file mode 100644
> index e04ab3491db..00000000000
> --- a/gas/testsuite/gas/riscv/zicboz.d
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -#as: -march=rv64g_zicboz
> -#source: zicboz.s
> -#objdump: -dr
> -
> -.*:[ ]+file format .*
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+\(ra\)
> -[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+\(t5\)
> -[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+\(ra\)
> -[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+\(t5\)
> diff --git a/gas/testsuite/gas/riscv/zicboz.s b/gas/testsuite/gas/riscv/zicboz.s
> deleted file mode 100644
> index 3830362c376..00000000000
> --- a/gas/testsuite/gas/riscv/zicboz.s
> +++ /dev/null
> @@ -1,5 +0,0 @@
> -target:
> - cbo.zero 0(x1)
> - cbo.zero (x30)
> - cbo.zero 2-2(x1)
> - cbo.zero (3*5-15)(x30)
> --
> 2.37.2
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 10/12] RISC-V: Enhance 'Zicbop' testcases
2022-11-05 12:29 ` [PATCH 10/12] RISC-V: Enhance 'Zicbop' testcases Tsukasa OI
@ 2022-11-29 8:51 ` Nelson Chu
0 siblings, 0 replies; 26+ messages in thread
From: Nelson Chu @ 2022-11-29 8:51 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Kito Cheng, Palmer Dabbelt, binutils
On Sat, Nov 5, 2022 at 8:31 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> This commit makes some tidying and enhancements to 'Zicbop' testcases.
> It adds "no required extension" testcases based on new test utilities. It
> adds the hint of the failure reason to the file names.
I suggest moving the zicbop into zicbom-zicboz test case, and don't
care the no-arch test cases for now.
Nelson
> gas/ChangeLog:
>
> * testsuite/gas/riscv/zicbop.s: Enhanced to test offset zero.
> * testsuite/gas/riscv/zicbop.d: Likewise.
> Minimize extension requirements and objdump options.
> * testsuite/gas/riscv/zicbop-noarch.s: New test for
> architecture failure.
> * testsuite/gas/riscv/zicbop-noarch.d: Likewise.
> * testsuite/gas/riscv/zicbop-noarch.l: Likewise.
> * testsuite/gas/riscv/zicbop-fail-offset.s: Move from
> zicbop-fail.s.
> * testsuite/gas/riscv/zicbop-fail-offset.d: Likewise.
> Minimize extension requirements.
> * testsuite/gas/riscv/zicbop-fail-offset.l: Likewise.
> * testsuite/gas/riscv/zicbop-fail.s: Removed.
> * testsuite/gas/riscv/zicbop-fail.d: Removed.
> * testsuite/gas/riscv/zicbop-fail.l: Removed.
> ---
> gas/testsuite/gas/riscv/zicbop-fail-offset.d | 2 ++
> .../gas/riscv/{zicbop-fail.l => zicbop-fail-offset.l} | 0
> .../gas/riscv/{zicbop-fail.s => zicbop-fail-offset.s} | 0
> gas/testsuite/gas/riscv/zicbop-fail.d | 3 ---
> gas/testsuite/gas/riscv/zicbop-noarch.d | 4 ++++
> gas/testsuite/gas/riscv/zicbop-noarch.l | 7 +++++++
> gas/testsuite/gas/riscv/zicbop.d | 8 +++++---
> gas/testsuite/gas/riscv/zicbop.s | 7 +++++++
> 8 files changed, 25 insertions(+), 6 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/zicbop-fail-offset.d
> rename gas/testsuite/gas/riscv/{zicbop-fail.l => zicbop-fail-offset.l} (100%)
> rename gas/testsuite/gas/riscv/{zicbop-fail.s => zicbop-fail-offset.s} (100%)
> delete mode 100644 gas/testsuite/gas/riscv/zicbop-fail.d
> create mode 100644 gas/testsuite/gas/riscv/zicbop-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zicbop-noarch.l
>
> diff --git a/gas/testsuite/gas/riscv/zicbop-fail-offset.d b/gas/testsuite/gas/riscv/zicbop-fail-offset.d
> new file mode 100644
> index 00000000000..4680f6eef0d
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicbop-fail-offset.d
> @@ -0,0 +1,2 @@
> +#as: -march=rv32i_zicbop
> +#error_output: zicbop-fail-offset.l
> diff --git a/gas/testsuite/gas/riscv/zicbop-fail.l b/gas/testsuite/gas/riscv/zicbop-fail-offset.l
> similarity index 100%
> rename from gas/testsuite/gas/riscv/zicbop-fail.l
> rename to gas/testsuite/gas/riscv/zicbop-fail-offset.l
> diff --git a/gas/testsuite/gas/riscv/zicbop-fail.s b/gas/testsuite/gas/riscv/zicbop-fail-offset.s
> similarity index 100%
> rename from gas/testsuite/gas/riscv/zicbop-fail.s
> rename to gas/testsuite/gas/riscv/zicbop-fail-offset.s
> diff --git a/gas/testsuite/gas/riscv/zicbop-fail.d b/gas/testsuite/gas/riscv/zicbop-fail.d
> deleted file mode 100644
> index d734c7d4d15..00000000000
> --- a/gas/testsuite/gas/riscv/zicbop-fail.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv64g_zicbop
> -#source: zicbop-fail.s
> -#error_output: zicbop-fail.l
> diff --git a/gas/testsuite/gas/riscv/zicbop-noarch.d b/gas/testsuite/gas/riscv/zicbop-noarch.d
> new file mode 100644
> index 00000000000..2f51eb9b8d1
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicbop-noarch.d
> @@ -0,0 +1,4 @@
> +#as: -march=rv32i -I$srcdir/$subdir -defsym NOARCH=1
> +#source: zicbop.s
> +#objdump: -d
> +#error_output: zicbop-noarch.l
> diff --git a/gas/testsuite/gas/riscv/zicbop-noarch.l b/gas/testsuite/gas/riscv/zicbop-noarch.l
> new file mode 100644
> index 00000000000..742fedd9009
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zicbop-noarch.l
> @@ -0,0 +1,7 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `prefetch\.i \(x1\)', extension `zicbop' required
> +.*: Error: unrecognized opcode `prefetch\.i 0x20\(x1\)', extension `zicbop' required
> +.*: Error: unrecognized opcode `prefetch\.r \(x16\)', extension `zicbop' required
> +.*: Error: unrecognized opcode `prefetch\.r -2048\(x16\)', extension `zicbop' required
> +.*: Error: unrecognized opcode `prefetch\.w \(x31\)', extension `zicbop' required
> +.*: Error: unrecognized opcode `prefetch\.w \+0x7e0\(x31\)', extension `zicbop' required
> diff --git a/gas/testsuite/gas/riscv/zicbop.d b/gas/testsuite/gas/riscv/zicbop.d
> index 056a8a501ff..b19ead39cd6 100644
> --- a/gas/testsuite/gas/riscv/zicbop.d
> +++ b/gas/testsuite/gas/riscv/zicbop.d
> @@ -1,12 +1,14 @@
> -#as: -march=rv64g_zicbop
> -#source: zicbop.s
> -#objdump: -dr
> +#as: -march=rv32i -I$srcdir/$subdir
> +#objdump: -d
>
> .*:[ ]+file format .*
>
> Disassembly of section .text:
>
> 0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+0000e013[ ]+prefetch\.i[ ]+0\(ra\)
> [ ]+[0-9a-f]+:[ ]+0200e013[ ]+prefetch\.i[ ]+32\(ra\)
> +[ ]+[0-9a-f]+:[ ]+00186013[ ]+prefetch\.r[ ]+0\(a6\)
> [ ]+[0-9a-f]+:[ ]+80186013[ ]+prefetch\.r[ ]+-2048\(a6\)
> +[ ]+[0-9a-f]+:[ ]+003fe013[ ]+prefetch\.w[ ]+0\(t6\)
> [ ]+[0-9a-f]+:[ ]+7e3fe013[ ]+prefetch\.w[ ]+2016\(t6\)
> diff --git a/gas/testsuite/gas/riscv/zicbop.s b/gas/testsuite/gas/riscv/zicbop.s
> index ffe2014be6f..698bb5d0d8e 100644
> --- a/gas/testsuite/gas/riscv/zicbop.s
> +++ b/gas/testsuite/gas/riscv/zicbop.s
> @@ -1,4 +1,11 @@
> +.include "testutils.inc"
> +
> target:
> + SET_ARCH_START +zicbop
> + prefetch.i (x1)
> prefetch.i 0x20(x1)
> + prefetch.r (x16)
> prefetch.r -2048(x16)
> + prefetch.w (x31)
> prefetch.w +0x7e0(x31)
> + SET_ARCH_END
This is only one extension needed to add, so don't need the mapping symbols.
> --
> 2.37.2
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 11/12] RISC-V: Reorganize/enhance 'Zb*' extension tests
2022-11-05 12:29 ` [PATCH 11/12] RISC-V: Reorganize/enhance 'Zb*' extension tests Tsukasa OI
@ 2022-11-29 8:57 ` Nelson Chu
0 siblings, 0 replies; 26+ messages in thread
From: Nelson Chu @ 2022-11-29 8:57 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Kito Cheng, Palmer Dabbelt, binutils
On Sat, Nov 5, 2022 at 8:31 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> This commit reorganizes tests for 'Zb*' extensions and adds "no required
> extension" testcases based on new test utilities. It also contains minor
> tidying (such as using different registers per operand).
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/zb-ext.s: Reorganize and make some tidying.
> * testsuite/gas/riscv/zb-ext-32.d: Reflect new zb-ext.s.
> Make matching pattern stricter.
> * testsuite/gas/riscv/zb-ext-64.d: Likewise.
> * testsuite/gas/riscv/zb-ext-32-noalias.d: Likewise.
> * testsuite/gas/riscv/zb-ext-64-noalias.d: Likewise.
> * testsuite/gas/riscv/zb-ext-32-noarch.d: New test.
> * testsuite/gas/riscv/zb-ext-32-noarch.l: Likewise.
> * testsuite/gas/riscv/zb-ext-64-noarch.d: New test.
> * testsuite/gas/riscv/zb-ext-64-noarch.l: Likewise.
> * testsuite/gas/riscv/b-ext.s: Removed.
> * testsuite/gas/riscv/b-ext.d: Removed.
> * testsuite/gas/riscv/b-ext-64.s: Removed.
> * testsuite/gas/riscv/b-ext-64.d: Removed.
> * testsuite/gas/riscv/b-ext-na.d: Removed.
> * testsuite/gas/riscv/b-ext-64-na.d: Removed.
> ---
> gas/testsuite/gas/riscv/b-ext-64.d | 72 ----------------
> gas/testsuite/gas/riscv/b-ext-64.s | 64 --------------
> gas/testsuite/gas/riscv/b-ext.d | 51 -----------
> gas/testsuite/gas/riscv/b-ext.s | 43 ----------
> .../riscv/{b-ext-na.d => zb-ext-32-noalias.d} | 38 ++++-----
> gas/testsuite/gas/riscv/zb-ext-32-noarch.d | 3 +
> gas/testsuite/gas/riscv/zb-ext-32-noarch.l | 60 +++++++++++++
> gas/testsuite/gas/riscv/zb-ext-32.d | 51 +++++++++++
> .../{b-ext-64-na.d => zb-ext-64-noalias.d} | 72 ++++++++--------
> gas/testsuite/gas/riscv/zb-ext-64-noarch.d | 3 +
> gas/testsuite/gas/riscv/zb-ext-64-noarch.l | 59 +++++++++++++
> gas/testsuite/gas/riscv/zb-ext-64.d | 72 ++++++++++++++++
> gas/testsuite/gas/riscv/zb-ext.s | 84 +++++++++++++++++++
> 13 files changed, 387 insertions(+), 285 deletions(-)
> delete mode 100644 gas/testsuite/gas/riscv/b-ext-64.d
> delete mode 100644 gas/testsuite/gas/riscv/b-ext-64.s
> delete mode 100644 gas/testsuite/gas/riscv/b-ext.d
> delete mode 100644 gas/testsuite/gas/riscv/b-ext.s
> rename gas/testsuite/gas/riscv/{b-ext-na.d => zb-ext-32-noalias.d} (67%)
> create mode 100644 gas/testsuite/gas/riscv/zb-ext-32-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zb-ext-32-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/zb-ext-32.d
> rename gas/testsuite/gas/riscv/{b-ext-64-na.d => zb-ext-64-noalias.d} (73%)
> create mode 100644 gas/testsuite/gas/riscv/zb-ext-64-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zb-ext-64-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/zb-ext-64.d
> create mode 100644 gas/testsuite/gas/riscv/zb-ext.s
>
> diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
> deleted file mode 100644
> index f88fef9aeb2..00000000000
> --- a/gas/testsuite/gas/riscv/b-ext-64.d
> +++ /dev/null
> @@ -1,72 +0,0 @@
> -#as: -march=rv64i_zba_zbb_zbc_zbs
> -#source: b-ext-64.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+0:[ ]+60051513[ ]+clz[ ]+a0,a0
> -[ ]+4:[ ]+60151513[ ]+ctz[ ]+a0,a0
> -[ ]+8:[ ]+60251513[ ]+cpop[ ]+a0,a0
> -[ ]+c:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
> -[ ]+10:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
> -[ ]+14:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
> -[ ]+18:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
> -[ ]+1c:[ ]+60451513[ ]+sext.b[ ]+a0,a0
> -[ ]+20:[ ]+60551513[ ]+sext.h[ ]+a0,a0
> -[ ]+24:[ ]+0805453b[ ]+zext.h[ ]+a0,a0
> -[ ]+28:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
> -[ ]+2c:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
> -[ ]+30:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
> -[ ]+34:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
> -[ ]+38:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
> -[ ]+3c:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
> -[ ]+40:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
> -[ ]+44:[ ]+6b855513[ ]+rev8[ ]+a0,a0
> -[ ]+48:[ ]+28755513[ ]+orc.b[ ]+a0,a0
> -[ ]+4c:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
> -[ ]+50:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
> -[ ]+54:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
> -[ ]+58:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
> -[ ]+5c:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
> -[ ]+60:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
> -[ ]+64:[ ]+6005151b[ ]+clzw[ ]+a0,a0
> -[ ]+68:[ ]+6015151b[ ]+ctzw[ ]+a0,a0
> -[ ]+6c:[ ]+6025151b[ ]+cpopw[ ]+a0,a0
> -[ ]+70:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
> -[ ]+74:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
> -[ ]+78:[ ]+6025d51b[ ]+rorw[ ]+a0,a1,0x2
> -[ ]+7c:[ ]+6025d51b[ ]+rorw[ ]+a0,a1,0x2
> -[ ]+80:[ ]+20c5a53b[ ]+sh1add.uw[ ]+a0,a1,a2
> -[ ]+84:[ ]+20c5c53b[ ]+sh2add.uw[ ]+a0,a1,a2
> -[ ]+88:[ ]+20c5e53b[ ]+sh3add.uw[ ]+a0,a1,a2
> -[ ]+8c:[ ]+08c5853b[ ]+add.uw[ ]+a0,a1,a2
> -[ ]+90:[ ]+0805853b[ ]+zext.w[ ]+a0,a1
> -[ ]+94:[ ]+0825951b[ ]+slli.uw[ ]+a0,a1,0x2
> -[ ]+[0-9a-f]+:[ ]+48059513[ ]+bclr[ ]+a0,a1,0x0
> -[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclr[ ]+a0,a1,0x1f
> -[ ]+[0-9a-f]+:[ ]+28059513[ ]+bset[ ]+a0,a1,0x0
> -[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bset[ ]+a0,a1,0x1f
> -[ ]+[0-9a-f]+:[ ]+68059513[ ]+binv[ ]+a0,a1,0x0
> -[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binv[ ]+a0,a1,0x1f
> -[ ]+[0-9a-f]+:[ ]+4805d513[ ]+bext[ ]+a0,a1,0x0
> -[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bext[ ]+a0,a1,0x1f
> -[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclr[ ]+a0,a1,0x3f
> -[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bset[ ]+a0,a1,0x3f
> -[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binv[ ]+a0,a1,0x3f
> -[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bext[ ]+a0,a1,0x3f
> -[ ]+[0-9a-f]+:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclr[ ]+a0,a1,0x1f
> -[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bset[ ]+a0,a1,0x1f
> -[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binv[ ]+a0,a1,0x1f
> -[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bext[ ]+a0,a1,0x1f
> -[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclr[ ]+a0,a1,0x3f
> -[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bset[ ]+a0,a1,0x3f
> -[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binv[ ]+a0,a1,0x3f
> -[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bext[ ]+a0,a1,0x3f
> diff --git a/gas/testsuite/gas/riscv/b-ext-64.s b/gas/testsuite/gas/riscv/b-ext-64.s
> deleted file mode 100644
> index 57e501e9a41..00000000000
> --- a/gas/testsuite/gas/riscv/b-ext-64.s
> +++ /dev/null
> @@ -1,64 +0,0 @@
> -target:
> - clz a0, a0
> - ctz a0, a0
> - cpop a0, a0
> - min a0, a1, a2
> - minu a0, a1, a2
> - max a0, a1, a2
> - maxu a0, a1, a2
> - sext.b a0, a0
> - sext.h a0, a0
> - zext.h a0, a0
> - andn a0, a1, a2
> - orn a0, a1, a2
> - xnor a0, a1, a2
> - rol a0, a1, a2
> - ror a0, a1, a2
> - ror a0, a1, 2
> - rori a0, a1, 2
> - rev8 a0, a0
> - orc.b a0, a0
> - sh1add a0, a1, a2
> - sh2add a0, a1, a2
> - sh3add a0, a1, a2
> - clmul a0, a1, a2
> - clmulh a0, a1, a2
> - clmulr a0, a1, a2
> - clzw a0, a0
> - ctzw a0, a0
> - cpopw a0, a0
> - rolw a0, a1, a2
> - rorw a0, a1, a2
> - rorw a0, a1, 2
> - roriw a0, a1, 2
> - sh1add.uw a0, a1, a2
> - sh2add.uw a0, a1, a2
> - sh3add.uw a0, a1, a2
> - add.uw a0, a1, a2
> - zext.w a0, a1
> - slli.uw a0, a1, 2
> - bclri a0, a1, 0
> - bclri a0, a1, 31
> - bseti a0, a1, 0
> - bseti a0, a1, 31
> - binvi a0, a1, 0
> - binvi a0, a1, 31
> - bexti a0, a1, 0
> - bexti a0, a1, 31
> - bclri a0, a1, 63
> - bseti a0, a1, 63
> - binvi a0, a1, 63
> - bexti a0, a1, 63
> - bclr a0, a1, a2
> - bset a0, a1, a2
> - binv a0, a1, a2
> - bext a0, a1, a2
> - #aliases
> - bclr a0, a1, 31
> - bset a0, a1, 31
> - binv a0, a1, 31
> - bext a0, a1, 31
> - bclr a0, a1, 63
> - bset a0, a1, 63
> - binv a0, a1, 63
> - bext a0, a1, 63
> diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d
> deleted file mode 100644
> index 6bbbeb0f96b..00000000000
> --- a/gas/testsuite/gas/riscv/b-ext.d
> +++ /dev/null
> @@ -1,51 +0,0 @@
> -#as: -march=rv32i_zba_zbb_zbc_zbs
> -#source: b-ext.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+0:[ ]+60051513[ ]+clz[ ]+a0,a0
> -[ ]+4:[ ]+60151513[ ]+ctz[ ]+a0,a0
> -[ ]+8:[ ]+60251513[ ]+cpop[ ]+a0,a0
> -[ ]+c:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
> -[ ]+10:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
> -[ ]+14:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
> -[ ]+18:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
> -[ ]+1c:[ ]+60451513[ ]+sext.b[ ]+a0,a0
> -[ ]+20:[ ]+60551513[ ]+sext.h[ ]+a0,a0
> -[ ]+24:[ ]+08054533[ ]+zext.h[ ]+a0,a0
> -[ ]+28:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
> -[ ]+2c:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
> -[ ]+30:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
> -[ ]+34:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
> -[ ]+38:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
> -[ ]+3c:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
> -[ ]+40:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
> -[ ]+44:[ ]+69855513[ ]+rev8[ ]+a0,a0
> -[ ]+48:[ ]+28755513[ ]+orc.b[ ]+a0,a0
> -[ ]+4c:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
> -[ ]+50:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
> -[ ]+54:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
> -[ ]+58:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
> -[ ]+5c:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
> -[ ]+60:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+48059513[ ]+bclr[ ]+a0,a1,0x0
> -[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclr[ ]+a0,a1,0x1f
> -[ ]+[0-9a-f]+:[ ]+28059513[ ]+bset[ ]+a0,a1,0x0
> -[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bset[ ]+a0,a1,0x1f
> -[ ]+[0-9a-f]+:[ ]+68059513[ ]+binv[ ]+a0,a1,0x0
> -[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binv[ ]+a0,a1,0x1f
> -[ ]+[0-9a-f]+:[ ]+4805d513[ ]+bext[ ]+a0,a1,0x0
> -[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bext[ ]+a0,a1,0x1f
> -[ ]+[0-9a-f]+:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclr[ ]+a0,a1,0x1f
> -[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bset[ ]+a0,a1,0x1f
> -[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binv[ ]+a0,a1,0x1f
> -[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bext[ ]+a0,a1,0x1f
> diff --git a/gas/testsuite/gas/riscv/b-ext.s b/gas/testsuite/gas/riscv/b-ext.s
> deleted file mode 100644
> index 9de3fc32806..00000000000
> --- a/gas/testsuite/gas/riscv/b-ext.s
> +++ /dev/null
> @@ -1,43 +0,0 @@
> -target:
> - clz a0, a0
> - ctz a0, a0
> - cpop a0, a0
> - min a0, a1, a2
> - minu a0, a1, a2
> - max a0, a1, a2
> - maxu a0, a1, a2
> - sext.b a0, a0
> - sext.h a0, a0
> - zext.h a0, a0
> - andn a0, a1, a2
> - orn a0, a1, a2
> - xnor a0, a1, a2
> - rol a0, a1, a2
> - ror a0, a1, a2
> - ror a0, a1, 2
> - rori a0, a1, 2
> - rev8 a0, a0
> - orc.b a0, a0
> - sh1add a0, a1, a2
> - sh2add a0, a1, a2
> - sh3add a0, a1, a2
> - clmul a0, a1, a2
> - clmulh a0, a1, a2
> - clmulr a0, a1, a2
> - bclri a0, a1, 0
> - bclri a0, a1, 31
> - bseti a0, a1, 0
> - bseti a0, a1, 31
> - binvi a0, a1, 0
> - binvi a0, a1, 31
> - bexti a0, a1, 0
> - bexti a0, a1, 31
> - bclr a0, a1, a2
> - bset a0, a1, a2
> - binv a0, a1, a2
> - bext a0, a1, a2
> - #aliases
> - bclr a0, a1, 31
> - bset a0, a1, 31
> - binv a0, a1, 31
> - bext a0, a1, 31
> diff --git a/gas/testsuite/gas/riscv/b-ext-na.d b/gas/testsuite/gas/riscv/zb-ext-32-noalias.d
> similarity index 67%
> rename from gas/testsuite/gas/riscv/b-ext-na.d
> rename to gas/testsuite/gas/riscv/zb-ext-32-noalias.d
> index 0c80a379fae..2d532321910 100644
> --- a/gas/testsuite/gas/riscv/b-ext-na.d
> +++ b/gas/testsuite/gas/riscv/zb-ext-32-noalias.d
> @@ -1,6 +1,6 @@
> -#as: -march=rv32i_zba_zbb_zbc_zbs
> -#source: b-ext.s
> -#objdump: -d -Mno-aliases
> +#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32
> +#source: zb-ext.s
> +#objdump: -d -M no-aliases
>
> .*:[ ]+file format .*
>
> @@ -8,28 +8,28 @@
> Disassembly of section .text:
>
> 0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+60051513[ ]+clz[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+60151513[ ]+ctz[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+60251513[ ]+cpop[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60059513[ ]+clz[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+60159513[ ]+ctz[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+60259513[ ]+cpop[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+60451513[ ]+sext\.b[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+60551513[ ]+sext\.h[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+08054533[ ]+zext\.h[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+60459513[ ]+sext\.b[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+60559513[ ]+sext\.h[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+0805c533[ ]+zext\.h[ ]+a0,a1
> [ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
> +[ ]+[0-9a-f]+:[ ]+6985d513[ ]+rev8[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+2875d513[ ]+orc\.b[ ]+a0,a1
> [ ]+[0-9a-f]+:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
> -[ ]+[0-9a-f]+:[ ]+69855513[ ]+rev8[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+28755513[ ]+orc\.b[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
> diff --git a/gas/testsuite/gas/riscv/zb-ext-32-noarch.d b/gas/testsuite/gas/riscv/zb-ext-32-noarch.d
> new file mode 100644
> index 00000000000..e9a2c0dda07
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zb-ext-32-noarch.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32 -defsym NOARCH=1
> +#source: zb-ext.s
> +#error_output: zb-ext-32-noarch.l
> diff --git a/gas/testsuite/gas/riscv/zb-ext-32-noarch.l b/gas/testsuite/gas/riscv/zb-ext-32-noarch.l
> new file mode 100644
> index 00000000000..16859b86ad9
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zb-ext-32-noarch.l
> @@ -0,0 +1,60 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `sh1add a0,a1,a2', extension `zba' required
> +.*: Error: unrecognized opcode `sh2add a0,a1,a2', extension `zba' required
> +.*: Error: unrecognized opcode `sh3add a0,a1,a2', extension `zba' required
> +.*: Error: unrecognized opcode `sh1add\.uw a0,a1,a2'
> +.*: Error: unrecognized opcode `sh2add\.uw a0,a1,a2'
> +.*: Error: unrecognized opcode `sh3add\.uw a0,a1,a2'
> +.*: Error: unrecognized opcode `add\.uw a0,a1,a2'
> +.*: Error: unrecognized opcode `slli\.uw a0,a1,2'
> +.*: Error: unrecognized opcode `zext\.w a0,a1'
> +.*: Error: unrecognized opcode `clz a0,a1', extension `zbb' required
> +.*: Error: unrecognized opcode `ctz a0,a1', extension `zbb' required
> +.*: Error: unrecognized opcode `cpop a0,a1', extension `zbb' required
> +.*: Error: unrecognized opcode `min a0,a1,a2', extension `zbb' required
> +.*: Error: unrecognized opcode `minu a0,a1,a2', extension `zbb' required
> +.*: Error: unrecognized opcode `max a0,a1,a2', extension `zbb' required
> +.*: Error: unrecognized opcode `maxu a0,a1,a2', extension `zbb' required
> +.*: Error: unrecognized opcode `andn a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `orn a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `xnor a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `rol a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `ror a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `rori a0,a1,2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `rev8 a0,a1', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `orc\.b a0,a1', extension `zbb' required
> +.*: Error: unrecognized opcode `clzw a0,a1'
> +.*: Error: unrecognized opcode `ctzw a0,a1'
> +.*: Error: unrecognized opcode `cpopw a0,a1'
> +.*: Error: unrecognized opcode `rolw a0,a1,a2'
> +.*: Error: unrecognized opcode `rorw a0,a1,a2'
> +.*: Error: unrecognized opcode `roriw a0,a1,2'
> +.*: Error: unrecognized opcode `ror a0,a1,2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `rorw a0,a1,2'
> +.*: Error: unrecognized opcode `clmul a0,a1,a2', extension `zbc' or `zbkc' required
> +.*: Error: unrecognized opcode `clmulh a0,a1,a2', extension `zbc' or `zbkc' required
> +.*: Error: unrecognized opcode `clmulr a0,a1,a2', extension `zbc' required
> +.*: Error: unrecognized opcode `bclri a0,a1,0', extension `zbs' required
> +.*: Error: unrecognized opcode `bclri a0,a1,31', extension `zbs' required
> +.*: Error: unrecognized opcode `bseti a0,a1,0', extension `zbs' required
> +.*: Error: unrecognized opcode `bseti a0,a1,31', extension `zbs' required
> +.*: Error: unrecognized opcode `binvi a0,a1,0', extension `zbs' required
> +.*: Error: unrecognized opcode `binvi a0,a1,31', extension `zbs' required
> +.*: Error: unrecognized opcode `bexti a0,a1,0', extension `zbs' required
> +.*: Error: unrecognized opcode `bexti a0,a1,31', extension `zbs' required
> +.*: Error: unrecognized opcode `bclr a0,a1,a2', extension `zbs' required
> +.*: Error: unrecognized opcode `bset a0,a1,a2', extension `zbs' required
> +.*: Error: unrecognized opcode `binv a0,a1,a2', extension `zbs' required
> +.*: Error: unrecognized opcode `bext a0,a1,a2', extension `zbs' required
> +.*: Error: unrecognized opcode `bclr a0,a1,31', extension `zbs' required
> +.*: Error: unrecognized opcode `bset a0,a1,31', extension `zbs' required
> +.*: Error: unrecognized opcode `binv a0,a1,31', extension `zbs' required
> +.*: Error: unrecognized opcode `bext a0,a1,31', extension `zbs' required
> +.*: Error: unrecognized opcode `bclri a0,a1,63', extension `zbs' required
> +.*: Error: unrecognized opcode `bseti a0,a1,63', extension `zbs' required
> +.*: Error: unrecognized opcode `binvi a0,a1,63', extension `zbs' required
> +.*: Error: unrecognized opcode `bexti a0,a1,63', extension `zbs' required
> +.*: Error: unrecognized opcode `bclr a0,a1,63', extension `zbs' required
> +.*: Error: unrecognized opcode `bset a0,a1,63', extension `zbs' required
> +.*: Error: unrecognized opcode `binv a0,a1,63', extension `zbs' required
> +.*: Error: unrecognized opcode `bext a0,a1,63', extension `zbs' required
> diff --git a/gas/testsuite/gas/riscv/zb-ext-32.d b/gas/testsuite/gas/riscv/zb-ext-32.d
> new file mode 100644
> index 00000000000..419f36a0745
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zb-ext-32.d
> @@ -0,0 +1,51 @@
> +#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32
> +#source: zb-ext.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60059513[ ]+clz[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+60159513[ ]+ctz[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+60259513[ ]+cpop[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60459513[ ]+sext\.b[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+60559513[ ]+sext\.h[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+0805c533[ ]+zext\.h[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
> +[ ]+[0-9a-f]+:[ ]+6985d513[ ]+rev8[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+2875d513[ ]+orc\.b[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
> +[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+48059513[ ]+bclr[ ]+a0,a1,0x0
> +[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclr[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+28059513[ ]+bset[ ]+a0,a1,0x0
> +[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bset[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+68059513[ ]+binv[ ]+a0,a1,0x0
> +[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binv[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+4805d513[ ]+bext[ ]+a0,a1,0x0
> +[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bext[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclr[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bset[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binv[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bext[ ]+a0,a1,0x1f
> diff --git a/gas/testsuite/gas/riscv/b-ext-64-na.d b/gas/testsuite/gas/riscv/zb-ext-64-noalias.d
> similarity index 73%
> rename from gas/testsuite/gas/riscv/b-ext-64-na.d
> rename to gas/testsuite/gas/riscv/zb-ext-64-noalias.d
> index ec5acd017ed..341eb22eb1b 100644
> --- a/gas/testsuite/gas/riscv/b-ext-64-na.d
> +++ b/gas/testsuite/gas/riscv/zb-ext-64-noalias.d
> @@ -1,6 +1,6 @@
> -#as: -march=rv64i_zba_zbb_zbc_zbs
> -#source: b-ext-64.s
> -#objdump: -d -Mno-aliases
> +#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64
> +#source: zb-ext.s
> +#objdump: -d -M no-aliases
>
> .*:[ ]+file format .*
>
> @@ -8,44 +8,44 @@
> Disassembly of section .text:
>
> 0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+60051513[ ]+clz[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+60151513[ ]+ctz[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+60251513[ ]+cpop[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c5a53b[ ]+sh1add\.uw[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c5c53b[ ]+sh2add\.uw[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c5e53b[ ]+sh3add\.uw[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+08c5853b[ ]+add\.uw[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0825951b[ ]+slli\.uw[ ]+a0,a1,0x2
> +[ ]+[0-9a-f]+:[ ]+0805853b[ ]+add\.uw[ ]+a0,a1,zero
> +[ ]+[0-9a-f]+:[ ]+60059513[ ]+clz[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+60159513[ ]+ctz[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+60259513[ ]+cpop[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+60451513[ ]+sext\.b[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+60551513[ ]+sext\.h[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+0805453b[ ]+zext\.h[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+60459513[ ]+sext\.b[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+60559513[ ]+sext\.h[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+0805c53b[ ]+zext\.h[ ]+a0,a1
> [ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
> -[ ]+[0-9a-f]+:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
> -[ ]+[0-9a-f]+:[ ]+6b855513[ ]+rev8[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+28755513[ ]+orc\.b[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+6005151b[ ]+clzw[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+6015151b[ ]+ctzw[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+6025151b[ ]+cpopw[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+6b85d513[ ]+rev8[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+2875d513[ ]+orc\.b[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+6005951b[ ]+clzw[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+6015951b[ ]+ctzw[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+6025951b[ ]+cpopw[ ]+a0,a1
> [ ]+[0-9a-f]+:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+6025d51b[ ]+roriw[ ]+a0,a1,0x2
> +[ ]+[0-9a-f]+:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
> [ ]+[0-9a-f]+:[ ]+6025d51b[ ]+roriw[ ]+a0,a1,0x2
> -[ ]+[0-9a-f]+:[ ]+20c5a53b[ ]+sh1add\.uw[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+20c5c53b[ ]+sh2add\.uw[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+20c5e53b[ ]+sh3add\.uw[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+08c5853b[ ]+add\.uw[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+0805853b[ ]+add\.uw[ ]+a0,a1,zero
> -[ ]+[0-9a-f]+:[ ]+0825951b[ ]+slli\.uw[ ]+a0,a1,0x2
> +[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+48059513[ ]+bclri[ ]+a0,a1,0x0
> [ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclri[ ]+a0,a1,0x1f
> [ ]+[0-9a-f]+:[ ]+28059513[ ]+bseti[ ]+a0,a1,0x0
> @@ -54,10 +54,6 @@ Disassembly of section .text:
> [ ]+[0-9a-f]+:[ ]+69f59513[ ]+binvi[ ]+a0,a1,0x1f
> [ ]+[0-9a-f]+:[ ]+4805d513[ ]+bexti[ ]+a0,a1,0x0
> [ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bexti[ ]+a0,a1,0x1f
> -[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclri[ ]+a0,a1,0x3f
> -[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bseti[ ]+a0,a1,0x3f
> -[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binvi[ ]+a0,a1,0x3f
> -[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bexti[ ]+a0,a1,0x3f
> [ ]+[0-9a-f]+:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
> @@ -70,3 +66,7 @@ Disassembly of section .text:
> [ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bseti[ ]+a0,a1,0x3f
> [ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binvi[ ]+a0,a1,0x3f
> [ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bexti[ ]+a0,a1,0x3f
> +[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclri[ ]+a0,a1,0x3f
> +[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bseti[ ]+a0,a1,0x3f
> +[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binvi[ ]+a0,a1,0x3f
> +[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bexti[ ]+a0,a1,0x3f
> diff --git a/gas/testsuite/gas/riscv/zb-ext-64-noarch.d b/gas/testsuite/gas/riscv/zb-ext-64-noarch.d
> new file mode 100644
> index 00000000000..3655678814f
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zb-ext-64-noarch.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64 -defsym NOARCH=1
> +#source: zb-ext.s
> +#error_output: zb-ext-64-noarch.l
> diff --git a/gas/testsuite/gas/riscv/zb-ext-64-noarch.l b/gas/testsuite/gas/riscv/zb-ext-64-noarch.l
> new file mode 100644
> index 00000000000..9b358fb3b55
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zb-ext-64-noarch.l
> @@ -0,0 +1,59 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `sh1add a0,a1,a2', extension `zba' required
> +.*: Error: unrecognized opcode `sh2add a0,a1,a2', extension `zba' required
> +.*: Error: unrecognized opcode `sh3add a0,a1,a2', extension `zba' required
> +.*: Error: unrecognized opcode `sh1add\.uw a0,a1,a2', extension `zba' required
> +.*: Error: unrecognized opcode `sh2add\.uw a0,a1,a2', extension `zba' required
> +.*: Error: unrecognized opcode `sh3add\.uw a0,a1,a2', extension `zba' required
> +.*: Error: unrecognized opcode `add\.uw a0,a1,a2', extension `zba' required
> +.*: Error: unrecognized opcode `slli\.uw a0,a1,2', extension `zba' required
> +.*: Error: unrecognized opcode `clz a0,a1', extension `zbb' required
> +.*: Error: unrecognized opcode `ctz a0,a1', extension `zbb' required
> +.*: Error: unrecognized opcode `cpop a0,a1', extension `zbb' required
> +.*: Error: unrecognized opcode `min a0,a1,a2', extension `zbb' required
> +.*: Error: unrecognized opcode `minu a0,a1,a2', extension `zbb' required
> +.*: Error: unrecognized opcode `max a0,a1,a2', extension `zbb' required
> +.*: Error: unrecognized opcode `maxu a0,a1,a2', extension `zbb' required
> +.*: Error: unrecognized opcode `andn a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `orn a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `xnor a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `rol a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `ror a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `rori a0,a1,2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `rev8 a0,a1', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `orc\.b a0,a1', extension `zbb' required
> +.*: Error: unrecognized opcode `clzw a0,a1', extension `zbb' required
> +.*: Error: unrecognized opcode `ctzw a0,a1', extension `zbb' required
> +.*: Error: unrecognized opcode `cpopw a0,a1', extension `zbb' required
> +.*: Error: unrecognized opcode `rolw a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `rorw a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `roriw a0,a1,2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `ror a0,a1,2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `rorw a0,a1,2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `clmul a0,a1,a2', extension `zbc' or `zbkc' required
> +.*: Error: unrecognized opcode `clmulh a0,a1,a2', extension `zbc' or `zbkc' required
> +.*: Error: unrecognized opcode `clmulr a0,a1,a2', extension `zbc' required
> +.*: Error: unrecognized opcode `bclri a0,a1,0', extension `zbs' required
> +.*: Error: unrecognized opcode `bclri a0,a1,31', extension `zbs' required
> +.*: Error: unrecognized opcode `bseti a0,a1,0', extension `zbs' required
> +.*: Error: unrecognized opcode `bseti a0,a1,31', extension `zbs' required
> +.*: Error: unrecognized opcode `binvi a0,a1,0', extension `zbs' required
> +.*: Error: unrecognized opcode `binvi a0,a1,31', extension `zbs' required
> +.*: Error: unrecognized opcode `bexti a0,a1,0', extension `zbs' required
> +.*: Error: unrecognized opcode `bexti a0,a1,31', extension `zbs' required
> +.*: Error: unrecognized opcode `bclr a0,a1,a2', extension `zbs' required
> +.*: Error: unrecognized opcode `bset a0,a1,a2', extension `zbs' required
> +.*: Error: unrecognized opcode `binv a0,a1,a2', extension `zbs' required
> +.*: Error: unrecognized opcode `bext a0,a1,a2', extension `zbs' required
> +.*: Error: unrecognized opcode `bclr a0,a1,31', extension `zbs' required
> +.*: Error: unrecognized opcode `bset a0,a1,31', extension `zbs' required
> +.*: Error: unrecognized opcode `binv a0,a1,31', extension `zbs' required
> +.*: Error: unrecognized opcode `bext a0,a1,31', extension `zbs' required
> +.*: Error: unrecognized opcode `bclri a0,a1,63', extension `zbs' required
> +.*: Error: unrecognized opcode `bseti a0,a1,63', extension `zbs' required
> +.*: Error: unrecognized opcode `binvi a0,a1,63', extension `zbs' required
> +.*: Error: unrecognized opcode `bexti a0,a1,63', extension `zbs' required
> +.*: Error: unrecognized opcode `bclr a0,a1,63', extension `zbs' required
> +.*: Error: unrecognized opcode `bset a0,a1,63', extension `zbs' required
> +.*: Error: unrecognized opcode `binv a0,a1,63', extension `zbs' required
> +.*: Error: unrecognized opcode `bext a0,a1,63', extension `zbs' required
> diff --git a/gas/testsuite/gas/riscv/zb-ext-64.d b/gas/testsuite/gas/riscv/zb-ext-64.d
> new file mode 100644
> index 00000000000..df206c0f298
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zb-ext-64.d
> @@ -0,0 +1,72 @@
> +#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64
> +#source: zb-ext.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c5a53b[ ]+sh1add\.uw[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c5c53b[ ]+sh2add\.uw[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c5e53b[ ]+sh3add\.uw[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+08c5853b[ ]+add\.uw[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0825951b[ ]+slli\.uw[ ]+a0,a1,0x2
> +[ ]+[0-9a-f]+:[ ]+0805853b[ ]+zext\.w[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+60059513[ ]+clz[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+60159513[ ]+ctz[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+60259513[ ]+cpop[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60459513[ ]+sext\.b[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+60559513[ ]+sext\.h[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+0805c53b[ ]+zext\.h[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
> +[ ]+[0-9a-f]+:[ ]+6b85d513[ ]+rev8[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+2875d513[ ]+orc\.b[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+6005951b[ ]+clzw[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+6015951b[ ]+ctzw[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+6025951b[ ]+cpopw[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+6025d51b[ ]+rorw[ ]+a0,a1,0x2
> +[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
> +[ ]+[0-9a-f]+:[ ]+6025d51b[ ]+rorw[ ]+a0,a1,0x2
> +[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+48059513[ ]+bclr[ ]+a0,a1,0x0
> +[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclr[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+28059513[ ]+bset[ ]+a0,a1,0x0
> +[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bset[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+68059513[ ]+binv[ ]+a0,a1,0x0
> +[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binv[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+4805d513[ ]+bext[ ]+a0,a1,0x0
> +[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bext[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclr[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bset[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binv[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bext[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclr[ ]+a0,a1,0x3f
> +[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bset[ ]+a0,a1,0x3f
> +[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binv[ ]+a0,a1,0x3f
> +[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bext[ ]+a0,a1,0x3f
> +[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclr[ ]+a0,a1,0x3f
> +[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bset[ ]+a0,a1,0x3f
> +[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binv[ ]+a0,a1,0x3f
> +[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bext[ ]+a0,a1,0x3f
> diff --git a/gas/testsuite/gas/riscv/zb-ext.s b/gas/testsuite/gas/riscv/zb-ext.s
> new file mode 100644
> index 00000000000..2489fcd47c2
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zb-ext.s
> @@ -0,0 +1,84 @@
> +.include "testutils.inc"
> +
> +target:
> + SET_ARCH_START +zba
> + sh1add a0, a1, a2
> + sh2add a0, a1, a2
> + sh3add a0, a1, a2
> +.if XLEN_GE_64
> + sh1add.uw a0, a1, a2
> + sh2add.uw a0, a1, a2
> + sh3add.uw a0, a1, a2
> + add.uw a0, a1, a2
> + slli.uw a0, a1, 2
> + zext.w a0, a1 # Alias (has RVI macro)
> +.endif
> + SET_ARCH_END
> +
> + SET_ARCH_START +zbb
> + clz a0, a1
> + ctz a0, a1
> + cpop a0, a1
> + min a0, a1, a2
> + minu a0, a1, a2
> + max a0, a1, a2
> + maxu a0, a1, a2
> + sext.b a0, a1 # Has RVI macro
> + sext.h a0, a1 # Has RVI macro
> + zext.h a0, a1 # Has RVI macro
> + andn a0, a1, a2
> + orn a0, a1, a2
> + xnor a0, a1, a2
> + rol a0, a1, a2
> + ror a0, a1, a2
> + rori a0, a1, 2
> + rev8 a0, a1
> + orc.b a0, a1
> +.if XLEN_GE_64
> + clzw a0, a1
> + ctzw a0, a1
> + cpopw a0, a1
> + rolw a0, a1, a2
> + rorw a0, a1, a2
> + roriw a0, a1, 2
> +.endif
> + ror a0, a1, 2 # Alias
> +.if XLEN_GE_64
> + rorw a0, a1, 2 # Alias
> +.endif
> + SET_ARCH_END
> +
> + SET_ARCH_START +zbc
> + clmul a0, a1, a2
> + clmulh a0, a1, a2
> + clmulr a0, a1, a2
> + SET_ARCH_END
> +
> + SET_ARCH_START +zbs
> + bclri a0, a1, 0
> + bclri a0, a1, 31
> + bseti a0, a1, 0
> + bseti a0, a1, 31
> + binvi a0, a1, 0
> + binvi a0, a1, 31
> + bexti a0, a1, 0
> + bexti a0, a1, 31
> + bclr a0, a1, a2
> + bset a0, a1, a2
> + binv a0, a1, a2
> + bext a0, a1, a2
> + bclr a0, a1, 31 # Alias
> + bset a0, a1, 31 # Alias
> + binv a0, a1, 31 # Alias
> + bext a0, a1, 31 # Alias
> +.if XLEN_GE_64
> + bclri a0, a1, 63
> + bseti a0, a1, 63
> + binvi a0, a1, 63
> + bexti a0, a1, 63
> + bclr a0, a1, 63 # Alias
> + bset a0, a1, 63 # Alias
> + binv a0, a1, 63 # Alias
> + bext a0, a1, 63 # Alias
> +.endif
> + SET_ARCH_END
Something like,
...
.option arch, +zbs
bclri a0, a1, 0
...
.option arch, rv64i_zbs
bclri a0, a1, 63
...
Nelson
> --
> 2.37.2
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 12/12] RISC-V: Combine/enhance 'Zk*'/'Zbk*' extension tests
2022-11-05 12:29 ` [PATCH 12/12] RISC-V: Combine/enhance 'Zk*'/'Zbk*' " Tsukasa OI
@ 2022-11-29 9:00 ` Nelson Chu
0 siblings, 0 replies; 26+ messages in thread
From: Nelson Chu @ 2022-11-29 9:00 UTC (permalink / raw)
To: Tsukasa OI; +Cc: Kito Cheng, Palmer Dabbelt, binutils
On Sat, Nov 5, 2022 at 8:31 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> This commit combines tests for 'Zk*' and 'Zbk*' extensions and adds
> "no required extension" testcases based on new test utilities. It also
> contains minor tidying (such as using different registers per operand).
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/zbk-ext.s: Combine zbkb-{32,64}.s, zbkc.s
> and zbkx.s. Use different register per operand.
> * testsuite/gas/riscv/zbk-ext-32.d: Combine zbk[bcx]-32.d.
> Reflect zbk-ext.s changes.
> * testsuite/gas/riscv/zbk-ext-64.d: Combine zbk[bcx]-64.d.
> Reflect zbk-ext.s changes.
> * testsuite/gas/riscv/zbk-ext-32-noalias.d: New test based on the
> concept of zbkb-32-na.d and the code based on zbk-ext-32.d.
> * testsuite/gas/riscv/zbk-ext-64-noalias.d: Likewise but new.
> * testsuite/gas/riscv/zbk-ext-32-noarch.d: New test.
> * testsuite/gas/riscv/zbk-ext-32-noarch.l: Likewise.
> * testsuite/gas/riscv/zbk-ext-64-noarch.d: New test.
> * testsuite/gas/riscv/zbk-ext-64-noarch.l: Likewise.
> * testsuite/gas/riscv/zk-ext-32.s: Combine zkn*-32.s, zksed.s
> and zksh.s. Use different register per operand.
> * testsuite/gas/riscv/zk-ext-32.d: Combine zk[ns]*-32.d.
> Reflect zk-ext-32.s changes.
> * testsuite/gas/riscv/zk-ext-64.s: Combine zkn*-64.s, zksed.s
> and zksh.s. Use different register per operand.
> * testsuite/gas/riscv/zk-ext-64.d: Combine zk[ns]*-64.d.
> Reflect zk-ext-64.s changes.
> * testsuite/gas/riscv/zk-ext-32-noarch.d: New test.
> * testsuite/gas/riscv/zk-ext-32-noarch.l: Likewise.
> * testsuite/gas/riscv/zk-ext-64-noarch.d: New test.
> * testsuite/gas/riscv/zk-ext-64-noarch.l: Likewise.
> * testsuite/gas/riscv/zkt.d: Separate test for the 'Zkt' extension
> whether this extension is supported through -march.
> * testsuite/gas/riscv/k-ext.s: Removed as duplicate.
> * testsuite/gas/riscv/k-ext.d: Removed as duplicate.
> * testsuite/gas/riscv/k-ext-64.s: Removed as duplicate.
> * testsuite/gas/riscv/k-ext-64.d: Removed as duplicate.
> * testsuite/gas/riscv/zbkb-32.s: Removed.
> * testsuite/gas/riscv/zbkb-32.d: Removed.
> * testsuite/gas/riscv/zbkb-32-na.d: Removed.
> * testsuite/gas/riscv/zbkb-64.s: Removed.
> * testsuite/gas/riscv/zbkb-64.d: Removed.
> * testsuite/gas/riscv/zbkc.s: Removed.
> * testsuite/gas/riscv/zbkc-32.d: Removed.
> * testsuite/gas/riscv/zbkc-64.d: Removed.
> * testsuite/gas/riscv/zbkx.s: Removed.
> * testsuite/gas/riscv/zbkx-32.d: Removed.
> * testsuite/gas/riscv/zbkx-64.d: Removed.
> * testsuite/gas/riscv/zknd-32.s: Removed.
> * testsuite/gas/riscv/zknd-32.d: Removed.
> * testsuite/gas/riscv/zknd-64.s: Removed.
> * testsuite/gas/riscv/zknd-64.d: Removed.
> * testsuite/gas/riscv/zkne-32.s: Removed.
> * testsuite/gas/riscv/zkne-32.d: Removed.
> * testsuite/gas/riscv/zkne-64.s: Removed.
> * testsuite/gas/riscv/zkne-64.d: Removed.
> * testsuite/gas/riscv/zknh-32.s: Removed.
> * testsuite/gas/riscv/zknh-32.d: Removed.
> * testsuite/gas/riscv/zknh-64.s: Removed.
> * testsuite/gas/riscv/zknh-64.d: Removed.
> * testsuite/gas/riscv/zksed.s: Removed.
> * testsuite/gas/riscv/zksed-32.d: Removed.
> * testsuite/gas/riscv/zksed-64.d: Removed.
> * testsuite/gas/riscv/zksh.s: Removed.
> * testsuite/gas/riscv/zksh-32.d: Removed.
> * testsuite/gas/riscv/zksh-64.d: Removed.
> ---
> gas/testsuite/gas/riscv/k-ext-64.d | 47 --------------------
> gas/testsuite/gas/riscv/k-ext-64.s | 38 ----------------
> gas/testsuite/gas/riscv/k-ext.d | 44 ------------------
> gas/testsuite/gas/riscv/k-ext.s | 35 ---------------
> gas/testsuite/gas/riscv/zbk-ext-32-noalias.d | 26 +++++++++++
> gas/testsuite/gas/riscv/zbk-ext-32-noarch.d | 3 ++
> gas/testsuite/gas/riscv/zbk-ext-32-noarch.l | 21 +++++++++
> gas/testsuite/gas/riscv/zbk-ext-32.d | 26 +++++++++++
> gas/testsuite/gas/riscv/zbk-ext-64-noalias.d | 28 ++++++++++++
> gas/testsuite/gas/riscv/zbk-ext-64-noarch.d | 3 ++
> gas/testsuite/gas/riscv/zbk-ext-64-noarch.l | 21 +++++++++
> gas/testsuite/gas/riscv/zbk-ext-64.d | 28 ++++++++++++
> gas/testsuite/gas/riscv/zbk-ext.s | 37 +++++++++++++++
> gas/testsuite/gas/riscv/zbkb-32-na.d | 23 ----------
> gas/testsuite/gas/riscv/zbkb-32.d | 22 ---------
> gas/testsuite/gas/riscv/zbkb-32.s | 13 ------
> gas/testsuite/gas/riscv/zbkb-64.d | 24 ----------
> gas/testsuite/gas/riscv/zbkb-64.s | 15 -------
> gas/testsuite/gas/riscv/zbkc-32.d | 12 -----
> gas/testsuite/gas/riscv/zbkc-64.d | 12 -----
> gas/testsuite/gas/riscv/zbkc.s | 3 --
> gas/testsuite/gas/riscv/zbkx-32.d | 12 -----
> gas/testsuite/gas/riscv/zbkx-64.d | 12 -----
> gas/testsuite/gas/riscv/zbkx.s | 3 --
> gas/testsuite/gas/riscv/zk-ext-32-noarch.d | 3 ++
> gas/testsuite/gas/riscv/zk-ext-32-noarch.l | 20 +++++++++
> gas/testsuite/gas/riscv/zk-ext-32.d | 28 ++++++++++++
> gas/testsuite/gas/riscv/zk-ext-32.s | 41 +++++++++++++++++
> gas/testsuite/gas/riscv/zk-ext-64-noarch.d | 3 ++
> gas/testsuite/gas/riscv/zk-ext-64-noarch.l | 23 ++++++++++
> gas/testsuite/gas/riscv/zk-ext-64.d | 31 +++++++++++++
> gas/testsuite/gas/riscv/zk-ext-64.s | 44 ++++++++++++++++++
> gas/testsuite/gas/riscv/zknd-32.d | 12 -----
> gas/testsuite/gas/riscv/zknd-32.s | 3 --
> gas/testsuite/gas/riscv/zknd-64.d | 15 -------
> gas/testsuite/gas/riscv/zknd-64.s | 6 ---
> gas/testsuite/gas/riscv/zkne-32.d | 12 -----
> gas/testsuite/gas/riscv/zkne-32.s | 3 --
> gas/testsuite/gas/riscv/zkne-64.d | 14 ------
> gas/testsuite/gas/riscv/zkne-64.s | 5 ---
> gas/testsuite/gas/riscv/zknh-32.d | 20 ---------
> gas/testsuite/gas/riscv/zknh-32.s | 11 -----
> gas/testsuite/gas/riscv/zknh-64.d | 18 --------
> gas/testsuite/gas/riscv/zknh-64.s | 9 ----
> gas/testsuite/gas/riscv/zksed-32.d | 12 -----
> gas/testsuite/gas/riscv/zksed-64.d | 12 -----
> gas/testsuite/gas/riscv/zksed.s | 3 --
> gas/testsuite/gas/riscv/zksh-32.d | 12 -----
> gas/testsuite/gas/riscv/zksh-64.d | 12 -----
> gas/testsuite/gas/riscv/zksh.s | 3 --
> gas/testsuite/gas/riscv/zkt.d | 5 +++
> 51 files changed, 391 insertions(+), 497 deletions(-)
> delete mode 100644 gas/testsuite/gas/riscv/k-ext-64.d
> delete mode 100644 gas/testsuite/gas/riscv/k-ext-64.s
> delete mode 100644 gas/testsuite/gas/riscv/k-ext.d
> delete mode 100644 gas/testsuite/gas/riscv/k-ext.s
> create mode 100644 gas/testsuite/gas/riscv/zbk-ext-32-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/zbk-ext-32-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zbk-ext-32-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/zbk-ext-32.d
> create mode 100644 gas/testsuite/gas/riscv/zbk-ext-64-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/zbk-ext-64-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zbk-ext-64-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/zbk-ext-64.d
> create mode 100644 gas/testsuite/gas/riscv/zbk-ext.s
> delete mode 100644 gas/testsuite/gas/riscv/zbkb-32-na.d
> delete mode 100644 gas/testsuite/gas/riscv/zbkb-32.d
> delete mode 100644 gas/testsuite/gas/riscv/zbkb-32.s
> delete mode 100644 gas/testsuite/gas/riscv/zbkb-64.d
> delete mode 100644 gas/testsuite/gas/riscv/zbkb-64.s
> delete mode 100644 gas/testsuite/gas/riscv/zbkc-32.d
> delete mode 100644 gas/testsuite/gas/riscv/zbkc-64.d
> delete mode 100644 gas/testsuite/gas/riscv/zbkc.s
> delete mode 100644 gas/testsuite/gas/riscv/zbkx-32.d
> delete mode 100644 gas/testsuite/gas/riscv/zbkx-64.d
> delete mode 100644 gas/testsuite/gas/riscv/zbkx.s
> create mode 100644 gas/testsuite/gas/riscv/zk-ext-32-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zk-ext-32-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/zk-ext-32.d
> create mode 100644 gas/testsuite/gas/riscv/zk-ext-32.s
> create mode 100644 gas/testsuite/gas/riscv/zk-ext-64-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/zk-ext-64-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/zk-ext-64.d
> create mode 100644 gas/testsuite/gas/riscv/zk-ext-64.s
> delete mode 100644 gas/testsuite/gas/riscv/zknd-32.d
> delete mode 100644 gas/testsuite/gas/riscv/zknd-32.s
> delete mode 100644 gas/testsuite/gas/riscv/zknd-64.d
> delete mode 100644 gas/testsuite/gas/riscv/zknd-64.s
> delete mode 100644 gas/testsuite/gas/riscv/zkne-32.d
> delete mode 100644 gas/testsuite/gas/riscv/zkne-32.s
> delete mode 100644 gas/testsuite/gas/riscv/zkne-64.d
> delete mode 100644 gas/testsuite/gas/riscv/zkne-64.s
> delete mode 100644 gas/testsuite/gas/riscv/zknh-32.d
> delete mode 100644 gas/testsuite/gas/riscv/zknh-32.s
> delete mode 100644 gas/testsuite/gas/riscv/zknh-64.d
> delete mode 100644 gas/testsuite/gas/riscv/zknh-64.s
> delete mode 100644 gas/testsuite/gas/riscv/zksed-32.d
> delete mode 100644 gas/testsuite/gas/riscv/zksed-64.d
> delete mode 100644 gas/testsuite/gas/riscv/zksed.s
> delete mode 100644 gas/testsuite/gas/riscv/zksh-32.d
> delete mode 100644 gas/testsuite/gas/riscv/zksh-64.d
> delete mode 100644 gas/testsuite/gas/riscv/zksh.s
> create mode 100644 gas/testsuite/gas/riscv/zkt.d
>
> diff --git a/gas/testsuite/gas/riscv/k-ext-64.d b/gas/testsuite/gas/riscv/k-ext-64.d
> deleted file mode 100644
> index d56e0354a37..00000000000
> --- a/gas/testsuite/gas/riscv/k-ext-64.d
> +++ /dev/null
> @@ -1,47 +0,0 @@
> -#as: -march=rv64i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt
> -#source: k-ext-64.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
> -[ ]+[0-9a-f]+:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+6025d51b[ ]+rorw[ ]+a0,a1,0x2
> -[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+08c5c53b[ ]+packw[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+68755513[ ]+brev8[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+6b855513[ ]+rev8[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+28c5a533[ ]+xperm4[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+28c5c533[ ]+xperm8[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+3ac58533[ ]+aes64ds[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+3ec58533[ ]+aes64dsm[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+30051513[ ]+aes64im[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+31459513[ ]+aes64ks1i[ ]+a0,a1,0x4
> -[ ]+[0-9a-f]+:[ ]+7ec58533[ ]+aes64ks2[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+32c58533[ ]+aes64es[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+36c58533[ ]+aes64esm[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+10251513[ ]+sha256sig0[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10351513[ ]+sha256sig1[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10051513[ ]+sha256sum0[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10151513[ ]+sha256sum1[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10651513[ ]+sha512sig0[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10751513[ ]+sha512sig1[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10451513[ ]+sha512sum0[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10551513[ ]+sha512sum1[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+b0c58533[ ]+sm4ed[ ]+a0,a1,a2,0x2
> -[ ]+[0-9a-f]+:[ ]+b4c58533[ ]+sm4ks[ ]+a0,a1,a2,0x2
> -[ ]+[0-9a-f]+:[ ]+10851513[ ]+sm3p0[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10951513[ ]+sm3p1[ ]+a0,a0
> diff --git a/gas/testsuite/gas/riscv/k-ext-64.s b/gas/testsuite/gas/riscv/k-ext-64.s
> deleted file mode 100644
> index 302b82ea005..00000000000
> --- a/gas/testsuite/gas/riscv/k-ext-64.s
> +++ /dev/null
> @@ -1,38 +0,0 @@
> -target:
> - ror a0, a1, a2
> - rol a0, a1, a2
> - rori a0, a1, 2
> - rorw a0, a1, a2
> - rolw a0, a1, a2
> - roriw a0, a1, 2
> - andn a0, a1, a2
> - orn a0, a1, a2
> - xnor a0, a1, a2
> - pack a0, a1, a2
> - packh a0, a1, a2
> - packw a0, a1, a2
> - brev8 a0, a0
> - rev8 a0, a0
> - clmul a0, a1, a2
> - clmulh a0, a1, a2
> - xperm4 a0, a1, a2
> - xperm8 a0, a1, a2
> - aes64ds a0, a1, a2
> - aes64dsm a0, a1, a2
> - aes64im a0, a0
> - aes64ks1i a0, a1, 4
> - aes64ks2 a0, a1, a2
> - aes64es a0, a1, a2
> - aes64esm a0, a1, a2
> - sha256sig0 a0, a0
> - sha256sig1 a0, a0
> - sha256sum0 a0, a0
> - sha256sum1 a0, a0
> - sha512sig0 a0, a0
> - sha512sig1 a0, a0
> - sha512sum0 a0, a0
> - sha512sum1 a0, a0
> - sm4ed a0, a1, a2, 2
> - sm4ks a0, a1, a2, 2
> - sm3p0 a0, a0
> - sm3p1 a0, a0
> diff --git a/gas/testsuite/gas/riscv/k-ext.d b/gas/testsuite/gas/riscv/k-ext.d
> deleted file mode 100644
> index b00a1c959c2..00000000000
> --- a/gas/testsuite/gas/riscv/k-ext.d
> +++ /dev/null
> @@ -1,44 +0,0 @@
> -#as: -march=rv32i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt
> -#source: k-ext.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
> -[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+68755513[ ]+brev8[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+69855513[ ]+rev8[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+08f51513[ ]+zip[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+08f55513[ ]+unzip[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+28c5a533[ ]+xperm4[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+28c5c533[ ]+xperm8[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+aac58533[ ]+aes32dsi[ ]+a0,a1,a2,0x2
> -[ ]+[0-9a-f]+:[ ]+aec58533[ ]+aes32dsmi[ ]+a0,a1,a2,0x2
> -[ ]+[0-9a-f]+:[ ]+a2c58533[ ]+aes32esi[ ]+a0,a1,a2,0x2
> -[ ]+[0-9a-f]+:[ ]+a6c58533[ ]+aes32esmi[ ]+a0,a1,a2,0x2
> -[ ]+[0-9a-f]+:[ ]+10251513[ ]+sha256sig0[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10351513[ ]+sha256sig1[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10051513[ ]+sha256sum0[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10151513[ ]+sha256sum1[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+5cc58533[ ]+sha512sig0h[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+54c58533[ ]+sha512sig0l[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+5ec58533[ ]+sha512sig1h[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+56c58533[ ]+sha512sig1l[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+50c58533[ ]+sha512sum0r[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+52c58533[ ]+sha512sum1r[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+b0c58533[ ]+sm4ed[ ]+a0,a1,a2,0x2
> -[ ]+[0-9a-f]+:[ ]+b4c58533[ ]+sm4ks[ ]+a0,a1,a2,0x2
> -[ ]+[0-9a-f]+:[ ]+10851513[ ]+sm3p0[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10951513[ ]+sm3p1[ ]+a0,a0
> diff --git a/gas/testsuite/gas/riscv/k-ext.s b/gas/testsuite/gas/riscv/k-ext.s
> deleted file mode 100644
> index 8eb27684710..00000000000
> --- a/gas/testsuite/gas/riscv/k-ext.s
> +++ /dev/null
> @@ -1,35 +0,0 @@
> -target:
> - ror a0, a1, a2
> - rol a0, a1, a2
> - rori a0, a1, 2
> - andn a0, a1, a2
> - orn a0, a1, a2
> - xnor a0, a1, a2
> - pack a0, a1, a2
> - packh a0, a1, a2
> - brev8 a0, a0
> - rev8 a0, a0
> - zip a0, a0
> - unzip a0, a0
> - clmul a0, a1, a2
> - clmulh a0, a1, a2
> - xperm4 a0, a1, a2
> - xperm8 a0, a1, a2
> - aes32dsi a0, a1, a2, 2
> - aes32dsmi a0, a1, a2, 2
> - aes32esi a0, a1, a2, 2
> - aes32esmi a0, a1, a2, 2
> - sha256sig0 a0, a0
> - sha256sig1 a0, a0
> - sha256sum0 a0, a0
> - sha256sum1 a0, a0
> - sha512sig0h a0, a1, a2
> - sha512sig0l a0, a1, a2
> - sha512sig1h a0, a1, a2
> - sha512sig1l a0, a1, a2
> - sha512sum0r a0, a1, a2
> - sha512sum1r a0, a1, a2
> - sm4ed a0, a1, a2, 2
> - sm4ks a0, a1, a2, 2
> - sm3p0 a0, a0
> - sm3p1 a0, a0
> diff --git a/gas/testsuite/gas/riscv/zbk-ext-32-noalias.d b/gas/testsuite/gas/riscv/zbk-ext-32-noalias.d
> new file mode 100644
> index 00000000000..bbbd0caefc2
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zbk-ext-32-noalias.d
> @@ -0,0 +1,26 @@
> +#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32
> +#source: zbk-ext.s
> +#objdump: -d -M no-aliases
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
> +[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+6875d513[ ]+brev8[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+6985d513[ ]+rev8[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+08f59513[ ]+zip[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+08f5d513[ ]+unzip[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+28c5a533[ ]+xperm4[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+28c5c533[ ]+xperm8[ ]+a0,a1,a2
> diff --git a/gas/testsuite/gas/riscv/zbk-ext-32-noarch.d b/gas/testsuite/gas/riscv/zbk-ext-32-noarch.d
> new file mode 100644
> index 00000000000..be2c8bd653b
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zbk-ext-32-noarch.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32 -defsym NOARCH=1
> +#source: zbk-ext.s
> +#error_output: zbk-ext-32-noarch.l
> diff --git a/gas/testsuite/gas/riscv/zbk-ext-32-noarch.l b/gas/testsuite/gas/riscv/zbk-ext-32-noarch.l
> new file mode 100644
> index 00000000000..0a9c603e7db
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zbk-ext-32-noarch.l
> @@ -0,0 +1,21 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `ror a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `rol a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `rori a0,a1,2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `rorw a0,a1,a2'
> +.*: Error: unrecognized opcode `rolw a0,a1,a2'
> +.*: Error: unrecognized opcode `roriw a0,a1,2'
> +.*: Error: unrecognized opcode `andn a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `orn a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `xnor a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `pack a0,a1,a2', extension `zbkb' required
> +.*: Error: unrecognized opcode `packh a0,a1,a2', extension `zbkb' required
> +.*: Error: unrecognized opcode `packw a0,a1,a2'
> +.*: Error: unrecognized opcode `brev8 a0,a1', extension `zbkb' required
> +.*: Error: unrecognized opcode `rev8 a0,a1', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `zip a0,a1', extension `zbkb' required
> +.*: Error: unrecognized opcode `unzip a0,a1', extension `zbkb' required
> +.*: Error: unrecognized opcode `clmul a0,a1,a2', extension `zbc' or `zbkc' required
> +.*: Error: unrecognized opcode `clmulh a0,a1,a2', extension `zbc' or `zbkc' required
> +.*: Error: unrecognized opcode `xperm4 a0,a1,a2', extension `zbkx' required
> +.*: Error: unrecognized opcode `xperm8 a0,a1,a2', extension `zbkx' required
> diff --git a/gas/testsuite/gas/riscv/zbk-ext-32.d b/gas/testsuite/gas/riscv/zbk-ext-32.d
> new file mode 100644
> index 00000000000..05c6fddaef4
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zbk-ext-32.d
> @@ -0,0 +1,26 @@
> +#as: -march=rv32i -I$srcdir/$subdir -defsym XLEN=32
> +#source: zbk-ext.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
> +[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+6875d513[ ]+brev8[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+6985d513[ ]+rev8[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+08f59513[ ]+zip[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+08f5d513[ ]+unzip[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+28c5a533[ ]+xperm4[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+28c5c533[ ]+xperm8[ ]+a0,a1,a2
> diff --git a/gas/testsuite/gas/riscv/zbk-ext-64-noalias.d b/gas/testsuite/gas/riscv/zbk-ext-64-noalias.d
> new file mode 100644
> index 00000000000..03ee8c809b0
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zbk-ext-64-noalias.d
> @@ -0,0 +1,28 @@
> +#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64
> +#source: zbk-ext.s
> +#objdump: -d -M no-aliases
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
> +[ ]+[0-9a-f]+:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+6025d51b[ ]+roriw[ ]+a0,a1,0x2
> +[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+08c5c53b[ ]+packw[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+6875d513[ ]+brev8[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+6b85d513[ ]+rev8[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+28c5a533[ ]+xperm4[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+28c5c533[ ]+xperm8[ ]+a0,a1,a2
> diff --git a/gas/testsuite/gas/riscv/zbk-ext-64-noarch.d b/gas/testsuite/gas/riscv/zbk-ext-64-noarch.d
> new file mode 100644
> index 00000000000..de1c854b808
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zbk-ext-64-noarch.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64 -defsym NOARCH=1
> +#source: zbk-ext.s
> +#error_output: zbk-ext-64-noarch.l
> diff --git a/gas/testsuite/gas/riscv/zbk-ext-64-noarch.l b/gas/testsuite/gas/riscv/zbk-ext-64-noarch.l
> new file mode 100644
> index 00000000000..e0759ac4b7a
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zbk-ext-64-noarch.l
> @@ -0,0 +1,21 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `ror a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `rol a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `rori a0,a1,2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `rorw a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `rolw a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `roriw a0,a1,2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `andn a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `orn a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `xnor a0,a1,a2', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `pack a0,a1,a2', extension `zbkb' required
> +.*: Error: unrecognized opcode `packh a0,a1,a2', extension `zbkb' required
> +.*: Error: unrecognized opcode `packw a0,a1,a2', extension `zbkb' required
> +.*: Error: unrecognized opcode `brev8 a0,a1', extension `zbkb' required
> +.*: Error: unrecognized opcode `rev8 a0,a1', extension `zbb' or `zbkb' required
> +.*: Error: unrecognized opcode `zip a0,a1'
> +.*: Error: unrecognized opcode `unzip a0,a1'
> +.*: Error: unrecognized opcode `clmul a0,a1,a2', extension `zbc' or `zbkc' required
> +.*: Error: unrecognized opcode `clmulh a0,a1,a2', extension `zbc' or `zbkc' required
> +.*: Error: unrecognized opcode `xperm4 a0,a1,a2', extension `zbkx' required
> +.*: Error: unrecognized opcode `xperm8 a0,a1,a2', extension `zbkx' required
> diff --git a/gas/testsuite/gas/riscv/zbk-ext-64.d b/gas/testsuite/gas/riscv/zbk-ext-64.d
> new file mode 100644
> index 00000000000..2c2a0098cac
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zbk-ext-64.d
> @@ -0,0 +1,28 @@
> +#as: -march=rv64i -I$srcdir/$subdir -defsym XLEN=64
> +#source: zbk-ext.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
> +[ ]+[0-9a-f]+:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+6025d51b[ ]+rorw[ ]+a0,a1,0x2
> +[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+08c5c53b[ ]+packw[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+6875d513[ ]+brev8[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+6b85d513[ ]+rev8[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+28c5a533[ ]+xperm4[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+28c5c533[ ]+xperm8[ ]+a0,a1,a2
> diff --git a/gas/testsuite/gas/riscv/zbk-ext.s b/gas/testsuite/gas/riscv/zbk-ext.s
> new file mode 100644
> index 00000000000..d839513d592
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zbk-ext.s
> @@ -0,0 +1,37 @@
> +.include "testutils.inc"
> +
> +target:
> + SET_ARCH_START +zbkb
> + ror a0, a1, a2
> + rol a0, a1, a2
> + rori a0, a1, 2
> +.if XLEN_GE_64
> + rorw a0, a1, a2
> + rolw a0, a1, a2
> + roriw a0, a1, 2
> +.endif
> + andn a0, a1, a2
> + orn a0, a1, a2
> + xnor a0, a1, a2
> + pack a0, a1, a2
> + packh a0, a1, a2
> +.if XLEN_GE_64
> + packw a0, a1, a2
> +.endif
> + brev8 a0, a1
> + rev8 a0, a1
> +.if XLEN_EQ_32
> + zip a0, a1
> + unzip a0, a1
> +.endif
> + SET_ARCH_END
> +
> + SET_ARCH_START +zbkc
> + clmul a0, a1, a2
> + clmulh a0, a1, a2
> + SET_ARCH_END
> +
> + SET_ARCH_START +zbkx
> + xperm4 a0, a1, a2
> + xperm8 a0, a1, a2
> + SET_ARCH_END
> diff --git a/gas/testsuite/gas/riscv/zbkb-32-na.d b/gas/testsuite/gas/riscv/zbkb-32-na.d
> deleted file mode 100644
> index a7b67ca4468..00000000000
> --- a/gas/testsuite/gas/riscv/zbkb-32-na.d
> +++ /dev/null
> @@ -1,23 +0,0 @@
> -#as: -march=rv32i_zbkb
> -#source: zbkb-32.s
> -#objdump: -d -Mno-aliases
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
> -[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+68755513[ ]+brev8[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+69855513[ ]+rev8[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+08f51513[ ]+zip[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+08f55513[ ]+unzip[ ]+a0,a0
> -#pass
> diff --git a/gas/testsuite/gas/riscv/zbkb-32.d b/gas/testsuite/gas/riscv/zbkb-32.d
> deleted file mode 100644
> index 1ab233c7778..00000000000
> --- a/gas/testsuite/gas/riscv/zbkb-32.d
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -#as: -march=rv32i_zbkb
> -#source: zbkb-32.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
> -[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+68755513[ ]+brev8[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+69855513[ ]+rev8[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+08f51513[ ]+zip[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+08f55513[ ]+unzip[ ]+a0,a0
> diff --git a/gas/testsuite/gas/riscv/zbkb-32.s b/gas/testsuite/gas/riscv/zbkb-32.s
> deleted file mode 100644
> index 6f917154517..00000000000
> --- a/gas/testsuite/gas/riscv/zbkb-32.s
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -target:
> - ror a0, a1, a2
> - rol a0, a1, a2
> - rori a0, a1, 2
> - andn a0, a1, a2
> - orn a0, a1, a2
> - xnor a0, a1, a2
> - pack a0, a1, a2
> - packh a0, a1, a2
> - brev8 a0, a0
> - rev8 a0, a0
> - zip a0, a0
> - unzip a0, a0
> diff --git a/gas/testsuite/gas/riscv/zbkb-64.d b/gas/testsuite/gas/riscv/zbkb-64.d
> deleted file mode 100644
> index e942bc6f1f0..00000000000
> --- a/gas/testsuite/gas/riscv/zbkb-64.d
> +++ /dev/null
> @@ -1,24 +0,0 @@
> -#as: -march=rv64i_zbkb
> -#source: zbkb-64.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+6025d513[ ]+ror[ ]+a0,a1,0x2
> -[ ]+[0-9a-f]+:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+6025d51b[ ]+rorw[ ]+a0,a1,0x2
> -[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+08c5c53b[ ]+packw[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+68755513[ ]+brev8[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+6b855513[ ]+rev8[ ]+a0,a0
> diff --git a/gas/testsuite/gas/riscv/zbkb-64.s b/gas/testsuite/gas/riscv/zbkb-64.s
> deleted file mode 100644
> index b5cf79f890e..00000000000
> --- a/gas/testsuite/gas/riscv/zbkb-64.s
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -target:
> - ror a0, a1, a2
> - rol a0, a1, a2
> - rori a0, a1, 2
> - rorw a0, a1, a2
> - rolw a0, a1, a2
> - roriw a0, a1, 2
> - andn a0, a1, a2
> - orn a0, a1, a2
> - xnor a0, a1, a2
> - pack a0, a1, a2
> - packh a0, a1, a2
> - packw a0, a1, a2
> - brev8 a0, a0
> - rev8 a0, a0
> diff --git a/gas/testsuite/gas/riscv/zbkc-32.d b/gas/testsuite/gas/riscv/zbkc-32.d
> deleted file mode 100644
> index 69d89875652..00000000000
> --- a/gas/testsuite/gas/riscv/zbkc-32.d
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -#as: -march=rv32i_zbkc
> -#source: zbkc.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
> diff --git a/gas/testsuite/gas/riscv/zbkc-64.d b/gas/testsuite/gas/riscv/zbkc-64.d
> deleted file mode 100644
> index 26cdf7014c9..00000000000
> --- a/gas/testsuite/gas/riscv/zbkc-64.d
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -#as: -march=rv64i_zbkc
> -#source: zbkc.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
> diff --git a/gas/testsuite/gas/riscv/zbkc.s b/gas/testsuite/gas/riscv/zbkc.s
> deleted file mode 100644
> index 2a987746e7b..00000000000
> --- a/gas/testsuite/gas/riscv/zbkc.s
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -target:
> - clmul a0, a1, a2
> - clmulh a0, a1, a2
> diff --git a/gas/testsuite/gas/riscv/zbkx-32.d b/gas/testsuite/gas/riscv/zbkx-32.d
> deleted file mode 100644
> index b1f7fc017bf..00000000000
> --- a/gas/testsuite/gas/riscv/zbkx-32.d
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -#as: -march=rv32i_zbkx
> -#source: zbkx.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+28c5a533[ ]+xperm4[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+28c5c533[ ]+xperm8[ ]+a0,a1,a2
> diff --git a/gas/testsuite/gas/riscv/zbkx-64.d b/gas/testsuite/gas/riscv/zbkx-64.d
> deleted file mode 100644
> index 3ab8bf69c75..00000000000
> --- a/gas/testsuite/gas/riscv/zbkx-64.d
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -#as: -march=rv64i_zbkx
> -#source: zbkx.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+28c5a533[ ]+xperm4[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+28c5c533[ ]+xperm8[ ]+a0,a1,a2
> diff --git a/gas/testsuite/gas/riscv/zbkx.s b/gas/testsuite/gas/riscv/zbkx.s
> deleted file mode 100644
> index 8c3077105fe..00000000000
> --- a/gas/testsuite/gas/riscv/zbkx.s
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -target:
> - xperm4 a0, a1, a2
> - xperm8 a0, a1, a2
> diff --git a/gas/testsuite/gas/riscv/zk-ext-32-noarch.d b/gas/testsuite/gas/riscv/zk-ext-32-noarch.d
> new file mode 100644
> index 00000000000..7a489dedbac
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zk-ext-32-noarch.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i -mcsr-check -I$srcdir/$subdir -defsym NOARCH=1
> +#source: zk-ext-32.s
> +#error_output: zk-ext-32-noarch.l
> diff --git a/gas/testsuite/gas/riscv/zk-ext-32-noarch.l b/gas/testsuite/gas/riscv/zk-ext-32-noarch.l
> new file mode 100644
> index 00000000000..372dc523276
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zk-ext-32-noarch.l
> @@ -0,0 +1,20 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `aes32dsi a0,a1,a2,2', extension `zknd' required
> +.*: Error: unrecognized opcode `aes32dsmi a0,a1,a2,2', extension `zknd' required
> +.*: Error: unrecognized opcode `aes32esi a0,a1,a2,2', extension `zkne' required
> +.*: Error: unrecognized opcode `aes32esmi a0,a1,a2,2', extension `zkne' required
> +.*: Error: unrecognized opcode `sha256sig0 a0,a1', extension `zknh' required
> +.*: Error: unrecognized opcode `sha256sig1 a0,a1', extension `zknh' required
> +.*: Error: unrecognized opcode `sha256sum0 a0,a1', extension `zknh' required
> +.*: Error: unrecognized opcode `sha256sum1 a0,a1', extension `zknh' required
> +.*: Error: unrecognized opcode `sha512sig0h a0,a1,a2', extension `zknh' required
> +.*: Error: unrecognized opcode `sha512sig0l a0,a1,a2', extension `zknh' required
> +.*: Error: unrecognized opcode `sha512sig1h a0,a1,a2', extension `zknh' required
> +.*: Error: unrecognized opcode `sha512sig1l a0,a1,a2', extension `zknh' required
> +.*: Error: unrecognized opcode `sha512sum0r a0,a1,a2', extension `zknh' required
> +.*: Error: unrecognized opcode `sha512sum1r a0,a1,a2', extension `zknh' required
> +.*: Error: unrecognized opcode `sm4ed a0,a1,a2,2', extension `zksed' required
> +.*: Error: unrecognized opcode `sm4ks a0,a1,a2,2', extension `zksed' required
> +.*: Error: unrecognized opcode `sm3p0 a0,a1', extension `zksh' required
> +.*: Error: unrecognized opcode `sm3p1 a0,a1', extension `zksh' required
> +.*: Warning: invalid CSR `seed', needs `zkr' extension
> diff --git a/gas/testsuite/gas/riscv/zk-ext-32.d b/gas/testsuite/gas/riscv/zk-ext-32.d
> new file mode 100644
> index 00000000000..03cd158ab43
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zk-ext-32.d
> @@ -0,0 +1,28 @@
> +#as: -march=rv32i -mcsr-check -I$srcdir/$subdir
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+aac58533[ ]+aes32dsi[ ]+a0,a1,a2,0x2
> +[ ]+[0-9a-f]+:[ ]+aec58533[ ]+aes32dsmi[ ]+a0,a1,a2,0x2
> +[ ]+[0-9a-f]+:[ ]+a2c58533[ ]+aes32esi[ ]+a0,a1,a2,0x2
> +[ ]+[0-9a-f]+:[ ]+a6c58533[ ]+aes32esmi[ ]+a0,a1,a2,0x2
> +[ ]+[0-9a-f]+:[ ]+10259513[ ]+sha256sig0[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+10359513[ ]+sha256sig1[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+10059513[ ]+sha256sum0[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+10159513[ ]+sha256sum1[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+5cc58533[ ]+sha512sig0h[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+54c58533[ ]+sha512sig0l[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+5ec58533[ ]+sha512sig1h[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+56c58533[ ]+sha512sig1l[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+50c58533[ ]+sha512sum0r[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+52c58533[ ]+sha512sum1r[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+b0c58533[ ]+sm4ed[ ]+a0,a1,a2,0x2
> +[ ]+[0-9a-f]+:[ ]+b4c58533[ ]+sm4ks[ ]+a0,a1,a2,0x2
> +[ ]+[0-9a-f]+:[ ]+10859513[ ]+sm3p0[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+10959513[ ]+sm3p1[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed
> diff --git a/gas/testsuite/gas/riscv/zk-ext-32.s b/gas/testsuite/gas/riscv/zk-ext-32.s
> new file mode 100644
> index 00000000000..892644c054a
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zk-ext-32.s
> @@ -0,0 +1,41 @@
> +.include "testutils.inc"
> +
> +target:
> + SET_ARCH_START +zknd
> + aes32dsi a0, a1, a2, 2
> + aes32dsmi a0, a1, a2, 2
> + SET_ARCH_END
> +
> + SET_ARCH_START +zkne
> + aes32esi a0, a1, a2, 2
> + aes32esmi a0, a1, a2, 2
> + SET_ARCH_END
> +
> + SET_ARCH_START +zknh
> + sha256sig0 a0, a1
> + sha256sig1 a0, a1
> + sha256sum0 a0, a1
> + sha256sum1 a0, a1
> + sha512sig0h a0, a1, a2
> + sha512sig0l a0, a1, a2
> + sha512sig1h a0, a1, a2
> + sha512sig1l a0, a1, a2
> + sha512sum0r a0, a1, a2
> + sha512sum1r a0, a1, a2
> + SET_ARCH_END
> +
> + SET_ARCH_START +zksed
> + sm4ed a0, a1, a2, 2
> + sm4ks a0, a1, a2, 2
> + SET_ARCH_END
> +
> + SET_ARCH_START +zksh
> + sm3p0 a0, a1
> + sm3p1 a0, a1
> + SET_ARCH_END
> +
> + SET_ARCH_START_FORCE +zicsr
> + SET_ARCH_START +zkr
> + csrr a0, seed
> + SET_ARCH_END
> + SET_ARCH_END
Likewise, and I suggest keep the csr testcase together, and don't test
them with the insturctions.
Nelson
> diff --git a/gas/testsuite/gas/riscv/zk-ext-64-noarch.d b/gas/testsuite/gas/riscv/zk-ext-64-noarch.d
> new file mode 100644
> index 00000000000..e83e4b17a81
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zk-ext-64-noarch.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv64i -mcsr-check -I$srcdir/$subdir -defsym NOARCH=1
> +#source: zk-ext-64.s
> +#error_output: zk-ext-64-noarch.l
> diff --git a/gas/testsuite/gas/riscv/zk-ext-64-noarch.l b/gas/testsuite/gas/riscv/zk-ext-64-noarch.l
> new file mode 100644
> index 00000000000..38362f54465
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zk-ext-64-noarch.l
> @@ -0,0 +1,23 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `aes64ds a0,a1,a2', extension `zknd' required
> +.*: Error: unrecognized opcode `aes64dsm a0,a1,a2', extension `zknd' required
> +.*: Error: unrecognized opcode `aes64im a0,a1', extension `zknd' required
> +.*: Error: unrecognized opcode `aes64ks1i a0,a1,4', extension `zknd' or `zkne' required
> +.*: Error: unrecognized opcode `aes64ks2 a0,a1,a2', extension `zknd' or `zkne' required
> +.*: Error: unrecognized opcode `aes64es a0,a1,a2', extension `zkne' required
> +.*: Error: unrecognized opcode `aes64esm a0,a1,a2', extension `zkne' required
> +.*: Error: unrecognized opcode `aes64ks1i a0,a1,4', extension `zknd' or `zkne' required
> +.*: Error: unrecognized opcode `aes64ks2 a0,a1,a2', extension `zknd' or `zkne' required
> +.*: Error: unrecognized opcode `sha256sig0 a0,a1', extension `zknh' required
> +.*: Error: unrecognized opcode `sha256sig1 a0,a1', extension `zknh' required
> +.*: Error: unrecognized opcode `sha256sum0 a0,a1', extension `zknh' required
> +.*: Error: unrecognized opcode `sha256sum1 a0,a1', extension `zknh' required
> +.*: Error: unrecognized opcode `sha512sig0 a0,a1', extension `zknh' required
> +.*: Error: unrecognized opcode `sha512sig1 a0,a1', extension `zknh' required
> +.*: Error: unrecognized opcode `sha512sum0 a0,a1', extension `zknh' required
> +.*: Error: unrecognized opcode `sha512sum1 a0,a1', extension `zknh' required
> +.*: Error: unrecognized opcode `sm4ed a0,a1,a2,2', extension `zksed' required
> +.*: Error: unrecognized opcode `sm4ks a0,a1,a2,2', extension `zksed' required
> +.*: Error: unrecognized opcode `sm3p0 a0,a1', extension `zksh' required
> +.*: Error: unrecognized opcode `sm3p1 a0,a1', extension `zksh' required
> +.*: Warning: invalid CSR `seed', needs `zkr' extension
> diff --git a/gas/testsuite/gas/riscv/zk-ext-64.d b/gas/testsuite/gas/riscv/zk-ext-64.d
> new file mode 100644
> index 00000000000..ee134f6cdf0
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zk-ext-64.d
> @@ -0,0 +1,31 @@
> +#as: -march=rv64i -mcsr-check -I$srcdir/$subdir
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+3ac58533[ ]+aes64ds[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+3ec58533[ ]+aes64dsm[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+30059513[ ]+aes64im[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+31459513[ ]+aes64ks1i[ ]+a0,a1,0x4
> +[ ]+[0-9a-f]+:[ ]+7ec58533[ ]+aes64ks2[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+32c58533[ ]+aes64es[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+36c58533[ ]+aes64esm[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+31459513[ ]+aes64ks1i[ ]+a0,a1,0x4
> +[ ]+[0-9a-f]+:[ ]+7ec58533[ ]+aes64ks2[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+10259513[ ]+sha256sig0[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+10359513[ ]+sha256sig1[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+10059513[ ]+sha256sum0[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+10159513[ ]+sha256sum1[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+10659513[ ]+sha512sig0[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+10759513[ ]+sha512sig1[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+10459513[ ]+sha512sum0[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+10559513[ ]+sha512sum1[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+b0c58533[ ]+sm4ed[ ]+a0,a1,a2,0x2
> +[ ]+[0-9a-f]+:[ ]+b4c58533[ ]+sm4ks[ ]+a0,a1,a2,0x2
> +[ ]+[0-9a-f]+:[ ]+10859513[ ]+sm3p0[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+10959513[ ]+sm3p1[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed
> diff --git a/gas/testsuite/gas/riscv/zk-ext-64.s b/gas/testsuite/gas/riscv/zk-ext-64.s
> new file mode 100644
> index 00000000000..9d8104908a9
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zk-ext-64.s
> @@ -0,0 +1,44 @@
> +.include "testutils.inc"
> +
> +target:
> + SET_ARCH_START +zknd
> + aes64ds a0, a1, a2
> + aes64dsm a0, a1, a2
> + aes64im a0, a1
> + aes64ks1i a0, a1, 4
> + aes64ks2 a0, a1, a2
> + SET_ARCH_END
> +
> + SET_ARCH_START +zkne
> + aes64es a0, a1, a2
> + aes64esm a0, a1, a2
> + aes64ks1i a0, a1, 4
> + aes64ks2 a0, a1, a2
> + SET_ARCH_END
> +
> + SET_ARCH_START +zknh
> + sha256sig0 a0, a1
> + sha256sig1 a0, a1
> + sha256sum0 a0, a1
> + sha256sum1 a0, a1
> + sha512sig0 a0, a1
> + sha512sig1 a0, a1
> + sha512sum0 a0, a1
> + sha512sum1 a0, a1
> + SET_ARCH_END
> +
> + SET_ARCH_START +zksed
> + sm4ed a0, a1, a2, 2
> + sm4ks a0, a1, a2, 2
> + SET_ARCH_END
> +
> + SET_ARCH_START +zksh
> + sm3p0 a0, a1
> + sm3p1 a0, a1
> + SET_ARCH_END
> +
> + SET_ARCH_START_FORCE +zicsr
> + SET_ARCH_START +zkr
> + csrr a0, seed
> + SET_ARCH_END
> + SET_ARCH_END
> diff --git a/gas/testsuite/gas/riscv/zknd-32.d b/gas/testsuite/gas/riscv/zknd-32.d
> deleted file mode 100644
> index a6995bf6f1c..00000000000
> --- a/gas/testsuite/gas/riscv/zknd-32.d
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -#as: -march=rv32i_zknd
> -#source: zknd-32.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+aac58533[ ]+aes32dsi[ ]+a0,a1,a2,0x2
> -[ ]+[0-9a-f]+:[ ]+aec58533[ ]+aes32dsmi[ ]+a0,a1,a2,0x2
> diff --git a/gas/testsuite/gas/riscv/zknd-32.s b/gas/testsuite/gas/riscv/zknd-32.s
> deleted file mode 100644
> index 0d09badd1c6..00000000000
> --- a/gas/testsuite/gas/riscv/zknd-32.s
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -target:
> - aes32dsi a0, a1, a2, 2
> - aes32dsmi a0, a1, a2, 2
> diff --git a/gas/testsuite/gas/riscv/zknd-64.d b/gas/testsuite/gas/riscv/zknd-64.d
> deleted file mode 100644
> index ba4c91ceb34..00000000000
> --- a/gas/testsuite/gas/riscv/zknd-64.d
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -#as: -march=rv64i_zknd
> -#source: zknd-64.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+3ac58533[ ]+aes64ds[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+3ec58533[ ]+aes64dsm[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+30051513[ ]+aes64im[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+31459513[ ]+aes64ks1i[ ]+a0,a1,0x4
> -[ ]+[0-9a-f]+:[ ]+7ec58533[ ]+aes64ks2[ ]+a0,a1,a2
> diff --git a/gas/testsuite/gas/riscv/zknd-64.s b/gas/testsuite/gas/riscv/zknd-64.s
> deleted file mode 100644
> index 4846e93c16f..00000000000
> --- a/gas/testsuite/gas/riscv/zknd-64.s
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -target:
> - aes64ds a0, a1, a2
> - aes64dsm a0, a1, a2
> - aes64im a0, a0
> - aes64ks1i a0, a1, 4
> - aes64ks2 a0, a1, a2
> diff --git a/gas/testsuite/gas/riscv/zkne-32.d b/gas/testsuite/gas/riscv/zkne-32.d
> deleted file mode 100644
> index 4950e748800..00000000000
> --- a/gas/testsuite/gas/riscv/zkne-32.d
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -#as: -march=rv32i_zkne
> -#source: zkne-32.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+a2c58533[ ]+aes32esi[ ]+a0,a1,a2,0x2
> -[ ]+[0-9a-f]+:[ ]+a6c58533[ ]+aes32esmi[ ]+a0,a1,a2,0x2
> diff --git a/gas/testsuite/gas/riscv/zkne-32.s b/gas/testsuite/gas/riscv/zkne-32.s
> deleted file mode 100644
> index f864fc1778b..00000000000
> --- a/gas/testsuite/gas/riscv/zkne-32.s
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -target:
> - aes32esi a0, a1, a2, 2
> - aes32esmi a0, a1, a2, 2
> diff --git a/gas/testsuite/gas/riscv/zkne-64.d b/gas/testsuite/gas/riscv/zkne-64.d
> deleted file mode 100644
> index 31bc084a807..00000000000
> --- a/gas/testsuite/gas/riscv/zkne-64.d
> +++ /dev/null
> @@ -1,14 +0,0 @@
> -#as: -march=rv64i_zkne
> -#source: zkne-64.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+32c58533[ ]+aes64es[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+36c58533[ ]+aes64esm[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+31459513[ ]+aes64ks1i[ ]+a0,a1,0x4
> -[ ]+[0-9a-f]+:[ ]+7ec58533[ ]+aes64ks2[ ]+a0,a1,a2
> diff --git a/gas/testsuite/gas/riscv/zkne-64.s b/gas/testsuite/gas/riscv/zkne-64.s
> deleted file mode 100644
> index 9b5612001af..00000000000
> --- a/gas/testsuite/gas/riscv/zkne-64.s
> +++ /dev/null
> @@ -1,5 +0,0 @@
> -target:
> - aes64es a0, a1, a2
> - aes64esm a0, a1, a2
> - aes64ks1i a0, a1, 4
> - aes64ks2 a0, a1, a2
> diff --git a/gas/testsuite/gas/riscv/zknh-32.d b/gas/testsuite/gas/riscv/zknh-32.d
> deleted file mode 100644
> index c8ef70d67f4..00000000000
> --- a/gas/testsuite/gas/riscv/zknh-32.d
> +++ /dev/null
> @@ -1,20 +0,0 @@
> -#as: -march=rv32i_zknh
> -#source: zknh-32.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+10251513[ ]+sha256sig0[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10351513[ ]+sha256sig1[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10051513[ ]+sha256sum0[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10151513[ ]+sha256sum1[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+5cc58533[ ]+sha512sig0h[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+54c58533[ ]+sha512sig0l[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+5ec58533[ ]+sha512sig1h[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+56c58533[ ]+sha512sig1l[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+50c58533[ ]+sha512sum0r[ ]+a0,a1,a2
> -[ ]+[0-9a-f]+:[ ]+52c58533[ ]+sha512sum1r[ ]+a0,a1,a2
> diff --git a/gas/testsuite/gas/riscv/zknh-32.s b/gas/testsuite/gas/riscv/zknh-32.s
> deleted file mode 100644
> index dc2cd3c6657..00000000000
> --- a/gas/testsuite/gas/riscv/zknh-32.s
> +++ /dev/null
> @@ -1,11 +0,0 @@
> -target:
> - sha256sig0 a0, a0
> - sha256sig1 a0, a0
> - sha256sum0 a0, a0
> - sha256sum1 a0, a0
> - sha512sig0h a0, a1, a2
> - sha512sig0l a0, a1, a2
> - sha512sig1h a0, a1, a2
> - sha512sig1l a0, a1, a2
> - sha512sum0r a0, a1, a2
> - sha512sum1r a0, a1, a2
> diff --git a/gas/testsuite/gas/riscv/zknh-64.d b/gas/testsuite/gas/riscv/zknh-64.d
> deleted file mode 100644
> index b72e31e3547..00000000000
> --- a/gas/testsuite/gas/riscv/zknh-64.d
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -#as: -march=rv64i_zknh
> -#source: zknh-64.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+10251513[ ]+sha256sig0[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10351513[ ]+sha256sig1[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10051513[ ]+sha256sum0[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10151513[ ]+sha256sum1[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10651513[ ]+sha512sig0[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10751513[ ]+sha512sig1[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10451513[ ]+sha512sum0[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10551513[ ]+sha512sum1[ ]+a0,a0
> diff --git a/gas/testsuite/gas/riscv/zknh-64.s b/gas/testsuite/gas/riscv/zknh-64.s
> deleted file mode 100644
> index 897dc0ba32e..00000000000
> --- a/gas/testsuite/gas/riscv/zknh-64.s
> +++ /dev/null
> @@ -1,9 +0,0 @@
> -target:
> - sha256sig0 a0, a0
> - sha256sig1 a0, a0
> - sha256sum0 a0, a0
> - sha256sum1 a0, a0
> - sha512sig0 a0, a0
> - sha512sig1 a0, a0
> - sha512sum0 a0, a0
> - sha512sum1 a0, a0
> diff --git a/gas/testsuite/gas/riscv/zksed-32.d b/gas/testsuite/gas/riscv/zksed-32.d
> deleted file mode 100644
> index 3c84c0f31ce..00000000000
> --- a/gas/testsuite/gas/riscv/zksed-32.d
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -#as: -march=rv32i_zksed
> -#source: zksed.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+b0c58533[ ]+sm4ed[ ]+a0,a1,a2,0x2
> -[ ]+[0-9a-f]+:[ ]+b4c58533[ ]+sm4ks[ ]+a0,a1,a2,0x2
> diff --git a/gas/testsuite/gas/riscv/zksed-64.d b/gas/testsuite/gas/riscv/zksed-64.d
> deleted file mode 100644
> index 29d828a9009..00000000000
> --- a/gas/testsuite/gas/riscv/zksed-64.d
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -#as: -march=rv64i_zksed
> -#source: zksed.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+b0c58533[ ]+sm4ed[ ]+a0,a1,a2,0x2
> -[ ]+[0-9a-f]+:[ ]+b4c58533[ ]+sm4ks[ ]+a0,a1,a2,0x2
> diff --git a/gas/testsuite/gas/riscv/zksed.s b/gas/testsuite/gas/riscv/zksed.s
> deleted file mode 100644
> index ee95c7a8584..00000000000
> --- a/gas/testsuite/gas/riscv/zksed.s
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -target:
> - sm4ed a0, a1, a2, 2
> - sm4ks a0, a1, a2, 2
> diff --git a/gas/testsuite/gas/riscv/zksh-32.d b/gas/testsuite/gas/riscv/zksh-32.d
> deleted file mode 100644
> index 14ac63d95e6..00000000000
> --- a/gas/testsuite/gas/riscv/zksh-32.d
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -#as: -march=rv32i_zksh
> -#source: zksh.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+10851513[ ]+sm3p0[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10951513[ ]+sm3p1[ ]+a0,a0
> diff --git a/gas/testsuite/gas/riscv/zksh-64.d b/gas/testsuite/gas/riscv/zksh-64.d
> deleted file mode 100644
> index 2d13e38dd37..00000000000
> --- a/gas/testsuite/gas/riscv/zksh-64.d
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -#as: -march=rv64i_zksh
> -#source: zksh.s
> -#objdump: -d
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+[0-9a-f]+:[ ]+10851513[ ]+sm3p0[ ]+a0,a0
> -[ ]+[0-9a-f]+:[ ]+10951513[ ]+sm3p1[ ]+a0,a0
> diff --git a/gas/testsuite/gas/riscv/zksh.s b/gas/testsuite/gas/riscv/zksh.s
> deleted file mode 100644
> index b321c26f2b2..00000000000
> --- a/gas/testsuite/gas/riscv/zksh.s
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -target:
> - sm3p0 a0, a0
> - sm3p1 a0, a0
> diff --git a/gas/testsuite/gas/riscv/zkt.d b/gas/testsuite/gas/riscv/zkt.d
> new file mode 100644
> index 00000000000..feca41b64fa
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zkt.d
> @@ -0,0 +1,5 @@
> +#as: -march=rv32i_zkt
> +#source: empty.s
> +#objdump: -d
> +
> +#...
> --
> 2.37.2
>
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2022-11-29 9:01 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-05 12:29 [PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
2022-11-05 12:29 ` [PATCH 01/12] RISC-V: Remove unnecessary empty matching file Tsukasa OI
2022-11-29 7:38 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 02/12] RISC-V: Tidy disassembler corner case tests Tsukasa OI
2022-11-29 7:48 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 03/12] RISC-V: Tidying related to 'Zfinx' disassembler test Tsukasa OI
2022-11-29 7:50 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 04/12] RISC-V: GAS: Add basic shared test utilities Tsukasa OI
2022-11-29 7:53 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 05/12] RISC-V: Redefine "nop" test Tsukasa OI
2022-11-29 7:58 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 06/12] RISC-V: Reorganize/enhance {sign,zero}-extension instructions Tsukasa OI
2022-11-29 8:10 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 07/12] RISC-V: Combine complex extension error handling tests Tsukasa OI
2022-11-29 8:16 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 08/12] RISC-V: Refine/enhance 'M'/'Zmmul' extension tests Tsukasa OI
2022-11-29 8:23 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 09/12] RISC-V: Combine/enhance 'Zicbo[mz]' " Tsukasa OI
2022-11-29 8:38 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 10/12] RISC-V: Enhance 'Zicbop' testcases Tsukasa OI
2022-11-29 8:51 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 11/12] RISC-V: Reorganize/enhance 'Zb*' extension tests Tsukasa OI
2022-11-29 8:57 ` Nelson Chu
2022-11-05 12:29 ` [PATCH 12/12] RISC-V: Combine/enhance 'Zk*'/'Zbk*' " Tsukasa OI
2022-11-29 9:00 ` Nelson Chu
2022-11-20 2:28 ` [PING^1][PATCH 00/12] RISC-V: Test refinements (Batch 1) Tsukasa OI
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