[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.*

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:5f950bc5b2949a2e6c07998b0517aa08a5945dc7

commit 5f950bc5b2949a2e6c07998b0517aa08a5945dc7
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 19:08:35 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 58 +++-----------------------------------------------
 1 file changed, 3 insertions(+), 55 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 61634f875b1..c157e73db69 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,60 +1,8 @@
-==================== Branch work119, patch #52 ====================
+==================== Branch work119, patch #52 was reverted ====================
 
-Improve vec_extract of V4SF with variable element number.
+==================== Branch work119, patch #51 was reverted ====================
 
-This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
-where the element number is variable combined with a conversion to DFmode.
-
-I also modified the insn for vec_extract of V4SFmode where the element number is
-variable to split before register allocation.
-
-2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
-
-	* config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before
-	register allocation.
-	(vsx_extract_v4sf_var_load_to_df): New insn.
-
-gcc/testsuite/
-
-	* gcc.target/powerpc/vec-extract-mem-float-2.c: New test.
-
-==================== Branch work119, patch #51 ====================
-
-Combine vec_extract of V4SF with DF convert.
-
-This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
-where the element number is constant combined with a conversion to DFmode.
-
-In addition, I changed the vec_extract of V4SFmode where the element number is
-constant without conversion to do the split before register allocation.  I also
-simplified the alternatives.
-
-2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
-
-	* config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow split before
-	register allocation.
-	(vsx_extract_v4sf_to_df_load): New insn.
-
-gcc/testsuite/
-
-	* gcc.target/powerpc/vec-extract-mem-float-1.c: New test.
-
-==================== Branch work119, patch #50 ====================
-
-Allow vec_extract support functions to be called before reload.
-
-2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
-
-	* config/rs6000/rs6000.cc (get_vector_offset): Allow being called before
-	register allocation.
-	(adjust_vec_address_pcrel): Likewise.
-	(rs6000_adjust_vec_address): Likewise.
+==================== Branch work119, patch #50 was reverted ====================
 
 ==================== Branch work119, patch #49 was reverted ====================

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:cdebb718826139a742b3d1161f72ce14fd2c7977

commit cdebb718826139a742b3d1161f72ce14fd2c7977
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Apr 24 19:01:27 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 68 ++++++++------------------------------------------
 1 file changed, 11 insertions(+), 57 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 0d54f525348..a31fb05b750 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,70 +1,24 @@
-==================== Branch work119, patch #62 ====================
+==================== Branch work119, patch #72 was reverted ====================
 
-Add vec_extract test cases.
+==================== Branch work119, patch #71 was reverted ====================
 
-This patch adds test cases to verify that the vec_extract optimizations in
-include sign/zero extension with the load are generating code.
+==================== Branch work119, patch #70 was reverted ====================
 
-2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/testsuite/
-
-	* gcc.target/powerpc/vec-extract-mem-char-1.c: New test.
-	* gcc.target/powerpc/vec-extract-mem-int-1.c: New test.
-	* gcc.target/powerpc/vec-extract-mem-short-1.c: New test.
+==================== Branch work119, patch #69 was reverted ====================
 
+==================== Branch work119, patch #68 was reverted ====================
 
-==================== Branch work119, patch #62 ====================
+==================== Branch work119, patch #67 was reverted ====================
 
-Fold V16QI vsx_extract from memory with constant element with zero extension.
+==================== Branch work119, patch #66 was reverted ====================
 
-This patch folds V16QI vsx_extract from memory where the element number is
-constant with zero extension to SImode/DImode.
-
-2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
+==================== Branch work119, patch #65 was reverted ====================
 
-	* config/rs6000/vsx.md (vsx_extract_v16qi_load_to_u<mode>): New insn.
-
-==================== Branch work119, patch #62 ====================
-
-Fold V8HI vsx_extract from memory with constant element with sign/zero extension.
-
-This patch folds V8HI vsx_extract from memory where the element number is
-constant with sign or zero extension to SImode/DImode.
-
-2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
+==================== Branch work119, patch #64 was reverted ====================
 
-	* config/rs6000/vsx.md (vsx_extract_v8hi_load_to_<su><mode>): New insn.
-
-==================== Branch work119, patch #62 ====================
-
-Fold V4SI sign or zero extension into vsx_extract from memory with constant element.
-
-This patch folds V4SI vsx_extract from memory where the element number is
-constant with sign or zero extension to DImode.
-
-2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
-
-	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>di): New insn.
-
-==================== Branch work119, patch #62 ====================
-
-Allow integer vec_extract to load vector registers.
-
-2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
+==================== Branch work119, patch #63 was reverted ====================
 
-	* config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute
-	(vsx_extract_<mode>_load): Allow vec_extract of integer types with a
-	constant element number to load into vector registers.  Don't require a
-	base register temporary if the element number is 0.
+==================== Branch work119, patch #62 was reverted ====================
 
 ==================== Branch work119, patch #61 ====================

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:8ca5b658578bbfa9012f57884608b3bceb4124cd

commit 8ca5b658578bbfa9012f57884608b3bceb4124cd
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 20:58:46 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 30b1619c5f2..0d54f525348 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,71 @@
+==================== Branch work119, patch #62 ====================
+
+Add vec_extract test cases.
+
+This patch adds test cases to verify that the vec_extract optimizations in
+include sign/zero extension with the load are generating code.
+
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-char-1.c: New test.
+	* gcc.target/powerpc/vec-extract-mem-int-1.c: New test.
+	* gcc.target/powerpc/vec-extract-mem-short-1.c: New test.
+
+
+==================== Branch work119, patch #62 ====================
+
+Fold V16QI vsx_extract from memory with constant element with zero extension.
+
+This patch folds V16QI vsx_extract from memory where the element number is
+constant with zero extension to SImode/DImode.
+
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v16qi_load_to_u<mode>): New insn.
+
+==================== Branch work119, patch #62 ====================
+
+Fold V8HI vsx_extract from memory with constant element with sign/zero extension.
+
+This patch folds V8HI vsx_extract from memory where the element number is
+constant with sign or zero extension to SImode/DImode.
+
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v8hi_load_to_<su><mode>): New insn.
+
+==================== Branch work119, patch #62 ====================
+
+Fold V4SI sign or zero extension into vsx_extract from memory with constant element.
+
+This patch folds V4SI vsx_extract from memory where the element number is
+constant with sign or zero extension to DImode.
+
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>di): New insn.
+
+==================== Branch work119, patch #62 ====================
+
+Allow integer vec_extract to load vector registers.
+
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute
+	(vsx_extract_<mode>_load): Allow vec_extract of integer types with a
+	constant element number to load into vector registers.  Don't require a
+	base register temporary if the element number is 0.
+
 ==================== Branch work119, patch #61 ====================
 
 Combine vec_extract of V4SF with DF convert with variable element.

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:9c8fe27948dc1b000cb4d8d75e7b2bd8e876d297

commit 9c8fe27948dc1b000cb4d8d75e7b2bd8e876d297
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 19:33:08 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index c157e73db69..30b1619c5f2 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,29 @@
+==================== Branch work119, patch #61 ====================
+
+Combine vec_extract of V4SF with DF convert with variable element.
+
+This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
+where the element number is variable combined with a conversion to DFmode.
+
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4sf_var_load_to_df): New insn.
+
+==================== Branch work119, patch #60 ====================
+
+Combine vec_extract of V4SF with DF convert with constant element number.
+
+This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
+where the element number is constant combined with a conversion to DFmode.
+
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn.
+
 ==================== Branch work119, patch #52 was reverted ====================
 
 ==================== Branch work119, patch #51 was reverted ====================

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:3e3308ee2e7dcd770baeb1b6e336657ce73c88de

commit 3e3308ee2e7dcd770baeb1b6e336657ce73c88de
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 19:06:28 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner   | 58 +++---------------------------------------------
 gcc/config/rs6000/vsx.md | 38 ++++++++++++++++++++++++-------
 2 files changed, 33 insertions(+), 63 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 61634f875b1..c157e73db69 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,60 +1,8 @@
-==================== Branch work119, patch #52 ====================
+==================== Branch work119, patch #52 was reverted ====================
 
-Improve vec_extract of V4SF with variable element number.
+==================== Branch work119, patch #51 was reverted ====================
 
-This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
-where the element number is variable combined with a conversion to DFmode.
-
-I also modified the insn for vec_extract of V4SFmode where the element number is
-variable to split before register allocation.
-
-2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
-
-	* config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before
-	register allocation.
-	(vsx_extract_v4sf_var_load_to_df): New insn.
-
-gcc/testsuite/
-
-	* gcc.target/powerpc/vec-extract-mem-float-2.c: New test.
-
-==================== Branch work119, patch #51 ====================
-
-Combine vec_extract of V4SF with DF convert.
-
-This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
-where the element number is constant combined with a conversion to DFmode.
-
-In addition, I changed the vec_extract of V4SFmode where the element number is
-constant without conversion to do the split before register allocation.  I also
-simplified the alternatives.
-
-2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
-
-	* config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow split before
-	register allocation.
-	(vsx_extract_v4sf_to_df_load): New insn.
-
-gcc/testsuite/
-
-	* gcc.target/powerpc/vec-extract-mem-float-1.c: New test.
-
-==================== Branch work119, patch #50 ====================
-
-Allow vec_extract support functions to be called before reload.
-
-2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
-
-	* config/rs6000/rs6000.cc (get_vector_offset): Allow being called before
-	register allocation.
-	(adjust_vec_address_pcrel): Likewise.
-	(rs6000_adjust_vec_address): Likewise.
+==================== Branch work119, patch #50 was reverted ====================
 
 ==================== Branch work119, patch #49 was reverted ====================
 
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 417aff5e24b..17e56ab1ce4 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,23 +3549,45 @@
   [(set_attr "length" "8")
    (set_attr "type" "fp")])
 
+;; V4SF extract from memory convert to DFmode with constant element number.  If
+;; the element number is 0, we don't need a temporary register.
 (define_insn_and_split "*vsx_extract_v4sf_load"
-  [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
+  [(set (match_operand:SF 0 "register_operand" "=wa,wa,?r,?r")
 	(vec_select:SF
-	 (match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
-	 (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")])))
-   (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
+	 (match_operand:V4SF 1 "memory_operand" "m,Q,m,Q")
+	 (parallel
+	  [(match_operand:QI 2 "const_0_to_3_operand" "O,n,O,n")])))
+   (clobber (match_scratch:P 3 "=X,&b,X,&b"))]
   "VECTOR_MEM_VSX_P (V4SFmode)"
   "#"
-  "&& reload_completed"
+  "&& 1"
   [(set (match_dup 0) (match_dup 4))]
 {
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
 					   operands[3], SFmode);
 }
-  [(set_attr "type" "fpload,fpload,fpload,load")
-   (set_attr "length" "8")
-   (set_attr "isa" "*,p7v,p9v,*")])
+  [(set_attr "type" "fpload,fpload,load,load")
+   (set_attr "length" "4,8,4,8")])
+
+;; V4SF extract from memory and convert to DFmode with constant element number.
+(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
+  [(set (match_operand:DF 0 "register_operand" "=wa,wa")
+	(float_extend:DF
+	 (vec_select:SF
+	  (match_operand:V4SF 1 "memory_operand" "m,Q")
+	  (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")]))))
+   (clobber (match_scratch:P 3 "=X,&b"))]
+  "VECTOR_MEM_VSX_P (V4SFmode)"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(float_extend:DF (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], SFmode);
+}
+  [(set_attr "type" "fpload")
+   (set_attr "length" "4,8")])
 
 ;; Variable V4SF extract from a register
 (define_insn_and_split "vsx_extract_v4sf_var"

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:ef1242f0cfa9c773050c6cebb5770d3152409fef

commit ef1242f0cfa9c773050c6cebb5770d3152409fef
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 18:02:18 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 82745912b34..61634f875b1 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,25 @@
+==================== Branch work119, patch #52 ====================
+
+Improve vec_extract of V4SF with variable element number.
+
+This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
+where the element number is variable combined with a conversion to DFmode.
+
+I also modified the insn for vec_extract of V4SFmode where the element number is
+variable to split before register allocation.
+
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before
+	register allocation.
+	(vsx_extract_v4sf_var_load_to_df): New insn.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-float-2.c: New test.
+
 ==================== Branch work119, patch #51 ====================
 
 Combine vec_extract of V4SF with DF convert.
@@ -6,7 +28,8 @@ This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
 where the element number is constant combined with a conversion to DFmode.
 
 In addition, I changed the vec_extract of V4SFmode where the element number is
-constant without conversion to do the split before register allocation.
+constant without conversion to do the split before register allocation.  I also
+simplified the alternatives.
 
 2023-04-21   Michael Meissner  <meissner@linux.ibm.com>

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:0fdc893628d27b3bc6efda1635b46ab5cfd170fb

commit 0fdc893628d27b3bc6efda1635b46ab5cfd170fb
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 11:23:05 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 156db43a1c1..b16a81f8d58 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -161,7 +161,7 @@ PR target/101169 - Fix test suite insn counts
 
 Adjust insn counts.
 
-2023-04-20   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/testsuite/

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:4481e35da13348a1acf4d17c2a2f0c018c95cf41

commit 4481e35da13348a1acf4d17c2a2f0c018c95cf41
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 00:23:53 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 47 ++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 44 insertions(+), 3 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 29c73d701dd..156db43a1c1 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,8 +1,49 @@
+==================== Branch work119, patch #49 ====================
+
+Fold sign or zero extension into vsx_extract from memory with variable element.
+
+This patch folds conversion to floating point of vsx_extract from memory of V4SI
+elements where the element number is constant.  This code optimizes things so it
+will load the integer with LFIWAX or LFIWZX directly into a vector register
+rather than loading it into a GPR and doing a direct move operation.
+
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<uns><mode>): New
+	insn.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-int-4.c: New file.
+
+==================== Branch work119, patch #48 ====================
+
+Fold sign or zero convert into variable vsx_extract from memory.
+
+This patch folds sign or zero convert operations into vsx_extract from memory
+where the element number is constant.
+
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_<mode>_var_load_to_udi): New insn.
+	(vsx_extract_<mode>_var_load_to_sdi): New insn.
+	(vsx_extract_v8hi_var_load_to_<su>si): New insn.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-char-2.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-short-2.c: New file.
+
 ==================== Branch work119, patch #47 ====================
 
 Allow vec_extract with variable element number to load vector registers.
 
-2023-04-20   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
@@ -17,7 +58,7 @@ Combine variable element vec_extract of V4SF with DF convert.
 This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
 where the element number is variable combined with a conversion to DFmode.
 
-2023-04-20   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
@@ -52,7 +93,7 @@ Fold sign or zero convert into vsx_extract from memory.
 This patch folds sign or zero convert operations into vsx_extract from memory
 where the element number is constant.
 
-2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:29b454a5acd53d82628cbcc42dd5fba0b2c22cf6

commit 29b454a5acd53d82628cbcc42dd5fba0b2c22cf6
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Apr 20 22:57:49 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 925b88c03e2..29c73d701dd 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,15 @@
+==================== Branch work119, patch #47 ====================
+
+Allow vec_extract with variable element number to load vector registers.
+
+2023-04-20   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vec_extract
+	of integer types with a variable element number to load into vector
+	registers.  Allow splitting before register allocation.
+
 ==================== Branch work119, patch #46 ====================
 
 Combine variable element vec_extract of V4SF with DF convert.

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:4c7d6fc21b8bb6133f2cfa9efc0349051e943b41

commit 4c7d6fc21b8bb6133f2cfa9efc0349051e943b41
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Apr 20 16:48:08 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index bc46be9ce86..925b88c03e2 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,4 +1,17 @@
-==================== Branch work119, patch #45 was reverted ====================
+==================== Branch work119, patch #46 ====================
+
+Combine variable element vec_extract of V4SF with DF convert.
+
+This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
+where the element number is variable combined with a conversion to DFmode.
+
+2023-04-20   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4sf_var_load_to_df): New insn.
+
+==================== Branch work119, patch #45 ====================
 
 Fold conversion to float into V4SI vsx_extract from memory.

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:db4c4a2c4a3449374c8c7ac17ae40b786e0c7bad

commit db4c4a2c4a3449374c8c7ac17ae40b786e0c7bad
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Apr 20 15:42:49 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index bf4b77a0dc9..bc46be9ce86 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -89,7 +89,25 @@ gcc/
 
 ==================== Branch work119, patch #30 was reverted ====================
 
-==================== Branch work119, patch #23 was reverted ====================
+==================== Branch work119, patch #23 ====================
+
+PR target/101169 - Fix test suite insn counts
+
+Adjust insn counts.
+
+2023-04-20   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/testsuite/
+
+	PR target/101169
+	* gcc.target/powerpc/fold-vec-extract-char.p7.c: Update insn count.
+	* gcc.target/powerpc/fold-vec-extract-double.p7.c: Likewise.
+	* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
+	* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
+	* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
+	* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
+	* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
+	* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
 
 ==================== Branch work119, patch #22 ====================

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:1ea2a49ccd0b6fec6d5e6d166447ab94795a2b89

commit 1ea2a49ccd0b6fec6d5e6d166447ab94795a2b89
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 19 18:09:27 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 91 ++++++++++++++++++++++++++++----------------------
 1 file changed, 52 insertions(+), 39 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 8fff1cb0c00..bf4b77a0dc9 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,72 +1,66 @@
-==================== Branch work119, patch #23 ====================
+==================== Branch work119, patch #45 was reverted ====================
 
-Optimize V8HI/V16QI vec_extract from memory with constant element number
-
-This patch adds combiner insns to fold in conversion to DImode from vec_extract
-of a V8HI or V16QI variable with constant element number.  With this patch, GCC
-will directly emit LHA, LHZ, or LBZ without needing an instruction to do the
-sign or zero extension.
+Fold conversion to float into V4SI vsx_extract from memory.
 
+This patch folds conversion to floating point of vsx_extract from memory of V4SI
+elements where the element number is constant.  This code optimizes things so it
+will load the integer with LFIWAX or LFIWZX directly into a vector register
+rather than loading it into a GPR and doing a direct move operation.
 
 2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
-	* config/rs6000/vsx.md (vsx_extract_<mode>_load_to_udi): New insn.
-	(sx_extract_v8hi_load_to_sd): New insn.
+	* config/rs6000/vsx.md (SIGN_ZERO_EXTEND): New mode attribute.
+	(vsx_extract_v4si_load_to_<uns><mode>): New insn.
 
 gcc/testsuite/
 
-	* gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
-	* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
 
-==================== Branch work119, patch #22 ====================
+==================== Branch work119, patch #44 was reverted ====================
 
-Add float/double conversions fro V4SI vec_extract
+==================== Branch work119, patch #43 ====================
 
-This patch adds combiner insns to fold in conversion to float, double, or the
-IEEE 128-bit types (both signed and unsigned) of V4SI vec_extract with a
-constant element.  With this patch, GCC will load the SImode value directly into
-the vector register with LFIWZX or LFIWAX instead of doing a LWZ and then moving
-the value over with a direct move before the floating point conversion.
+Fold sign or zero convert into vsx_extract from memory.
+
+This patch folds sign or zero convert operations into vsx_extract from memory
+where the element number is constant.
 
 2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
-	* config/rs6000/vsx.md (SIGN_ZERO): New code attribute.
-	(FL_CONSTRAINT): New code attribute.
-	(vsx_extract_v4si_load_to_<uns><mode): New insn.
+	* config/rs6000/vsx.md (VSX_EXTRACT_ISIGN): New mode attribute.
+	(vsx_extract_<mode>_load_to_udi): New insn.
+	(vsx_extract_<mode>_load_to_sdi): New insn.
+	(vsx_extract_v8hi_load_to_<su>si): New insn.
 
 gcc/testsuite/
 
-	* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
-
-==================== Branch work119, patch #21 ====================
+	* gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-int-1.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
 
-Add sign/zero conversions for V4SI vec_extract
+==================== Branch work119, patch #42 ====================
 
-This patch adds combiner insns to fold in sign and zero extension of vec_extract
-of V4SI with a constant element when expanding to DImode.
+Allow vec_extract to load vector registers.
 
 2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 
-	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>di): New insn.
-
-gcc/testsuite/
-
-	* gcc.target/powerpc/vec-extract-mem-int-2.c: New test.
+	* config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute
+	(vsx_extract_<mode>_load): Allow vec_extract of integer types with a
+	constant element number to load into vector registers.  Allow splitting
+	before register allocation.
 
-==================== Branch work119, patch #21 ====================
+==================== Branch work119, patch #41 ====================
 
-Enhance vec_extract from int memory with constant element numbers.
+Combine vec_extract of V4SF with DF convert.
 
 This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
 where the element number is constant combined with a conversion to DFmode.
-Without this patch, the compiler would load the value into a GPR register and
-then do a direct move if it needs the value in a vector register.
 
 2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
 
@@ -74,9 +68,28 @@ gcc/
 
 	* config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn.
 
-gcc/testsuite/
+==================== Branch work119, patch #40 ====================
+
+Allow vec_extract support functions to be called before reload.
+
+2023-04-19   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000.cc (get_vector_offset): Allow being called before
+	register allocation.
+	(adjust_vec_address_pcrel): Likewise.
+	(rs6000_adjust_vec_address): Likewise.
 
-	* gcc.target/powerpc/vec-extract-mem-int-1.c: New test.
+==================== Branch work119, patch #33 was reverted ====================
+
+==================== Branch work119, patch #32 was reverted ====================
+
+==================== Branch work119, patch #31 was reverted ====================
+
+==================== Branch work119, patch #30 was reverted ====================
+
+==================== Branch work119, patch #23 was reverted ====================
 
 ==================== Branch work119, patch #22 ====================
 
@@ -88,7 +101,7 @@ In doing other work, I noticed that there was an insn:
 
 Which did not have an iterator.  I removed the useless <mode>.
 
-2023-04-17   Michael Meissner  <meissner@linux.ibm.com>
+2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:2c37d93bf15ae8f5b0bcfe7c91108d5ff262d2f1

commit 2c37d93bf15ae8f5b0bcfe7c91108d5ff262d2f1
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Apr 18 18:16:33 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 88bdd55c470..8fff1cb0c00 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,4 +1,26 @@
-==================== Branch work119, patch #21 ====================
+==================== Branch work119, patch #23 ====================
+
+Optimize V8HI/V16QI vec_extract from memory with constant element number
+
+This patch adds combiner insns to fold in conversion to DImode from vec_extract
+of a V8HI or V16QI variable with constant element number.  With this patch, GCC
+will directly emit LHA, LHZ, or LBZ without needing an instruction to do the
+sign or zero extension.
+
+
+2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_<mode>_load_to_udi): New insn.
+	(sx_extract_v8hi_load_to_sd): New insn.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
+
+==================== Branch work119, patch #22 ====================
 
 Add float/double conversions fro V4SI vec_extract

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:222af81c70a3c23cd31b453fdf524a52de07a2ff

commit 222af81c70a3c23cd31b453fdf524a52de07a2ff
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Apr 18 01:45:23 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 49592e20a32..88bdd55c470 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,5 +1,80 @@
 ==================== Branch work119, patch #21 ====================
 
+Add float/double conversions fro V4SI vec_extract
+
+This patch adds combiner insns to fold in conversion to float, double, or the
+IEEE 128-bit types (both signed and unsigned) of V4SI vec_extract with a
+constant element.  With this patch, GCC will load the SImode value directly into
+the vector register with LFIWZX or LFIWAX instead of doing a LWZ and then moving
+the value over with a direct move before the floating point conversion.
+
+2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (SIGN_ZERO): New code attribute.
+	(FL_CONSTRAINT): New code attribute.
+	(vsx_extract_v4si_load_to_<uns><mode): New insn.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
+
+==================== Branch work119, patch #21 ====================
+
+Add sign/zero conversions for V4SI vec_extract
+
+This patch adds combiner insns to fold in sign and zero extension of vec_extract
+of V4SI with a constant element when expanding to DImode.
+
+2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>di): New insn.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-int-2.c: New test.
+
+==================== Branch work119, patch #21 ====================
+
+Enhance vec_extract from int memory with constant element numbers.
+
+This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
+where the element number is constant combined with a conversion to DFmode.
+Without this patch, the compiler would load the value into a GPR register and
+then do a direct move if it needs the value in a vector register.
+
+2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-int-1.c: New test.
+
+==================== Branch work119, patch #22 ====================
+
+Fix typo in insn name.
+
+In doing other work, I noticed that there was an insn:
+
+	vsx_extract_v4sf_<mode>_load
+
+Which did not have an iterator.  I removed the useless <mode>.
+
+2023-04-17   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4sf_load): Rename from
+	vsx_extract_v4sf_<mode>_load.
+
+==================== Branch work119, patch #21 ====================
+
 Improve 64->128 bit zero extension on PowerPC
 
 2023-04-17   Michael Meissner  <meissner@linux.ibm.com>

[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:c5af745c7de80750d4c2e769a5bda1705b8ebe4c

commit c5af745c7de80750d4c2e769a5bda1705b8ebe4c
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Apr 17 16:02:48 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 99 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 99 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index bf4cb40ab10..49592e20a32 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,102 @@
+==================== Branch work119, patch #21 ====================
+
+Improve 64->128 bit zero extension on PowerPC
+
+2023-04-17   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	PR target/108958
+	* gcc/config/rs6000.md (zero_extendditi2): New insn.
+
+gcc/testsuite/
+
+	PR target/108958
+	* gcc.target/powerpc/zero-extend-di-ti.c: New test.
+
+==================== Branch work119, patch #20 ====================
+
+Fix splat of extract for long long and double.
+
+2023-04-17   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	PR target/99293
+	* gcc/config/rs6000/vsx.md (vsx_splat_extract_<mode>): New combiner
+	insn.
+
+gcc/testsuite/
+
+	PR target/108958
+	* gcc.target/powerpc/pr99293.c: New test.
+	* gcc.target/powerpc/builtins-1.c: Update insn count.
+
+
+==================== Branch work119, patch #1 ====================
+
+Make load/cmp fusion know about prefixed loads.
+
+I posted a version of patch on March 21st and a second version on March 24th.
+This patch makes some code changes suggested in the genfusion.pl code from the
+last 2 patch submissions.  The fusion.md that is produced by genfusion.pl is
+the same in all 3 versions.
+
+I changed the genfusion.pl to match the suggestion for code layout.  I also
+used the correct comment for each of the instructions (in the 2nd patch, the
+when I rewrote the comments about ld and lwa being DS format instructions, I
+had put the ld comment in the section handling lwa, and vice versa).
+
+I also removed lp64 from the new test.  When I first added the prefixed code,
+it was only done for 64-bit, but now it is allowed for 32-bit.  However, the
+case that shows up (lwa) would not hit in 32-bit, since it only generates lwz
+and not lwa.  It also would not generate ld.  But the test does pass when it is
+built with -m32.
+
+The issue with the bug is the power10 load GPR + cmpi -1/0/1 fusion
+optimization generates illegal assembler code.
+
+Ultimately the code was dying because the fusion load + compare -1/0/1 patterns
+did not handle the possibility that the load might be prefixed.
+
+The main cause is the constraints for the individual loads in the fusion did not
+match the machine.  In particular, LWA is a ds format instruction when it is
+unprefixed.  The code did not also set the prefixed attribute correctly.
+
+This patch rewrites the genfusion.pl script so that it will have more accurate
+constraints for the LWA and LD instructions (which are DS instructions).  The
+updated genfusion.pl was then run to update fusion.md.  Finally, the code for
+the "prefixed" attribute is modified so that it considers load + compare
+immediate patterns to be like the normal load insns in checking whether
+operand[1] is a prefixed instruction.
+
+I have tested this code on a power9 little endian system (with long double
+being IEEE 128-bit and IBM 128-bit), a power10 little endian system, and a
+power8 big endian system, testing both 32-bit and 64-bit code generation.  Can
+I put this code into the master branch, and after a waiting period, apply it to
+the GCC 12 and GCC 11 branches (the bug does show up in those branches, and the
+patch applies without change).
+
+2023-04-17   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	PR target/105325
+	* gcc/config/rs6000/genfusion.pl (gen_ld_cmpi_p10): Improve generation
+	of the ld and lwa instructions which use the DS encoding instead of D.
+	Use the YZ constraint for these loads.	Handle prefixed loads better.
+	Set the sign_extend attribute as appropriate.
+	* gcc/config/rs6000/fusion.md: Regenerate.
+	* gcc/config/rs6000/rs6000.md (prefixed attribute): Add fused_load_cmpi
+	instructions to the list of instructions that might have a prefixed load
+	instruction.
+
+gcc/testsuite/
+
+	PR target/105325
+	* g++.target/powerpc/pr105325.C: New test.
+	* gcc.target/powerpc/fusion-p10-ldcmpi.c: Adjust insn counts.
+
 ==================== Branch work119, baseline ====================
 
 2023-04-17   Michael Meissner  <meissner@linux.ibm.com>