* [PATCH v6 1/9] RISC-V: autovec: Add new predicates and function prototypes
2023-05-05 15:45 [PATCH v6 0/9] RISC-V: autovec: Add autovec support Michael Collison
@ 2023-05-05 15:45 ` Michael Collison
2023-05-06 17:01 ` Jeff Law
2023-05-05 15:46 ` [PATCH v6 2/9] RISC-V: autovec: Export policy functions to global scope Michael Collison
` (8 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Michael Collison @ 2023-05-05 15:45 UTC (permalink / raw)
To: gcc-patches
2023-04-24 Michael Collison <collison@rivosinc.com>
Juzhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-protos.h
(riscv_vector_preferred_simd_mode): New.
(riscv_vector_mask_mode_p): Ditto.
(riscv_vector_get_mask_mode): Ditto.
(emit_vlmax_vsetvl): Ditto.
(get_mask_policy_no_pred): Ditto.
(get_tail_policy_no_pred): Ditto.
(vlmul_field_enum): Ditto.
* config/riscv/riscv-v.cc (emit_vlmax_vsetvl):
Remove static scope.
* config/riscv/riscv-opts.h (riscv_vector_lmul_enum): New enum.
---
gcc/config/riscv/riscv-opts.h | 10 ++++++++++
gcc/config/riscv/riscv-protos.h | 9 +++++++++
2 files changed, 19 insertions(+)
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 4207db240ea..00c4ab222ae 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -67,6 +67,7 @@ enum stack_protector_guard {
SSP_GLOBAL /* global canary */
};
+
/* RISC-V auto-vectorization preference. */
enum riscv_autovec_preference_enum {
NO_AUTOVEC,
@@ -82,6 +83,15 @@ enum riscv_autovec_lmul_enum {
RVV_M8 = 8
};
+/* vectorization factor. */
+enum riscv_vector_lmul_enum
+{
+ RVV_LMUL1 = 1,
+ RVV_LMUL2 = 2,
+ RVV_LMUL4 = 4,
+ RVV_LMUL8 = 8
+};
+
#define MASK_ZICSR (1 << 0)
#define MASK_ZIFENCEI (1 << 1)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 33eb574aadc..fb39b856735 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -243,4 +243,13 @@ th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
#endif
extern bool riscv_use_divmod_expander (void);
+/* Routines implemented in riscv-v.cc. */
+
+namespace riscv_vector {
+extern machine_mode riscv_vector_preferred_simd_mode (scalar_mode mode);
+extern bool riscv_vector_mask_mode_p (machine_mode);
+extern opt_machine_mode riscv_vector_get_mask_mode (machine_mode mode);
+extern rtx get_mask_policy_no_pred ();
+extern rtx get_tail_policy_no_pred ();
+}
#endif /* ! GCC_RISCV_PROTOS_H */
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v6 1/9] RISC-V: autovec: Add new predicates and function prototypes
2023-05-05 15:45 ` [PATCH v6 1/9] RISC-V: autovec: Add new predicates and function prototypes Michael Collison
@ 2023-05-06 17:01 ` Jeff Law
0 siblings, 0 replies; 17+ messages in thread
From: Jeff Law @ 2023-05-06 17:01 UTC (permalink / raw)
To: Michael Collison, gcc-patches
On 5/5/23 09:45, Michael Collison wrote:
> 2023-04-24 Michael Collison <collison@rivosinc.com>
> Juzhe Zhong <juzhe.zhong@rivai.ai>
>
> * config/riscv/riscv-protos.h
> (riscv_vector_preferred_simd_mode): New.
> (riscv_vector_mask_mode_p): Ditto.
> (riscv_vector_get_mask_mode): Ditto.
> (emit_vlmax_vsetvl): Ditto.
> (get_mask_policy_no_pred): Ditto.
> (get_tail_policy_no_pred): Ditto.
> (vlmul_field_enum): Ditto.
> * config/riscv/riscv-v.cc (emit_vlmax_vsetvl):
> Remove static scope.
> * config/riscv/riscv-opts.h (riscv_vector_lmul_enum): New enum.
> ---
> gcc/config/riscv/riscv-opts.h | 10 ++++++++++
> gcc/config/riscv/riscv-protos.h | 9 +++++++++
> 2 files changed, 19 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 4207db240ea..00c4ab222ae 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -67,6 +67,7 @@ enum stack_protector_guard {
> SSP_GLOBAL /* global canary */
> };
>
> +
> /* RISC-V auto-vectorization preference. */
> enum riscv_autovec_preference_enum {
> NO_AUTOVEC,
Extranous change. Removed.
> @@ -82,6 +83,15 @@ enum riscv_autovec_lmul_enum {
> RVV_M8 = 8
> };
>
> +/* vectorization factor. */
> +enum riscv_vector_lmul_enum
> +{
> + RVV_LMUL1 = 1,
> + RVV_LMUL2 = 2,
> + RVV_LMUL4 = 4,
> + RVV_LMUL8 = 8
> +};
> +
> #define MASK_ZICSR (1 << 0)
> #define MASK_ZIFENCEI (1 << 1)
>
I ack'd this hunk earlier, but Kito asked for it to be removed. Given I
don't see any uses of LMUL in the series, I'm just going to remove this
for now. We can always add it back at the point where we need it.
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 33eb574aadc..fb39b856735 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -243,4 +243,13 @@ th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
> #endif
>
> extern bool riscv_use_divmod_expander (void);
> +/* Routines implemented in riscv-v.cc. */
> +
> +namespace riscv_vector {
> +extern machine_mode riscv_vector_preferred_simd_mode (scalar_mode mode);
This prototype is on the trunk now.
> +extern bool riscv_vector_mask_mode_p (machine_mode);
> +extern opt_machine_mode riscv_vector_get_mask_mode (machine_mode mode);
> +extern rtx get_mask_policy_no_pred ();
> +extern rtx get_tail_policy_no_pred ();
I'll go ahead and commit these. I think that's all that's left from
this patch. Going forward, the right time to add the prototypes is in
the same patch that adds the function.
Jeff
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v6 2/9] RISC-V: autovec: Export policy functions to global scope
2023-05-05 15:45 [PATCH v6 0/9] RISC-V: autovec: Add autovec support Michael Collison
2023-05-05 15:45 ` [PATCH v6 1/9] RISC-V: autovec: Add new predicates and function prototypes Michael Collison
@ 2023-05-05 15:46 ` Michael Collison
2023-05-06 17:20 ` Jeff Law
2023-05-05 15:46 ` [PATCH v6 3/9] RISC-V:autovec: Add auto-vectorization support functions Michael Collison
` (7 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Michael Collison @ 2023-05-05 15:46 UTC (permalink / raw)
To: gcc-patches
2023-03-02 Michael Collison <collison@rivosinc.com>
Juzhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred):
Remove static declaration to to make externally visible.
(get_mask_policy_for_pred): Ditto.
* config/riscv/riscv-vector-builtins.h (get_tail_policy_for_pred):
New external declaration.
(get_mask_policy_for_pred): Ditto.
---
gcc/config/riscv/riscv-vector-builtins.cc | 4 ++--
gcc/config/riscv/riscv-vector-builtins.h | 3 +++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 434bd8e157b..f0ebc095fa7 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -2496,7 +2496,7 @@ use_real_merge_p (enum predication_type_index pred)
/* Get TAIL policy for predication. If predication indicates TU, return the TU.
Otherwise, return the prefer default configuration. */
-static rtx
+rtx
get_tail_policy_for_pred (enum predication_type_index pred)
{
if (pred == PRED_TYPE_tu || pred == PRED_TYPE_tum || pred == PRED_TYPE_tumu)
@@ -2506,7 +2506,7 @@ get_tail_policy_for_pred (enum predication_type_index pred)
/* Get MASK policy for predication. If predication indicates MU, return the MU.
Otherwise, return the prefer default configuration. */
-static rtx
+rtx
get_mask_policy_for_pred (enum predication_type_index pred)
{
if (pred == PRED_TYPE_tumu || pred == PRED_TYPE_mu)
diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h
index 8ffb9d33e33..de3fd6ca290 100644
--- a/gcc/config/riscv/riscv-vector-builtins.h
+++ b/gcc/config/riscv/riscv-vector-builtins.h
@@ -483,6 +483,9 @@ extern rvv_builtin_types_t builtin_types[NUM_VECTOR_TYPES + 1];
extern function_instance get_read_vl_instance (void);
extern tree get_read_vl_decl (void);
+extern rtx get_tail_policy_for_pred (enum predication_type_index pred);
+extern rtx get_mask_policy_for_pred (enum predication_type_index pred);
+
inline tree
rvv_arg_type_info::get_scalar_type (vector_type_index type_idx) const
{
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v6 3/9] RISC-V:autovec: Add auto-vectorization support functions
2023-05-05 15:45 [PATCH v6 0/9] RISC-V: autovec: Add autovec support Michael Collison
2023-05-05 15:45 ` [PATCH v6 1/9] RISC-V: autovec: Add new predicates and function prototypes Michael Collison
2023-05-05 15:46 ` [PATCH v6 2/9] RISC-V: autovec: Export policy functions to global scope Michael Collison
@ 2023-05-05 15:46 ` Michael Collison
2023-05-06 17:33 ` Jeff Law
2023-05-05 15:46 ` [PATCH v6 4/9] RISC-V:autovec: Add target vectorization hooks Michael Collison
` (6 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Michael Collison @ 2023-05-05 15:46 UTC (permalink / raw)
To: gcc-patches
2023-04-24 Michael Collison <collison@rivosinc.com>
Juzhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-v.cc
(riscv_vector_preferred_simd_mode): New function.
(get_mask_policy_no_pred): Ditto.
(get_tail_policy_no_pred): Ditto.
(riscv_vector_mask_mode_p): Ditto.
(riscv_vector_get_mask_mode): Ditto.
---
gcc/config/riscv/riscv-v.cc | 91 +++++++++++++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 99c414cc910..7faffb55046 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -39,9 +39,11 @@
#include "emit-rtl.h"
#include "tm_p.h"
#include "target.h"
+#include "targhooks.h"
#include "expr.h"
#include "optabs.h"
#include "tm-constrs.h"
+#include "riscv-vector-builtins.h"
#include "rtx-vector-builder.h"
using namespace riscv_vector;
@@ -176,6 +178,56 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul)
return ratio;
}
+/* SCALABLE means that the vector-length is agnostic (run-time invariant and
+ compile-time unknown). FIXED meands that the vector-length is specific
+ (compile-time known). Both RVV_SCALABLE and RVV_FIXED_VLMAX are doing
+ auto-vectorization using VLMAX vsetvl configuration. */
+static bool
+autovec_use_vlmax_p (void)
+{
+ return riscv_autovec_preference == RVV_SCALABLE
+ || riscv_autovec_preference == RVV_FIXED_VLMAX;
+}
+
+/* Return the vectorization machine mode for RVV according to LMUL. */
+machine_mode
+riscv_vector_preferred_simd_mode (scalar_mode mode)
+{
+ /* We only enable auto-vectorization when TARGET_MIN_VLEN >= 128 &&
+ riscv_autovec_lmul < RVV_M2. Since GCC loop vectorizer report ICE
+ when we enable -march=rv64gc_zve32* and -march=rv32gc_zve64*.
+ in the 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. Since we have
+ VNx1SImode in -march=*zve32* and VNx1DImode in -march=*zve64*, they are
+ enabled in targetm. vector_mode_supported_p and SLP vectorizer will try to
+ use them. Currently, we can support auto-vectorization in
+ -march=rv32_zve32x_zvl128b. Wheras, -march=rv32_zve32x_zvl32b or
+ -march=rv32_zve32x_zvl64b are disabled.
+ */
+ if (autovec_use_vlmax_p ())
+ {
+ /* If TARGET_MIN_VLEN < 128, we don't allow LMUL < 2
+ auto-vectorization since Loop Vectorizer may use VNx1SImode or
+ VNx1DImode to vectorize which will create ICE in the
+ 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. */
+ if (TARGET_MIN_VLEN < 128 && riscv_autovec_lmul < RVV_M2)
+ return word_mode;
+ /* We use LMUL = 1 as base bytesize which is BYTES_PER_RISCV_VECTOR and
+ riscv_autovec_lmul as multiply factor to calculate the the NUNITS to
+ get the auto-vectorization mode. */
+ poly_uint64 nunits;
+ poly_uint64 vector_size
+ = BYTES_PER_RISCV_VECTOR * ((int) riscv_autovec_lmul);
+ poly_uint64 scalar_size = GET_MODE_SIZE (mode);
+ gcc_assert (multiple_p (vector_size, scalar_size, &nunits));
+ machine_mode rvv_mode;
+ if (get_vector_mode (mode, nunits).exists (&rvv_mode))
+ return rvv_mode;
+ }
+ /* TODO: We will support minimum length VLS auto-vectorization in the future.
+ */
+ return word_mode;
+}
+
/* Emit an RVV unmask && vl mov from SRC to DEST. */
static void
emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len,
@@ -430,6 +482,45 @@ get_avl_type_rtx (enum avl_type type)
return gen_int_mode (type, Pmode);
}
+/* Return the mask policy for no predication. */
+rtx
+get_mask_policy_no_pred ()
+{
+ return get_mask_policy_for_pred (PRED_TYPE_none);
+}
+
+/* Return the tail policy for no predication. */
+rtx
+get_tail_policy_no_pred ()
+{
+ return get_tail_policy_for_pred (PRED_TYPE_none);
+}
+
+/* Return true if it is a RVV mask mode. */
+bool
+riscv_vector_mask_mode_p (machine_mode mode)
+{
+ return (mode == VNx1BImode || mode == VNx2BImode || mode == VNx4BImode
+ || mode == VNx8BImode || mode == VNx16BImode || mode == VNx32BImode
+ || mode == VNx64BImode);
+}
+
+/* Return the appropriate mask mode for MODE. */
+
+opt_machine_mode
+riscv_vector_get_mask_mode (machine_mode mode)
+{
+ machine_mode mask_mode;
+ int nf = 1;
+
+ FOR_EACH_MODE_IN_CLASS (mask_mode, MODE_VECTOR_BOOL)
+ if (GET_MODE_INNER (mask_mode) == BImode
+ && known_eq (GET_MODE_NUNITS (mask_mode) * nf, GET_MODE_NUNITS (mode))
+ && riscv_vector_mask_mode_p (mask_mode))
+ return mask_mode;
+ return default_get_mask_mode (mode);
+}
+
/* Return the RVV vector mode that has NUNITS elements of mode INNER_MODE.
This function is not only used by builtins, but also will be used by
auto-vectorization in the future. */
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v6 3/9] RISC-V:autovec: Add auto-vectorization support functions
2023-05-05 15:46 ` [PATCH v6 3/9] RISC-V:autovec: Add auto-vectorization support functions Michael Collison
@ 2023-05-06 17:33 ` Jeff Law
0 siblings, 0 replies; 17+ messages in thread
From: Jeff Law @ 2023-05-06 17:33 UTC (permalink / raw)
To: Michael Collison, juzhe.zhong; +Cc: gcc-patches
On 5/5/23 09:46, Michael Collison wrote:
> 2023-04-24 Michael Collison <collison@rivosinc.com>
> Juzhe Zhong <juzhe.zhong@rivai.ai>
>
> * config/riscv/riscv-v.cc
> (riscv_vector_preferred_simd_mode): New function.
> (get_mask_policy_no_pred): Ditto.
> (get_tail_policy_no_pred): Ditto.
> (riscv_vector_mask_mode_p): Ditto.
> (riscv_vector_get_mask_mode): Ditto.
Didn't include the addition of autovec_use_vlmax_p. Fixed.
> ---
>
> +/* SCALABLE means that the vector-length is agnostic (run-time invariant and
> + compile-time unknown). FIXED meands that the vector-length is specific
> + (compile-time known). Both RVV_SCALABLE and RVV_FIXED_VLMAX are doing
> + auto-vectorization using VLMAX vsetvl configuration. */
> +static bool
> +autovec_use_vlmax_p (void)
> +{
> + return riscv_autovec_preference == RVV_SCALABLE
> + || riscv_autovec_preference == RVV_FIXED_VLMAX;
When a line gets wrapped, add parens and adjust indentation accordingly.
I've fixed it this time in the interests of getting this stuff unblocked.
> +}
> +
> +/* Return the vectorization machine mode for RVV according to LMUL. */
> +machine_mode
> +riscv_vector_preferred_simd_mode (scalar_mode mode)
> +{
> + /* We only enable auto-vectorization when TARGET_MIN_VLEN >= 128 &&
> + riscv_autovec_lmul < RVV_M2. Since GCC loop vectorizer report ICE
> + when we enable -march=rv64gc_zve32* and -march=rv32gc_zve64*.
> + in the 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. Since we have
> + VNx1SImode in -march=*zve32* and VNx1DImode in -march=*zve64*, they are
> + enabled in targetm. vector_mode_supported_p and SLP vectorizer will try to
> + use them. Currently, we can support auto-vectorization in
> + -march=rv32_zve32x_zvl128b. Wheras, -march=rv32_zve32x_zvl32b or
> + -march=rv32_zve32x_zvl64b are disabled.
> + */
Another nit. Go ahead and close the comment on the last line of text.
I think my question from last week still stands.
> + if (autovec_use_vlmax_p ())
> + {
> + /* If TARGET_MIN_VLEN < 128, we don't allow LMUL < 2
> + auto-vectorization since Loop Vectorizer may use VNx1SImode or
> + VNx1DImode to vectorize which will create ICE in the
> + 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. */
Seems redundant with outer conditional. Removed.
> + if (TARGET_MIN_VLEN < 128 && riscv_autovec_lmul < RVV_M2)
> + return word_mode;
> + /* We use LMUL = 1 as base bytesize which is BYTES_PER_RISCV_VECTOR and
> + riscv_autovec_lmul as multiply factor to calculate the the NUNITS to
> + get the auto-vectorization mode. *
> + poly_uint64 nunits;
> + poly_uint64 vector_size
> + = BYTES_PER_RISCV_VECTOR * ((int) riscv_autovec_lmul);
> + poly_uint64 scalar_size = GET_MODE_SIZE (mode);
> + gcc_assert (multiple_p (vector_size, scalar_size, &nunits));
> + machine_mode rvv_mode;
> + if (get_vector_mode (mode, nunits).exists (&rvv_mode))
> + return rvv_mode;
> + }
> + /* TODO: We will support minimum length VLS auto-vectorization in the future.
> + */
Rewrapped to avoid having the close comment on a line by itself.
> @@ -430,6 +482,45 @@ get_avl_type_rtx (enum avl_type type)
> return gen_int_mode (type, Pmode);
> }
>
> +/* Return the mask policy for no predication. */
> +rtx
> +get_mask_policy_no_pred ()
> +{
> + return get_mask_policy_for_pred (PRED_TYPE_none);
> +}
> +
> +/* Return the tail policy for no predication. */
> +rtx
> +get_tail_policy_no_pred ()
> +{
> + return get_tail_policy_for_pred (PRED_TYPE_none);
> +}
Added explicit "void" to the argument list for those two functions.
> +/* Return the appropriate mask mode for MODE. */
> +
> +opt_machine_mode
> +riscv_vector_get_mask_mode (machine_mode mode)
> +{
> + machine_mode mask_mode;
> + int nf = 1;
> +
> + FOR_EACH_MODE_IN_CLASS (mask_mode, MODE_VECTOR_BOOL)
> + if (GET_MODE_INNER (mask_mode) == BImode
> + && known_eq (GET_MODE_NUNITS (mask_mode) * nf, GET_MODE_NUNITS (mode))
> + && riscv_vector_mask_mode_p (mask_mode))
> + return mask_mode;
Presumably the IF is part of the loop, meaning it needs to be indented
to show that relationship. Fixed.
Pushed to the trunk with the above fixes.
jeff
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v6 4/9] RISC-V:autovec: Add target vectorization hooks
2023-05-05 15:45 [PATCH v6 0/9] RISC-V: autovec: Add autovec support Michael Collison
` (2 preceding siblings ...)
2023-05-05 15:46 ` [PATCH v6 3/9] RISC-V:autovec: Add auto-vectorization support functions Michael Collison
@ 2023-05-05 15:46 ` Michael Collison
2023-05-06 18:28 ` Jeff Law
2023-05-05 15:46 ` [PATCH v6 5/9] RISC-V:autovec: Add autovectorization patterns for binary integer & len_load/store Michael Collison
` (5 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Michael Collison @ 2023-05-05 15:46 UTC (permalink / raw)
To: gcc-patches
2023-04-24 Michael Collison <collison@rivosinc.com>
Juzhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv.cc
(riscv_estimated_poly_value): Implement
TARGET_ESTIMATED_POLY_VALUE.
(riscv_preferred_simd_mode): Implement
TARGET_VECTORIZE_PREFERRED_SIMD_MODE.
(riscv_get_mask_mode): Implement TARGET_VECTORIZE_GET_MASK_MODE.
(riscv_empty_mask_is_expensive): Implement
TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE.
(riscv_vectorize_create_costs): Implement
TARGET_VECTORIZE_CREATE_COSTS.
(riscv_support_vector_misalignment): Implement
TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT.
(TARGET_ESTIMATED_POLY_VALUE): Register target macro.
(TARGET_VECTORIZE_GET_MASK_MODE): Ditto.
(TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE): Ditto.
(TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT): Ditto.
---
gcc/config/riscv/riscv.cc | 130 ++++++++++++++++++++++++++++++++++++++
1 file changed, 130 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 1e328f6a801..1425f50d80a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -60,6 +60,15 @@ along with GCC; see the file COPYING3. If not see
#include "opts.h"
#include "tm-constrs.h"
#include "rtl-iter.h"
+#include "gimple.h"
+#include "cfghooks.h"
+#include "cfgloop.h"
+#include "cfgrtl.h"
+#include "sel-sched.h"
+#include "fold-const.h"
+#include "gimple-iterator.h"
+#include "gimple-expr.h"
+#include "tree-vectorizer.h"
/* This file should be included last. */
#include "target-def.h"
@@ -7138,6 +7147,112 @@ riscv_dwarf_poly_indeterminate_value (unsigned int i, unsigned int *factor,
return RISCV_DWARF_VLENB;
}
+/* Implement TARGET_ESTIMATED_POLY_VALUE.
+ Look into the tuning structure for an estimate.
+ KIND specifies the type of requested estimate: min, max or likely.
+ For cores with a known RVV width all three estimates are the same.
+ For generic RVV tuning we want to distinguish the maximum estimate from
+ the minimum and likely ones.
+ The likely estimate is the same as the minimum in that case to give a
+ conservative behavior of auto-vectorizing with RVV when it is a win
+ even for 128-bit RVV.
+ When RVV width information is available VAL.coeffs[1] is multiplied by
+ the number of VQ chunks over the initial Advanced SIMD 128 bits. */
+
+static HOST_WIDE_INT
+riscv_estimated_poly_value (poly_int64 val,
+ poly_value_estimate_kind kind = POLY_VALUE_LIKELY)
+{
+ unsigned int width_source = BITS_PER_RISCV_VECTOR.is_constant ()
+ ? (unsigned int) BITS_PER_RISCV_VECTOR.to_constant ()
+ : (unsigned int) RVV_SCALABLE;
+
+ /* If there is no core-specific information then the minimum and likely
+ values are based on 128-bit vectors and the maximum is based on
+ the architectural maximum of 65536 bits. */
+ if (width_source == RVV_SCALABLE)
+ switch (kind)
+ {
+ case POLY_VALUE_MIN:
+ case POLY_VALUE_LIKELY:
+ return val.coeffs[0];
+
+ case POLY_VALUE_MAX:
+ return val.coeffs[0] + val.coeffs[1] * 15;
+ }
+
+ /* Allow BITS_PER_RISCV_VECTOR to be a bitmask of different VL, treating the
+ lowest as likely. This could be made more general if future -mtune
+ options need it to be. */
+ if (kind == POLY_VALUE_MAX)
+ width_source = 1 << floor_log2 (width_source);
+ else
+ width_source = least_bit_hwi (width_source);
+
+ /* If the core provides width information, use that. */
+ HOST_WIDE_INT over_128 = width_source - 128;
+ return val.coeffs[0] + val.coeffs[1] * over_128 / 128;
+}
+
+/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
+
+static machine_mode
+riscv_preferred_simd_mode (scalar_mode mode)
+{
+ if (TARGET_VECTOR)
+ return riscv_vector::riscv_vector_preferred_simd_mode (mode);
+
+ return word_mode;
+}
+
+bool
+riscv_support_vector_misalignment (machine_mode mode,
+ const_tree type ATTRIBUTE_UNUSED,
+ int misalignment,
+ bool is_packed ATTRIBUTE_UNUSED)
+{
+ if (TARGET_VECTOR)
+ {
+ if (STRICT_ALIGNMENT)
+ {
+ /* Return if movmisalign pattern is not supported for this mode. */
+ if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
+ return false;
+
+ /* Misalignment factor is unknown at compile time. */
+ if (misalignment == -1)
+ return false;
+ }
+ return true;
+ }
+
+ return default_builtin_support_vector_misalignment (mode, type, misalignment,
+ is_packed);
+}
+
+/* Implement TARGET_VECTORIZE_GET_MASK_MODE. */
+
+static opt_machine_mode
+riscv_get_mask_mode (machine_mode mode)
+{
+ machine_mode mask_mode = VOIDmode;
+ if (TARGET_VECTOR
+ && riscv_vector::riscv_vector_get_mask_mode (mode).exists (&mask_mode))
+ return mask_mode;
+
+ return default_get_mask_mode (mode);
+}
+
+/* Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. Assume for now that
+ it isn't worth branching around empty masked ops (including masked
+ stores). */
+
+static bool
+riscv_empty_mask_is_expensive (unsigned)
+{
+ return false;
+}
+
/* Return true if a shift-amount matches the trailing cleared bits on
a bitmask. */
@@ -7522,9 +7637,24 @@ riscv_use_divmod_expander (void)
#undef TARGET_VERIFY_TYPE_CONTEXT
#define TARGET_VERIFY_TYPE_CONTEXT riscv_verify_type_context
+#undef TARGET_ESTIMATED_POLY_VALUE
+#define TARGET_ESTIMATED_POLY_VALUE riscv_estimated_poly_value
+
+#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
+#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE riscv_preferred_simd_mode
+
+#undef TARGET_VECTORIZE_GET_MASK_MODE
+#define TARGET_VECTORIZE_GET_MASK_MODE riscv_get_mask_mode
+
+#undef TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE
+#define TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE riscv_empty_mask_is_expensive
+
#undef TARGET_VECTOR_ALIGNMENT
#define TARGET_VECTOR_ALIGNMENT riscv_vector_alignment
+#undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
+#define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT riscv_support_vector_misalignment
+
#undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
#define TARGET_DWARF_POLY_INDETERMINATE_VALUE riscv_dwarf_poly_indeterminate_value
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v6 4/9] RISC-V:autovec: Add target vectorization hooks
2023-05-05 15:46 ` [PATCH v6 4/9] RISC-V:autovec: Add target vectorization hooks Michael Collison
@ 2023-05-06 18:28 ` Jeff Law
0 siblings, 0 replies; 17+ messages in thread
From: Jeff Law @ 2023-05-06 18:28 UTC (permalink / raw)
To: Michael Collison, gcc-patches
On 5/5/23 09:46, Michael Collison wrote:
> 2023-04-24 Michael Collison <collison@rivosinc.com>
> Juzhe Zhong <juzhe.zhong@rivai.ai>
>
> * config/riscv/riscv.cc
> (riscv_estimated_poly_value): Implement
> TARGET_ESTIMATED_POLY_VALUE.
> (riscv_preferred_simd_mode): Implement
> TARGET_VECTORIZE_PREFERRED_SIMD_MODE.
> (riscv_get_mask_mode): Implement TARGET_VECTORIZE_GET_MASK_MODE.
> (riscv_empty_mask_is_expensive): Implement
> TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE.
> (riscv_vectorize_create_costs): Implement
> TARGET_VECTORIZE_CREATE_COSTS.
> (riscv_support_vector_misalignment): Implement
> TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT.
> (TARGET_ESTIMATED_POLY_VALUE): Register target macro.
> (TARGET_VECTORIZE_GET_MASK_MODE): Ditto.
> (TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE): Ditto.
> (TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT): Ditto.
Thanks. I removed the duplicated preferred_simd_mode definition and
related macro and pushed this to the trunk.
jeff
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v6 5/9] RISC-V:autovec: Add autovectorization patterns for binary integer & len_load/store
2023-05-05 15:45 [PATCH v6 0/9] RISC-V: autovec: Add autovec support Michael Collison
` (3 preceding siblings ...)
2023-05-05 15:46 ` [PATCH v6 4/9] RISC-V:autovec: Add target vectorization hooks Michael Collison
@ 2023-05-05 15:46 ` Michael Collison
2023-05-05 15:46 ` [PATCH v6 6/9] RISC-V:autovec: Add autovectorization tests for add & sub Michael Collison
` (4 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Michael Collison @ 2023-05-05 15:46 UTC (permalink / raw)
To: gcc-patches
2023-04-25 Michael Collison <collison@rivosinc.com>
Juzhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include
vector-iterators.md.
* config/riscv/vector-auto.md: New file containing
autovectorization patterns.
* config/riscv/vector.md: Remove include of vector-iterators.md
and include vector-auto.md.
---
gcc/config/riscv/riscv.md | 1 +
gcc/config/riscv/vector-auto.md | 74 +++++++++++++++++++++++++++++++++
gcc/config/riscv/vector.md | 4 +-
3 files changed, 77 insertions(+), 2 deletions(-)
create mode 100644 gcc/config/riscv/vector-auto.md
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index c508ee3ad89..e9b49eda617 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -140,6 +140,7 @@
(include "predicates.md")
(include "constraints.md")
(include "iterators.md")
+(include "vector-iterators.md")
;; ....................
;;
diff --git a/gcc/config/riscv/vector-auto.md b/gcc/config/riscv/vector-auto.md
new file mode 100644
index 00000000000..83d2ab6957a
--- /dev/null
+++ b/gcc/config/riscv/vector-auto.md
@@ -0,0 +1,74 @@
+;; Machine description for RISC-V 'V' Extension for GNU compiler.
+;; Copyright (C) 2022-2023 Free Software Foundation, Inc.
+;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
+;; Contributed by Michael Collison (collison@rivosinc.com, Rivos Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; len_load/len_store is a sub-optimal pattern for RVV auto-vectorization support.
+;; We will replace them when len_maskload/len_maskstore is supported in loop vectorizer.
+(define_expand "len_load_<mode>"
+ [(match_operand:V 0 "register_operand")
+ (match_operand:V 1 "memory_operand")
+ (match_operand 2 "vector_length_operand")
+ (match_operand 3 "const_0_operand")]
+ "TARGET_VECTOR"
+{
+ riscv_vector::emit_nonvlmax_op (code_for_pred_mov (<MODE>mode), operands[0],
+ operands[1], operands[2], <VM>mode);
+ DONE;
+})
+
+(define_expand "len_store_<mode>"
+ [(match_operand:V 0 "memory_operand")
+ (match_operand:V 1 "register_operand")
+ (match_operand 2 "vector_length_operand")
+ (match_operand 3 "const_0_operand")]
+ "TARGET_VECTOR"
+{
+ riscv_vector::emit_nonvlmax_op (code_for_pred_mov (<MODE>mode), operands[0],
+ operands[1], operands[2], <VM>mode);
+ DONE;
+})
+
+;; -------------------------------------------------------------------------
+;; ---- [INT] Vector binary patterns
+;; -------------------------------------------------------------------------
+
+(define_expand "<optab><mode>3"
+ [(set (match_operand:VI 0 "register_operand")
+ (any_int_binop:VI (match_operand:VI 1 "<binop_rhs1_predicate>")
+ (match_operand:VI 2 "<binop_rhs2_predicate>")))]
+ "TARGET_VECTOR"
+{
+ using namespace riscv_vector;
+
+ rtx merge = RVV_VUNDEF (<MODE>mode);
+ rtx vl = gen_reg_rtx (Pmode);
+ emit_vlmax_vsetvl (<MODE>mode, vl);
+ rtx mask_policy = get_mask_policy_no_pred ();
+ rtx tail_policy = get_tail_policy_no_pred ();
+ rtx mask = CONSTM1_RTX(<VM>mode);
+ rtx vlmax_avl_p = get_avl_type_rtx (NONVLMAX);
+
+ emit_insn (gen_pred_<optab><mode> (operands[0], mask, merge, operands[1], operands[2],
+ vl, tail_policy, mask_policy, vlmax_avl_p));
+
+ DONE;
+})
+
+
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1642822d098..5c9252c281b 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -26,8 +26,6 @@
;; - Auto-vectorization (TBD)
;; - Combine optimization (TBD)
-(include "vector-iterators.md")
-
(define_constants [
(INVALID_ATTRIBUTE 255)
(X0_REGNUM 0)
@@ -368,6 +366,8 @@
(symbol_ref "INTVAL (operands[4])")]
(const_int INVALID_ATTRIBUTE)))
+(include "vector-auto.md")
+
;; -----------------------------------------------------------------
;; ---- Miscellaneous Operations
;; -----------------------------------------------------------------
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v6 6/9] RISC-V:autovec: Add autovectorization tests for add & sub
2023-05-05 15:45 [PATCH v6 0/9] RISC-V: autovec: Add autovec support Michael Collison
` (4 preceding siblings ...)
2023-05-05 15:46 ` [PATCH v6 5/9] RISC-V:autovec: Add autovectorization patterns for binary integer & len_load/store Michael Collison
@ 2023-05-05 15:46 ` Michael Collison
2023-05-05 15:46 ` [PATCH v6 7/9] RISC-V: autovec: Verify that GET_MODE_NUNITS is a multiple of 2 Michael Collison
` (3 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Michael Collison @ 2023-05-05 15:46 UTC (permalink / raw)
To: gcc-patches
2023-03-02 Michael Collison <collison@rivosinc.com>
Vineet Gupta <vineetg@rivosinc.com>
* gcc.target/riscv/rvv/autovec: New directory
for autovectorization tests.
* gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New
test to verify code generation of vector add on rv32.
* gcc.target/riscv/rvv/autovec/loop-add.c: New
test to verify code generation of vector add on rv64.
* gcc.target/riscv/rvv/autovec/loop-sub-rv32.c: New
test to verify code generation of vector subtract on rv32.
* gcc.target/riscv/rvv/autovec/loop-sub.c: New
test to verify code generation of vector subtract on rv64.
---
.../riscv/rvv/autovec/loop-add-rv32.c | 24 +++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-add.c | 24 +++++++++++++++++++
.../riscv/rvv/autovec/loop-sub-rv32.c | 24 +++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-sub.c | 24 +++++++++++++++++++
4 files changed, 96 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
new file mode 100644
index 00000000000..bdc3b6892e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] + b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
new file mode 100644
index 00000000000..d7f992c7d27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] + b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
new file mode 100644
index 00000000000..7d0a40ec539
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] - b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
new file mode 100644
index 00000000000..c8900884f83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] - b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v6 7/9] RISC-V: autovec: Verify that GET_MODE_NUNITS is a multiple of 2.
2023-05-05 15:45 [PATCH v6 0/9] RISC-V: autovec: Add autovec support Michael Collison
` (5 preceding siblings ...)
2023-05-05 15:46 ` [PATCH v6 6/9] RISC-V:autovec: Add autovectorization tests for add & sub Michael Collison
@ 2023-05-05 15:46 ` Michael Collison
2023-05-06 18:39 ` Jeff Law
2023-05-05 15:46 ` [PATCH v6 8/9] RISC-V:autovec: Add autovectorization tests for binary integer Michael Collison
` (2 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Michael Collison @ 2023-05-05 15:46 UTC (permalink / raw)
To: gcc-patches
While working on autovectorizing for the RISCV port I encountered an issue
where can_duplicate_and_interleave_p assumes that GET_MODE_NUNITS is a
evenly divisible by two. The RISC-V target has vector modes (e.g. VNx1DImode),
where GET_MODE_NUNITS is equal to one.
Tested on RISCV and x86_64-linux-gnu. Okay?
2023-03-09 Michael Collison <collison@rivosinc.com>
* tree-vect-slp.cc (can_duplicate_and_interleave_p):
Check that GET_MODE_NUNITS is a multiple of 2.
---
gcc/tree-vect-slp.cc | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index b299e209b5b..3b7a21724ec 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -423,10 +423,13 @@ can_duplicate_and_interleave_p (vec_info *vinfo, unsigned int count,
(GET_MODE_BITSIZE (int_mode), 1);
tree vector_type
= get_vectype_for_scalar_type (vinfo, int_type, count);
+ poly_int64 half_nelts;
if (vector_type
&& VECTOR_MODE_P (TYPE_MODE (vector_type))
&& known_eq (GET_MODE_SIZE (TYPE_MODE (vector_type)),
- GET_MODE_SIZE (base_vector_mode)))
+ GET_MODE_SIZE (base_vector_mode))
+ && multiple_p (GET_MODE_NUNITS (TYPE_MODE (vector_type)),
+ 2, &half_nelts))
{
/* Try fusing consecutive sequences of COUNT / NVECTORS elements
together into elements of type INT_TYPE and using the result
@@ -434,7 +437,7 @@ can_duplicate_and_interleave_p (vec_info *vinfo, unsigned int count,
poly_uint64 nelts = GET_MODE_NUNITS (TYPE_MODE (vector_type));
vec_perm_builder sel1 (nelts, 2, 3);
vec_perm_builder sel2 (nelts, 2, 3);
- poly_int64 half_nelts = exact_div (nelts, 2);
+
for (unsigned int i = 0; i < 3; ++i)
{
sel1.quick_push (i);
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v6 7/9] RISC-V: autovec: Verify that GET_MODE_NUNITS is a multiple of 2.
2023-05-05 15:46 ` [PATCH v6 7/9] RISC-V: autovec: Verify that GET_MODE_NUNITS is a multiple of 2 Michael Collison
@ 2023-05-06 18:39 ` Jeff Law
0 siblings, 0 replies; 17+ messages in thread
From: Jeff Law @ 2023-05-06 18:39 UTC (permalink / raw)
To: Michael Collison, gcc-patches
On 5/5/23 09:46, Michael Collison wrote:
> While working on autovectorizing for the RISCV port I encountered an issue
> where can_duplicate_and_interleave_p assumes that GET_MODE_NUNITS is a
> evenly divisible by two. The RISC-V target has vector modes (e.g. VNx1DImode),
> where GET_MODE_NUNITS is equal to one.
>
> Tested on RISCV and x86_64-linux-gnu. Okay?
>
> 2023-03-09 Michael Collison <collison@rivosinc.com>
>
> * tree-vect-slp.cc (can_duplicate_and_interleave_p):
> Check that GET_MODE_NUNITS is a multiple of 2.
I've pushed this to the trunk given it was acked by Richard S and he
explicitly indicated it need not wait for all the patches in this kit.
jeff
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v6 8/9] RISC-V:autovec: Add autovectorization tests for binary integer
2023-05-05 15:45 [PATCH v6 0/9] RISC-V: autovec: Add autovec support Michael Collison
` (6 preceding siblings ...)
2023-05-05 15:46 ` [PATCH v6 7/9] RISC-V: autovec: Verify that GET_MODE_NUNITS is a multiple of 2 Michael Collison
@ 2023-05-05 15:46 ` Michael Collison
2023-05-05 15:46 ` [PATCH v6 9/9] RISC-V:autovec: This patch supports 8 bit auto-vectorization in riscv Michael Collison
2023-05-05 16:34 ` [PATCH v6 0/9] RISC-V: autovec: Add autovec support Kito Cheng
9 siblings, 0 replies; 17+ messages in thread
From: Michael Collison @ 2023-05-05 15:46 UTC (permalink / raw)
To: gcc-patches
2023-04-05 Michael Collison <collison@rivosinc.com>
* gcc.target/riscv/rvv/autovec/loop-and-rv32.c: New
test to verify code generation of vector "and" on rv32.
* gcc.target/riscv/rvv/autovec/loop-and.c: New
test to verify code generation of vector "and" on rv64.
* gcc.target/riscv/rvv/autovec/loop-div-rv32.c: New
test to verify code generation of vector divide on rv32.
* gcc.target/riscv/rvv/autovec/loop-div.c: New
test to verify code generation of vector divide on rv64.
* gcc.target/riscv/rvv/autovec/loop-max-rv32.c: New
test to verify code generation of vector maximum on rv32.
* gcc.target/riscv/rvv/autovec/loop-max.c: New
test to verify code generation of vector maximum on rv64.
* gcc.target/riscv/rvv/autovec/loop-min-rv32.c: New
test to verify code generation of vector minimum on rv32.
* gcc.target/riscv/rvv/autovec/loop-min.c: New
test to verify code generation of vector minimum on rv64.
* gcc.target/riscv/rvv/autovec/loop-mod-rv32.c: New
test to verify code generation of vector modulus on rv32.
* gcc.target/riscv/rvv/autovec/loop-mod.c: New
test to verify code generation of vector modulus on rv64.
* gcc.target/riscv/rvv/autovec/loop-mul-rv32.c: New
test to verify code generation of vector multiply on rv32.
* gcc.target/riscv/rvv/autovec/loop-mul.c: New
test to verify code generation of vector multiply on rv64.
* gcc.target/riscv/rvv/autovec/loop-or-rv32.c: New
test to verify code generation of vector "or" on rv32.
* gcc.target/riscv/rvv/autovec/loop-or.c: New
test to verify code generation of vector "or" on rv64.
* gcc.target/riscv/rvv/autovec/loop-xor-rv32.c: New
test to verify code generation of vector xor on rv32.
* gcc.target/riscv/rvv/autovec/loop-xor.c: New
test to verify code generation of vector xor on rv64.
---
.../riscv/rvv/autovec/loop-and-rv32.c | 24 ++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-and.c | 24 ++++++++++++++++++
.../riscv/rvv/autovec/loop-div-rv32.c | 25 +++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-div.c | 25 +++++++++++++++++++
.../riscv/rvv/autovec/loop-max-rv32.c | 25 +++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-max.c | 25 +++++++++++++++++++
.../riscv/rvv/autovec/loop-min-rv32.c | 25 +++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-min.c | 25 +++++++++++++++++++
.../riscv/rvv/autovec/loop-mod-rv32.c | 25 +++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-mod.c | 25 +++++++++++++++++++
.../riscv/rvv/autovec/loop-mul-rv32.c | 24 ++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-mul.c | 24 ++++++++++++++++++
.../riscv/rvv/autovec/loop-or-rv32.c | 24 ++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-or.c | 24 ++++++++++++++++++
.../riscv/rvv/autovec/loop-xor-rv32.c | 24 ++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-xor.c | 24 ++++++++++++++++++
gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 4 +++
17 files changed, 396 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
new file mode 100644
index 00000000000..eb1ac5b44fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vand_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] & b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
new file mode 100644
index 00000000000..ff0cc2a5df7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vand_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] & b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
new file mode 100644
index 00000000000..21960f265b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vdiv_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] / b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
new file mode 100644
index 00000000000..bd675b4f6f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vdiv_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] / b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
new file mode 100644
index 00000000000..751ee9ecaa3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vmax_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] >= b[i] ? a[i] : b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
new file mode 100644
index 00000000000..f4dbf3f04fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vmax_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] >= b[i] ? a[i] : b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
new file mode 100644
index 00000000000..e51cf590577
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vmin_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] <= b[i] ? a[i] : b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
new file mode 100644
index 00000000000..304f939f6f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vmin_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] <= b[i] ? a[i] : b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
new file mode 100644
index 00000000000..7c497f6e4cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vmod_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] % b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
new file mode 100644
index 00000000000..7508f4a50d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vmod_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] % b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
new file mode 100644
index 00000000000..fd6dcbf9c53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] * b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
new file mode 100644
index 00000000000..9fce40890ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] * b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
new file mode 100644
index 00000000000..305d106abd9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] | b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
new file mode 100644
index 00000000000..501017bc790
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] | b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
new file mode 100644
index 00000000000..6a9ffdb11d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vxor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] ^ b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
new file mode 100644
index 00000000000..c9d7d7f8a75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vxor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] ^ b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index 4b5509db385..60b620b0875 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -42,10 +42,14 @@ dg-init
# Main loop.
set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -mabi=$gcc_mabi -O3"
+set AUTOVECFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -O2 -fno-vect-cost-model -std=c99"
+
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \
"" $CFLAGS
gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
"" $CFLAGS
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \
+ "" $AUTOVECFLAGS
# All done.
dg-finish
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v6 9/9] RISC-V:autovec: This patch supports 8 bit auto-vectorization in riscv.
2023-05-05 15:45 [PATCH v6 0/9] RISC-V: autovec: Add autovec support Michael Collison
` (7 preceding siblings ...)
2023-05-05 15:46 ` [PATCH v6 8/9] RISC-V:autovec: Add autovectorization tests for binary integer Michael Collison
@ 2023-05-05 15:46 ` Michael Collison
2023-05-05 16:34 ` [PATCH v6 0/9] RISC-V: autovec: Add autovec support Kito Cheng
9 siblings, 0 replies; 17+ messages in thread
From: Michael Collison @ 2023-05-05 15:46 UTC (permalink / raw)
To: gcc-patches
From: Kevin Lee <kevinl@rivosinc.com>
2023-04-14 Kevin Lee <kevinl@rivosinc.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/loop-add-rv32.c: Support 8bit
type
* gcc.target/riscv/rvv/autovec/loop-add.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-and-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-and.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-div-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-div.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-max-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-max.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-min-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-min.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-mod-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-mod.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-mul-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-mul.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-or-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-or.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-sub-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-sub.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-xor-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-xor.c: Ditto
---
.../gcc.target/riscv/rvv/autovec/loop-add-rv32.c | 7 ++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c | 7 ++++---
.../gcc.target/riscv/rvv/autovec/loop-and-rv32.c | 7 ++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c | 7 ++++---
.../gcc.target/riscv/rvv/autovec/loop-div-rv32.c | 10 ++++++----
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c | 10 ++++++----
.../gcc.target/riscv/rvv/autovec/loop-max-rv32.c | 9 +++++----
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c | 9 +++++----
.../gcc.target/riscv/rvv/autovec/loop-min-rv32.c | 9 +++++----
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c | 9 +++++----
.../gcc.target/riscv/rvv/autovec/loop-mod-rv32.c | 10 ++++++----
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c | 10 ++++++----
.../gcc.target/riscv/rvv/autovec/loop-mul-rv32.c | 7 ++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c | 7 ++++---
.../gcc.target/riscv/rvv/autovec/loop-or-rv32.c | 7 ++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c | 7 ++++---
.../gcc.target/riscv/rvv/autovec/loop-sub-rv32.c | 7 ++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c | 7 ++++---
.../gcc.target/riscv/rvv/autovec/loop-xor-rv32.c | 7 ++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c | 7 ++++---
20 files changed, 92 insertions(+), 68 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
index bdc3b6892e9..d2765e67d0d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] + b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
index d7f992c7d27..c43f6d3e8cb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] + b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
index eb1ac5b44fd..703f4843c2b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] & b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
index ff0cc2a5df7..ae74e4c6cc5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] & b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
index 21960f265b7..59d379d8647 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] / b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,6 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */
+/* int8_t and int16_t not autovec currently */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
index bd675b4f6f0..aa8ca21bac9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] / b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,6 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */
+/* int8_t and int16_t not autovec currently */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
index 751ee9ecaa3..5e44b3f1a5a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] >= b[i] ? a[i] : b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,5 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
index f4dbf3f04fc..4e4cc3ea97d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] >= b[i] ? a[i] : b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,5 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
index e51cf590577..128bbed8d79 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] <= b[i] ? a[i] : b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,5 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
index 304f939f6f9..74e75dd5adc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] <= b[i] ? a[i] : b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,5 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
index 7c497f6e4cc..23bc5d04bd3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] % b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,6 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */
+/* int8_t and int16_t not autovec currently */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
index 7508f4a50d1..2b1d57a0cb2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] % b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,6 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */
+/* int8_t and int16_t not autovec currently */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
index fd6dcbf9c53..6561633536a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] * b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
index 9fce40890ef..08b207f0701 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] * b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
index 305d106abd9..58f7b06b5be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] | b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
index 501017bc790..7e6b0bed282 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] | b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
index 7d0a40ec539..48ae9411872 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] - b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
index c8900884f83..23a91e38931 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] - b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
index 6a9ffdb11d5..0a65b6261b1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] ^ b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
index c9d7d7f8a75..9bfff8e6701 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */
#include <stdint.h>
@@ -10,8 +10,9 @@
dst[i] = a[i] ^ b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 8 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v6 0/9] RISC-V: autovec: Add autovec support
2023-05-05 15:45 [PATCH v6 0/9] RISC-V: autovec: Add autovec support Michael Collison
` (8 preceding siblings ...)
2023-05-05 15:46 ` [PATCH v6 9/9] RISC-V:autovec: This patch supports 8 bit auto-vectorization in riscv Michael Collison
@ 2023-05-05 16:34 ` Kito Cheng
2023-05-05 17:12 ` Michael Collison
9 siblings, 1 reply; 17+ messages in thread
From: Kito Cheng @ 2023-05-05 16:34 UTC (permalink / raw)
To: Jeff Law, Michael Collison, Palmer Dabbelt, 钟居哲
Cc: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 6556 bytes --]
Errr, why you just mixed in JuZhe’s patch set into this patch set?
Michael Collison <collison@rivosinc.com>於 2023年5月5日 週五,23:47寫道:
> This series of patches adds foundational support for RISC-V
> auto-vectorization support. These patches are based on the current upstream
> rvv vector intrinsic support and is not a new implementation. Most of the
> implementation consists of adding the new vector cost model, the
> autovectorization patterns themselves and target hooks. This implementation
> only provides support for integer addition and subtraction as a proof of
> concept. This patch set should not be construed to be feature complete.
> Based on conversations with the community these patches are intended to lay
> the groundwork for feature completion and collaboration within the RISC-V
> community.
>
> These patches are largely based off the work of Juzhe Zhong (
> juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>) of RiVAI. More
> specifically the rvv-next branch at:
> https://github.com/riscv-collab/riscv-gcc.git <
> https://github.com/riscv-collab/riscv-gcc.git>is the foundation of this
> patch set.
>
> As discussed on this list, if these patches are approved they will be
> merged into a "auto-vectorization" branch once gcc-13 branches for release.
> There are two known issues related to crashes (assert failures) associated
> with tree vectorization; one of which I have sent a patch for and have
> received feedback.
>
> Changes in v6:
> - Incorporated upstream comments, added target hook for
> TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
>
> Changes in v5:
>
> - Incorporated upstream comments large to delete unnecessary code
>
> Changes in v4:
>
> - Added support for binary integer operations and test cases
> - Fixed bug to support 8-bit integer vectorization
> - Fixed several assert errors related to non-multiple of two vector modes
>
> Changes in v3:
>
> - Removed the cost model and cost hooks based on feedback from Richard
> Biener
> - Used RVV_VUNDEF macro to fix failing patterns
>
> Changes in v2
>
> - Updated ChangeLog entry to include RiVAI contributions
> - Fixed ChangeLog email formatting
> - Fixed gnu formatting issues in the code
>
> Kevin Lee (1):
> RISC-V:autovec: This patch supports 8 bit auto-vectorization in riscv.
>
> Michael Collison (8):
> RISC-V: Add new predicates and function prototypes
> RISC-V: autovec: Export policy functions to global scope
> RISC-V:autovec: Add auto-vectorization support functions
> RISC-V:autovec: Add target vectorization hooks
> RISC-V:autovec: Add autovectorization patterns for binary integer &
> len_load/store
> RISC-V:autovec: Add autovectorization tests for add & sub
> vect: Verify that GET_MODE_NUNITS is a multiple of 2.
> RISC-V:autovec: Add autovectorization tests for binary integer
>
> gcc/config/riscv/riscv-opts.h | 10 ++
> gcc/config/riscv/riscv-protos.h | 9 ++
> gcc/config/riscv/riscv-v.cc | 91 ++++++++++++
> gcc/config/riscv/riscv-vector-builtins.cc | 4 +-
> gcc/config/riscv/riscv-vector-builtins.h | 3 +
> gcc/config/riscv/riscv.cc | 130 ++++++++++++++++++
> gcc/config/riscv/riscv.md | 1 +
> gcc/config/riscv/vector-auto.md | 74 ++++++++++
> gcc/config/riscv/vector.md | 4 +-
> .../riscv/rvv/autovec/loop-add-rv32.c | 25 ++++
> .../gcc.target/riscv/rvv/autovec/loop-add.c | 25 ++++
> .../riscv/rvv/autovec/loop-and-rv32.c | 25 ++++
> .../gcc.target/riscv/rvv/autovec/loop-and.c | 25 ++++
> .../riscv/rvv/autovec/loop-div-rv32.c | 27 ++++
> .../gcc.target/riscv/rvv/autovec/loop-div.c | 27 ++++
> .../riscv/rvv/autovec/loop-max-rv32.c | 26 ++++
> .../gcc.target/riscv/rvv/autovec/loop-max.c | 26 ++++
> .../riscv/rvv/autovec/loop-min-rv32.c | 26 ++++
> .../gcc.target/riscv/rvv/autovec/loop-min.c | 26 ++++
> .../riscv/rvv/autovec/loop-mod-rv32.c | 27 ++++
> .../gcc.target/riscv/rvv/autovec/loop-mod.c | 27 ++++
> .../riscv/rvv/autovec/loop-mul-rv32.c | 25 ++++
> .../gcc.target/riscv/rvv/autovec/loop-mul.c | 25 ++++
> .../riscv/rvv/autovec/loop-or-rv32.c | 25 ++++
> .../gcc.target/riscv/rvv/autovec/loop-or.c | 25 ++++
> .../riscv/rvv/autovec/loop-sub-rv32.c | 25 ++++
> .../gcc.target/riscv/rvv/autovec/loop-sub.c | 25 ++++
> .../riscv/rvv/autovec/loop-xor-rv32.c | 25 ++++
> .../gcc.target/riscv/rvv/autovec/loop-xor.c | 25 ++++
> gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 4 +
> gcc/tree-vect-slp.cc | 7 +-
> 31 files changed, 843 insertions(+), 6 deletions(-)
> create mode 100644 gcc/config/riscv/vector-auto.md
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v6 0/9] RISC-V: autovec: Add autovec support
2023-05-05 16:34 ` [PATCH v6 0/9] RISC-V: autovec: Add autovec support Kito Cheng
@ 2023-05-05 17:12 ` Michael Collison
0 siblings, 0 replies; 17+ messages in thread
From: Michael Collison @ 2023-05-05 17:12 UTC (permalink / raw)
To: Kito Cheng, Jeff Law, Palmer Dabbelt, 钟居哲
Cc: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 7495 bytes --]
Because everyone was commenting that we needed vector load/store support
(including Juzhe). Juzhe specifically pointed me to his patch for the
load/store patterns in his review of my code. Would you like me to
remove the patterns?
On 5/5/23 12:34, Kito Cheng wrote:
> Errr, why you just mixed in JuZhe’s patch set into this patch set?
>
> Michael Collison <collison@rivosinc.com>於 2023年5月5日 週五,23:47寫道:
>
> This series of patches adds foundational support for RISC-V
> auto-vectorization support. These patches are based on the current
> upstream rvv vector intrinsic support and is not a new
> implementation. Most of the implementation consists of adding the
> new vector cost model, the autovectorization patterns themselves
> and target hooks. This implementation only provides support for
> integer addition and subtraction as a proof of concept. This patch
> set should not be construed to be feature complete. Based on
> conversations with the community these patches are intended to lay
> the groundwork for feature completion and collaboration within the
> RISC-V community.
>
> These patches are largely based off the work of Juzhe Zhong
> (juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>) of RiVAI. More
> specifically the rvv-next branch at:
> https://github.com/riscv-collab/riscv-gcc.git
> <https://github.com/riscv-collab/riscv-gcc.git>is the foundation
> of this patch set.
>
> As discussed on this list, if these patches are approved they will
> be merged into a "auto-vectorization" branch once gcc-13 branches
> for release. There are two known issues related to crashes (assert
> failures) associated with tree vectorization; one of which I have
> sent a patch for and have received feedback.
>
> Changes in v6:
> - Incorporated upstream comments, added target hook for
> TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
>
> Changes in v5:
>
> - Incorporated upstream comments large to delete unnecessary code
>
> Changes in v4:
>
> - Added support for binary integer operations and test cases
> - Fixed bug to support 8-bit integer vectorization
> - Fixed several assert errors related to non-multiple of two
> vector modes
>
> Changes in v3:
>
> - Removed the cost model and cost hooks based on feedback from
> Richard Biener
> - Used RVV_VUNDEF macro to fix failing patterns
>
> Changes in v2
>
> - Updated ChangeLog entry to include RiVAI contributions
> - Fixed ChangeLog email formatting
> - Fixed gnu formatting issues in the code
>
> Kevin Lee (1):
> RISC-V:autovec: This patch supports 8 bit auto-vectorization in
> riscv.
>
> Michael Collison (8):
> RISC-V: Add new predicates and function prototypes
> RISC-V: autovec: Export policy functions to global scope
> RISC-V:autovec: Add auto-vectorization support functions
> RISC-V:autovec: Add target vectorization hooks
> RISC-V:autovec: Add autovectorization patterns for binary integer &
> len_load/store
> RISC-V:autovec: Add autovectorization tests for add & sub
> vect: Verify that GET_MODE_NUNITS is a multiple of 2.
> RISC-V:autovec: Add autovectorization tests for binary integer
>
> gcc/config/riscv/riscv-opts.h | 10 ++
> gcc/config/riscv/riscv-protos.h | 9 ++
> gcc/config/riscv/riscv-v.cc | 91 ++++++++++++
> gcc/config/riscv/riscv-vector-builtins.cc | 4 +-
> gcc/config/riscv/riscv-vector-builtins.h | 3 +
> gcc/config/riscv/riscv.cc | 130
> ++++++++++++++++++
> gcc/config/riscv/riscv.md | 1 +
> gcc/config/riscv/vector-auto.md | 74 ++++++++++
> gcc/config/riscv/vector.md | 4 +-
> .../riscv/rvv/autovec/loop-add-rv32.c | 25 ++++
> .../gcc.target/riscv/rvv/autovec/loop-add.c | 25 ++++
> .../riscv/rvv/autovec/loop-and-rv32.c | 25 ++++
> .../gcc.target/riscv/rvv/autovec/loop-and.c | 25 ++++
> .../riscv/rvv/autovec/loop-div-rv32.c | 27 ++++
> .../gcc.target/riscv/rvv/autovec/loop-div.c | 27 ++++
> .../riscv/rvv/autovec/loop-max-rv32.c | 26 ++++
> .../gcc.target/riscv/rvv/autovec/loop-max.c | 26 ++++
> .../riscv/rvv/autovec/loop-min-rv32.c | 26 ++++
> .../gcc.target/riscv/rvv/autovec/loop-min.c | 26 ++++
> .../riscv/rvv/autovec/loop-mod-rv32.c | 27 ++++
> .../gcc.target/riscv/rvv/autovec/loop-mod.c | 27 ++++
> .../riscv/rvv/autovec/loop-mul-rv32.c | 25 ++++
> .../gcc.target/riscv/rvv/autovec/loop-mul.c | 25 ++++
> .../riscv/rvv/autovec/loop-or-rv32.c | 25 ++++
> .../gcc.target/riscv/rvv/autovec/loop-or.c | 25 ++++
> .../riscv/rvv/autovec/loop-sub-rv32.c | 25 ++++
> .../gcc.target/riscv/rvv/autovec/loop-sub.c | 25 ++++
> .../riscv/rvv/autovec/loop-xor-rv32.c | 25 ++++
> .../gcc.target/riscv/rvv/autovec/loop-xor.c | 25 ++++
> gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 4 +
> gcc/tree-vect-slp.cc | 7 +-
> 31 files changed, 843 insertions(+), 6 deletions(-)
> create mode 100644 gcc/config/riscv/vector-auto.md
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
>
> --
> 2.34.1
>
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