From: Richard Sandiford <richard.sandiford@arm.com>
To: binutils@sourceware.org
Cc: Richard Sandiford <richard.sandiford@arm.com>
Subject: [PATCH 13/43] aarch64: Rename za_tile_vector to za_index
Date: Thu, 30 Mar 2023 11:23:29 +0100 [thread overview]
Message-ID: <20230330102359.3327695-14-richard.sandiford@arm.com> (raw)
In-Reply-To: <20230330102359.3327695-1-richard.sandiford@arm.com>
za_tile_vector is also used for indexing ZA as a whole, rather than
just for indexing tiles. The former is more common than the latter
in SME2, so this patch generalises the name to "indexed_za".
The patch also names the associated structure, so that later patches
can reuse it during parsing.
---
gas/config/tc-aarch64.c | 18 +++++++++---------
include/opcode/aarch64.h | 23 +++++++++++++----------
opcodes/aarch64-asm.c | 18 +++++++++---------
opcodes/aarch64-dis.c | 34 +++++++++++++++++-----------------
opcodes/aarch64-opc.c | 20 ++++++++++----------
5 files changed, 58 insertions(+), 55 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 26588cb4596..b06a9379f2e 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -7185,9 +7185,9 @@ parse_operands (char *str, const aarch64_opcode *opcode)
if (val == PARSE_FAIL)
goto failure;
- info->za_tile_vector.regno = val;
- info->za_tile_vector.index.regno = index_base_reg;
- info->za_tile_vector.index.imm = imm;
+ info->indexed_za.regno = val;
+ info->indexed_za.index.regno = index_base_reg;
+ info->indexed_za.index.imm = imm;
info->qualifier = qualifier;
break;
}
@@ -7535,10 +7535,10 @@ parse_operands (char *str, const aarch64_opcode *opcode)
&qualifier);
if (val == PARSE_FAIL)
goto failure;
- info->za_tile_vector.regno = val;
- info->za_tile_vector.index.regno = vector_select_register;
- info->za_tile_vector.index.imm = imm;
- info->za_tile_vector.v = slice_indicator;
+ info->indexed_za.regno = val;
+ info->indexed_za.index.regno = vector_select_register;
+ info->indexed_za.index.imm = imm;
+ info->indexed_za.v = slice_indicator;
info->qualifier = qualifier;
break;
}
@@ -7556,8 +7556,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
val = parse_sme_za_array (&str, &imm);
if (val == PARSE_FAIL)
goto failure;
- info->za_tile_vector.index.regno = val;
- info->za_tile_vector.index.imm = imm;
+ info->indexed_za.index.regno = val;
+ info->indexed_za.index.imm = imm;
break;
}
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 691247aa934..4a554df2b36 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1108,6 +1108,18 @@ extern const aarch64_cond aarch64_conds[16];
const aarch64_cond* get_cond_from_value (aarch64_insn value);
const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
\f
+/* Information about a reference to part of ZA. */
+struct aarch64_indexed_za
+{
+ int regno; /* <ZAn> */
+ struct
+ {
+ int regno; /* <Wv> */
+ int imm; /* <imm> */
+ } index;
+ unsigned v : 1; /* <HV> horizontal or vertical vector indicator. */
+};
+
/* Structure representing an operand. */
struct aarch64_opnd_info
@@ -1172,16 +1184,7 @@ struct aarch64_opnd_info
} sysreg;
/* ZA tile vector, e.g. <ZAn><HV>.D[<Wv>{, <imm>}] */
- struct
- {
- int regno; /* <ZAn> */
- struct
- {
- int regno; /* <Wv> */
- int imm; /* <imm> */
- } index;
- unsigned v : 1; /* <HV> horizontal or vertical vector indicator. */
- } za_tile_vector;
+ struct aarch64_indexed_za indexed_za;
const aarch64_cond *cond;
/* The encoding of the PSTATE field. */
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index bfabcb9e3a2..73ee15a0257 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1340,10 +1340,10 @@ aarch64_ins_sme_za_hv_tiles (const aarch64_operand *self,
{
int fld_size;
int fld_q;
- int fld_v = info->za_tile_vector.v;
- int fld_rv = info->za_tile_vector.index.regno - 12;
- int fld_zan_imm = info->za_tile_vector.index.imm;
- int regno = info->za_tile_vector.regno;
+ int fld_v = info->indexed_za.v;
+ int fld_rv = info->indexed_za.index.regno - 12;
+ int fld_zan_imm = info->indexed_za.index.imm;
+ int regno = info->indexed_za.regno;
switch (info->qualifier)
{
@@ -1410,8 +1410,8 @@ aarch64_ins_sme_za_array (const aarch64_operand *self,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
- int regno = info->za_tile_vector.index.regno - 12;
- int imm = info->za_tile_vector.index.imm;
+ int regno = info->indexed_za.index.regno - 12;
+ int imm = info->indexed_za.index.imm;
insert_field (self->fields[0], code, regno, 0);
insert_field (self->fields[1], code, imm, 0);
return true;
@@ -1464,9 +1464,9 @@ aarch64_ins_sme_pred_reg_with_index (const aarch64_operand *self,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
- int fld_pn = info->za_tile_vector.regno;
- int fld_rm = info->za_tile_vector.index.regno - 12;
- int imm = info->za_tile_vector.index.imm;
+ int fld_pn = info->indexed_za.regno;
+ int fld_rm = info->indexed_za.index.regno - 12;
+ int imm = info->indexed_za.index.imm;
int fld_i1, fld_tszh, fld_tshl;
insert_field (self->fields[0], code, fld_rm, 0);
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 01881ea377d..eabcc9ee586 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1786,34 +1786,34 @@ aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self,
/* Deduce qualifier encoded in size and Q fields. */
if (fld_size == 0)
{
- info->za_tile_vector.regno = 0;
- info->za_tile_vector.index.imm = fld_zan_imm;
+ info->indexed_za.regno = 0;
+ info->indexed_za.index.imm = fld_zan_imm;
}
else if (fld_size == 1)
{
- info->za_tile_vector.regno = fld_zan_imm >> 3;
- info->za_tile_vector.index.imm = fld_zan_imm & 0x07;
+ info->indexed_za.regno = fld_zan_imm >> 3;
+ info->indexed_za.index.imm = fld_zan_imm & 0x07;
}
else if (fld_size == 2)
{
- info->za_tile_vector.regno = fld_zan_imm >> 2;
- info->za_tile_vector.index.imm = fld_zan_imm & 0x03;
+ info->indexed_za.regno = fld_zan_imm >> 2;
+ info->indexed_za.index.imm = fld_zan_imm & 0x03;
}
else if (fld_size == 3 && fld_q == 0)
{
- info->za_tile_vector.regno = fld_zan_imm >> 1;
- info->za_tile_vector.index.imm = fld_zan_imm & 0x01;
+ info->indexed_za.regno = fld_zan_imm >> 1;
+ info->indexed_za.index.imm = fld_zan_imm & 0x01;
}
else if (fld_size == 3 && fld_q == 1)
{
- info->za_tile_vector.regno = fld_zan_imm;
- info->za_tile_vector.index.imm = 0;
+ info->indexed_za.regno = fld_zan_imm;
+ info->indexed_za.index.imm = 0;
}
else
return false;
- info->za_tile_vector.index.regno = fld_rv + 12;
- info->za_tile_vector.v = fld_v;
+ info->indexed_za.index.regno = fld_rv + 12;
+ info->indexed_za.v = fld_v;
return true;
}
@@ -1847,8 +1847,8 @@ aarch64_ext_sme_za_array (const aarch64_operand *self,
{
int regno = extract_field (self->fields[0], code, 0) + 12;
int imm = extract_field (self->fields[1], code, 0);
- info->za_tile_vector.index.regno = regno;
- info->za_tile_vector.index.imm = imm;
+ info->indexed_za.index.regno = regno;
+ info->indexed_za.index.imm = imm;
return true;
}
@@ -1902,8 +1902,8 @@ aarch64_ext_sme_pred_reg_with_index (const aarch64_operand *self,
aarch64_insn fld_tszl = extract_field (self->fields[4], code, 0);
int imm;
- info->za_tile_vector.regno = fld_pn;
- info->za_tile_vector.index.regno = fld_rm + 12;
+ info->indexed_za.regno = fld_pn;
+ info->indexed_za.index.regno = fld_rm + 12;
if (fld_tszl & 0x1)
imm = (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1);
@@ -1916,7 +1916,7 @@ aarch64_ext_sme_pred_reg_with_index (const aarch64_operand *self,
else
return false;
- info->za_tile_vector.index.imm = imm;
+ info->indexed_za.index.imm = imm;
return true;
}
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index a0e6240592c..bbbac418f91 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2770,7 +2770,7 @@ aarch64_match_operands_constraint (aarch64_inst *inst,
case sme_str:
assert (inst->operands[0].type == AARCH64_OPND_SME_ZA_array);
assert (inst->operands[1].type == AARCH64_OPND_SME_ADDR_RI_U4xVL);
- if (inst->operands[0].za_tile_vector.index.imm
+ if (inst->operands[0].indexed_za.index.imm
!= inst->operands[1].addr.offset.imm)
{
if (mismatch_detail)
@@ -3556,11 +3556,11 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
snprintf (buf, size, "%s%s[%s, %s]%s",
opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "{" : "",
style_reg (styler, "za%d%c.%s",
- opnd->za_tile_vector.regno,
- opnd->za_tile_vector.v == 1 ? 'v' : 'h',
+ opnd->indexed_za.regno,
+ opnd->indexed_za.v == 1 ? 'v' : 'h',
aarch64_get_qualifier_name (opnd->qualifier)),
- style_reg (styler, "w%d", opnd->za_tile_vector.index.regno),
- style_imm (styler, "%d", opnd->za_tile_vector.index.imm),
+ style_reg (styler, "w%d", opnd->indexed_za.index.regno),
+ style_imm (styler, "%d", opnd->indexed_za.index.imm),
opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "}" : "");
break;
@@ -3571,8 +3571,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_SME_ZA_array:
snprintf (buf, size, "%s[%s, %s]",
style_reg (styler, "za"),
- style_reg (styler, "w%d", opnd->za_tile_vector.index.regno),
- style_imm (styler, "%d", opnd->za_tile_vector.index.imm));
+ style_reg (styler, "w%d", opnd->indexed_za.index.regno),
+ style_imm (styler, "%d", opnd->indexed_za.index.imm));
break;
case AARCH64_OPND_SME_SM_ZA:
@@ -3582,10 +3582,10 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_SME_PnT_Wm_imm:
snprintf (buf, size, "%s[%s, %s]",
- style_reg (styler, "p%d.%s", opnd->za_tile_vector.regno,
+ style_reg (styler, "p%d.%s", opnd->indexed_za.regno,
aarch64_get_qualifier_name (opnd->qualifier)),
- style_reg (styler, "w%d", opnd->za_tile_vector.index.regno),
- style_imm (styler, "%d", opnd->za_tile_vector.index.imm));
+ style_reg (styler, "w%d", opnd->indexed_za.index.regno),
+ style_imm (styler, "%d", opnd->indexed_za.index.imm));
break;
case AARCH64_OPND_CRn:
--
2.25.1
next prev parent reply other threads:[~2023-03-30 10:24 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
2023-03-30 10:23 ` [PATCH 01/43] aarch64: Fix PSEL opcode mask Richard Sandiford
2023-03-30 10:23 ` [PATCH 02/43] aarch64: Restrict range of PRFM opcodes Richard Sandiford
2023-03-30 10:23 ` [PATCH 03/43] aarch64: Fix SVE2 register/immediate distinction Richard Sandiford
2023-03-30 10:23 ` [PATCH 04/43] aarch64: Make SME instructions use F_STRICT Richard Sandiford
2023-03-30 10:23 ` [PATCH 05/43] aarch64: Use aarch64_operand_error more widely Richard Sandiford
2023-03-30 10:23 ` [PATCH 06/43] aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT* Richard Sandiford
2023-03-30 10:23 ` [PATCH 07/43] aarch64: Add REG_TYPE_ZATHV Richard Sandiford
2023-03-30 10:23 ` [PATCH 08/43] aarch64: Move vectype_to_qualifier further up Richard Sandiford
2023-03-30 10:23 ` [PATCH 09/43] aarch64: Rework parse_typed_reg interface Richard Sandiford
2023-03-30 10:23 ` [PATCH 10/43] aarch64: Reuse parse_typed_reg for ZA tiles Richard Sandiford
2023-03-30 10:23 ` [PATCH 11/43] aarch64: Consolidate ZA tile range checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 12/43] aarch64: Treat ZA as a register Richard Sandiford
2023-03-30 10:23 ` Richard Sandiford [this message]
2023-03-30 10:23 ` [PATCH 14/43] aarch64: Make indexed_za use 64-bit immediates Richard Sandiford
2023-03-30 10:23 ` [PATCH 15/43] aarch64: Pass aarch64_indexed_za to parsers Richard Sandiford
2023-03-30 10:23 ` [PATCH 16/43] aarch64: Move ZA range checks to aarch64-opc.c Richard Sandiford
2023-03-30 10:23 ` [PATCH 17/43] aarch64: Consolidate ZA slice parsing Richard Sandiford
2023-03-30 10:23 ` [PATCH 18/43] aarch64: Commonise index parsing Richard Sandiford
2023-03-30 10:23 ` [PATCH 19/43] aarch64: Move w12-w15 range check to libopcodes Richard Sandiford
2023-03-30 10:23 ` [PATCH 20/43] aarch64: Tweak error for missing immediate offset Richard Sandiford
2023-03-30 10:23 ` [PATCH 21/43] aarch64: Tweak errors for base & offset registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 22/43] aarch64: Tweak parsing of integer & FP registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 23/43] aarch64: Improve errors for malformed register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 24/43] aarch64: Try to avoid inappropriate default errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 25/43] aarch64: Rework reporting of failed register checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 26/43] aarch64: Update operand_mismatch_kind_names Richard Sandiford
2023-03-30 10:23 ` [PATCH 27/43] aarch64: Deprioritise AARCH64_OPDE_REG_LIST Richard Sandiford
2023-03-30 10:23 ` [PATCH 28/43] aarch64: Add an error code for out-of-range registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 29/43] aarch64: Commonise checks for index operands Richard Sandiford
2023-03-30 10:23 ` [PATCH 30/43] aarch64: Add an operand class for SVE register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 31/43] aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield Richard Sandiford
2023-03-30 10:23 ` [PATCH 32/43] aarch64: Tweak register list errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 33/43] aarch64: Try to report invalid variants against the closest match Richard Sandiford
2023-03-30 10:23 ` [PATCH 34/43] aarch64: Tweak priorities of parsing-related errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 35/43] aarch64: Rename aarch64-tbl.h OP_SME_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 36/43] aarch64: Reorder some OP_SVE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper Richard Sandiford
2023-03-30 10:23 ` [PATCH 38/43] aarch64: Rename some of GAS's REG_TYPE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 39/43] aarch64: Regularise FLD_* suffixes Richard Sandiford
2023-03-30 10:23 ` [PATCH 40/43] aarch64: Resync field names Richard Sandiford
2023-03-30 10:23 ` [PATCH 41/43] aarch64: Sort fields alphanumerically Richard Sandiford
2023-03-30 10:23 ` [PATCH 42/43] aarch64: Add support for strided register lists Richard Sandiford
2023-03-30 15:50 ` Simon Marchi
2023-03-30 16:06 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 43/43] aarch64: Prefer register ranges & support wrapping Richard Sandiford
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