From: Richard Sandiford <richard.sandiford@arm.com>
To: binutils@sourceware.org
Cc: Richard Sandiford <richard.sandiford@arm.com>
Subject: [PATCH 24/43] aarch64: Try to avoid inappropriate default errors
Date: Thu, 30 Mar 2023 11:23:40 +0100 [thread overview]
Message-ID: <20230330102359.3327695-25-richard.sandiford@arm.com> (raw)
In-Reply-To: <20230330102359.3327695-1-richard.sandiford@arm.com>
After parsing a '{' and the first register, parse_typed_reg would
report errors in subsequent registers in the same way as for the
first register. It used set_default_error, which reports errors
of the form "operand N must be X".
The problem is that if there are multiple opcode entries for the
same mnemonic, there could be several matches that lead to a
default error. There's no guarantee that the default error for
the register list is the one that will be chosen.
To take an example from the testsuite:
ext z0.b,{z31.b,z32.b},#0
gave:
operand 2 must be an SVE vector register
with the error being reported against the single-vector version
of ext, even though the operand is clearly a list.
This patch uses set_fatal_syntax_error to bump the priority of the
error once we're sure that the operand is a list of the right type.
---
gas/config/tc-aarch64.c | 21 +++++++++++++++++----
gas/testsuite/gas/aarch64/illegal-sve2.l | 2 +-
gas/testsuite/gas/aarch64/sme-4-illegal.l | 2 ++
gas/testsuite/gas/aarch64/sme-4-illegal.s | 2 ++
gas/testsuite/gas/aarch64/sve-invalid.l | 2 ++
gas/testsuite/gas/aarch64/sve-invalid.s | 2 ++
6 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 596cc0f0813..616454b584e 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -1073,10 +1073,14 @@ parse_index_expression (char **str, int64_t *imm)
FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list.
FLAGS includes PTR_FULL_REG if the function should ignore any potential
- register index. */
+ register index.
+
+ FLAGS includes PTR_GOOD_MATCH if we are sufficiently far into parsing
+ an operand that we can be confident that it is a good match. */
#define PTR_IN_REGLIST (1U << 0)
#define PTR_FULL_REG (1U << 1)
+#define PTR_GOOD_MATCH (1U << 2)
static const reg_entry *
parse_typed_reg (char **ccp, aarch64_reg_type type,
@@ -1101,6 +1105,8 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
*typeinfo = atype;
if (!isalpha && (flags & PTR_IN_REGLIST))
set_fatal_syntax_error (_("syntax error in register list"));
+ else if (flags & PTR_GOOD_MATCH)
+ set_fatal_syntax_error (NULL);
else
set_default_error ();
return NULL;
@@ -1109,7 +1115,10 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
if (! aarch64_check_reg_type (reg, type))
{
DEBUG_TRACE ("reg type check failed");
- set_default_error ();
+ if (flags & PTR_GOOD_MATCH)
+ set_fatal_syntax_error (NULL);
+ else
+ set_default_error ();
return NULL;
}
type = reg->type;
@@ -1262,6 +1271,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
int i;
bool error = false;
bool expect_index = false;
+ unsigned int ptr_flags = PTR_IN_REGLIST;
if (*str != '{')
{
@@ -1288,7 +1298,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
val_range = val;
}
const reg_entry *reg = parse_typed_reg (&str, type, &typeinfo,
- PTR_IN_REGLIST);
+ ptr_flags);
if (!reg)
{
set_first_syntax_error (_("invalid vector register in list"));
@@ -1336,6 +1346,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
nb_regs++;
}
in_range = 0;
+ ptr_flags |= PTR_GOOD_MATCH;
}
while (skip_past_comma (&str) || (in_range = 1, *str == '-'));
@@ -4530,13 +4541,14 @@ parse_sme_zero_mask(char **str)
char *q;
int mask;
aarch64_opnd_qualifier_t qualifier;
+ unsigned int ptr_flags = PTR_IN_REGLIST;
mask = 0x00;
q = *str;
do
{
const reg_entry *reg = parse_reg_with_qual (&q, REG_TYPE_ZA_ZAT,
- &qualifier, PTR_IN_REGLIST);
+ &qualifier, ptr_flags);
if (!reg)
return PARSE_FAIL;
@@ -4581,6 +4593,7 @@ parse_sme_zero_mask(char **str)
return PARSE_FAIL;
}
}
+ ptr_flags |= PTR_GOOD_MATCH;
}
while (skip_past_char (&q, ','));
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 2eab4120331..13df21b4a4e 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -255,7 +255,7 @@
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z31\.b},#0'
[^ :]+:[0-9]+: Error: immediate value out of range 0 to 255 at operand 3 -- `ext z0\.b,{z0\.b,z1\.b},#256'
[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ext z32\.b,{z0\.b,z1\.b},#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ext z0\.b,{z31\.b,z32\.b},#0'
+[^ :]+:[0-9]+: Error: operand 2 must be a list of SVE vector registers -- `ext z0\.b,{z31\.b,z32\.b},#0'
[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ext z0\.b,{z32\.b,z33\.b},#0'
[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `faddp z32\.h,p0/m,z32\.h,z0\.h'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `faddp z0\.h,p8/m,z0\.h,z0\.h'
diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.l b/gas/testsuite/gas/aarch64/sme-4-illegal.l
index 72f62667768..57d7d65c08c 100644
--- a/gas/testsuite/gas/aarch64/sme-4-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-4-illegal.l
@@ -16,6 +16,8 @@
[^:]*:[0-9]+: Error: missing ZA tile size at operand 1 -- `zero {za0}'
[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {,za0.d}'
[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za0.d,}'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0.d,z1.d}'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0.d,za32.d}'
[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za0.d,za1.d,}'
[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za,}'
[^:]*:[0-9]+: Error: unexpected character `}' in element size at operand 1 -- `zero {za.}'
diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.s b/gas/testsuite/gas/aarch64/sme-4-illegal.s
index 3d81942f724..da4aa3da266 100644
--- a/gas/testsuite/gas/aarch64/sme-4-illegal.s
+++ b/gas/testsuite/gas/aarch64/sme-4-illegal.s
@@ -19,6 +19,8 @@ zero { , , }
zero { za0 }
zero { , za0.d }
zero { za0.d , }
+zero { za0.d, z1.d }
+zero { za0.d, za32.d }
zero { za0.d , za1.d , }
zero { za, }
zero { za. }
diff --git a/gas/testsuite/gas/aarch64/sve-invalid.l b/gas/testsuite/gas/aarch64/sve-invalid.l
index 930d67328e6..b0750933612 100644
--- a/gas/testsuite/gas/aarch64/sve-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve-invalid.l
@@ -1208,3 +1208,5 @@
.*: Error: syntax error in register list at operand 1 -- `ld2b {.b},p0/z,\[x0\]'
.*: Error: syntax error in register list at operand 1 -- `ld2b {z0.b-},p0/z,\[x0\]'
.*: Error: syntax error in register list at operand 1 -- `ld2b {z0.b,},p0/z,\[x0\]'
+.*: Error: operand 1 must be a list of SVE vector registers -- `ld2b {z0\.b-z32\.b},p0/z,\[x0\]'
+.*: Error: operand 1 must be a list of SVE vector registers -- `ld2b {z0\.b-v1\.16b},p0/z,\[x0\]'
diff --git a/gas/testsuite/gas/aarch64/sve-invalid.s b/gas/testsuite/gas/aarch64/sve-invalid.s
index ece2142b072..b56a08dc15c 100644
--- a/gas/testsuite/gas/aarch64/sve-invalid.s
+++ b/gas/testsuite/gas/aarch64/sve-invalid.s
@@ -1329,3 +1329,5 @@
ld2b {.b}, p0/z, [x0]
ld2b {z0.b-}, p0/z, [x0]
ld2b {z0.b,}, p0/z, [x0]
+ ld2b {z0.b-z32.b}, p0/z, [x0]
+ ld2b {z0.b-v1.16b}, p0/z, [x0]
--
2.25.1
next prev parent reply other threads:[~2023-03-30 10:24 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
2023-03-30 10:23 ` [PATCH 01/43] aarch64: Fix PSEL opcode mask Richard Sandiford
2023-03-30 10:23 ` [PATCH 02/43] aarch64: Restrict range of PRFM opcodes Richard Sandiford
2023-03-30 10:23 ` [PATCH 03/43] aarch64: Fix SVE2 register/immediate distinction Richard Sandiford
2023-03-30 10:23 ` [PATCH 04/43] aarch64: Make SME instructions use F_STRICT Richard Sandiford
2023-03-30 10:23 ` [PATCH 05/43] aarch64: Use aarch64_operand_error more widely Richard Sandiford
2023-03-30 10:23 ` [PATCH 06/43] aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT* Richard Sandiford
2023-03-30 10:23 ` [PATCH 07/43] aarch64: Add REG_TYPE_ZATHV Richard Sandiford
2023-03-30 10:23 ` [PATCH 08/43] aarch64: Move vectype_to_qualifier further up Richard Sandiford
2023-03-30 10:23 ` [PATCH 09/43] aarch64: Rework parse_typed_reg interface Richard Sandiford
2023-03-30 10:23 ` [PATCH 10/43] aarch64: Reuse parse_typed_reg for ZA tiles Richard Sandiford
2023-03-30 10:23 ` [PATCH 11/43] aarch64: Consolidate ZA tile range checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 12/43] aarch64: Treat ZA as a register Richard Sandiford
2023-03-30 10:23 ` [PATCH 13/43] aarch64: Rename za_tile_vector to za_index Richard Sandiford
2023-03-30 10:23 ` [PATCH 14/43] aarch64: Make indexed_za use 64-bit immediates Richard Sandiford
2023-03-30 10:23 ` [PATCH 15/43] aarch64: Pass aarch64_indexed_za to parsers Richard Sandiford
2023-03-30 10:23 ` [PATCH 16/43] aarch64: Move ZA range checks to aarch64-opc.c Richard Sandiford
2023-03-30 10:23 ` [PATCH 17/43] aarch64: Consolidate ZA slice parsing Richard Sandiford
2023-03-30 10:23 ` [PATCH 18/43] aarch64: Commonise index parsing Richard Sandiford
2023-03-30 10:23 ` [PATCH 19/43] aarch64: Move w12-w15 range check to libopcodes Richard Sandiford
2023-03-30 10:23 ` [PATCH 20/43] aarch64: Tweak error for missing immediate offset Richard Sandiford
2023-03-30 10:23 ` [PATCH 21/43] aarch64: Tweak errors for base & offset registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 22/43] aarch64: Tweak parsing of integer & FP registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 23/43] aarch64: Improve errors for malformed register lists Richard Sandiford
2023-03-30 10:23 ` Richard Sandiford [this message]
2023-03-30 10:23 ` [PATCH 25/43] aarch64: Rework reporting of failed register checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 26/43] aarch64: Update operand_mismatch_kind_names Richard Sandiford
2023-03-30 10:23 ` [PATCH 27/43] aarch64: Deprioritise AARCH64_OPDE_REG_LIST Richard Sandiford
2023-03-30 10:23 ` [PATCH 28/43] aarch64: Add an error code for out-of-range registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 29/43] aarch64: Commonise checks for index operands Richard Sandiford
2023-03-30 10:23 ` [PATCH 30/43] aarch64: Add an operand class for SVE register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 31/43] aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield Richard Sandiford
2023-03-30 10:23 ` [PATCH 32/43] aarch64: Tweak register list errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 33/43] aarch64: Try to report invalid variants against the closest match Richard Sandiford
2023-03-30 10:23 ` [PATCH 34/43] aarch64: Tweak priorities of parsing-related errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 35/43] aarch64: Rename aarch64-tbl.h OP_SME_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 36/43] aarch64: Reorder some OP_SVE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper Richard Sandiford
2023-03-30 10:23 ` [PATCH 38/43] aarch64: Rename some of GAS's REG_TYPE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 39/43] aarch64: Regularise FLD_* suffixes Richard Sandiford
2023-03-30 10:23 ` [PATCH 40/43] aarch64: Resync field names Richard Sandiford
2023-03-30 10:23 ` [PATCH 41/43] aarch64: Sort fields alphanumerically Richard Sandiford
2023-03-30 10:23 ` [PATCH 42/43] aarch64: Add support for strided register lists Richard Sandiford
2023-03-30 15:50 ` Simon Marchi
2023-03-30 16:06 ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 43/43] aarch64: Prefer register ranges & support wrapping Richard Sandiford
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